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radeonsi: bump MAX_GS_INVOCATIONS
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
45 * size as integer.
46 */
47 void *si_get_ir_binary(struct si_shader_selector *sel)
48 {
49 struct blob blob;
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->tokens) {
54 ir_binary = sel->tokens;
55 ir_size = tgsi_num_tokens(sel->tokens) *
56 sizeof(struct tgsi_token);
57 } else {
58 assert(sel->nir);
59
60 blob_init(&blob);
61 nir_serialize(&blob, sel->nir);
62 ir_binary = blob.data;
63 ir_size = blob.size;
64 }
65
66 unsigned size = 4 + ir_size + sizeof(sel->so);
67 char *result = (char*)MALLOC(size);
68 if (!result)
69 return NULL;
70
71 *((uint32_t*)result) = size;
72 memcpy(result + 4, ir_binary, ir_size);
73 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
74
75 if (sel->nir)
76 blob_finish(&blob);
77
78 return result;
79 }
80
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
83 {
84 /* data may be NULL if size == 0 */
85 if (size)
86 memcpy(ptr, data, size);
87 ptr += DIV_ROUND_UP(size, 4);
88 return ptr;
89 }
90
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
93 {
94 memcpy(data, ptr, size);
95 ptr += DIV_ROUND_UP(size, 4);
96 return ptr;
97 }
98
99 /**
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
102 */
103 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
104 {
105 *ptr++ = size;
106 return write_data(ptr, data, size);
107 }
108
109 /**
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
112 */
113 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
114 {
115 *size = *ptr++;
116 assert(*data == NULL);
117 if (!*size)
118 return ptr;
119 *data = malloc(*size);
120 return read_data(ptr, *data, *size);
121 }
122
123 /**
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
125 * as integer.
126 */
127 static void *si_get_shader_binary(struct si_shader *shader)
128 {
129 /* There is always a size of data followed by the data itself. */
130 unsigned relocs_size = shader->binary.reloc_count *
131 sizeof(shader->binary.relocs[0]);
132 unsigned disasm_size = shader->binary.disasm_string ?
133 strlen(shader->binary.disasm_string) + 1 : 0;
134 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
135 strlen(shader->binary.llvm_ir_string) + 1 : 0;
136 unsigned size =
137 4 + /* total size */
138 4 + /* CRC32 of the data below */
139 align(sizeof(shader->config), 4) +
140 align(sizeof(shader->info), 4) +
141 4 + align(shader->binary.code_size, 4) +
142 4 + align(shader->binary.rodata_size, 4) +
143 4 + align(relocs_size, 4) +
144 4 + align(disasm_size, 4) +
145 4 + align(llvm_ir_size, 4);
146 void *buffer = CALLOC(1, size);
147 uint32_t *ptr = (uint32_t*)buffer;
148
149 if (!buffer)
150 return NULL;
151
152 *ptr++ = size;
153 ptr++; /* CRC32 is calculated at the end. */
154
155 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
156 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
157 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
158 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
159 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
160 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
161 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
162 assert((char *)ptr - (char *)buffer == size);
163
164 /* Compute CRC32. */
165 ptr = (uint32_t*)buffer;
166 ptr++;
167 *ptr = util_hash_crc32(ptr + 1, size - 8);
168
169 return buffer;
170 }
171
172 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
173 {
174 uint32_t *ptr = (uint32_t*)binary;
175 uint32_t size = *ptr++;
176 uint32_t crc32 = *ptr++;
177 unsigned chunk_size;
178
179 if (util_hash_crc32(ptr, size - 8) != crc32) {
180 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
181 return false;
182 }
183
184 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
185 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
186 ptr = read_chunk(ptr, (void**)&shader->binary.code,
187 &shader->binary.code_size);
188 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
189 &shader->binary.rodata_size);
190 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
191 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
192 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
193 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
194
195 return true;
196 }
197
198 /**
199 * Insert a shader into the cache. It's assumed the shader is not in the cache.
200 * Use si_shader_cache_load_shader before calling this.
201 *
202 * Returns false on failure, in which case the ir_binary should be freed.
203 */
204 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
205 struct si_shader *shader,
206 bool insert_into_disk_cache)
207 {
208 void *hw_binary;
209 struct hash_entry *entry;
210 uint8_t key[CACHE_KEY_SIZE];
211
212 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
213 if (entry)
214 return false; /* already added */
215
216 hw_binary = si_get_shader_binary(shader);
217 if (!hw_binary)
218 return false;
219
220 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
221 hw_binary) == NULL) {
222 FREE(hw_binary);
223 return false;
224 }
225
226 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
227 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
228 *((uint32_t *)ir_binary), key);
229 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
230 *((uint32_t *) hw_binary), NULL);
231 }
232
233 return true;
234 }
235
236 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
237 struct si_shader *shader)
238 {
239 struct hash_entry *entry =
240 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
241 if (!entry) {
242 if (sscreen->disk_shader_cache) {
243 unsigned char sha1[CACHE_KEY_SIZE];
244 size_t tg_size = *((uint32_t *) ir_binary);
245
246 disk_cache_compute_key(sscreen->disk_shader_cache,
247 ir_binary, tg_size, sha1);
248
249 size_t binary_size;
250 uint8_t *buffer =
251 disk_cache_get(sscreen->disk_shader_cache,
252 sha1, &binary_size);
253 if (!buffer)
254 return false;
255
256 if (binary_size < sizeof(uint32_t) ||
257 *((uint32_t*)buffer) != binary_size) {
258 /* Something has gone wrong discard the item
259 * from the cache and rebuild/link from
260 * source.
261 */
262 assert(!"Invalid radeonsi shader disk cache "
263 "item!");
264
265 disk_cache_remove(sscreen->disk_shader_cache,
266 sha1);
267 free(buffer);
268
269 return false;
270 }
271
272 if (!si_load_shader_binary(shader, buffer)) {
273 free(buffer);
274 return false;
275 }
276 free(buffer);
277
278 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
279 shader, false))
280 FREE(ir_binary);
281 } else {
282 return false;
283 }
284 } else {
285 if (si_load_shader_binary(shader, entry->data))
286 FREE(ir_binary);
287 else
288 return false;
289 }
290 p_atomic_inc(&sscreen->num_shader_cache_hits);
291 return true;
292 }
293
294 static uint32_t si_shader_cache_key_hash(const void *key)
295 {
296 /* The first dword is the key size. */
297 return util_hash_crc32(key, *(uint32_t*)key);
298 }
299
300 static bool si_shader_cache_key_equals(const void *a, const void *b)
301 {
302 uint32_t *keya = (uint32_t*)a;
303 uint32_t *keyb = (uint32_t*)b;
304
305 /* The first dword is the key size. */
306 if (*keya != *keyb)
307 return false;
308
309 return memcmp(keya, keyb, *keya) == 0;
310 }
311
312 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
313 {
314 FREE((void*)entry->key);
315 FREE(entry->data);
316 }
317
318 bool si_init_shader_cache(struct si_screen *sscreen)
319 {
320 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
321 sscreen->shader_cache =
322 _mesa_hash_table_create(NULL,
323 si_shader_cache_key_hash,
324 si_shader_cache_key_equals);
325
326 return sscreen->shader_cache != NULL;
327 }
328
329 void si_destroy_shader_cache(struct si_screen *sscreen)
330 {
331 if (sscreen->shader_cache)
332 _mesa_hash_table_destroy(sscreen->shader_cache,
333 si_destroy_shader_cache_entry);
334 mtx_destroy(&sscreen->shader_cache_mutex);
335 }
336
337 /* SHADER STATES */
338
339 static void si_set_tesseval_regs(struct si_screen *sscreen,
340 struct si_shader_selector *tes,
341 struct si_pm4_state *pm4)
342 {
343 struct tgsi_shader_info *info = &tes->info;
344 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
345 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
346 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
347 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
348 unsigned type, partitioning, topology, distribution_mode;
349
350 switch (tes_prim_mode) {
351 case PIPE_PRIM_LINES:
352 type = V_028B6C_TESS_ISOLINE;
353 break;
354 case PIPE_PRIM_TRIANGLES:
355 type = V_028B6C_TESS_TRIANGLE;
356 break;
357 case PIPE_PRIM_QUADS:
358 type = V_028B6C_TESS_QUAD;
359 break;
360 default:
361 assert(0);
362 return;
363 }
364
365 switch (tes_spacing) {
366 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
367 partitioning = V_028B6C_PART_FRAC_ODD;
368 break;
369 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
370 partitioning = V_028B6C_PART_FRAC_EVEN;
371 break;
372 case PIPE_TESS_SPACING_EQUAL:
373 partitioning = V_028B6C_PART_INTEGER;
374 break;
375 default:
376 assert(0);
377 return;
378 }
379
380 if (tes_point_mode)
381 topology = V_028B6C_OUTPUT_POINT;
382 else if (tes_prim_mode == PIPE_PRIM_LINES)
383 topology = V_028B6C_OUTPUT_LINE;
384 else if (tes_vertex_order_cw)
385 /* for some reason, this must be the other way around */
386 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
387 else
388 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
389
390 if (sscreen->has_distributed_tess) {
391 if (sscreen->info.family == CHIP_FIJI ||
392 sscreen->info.family >= CHIP_POLARIS10)
393 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
394 else
395 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
396 } else
397 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
398
399 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
400 S_028B6C_TYPE(type) |
401 S_028B6C_PARTITIONING(partitioning) |
402 S_028B6C_TOPOLOGY(topology) |
403 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
404 }
405
406 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
407 * whether the "fractional odd" tessellation spacing is used.
408 *
409 * Possible VGT configurations and which state should set the register:
410 *
411 * Reg set in | VGT shader configuration | Value
412 * ------------------------------------------------------
413 * VS as VS | VS | 30
414 * VS as ES | ES -> GS -> VS | 30
415 * TES as VS | LS -> HS -> VS | 14 or 30
416 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
417 *
418 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
419 */
420 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
421 struct si_shader_selector *sel,
422 struct si_shader *shader,
423 struct si_pm4_state *pm4)
424 {
425 unsigned type = sel->type;
426
427 if (sscreen->info.family < CHIP_POLARIS10)
428 return;
429
430 /* VS as VS, or VS as ES: */
431 if ((type == PIPE_SHADER_VERTEX &&
432 (!shader ||
433 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
434 /* TES as VS, or TES as ES: */
435 type == PIPE_SHADER_TESS_EVAL) {
436 unsigned vtx_reuse_depth = 30;
437
438 if (type == PIPE_SHADER_TESS_EVAL &&
439 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
440 PIPE_TESS_SPACING_FRACTIONAL_ODD)
441 vtx_reuse_depth = 14;
442
443 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
444 vtx_reuse_depth);
445 }
446 }
447
448 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
449 {
450 if (shader->pm4)
451 si_pm4_clear_state(shader->pm4);
452 else
453 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
454
455 return shader->pm4;
456 }
457
458 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
459 {
460 /* Add the pointer to VBO descriptors. */
461 if (HAVE_32BIT_POINTERS) {
462 return num_always_on_user_sgprs + 1;
463 } else {
464 assert(num_always_on_user_sgprs % 2 == 0);
465 return num_always_on_user_sgprs + 2;
466 }
467 }
468
469 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
470 {
471 struct si_pm4_state *pm4;
472 unsigned vgpr_comp_cnt;
473 uint64_t va;
474
475 assert(sscreen->info.chip_class <= VI);
476
477 pm4 = si_get_shader_pm4_state(shader);
478 if (!pm4)
479 return;
480
481 va = shader->bo->gpu_address;
482 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
483
484 /* We need at least 2 components for LS.
485 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
486 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
487 */
488 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
489
490 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
491 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
492
493 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
494 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
495 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
496 S_00B528_DX10_CLAMP(1) |
497 S_00B528_FLOAT_MODE(shader->config.float_mode);
498 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
499 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
500 }
501
502 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
503 {
504 struct si_pm4_state *pm4;
505 uint64_t va;
506 unsigned ls_vgpr_comp_cnt = 0;
507
508 pm4 = si_get_shader_pm4_state(shader);
509 if (!pm4)
510 return;
511
512 va = shader->bo->gpu_address;
513 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
514
515 if (sscreen->info.chip_class >= GFX9) {
516 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
517 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
518
519 /* We need at least 2 components for LS.
520 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
521 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
522 */
523 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
524
525 unsigned num_user_sgprs =
526 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
527
528 shader->config.rsrc2 =
529 S_00B42C_USER_SGPR(num_user_sgprs) |
530 S_00B42C_USER_SGPR_MSB(num_user_sgprs >> 5) |
531 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
532 } else {
533 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
534 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
535
536 shader->config.rsrc2 =
537 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
538 S_00B42C_OC_LDS_EN(1) |
539 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
540 }
541
542 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
543 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
544 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
545 S_00B428_DX10_CLAMP(1) |
546 S_00B428_FLOAT_MODE(shader->config.float_mode) |
547 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
548
549 if (sscreen->info.chip_class <= VI) {
550 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
551 shader->config.rsrc2);
552 }
553 }
554
555 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
556 {
557 struct si_pm4_state *pm4;
558 unsigned num_user_sgprs;
559 unsigned vgpr_comp_cnt;
560 uint64_t va;
561 unsigned oc_lds_en;
562
563 assert(sscreen->info.chip_class <= VI);
564
565 pm4 = si_get_shader_pm4_state(shader);
566 if (!pm4)
567 return;
568
569 va = shader->bo->gpu_address;
570 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
571
572 if (shader->selector->type == PIPE_SHADER_VERTEX) {
573 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
574 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
575 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
576 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
577 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
578 num_user_sgprs = SI_TES_NUM_USER_SGPR;
579 } else
580 unreachable("invalid shader selector type");
581
582 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
583
584 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
585 shader->selector->esgs_itemsize / 4);
586 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
587 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
588 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
589 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
590 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
591 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
592 S_00B328_DX10_CLAMP(1) |
593 S_00B328_FLOAT_MODE(shader->config.float_mode));
594 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
595 S_00B32C_USER_SGPR(num_user_sgprs) |
596 S_00B32C_OC_LDS_EN(oc_lds_en) |
597 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
598
599 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
600 si_set_tesseval_regs(sscreen, shader->selector, pm4);
601
602 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
603 }
604
605 static unsigned si_conv_prim_to_gs_out(unsigned mode)
606 {
607 static const int prim_conv[] = {
608 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
609 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
610 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
611 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
612 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
613 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
614 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
615 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
616 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
617 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
618 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
619 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
620 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
621 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
622 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
623 };
624 assert(mode < ARRAY_SIZE(prim_conv));
625
626 return prim_conv[mode];
627 }
628
629 struct gfx9_gs_info {
630 unsigned es_verts_per_subgroup;
631 unsigned gs_prims_per_subgroup;
632 unsigned gs_inst_prims_in_subgroup;
633 unsigned max_prims_per_subgroup;
634 unsigned lds_size;
635 };
636
637 static void gfx9_get_gs_info(struct si_shader_selector *es,
638 struct si_shader_selector *gs,
639 struct gfx9_gs_info *out)
640 {
641 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
642 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
643 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
644 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
645
646 /* All these are in dwords: */
647 /* We can't allow using the whole LDS, because GS waves compete with
648 * other shader stages for LDS space. */
649 const unsigned max_lds_size = 8 * 1024;
650 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
651 unsigned esgs_lds_size;
652
653 /* All these are per subgroup: */
654 const unsigned max_out_prims = 32 * 1024;
655 const unsigned max_es_verts = 255;
656 const unsigned ideal_gs_prims = 64;
657 unsigned max_gs_prims, gs_prims;
658 unsigned min_es_verts, es_verts, worst_case_es_verts;
659
660 if (uses_adjacency || gs_num_invocations > 1)
661 max_gs_prims = 127 / gs_num_invocations;
662 else
663 max_gs_prims = 255;
664
665 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
666 * Make sure we don't go over the maximum value.
667 */
668 if (gs->gs_max_out_vertices > 0) {
669 max_gs_prims = MIN2(max_gs_prims,
670 max_out_prims /
671 (gs->gs_max_out_vertices * gs_num_invocations));
672 }
673 assert(max_gs_prims > 0);
674
675 /* If the primitive has adjacency, halve the number of vertices
676 * that will be reused in multiple primitives.
677 */
678 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
679
680 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
681 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
682
683 /* Compute ESGS LDS size based on the worst case number of ES vertices
684 * needed to create the target number of GS prims per subgroup.
685 */
686 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
687
688 /* If total LDS usage is too big, refactor partitions based on ratio
689 * of ESGS item sizes.
690 */
691 if (esgs_lds_size > max_lds_size) {
692 /* Our target GS Prims Per Subgroup was too large. Calculate
693 * the maximum number of GS Prims Per Subgroup that will fit
694 * into LDS, capped by the maximum that the hardware can support.
695 */
696 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
697 max_gs_prims);
698 assert(gs_prims > 0);
699 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
700 max_es_verts);
701
702 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
703 assert(esgs_lds_size <= max_lds_size);
704 }
705
706 /* Now calculate remaining ESGS information. */
707 if (esgs_lds_size)
708 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
709 else
710 es_verts = max_es_verts;
711
712 /* Vertices for adjacency primitives are not always reused, so restore
713 * it for ES_VERTS_PER_SUBGRP.
714 */
715 min_es_verts = gs->gs_input_verts_per_prim;
716
717 /* For normal primitives, the VGT only checks if they are past the ES
718 * verts per subgroup after allocating a full GS primitive and if they
719 * are, kick off a new subgroup. But if those additional ES verts are
720 * unique (e.g. not reused) we need to make sure there is enough LDS
721 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
722 */
723 es_verts -= min_es_verts - 1;
724
725 out->es_verts_per_subgroup = es_verts;
726 out->gs_prims_per_subgroup = gs_prims;
727 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
728 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
729 gs->gs_max_out_vertices;
730 out->lds_size = align(esgs_lds_size, 128) / 128;
731
732 assert(out->max_prims_per_subgroup <= max_out_prims);
733 }
734
735 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
736 {
737 struct si_shader_selector *sel = shader->selector;
738 const ubyte *num_components = sel->info.num_stream_output_components;
739 unsigned gs_num_invocations = sel->gs_num_invocations;
740 struct si_pm4_state *pm4;
741 uint64_t va;
742 unsigned max_stream = sel->max_gs_stream;
743 unsigned offset;
744
745 pm4 = si_get_shader_pm4_state(shader);
746 if (!pm4)
747 return;
748
749 offset = num_components[0] * sel->gs_max_out_vertices;
750 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
751 if (max_stream >= 1)
752 offset += num_components[1] * sel->gs_max_out_vertices;
753 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
754 if (max_stream >= 2)
755 offset += num_components[2] * sel->gs_max_out_vertices;
756 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
757 si_pm4_set_reg(pm4, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
758 si_conv_prim_to_gs_out(sel->gs_output_prim));
759 if (max_stream >= 3)
760 offset += num_components[3] * sel->gs_max_out_vertices;
761 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
762
763 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
764 assert(offset < (1 << 15));
765
766 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, sel->gs_max_out_vertices);
767
768 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
769 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
770 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
771 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
772
773 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
774 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
775 S_028B90_ENABLE(gs_num_invocations > 0));
776
777 va = shader->bo->gpu_address;
778 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
779
780 if (sscreen->info.chip_class >= GFX9) {
781 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
782 unsigned es_type = shader->key.part.gs.es->type;
783 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
784 struct gfx9_gs_info gs_info;
785
786 if (es_type == PIPE_SHADER_VERTEX)
787 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
788 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
789 else if (es_type == PIPE_SHADER_TESS_EVAL)
790 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
791 else
792 unreachable("invalid shader selector type");
793
794 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
795 * VGPR[0:4] are always loaded.
796 */
797 if (sel->info.uses_invocationid)
798 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
799 else if (sel->info.uses_primid)
800 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
801 else if (input_prim >= PIPE_PRIM_TRIANGLES)
802 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
803 else
804 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
805
806 unsigned num_user_sgprs;
807 if (es_type == PIPE_SHADER_VERTEX)
808 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
809 else
810 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
811
812 gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
813
814 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
815 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
816
817 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
818 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
819 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
820 S_00B228_DX10_CLAMP(1) |
821 S_00B228_FLOAT_MODE(shader->config.float_mode) |
822 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
823 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
824 S_00B22C_USER_SGPR(num_user_sgprs) |
825 S_00B22C_USER_SGPR_MSB(num_user_sgprs >> 5) |
826 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
827 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
828 S_00B22C_LDS_SIZE(gs_info.lds_size) |
829 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
830
831 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
832 S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) |
833 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) |
834 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup));
835 si_pm4_set_reg(pm4, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
836 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup));
837 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
838 shader->key.part.gs.es->esgs_itemsize / 4);
839
840 if (es_type == PIPE_SHADER_TESS_EVAL)
841 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
842
843 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
844 NULL, pm4);
845 } else {
846 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
847 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
848
849 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
850 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
851 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
852 S_00B228_DX10_CLAMP(1) |
853 S_00B228_FLOAT_MODE(shader->config.float_mode));
854 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
855 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
856 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
857 }
858 }
859
860 /**
861 * Compute the state for \p shader, which will run as a vertex shader on the
862 * hardware.
863 *
864 * If \p gs is non-NULL, it points to the geometry shader for which this shader
865 * is the copy shader.
866 */
867 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
868 struct si_shader_selector *gs)
869 {
870 const struct tgsi_shader_info *info = &shader->selector->info;
871 struct si_pm4_state *pm4;
872 unsigned num_user_sgprs;
873 unsigned nparams, vgpr_comp_cnt;
874 uint64_t va;
875 unsigned oc_lds_en;
876 unsigned window_space =
877 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
878 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
879
880 pm4 = si_get_shader_pm4_state(shader);
881 if (!pm4)
882 return;
883
884 /* We always write VGT_GS_MODE in the VS state, because every switch
885 * between different shader pipelines involving a different GS or no
886 * GS at all involves a switch of the VS (different GS use different
887 * copy shaders). On the other hand, when the API switches from a GS to
888 * no GS and then back to the same GS used originally, the GS state is
889 * not sent again.
890 */
891 if (!gs) {
892 unsigned mode = V_028A40_GS_OFF;
893
894 /* PrimID needs GS scenario A. */
895 if (enable_prim_id)
896 mode = V_028A40_GS_SCENARIO_A;
897
898 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, S_028A40_MODE(mode));
899 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
900 } else {
901 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
902 ac_vgt_gs_mode(gs->gs_max_out_vertices,
903 sscreen->info.chip_class));
904 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
905 }
906
907 if (sscreen->info.chip_class <= VI) {
908 /* Reuse needs to be set off if we write oViewport. */
909 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF,
910 S_028AB4_REUSE_OFF(info->writes_viewport_index));
911 }
912
913 va = shader->bo->gpu_address;
914 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
915
916 if (gs) {
917 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
918 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
919 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
920 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
921 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
922 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
923 */
924 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
925
926 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
927 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
928 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
929 } else {
930 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
931 }
932 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
933 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
934 num_user_sgprs = SI_TES_NUM_USER_SGPR;
935 } else
936 unreachable("invalid shader selector type");
937
938 /* VS is required to export at least one param. */
939 nparams = MAX2(shader->info.nr_param_exports, 1);
940 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
941 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
942
943 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
944 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
945 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
946 V_02870C_SPI_SHADER_4COMP :
947 V_02870C_SPI_SHADER_NONE) |
948 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
949 V_02870C_SPI_SHADER_4COMP :
950 V_02870C_SPI_SHADER_NONE) |
951 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
952 V_02870C_SPI_SHADER_4COMP :
953 V_02870C_SPI_SHADER_NONE));
954
955 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
956
957 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
958 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
959 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
960 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
961 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
962 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
963 S_00B128_DX10_CLAMP(1) |
964 S_00B128_FLOAT_MODE(shader->config.float_mode));
965 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
966 S_00B12C_USER_SGPR(num_user_sgprs) |
967 S_00B12C_OC_LDS_EN(oc_lds_en) |
968 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
969 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
970 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
971 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
972 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
973 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
974 if (window_space)
975 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
976 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
977 else
978 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
979 S_028818_VTX_W0_FMT(1) |
980 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
981 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
982 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
983
984 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
985 si_set_tesseval_regs(sscreen, shader->selector, pm4);
986
987 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
988 }
989
990 static unsigned si_get_ps_num_interp(struct si_shader *ps)
991 {
992 struct tgsi_shader_info *info = &ps->selector->info;
993 unsigned num_colors = !!(info->colors_read & 0x0f) +
994 !!(info->colors_read & 0xf0);
995 unsigned num_interp = ps->selector->info.num_inputs +
996 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
997
998 assert(num_interp <= 32);
999 return MIN2(num_interp, 32);
1000 }
1001
1002 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1003 {
1004 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1005 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1006
1007 /* If the i-th target format is set, all previous target formats must
1008 * be non-zero to avoid hangs.
1009 */
1010 for (i = 0; i < num_targets; i++)
1011 if (!(value & (0xf << (i * 4))))
1012 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1013
1014 return value;
1015 }
1016
1017 static void si_shader_ps(struct si_shader *shader)
1018 {
1019 struct tgsi_shader_info *info = &shader->selector->info;
1020 struct si_pm4_state *pm4;
1021 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1022 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1023 uint64_t va;
1024 unsigned input_ena = shader->config.spi_ps_input_ena;
1025
1026 /* we need to enable at least one of them, otherwise we hang the GPU */
1027 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1028 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1029 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1030 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1031 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1032 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1033 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1034 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1035 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1036 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1037 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1038 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1039 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1040 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1041
1042 /* Validate interpolation optimization flags (read as implications). */
1043 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1044 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1045 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1046 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1047 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1048 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1049 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1050 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1051 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1052 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1053 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1054 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1055 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1056 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1057 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1058 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1059 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1060 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1061
1062 /* Validate cases when the optimizations are off (read as implications). */
1063 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1064 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1065 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1066 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1067 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1068 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1069
1070 pm4 = si_get_shader_pm4_state(shader);
1071 if (!pm4)
1072 return;
1073
1074 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1075 * Possible vaules:
1076 * 0 -> Position = pixel center
1077 * 1 -> Position = pixel centroid
1078 * 2 -> Position = at sample position
1079 *
1080 * From GLSL 4.5 specification, section 7.1:
1081 * "The variable gl_FragCoord is available as an input variable from
1082 * within fragment shaders and it holds the window relative coordinates
1083 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1084 * value can be for any location within the pixel, or one of the
1085 * fragment samples. The use of centroid does not further restrict
1086 * this value to be inside the current primitive."
1087 *
1088 * Meaning that centroid has no effect and we can return anything within
1089 * the pixel. Thus, return the value at sample position, because that's
1090 * the most accurate one shaders can get.
1091 */
1092 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1093
1094 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1095 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1096 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1097
1098 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1099 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1100
1101 /* Ensure that some export memory is always allocated, for two reasons:
1102 *
1103 * 1) Correctness: The hardware ignores the EXEC mask if no export
1104 * memory is allocated, so KILL and alpha test do not work correctly
1105 * without this.
1106 * 2) Performance: Every shader needs at least a NULL export, even when
1107 * it writes no color/depth output. The NULL export instruction
1108 * stalls without this setting.
1109 *
1110 * Don't add this to CB_SHADER_MASK.
1111 */
1112 if (!spi_shader_col_format &&
1113 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1114 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1115
1116 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
1117 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
1118 shader->config.spi_ps_input_addr);
1119
1120 /* Set interpolation controls. */
1121 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1122
1123 /* Set registers. */
1124 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1125 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
1126
1127 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
1128 ac_get_spi_shader_z_format(info->writes_z,
1129 info->writes_stencil,
1130 info->writes_samplemask));
1131
1132 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
1133 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
1134
1135 va = shader->bo->gpu_address;
1136 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1137 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1138 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1139
1140 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1141 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1142 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
1143 S_00B028_DX10_CLAMP(1) |
1144 S_00B028_FLOAT_MODE(shader->config.float_mode));
1145 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1146 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1147 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1148 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1149 }
1150
1151 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1152 struct si_shader *shader)
1153 {
1154 switch (shader->selector->type) {
1155 case PIPE_SHADER_VERTEX:
1156 if (shader->key.as_ls)
1157 si_shader_ls(sscreen, shader);
1158 else if (shader->key.as_es)
1159 si_shader_es(sscreen, shader);
1160 else
1161 si_shader_vs(sscreen, shader, NULL);
1162 break;
1163 case PIPE_SHADER_TESS_CTRL:
1164 si_shader_hs(sscreen, shader);
1165 break;
1166 case PIPE_SHADER_TESS_EVAL:
1167 if (shader->key.as_es)
1168 si_shader_es(sscreen, shader);
1169 else
1170 si_shader_vs(sscreen, shader, NULL);
1171 break;
1172 case PIPE_SHADER_GEOMETRY:
1173 si_shader_gs(sscreen, shader);
1174 break;
1175 case PIPE_SHADER_FRAGMENT:
1176 si_shader_ps(shader);
1177 break;
1178 default:
1179 assert(0);
1180 }
1181 }
1182
1183 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1184 {
1185 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1186 if (sctx->queued.named.dsa)
1187 return sctx->queued.named.dsa->alpha_func;
1188
1189 return PIPE_FUNC_ALWAYS;
1190 }
1191
1192 static void si_shader_selector_key_vs(struct si_context *sctx,
1193 struct si_shader_selector *vs,
1194 struct si_shader_key *key,
1195 struct si_vs_prolog_bits *prolog_key)
1196 {
1197 if (!sctx->vertex_elements)
1198 return;
1199
1200 prolog_key->instance_divisor_is_one =
1201 sctx->vertex_elements->instance_divisor_is_one;
1202 prolog_key->instance_divisor_is_fetched =
1203 sctx->vertex_elements->instance_divisor_is_fetched;
1204
1205 /* Prefer a monolithic shader to allow scheduling divisions around
1206 * VBO loads. */
1207 if (prolog_key->instance_divisor_is_fetched)
1208 key->opt.prefer_mono = 1;
1209
1210 unsigned count = MIN2(vs->info.num_inputs,
1211 sctx->vertex_elements->count);
1212 memcpy(key->mono.vs_fix_fetch, sctx->vertex_elements->fix_fetch, count);
1213 }
1214
1215 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1216 struct si_shader_selector *vs,
1217 struct si_shader_key *key)
1218 {
1219 struct si_shader_selector *ps = sctx->ps_shader.cso;
1220
1221 key->opt.clip_disable =
1222 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1223 (vs->info.clipdist_writemask ||
1224 vs->info.writes_clipvertex) &&
1225 !vs->info.culldist_writemask;
1226
1227 /* Find out if PS is disabled. */
1228 bool ps_disabled = true;
1229 if (ps) {
1230 const struct si_state_blend *blend = sctx->queued.named.blend;
1231 bool alpha_to_coverage = blend && blend->alpha_to_coverage;
1232 bool ps_modifies_zs = ps->info.uses_kill ||
1233 ps->info.writes_z ||
1234 ps->info.writes_stencil ||
1235 ps->info.writes_samplemask ||
1236 alpha_to_coverage ||
1237 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1238 unsigned ps_colormask = si_get_total_colormask(sctx);
1239
1240 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1241 (!ps_colormask &&
1242 !ps_modifies_zs &&
1243 !ps->info.writes_memory);
1244 }
1245
1246 /* Find out which VS outputs aren't used by the PS. */
1247 uint64_t outputs_written = vs->outputs_written_before_ps;
1248 uint64_t inputs_read = 0;
1249
1250 /* Ignore outputs that are not passed from VS to PS. */
1251 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1252 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1253 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1254
1255 if (!ps_disabled) {
1256 inputs_read = ps->inputs_read;
1257 }
1258
1259 uint64_t linked = outputs_written & inputs_read;
1260
1261 key->opt.kill_outputs = ~linked & outputs_written;
1262 }
1263
1264 /* Compute the key for the hw shader variant */
1265 static inline void si_shader_selector_key(struct pipe_context *ctx,
1266 struct si_shader_selector *sel,
1267 struct si_shader_key *key)
1268 {
1269 struct si_context *sctx = (struct si_context *)ctx;
1270
1271 memset(key, 0, sizeof(*key));
1272
1273 switch (sel->type) {
1274 case PIPE_SHADER_VERTEX:
1275 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1276
1277 if (sctx->tes_shader.cso)
1278 key->as_ls = 1;
1279 else if (sctx->gs_shader.cso)
1280 key->as_es = 1;
1281 else {
1282 si_shader_selector_key_hw_vs(sctx, sel, key);
1283
1284 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1285 key->mono.u.vs_export_prim_id = 1;
1286 }
1287 break;
1288 case PIPE_SHADER_TESS_CTRL:
1289 if (sctx->chip_class >= GFX9) {
1290 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1291 key, &key->part.tcs.ls_prolog);
1292 key->part.tcs.ls = sctx->vs_shader.cso;
1293
1294 /* When the LS VGPR fix is needed, monolithic shaders
1295 * can:
1296 * - avoid initializing EXEC in both the LS prolog
1297 * and the LS main part when !vs_needs_prolog
1298 * - remove the fixup for unused input VGPRs
1299 */
1300 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1301
1302 /* The LS output / HS input layout can be communicated
1303 * directly instead of via user SGPRs for merged LS-HS.
1304 * The LS VGPR fix prefers this too.
1305 */
1306 key->opt.prefer_mono = 1;
1307 }
1308
1309 key->part.tcs.epilog.prim_mode =
1310 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1311 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1312 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1313 key->part.tcs.epilog.tes_reads_tess_factors =
1314 sctx->tes_shader.cso->info.reads_tess_factors;
1315
1316 if (sel == sctx->fixed_func_tcs_shader.cso)
1317 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1318 break;
1319 case PIPE_SHADER_TESS_EVAL:
1320 if (sctx->gs_shader.cso)
1321 key->as_es = 1;
1322 else {
1323 si_shader_selector_key_hw_vs(sctx, sel, key);
1324
1325 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1326 key->mono.u.vs_export_prim_id = 1;
1327 }
1328 break;
1329 case PIPE_SHADER_GEOMETRY:
1330 if (sctx->chip_class >= GFX9) {
1331 if (sctx->tes_shader.cso) {
1332 key->part.gs.es = sctx->tes_shader.cso;
1333 } else {
1334 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1335 key, &key->part.gs.vs_prolog);
1336 key->part.gs.es = sctx->vs_shader.cso;
1337 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1338 }
1339
1340 /* Merged ES-GS can have unbalanced wave usage.
1341 *
1342 * ES threads are per-vertex, while GS threads are
1343 * per-primitive. So without any amplification, there
1344 * are fewer GS threads than ES threads, which can result
1345 * in empty (no-op) GS waves. With too much amplification,
1346 * there are more GS threads than ES threads, which
1347 * can result in empty (no-op) ES waves.
1348 *
1349 * Non-monolithic shaders are implemented by setting EXEC
1350 * at the beginning of shader parts, and don't jump to
1351 * the end if EXEC is 0.
1352 *
1353 * Monolithic shaders use conditional blocks, so they can
1354 * jump and skip empty waves of ES or GS. So set this to
1355 * always use optimized variants, which are monolithic.
1356 */
1357 key->opt.prefer_mono = 1;
1358 }
1359 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1360 break;
1361 case PIPE_SHADER_FRAGMENT: {
1362 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1363 struct si_state_blend *blend = sctx->queued.named.blend;
1364
1365 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1366 sel->info.colors_written == 0x1)
1367 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1368
1369 if (blend) {
1370 /* Select the shader color format based on whether
1371 * blending or alpha are needed.
1372 */
1373 key->part.ps.epilog.spi_shader_col_format =
1374 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1375 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1376 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1377 sctx->framebuffer.spi_shader_col_format_blend) |
1378 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1379 sctx->framebuffer.spi_shader_col_format_alpha) |
1380 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1381 sctx->framebuffer.spi_shader_col_format);
1382 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1383
1384 /* The output for dual source blending should have
1385 * the same format as the first output.
1386 */
1387 if (blend->dual_src_blend)
1388 key->part.ps.epilog.spi_shader_col_format |=
1389 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1390 } else
1391 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1392
1393 /* If alpha-to-coverage is enabled, we have to export alpha
1394 * even if there is no color buffer.
1395 */
1396 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1397 blend && blend->alpha_to_coverage)
1398 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1399
1400 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1401 * to the range supported by the type if a channel has less
1402 * than 16 bits and the export format is 16_ABGR.
1403 */
1404 if (sctx->chip_class <= CIK && sctx->family != CHIP_HAWAII) {
1405 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1406 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1407 }
1408
1409 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1410 if (!key->part.ps.epilog.last_cbuf) {
1411 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1412 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1413 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1414 }
1415
1416 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1417 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1418
1419 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1420 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1421
1422 if (sctx->queued.named.blend) {
1423 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1424 rs->multisample_enable;
1425 }
1426
1427 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1428 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1429 (is_line && rs->line_smooth)) &&
1430 sctx->framebuffer.nr_samples <= 1;
1431 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1432
1433 if (sctx->ps_iter_samples > 1 &&
1434 sel->info.reads_samplemask) {
1435 key->part.ps.prolog.samplemask_log_ps_iter =
1436 util_logbase2(sctx->ps_iter_samples);
1437 }
1438
1439 if (rs->force_persample_interp &&
1440 rs->multisample_enable &&
1441 sctx->framebuffer.nr_samples > 1 &&
1442 sctx->ps_iter_samples > 1) {
1443 key->part.ps.prolog.force_persp_sample_interp =
1444 sel->info.uses_persp_center ||
1445 sel->info.uses_persp_centroid;
1446
1447 key->part.ps.prolog.force_linear_sample_interp =
1448 sel->info.uses_linear_center ||
1449 sel->info.uses_linear_centroid;
1450 } else if (rs->multisample_enable &&
1451 sctx->framebuffer.nr_samples > 1) {
1452 key->part.ps.prolog.bc_optimize_for_persp =
1453 sel->info.uses_persp_center &&
1454 sel->info.uses_persp_centroid;
1455 key->part.ps.prolog.bc_optimize_for_linear =
1456 sel->info.uses_linear_center &&
1457 sel->info.uses_linear_centroid;
1458 } else {
1459 /* Make sure SPI doesn't compute more than 1 pair
1460 * of (i,j), which is the optimization here. */
1461 key->part.ps.prolog.force_persp_center_interp =
1462 sel->info.uses_persp_center +
1463 sel->info.uses_persp_centroid +
1464 sel->info.uses_persp_sample > 1;
1465
1466 key->part.ps.prolog.force_linear_center_interp =
1467 sel->info.uses_linear_center +
1468 sel->info.uses_linear_centroid +
1469 sel->info.uses_linear_sample > 1;
1470
1471 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
1472 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1473 }
1474
1475 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1476
1477 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1478 if (sctx->ps_uses_fbfetch) {
1479 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
1480 struct pipe_resource *tex = cb0->texture;
1481
1482 /* 1D textures are allocated and used as 2D on GFX9. */
1483 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
1484 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
1485 (tex->target == PIPE_TEXTURE_1D ||
1486 tex->target == PIPE_TEXTURE_1D_ARRAY);
1487 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
1488 tex->target == PIPE_TEXTURE_2D_ARRAY ||
1489 tex->target == PIPE_TEXTURE_CUBE ||
1490 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
1491 tex->target == PIPE_TEXTURE_3D;
1492 }
1493 break;
1494 }
1495 default:
1496 assert(0);
1497 }
1498
1499 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
1500 memset(&key->opt, 0, sizeof(key->opt));
1501 }
1502
1503 static void si_build_shader_variant(struct si_shader *shader,
1504 int thread_index,
1505 bool low_priority)
1506 {
1507 struct si_shader_selector *sel = shader->selector;
1508 struct si_screen *sscreen = sel->screen;
1509 struct ac_llvm_compiler *compiler;
1510 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1511 int r;
1512
1513 if (thread_index >= 0) {
1514 if (low_priority) {
1515 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
1516 compiler = &sscreen->compiler_lowp[thread_index];
1517 } else {
1518 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
1519 compiler = &sscreen->compiler[thread_index];
1520 }
1521 if (!debug->async)
1522 debug = NULL;
1523 } else {
1524 assert(!low_priority);
1525 compiler = shader->compiler_ctx_state.compiler;
1526 }
1527
1528 r = si_shader_create(sscreen, compiler, shader, debug);
1529 if (unlikely(r)) {
1530 PRINT_ERR("Failed to build shader variant (type=%u) %d\n",
1531 sel->type, r);
1532 shader->compilation_failed = true;
1533 return;
1534 }
1535
1536 if (shader->compiler_ctx_state.is_debug_context) {
1537 FILE *f = open_memstream(&shader->shader_log,
1538 &shader->shader_log_size);
1539 if (f) {
1540 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1541 fclose(f);
1542 }
1543 }
1544
1545 si_shader_init_pm4_state(sscreen, shader);
1546 }
1547
1548 static void si_build_shader_variant_low_priority(void *job, int thread_index)
1549 {
1550 struct si_shader *shader = (struct si_shader *)job;
1551
1552 assert(thread_index >= 0);
1553
1554 si_build_shader_variant(shader, thread_index, true);
1555 }
1556
1557 static const struct si_shader_key zeroed;
1558
1559 static bool si_check_missing_main_part(struct si_screen *sscreen,
1560 struct si_shader_selector *sel,
1561 struct si_compiler_ctx_state *compiler_state,
1562 struct si_shader_key *key)
1563 {
1564 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1565
1566 if (!*mainp) {
1567 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1568
1569 if (!main_part)
1570 return false;
1571
1572 /* We can leave the fence as permanently signaled because the
1573 * main part becomes visible globally only after it has been
1574 * compiled. */
1575 util_queue_fence_init(&main_part->ready);
1576
1577 main_part->selector = sel;
1578 main_part->key.as_es = key->as_es;
1579 main_part->key.as_ls = key->as_ls;
1580 main_part->is_monolithic = false;
1581
1582 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
1583 main_part, &compiler_state->debug) != 0) {
1584 FREE(main_part);
1585 return false;
1586 }
1587 *mainp = main_part;
1588 }
1589 return true;
1590 }
1591
1592 /* Select the hw shader variant depending on the current state. */
1593 static int si_shader_select_with_key(struct si_screen *sscreen,
1594 struct si_shader_ctx_state *state,
1595 struct si_compiler_ctx_state *compiler_state,
1596 struct si_shader_key *key,
1597 int thread_index)
1598 {
1599 struct si_shader_selector *sel = state->cso;
1600 struct si_shader_selector *previous_stage_sel = NULL;
1601 struct si_shader *current = state->current;
1602 struct si_shader *iter, *shader = NULL;
1603
1604 again:
1605 /* Check if we don't need to change anything.
1606 * This path is also used for most shaders that don't need multiple
1607 * variants, it will cost just a computation of the key and this
1608 * test. */
1609 if (likely(current &&
1610 memcmp(&current->key, key, sizeof(*key)) == 0)) {
1611 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
1612 if (current->is_optimized) {
1613 memset(&key->opt, 0, sizeof(key->opt));
1614 goto current_not_ready;
1615 }
1616
1617 util_queue_fence_wait(&current->ready);
1618 }
1619
1620 return current->compilation_failed ? -1 : 0;
1621 }
1622 current_not_ready:
1623
1624 /* This must be done before the mutex is locked, because async GS
1625 * compilation calls this function too, and therefore must enter
1626 * the mutex first.
1627 *
1628 * Only wait if we are in a draw call. Don't wait if we are
1629 * in a compiler thread.
1630 */
1631 if (thread_index < 0)
1632 util_queue_fence_wait(&sel->ready);
1633
1634 mtx_lock(&sel->mutex);
1635
1636 /* Find the shader variant. */
1637 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1638 /* Don't check the "current" shader. We checked it above. */
1639 if (current != iter &&
1640 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1641 mtx_unlock(&sel->mutex);
1642
1643 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
1644 /* If it's an optimized shader and its compilation has
1645 * been started but isn't done, use the unoptimized
1646 * shader so as not to cause a stall due to compilation.
1647 */
1648 if (iter->is_optimized) {
1649 memset(&key->opt, 0, sizeof(key->opt));
1650 goto again;
1651 }
1652
1653 util_queue_fence_wait(&iter->ready);
1654 }
1655
1656 if (iter->compilation_failed) {
1657 return -1; /* skip the draw call */
1658 }
1659
1660 state->current = iter;
1661 return 0;
1662 }
1663 }
1664
1665 /* Build a new shader. */
1666 shader = CALLOC_STRUCT(si_shader);
1667 if (!shader) {
1668 mtx_unlock(&sel->mutex);
1669 return -ENOMEM;
1670 }
1671
1672 util_queue_fence_init(&shader->ready);
1673
1674 shader->selector = sel;
1675 shader->key = *key;
1676 shader->compiler_ctx_state = *compiler_state;
1677
1678 /* If this is a merged shader, get the first shader's selector. */
1679 if (sscreen->info.chip_class >= GFX9) {
1680 if (sel->type == PIPE_SHADER_TESS_CTRL)
1681 previous_stage_sel = key->part.tcs.ls;
1682 else if (sel->type == PIPE_SHADER_GEOMETRY)
1683 previous_stage_sel = key->part.gs.es;
1684
1685 /* We need to wait for the previous shader. */
1686 if (previous_stage_sel && thread_index < 0)
1687 util_queue_fence_wait(&previous_stage_sel->ready);
1688 }
1689
1690 /* Compile the main shader part if it doesn't exist. This can happen
1691 * if the initial guess was wrong. */
1692 bool is_pure_monolithic =
1693 sscreen->use_monolithic_shaders ||
1694 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1695
1696 if (!is_pure_monolithic) {
1697 bool ok;
1698
1699 /* Make sure the main shader part is present. This is needed
1700 * for shaders that can be compiled as VS, LS, or ES, and only
1701 * one of them is compiled at creation.
1702 *
1703 * For merged shaders, check that the starting shader's main
1704 * part is present.
1705 */
1706 if (previous_stage_sel) {
1707 struct si_shader_key shader1_key = zeroed;
1708
1709 if (sel->type == PIPE_SHADER_TESS_CTRL)
1710 shader1_key.as_ls = 1;
1711 else if (sel->type == PIPE_SHADER_GEOMETRY)
1712 shader1_key.as_es = 1;
1713 else
1714 assert(0);
1715
1716 mtx_lock(&previous_stage_sel->mutex);
1717 ok = si_check_missing_main_part(sscreen,
1718 previous_stage_sel,
1719 compiler_state, &shader1_key);
1720 mtx_unlock(&previous_stage_sel->mutex);
1721 } else {
1722 ok = si_check_missing_main_part(sscreen, sel,
1723 compiler_state, key);
1724 }
1725 if (!ok) {
1726 FREE(shader);
1727 mtx_unlock(&sel->mutex);
1728 return -ENOMEM; /* skip the draw call */
1729 }
1730 }
1731
1732 /* Keep the reference to the 1st shader of merged shaders, so that
1733 * Gallium can't destroy it before we destroy the 2nd shader.
1734 *
1735 * Set sctx = NULL, because it's unused if we're not releasing
1736 * the shader, and we don't have any sctx here.
1737 */
1738 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
1739 previous_stage_sel);
1740
1741 /* Monolithic-only shaders don't make a distinction between optimized
1742 * and unoptimized. */
1743 shader->is_monolithic =
1744 is_pure_monolithic ||
1745 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1746
1747 shader->is_optimized =
1748 !is_pure_monolithic &&
1749 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1750
1751 /* If it's an optimized shader, compile it asynchronously. */
1752 if (shader->is_optimized &&
1753 !is_pure_monolithic &&
1754 thread_index < 0) {
1755 /* Compile it asynchronously. */
1756 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
1757 shader, &shader->ready,
1758 si_build_shader_variant_low_priority, NULL);
1759
1760 /* Add only after the ready fence was reset, to guard against a
1761 * race with si_bind_XX_shader. */
1762 if (!sel->last_variant) {
1763 sel->first_variant = shader;
1764 sel->last_variant = shader;
1765 } else {
1766 sel->last_variant->next_variant = shader;
1767 sel->last_variant = shader;
1768 }
1769
1770 /* Use the default (unoptimized) shader for now. */
1771 memset(&key->opt, 0, sizeof(key->opt));
1772 mtx_unlock(&sel->mutex);
1773 goto again;
1774 }
1775
1776 /* Reset the fence before adding to the variant list. */
1777 util_queue_fence_reset(&shader->ready);
1778
1779 if (!sel->last_variant) {
1780 sel->first_variant = shader;
1781 sel->last_variant = shader;
1782 } else {
1783 sel->last_variant->next_variant = shader;
1784 sel->last_variant = shader;
1785 }
1786
1787 mtx_unlock(&sel->mutex);
1788
1789 assert(!shader->is_optimized);
1790 si_build_shader_variant(shader, thread_index, false);
1791
1792 util_queue_fence_signal(&shader->ready);
1793
1794 if (!shader->compilation_failed)
1795 state->current = shader;
1796
1797 return shader->compilation_failed ? -1 : 0;
1798 }
1799
1800 static int si_shader_select(struct pipe_context *ctx,
1801 struct si_shader_ctx_state *state,
1802 struct si_compiler_ctx_state *compiler_state)
1803 {
1804 struct si_context *sctx = (struct si_context *)ctx;
1805 struct si_shader_key key;
1806
1807 si_shader_selector_key(ctx, state->cso, &key);
1808 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1809 &key, -1);
1810 }
1811
1812 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1813 bool streamout,
1814 struct si_shader_key *key)
1815 {
1816 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1817
1818 switch (info->processor) {
1819 case PIPE_SHADER_VERTEX:
1820 switch (next_shader) {
1821 case PIPE_SHADER_GEOMETRY:
1822 key->as_es = 1;
1823 break;
1824 case PIPE_SHADER_TESS_CTRL:
1825 case PIPE_SHADER_TESS_EVAL:
1826 key->as_ls = 1;
1827 break;
1828 default:
1829 /* If POSITION isn't written, it can only be a HW VS
1830 * if streamout is used. If streamout isn't used,
1831 * assume that it's a HW LS. (the next shader is TCS)
1832 * This heuristic is needed for separate shader objects.
1833 */
1834 if (!info->writes_position && !streamout)
1835 key->as_ls = 1;
1836 }
1837 break;
1838
1839 case PIPE_SHADER_TESS_EVAL:
1840 if (next_shader == PIPE_SHADER_GEOMETRY ||
1841 !info->writes_position)
1842 key->as_es = 1;
1843 break;
1844 }
1845 }
1846
1847 /**
1848 * Compile the main shader part or the monolithic shader as part of
1849 * si_shader_selector initialization. Since it can be done asynchronously,
1850 * there is no way to report compile failures to applications.
1851 */
1852 static void si_init_shader_selector_async(void *job, int thread_index)
1853 {
1854 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1855 struct si_screen *sscreen = sel->screen;
1856 struct ac_llvm_compiler *compiler;
1857 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
1858
1859 assert(!debug->debug_message || debug->async);
1860 assert(thread_index >= 0);
1861 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
1862 compiler = &sscreen->compiler[thread_index];
1863
1864 /* Compile the main shader part for use with a prolog and/or epilog.
1865 * If this fails, the driver will try to compile a monolithic shader
1866 * on demand.
1867 */
1868 if (!sscreen->use_monolithic_shaders) {
1869 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1870 void *ir_binary = NULL;
1871
1872 if (!shader) {
1873 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1874 return;
1875 }
1876
1877 /* We can leave the fence signaled because use of the default
1878 * main part is guarded by the selector's ready fence. */
1879 util_queue_fence_init(&shader->ready);
1880
1881 shader->selector = sel;
1882 shader->is_monolithic = false;
1883 si_parse_next_shader_property(&sel->info,
1884 sel->so.num_outputs != 0,
1885 &shader->key);
1886
1887 if (sel->tokens || sel->nir)
1888 ir_binary = si_get_ir_binary(sel);
1889
1890 /* Try to load the shader from the shader cache. */
1891 mtx_lock(&sscreen->shader_cache_mutex);
1892
1893 if (ir_binary &&
1894 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
1895 mtx_unlock(&sscreen->shader_cache_mutex);
1896 si_shader_dump_stats_for_shader_db(shader, debug);
1897 } else {
1898 mtx_unlock(&sscreen->shader_cache_mutex);
1899
1900 /* Compile the shader if it hasn't been loaded from the cache. */
1901 if (si_compile_tgsi_shader(sscreen, compiler, shader,
1902 debug) != 0) {
1903 FREE(shader);
1904 FREE(ir_binary);
1905 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1906 return;
1907 }
1908
1909 if (ir_binary) {
1910 mtx_lock(&sscreen->shader_cache_mutex);
1911 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
1912 FREE(ir_binary);
1913 mtx_unlock(&sscreen->shader_cache_mutex);
1914 }
1915 }
1916
1917 *si_get_main_shader_part(sel, &shader->key) = shader;
1918
1919 /* Unset "outputs_written" flags for outputs converted to
1920 * DEFAULT_VAL, so that later inter-shader optimizations don't
1921 * try to eliminate outputs that don't exist in the final
1922 * shader.
1923 *
1924 * This is only done if non-monolithic shaders are enabled.
1925 */
1926 if ((sel->type == PIPE_SHADER_VERTEX ||
1927 sel->type == PIPE_SHADER_TESS_EVAL) &&
1928 !shader->key.as_ls &&
1929 !shader->key.as_es) {
1930 unsigned i;
1931
1932 for (i = 0; i < sel->info.num_outputs; i++) {
1933 unsigned offset = shader->info.vs_output_param_offset[i];
1934
1935 if (offset <= AC_EXP_PARAM_OFFSET_31)
1936 continue;
1937
1938 unsigned name = sel->info.output_semantic_name[i];
1939 unsigned index = sel->info.output_semantic_index[i];
1940 unsigned id;
1941
1942 switch (name) {
1943 case TGSI_SEMANTIC_GENERIC:
1944 /* don't process indices the function can't handle */
1945 if (index >= SI_MAX_IO_GENERIC)
1946 break;
1947 /* fall through */
1948 default:
1949 id = si_shader_io_get_unique_index(name, index, true);
1950 sel->outputs_written_before_ps &= ~(1ull << id);
1951 break;
1952 case TGSI_SEMANTIC_POSITION: /* ignore these */
1953 case TGSI_SEMANTIC_PSIZE:
1954 case TGSI_SEMANTIC_CLIPVERTEX:
1955 case TGSI_SEMANTIC_EDGEFLAG:
1956 break;
1957 }
1958 }
1959 }
1960 }
1961
1962 /* The GS copy shader is always pre-compiled. */
1963 if (sel->type == PIPE_SHADER_GEOMETRY) {
1964 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
1965 if (!sel->gs_copy_shader) {
1966 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
1967 return;
1968 }
1969
1970 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
1971 }
1972 }
1973
1974 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
1975 struct util_queue_fence *ready_fence,
1976 struct si_compiler_ctx_state *compiler_ctx_state,
1977 void *job, util_queue_execute_func execute)
1978 {
1979 util_queue_fence_init(ready_fence);
1980
1981 struct util_async_debug_callback async_debug;
1982 bool wait =
1983 (sctx->debug.debug_message && !sctx->debug.async) ||
1984 sctx->is_debug ||
1985 si_can_dump_shader(sctx->screen, processor);
1986
1987 if (wait) {
1988 u_async_debug_init(&async_debug);
1989 compiler_ctx_state->debug = async_debug.base;
1990 }
1991
1992 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
1993 ready_fence, execute, NULL);
1994
1995 if (wait) {
1996 util_queue_fence_wait(ready_fence);
1997 u_async_debug_drain(&async_debug, &sctx->debug);
1998 u_async_debug_cleanup(&async_debug);
1999 }
2000 }
2001
2002 /* Return descriptor slot usage masks from the given shader info. */
2003 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2004 uint32_t *const_and_shader_buffers,
2005 uint64_t *samplers_and_images)
2006 {
2007 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2008
2009 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2010 num_constbufs = util_last_bit(info->const_buffers_declared);
2011 /* two 8-byte images share one 16-byte slot */
2012 num_images = align(util_last_bit(info->images_declared), 2);
2013 num_samplers = util_last_bit(info->samplers_declared);
2014
2015 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2016 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2017 *const_and_shader_buffers =
2018 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2019
2020 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2021 start = si_get_image_slot(num_images - 1) / 2;
2022 *samplers_and_images =
2023 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2024 }
2025
2026 static void *si_create_shader_selector(struct pipe_context *ctx,
2027 const struct pipe_shader_state *state)
2028 {
2029 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2030 struct si_context *sctx = (struct si_context*)ctx;
2031 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2032 int i;
2033
2034 if (!sel)
2035 return NULL;
2036
2037 pipe_reference_init(&sel->reference, 1);
2038 sel->screen = sscreen;
2039 sel->compiler_ctx_state.debug = sctx->debug;
2040 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2041
2042 sel->so = state->stream_output;
2043
2044 if (state->type == PIPE_SHADER_IR_TGSI) {
2045 sel->tokens = tgsi_dup_tokens(state->tokens);
2046 if (!sel->tokens) {
2047 FREE(sel);
2048 return NULL;
2049 }
2050
2051 tgsi_scan_shader(state->tokens, &sel->info);
2052 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2053 } else {
2054 assert(state->type == PIPE_SHADER_IR_NIR);
2055
2056 sel->nir = state->ir.nir;
2057
2058 si_nir_scan_shader(sel->nir, &sel->info);
2059 si_nir_scan_tess_ctrl(sel->nir, &sel->info, &sel->tcs_info);
2060
2061 si_lower_nir(sel);
2062 }
2063
2064 sel->type = sel->info.processor;
2065 p_atomic_inc(&sscreen->num_shaders_created);
2066 si_get_active_slot_masks(&sel->info,
2067 &sel->active_const_and_shader_buffers,
2068 &sel->active_samplers_and_images);
2069
2070 /* Record which streamout buffers are enabled. */
2071 for (i = 0; i < sel->so.num_outputs; i++) {
2072 sel->enabled_streamout_buffer_mask |=
2073 (1 << sel->so.output[i].output_buffer) <<
2074 (sel->so.output[i].stream * 4);
2075 }
2076
2077 /* The prolog is a no-op if there are no inputs. */
2078 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2079 sel->info.num_inputs &&
2080 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2081
2082 sel->force_correct_derivs_after_kill =
2083 sel->type == PIPE_SHADER_FRAGMENT &&
2084 sel->info.uses_derivatives &&
2085 sel->info.uses_kill &&
2086 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2087
2088 /* Set which opcode uses which (i,j) pair. */
2089 if (sel->info.uses_persp_opcode_interp_centroid)
2090 sel->info.uses_persp_centroid = true;
2091
2092 if (sel->info.uses_linear_opcode_interp_centroid)
2093 sel->info.uses_linear_centroid = true;
2094
2095 if (sel->info.uses_persp_opcode_interp_offset ||
2096 sel->info.uses_persp_opcode_interp_sample)
2097 sel->info.uses_persp_center = true;
2098
2099 if (sel->info.uses_linear_opcode_interp_offset ||
2100 sel->info.uses_linear_opcode_interp_sample)
2101 sel->info.uses_linear_center = true;
2102
2103 switch (sel->type) {
2104 case PIPE_SHADER_GEOMETRY:
2105 sel->gs_output_prim =
2106 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2107 sel->gs_max_out_vertices =
2108 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2109 sel->gs_num_invocations =
2110 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2111 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2112 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2113 sel->gs_max_out_vertices;
2114
2115 sel->max_gs_stream = 0;
2116 for (i = 0; i < sel->so.num_outputs; i++)
2117 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2118 sel->so.output[i].stream);
2119
2120 sel->gs_input_verts_per_prim =
2121 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2122 break;
2123
2124 case PIPE_SHADER_TESS_CTRL:
2125 /* Always reserve space for these. */
2126 sel->patch_outputs_written |=
2127 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2128 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2129 /* fall through */
2130 case PIPE_SHADER_VERTEX:
2131 case PIPE_SHADER_TESS_EVAL:
2132 for (i = 0; i < sel->info.num_outputs; i++) {
2133 unsigned name = sel->info.output_semantic_name[i];
2134 unsigned index = sel->info.output_semantic_index[i];
2135
2136 switch (name) {
2137 case TGSI_SEMANTIC_TESSINNER:
2138 case TGSI_SEMANTIC_TESSOUTER:
2139 case TGSI_SEMANTIC_PATCH:
2140 sel->patch_outputs_written |=
2141 1ull << si_shader_io_get_unique_index_patch(name, index);
2142 break;
2143
2144 case TGSI_SEMANTIC_GENERIC:
2145 /* don't process indices the function can't handle */
2146 if (index >= SI_MAX_IO_GENERIC)
2147 break;
2148 /* fall through */
2149 default:
2150 sel->outputs_written |=
2151 1ull << si_shader_io_get_unique_index(name, index, false);
2152 sel->outputs_written_before_ps |=
2153 1ull << si_shader_io_get_unique_index(name, index, true);
2154 break;
2155 case TGSI_SEMANTIC_EDGEFLAG:
2156 break;
2157 }
2158 }
2159 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2160 sel->lshs_vertex_stride = sel->esgs_itemsize;
2161
2162 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2163 * will start on a different bank. (except for the maximum 32*16).
2164 */
2165 if (sel->lshs_vertex_stride < 32*16)
2166 sel->lshs_vertex_stride += 4;
2167
2168 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2169 * conflicts, i.e. each vertex will start at a different bank.
2170 */
2171 if (sctx->chip_class >= GFX9)
2172 sel->esgs_itemsize += 4;
2173
2174 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2175 break;
2176
2177 case PIPE_SHADER_FRAGMENT:
2178 for (i = 0; i < sel->info.num_inputs; i++) {
2179 unsigned name = sel->info.input_semantic_name[i];
2180 unsigned index = sel->info.input_semantic_index[i];
2181
2182 switch (name) {
2183 case TGSI_SEMANTIC_GENERIC:
2184 /* don't process indices the function can't handle */
2185 if (index >= SI_MAX_IO_GENERIC)
2186 break;
2187 /* fall through */
2188 default:
2189 sel->inputs_read |=
2190 1ull << si_shader_io_get_unique_index(name, index, true);
2191 break;
2192 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2193 break;
2194 }
2195 }
2196
2197 for (i = 0; i < 8; i++)
2198 if (sel->info.colors_written & (1 << i))
2199 sel->colors_written_4bit |= 0xf << (4 * i);
2200
2201 for (i = 0; i < sel->info.num_inputs; i++) {
2202 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2203 int index = sel->info.input_semantic_index[i];
2204 sel->color_attr_index[index] = i;
2205 }
2206 }
2207 break;
2208 }
2209
2210 /* PA_CL_VS_OUT_CNTL */
2211 bool misc_vec_ena =
2212 sel->info.writes_psize || sel->info.writes_edgeflag ||
2213 sel->info.writes_layer || sel->info.writes_viewport_index;
2214 sel->pa_cl_vs_out_cntl =
2215 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2216 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2217 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2218 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2219 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2220 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2221 sel->clipdist_mask = sel->info.writes_clipvertex ?
2222 SIX_BITS : sel->info.clipdist_writemask;
2223 sel->culldist_mask = sel->info.culldist_writemask <<
2224 sel->info.num_written_clipdistance;
2225
2226 /* DB_SHADER_CONTROL */
2227 sel->db_shader_control =
2228 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2229 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2230 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2231 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2232
2233 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2234 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2235 sel->db_shader_control |=
2236 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2237 break;
2238 case TGSI_FS_DEPTH_LAYOUT_LESS:
2239 sel->db_shader_control |=
2240 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2241 break;
2242 }
2243
2244 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2245 *
2246 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2247 * --|-----------|------------|------------|--------------------|-------------------|-------------
2248 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2249 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2250 * 2 | false | true | n/a | LateZ | 1 | 0
2251 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2252 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2253 *
2254 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2255 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2256 *
2257 * Don't use ReZ without profiling !!!
2258 *
2259 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2260 * shaders.
2261 */
2262 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2263 /* Cases 3, 4. */
2264 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2265 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2266 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2267 } else if (sel->info.writes_memory) {
2268 /* Case 2. */
2269 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2270 S_02880C_EXEC_ON_HIER_FAIL(1);
2271 } else {
2272 /* Case 1. */
2273 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2274 }
2275
2276 (void) mtx_init(&sel->mutex, mtx_plain);
2277
2278 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2279 &sel->compiler_ctx_state, sel,
2280 si_init_shader_selector_async);
2281 return sel;
2282 }
2283
2284 static void si_update_streamout_state(struct si_context *sctx)
2285 {
2286 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2287
2288 if (!shader_with_so)
2289 return;
2290
2291 sctx->streamout.enabled_stream_buffers_mask =
2292 shader_with_so->enabled_streamout_buffer_mask;
2293 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2294 }
2295
2296 static void si_update_clip_regs(struct si_context *sctx,
2297 struct si_shader_selector *old_hw_vs,
2298 struct si_shader *old_hw_vs_variant,
2299 struct si_shader_selector *next_hw_vs,
2300 struct si_shader *next_hw_vs_variant)
2301 {
2302 if (next_hw_vs &&
2303 (!old_hw_vs ||
2304 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2305 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2306 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2307 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2308 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2309 !old_hw_vs_variant ||
2310 !next_hw_vs_variant ||
2311 old_hw_vs_variant->key.opt.clip_disable !=
2312 next_hw_vs_variant->key.opt.clip_disable))
2313 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2314 }
2315
2316 static void si_update_common_shader_state(struct si_context *sctx)
2317 {
2318 sctx->uses_bindless_samplers =
2319 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2320 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2321 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2322 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2323 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2324 sctx->uses_bindless_images =
2325 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2326 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2327 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2328 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2329 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2330 sctx->do_update_shaders = true;
2331 }
2332
2333 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2334 {
2335 struct si_context *sctx = (struct si_context *)ctx;
2336 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2337 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2338 struct si_shader_selector *sel = state;
2339
2340 if (sctx->vs_shader.cso == sel)
2341 return;
2342
2343 sctx->vs_shader.cso = sel;
2344 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2345 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2346
2347 si_update_common_shader_state(sctx);
2348 si_update_vs_viewport_state(sctx);
2349 si_set_active_descriptors_for_shader(sctx, sel);
2350 si_update_streamout_state(sctx);
2351 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2352 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2353 }
2354
2355 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2356 {
2357 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2358 (sctx->tes_shader.cso &&
2359 sctx->tes_shader.cso->info.uses_primid) ||
2360 (sctx->tcs_shader.cso &&
2361 sctx->tcs_shader.cso->info.uses_primid) ||
2362 (sctx->gs_shader.cso &&
2363 sctx->gs_shader.cso->info.uses_primid) ||
2364 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2365 sctx->ps_shader.cso->info.uses_primid);
2366 }
2367
2368 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2369 {
2370 struct si_context *sctx = (struct si_context *)ctx;
2371 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2372 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2373 struct si_shader_selector *sel = state;
2374 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2375
2376 if (sctx->gs_shader.cso == sel)
2377 return;
2378
2379 sctx->gs_shader.cso = sel;
2380 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2381 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2382
2383 si_update_common_shader_state(sctx);
2384 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2385
2386 if (enable_changed) {
2387 si_shader_change_notify(sctx);
2388 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2389 si_update_tess_uses_prim_id(sctx);
2390 }
2391 si_update_vs_viewport_state(sctx);
2392 si_set_active_descriptors_for_shader(sctx, sel);
2393 si_update_streamout_state(sctx);
2394 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2395 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2396 }
2397
2398 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2399 {
2400 struct si_context *sctx = (struct si_context *)ctx;
2401 struct si_shader_selector *sel = state;
2402 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2403
2404 if (sctx->tcs_shader.cso == sel)
2405 return;
2406
2407 sctx->tcs_shader.cso = sel;
2408 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2409 si_update_tess_uses_prim_id(sctx);
2410
2411 si_update_common_shader_state(sctx);
2412
2413 if (enable_changed)
2414 sctx->last_tcs = NULL; /* invalidate derived tess state */
2415
2416 si_set_active_descriptors_for_shader(sctx, sel);
2417 }
2418
2419 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2420 {
2421 struct si_context *sctx = (struct si_context *)ctx;
2422 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2423 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2424 struct si_shader_selector *sel = state;
2425 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2426
2427 if (sctx->tes_shader.cso == sel)
2428 return;
2429
2430 sctx->tes_shader.cso = sel;
2431 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2432 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2433 si_update_tess_uses_prim_id(sctx);
2434
2435 si_update_common_shader_state(sctx);
2436 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2437
2438 if (enable_changed) {
2439 si_shader_change_notify(sctx);
2440 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2441 }
2442 si_update_vs_viewport_state(sctx);
2443 si_set_active_descriptors_for_shader(sctx, sel);
2444 si_update_streamout_state(sctx);
2445 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2446 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2447 }
2448
2449 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2450 {
2451 struct si_context *sctx = (struct si_context *)ctx;
2452 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
2453 struct si_shader_selector *sel = state;
2454
2455 /* skip if supplied shader is one already in use */
2456 if (old_sel == sel)
2457 return;
2458
2459 sctx->ps_shader.cso = sel;
2460 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2461
2462 si_update_common_shader_state(sctx);
2463 if (sel) {
2464 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2465 si_update_tess_uses_prim_id(sctx);
2466
2467 if (!old_sel ||
2468 old_sel->info.colors_written != sel->info.colors_written)
2469 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2470
2471 if (sctx->screen->has_out_of_order_rast &&
2472 (!old_sel ||
2473 old_sel->info.writes_memory != sel->info.writes_memory ||
2474 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
2475 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
2476 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2477 }
2478 si_set_active_descriptors_for_shader(sctx, sel);
2479 si_update_ps_colorbuf0_slot(sctx);
2480 }
2481
2482 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2483 {
2484 if (shader->is_optimized) {
2485 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
2486 &shader->ready);
2487 }
2488
2489 util_queue_fence_destroy(&shader->ready);
2490
2491 if (shader->pm4) {
2492 switch (shader->selector->type) {
2493 case PIPE_SHADER_VERTEX:
2494 if (shader->key.as_ls) {
2495 assert(sctx->chip_class <= VI);
2496 si_pm4_delete_state(sctx, ls, shader->pm4);
2497 } else if (shader->key.as_es) {
2498 assert(sctx->chip_class <= VI);
2499 si_pm4_delete_state(sctx, es, shader->pm4);
2500 } else {
2501 si_pm4_delete_state(sctx, vs, shader->pm4);
2502 }
2503 break;
2504 case PIPE_SHADER_TESS_CTRL:
2505 si_pm4_delete_state(sctx, hs, shader->pm4);
2506 break;
2507 case PIPE_SHADER_TESS_EVAL:
2508 if (shader->key.as_es) {
2509 assert(sctx->chip_class <= VI);
2510 si_pm4_delete_state(sctx, es, shader->pm4);
2511 } else {
2512 si_pm4_delete_state(sctx, vs, shader->pm4);
2513 }
2514 break;
2515 case PIPE_SHADER_GEOMETRY:
2516 if (shader->is_gs_copy_shader)
2517 si_pm4_delete_state(sctx, vs, shader->pm4);
2518 else
2519 si_pm4_delete_state(sctx, gs, shader->pm4);
2520 break;
2521 case PIPE_SHADER_FRAGMENT:
2522 si_pm4_delete_state(sctx, ps, shader->pm4);
2523 break;
2524 }
2525 }
2526
2527 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2528 si_shader_destroy(shader);
2529 free(shader);
2530 }
2531
2532 void si_destroy_shader_selector(struct si_context *sctx,
2533 struct si_shader_selector *sel)
2534 {
2535 struct si_shader *p = sel->first_variant, *c;
2536 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2537 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2538 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2539 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2540 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2541 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2542 };
2543
2544 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
2545
2546 if (current_shader[sel->type]->cso == sel) {
2547 current_shader[sel->type]->cso = NULL;
2548 current_shader[sel->type]->current = NULL;
2549 }
2550
2551 while (p) {
2552 c = p->next_variant;
2553 si_delete_shader(sctx, p);
2554 p = c;
2555 }
2556
2557 if (sel->main_shader_part)
2558 si_delete_shader(sctx, sel->main_shader_part);
2559 if (sel->main_shader_part_ls)
2560 si_delete_shader(sctx, sel->main_shader_part_ls);
2561 if (sel->main_shader_part_es)
2562 si_delete_shader(sctx, sel->main_shader_part_es);
2563 if (sel->gs_copy_shader)
2564 si_delete_shader(sctx, sel->gs_copy_shader);
2565
2566 util_queue_fence_destroy(&sel->ready);
2567 mtx_destroy(&sel->mutex);
2568 free(sel->tokens);
2569 ralloc_free(sel->nir);
2570 free(sel);
2571 }
2572
2573 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
2574 {
2575 struct si_context *sctx = (struct si_context *)ctx;
2576 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2577
2578 si_shader_selector_reference(sctx, &sel, NULL);
2579 }
2580
2581 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2582 struct si_shader *vs, unsigned name,
2583 unsigned index, unsigned interpolate)
2584 {
2585 struct tgsi_shader_info *vsinfo = &vs->selector->info;
2586 unsigned j, offset, ps_input_cntl = 0;
2587
2588 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2589 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
2590 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2591
2592 if (name == TGSI_SEMANTIC_PCOORD ||
2593 (name == TGSI_SEMANTIC_TEXCOORD &&
2594 sctx->sprite_coord_enable & (1 << index))) {
2595 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2596 }
2597
2598 for (j = 0; j < vsinfo->num_outputs; j++) {
2599 if (name == vsinfo->output_semantic_name[j] &&
2600 index == vsinfo->output_semantic_index[j]) {
2601 offset = vs->info.vs_output_param_offset[j];
2602
2603 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2604 /* The input is loaded from parameter memory. */
2605 ps_input_cntl |= S_028644_OFFSET(offset);
2606 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2607 if (offset == AC_EXP_PARAM_UNDEFINED) {
2608 /* This can happen with depth-only rendering. */
2609 offset = 0;
2610 } else {
2611 /* The input is a DEFAULT_VAL constant. */
2612 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2613 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2614 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2615 }
2616
2617 ps_input_cntl = S_028644_OFFSET(0x20) |
2618 S_028644_DEFAULT_VAL(offset);
2619 }
2620 break;
2621 }
2622 }
2623
2624 if (name == TGSI_SEMANTIC_PRIMID)
2625 /* PrimID is written after the last output. */
2626 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2627 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2628 /* No corresponding output found, load defaults into input.
2629 * Don't set any other bits.
2630 * (FLAT_SHADE=1 completely changes behavior) */
2631 ps_input_cntl = S_028644_OFFSET(0x20);
2632 /* D3D 9 behaviour. GL is undefined */
2633 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2634 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2635 }
2636 return ps_input_cntl;
2637 }
2638
2639 static void si_emit_spi_map(struct si_context *sctx)
2640 {
2641 struct si_shader *ps = sctx->ps_shader.current;
2642 struct si_shader *vs = si_get_vs_state(sctx);
2643 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2644 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2645 unsigned spi_ps_input_cntl[32];
2646
2647 if (!ps || !ps->selector->info.num_inputs)
2648 return;
2649
2650 num_interp = si_get_ps_num_interp(ps);
2651 assert(num_interp > 0);
2652
2653 for (i = 0; i < psinfo->num_inputs; i++) {
2654 unsigned name = psinfo->input_semantic_name[i];
2655 unsigned index = psinfo->input_semantic_index[i];
2656 unsigned interpolate = psinfo->input_interpolate[i];
2657
2658 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
2659 index, interpolate);
2660
2661 if (name == TGSI_SEMANTIC_COLOR) {
2662 assert(index < ARRAY_SIZE(bcol_interp));
2663 bcol_interp[index] = interpolate;
2664 }
2665 }
2666
2667 if (ps->key.part.ps.prolog.color_two_side) {
2668 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2669
2670 for (i = 0; i < 2; i++) {
2671 if (!(psinfo->colors_read & (0xf << (i * 4))))
2672 continue;
2673
2674 spi_ps_input_cntl[num_written++] =
2675 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
2676
2677 }
2678 }
2679 assert(num_interp == num_written);
2680
2681 /* R_028644_SPI_PS_INPUT_CNTL_0 */
2682 /* Dota 2: Only ~16% of SPI map updates set different values. */
2683 /* Talos: Only ~9% of SPI map updates set different values. */
2684 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
2685 spi_ps_input_cntl,
2686 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
2687 }
2688
2689 /**
2690 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2691 */
2692 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2693 {
2694 if (sctx->init_config_has_vgt_flush)
2695 return;
2696
2697 /* Done by Vulkan before VGT_FLUSH. */
2698 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2699 si_pm4_cmd_add(sctx->init_config,
2700 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2701 si_pm4_cmd_end(sctx->init_config, false);
2702
2703 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2704 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2705 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2706 si_pm4_cmd_end(sctx->init_config, false);
2707 sctx->init_config_has_vgt_flush = true;
2708 }
2709
2710 /* Initialize state related to ESGS / GSVS ring buffers */
2711 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2712 {
2713 struct si_shader_selector *es =
2714 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2715 struct si_shader_selector *gs = sctx->gs_shader.cso;
2716 struct si_pm4_state *pm4;
2717
2718 /* Chip constants. */
2719 unsigned num_se = sctx->screen->info.max_se;
2720 unsigned wave_size = 64;
2721 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2722 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2723 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2724 */
2725 unsigned gs_vertex_reuse = (sctx->chip_class >= VI ? 32 : 16) * num_se;
2726 unsigned alignment = 256 * num_se;
2727 /* The maximum size is 63.999 MB per SE. */
2728 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2729
2730 /* Calculate the minimum size. */
2731 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2732 wave_size, alignment);
2733
2734 /* These are recommended sizes, not minimum sizes. */
2735 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2736 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2737 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2738 gs->max_gsvs_emit_size;
2739
2740 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2741 esgs_ring_size = align(esgs_ring_size, alignment);
2742 gsvs_ring_size = align(gsvs_ring_size, alignment);
2743
2744 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2745 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2746
2747 /* Some rings don't have to be allocated if shaders don't use them.
2748 * (e.g. no varyings between ES and GS or GS and VS)
2749 *
2750 * GFX9 doesn't have the ESGS ring.
2751 */
2752 bool update_esgs = sctx->chip_class <= VI &&
2753 esgs_ring_size &&
2754 (!sctx->esgs_ring ||
2755 sctx->esgs_ring->width0 < esgs_ring_size);
2756 bool update_gsvs = gsvs_ring_size &&
2757 (!sctx->gsvs_ring ||
2758 sctx->gsvs_ring->width0 < gsvs_ring_size);
2759
2760 if (!update_esgs && !update_gsvs)
2761 return true;
2762
2763 if (update_esgs) {
2764 pipe_resource_reference(&sctx->esgs_ring, NULL);
2765 sctx->esgs_ring =
2766 pipe_aligned_buffer_create(sctx->b.screen,
2767 SI_RESOURCE_FLAG_UNMAPPABLE,
2768 PIPE_USAGE_DEFAULT,
2769 esgs_ring_size, alignment);
2770 if (!sctx->esgs_ring)
2771 return false;
2772 }
2773
2774 if (update_gsvs) {
2775 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2776 sctx->gsvs_ring =
2777 pipe_aligned_buffer_create(sctx->b.screen,
2778 SI_RESOURCE_FLAG_UNMAPPABLE,
2779 PIPE_USAGE_DEFAULT,
2780 gsvs_ring_size, alignment);
2781 if (!sctx->gsvs_ring)
2782 return false;
2783 }
2784
2785 /* Create the "init_config_gs_rings" state. */
2786 pm4 = CALLOC_STRUCT(si_pm4_state);
2787 if (!pm4)
2788 return false;
2789
2790 if (sctx->chip_class >= CIK) {
2791 if (sctx->esgs_ring) {
2792 assert(sctx->chip_class <= VI);
2793 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2794 sctx->esgs_ring->width0 / 256);
2795 }
2796 if (sctx->gsvs_ring)
2797 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2798 sctx->gsvs_ring->width0 / 256);
2799 } else {
2800 if (sctx->esgs_ring)
2801 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2802 sctx->esgs_ring->width0 / 256);
2803 if (sctx->gsvs_ring)
2804 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2805 sctx->gsvs_ring->width0 / 256);
2806 }
2807
2808 /* Set the state. */
2809 if (sctx->init_config_gs_rings)
2810 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2811 sctx->init_config_gs_rings = pm4;
2812
2813 if (!sctx->init_config_has_vgt_flush) {
2814 si_init_config_add_vgt_flush(sctx);
2815 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2816 }
2817
2818 /* Flush the context to re-emit both init_config states. */
2819 sctx->initial_gfx_cs_size = 0; /* force flush */
2820 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
2821
2822 /* Set ring bindings. */
2823 if (sctx->esgs_ring) {
2824 assert(sctx->chip_class <= VI);
2825 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
2826 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2827 true, true, 4, 64, 0);
2828 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
2829 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2830 false, false, 0, 0, 0);
2831 }
2832 if (sctx->gsvs_ring) {
2833 si_set_ring_buffer(sctx, SI_RING_GSVS,
2834 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2835 false, false, 0, 0, 0);
2836 }
2837
2838 return true;
2839 }
2840
2841 static void si_shader_lock(struct si_shader *shader)
2842 {
2843 mtx_lock(&shader->selector->mutex);
2844 if (shader->previous_stage_sel) {
2845 assert(shader->previous_stage_sel != shader->selector);
2846 mtx_lock(&shader->previous_stage_sel->mutex);
2847 }
2848 }
2849
2850 static void si_shader_unlock(struct si_shader *shader)
2851 {
2852 if (shader->previous_stage_sel)
2853 mtx_unlock(&shader->previous_stage_sel->mutex);
2854 mtx_unlock(&shader->selector->mutex);
2855 }
2856
2857 /**
2858 * @returns 1 if \p sel has been updated to use a new scratch buffer
2859 * 0 if not
2860 * < 0 if there was a failure
2861 */
2862 static int si_update_scratch_buffer(struct si_context *sctx,
2863 struct si_shader *shader)
2864 {
2865 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2866 int r;
2867
2868 if (!shader)
2869 return 0;
2870
2871 /* This shader doesn't need a scratch buffer */
2872 if (shader->config.scratch_bytes_per_wave == 0)
2873 return 0;
2874
2875 /* Prevent race conditions when updating:
2876 * - si_shader::scratch_bo
2877 * - si_shader::binary::code
2878 * - si_shader::previous_stage::binary::code.
2879 */
2880 si_shader_lock(shader);
2881
2882 /* This shader is already configured to use the current
2883 * scratch buffer. */
2884 if (shader->scratch_bo == sctx->scratch_buffer) {
2885 si_shader_unlock(shader);
2886 return 0;
2887 }
2888
2889 assert(sctx->scratch_buffer);
2890
2891 if (shader->previous_stage)
2892 si_shader_apply_scratch_relocs(shader->previous_stage, scratch_va);
2893
2894 si_shader_apply_scratch_relocs(shader, scratch_va);
2895
2896 /* Replace the shader bo with a new bo that has the relocs applied. */
2897 r = si_shader_binary_upload(sctx->screen, shader);
2898 if (r) {
2899 si_shader_unlock(shader);
2900 return r;
2901 }
2902
2903 /* Update the shader state to use the new shader bo. */
2904 si_shader_init_pm4_state(sctx->screen, shader);
2905
2906 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2907
2908 si_shader_unlock(shader);
2909 return 1;
2910 }
2911
2912 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2913 {
2914 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2915 }
2916
2917 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2918 {
2919 return shader ? shader->config.scratch_bytes_per_wave : 0;
2920 }
2921
2922 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
2923 {
2924 if (!sctx->tes_shader.cso)
2925 return NULL; /* tessellation disabled */
2926
2927 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
2928 sctx->fixed_func_tcs_shader.current;
2929 }
2930
2931 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2932 {
2933 unsigned bytes = 0;
2934
2935 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2936 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2937 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2938 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2939
2940 if (sctx->tes_shader.cso) {
2941 struct si_shader *tcs = si_get_tcs_current(sctx);
2942
2943 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
2944 }
2945 return bytes;
2946 }
2947
2948 static bool si_update_scratch_relocs(struct si_context *sctx)
2949 {
2950 struct si_shader *tcs = si_get_tcs_current(sctx);
2951 int r;
2952
2953 /* Update the shaders, so that they are using the latest scratch.
2954 * The scratch buffer may have been changed since these shaders were
2955 * last used, so we still need to try to update them, even if they
2956 * require scratch buffers smaller than the current size.
2957 */
2958 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2959 if (r < 0)
2960 return false;
2961 if (r == 1)
2962 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2963
2964 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2965 if (r < 0)
2966 return false;
2967 if (r == 1)
2968 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2969
2970 r = si_update_scratch_buffer(sctx, tcs);
2971 if (r < 0)
2972 return false;
2973 if (r == 1)
2974 si_pm4_bind_state(sctx, hs, tcs->pm4);
2975
2976 /* VS can be bound as LS, ES, or VS. */
2977 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2978 if (r < 0)
2979 return false;
2980 if (r == 1) {
2981 if (sctx->tes_shader.current)
2982 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2983 else if (sctx->gs_shader.current)
2984 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2985 else
2986 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2987 }
2988
2989 /* TES can be bound as ES or VS. */
2990 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2991 if (r < 0)
2992 return false;
2993 if (r == 1) {
2994 if (sctx->gs_shader.current)
2995 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2996 else
2997 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2998 }
2999
3000 return true;
3001 }
3002
3003 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3004 {
3005 unsigned current_scratch_buffer_size =
3006 si_get_current_scratch_buffer_size(sctx);
3007 unsigned scratch_bytes_per_wave =
3008 si_get_max_scratch_bytes_per_wave(sctx);
3009 unsigned scratch_needed_size = scratch_bytes_per_wave *
3010 sctx->scratch_waves;
3011 unsigned spi_tmpring_size;
3012
3013 if (scratch_needed_size > 0) {
3014 if (scratch_needed_size > current_scratch_buffer_size) {
3015 /* Create a bigger scratch buffer */
3016 r600_resource_reference(&sctx->scratch_buffer, NULL);
3017
3018 sctx->scratch_buffer =
3019 si_aligned_buffer_create(&sctx->screen->b,
3020 SI_RESOURCE_FLAG_UNMAPPABLE,
3021 PIPE_USAGE_DEFAULT,
3022 scratch_needed_size, 256);
3023 if (!sctx->scratch_buffer)
3024 return false;
3025
3026 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3027 si_context_add_resource_size(sctx,
3028 &sctx->scratch_buffer->b.b);
3029 }
3030
3031 if (!si_update_scratch_relocs(sctx))
3032 return false;
3033 }
3034
3035 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3036 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3037 "scratch size should already be aligned correctly.");
3038
3039 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3040 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3041 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3042 sctx->spi_tmpring_size = spi_tmpring_size;
3043 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3044 }
3045 return true;
3046 }
3047
3048 static void si_init_tess_factor_ring(struct si_context *sctx)
3049 {
3050 assert(!sctx->tess_rings);
3051
3052 /* The address must be aligned to 2^19, because the shader only
3053 * receives the high 13 bits.
3054 */
3055 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3056 SI_RESOURCE_FLAG_32BIT,
3057 PIPE_USAGE_DEFAULT,
3058 sctx->screen->tess_offchip_ring_size +
3059 sctx->screen->tess_factor_ring_size,
3060 1 << 19);
3061 if (!sctx->tess_rings)
3062 return;
3063
3064 si_init_config_add_vgt_flush(sctx);
3065
3066 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_rings),
3067 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3068
3069 uint64_t factor_va = r600_resource(sctx->tess_rings)->gpu_address +
3070 sctx->screen->tess_offchip_ring_size;
3071
3072 /* Append these registers to the init config state. */
3073 if (sctx->chip_class >= CIK) {
3074 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3075 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3076 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3077 factor_va >> 8);
3078 if (sctx->chip_class >= GFX9)
3079 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3080 S_030944_BASE_HI(factor_va >> 40));
3081 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3082 sctx->screen->vgt_hs_offchip_param);
3083 } else {
3084 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3085 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3086 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3087 factor_va >> 8);
3088 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3089 sctx->screen->vgt_hs_offchip_param);
3090 }
3091
3092 /* Flush the context to re-emit the init_config state.
3093 * This is done only once in a lifetime of a context.
3094 */
3095 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3096 sctx->initial_gfx_cs_size = 0; /* force flush */
3097 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3098 }
3099
3100 static void si_update_vgt_shader_config(struct si_context *sctx)
3101 {
3102 /* Calculate the index of the config.
3103 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3104 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
3105 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
3106
3107 if (!*pm4) {
3108 uint32_t stages = 0;
3109
3110 *pm4 = CALLOC_STRUCT(si_pm4_state);
3111
3112 if (sctx->tes_shader.cso) {
3113 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3114 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3115
3116 if (sctx->gs_shader.cso)
3117 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3118 S_028B54_GS_EN(1) |
3119 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3120 else
3121 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3122 } else if (sctx->gs_shader.cso) {
3123 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3124 S_028B54_GS_EN(1) |
3125 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3126 }
3127
3128 if (sctx->chip_class >= GFX9)
3129 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3130
3131 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3132 }
3133 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3134 }
3135
3136 bool si_update_shaders(struct si_context *sctx)
3137 {
3138 struct pipe_context *ctx = (struct pipe_context*)sctx;
3139 struct si_compiler_ctx_state compiler_state;
3140 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3141 struct si_shader *old_vs = si_get_vs_state(sctx);
3142 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3143 struct si_shader *old_ps = sctx->ps_shader.current;
3144 unsigned old_spi_shader_col_format =
3145 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3146 int r;
3147
3148 compiler_state.compiler = &sctx->compiler;
3149 compiler_state.debug = sctx->debug;
3150 compiler_state.is_debug_context = sctx->is_debug;
3151
3152 /* Update stages before GS. */
3153 if (sctx->tes_shader.cso) {
3154 if (!sctx->tess_rings) {
3155 si_init_tess_factor_ring(sctx);
3156 if (!sctx->tess_rings)
3157 return false;
3158 }
3159
3160 /* VS as LS */
3161 if (sctx->chip_class <= VI) {
3162 r = si_shader_select(ctx, &sctx->vs_shader,
3163 &compiler_state);
3164 if (r)
3165 return false;
3166 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3167 }
3168
3169 if (sctx->tcs_shader.cso) {
3170 r = si_shader_select(ctx, &sctx->tcs_shader,
3171 &compiler_state);
3172 if (r)
3173 return false;
3174 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3175 } else {
3176 if (!sctx->fixed_func_tcs_shader.cso) {
3177 sctx->fixed_func_tcs_shader.cso =
3178 si_create_fixed_func_tcs(sctx);
3179 if (!sctx->fixed_func_tcs_shader.cso)
3180 return false;
3181 }
3182
3183 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3184 &compiler_state);
3185 if (r)
3186 return false;
3187 si_pm4_bind_state(sctx, hs,
3188 sctx->fixed_func_tcs_shader.current->pm4);
3189 }
3190
3191 if (sctx->gs_shader.cso) {
3192 /* TES as ES */
3193 if (sctx->chip_class <= VI) {
3194 r = si_shader_select(ctx, &sctx->tes_shader,
3195 &compiler_state);
3196 if (r)
3197 return false;
3198 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3199 }
3200 } else {
3201 /* TES as VS */
3202 r = si_shader_select(ctx, &sctx->tes_shader,
3203 &compiler_state);
3204 if (r)
3205 return false;
3206 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3207 }
3208 } else if (sctx->gs_shader.cso) {
3209 if (sctx->chip_class <= VI) {
3210 /* VS as ES */
3211 r = si_shader_select(ctx, &sctx->vs_shader,
3212 &compiler_state);
3213 if (r)
3214 return false;
3215 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3216
3217 si_pm4_bind_state(sctx, ls, NULL);
3218 si_pm4_bind_state(sctx, hs, NULL);
3219 }
3220 } else {
3221 /* VS as VS */
3222 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
3223 if (r)
3224 return false;
3225 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3226 si_pm4_bind_state(sctx, ls, NULL);
3227 si_pm4_bind_state(sctx, hs, NULL);
3228 }
3229
3230 /* Update GS. */
3231 if (sctx->gs_shader.cso) {
3232 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
3233 if (r)
3234 return false;
3235 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3236 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3237
3238 if (!si_update_gs_ring_buffers(sctx))
3239 return false;
3240 } else {
3241 si_pm4_bind_state(sctx, gs, NULL);
3242 if (sctx->chip_class <= VI)
3243 si_pm4_bind_state(sctx, es, NULL);
3244 }
3245
3246 si_update_vgt_shader_config(sctx);
3247
3248 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3249 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3250
3251 if (sctx->ps_shader.cso) {
3252 unsigned db_shader_control;
3253
3254 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
3255 if (r)
3256 return false;
3257 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3258
3259 db_shader_control =
3260 sctx->ps_shader.cso->db_shader_control |
3261 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3262
3263 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3264 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3265 sctx->flatshade != rs->flatshade) {
3266 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3267 sctx->flatshade = rs->flatshade;
3268 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3269 }
3270
3271 if (sctx->screen->rbplus_allowed &&
3272 si_pm4_state_changed(sctx, ps) &&
3273 (!old_ps ||
3274 old_spi_shader_col_format !=
3275 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3276 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3277
3278 if (sctx->ps_db_shader_control != db_shader_control) {
3279 sctx->ps_db_shader_control = db_shader_control;
3280 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3281 if (sctx->screen->dpbb_allowed)
3282 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3283 }
3284
3285 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3286 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3287 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3288
3289 if (sctx->chip_class == SI)
3290 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3291
3292 if (sctx->framebuffer.nr_samples <= 1)
3293 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3294 }
3295 }
3296
3297 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3298 si_pm4_state_enabled_and_changed(sctx, hs) ||
3299 si_pm4_state_enabled_and_changed(sctx, es) ||
3300 si_pm4_state_enabled_and_changed(sctx, gs) ||
3301 si_pm4_state_enabled_and_changed(sctx, vs) ||
3302 si_pm4_state_enabled_and_changed(sctx, ps)) {
3303 if (!si_update_spi_tmpring_size(sctx))
3304 return false;
3305 }
3306
3307 if (sctx->chip_class >= CIK) {
3308 if (si_pm4_state_enabled_and_changed(sctx, ls))
3309 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3310 else if (!sctx->queued.named.ls)
3311 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3312
3313 if (si_pm4_state_enabled_and_changed(sctx, hs))
3314 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3315 else if (!sctx->queued.named.hs)
3316 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3317
3318 if (si_pm4_state_enabled_and_changed(sctx, es))
3319 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3320 else if (!sctx->queued.named.es)
3321 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3322
3323 if (si_pm4_state_enabled_and_changed(sctx, gs))
3324 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3325 else if (!sctx->queued.named.gs)
3326 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3327
3328 if (si_pm4_state_enabled_and_changed(sctx, vs))
3329 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3330 else if (!sctx->queued.named.vs)
3331 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3332
3333 if (si_pm4_state_enabled_and_changed(sctx, ps))
3334 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3335 else if (!sctx->queued.named.ps)
3336 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3337 }
3338
3339 sctx->do_update_shaders = false;
3340 return true;
3341 }
3342
3343 static void si_emit_scratch_state(struct si_context *sctx)
3344 {
3345 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3346
3347 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3348 sctx->spi_tmpring_size);
3349
3350 if (sctx->scratch_buffer) {
3351 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3352 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3353 RADEON_PRIO_SCRATCH_BUFFER);
3354 }
3355 }
3356
3357 void si_init_shader_functions(struct si_context *sctx)
3358 {
3359 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
3360 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
3361
3362 sctx->b.create_vs_state = si_create_shader_selector;
3363 sctx->b.create_tcs_state = si_create_shader_selector;
3364 sctx->b.create_tes_state = si_create_shader_selector;
3365 sctx->b.create_gs_state = si_create_shader_selector;
3366 sctx->b.create_fs_state = si_create_shader_selector;
3367
3368 sctx->b.bind_vs_state = si_bind_vs_shader;
3369 sctx->b.bind_tcs_state = si_bind_tcs_shader;
3370 sctx->b.bind_tes_state = si_bind_tes_shader;
3371 sctx->b.bind_gs_state = si_bind_gs_shader;
3372 sctx->b.bind_fs_state = si_bind_ps_shader;
3373
3374 sctx->b.delete_vs_state = si_delete_shader_selector;
3375 sctx->b.delete_tcs_state = si_delete_shader_selector;
3376 sctx->b.delete_tes_state = si_delete_shader_selector;
3377 sctx->b.delete_gs_state = si_delete_shader_selector;
3378 sctx->b.delete_fs_state = si_delete_shader_selector;
3379 }