2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "radeon/r600_cs.h"
30 #include "compiler/nir/nir_serialize.h"
31 #include "tgsi/tgsi_parse.h"
32 #include "tgsi/tgsi_ureg.h"
33 #include "util/hash_table.h"
34 #include "util/crc32.h"
35 #include "util/u_async_debug.h"
36 #include "util/u_memory.h"
37 #include "util/u_prim.h"
39 #include "util/disk_cache.h"
40 #include "util/mesa-sha1.h"
41 #include "ac_exp_param.h"
42 #include "ac_shader_util.h"
47 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
50 static void *si_get_ir_binary(struct si_shader_selector
*sel
)
57 ir_binary
= sel
->tokens
;
58 ir_size
= tgsi_num_tokens(sel
->tokens
) *
59 sizeof(struct tgsi_token
);
64 nir_serialize(&blob
, sel
->nir
);
65 ir_binary
= blob
.data
;
69 unsigned size
= 4 + ir_size
+ sizeof(sel
->so
);
70 char *result
= (char*)MALLOC(size
);
74 *((uint32_t*)result
) = size
;
75 memcpy(result
+ 4, ir_binary
, ir_size
);
76 memcpy(result
+ 4 + ir_size
, &sel
->so
, sizeof(sel
->so
));
84 /** Copy "data" to "ptr" and return the next dword following copied data. */
85 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
87 /* data may be NULL if size == 0 */
89 memcpy(ptr
, data
, size
);
90 ptr
+= DIV_ROUND_UP(size
, 4);
94 /** Read data from "ptr". Return the next dword following the data. */
95 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
97 memcpy(data
, ptr
, size
);
98 ptr
+= DIV_ROUND_UP(size
, 4);
103 * Write the size as uint followed by the data. Return the next dword
104 * following the copied data.
106 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
109 return write_data(ptr
, data
, size
);
113 * Read the size as uint followed by the data. Return both via parameters.
114 * Return the next dword following the data.
116 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
119 assert(*data
== NULL
);
122 *data
= malloc(*size
);
123 return read_data(ptr
, *data
, *size
);
127 * Return the shader binary in a buffer. The first 4 bytes contain its size
130 static void *si_get_shader_binary(struct si_shader
*shader
)
132 /* There is always a size of data followed by the data itself. */
133 unsigned relocs_size
= shader
->binary
.reloc_count
*
134 sizeof(shader
->binary
.relocs
[0]);
135 unsigned disasm_size
= shader
->binary
.disasm_string
?
136 strlen(shader
->binary
.disasm_string
) + 1 : 0;
137 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
138 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
141 4 + /* CRC32 of the data below */
142 align(sizeof(shader
->config
), 4) +
143 align(sizeof(shader
->info
), 4) +
144 4 + align(shader
->binary
.code_size
, 4) +
145 4 + align(shader
->binary
.rodata_size
, 4) +
146 4 + align(relocs_size
, 4) +
147 4 + align(disasm_size
, 4) +
148 4 + align(llvm_ir_size
, 4);
149 void *buffer
= CALLOC(1, size
);
150 uint32_t *ptr
= (uint32_t*)buffer
;
156 ptr
++; /* CRC32 is calculated at the end. */
158 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
159 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
160 ptr
= write_chunk(ptr
, shader
->binary
.code
, shader
->binary
.code_size
);
161 ptr
= write_chunk(ptr
, shader
->binary
.rodata
, shader
->binary
.rodata_size
);
162 ptr
= write_chunk(ptr
, shader
->binary
.relocs
, relocs_size
);
163 ptr
= write_chunk(ptr
, shader
->binary
.disasm_string
, disasm_size
);
164 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
165 assert((char *)ptr
- (char *)buffer
== size
);
168 ptr
= (uint32_t*)buffer
;
170 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
175 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
177 uint32_t *ptr
= (uint32_t*)binary
;
178 uint32_t size
= *ptr
++;
179 uint32_t crc32
= *ptr
++;
182 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
183 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
187 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
188 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
189 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.code
,
190 &shader
->binary
.code_size
);
191 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.rodata
,
192 &shader
->binary
.rodata_size
);
193 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.relocs
, &chunk_size
);
194 shader
->binary
.reloc_count
= chunk_size
/ sizeof(shader
->binary
.relocs
[0]);
195 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.disasm_string
, &chunk_size
);
196 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
202 * Insert a shader into the cache. It's assumed the shader is not in the cache.
203 * Use si_shader_cache_load_shader before calling this.
205 * Returns false on failure, in which case the ir_binary should be freed.
207 static bool si_shader_cache_insert_shader(struct si_screen
*sscreen
,
209 struct si_shader
*shader
,
210 bool insert_into_disk_cache
)
213 struct hash_entry
*entry
;
214 uint8_t key
[CACHE_KEY_SIZE
];
216 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
218 return false; /* already added */
220 hw_binary
= si_get_shader_binary(shader
);
224 if (_mesa_hash_table_insert(sscreen
->shader_cache
, ir_binary
,
225 hw_binary
) == NULL
) {
230 if (sscreen
->disk_shader_cache
&& insert_into_disk_cache
) {
231 disk_cache_compute_key(sscreen
->disk_shader_cache
, ir_binary
,
232 *((uint32_t *)ir_binary
), key
);
233 disk_cache_put(sscreen
->disk_shader_cache
, key
, hw_binary
,
234 *((uint32_t *) hw_binary
), NULL
);
240 static bool si_shader_cache_load_shader(struct si_screen
*sscreen
,
242 struct si_shader
*shader
)
244 struct hash_entry
*entry
=
245 _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
247 if (sscreen
->disk_shader_cache
) {
248 unsigned char sha1
[CACHE_KEY_SIZE
];
249 size_t tg_size
= *((uint32_t *) ir_binary
);
251 disk_cache_compute_key(sscreen
->disk_shader_cache
,
252 ir_binary
, tg_size
, sha1
);
256 disk_cache_get(sscreen
->disk_shader_cache
,
261 if (binary_size
< sizeof(uint32_t) ||
262 *((uint32_t*)buffer
) != binary_size
) {
263 /* Something has gone wrong discard the item
264 * from the cache and rebuild/link from
267 assert(!"Invalid radeonsi shader disk cache "
270 disk_cache_remove(sscreen
->disk_shader_cache
,
277 if (!si_load_shader_binary(shader
, buffer
)) {
283 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
,
290 if (si_load_shader_binary(shader
, entry
->data
))
295 p_atomic_inc(&sscreen
->num_shader_cache_hits
);
299 static uint32_t si_shader_cache_key_hash(const void *key
)
301 /* The first dword is the key size. */
302 return util_hash_crc32(key
, *(uint32_t*)key
);
305 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
307 uint32_t *keya
= (uint32_t*)a
;
308 uint32_t *keyb
= (uint32_t*)b
;
310 /* The first dword is the key size. */
314 return memcmp(keya
, keyb
, *keya
) == 0;
317 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
319 FREE((void*)entry
->key
);
323 bool si_init_shader_cache(struct si_screen
*sscreen
)
325 (void) mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
326 sscreen
->shader_cache
=
327 _mesa_hash_table_create(NULL
,
328 si_shader_cache_key_hash
,
329 si_shader_cache_key_equals
);
331 return sscreen
->shader_cache
!= NULL
;
334 void si_destroy_shader_cache(struct si_screen
*sscreen
)
336 if (sscreen
->shader_cache
)
337 _mesa_hash_table_destroy(sscreen
->shader_cache
,
338 si_destroy_shader_cache_entry
);
339 mtx_destroy(&sscreen
->shader_cache_mutex
);
344 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
345 struct si_shader_selector
*tes
,
346 struct si_pm4_state
*pm4
)
348 struct tgsi_shader_info
*info
= &tes
->info
;
349 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
350 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
351 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
352 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
353 unsigned type
, partitioning
, topology
, distribution_mode
;
355 switch (tes_prim_mode
) {
356 case PIPE_PRIM_LINES
:
357 type
= V_028B6C_TESS_ISOLINE
;
359 case PIPE_PRIM_TRIANGLES
:
360 type
= V_028B6C_TESS_TRIANGLE
;
362 case PIPE_PRIM_QUADS
:
363 type
= V_028B6C_TESS_QUAD
;
370 switch (tes_spacing
) {
371 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
372 partitioning
= V_028B6C_PART_FRAC_ODD
;
374 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
375 partitioning
= V_028B6C_PART_FRAC_EVEN
;
377 case PIPE_TESS_SPACING_EQUAL
:
378 partitioning
= V_028B6C_PART_INTEGER
;
386 topology
= V_028B6C_OUTPUT_POINT
;
387 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
388 topology
= V_028B6C_OUTPUT_LINE
;
389 else if (tes_vertex_order_cw
)
390 /* for some reason, this must be the other way around */
391 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
393 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
395 if (sscreen
->has_distributed_tess
) {
396 if (sscreen
->info
.family
== CHIP_FIJI
||
397 sscreen
->info
.family
>= CHIP_POLARIS10
)
398 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
400 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
402 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
404 si_pm4_set_reg(pm4
, R_028B6C_VGT_TF_PARAM
,
405 S_028B6C_TYPE(type
) |
406 S_028B6C_PARTITIONING(partitioning
) |
407 S_028B6C_TOPOLOGY(topology
) |
408 S_028B6C_DISTRIBUTION_MODE(distribution_mode
));
411 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
412 * whether the "fractional odd" tessellation spacing is used.
414 * Possible VGT configurations and which state should set the register:
416 * Reg set in | VGT shader configuration | Value
417 * ------------------------------------------------------
419 * VS as ES | ES -> GS -> VS | 30
420 * TES as VS | LS -> HS -> VS | 14 or 30
421 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
423 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
425 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
426 struct si_shader_selector
*sel
,
427 struct si_shader
*shader
,
428 struct si_pm4_state
*pm4
)
430 unsigned type
= sel
->type
;
432 if (sscreen
->info
.family
< CHIP_POLARIS10
)
435 /* VS as VS, or VS as ES: */
436 if ((type
== PIPE_SHADER_VERTEX
&&
438 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
439 /* TES as VS, or TES as ES: */
440 type
== PIPE_SHADER_TESS_EVAL
) {
441 unsigned vtx_reuse_depth
= 30;
443 if (type
== PIPE_SHADER_TESS_EVAL
&&
444 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
445 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
446 vtx_reuse_depth
= 14;
448 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
453 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
456 si_pm4_clear_state(shader
->pm4
);
458 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
463 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs
)
465 /* Add the pointer to VBO descriptors. */
466 if (HAVE_32BIT_POINTERS
) {
467 return num_always_on_user_sgprs
+ 1;
469 assert(num_always_on_user_sgprs
% 2 == 0);
470 return num_always_on_user_sgprs
+ 2;
474 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
476 struct si_pm4_state
*pm4
;
477 unsigned vgpr_comp_cnt
;
480 assert(sscreen
->info
.chip_class
<= VI
);
482 pm4
= si_get_shader_pm4_state(shader
);
486 va
= shader
->bo
->gpu_address
;
487 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
489 /* We need at least 2 components for LS.
490 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
491 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
493 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
495 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
496 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
498 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
499 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
500 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
501 S_00B528_DX10_CLAMP(1) |
502 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
503 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
)) |
504 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
507 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
509 struct si_pm4_state
*pm4
;
511 unsigned ls_vgpr_comp_cnt
= 0;
513 pm4
= si_get_shader_pm4_state(shader
);
517 va
= shader
->bo
->gpu_address
;
518 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
520 if (sscreen
->info
.chip_class
>= GFX9
) {
521 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
522 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, S_00B414_MEM_BASE(va
>> 40));
524 /* We need at least 2 components for LS.
525 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
526 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
528 ls_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
530 unsigned num_user_sgprs
=
531 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR
);
533 shader
->config
.rsrc2
=
534 S_00B42C_USER_SGPR(num_user_sgprs
) |
535 S_00B42C_USER_SGPR_MSB(num_user_sgprs
>> 5) |
536 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
538 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
539 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, S_00B424_MEM_BASE(va
>> 40));
541 shader
->config
.rsrc2
=
542 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
543 S_00B42C_OC_LDS_EN(1) |
544 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
547 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
548 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
549 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
550 S_00B428_DX10_CLAMP(1) |
551 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
552 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt
));
554 if (sscreen
->info
.chip_class
<= VI
) {
555 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
556 shader
->config
.rsrc2
);
560 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
562 struct si_pm4_state
*pm4
;
563 unsigned num_user_sgprs
;
564 unsigned vgpr_comp_cnt
;
568 assert(sscreen
->info
.chip_class
<= VI
);
570 pm4
= si_get_shader_pm4_state(shader
);
574 va
= shader
->bo
->gpu_address
;
575 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
577 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
578 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
579 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
580 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
581 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
582 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
583 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
585 unreachable("invalid shader selector type");
587 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
589 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
590 shader
->selector
->esgs_itemsize
/ 4);
591 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
592 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
593 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
594 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
595 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
596 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
597 S_00B328_DX10_CLAMP(1) |
598 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
599 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
600 S_00B32C_USER_SGPR(num_user_sgprs
) |
601 S_00B32C_OC_LDS_EN(oc_lds_en
) |
602 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
604 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
605 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
607 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
610 struct gfx9_gs_info
{
611 unsigned es_verts_per_subgroup
;
612 unsigned gs_prims_per_subgroup
;
613 unsigned gs_inst_prims_in_subgroup
;
614 unsigned max_prims_per_subgroup
;
618 static void gfx9_get_gs_info(struct si_shader_selector
*es
,
619 struct si_shader_selector
*gs
,
620 struct gfx9_gs_info
*out
)
622 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
623 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
624 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
625 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
627 /* All these are in dwords: */
628 /* We can't allow using the whole LDS, because GS waves compete with
629 * other shader stages for LDS space. */
630 const unsigned max_lds_size
= 8 * 1024;
631 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
632 unsigned esgs_lds_size
;
634 /* All these are per subgroup: */
635 const unsigned max_out_prims
= 32 * 1024;
636 const unsigned max_es_verts
= 255;
637 const unsigned ideal_gs_prims
= 64;
638 unsigned max_gs_prims
, gs_prims
;
639 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
641 assert(gs_num_invocations
<= 32); /* GL maximum */
643 if (uses_adjacency
|| gs_num_invocations
> 1)
644 max_gs_prims
= 127 / gs_num_invocations
;
648 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
649 * Make sure we don't go over the maximum value.
651 if (gs
->gs_max_out_vertices
> 0) {
652 max_gs_prims
= MIN2(max_gs_prims
,
654 (gs
->gs_max_out_vertices
* gs_num_invocations
));
656 assert(max_gs_prims
> 0);
658 /* If the primitive has adjacency, halve the number of vertices
659 * that will be reused in multiple primitives.
661 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
663 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
664 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
666 /* Compute ESGS LDS size based on the worst case number of ES vertices
667 * needed to create the target number of GS prims per subgroup.
669 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
671 /* If total LDS usage is too big, refactor partitions based on ratio
672 * of ESGS item sizes.
674 if (esgs_lds_size
> max_lds_size
) {
675 /* Our target GS Prims Per Subgroup was too large. Calculate
676 * the maximum number of GS Prims Per Subgroup that will fit
677 * into LDS, capped by the maximum that the hardware can support.
679 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
681 assert(gs_prims
> 0);
682 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
685 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
686 assert(esgs_lds_size
<= max_lds_size
);
689 /* Now calculate remaining ESGS information. */
691 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
693 es_verts
= max_es_verts
;
695 /* Vertices for adjacency primitives are not always reused, so restore
696 * it for ES_VERTS_PER_SUBGRP.
698 min_es_verts
= gs
->gs_input_verts_per_prim
;
700 /* For normal primitives, the VGT only checks if they are past the ES
701 * verts per subgroup after allocating a full GS primitive and if they
702 * are, kick off a new subgroup. But if those additional ES verts are
703 * unique (e.g. not reused) we need to make sure there is enough LDS
704 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
706 es_verts
-= min_es_verts
- 1;
708 out
->es_verts_per_subgroup
= es_verts
;
709 out
->gs_prims_per_subgroup
= gs_prims
;
710 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
711 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
712 gs
->gs_max_out_vertices
;
713 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
715 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
718 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
720 struct si_shader_selector
*sel
= shader
->selector
;
721 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
722 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
723 struct si_pm4_state
*pm4
;
725 unsigned max_stream
= sel
->max_gs_stream
;
728 pm4
= si_get_shader_pm4_state(shader
);
732 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
733 si_pm4_set_reg(pm4
, R_028A60_VGT_GSVS_RING_OFFSET_1
, offset
);
735 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
736 si_pm4_set_reg(pm4
, R_028A64_VGT_GSVS_RING_OFFSET_2
, offset
);
738 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
739 si_pm4_set_reg(pm4
, R_028A68_VGT_GSVS_RING_OFFSET_3
, offset
);
741 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
742 si_pm4_set_reg(pm4
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
744 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
745 assert(offset
< (1 << 15));
747 si_pm4_set_reg(pm4
, R_028B38_VGT_GS_MAX_VERT_OUT
, sel
->gs_max_out_vertices
);
749 si_pm4_set_reg(pm4
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, num_components
[0]);
750 si_pm4_set_reg(pm4
, R_028B60_VGT_GS_VERT_ITEMSIZE_1
, (max_stream
>= 1) ? num_components
[1] : 0);
751 si_pm4_set_reg(pm4
, R_028B64_VGT_GS_VERT_ITEMSIZE_2
, (max_stream
>= 2) ? num_components
[2] : 0);
752 si_pm4_set_reg(pm4
, R_028B68_VGT_GS_VERT_ITEMSIZE_3
, (max_stream
>= 3) ? num_components
[3] : 0);
754 si_pm4_set_reg(pm4
, R_028B90_VGT_GS_INSTANCE_CNT
,
755 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
756 S_028B90_ENABLE(gs_num_invocations
> 0));
758 va
= shader
->bo
->gpu_address
;
759 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
761 if (sscreen
->info
.chip_class
>= GFX9
) {
762 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
763 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
764 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
765 struct gfx9_gs_info gs_info
;
767 if (es_type
== PIPE_SHADER_VERTEX
)
768 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
769 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
770 else if (es_type
== PIPE_SHADER_TESS_EVAL
)
771 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
773 unreachable("invalid shader selector type");
775 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
776 * VGPR[0:4] are always loaded.
778 if (sel
->info
.uses_invocationid
)
779 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
780 else if (sel
->info
.uses_primid
)
781 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
782 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
783 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
785 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
787 unsigned num_user_sgprs
;
788 if (es_type
== PIPE_SHADER_VERTEX
)
789 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
791 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
793 gfx9_get_gs_info(shader
->key
.part
.gs
.es
, sel
, &gs_info
);
795 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
796 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, S_00B214_MEM_BASE(va
>> 40));
798 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
799 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
800 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
801 S_00B228_DX10_CLAMP(1) |
802 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
803 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
804 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
805 S_00B22C_USER_SGPR(num_user_sgprs
) |
806 S_00B22C_USER_SGPR_MSB(num_user_sgprs
>> 5) |
807 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
808 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
809 S_00B22C_LDS_SIZE(gs_info
.lds_size
) |
810 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
812 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
813 S_028A44_ES_VERTS_PER_SUBGRP(gs_info
.es_verts_per_subgroup
) |
814 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info
.gs_prims_per_subgroup
) |
815 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info
.gs_inst_prims_in_subgroup
));
816 si_pm4_set_reg(pm4
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
817 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info
.max_prims_per_subgroup
));
818 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
819 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4);
821 if (es_type
== PIPE_SHADER_TESS_EVAL
)
822 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
824 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
827 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
828 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, S_00B224_MEM_BASE(va
>> 40));
830 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
831 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
832 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
833 S_00B228_DX10_CLAMP(1) |
834 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
835 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
836 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
837 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
842 * Compute the state for \p shader, which will run as a vertex shader on the
845 * If \p gs is non-NULL, it points to the geometry shader for which this shader
846 * is the copy shader.
848 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
849 struct si_shader_selector
*gs
)
851 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
852 struct si_pm4_state
*pm4
;
853 unsigned num_user_sgprs
;
854 unsigned nparams
, vgpr_comp_cnt
;
857 unsigned window_space
=
858 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
859 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
861 pm4
= si_get_shader_pm4_state(shader
);
865 /* We always write VGT_GS_MODE in the VS state, because every switch
866 * between different shader pipelines involving a different GS or no
867 * GS at all involves a switch of the VS (different GS use different
868 * copy shaders). On the other hand, when the API switches from a GS to
869 * no GS and then back to the same GS used originally, the GS state is
873 unsigned mode
= V_028A40_GS_OFF
;
875 /* PrimID needs GS scenario A. */
877 mode
= V_028A40_GS_SCENARIO_A
;
879 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, S_028A40_MODE(mode
));
880 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, enable_prim_id
);
882 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
,
883 ac_vgt_gs_mode(gs
->gs_max_out_vertices
,
884 sscreen
->info
.chip_class
));
885 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
888 if (sscreen
->info
.chip_class
<= VI
) {
889 /* Reuse needs to be set off if we write oViewport. */
890 si_pm4_set_reg(pm4
, R_028AB4_VGT_REUSE_OFF
,
891 S_028AB4_REUSE_OFF(info
->writes_viewport_index
));
894 va
= shader
->bo
->gpu_address
;
895 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
898 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
899 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
900 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
901 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
902 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
903 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
905 vgpr_comp_cnt
= enable_prim_id
? 2 : (shader
->info
.uses_instanceid
? 1 : 0);
907 if (info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
]) {
908 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
909 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
911 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
913 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
914 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
915 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
917 unreachable("invalid shader selector type");
919 /* VS is required to export at least one param. */
920 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
921 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
922 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
924 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
925 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
926 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
927 V_02870C_SPI_SHADER_4COMP
:
928 V_02870C_SPI_SHADER_NONE
) |
929 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
930 V_02870C_SPI_SHADER_4COMP
:
931 V_02870C_SPI_SHADER_NONE
) |
932 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
933 V_02870C_SPI_SHADER_4COMP
:
934 V_02870C_SPI_SHADER_NONE
));
936 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
938 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
939 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, S_00B124_MEM_BASE(va
>> 40));
940 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
941 S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
942 S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
943 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
944 S_00B128_DX10_CLAMP(1) |
945 S_00B128_FLOAT_MODE(shader
->config
.float_mode
));
946 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
947 S_00B12C_USER_SGPR(num_user_sgprs
) |
948 S_00B12C_OC_LDS_EN(oc_lds_en
) |
949 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
950 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
951 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
952 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
953 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
) |
954 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
956 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
957 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
959 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
960 S_028818_VTX_W0_FMT(1) |
961 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
962 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
963 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
965 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
966 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
968 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
971 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
973 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
974 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
975 !!(info
->colors_read
& 0xf0);
976 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
977 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
979 assert(num_interp
<= 32);
980 return MIN2(num_interp
, 32);
983 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
985 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
986 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
988 /* If the i-th target format is set, all previous target formats must
989 * be non-zero to avoid hangs.
991 for (i
= 0; i
< num_targets
; i
++)
992 if (!(value
& (0xf << (i
* 4))))
993 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
998 static void si_shader_ps(struct si_shader
*shader
)
1000 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1001 struct si_pm4_state
*pm4
;
1002 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1003 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1005 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1007 /* we need to enable at least one of them, otherwise we hang the GPU */
1008 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1009 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1010 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1011 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1012 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1013 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1014 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1015 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1016 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1017 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
1018 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1019 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1020 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1021 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1023 /* Validate interpolation optimization flags (read as implications). */
1024 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1025 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1026 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1027 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1028 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1029 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1030 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1031 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1032 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1033 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1034 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1035 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1036 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1037 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1038 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1039 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1040 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1041 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1043 /* Validate cases when the optimizations are off (read as implications). */
1044 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1045 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1046 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1047 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1048 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1049 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1051 pm4
= si_get_shader_pm4_state(shader
);
1055 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1057 * 0 -> Position = pixel center
1058 * 1 -> Position = pixel centroid
1059 * 2 -> Position = at sample position
1061 * From GLSL 4.5 specification, section 7.1:
1062 * "The variable gl_FragCoord is available as an input variable from
1063 * within fragment shaders and it holds the window relative coordinates
1064 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1065 * value can be for any location within the pixel, or one of the
1066 * fragment samples. The use of centroid does not further restrict
1067 * this value to be inside the current primitive."
1069 * Meaning that centroid has no effect and we can return anything within
1070 * the pixel. Thus, return the value at sample position, because that's
1071 * the most accurate one shaders can get.
1073 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1075 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1076 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1077 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1079 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1080 cb_shader_mask
= ac_get_cb_shader_mask(spi_shader_col_format
);
1082 /* Ensure that some export memory is always allocated, for two reasons:
1084 * 1) Correctness: The hardware ignores the EXEC mask if no export
1085 * memory is allocated, so KILL and alpha test do not work correctly
1087 * 2) Performance: Every shader needs at least a NULL export, even when
1088 * it writes no color/depth output. The NULL export instruction
1089 * stalls without this setting.
1091 * Don't add this to CB_SHADER_MASK.
1093 if (!spi_shader_col_format
&&
1094 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1095 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1097 si_pm4_set_reg(pm4
, R_0286CC_SPI_PS_INPUT_ENA
, input_ena
);
1098 si_pm4_set_reg(pm4
, R_0286D0_SPI_PS_INPUT_ADDR
,
1099 shader
->config
.spi_ps_input_addr
);
1101 /* Set interpolation controls. */
1102 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
));
1104 /* Set registers. */
1105 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
1106 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
1108 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
,
1109 ac_get_spi_shader_z_format(info
->writes_z
,
1110 info
->writes_stencil
,
1111 info
->writes_samplemask
));
1113 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
, spi_shader_col_format
);
1114 si_pm4_set_reg(pm4
, R_02823C_CB_SHADER_MASK
, cb_shader_mask
);
1116 va
= shader
->bo
->gpu_address
;
1117 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1118 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1119 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, S_00B024_MEM_BASE(va
>> 40));
1121 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
1122 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1123 S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
1124 S_00B028_DX10_CLAMP(1) |
1125 S_00B028_FLOAT_MODE(shader
->config
.float_mode
));
1126 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1127 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1128 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1129 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1132 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1133 struct si_shader
*shader
)
1135 switch (shader
->selector
->type
) {
1136 case PIPE_SHADER_VERTEX
:
1137 if (shader
->key
.as_ls
)
1138 si_shader_ls(sscreen
, shader
);
1139 else if (shader
->key
.as_es
)
1140 si_shader_es(sscreen
, shader
);
1142 si_shader_vs(sscreen
, shader
, NULL
);
1144 case PIPE_SHADER_TESS_CTRL
:
1145 si_shader_hs(sscreen
, shader
);
1147 case PIPE_SHADER_TESS_EVAL
:
1148 if (shader
->key
.as_es
)
1149 si_shader_es(sscreen
, shader
);
1151 si_shader_vs(sscreen
, shader
, NULL
);
1153 case PIPE_SHADER_GEOMETRY
:
1154 si_shader_gs(sscreen
, shader
);
1156 case PIPE_SHADER_FRAGMENT
:
1157 si_shader_ps(shader
);
1164 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1166 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1167 if (sctx
->queued
.named
.dsa
)
1168 return sctx
->queued
.named
.dsa
->alpha_func
;
1170 return PIPE_FUNC_ALWAYS
;
1173 static void si_shader_selector_key_vs(struct si_context
*sctx
,
1174 struct si_shader_selector
*vs
,
1175 struct si_shader_key
*key
,
1176 struct si_vs_prolog_bits
*prolog_key
)
1178 if (!sctx
->vertex_elements
)
1181 prolog_key
->instance_divisor_is_one
=
1182 sctx
->vertex_elements
->instance_divisor_is_one
;
1183 prolog_key
->instance_divisor_is_fetched
=
1184 sctx
->vertex_elements
->instance_divisor_is_fetched
;
1186 /* Prefer a monolithic shader to allow scheduling divisions around
1188 if (prolog_key
->instance_divisor_is_fetched
)
1189 key
->opt
.prefer_mono
= 1;
1191 unsigned count
= MIN2(vs
->info
.num_inputs
,
1192 sctx
->vertex_elements
->count
);
1193 memcpy(key
->mono
.vs_fix_fetch
, sctx
->vertex_elements
->fix_fetch
, count
);
1196 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1197 struct si_shader_selector
*vs
,
1198 struct si_shader_key
*key
)
1200 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1202 key
->opt
.clip_disable
=
1203 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1204 (vs
->info
.clipdist_writemask
||
1205 vs
->info
.writes_clipvertex
) &&
1206 !vs
->info
.culldist_writemask
;
1208 /* Find out if PS is disabled. */
1209 bool ps_disabled
= true;
1211 const struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1212 bool alpha_to_coverage
= blend
&& blend
->alpha_to_coverage
;
1213 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1214 ps
->info
.writes_z
||
1215 ps
->info
.writes_stencil
||
1216 ps
->info
.writes_samplemask
||
1217 alpha_to_coverage
||
1218 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1219 unsigned ps_colormask
= si_get_total_colormask(sctx
);
1221 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1224 !ps
->info
.writes_memory
);
1227 /* Find out which VS outputs aren't used by the PS. */
1228 uint64_t outputs_written
= vs
->outputs_written
;
1229 uint64_t inputs_read
= 0;
1231 /* ignore POSITION, PSIZE */
1232 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION
, 0) |
1233 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE
, 0))));
1236 inputs_read
= ps
->inputs_read
;
1239 uint64_t linked
= outputs_written
& inputs_read
;
1241 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1244 /* Compute the key for the hw shader variant */
1245 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1246 struct si_shader_selector
*sel
,
1247 struct si_shader_key
*key
)
1249 struct si_context
*sctx
= (struct si_context
*)ctx
;
1251 memset(key
, 0, sizeof(*key
));
1253 switch (sel
->type
) {
1254 case PIPE_SHADER_VERTEX
:
1255 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1257 if (sctx
->tes_shader
.cso
)
1259 else if (sctx
->gs_shader
.cso
)
1262 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1264 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1265 key
->mono
.u
.vs_export_prim_id
= 1;
1268 case PIPE_SHADER_TESS_CTRL
:
1269 if (sctx
->b
.chip_class
>= GFX9
) {
1270 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1271 key
, &key
->part
.tcs
.ls_prolog
);
1272 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1274 /* When the LS VGPR fix is needed, monolithic shaders
1276 * - avoid initializing EXEC in both the LS prolog
1277 * and the LS main part when !vs_needs_prolog
1278 * - remove the fixup for unused input VGPRs
1280 key
->part
.tcs
.ls_prolog
.ls_vgpr_fix
= sctx
->ls_vgpr_fix
;
1282 /* The LS output / HS input layout can be communicated
1283 * directly instead of via user SGPRs for merged LS-HS.
1284 * The LS VGPR fix prefers this too.
1286 key
->opt
.prefer_mono
= 1;
1289 key
->part
.tcs
.epilog
.prim_mode
=
1290 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1291 key
->part
.tcs
.epilog
.invoc0_tess_factors_are_def
=
1292 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1293 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1294 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1296 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1297 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1299 case PIPE_SHADER_TESS_EVAL
:
1300 if (sctx
->gs_shader
.cso
)
1303 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1305 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1306 key
->mono
.u
.vs_export_prim_id
= 1;
1309 case PIPE_SHADER_GEOMETRY
:
1310 if (sctx
->b
.chip_class
>= GFX9
) {
1311 if (sctx
->tes_shader
.cso
) {
1312 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1314 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1315 key
, &key
->part
.gs
.vs_prolog
);
1316 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1317 key
->part
.gs
.prolog
.gfx9_prev_is_vs
= 1;
1320 /* Merged ES-GS can have unbalanced wave usage.
1322 * ES threads are per-vertex, while GS threads are
1323 * per-primitive. So without any amplification, there
1324 * are fewer GS threads than ES threads, which can result
1325 * in empty (no-op) GS waves. With too much amplification,
1326 * there are more GS threads than ES threads, which
1327 * can result in empty (no-op) ES waves.
1329 * Non-monolithic shaders are implemented by setting EXEC
1330 * at the beginning of shader parts, and don't jump to
1331 * the end if EXEC is 0.
1333 * Monolithic shaders use conditional blocks, so they can
1334 * jump and skip empty waves of ES or GS. So set this to
1335 * always use optimized variants, which are monolithic.
1337 key
->opt
.prefer_mono
= 1;
1339 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1341 case PIPE_SHADER_FRAGMENT
: {
1342 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1343 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1345 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1346 sel
->info
.colors_written
== 0x1)
1347 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1350 /* Select the shader color format based on whether
1351 * blending or alpha are needed.
1353 key
->part
.ps
.epilog
.spi_shader_col_format
=
1354 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1355 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1356 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1357 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1358 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1359 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1360 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1361 sctx
->framebuffer
.spi_shader_col_format
);
1362 key
->part
.ps
.epilog
.spi_shader_col_format
&= blend
->cb_target_enabled_4bit
;
1364 /* The output for dual source blending should have
1365 * the same format as the first output.
1367 if (blend
->dual_src_blend
)
1368 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1369 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1371 key
->part
.ps
.epilog
.spi_shader_col_format
= sctx
->framebuffer
.spi_shader_col_format
;
1373 /* If alpha-to-coverage is enabled, we have to export alpha
1374 * even if there is no color buffer.
1376 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1377 blend
&& blend
->alpha_to_coverage
)
1378 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1380 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1381 * to the range supported by the type if a channel has less
1382 * than 16 bits and the export format is 16_ABGR.
1384 if (sctx
->b
.chip_class
<= CIK
&& sctx
->b
.family
!= CHIP_HAWAII
) {
1385 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1386 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1389 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1390 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1391 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1392 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1393 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1397 bool is_poly
= (sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES
&&
1398 sctx
->current_rast_prim
<= PIPE_PRIM_POLYGON
) ||
1399 sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES_ADJACENCY
;
1400 bool is_line
= !is_poly
&& sctx
->current_rast_prim
!= PIPE_PRIM_POINTS
;
1402 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1403 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1405 if (sctx
->queued
.named
.blend
) {
1406 key
->part
.ps
.epilog
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
1407 rs
->multisample_enable
;
1410 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1411 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1412 (is_line
&& rs
->line_smooth
)) &&
1413 sctx
->framebuffer
.nr_samples
<= 1;
1414 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1416 if (sctx
->ps_iter_samples
> 1 &&
1417 sel
->info
.reads_samplemask
) {
1418 key
->part
.ps
.prolog
.samplemask_log_ps_iter
=
1419 util_logbase2(util_next_power_of_two(sctx
->ps_iter_samples
));
1422 if (rs
->force_persample_interp
&&
1423 rs
->multisample_enable
&&
1424 sctx
->framebuffer
.nr_samples
> 1 &&
1425 sctx
->ps_iter_samples
> 1) {
1426 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1427 sel
->info
.uses_persp_center
||
1428 sel
->info
.uses_persp_centroid
;
1430 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1431 sel
->info
.uses_linear_center
||
1432 sel
->info
.uses_linear_centroid
;
1433 } else if (rs
->multisample_enable
&&
1434 sctx
->framebuffer
.nr_samples
> 1) {
1435 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
1436 sel
->info
.uses_persp_center
&&
1437 sel
->info
.uses_persp_centroid
;
1438 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
1439 sel
->info
.uses_linear_center
&&
1440 sel
->info
.uses_linear_centroid
;
1442 /* Make sure SPI doesn't compute more than 1 pair
1443 * of (i,j), which is the optimization here. */
1444 key
->part
.ps
.prolog
.force_persp_center_interp
=
1445 sel
->info
.uses_persp_center
+
1446 sel
->info
.uses_persp_centroid
+
1447 sel
->info
.uses_persp_sample
> 1;
1449 key
->part
.ps
.prolog
.force_linear_center_interp
=
1450 sel
->info
.uses_linear_center
+
1451 sel
->info
.uses_linear_centroid
+
1452 sel
->info
.uses_linear_sample
> 1;
1454 if (sel
->info
.opcode_count
[TGSI_OPCODE_INTERP_SAMPLE
])
1455 key
->mono
.u
.ps
.interpolate_at_sample_force_center
= 1;
1459 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
1461 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1462 if (sctx
->ps_uses_fbfetch
) {
1463 struct pipe_surface
*cb0
= sctx
->framebuffer
.state
.cbufs
[0];
1464 struct pipe_resource
*tex
= cb0
->texture
;
1466 /* 1D textures are allocated and used as 2D on GFX9. */
1467 key
->mono
.u
.ps
.fbfetch_msaa
= sctx
->framebuffer
.nr_samples
> 1;
1468 key
->mono
.u
.ps
.fbfetch_is_1D
= sctx
->b
.chip_class
!= GFX9
&&
1469 (tex
->target
== PIPE_TEXTURE_1D
||
1470 tex
->target
== PIPE_TEXTURE_1D_ARRAY
);
1471 key
->mono
.u
.ps
.fbfetch_layered
= tex
->target
== PIPE_TEXTURE_1D_ARRAY
||
1472 tex
->target
== PIPE_TEXTURE_2D_ARRAY
||
1473 tex
->target
== PIPE_TEXTURE_CUBE
||
1474 tex
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
1475 tex
->target
== PIPE_TEXTURE_3D
;
1483 if (unlikely(sctx
->screen
->debug_flags
& DBG(NO_OPT_VARIANT
)))
1484 memset(&key
->opt
, 0, sizeof(key
->opt
));
1487 static void si_build_shader_variant(struct si_shader
*shader
,
1491 struct si_shader_selector
*sel
= shader
->selector
;
1492 struct si_screen
*sscreen
= sel
->screen
;
1493 LLVMTargetMachineRef tm
;
1494 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
1497 if (thread_index
>= 0) {
1499 assert(thread_index
< ARRAY_SIZE(sscreen
->tm_low_priority
));
1500 tm
= sscreen
->tm_low_priority
[thread_index
];
1502 assert(thread_index
< ARRAY_SIZE(sscreen
->tm
));
1503 tm
= sscreen
->tm
[thread_index
];
1508 assert(!low_priority
);
1509 tm
= shader
->compiler_ctx_state
.tm
;
1512 r
= si_shader_create(sscreen
, tm
, shader
, debug
);
1514 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1516 shader
->compilation_failed
= true;
1520 if (shader
->compiler_ctx_state
.is_debug_context
) {
1521 FILE *f
= open_memstream(&shader
->shader_log
,
1522 &shader
->shader_log_size
);
1524 si_shader_dump(sscreen
, shader
, NULL
, sel
->type
, f
, false);
1529 si_shader_init_pm4_state(sscreen
, shader
);
1532 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
1534 struct si_shader
*shader
= (struct si_shader
*)job
;
1536 assert(thread_index
>= 0);
1538 si_build_shader_variant(shader
, thread_index
, true);
1541 static const struct si_shader_key zeroed
;
1543 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
1544 struct si_shader_selector
*sel
,
1545 struct si_compiler_ctx_state
*compiler_state
,
1546 struct si_shader_key
*key
)
1548 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
1551 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
1556 /* We can leave the fence as permanently signaled because the
1557 * main part becomes visible globally only after it has been
1559 util_queue_fence_init(&main_part
->ready
);
1561 main_part
->selector
= sel
;
1562 main_part
->key
.as_es
= key
->as_es
;
1563 main_part
->key
.as_ls
= key
->as_ls
;
1565 if (si_compile_tgsi_shader(sscreen
, compiler_state
->tm
,
1567 &compiler_state
->debug
) != 0) {
1576 /* Select the hw shader variant depending on the current state. */
1577 static int si_shader_select_with_key(struct si_screen
*sscreen
,
1578 struct si_shader_ctx_state
*state
,
1579 struct si_compiler_ctx_state
*compiler_state
,
1580 struct si_shader_key
*key
,
1583 struct si_shader_selector
*sel
= state
->cso
;
1584 struct si_shader_selector
*previous_stage_sel
= NULL
;
1585 struct si_shader
*current
= state
->current
;
1586 struct si_shader
*iter
, *shader
= NULL
;
1589 /* Check if we don't need to change anything.
1590 * This path is also used for most shaders that don't need multiple
1591 * variants, it will cost just a computation of the key and this
1593 if (likely(current
&&
1594 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0)) {
1595 if (unlikely(!util_queue_fence_is_signalled(¤t
->ready
))) {
1596 if (current
->is_optimized
) {
1597 memset(&key
->opt
, 0, sizeof(key
->opt
));
1598 goto current_not_ready
;
1601 util_queue_fence_wait(¤t
->ready
);
1604 return current
->compilation_failed
? -1 : 0;
1608 /* This must be done before the mutex is locked, because async GS
1609 * compilation calls this function too, and therefore must enter
1612 * Only wait if we are in a draw call. Don't wait if we are
1613 * in a compiler thread.
1615 if (thread_index
< 0)
1616 util_queue_fence_wait(&sel
->ready
);
1618 mtx_lock(&sel
->mutex
);
1620 /* Find the shader variant. */
1621 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
1622 /* Don't check the "current" shader. We checked it above. */
1623 if (current
!= iter
&&
1624 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
1625 mtx_unlock(&sel
->mutex
);
1627 if (unlikely(!util_queue_fence_is_signalled(&iter
->ready
))) {
1628 /* If it's an optimized shader and its compilation has
1629 * been started but isn't done, use the unoptimized
1630 * shader so as not to cause a stall due to compilation.
1632 if (iter
->is_optimized
) {
1633 memset(&key
->opt
, 0, sizeof(key
->opt
));
1637 util_queue_fence_wait(&iter
->ready
);
1640 if (iter
->compilation_failed
) {
1641 return -1; /* skip the draw call */
1644 state
->current
= iter
;
1649 /* Build a new shader. */
1650 shader
= CALLOC_STRUCT(si_shader
);
1652 mtx_unlock(&sel
->mutex
);
1656 util_queue_fence_init(&shader
->ready
);
1658 shader
->selector
= sel
;
1660 shader
->compiler_ctx_state
= *compiler_state
;
1662 /* If this is a merged shader, get the first shader's selector. */
1663 if (sscreen
->info
.chip_class
>= GFX9
) {
1664 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1665 previous_stage_sel
= key
->part
.tcs
.ls
;
1666 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1667 previous_stage_sel
= key
->part
.gs
.es
;
1669 /* We need to wait for the previous shader. */
1670 if (previous_stage_sel
&& thread_index
< 0)
1671 util_queue_fence_wait(&previous_stage_sel
->ready
);
1674 /* Compile the main shader part if it doesn't exist. This can happen
1675 * if the initial guess was wrong. */
1676 bool is_pure_monolithic
=
1677 sscreen
->use_monolithic_shaders
||
1678 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
1680 if (!is_pure_monolithic
) {
1683 /* Make sure the main shader part is present. This is needed
1684 * for shaders that can be compiled as VS, LS, or ES, and only
1685 * one of them is compiled at creation.
1687 * For merged shaders, check that the starting shader's main
1690 if (previous_stage_sel
) {
1691 struct si_shader_key shader1_key
= zeroed
;
1693 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1694 shader1_key
.as_ls
= 1;
1695 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1696 shader1_key
.as_es
= 1;
1700 mtx_lock(&previous_stage_sel
->mutex
);
1701 ok
= si_check_missing_main_part(sscreen
,
1703 compiler_state
, &shader1_key
);
1704 mtx_unlock(&previous_stage_sel
->mutex
);
1706 ok
= si_check_missing_main_part(sscreen
, sel
,
1707 compiler_state
, key
);
1711 mtx_unlock(&sel
->mutex
);
1712 return -ENOMEM
; /* skip the draw call */
1716 /* Keep the reference to the 1st shader of merged shaders, so that
1717 * Gallium can't destroy it before we destroy the 2nd shader.
1719 * Set sctx = NULL, because it's unused if we're not releasing
1720 * the shader, and we don't have any sctx here.
1722 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
1723 previous_stage_sel
);
1725 /* Monolithic-only shaders don't make a distinction between optimized
1726 * and unoptimized. */
1727 shader
->is_monolithic
=
1728 is_pure_monolithic
||
1729 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1731 shader
->is_optimized
=
1732 !is_pure_monolithic
&&
1733 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1735 /* If it's an optimized shader, compile it asynchronously. */
1736 if (shader
->is_optimized
&&
1737 !is_pure_monolithic
&&
1739 /* Compile it asynchronously. */
1740 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
,
1741 shader
, &shader
->ready
,
1742 si_build_shader_variant_low_priority
, NULL
);
1744 /* Add only after the ready fence was reset, to guard against a
1745 * race with si_bind_XX_shader. */
1746 if (!sel
->last_variant
) {
1747 sel
->first_variant
= shader
;
1748 sel
->last_variant
= shader
;
1750 sel
->last_variant
->next_variant
= shader
;
1751 sel
->last_variant
= shader
;
1754 /* Use the default (unoptimized) shader for now. */
1755 memset(&key
->opt
, 0, sizeof(key
->opt
));
1756 mtx_unlock(&sel
->mutex
);
1760 /* Reset the fence before adding to the variant list. */
1761 util_queue_fence_reset(&shader
->ready
);
1763 if (!sel
->last_variant
) {
1764 sel
->first_variant
= shader
;
1765 sel
->last_variant
= shader
;
1767 sel
->last_variant
->next_variant
= shader
;
1768 sel
->last_variant
= shader
;
1771 mtx_unlock(&sel
->mutex
);
1773 assert(!shader
->is_optimized
);
1774 si_build_shader_variant(shader
, thread_index
, false);
1776 util_queue_fence_signal(&shader
->ready
);
1778 if (!shader
->compilation_failed
)
1779 state
->current
= shader
;
1781 return shader
->compilation_failed
? -1 : 0;
1784 static int si_shader_select(struct pipe_context
*ctx
,
1785 struct si_shader_ctx_state
*state
,
1786 struct si_compiler_ctx_state
*compiler_state
)
1788 struct si_context
*sctx
= (struct si_context
*)ctx
;
1789 struct si_shader_key key
;
1791 si_shader_selector_key(ctx
, state
->cso
, &key
);
1792 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
1796 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
1798 struct si_shader_key
*key
)
1800 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
1802 switch (info
->processor
) {
1803 case PIPE_SHADER_VERTEX
:
1804 switch (next_shader
) {
1805 case PIPE_SHADER_GEOMETRY
:
1808 case PIPE_SHADER_TESS_CTRL
:
1809 case PIPE_SHADER_TESS_EVAL
:
1813 /* If POSITION isn't written, it can only be a HW VS
1814 * if streamout is used. If streamout isn't used,
1815 * assume that it's a HW LS. (the next shader is TCS)
1816 * This heuristic is needed for separate shader objects.
1818 if (!info
->writes_position
&& !streamout
)
1823 case PIPE_SHADER_TESS_EVAL
:
1824 if (next_shader
== PIPE_SHADER_GEOMETRY
||
1825 !info
->writes_position
)
1832 * Compile the main shader part or the monolithic shader as part of
1833 * si_shader_selector initialization. Since it can be done asynchronously,
1834 * there is no way to report compile failures to applications.
1836 static void si_init_shader_selector_async(void *job
, int thread_index
)
1838 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
1839 struct si_screen
*sscreen
= sel
->screen
;
1840 LLVMTargetMachineRef tm
;
1841 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
1843 assert(!debug
->debug_message
|| debug
->async
);
1844 assert(thread_index
>= 0);
1845 assert(thread_index
< ARRAY_SIZE(sscreen
->tm
));
1846 tm
= sscreen
->tm
[thread_index
];
1848 /* Compile the main shader part for use with a prolog and/or epilog.
1849 * If this fails, the driver will try to compile a monolithic shader
1852 if (!sscreen
->use_monolithic_shaders
) {
1853 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
1854 void *ir_binary
= NULL
;
1857 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
1861 /* We can leave the fence signaled because use of the default
1862 * main part is guarded by the selector's ready fence. */
1863 util_queue_fence_init(&shader
->ready
);
1865 shader
->selector
= sel
;
1866 si_parse_next_shader_property(&sel
->info
,
1867 sel
->so
.num_outputs
!= 0,
1870 if (sel
->tokens
|| sel
->nir
)
1871 ir_binary
= si_get_ir_binary(sel
);
1873 /* Try to load the shader from the shader cache. */
1874 mtx_lock(&sscreen
->shader_cache_mutex
);
1877 si_shader_cache_load_shader(sscreen
, ir_binary
, shader
)) {
1878 mtx_unlock(&sscreen
->shader_cache_mutex
);
1879 si_shader_dump_stats_for_shader_db(shader
, debug
);
1881 mtx_unlock(&sscreen
->shader_cache_mutex
);
1883 /* Compile the shader if it hasn't been loaded from the cache. */
1884 if (si_compile_tgsi_shader(sscreen
, tm
, shader
, false,
1888 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
1893 mtx_lock(&sscreen
->shader_cache_mutex
);
1894 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
, shader
, true))
1896 mtx_unlock(&sscreen
->shader_cache_mutex
);
1900 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
1902 /* Unset "outputs_written" flags for outputs converted to
1903 * DEFAULT_VAL, so that later inter-shader optimizations don't
1904 * try to eliminate outputs that don't exist in the final
1907 * This is only done if non-monolithic shaders are enabled.
1909 if ((sel
->type
== PIPE_SHADER_VERTEX
||
1910 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
1911 !shader
->key
.as_ls
&&
1912 !shader
->key
.as_es
) {
1915 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
1916 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
1918 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
1921 unsigned name
= sel
->info
.output_semantic_name
[i
];
1922 unsigned index
= sel
->info
.output_semantic_index
[i
];
1926 case TGSI_SEMANTIC_GENERIC
:
1927 /* don't process indices the function can't handle */
1928 if (index
>= SI_MAX_IO_GENERIC
)
1932 id
= si_shader_io_get_unique_index(name
, index
);
1933 sel
->outputs_written
&= ~(1ull << id
);
1935 case TGSI_SEMANTIC_POSITION
: /* ignore these */
1936 case TGSI_SEMANTIC_PSIZE
:
1937 case TGSI_SEMANTIC_CLIPVERTEX
:
1938 case TGSI_SEMANTIC_EDGEFLAG
:
1945 /* The GS copy shader is always pre-compiled. */
1946 if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
1947 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, tm
, sel
, debug
);
1948 if (!sel
->gs_copy_shader
) {
1949 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
1953 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
1957 /* Return descriptor slot usage masks from the given shader info. */
1958 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
1959 uint32_t *const_and_shader_buffers
,
1960 uint64_t *samplers_and_images
)
1962 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_samplers
;
1964 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
1965 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
1966 /* two 8-byte images share one 16-byte slot */
1967 num_images
= align(util_last_bit(info
->images_declared
), 2);
1968 num_samplers
= util_last_bit(info
->samplers_declared
);
1970 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
1971 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
1972 *const_and_shader_buffers
=
1973 u_bit_consecutive(start
, num_shaderbufs
+ num_constbufs
);
1975 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
1976 start
= si_get_image_slot(num_images
- 1) / 2;
1977 *samplers_and_images
=
1978 u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
1981 static void *si_create_shader_selector(struct pipe_context
*ctx
,
1982 const struct pipe_shader_state
*state
)
1984 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
1985 struct si_context
*sctx
= (struct si_context
*)ctx
;
1986 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
1992 pipe_reference_init(&sel
->reference
, 1);
1993 sel
->screen
= sscreen
;
1994 sel
->compiler_ctx_state
.debug
= sctx
->debug
;
1995 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
1997 sel
->so
= state
->stream_output
;
1999 if (state
->type
== PIPE_SHADER_IR_TGSI
) {
2000 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
2006 tgsi_scan_shader(state
->tokens
, &sel
->info
);
2007 tgsi_scan_tess_ctrl(state
->tokens
, &sel
->info
, &sel
->tcs_info
);
2009 assert(state
->type
== PIPE_SHADER_IR_NIR
);
2011 sel
->nir
= state
->ir
.nir
;
2013 si_nir_scan_shader(sel
->nir
, &sel
->info
);
2014 si_nir_scan_tess_ctrl(sel
->nir
, &sel
->info
, &sel
->tcs_info
);
2019 sel
->type
= sel
->info
.processor
;
2020 p_atomic_inc(&sscreen
->num_shaders_created
);
2021 si_get_active_slot_masks(&sel
->info
,
2022 &sel
->active_const_and_shader_buffers
,
2023 &sel
->active_samplers_and_images
);
2025 /* Record which streamout buffers are enabled. */
2026 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
2027 sel
->enabled_streamout_buffer_mask
|=
2028 (1 << sel
->so
.output
[i
].output_buffer
) <<
2029 (sel
->so
.output
[i
].stream
* 4);
2032 /* The prolog is a no-op if there are no inputs. */
2033 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
2034 sel
->info
.num_inputs
&&
2035 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
2037 sel
->force_correct_derivs_after_kill
=
2038 sel
->type
== PIPE_SHADER_FRAGMENT
&&
2039 sel
->info
.uses_derivatives
&&
2040 sel
->info
.uses_kill
&&
2041 sctx
->screen
->debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
2043 /* Set which opcode uses which (i,j) pair. */
2044 if (sel
->info
.uses_persp_opcode_interp_centroid
)
2045 sel
->info
.uses_persp_centroid
= true;
2047 if (sel
->info
.uses_linear_opcode_interp_centroid
)
2048 sel
->info
.uses_linear_centroid
= true;
2050 if (sel
->info
.uses_persp_opcode_interp_offset
||
2051 sel
->info
.uses_persp_opcode_interp_sample
)
2052 sel
->info
.uses_persp_center
= true;
2054 if (sel
->info
.uses_linear_opcode_interp_offset
||
2055 sel
->info
.uses_linear_opcode_interp_sample
)
2056 sel
->info
.uses_linear_center
= true;
2058 switch (sel
->type
) {
2059 case PIPE_SHADER_GEOMETRY
:
2060 sel
->gs_output_prim
=
2061 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
2062 sel
->gs_max_out_vertices
=
2063 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
2064 sel
->gs_num_invocations
=
2065 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2066 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2067 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
2068 sel
->gs_max_out_vertices
;
2070 sel
->max_gs_stream
= 0;
2071 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2072 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
2073 sel
->so
.output
[i
].stream
);
2075 sel
->gs_input_verts_per_prim
=
2076 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2079 case PIPE_SHADER_TESS_CTRL
:
2080 /* Always reserve space for these. */
2081 sel
->patch_outputs_written
|=
2082 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0)) |
2083 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0));
2085 case PIPE_SHADER_VERTEX
:
2086 case PIPE_SHADER_TESS_EVAL
:
2087 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2088 unsigned name
= sel
->info
.output_semantic_name
[i
];
2089 unsigned index
= sel
->info
.output_semantic_index
[i
];
2092 case TGSI_SEMANTIC_TESSINNER
:
2093 case TGSI_SEMANTIC_TESSOUTER
:
2094 case TGSI_SEMANTIC_PATCH
:
2095 sel
->patch_outputs_written
|=
2096 1ull << si_shader_io_get_unique_index_patch(name
, index
);
2099 case TGSI_SEMANTIC_GENERIC
:
2100 /* don't process indices the function can't handle */
2101 if (index
>= SI_MAX_IO_GENERIC
)
2105 sel
->outputs_written
|=
2106 1ull << si_shader_io_get_unique_index(name
, index
);
2108 case TGSI_SEMANTIC_CLIPVERTEX
: /* ignore these */
2109 case TGSI_SEMANTIC_EDGEFLAG
:
2113 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2115 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2116 * conflicts, i.e. each vertex will start at a different bank.
2118 if (sctx
->b
.chip_class
>= GFX9
)
2119 sel
->esgs_itemsize
+= 4;
2122 case PIPE_SHADER_FRAGMENT
:
2123 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2124 unsigned name
= sel
->info
.input_semantic_name
[i
];
2125 unsigned index
= sel
->info
.input_semantic_index
[i
];
2128 case TGSI_SEMANTIC_GENERIC
:
2129 /* don't process indices the function can't handle */
2130 if (index
>= SI_MAX_IO_GENERIC
)
2135 1ull << si_shader_io_get_unique_index(name
, index
);
2137 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2142 for (i
= 0; i
< 8; i
++)
2143 if (sel
->info
.colors_written
& (1 << i
))
2144 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2146 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2147 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2148 int index
= sel
->info
.input_semantic_index
[i
];
2149 sel
->color_attr_index
[index
] = i
;
2155 /* PA_CL_VS_OUT_CNTL */
2157 sel
->info
.writes_psize
|| sel
->info
.writes_edgeflag
||
2158 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
2159 sel
->pa_cl_vs_out_cntl
=
2160 S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
2161 S_02881C_USE_VTX_EDGE_FLAG(sel
->info
.writes_edgeflag
) |
2162 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
2163 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
2164 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
2165 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
2166 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
?
2167 SIX_BITS
: sel
->info
.clipdist_writemask
;
2168 sel
->culldist_mask
= sel
->info
.culldist_writemask
<<
2169 sel
->info
.num_written_clipdistance
;
2171 /* DB_SHADER_CONTROL */
2172 sel
->db_shader_control
=
2173 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2174 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2175 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2176 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2178 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2179 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2180 sel
->db_shader_control
|=
2181 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2183 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2184 sel
->db_shader_control
|=
2185 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2189 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2191 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2192 * --|-----------|------------|------------|--------------------|-------------------|-------------
2193 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2194 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2195 * 2 | false | true | n/a | LateZ | 1 | 0
2196 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2197 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2199 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2200 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2202 * Don't use ReZ without profiling !!!
2204 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2207 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2209 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2210 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2211 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
2212 } else if (sel
->info
.writes_memory
) {
2214 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
2215 S_02880C_EXEC_ON_HIER_FAIL(1);
2218 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2221 (void) mtx_init(&sel
->mutex
, mtx_plain
);
2222 util_queue_fence_init(&sel
->ready
);
2224 struct util_async_debug_callback async_debug
;
2226 (sctx
->debug
.debug_message
&& !sctx
->debug
.async
) ||
2228 si_can_dump_shader(sscreen
, sel
->info
.processor
);
2231 u_async_debug_init(&async_debug
);
2232 sel
->compiler_ctx_state
.debug
= async_debug
.base
;
2235 util_queue_add_job(&sscreen
->shader_compiler_queue
, sel
,
2236 &sel
->ready
, si_init_shader_selector_async
,
2240 util_queue_fence_wait(&sel
->ready
);
2241 u_async_debug_drain(&async_debug
, &sctx
->debug
);
2242 u_async_debug_cleanup(&async_debug
);
2248 static void si_update_streamout_state(struct si_context
*sctx
)
2250 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
2252 if (!shader_with_so
)
2255 sctx
->streamout
.enabled_stream_buffers_mask
=
2256 shader_with_so
->enabled_streamout_buffer_mask
;
2257 sctx
->streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
2260 static void si_update_clip_regs(struct si_context
*sctx
,
2261 struct si_shader_selector
*old_hw_vs
,
2262 struct si_shader
*old_hw_vs_variant
,
2263 struct si_shader_selector
*next_hw_vs
,
2264 struct si_shader
*next_hw_vs_variant
)
2268 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
2269 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
2270 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
2271 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
2272 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
||
2273 !old_hw_vs_variant
||
2274 !next_hw_vs_variant
||
2275 old_hw_vs_variant
->key
.opt
.clip_disable
!=
2276 next_hw_vs_variant
->key
.opt
.clip_disable
))
2277 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
2280 static void si_update_common_shader_state(struct si_context
*sctx
)
2282 sctx
->uses_bindless_samplers
=
2283 si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
2284 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
2285 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
2286 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
2287 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
2288 sctx
->uses_bindless_images
=
2289 si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
2290 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
2291 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
2292 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
2293 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
2294 sctx
->do_update_shaders
= true;
2297 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2299 struct si_context
*sctx
= (struct si_context
*)ctx
;
2300 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2301 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2302 struct si_shader_selector
*sel
= state
;
2304 if (sctx
->vs_shader
.cso
== sel
)
2307 sctx
->vs_shader
.cso
= sel
;
2308 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2309 sctx
->num_vs_blit_sgprs
= sel
? sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
] : 0;
2311 si_update_common_shader_state(sctx
);
2312 si_update_vs_viewport_state(sctx
);
2313 si_set_active_descriptors_for_shader(sctx
, sel
);
2314 si_update_streamout_state(sctx
);
2315 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2316 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2319 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
2321 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
2322 (sctx
->tes_shader
.cso
&&
2323 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
2324 (sctx
->tcs_shader
.cso
&&
2325 sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
2326 (sctx
->gs_shader
.cso
&&
2327 sctx
->gs_shader
.cso
->info
.uses_primid
) ||
2328 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&&
2329 sctx
->ps_shader
.cso
->info
.uses_primid
);
2332 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
2334 struct si_context
*sctx
= (struct si_context
*)ctx
;
2335 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2336 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2337 struct si_shader_selector
*sel
= state
;
2338 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
2340 if (sctx
->gs_shader
.cso
== sel
)
2343 sctx
->gs_shader
.cso
= sel
;
2344 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2345 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
2347 si_update_common_shader_state(sctx
);
2348 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2350 if (enable_changed
) {
2351 si_shader_change_notify(sctx
);
2352 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2353 si_update_tess_uses_prim_id(sctx
);
2355 si_update_vs_viewport_state(sctx
);
2356 si_set_active_descriptors_for_shader(sctx
, sel
);
2357 si_update_streamout_state(sctx
);
2358 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2359 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2362 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
2364 struct si_context
*sctx
= (struct si_context
*)ctx
;
2365 struct si_shader_selector
*sel
= state
;
2366 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
2368 if (sctx
->tcs_shader
.cso
== sel
)
2371 sctx
->tcs_shader
.cso
= sel
;
2372 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2373 si_update_tess_uses_prim_id(sctx
);
2375 si_update_common_shader_state(sctx
);
2378 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
2380 si_set_active_descriptors_for_shader(sctx
, sel
);
2383 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
2385 struct si_context
*sctx
= (struct si_context
*)ctx
;
2386 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2387 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2388 struct si_shader_selector
*sel
= state
;
2389 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
2391 if (sctx
->tes_shader
.cso
== sel
)
2394 sctx
->tes_shader
.cso
= sel
;
2395 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
2396 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
2397 si_update_tess_uses_prim_id(sctx
);
2399 si_update_common_shader_state(sctx
);
2400 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2402 if (enable_changed
) {
2403 si_shader_change_notify(sctx
);
2404 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
2406 si_update_vs_viewport_state(sctx
);
2407 si_set_active_descriptors_for_shader(sctx
, sel
);
2408 si_update_streamout_state(sctx
);
2409 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2410 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2413 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
2415 struct si_context
*sctx
= (struct si_context
*)ctx
;
2416 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
2417 struct si_shader_selector
*sel
= state
;
2419 /* skip if supplied shader is one already in use */
2423 sctx
->ps_shader
.cso
= sel
;
2424 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
2426 si_update_common_shader_state(sctx
);
2428 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2429 si_update_tess_uses_prim_id(sctx
);
2432 old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
2433 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
2435 if (sctx
->screen
->has_out_of_order_rast
&&
2437 old_sel
->info
.writes_memory
!= sel
->info
.writes_memory
||
2438 old_sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] !=
2439 sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]))
2440 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2442 si_set_active_descriptors_for_shader(sctx
, sel
);
2443 si_update_ps_colorbuf0_slot(sctx
);
2446 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
2448 if (shader
->is_optimized
) {
2449 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
,
2453 util_queue_fence_destroy(&shader
->ready
);
2456 switch (shader
->selector
->type
) {
2457 case PIPE_SHADER_VERTEX
:
2458 if (shader
->key
.as_ls
) {
2459 assert(sctx
->b
.chip_class
<= VI
);
2460 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
2461 } else if (shader
->key
.as_es
) {
2462 assert(sctx
->b
.chip_class
<= VI
);
2463 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2465 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2468 case PIPE_SHADER_TESS_CTRL
:
2469 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
2471 case PIPE_SHADER_TESS_EVAL
:
2472 if (shader
->key
.as_es
) {
2473 assert(sctx
->b
.chip_class
<= VI
);
2474 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2476 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2479 case PIPE_SHADER_GEOMETRY
:
2480 if (shader
->is_gs_copy_shader
)
2481 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2483 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
2485 case PIPE_SHADER_FRAGMENT
:
2486 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
2491 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
2492 si_shader_destroy(shader
);
2496 void si_destroy_shader_selector(struct si_context
*sctx
,
2497 struct si_shader_selector
*sel
)
2499 struct si_shader
*p
= sel
->first_variant
, *c
;
2500 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
2501 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
2502 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
2503 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
2504 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
2505 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
2508 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
2510 if (current_shader
[sel
->type
]->cso
== sel
) {
2511 current_shader
[sel
->type
]->cso
= NULL
;
2512 current_shader
[sel
->type
]->current
= NULL
;
2516 c
= p
->next_variant
;
2517 si_delete_shader(sctx
, p
);
2521 if (sel
->main_shader_part
)
2522 si_delete_shader(sctx
, sel
->main_shader_part
);
2523 if (sel
->main_shader_part_ls
)
2524 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
2525 if (sel
->main_shader_part_es
)
2526 si_delete_shader(sctx
, sel
->main_shader_part_es
);
2527 if (sel
->gs_copy_shader
)
2528 si_delete_shader(sctx
, sel
->gs_copy_shader
);
2530 util_queue_fence_destroy(&sel
->ready
);
2531 mtx_destroy(&sel
->mutex
);
2533 ralloc_free(sel
->nir
);
2537 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
2539 struct si_context
*sctx
= (struct si_context
*)ctx
;
2540 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
2542 si_shader_selector_reference(sctx
, &sel
, NULL
);
2545 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
2546 struct si_shader
*vs
, unsigned name
,
2547 unsigned index
, unsigned interpolate
)
2549 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
2550 unsigned j
, offset
, ps_input_cntl
= 0;
2552 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2553 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
))
2554 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
2556 if (name
== TGSI_SEMANTIC_PCOORD
||
2557 (name
== TGSI_SEMANTIC_TEXCOORD
&&
2558 sctx
->sprite_coord_enable
& (1 << index
))) {
2559 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
2562 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
2563 if (name
== vsinfo
->output_semantic_name
[j
] &&
2564 index
== vsinfo
->output_semantic_index
[j
]) {
2565 offset
= vs
->info
.vs_output_param_offset
[j
];
2567 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
2568 /* The input is loaded from parameter memory. */
2569 ps_input_cntl
|= S_028644_OFFSET(offset
);
2570 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2571 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
2572 /* This can happen with depth-only rendering. */
2575 /* The input is a DEFAULT_VAL constant. */
2576 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
2577 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
2578 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
2581 ps_input_cntl
= S_028644_OFFSET(0x20) |
2582 S_028644_DEFAULT_VAL(offset
);
2588 if (name
== TGSI_SEMANTIC_PRIMID
)
2589 /* PrimID is written after the last output. */
2590 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
2591 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2592 /* No corresponding output found, load defaults into input.
2593 * Don't set any other bits.
2594 * (FLAT_SHADE=1 completely changes behavior) */
2595 ps_input_cntl
= S_028644_OFFSET(0x20);
2596 /* D3D 9 behaviour. GL is undefined */
2597 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
2598 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
2600 return ps_input_cntl
;
2603 static void si_emit_spi_map(struct si_context
*sctx
, struct r600_atom
*atom
)
2605 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
2606 struct si_shader
*ps
= sctx
->ps_shader
.current
;
2607 struct si_shader
*vs
= si_get_vs_state(sctx
);
2608 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
2609 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
2611 if (!ps
|| !ps
->selector
->info
.num_inputs
)
2614 num_interp
= si_get_ps_num_interp(ps
);
2615 assert(num_interp
> 0);
2616 radeon_set_context_reg_seq(cs
, R_028644_SPI_PS_INPUT_CNTL_0
, num_interp
);
2618 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
2619 unsigned name
= psinfo
->input_semantic_name
[i
];
2620 unsigned index
= psinfo
->input_semantic_index
[i
];
2621 unsigned interpolate
= psinfo
->input_interpolate
[i
];
2623 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, name
, index
,
2627 if (name
== TGSI_SEMANTIC_COLOR
) {
2628 assert(index
< ARRAY_SIZE(bcol_interp
));
2629 bcol_interp
[index
] = interpolate
;
2633 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
2634 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
2636 for (i
= 0; i
< 2; i
++) {
2637 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
2640 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, bcol
,
2641 i
, bcol_interp
[i
]));
2645 assert(num_interp
== num_written
);
2649 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2651 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
2653 if (sctx
->init_config_has_vgt_flush
)
2656 /* Done by Vulkan before VGT_FLUSH. */
2657 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2658 si_pm4_cmd_add(sctx
->init_config
,
2659 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2660 si_pm4_cmd_end(sctx
->init_config
, false);
2662 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2663 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2664 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2665 si_pm4_cmd_end(sctx
->init_config
, false);
2666 sctx
->init_config_has_vgt_flush
= true;
2669 /* Initialize state related to ESGS / GSVS ring buffers */
2670 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
2672 struct si_shader_selector
*es
=
2673 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
2674 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
2675 struct si_pm4_state
*pm4
;
2677 /* Chip constants. */
2678 unsigned num_se
= sctx
->screen
->info
.max_se
;
2679 unsigned wave_size
= 64;
2680 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
2681 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2682 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2684 unsigned gs_vertex_reuse
= (sctx
->b
.chip_class
>= VI
? 32 : 16) * num_se
;
2685 unsigned alignment
= 256 * num_se
;
2686 /* The maximum size is 63.999 MB per SE. */
2687 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
2689 /* Calculate the minimum size. */
2690 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
2691 wave_size
, alignment
);
2693 /* These are recommended sizes, not minimum sizes. */
2694 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
2695 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
2696 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
2697 gs
->max_gsvs_emit_size
;
2699 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
2700 esgs_ring_size
= align(esgs_ring_size
, alignment
);
2701 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
2703 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
2704 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
2706 /* Some rings don't have to be allocated if shaders don't use them.
2707 * (e.g. no varyings between ES and GS or GS and VS)
2709 * GFX9 doesn't have the ESGS ring.
2711 bool update_esgs
= sctx
->b
.chip_class
<= VI
&&
2713 (!sctx
->esgs_ring
||
2714 sctx
->esgs_ring
->width0
< esgs_ring_size
);
2715 bool update_gsvs
= gsvs_ring_size
&&
2716 (!sctx
->gsvs_ring
||
2717 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
2719 if (!update_esgs
&& !update_gsvs
)
2723 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
2725 si_aligned_buffer_create(sctx
->b
.b
.screen
,
2726 SI_RESOURCE_FLAG_UNMAPPABLE
,
2728 esgs_ring_size
, alignment
);
2729 if (!sctx
->esgs_ring
)
2734 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
2736 si_aligned_buffer_create(sctx
->b
.b
.screen
,
2737 SI_RESOURCE_FLAG_UNMAPPABLE
,
2739 gsvs_ring_size
, alignment
);
2740 if (!sctx
->gsvs_ring
)
2744 /* Create the "init_config_gs_rings" state. */
2745 pm4
= CALLOC_STRUCT(si_pm4_state
);
2749 if (sctx
->b
.chip_class
>= CIK
) {
2750 if (sctx
->esgs_ring
) {
2751 assert(sctx
->b
.chip_class
<= VI
);
2752 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
2753 sctx
->esgs_ring
->width0
/ 256);
2755 if (sctx
->gsvs_ring
)
2756 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
2757 sctx
->gsvs_ring
->width0
/ 256);
2759 if (sctx
->esgs_ring
)
2760 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
2761 sctx
->esgs_ring
->width0
/ 256);
2762 if (sctx
->gsvs_ring
)
2763 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
2764 sctx
->gsvs_ring
->width0
/ 256);
2767 /* Set the state. */
2768 if (sctx
->init_config_gs_rings
)
2769 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
2770 sctx
->init_config_gs_rings
= pm4
;
2772 if (!sctx
->init_config_has_vgt_flush
) {
2773 si_init_config_add_vgt_flush(sctx
);
2774 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
2777 /* Flush the context to re-emit both init_config states. */
2778 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
2779 si_flush_gfx_cs(sctx
, PIPE_FLUSH_ASYNC
, NULL
);
2781 /* Set ring bindings. */
2782 if (sctx
->esgs_ring
) {
2783 assert(sctx
->b
.chip_class
<= VI
);
2784 si_set_ring_buffer(sctx
, SI_ES_RING_ESGS
,
2785 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2786 true, true, 4, 64, 0);
2787 si_set_ring_buffer(sctx
, SI_GS_RING_ESGS
,
2788 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2789 false, false, 0, 0, 0);
2791 if (sctx
->gsvs_ring
) {
2792 si_set_ring_buffer(sctx
, SI_RING_GSVS
,
2793 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
2794 false, false, 0, 0, 0);
2800 static void si_shader_lock(struct si_shader
*shader
)
2802 mtx_lock(&shader
->selector
->mutex
);
2803 if (shader
->previous_stage_sel
) {
2804 assert(shader
->previous_stage_sel
!= shader
->selector
);
2805 mtx_lock(&shader
->previous_stage_sel
->mutex
);
2809 static void si_shader_unlock(struct si_shader
*shader
)
2811 if (shader
->previous_stage_sel
)
2812 mtx_unlock(&shader
->previous_stage_sel
->mutex
);
2813 mtx_unlock(&shader
->selector
->mutex
);
2817 * @returns 1 if \p sel has been updated to use a new scratch buffer
2819 * < 0 if there was a failure
2821 static int si_update_scratch_buffer(struct si_context
*sctx
,
2822 struct si_shader
*shader
)
2824 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
2830 /* This shader doesn't need a scratch buffer */
2831 if (shader
->config
.scratch_bytes_per_wave
== 0)
2834 /* Prevent race conditions when updating:
2835 * - si_shader::scratch_bo
2836 * - si_shader::binary::code
2837 * - si_shader::previous_stage::binary::code.
2839 si_shader_lock(shader
);
2841 /* This shader is already configured to use the current
2842 * scratch buffer. */
2843 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
2844 si_shader_unlock(shader
);
2848 assert(sctx
->scratch_buffer
);
2850 if (shader
->previous_stage
)
2851 si_shader_apply_scratch_relocs(shader
->previous_stage
, scratch_va
);
2853 si_shader_apply_scratch_relocs(shader
, scratch_va
);
2855 /* Replace the shader bo with a new bo that has the relocs applied. */
2856 r
= si_shader_binary_upload(sctx
->screen
, shader
);
2858 si_shader_unlock(shader
);
2862 /* Update the shader state to use the new shader bo. */
2863 si_shader_init_pm4_state(sctx
->screen
, shader
);
2865 r600_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
2867 si_shader_unlock(shader
);
2871 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
2873 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
2876 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
2878 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
2881 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
2883 if (!sctx
->tes_shader
.cso
)
2884 return NULL
; /* tessellation disabled */
2886 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
:
2887 sctx
->fixed_func_tcs_shader
.current
;
2890 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
2894 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
2895 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
2896 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
2897 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
2899 if (sctx
->tes_shader
.cso
) {
2900 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
2902 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(tcs
));
2907 static bool si_update_scratch_relocs(struct si_context
*sctx
)
2909 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
2912 /* Update the shaders, so that they are using the latest scratch.
2913 * The scratch buffer may have been changed since these shaders were
2914 * last used, so we still need to try to update them, even if they
2915 * require scratch buffers smaller than the current size.
2917 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
2921 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
2923 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
2927 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
2929 r
= si_update_scratch_buffer(sctx
, tcs
);
2933 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
2935 /* VS can be bound as LS, ES, or VS. */
2936 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
2940 if (sctx
->tes_shader
.current
)
2941 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
2942 else if (sctx
->gs_shader
.current
)
2943 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
2945 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
2948 /* TES can be bound as ES or VS. */
2949 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
2953 if (sctx
->gs_shader
.current
)
2954 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
2956 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
2962 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
2964 unsigned current_scratch_buffer_size
=
2965 si_get_current_scratch_buffer_size(sctx
);
2966 unsigned scratch_bytes_per_wave
=
2967 si_get_max_scratch_bytes_per_wave(sctx
);
2968 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
2969 sctx
->scratch_waves
;
2970 unsigned spi_tmpring_size
;
2972 if (scratch_needed_size
> 0) {
2973 if (scratch_needed_size
> current_scratch_buffer_size
) {
2974 /* Create a bigger scratch buffer */
2975 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
2977 sctx
->scratch_buffer
= (struct r600_resource
*)
2978 si_aligned_buffer_create(&sctx
->screen
->b
,
2979 SI_RESOURCE_FLAG_UNMAPPABLE
,
2981 scratch_needed_size
, 256);
2982 if (!sctx
->scratch_buffer
)
2985 si_mark_atom_dirty(sctx
, &sctx
->scratch_state
);
2986 si_context_add_resource_size(sctx
,
2987 &sctx
->scratch_buffer
->b
.b
);
2990 if (!si_update_scratch_relocs(sctx
))
2994 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2995 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
2996 "scratch size should already be aligned correctly.");
2998 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
2999 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
3000 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
3001 sctx
->spi_tmpring_size
= spi_tmpring_size
;
3002 si_mark_atom_dirty(sctx
, &sctx
->scratch_state
);
3007 static void si_init_tess_factor_ring(struct si_context
*sctx
)
3009 assert(!sctx
->tess_rings
);
3011 /* The address must be aligned to 2^19, because the shader only
3012 * receives the high 13 bits.
3014 sctx
->tess_rings
= si_aligned_buffer_create(sctx
->b
.b
.screen
,
3015 SI_RESOURCE_FLAG_32BIT
,
3017 sctx
->screen
->tess_offchip_ring_size
+
3018 sctx
->screen
->tess_factor_ring_size
,
3020 if (!sctx
->tess_rings
)
3023 si_init_config_add_vgt_flush(sctx
);
3025 si_pm4_add_bo(sctx
->init_config
, r600_resource(sctx
->tess_rings
),
3026 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3028 uint64_t factor_va
= r600_resource(sctx
->tess_rings
)->gpu_address
+
3029 sctx
->screen
->tess_offchip_ring_size
;
3031 /* Append these registers to the init config state. */
3032 if (sctx
->b
.chip_class
>= CIK
) {
3033 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
3034 S_030938_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3035 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
3037 if (sctx
->b
.chip_class
>= GFX9
)
3038 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3039 S_030944_BASE_HI(factor_va
>> 40));
3040 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3041 sctx
->screen
->vgt_hs_offchip_param
);
3043 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
3044 S_008988_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3045 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
3047 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3048 sctx
->screen
->vgt_hs_offchip_param
);
3051 /* Flush the context to re-emit the init_config state.
3052 * This is done only once in a lifetime of a context.
3054 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3055 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
3056 si_flush_gfx_cs(sctx
, PIPE_FLUSH_ASYNC
, NULL
);
3060 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
3061 * VS passes its outputs to TES directly, so the fixed-function shader only
3062 * has to write TESSOUTER and TESSINNER.
3064 static void si_generate_fixed_func_tcs(struct si_context
*sctx
)
3066 struct ureg_src outer
, inner
;
3067 struct ureg_dst tessouter
, tessinner
;
3068 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
3071 return; /* if we get here, we're screwed */
3073 assert(!sctx
->fixed_func_tcs_shader
.cso
);
3075 outer
= ureg_DECL_system_value(ureg
,
3076 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
, 0);
3077 inner
= ureg_DECL_system_value(ureg
,
3078 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
, 0);
3080 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
3081 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
3083 ureg_MOV(ureg
, tessouter
, outer
);
3084 ureg_MOV(ureg
, tessinner
, inner
);
3087 sctx
->fixed_func_tcs_shader
.cso
=
3088 ureg_create_shader_and_destroy(ureg
, &sctx
->b
.b
);
3091 static void si_update_vgt_shader_config(struct si_context
*sctx
)
3093 /* Calculate the index of the config.
3094 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3095 unsigned index
= 2*!!sctx
->tes_shader
.cso
+ !!sctx
->gs_shader
.cso
;
3096 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[index
];
3099 uint32_t stages
= 0;
3101 *pm4
= CALLOC_STRUCT(si_pm4_state
);
3103 if (sctx
->tes_shader
.cso
) {
3104 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3105 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3107 if (sctx
->gs_shader
.cso
)
3108 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3110 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3112 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3113 } else if (sctx
->gs_shader
.cso
) {
3114 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3116 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3119 if (sctx
->b
.chip_class
>= GFX9
)
3120 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3122 si_pm4_set_reg(*pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3124 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3127 bool si_update_shaders(struct si_context
*sctx
)
3129 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3130 struct si_compiler_ctx_state compiler_state
;
3131 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3132 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3133 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
3134 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
3135 unsigned old_spi_shader_col_format
=
3136 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
3139 compiler_state
.tm
= sctx
->tm
;
3140 compiler_state
.debug
= sctx
->debug
;
3141 compiler_state
.is_debug_context
= sctx
->is_debug
;
3143 /* Update stages before GS. */
3144 if (sctx
->tes_shader
.cso
) {
3145 if (!sctx
->tess_rings
) {
3146 si_init_tess_factor_ring(sctx
);
3147 if (!sctx
->tess_rings
)
3152 if (sctx
->b
.chip_class
<= VI
) {
3153 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3157 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3160 if (sctx
->tcs_shader
.cso
) {
3161 r
= si_shader_select(ctx
, &sctx
->tcs_shader
,
3165 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3167 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3168 si_generate_fixed_func_tcs(sctx
);
3169 if (!sctx
->fixed_func_tcs_shader
.cso
)
3173 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
3177 si_pm4_bind_state(sctx
, hs
,
3178 sctx
->fixed_func_tcs_shader
.current
->pm4
);
3181 if (sctx
->gs_shader
.cso
) {
3183 if (sctx
->b
.chip_class
<= VI
) {
3184 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3188 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3192 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3196 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3198 } else if (sctx
->gs_shader
.cso
) {
3199 if (sctx
->b
.chip_class
<= VI
) {
3201 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3205 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3207 si_pm4_bind_state(sctx
, ls
, NULL
);
3208 si_pm4_bind_state(sctx
, hs
, NULL
);
3212 r
= si_shader_select(ctx
, &sctx
->vs_shader
, &compiler_state
);
3215 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3216 si_pm4_bind_state(sctx
, ls
, NULL
);
3217 si_pm4_bind_state(sctx
, hs
, NULL
);
3221 if (sctx
->gs_shader
.cso
) {
3222 r
= si_shader_select(ctx
, &sctx
->gs_shader
, &compiler_state
);
3225 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3226 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3228 if (!si_update_gs_ring_buffers(sctx
))
3231 si_pm4_bind_state(sctx
, gs
, NULL
);
3232 if (sctx
->b
.chip_class
<= VI
)
3233 si_pm4_bind_state(sctx
, es
, NULL
);
3236 si_update_vgt_shader_config(sctx
);
3238 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
3239 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
3241 if (sctx
->ps_shader
.cso
) {
3242 unsigned db_shader_control
;
3244 r
= si_shader_select(ctx
, &sctx
->ps_shader
, &compiler_state
);
3247 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3250 sctx
->ps_shader
.cso
->db_shader_control
|
3251 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
3253 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
3254 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
3255 sctx
->flatshade
!= rs
->flatshade
) {
3256 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
3257 sctx
->flatshade
= rs
->flatshade
;
3258 si_mark_atom_dirty(sctx
, &sctx
->spi_map
);
3261 if (sctx
->screen
->rbplus_allowed
&&
3262 si_pm4_state_changed(sctx
, ps
) &&
3264 old_spi_shader_col_format
!=
3265 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
3266 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
3268 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
3269 sctx
->ps_db_shader_control
= db_shader_control
;
3270 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
3271 if (sctx
->screen
->dpbb_allowed
)
3272 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
3275 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
3276 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
3277 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
3279 if (sctx
->b
.chip_class
== SI
)
3280 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
3282 if (sctx
->framebuffer
.nr_samples
<= 1)
3283 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
3287 if (si_pm4_state_enabled_and_changed(sctx
, ls
) ||
3288 si_pm4_state_enabled_and_changed(sctx
, hs
) ||
3289 si_pm4_state_enabled_and_changed(sctx
, es
) ||
3290 si_pm4_state_enabled_and_changed(sctx
, gs
) ||
3291 si_pm4_state_enabled_and_changed(sctx
, vs
) ||
3292 si_pm4_state_enabled_and_changed(sctx
, ps
)) {
3293 if (!si_update_spi_tmpring_size(sctx
))
3297 if (sctx
->b
.chip_class
>= CIK
) {
3298 if (si_pm4_state_enabled_and_changed(sctx
, ls
))
3299 sctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
3300 else if (!sctx
->queued
.named
.ls
)
3301 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_LS
;
3303 if (si_pm4_state_enabled_and_changed(sctx
, hs
))
3304 sctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
3305 else if (!sctx
->queued
.named
.hs
)
3306 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_HS
;
3308 if (si_pm4_state_enabled_and_changed(sctx
, es
))
3309 sctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
3310 else if (!sctx
->queued
.named
.es
)
3311 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_ES
;
3313 if (si_pm4_state_enabled_and_changed(sctx
, gs
))
3314 sctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
3315 else if (!sctx
->queued
.named
.gs
)
3316 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_GS
;
3318 if (si_pm4_state_enabled_and_changed(sctx
, vs
))
3319 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
3320 else if (!sctx
->queued
.named
.vs
)
3321 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VS
;
3323 if (si_pm4_state_enabled_and_changed(sctx
, ps
))
3324 sctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
3325 else if (!sctx
->queued
.named
.ps
)
3326 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_PS
;
3329 sctx
->do_update_shaders
= false;
3333 static void si_emit_scratch_state(struct si_context
*sctx
,
3334 struct r600_atom
*atom
)
3336 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
3338 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3339 sctx
->spi_tmpring_size
);
3341 if (sctx
->scratch_buffer
) {
3342 radeon_add_to_buffer_list(sctx
, sctx
->b
.gfx_cs
,
3343 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
3344 RADEON_PRIO_SCRATCH_BUFFER
);
3348 void *si_get_blit_vs(struct si_context
*sctx
, enum blitter_attrib_type type
,
3349 unsigned num_layers
)
3351 unsigned vs_blit_property
;
3355 case UTIL_BLITTER_ATTRIB_NONE
:
3356 vs
= num_layers
> 1 ? &sctx
->vs_blit_pos_layered
:
3358 vs_blit_property
= SI_VS_BLIT_SGPRS_POS
;
3360 case UTIL_BLITTER_ATTRIB_COLOR
:
3361 vs
= num_layers
> 1 ? &sctx
->vs_blit_color_layered
:
3362 &sctx
->vs_blit_color
;
3363 vs_blit_property
= SI_VS_BLIT_SGPRS_POS_COLOR
;
3365 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY
:
3366 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW
:
3367 assert(num_layers
== 1);
3368 vs
= &sctx
->vs_blit_texcoord
;
3369 vs_blit_property
= SI_VS_BLIT_SGPRS_POS_TEXCOORD
;
3378 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_VERTEX
);
3382 /* Tell the shader to load VS inputs from SGPRs: */
3383 ureg_property(ureg
, TGSI_PROPERTY_VS_BLIT_SGPRS
, vs_blit_property
);
3384 ureg_property(ureg
, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
, true);
3386 /* This is just a pass-through shader with 1-3 MOV instructions. */
3388 ureg_DECL_output(ureg
, TGSI_SEMANTIC_POSITION
, 0),
3389 ureg_DECL_vs_input(ureg
, 0));
3391 if (type
!= UTIL_BLITTER_ATTRIB_NONE
) {
3393 ureg_DECL_output(ureg
, TGSI_SEMANTIC_GENERIC
, 0),
3394 ureg_DECL_vs_input(ureg
, 1));
3397 if (num_layers
> 1) {
3398 struct ureg_src instance_id
=
3399 ureg_DECL_system_value(ureg
, TGSI_SEMANTIC_INSTANCEID
, 0);
3400 struct ureg_dst layer
=
3401 ureg_DECL_output(ureg
, TGSI_SEMANTIC_LAYER
, 0);
3403 ureg_MOV(ureg
, ureg_writemask(layer
, TGSI_WRITEMASK_X
),
3404 ureg_scalar(instance_id
, TGSI_SWIZZLE_X
));
3408 *vs
= ureg_create_shader_and_destroy(ureg
, &sctx
->b
.b
);
3412 void si_init_shader_functions(struct si_context
*sctx
)
3414 si_init_atom(sctx
, &sctx
->spi_map
, &sctx
->atoms
.s
.spi_map
, si_emit_spi_map
);
3415 si_init_atom(sctx
, &sctx
->scratch_state
, &sctx
->atoms
.s
.scratch_state
,
3416 si_emit_scratch_state
);
3418 sctx
->b
.b
.create_vs_state
= si_create_shader_selector
;
3419 sctx
->b
.b
.create_tcs_state
= si_create_shader_selector
;
3420 sctx
->b
.b
.create_tes_state
= si_create_shader_selector
;
3421 sctx
->b
.b
.create_gs_state
= si_create_shader_selector
;
3422 sctx
->b
.b
.create_fs_state
= si_create_shader_selector
;
3424 sctx
->b
.b
.bind_vs_state
= si_bind_vs_shader
;
3425 sctx
->b
.b
.bind_tcs_state
= si_bind_tcs_shader
;
3426 sctx
->b
.b
.bind_tes_state
= si_bind_tes_shader
;
3427 sctx
->b
.b
.bind_gs_state
= si_bind_gs_shader
;
3428 sctx
->b
.b
.bind_fs_state
= si_bind_ps_shader
;
3430 sctx
->b
.b
.delete_vs_state
= si_delete_shader_selector
;
3431 sctx
->b
.b
.delete_tcs_state
= si_delete_shader_selector
;
3432 sctx
->b
.b
.delete_tes_state
= si_delete_shader_selector
;
3433 sctx
->b
.b
.delete_gs_state
= si_delete_shader_selector
;
3434 sctx
->b
.b
.delete_fs_state
= si_delete_shader_selector
;