2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
47 void *si_get_ir_binary(struct si_shader_selector
*sel
)
54 ir_binary
= sel
->tokens
;
55 ir_size
= tgsi_num_tokens(sel
->tokens
) *
56 sizeof(struct tgsi_token
);
61 nir_serialize(&blob
, sel
->nir
);
62 ir_binary
= blob
.data
;
66 unsigned size
= 4 + ir_size
+ sizeof(sel
->so
);
67 char *result
= (char*)MALLOC(size
);
71 *((uint32_t*)result
) = size
;
72 memcpy(result
+ 4, ir_binary
, ir_size
);
73 memcpy(result
+ 4 + ir_size
, &sel
->so
, sizeof(sel
->so
));
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
84 /* data may be NULL if size == 0 */
86 memcpy(ptr
, data
, size
);
87 ptr
+= DIV_ROUND_UP(size
, 4);
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
94 memcpy(data
, ptr
, size
);
95 ptr
+= DIV_ROUND_UP(size
, 4);
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
103 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
106 return write_data(ptr
, data
, size
);
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
113 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
116 assert(*data
== NULL
);
119 *data
= malloc(*size
);
120 return read_data(ptr
, *data
, *size
);
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
127 static void *si_get_shader_binary(struct si_shader
*shader
)
129 /* There is always a size of data followed by the data itself. */
130 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
131 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
133 /* Refuse to allocate overly large buffers and guard against integer
135 if (shader
->binary
.elf_size
> UINT_MAX
/ 4 ||
136 llvm_ir_size
> UINT_MAX
/ 4)
141 4 + /* CRC32 of the data below */
142 align(sizeof(shader
->config
), 4) +
143 align(sizeof(shader
->info
), 4) +
144 4 + align(shader
->binary
.elf_size
, 4) +
145 4 + align(llvm_ir_size
, 4);
146 void *buffer
= CALLOC(1, size
);
147 uint32_t *ptr
= (uint32_t*)buffer
;
153 ptr
++; /* CRC32 is calculated at the end. */
155 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
156 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
157 ptr
= write_chunk(ptr
, shader
->binary
.elf_buffer
, shader
->binary
.elf_size
);
158 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
159 assert((char *)ptr
- (char *)buffer
== size
);
162 ptr
= (uint32_t*)buffer
;
164 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
169 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
171 uint32_t *ptr
= (uint32_t*)binary
;
172 uint32_t size
= *ptr
++;
173 uint32_t crc32
= *ptr
++;
177 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
178 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
182 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
183 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
184 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.elf_buffer
,
186 shader
->binary
.elf_size
= elf_size
;
187 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
193 * Insert a shader into the cache. It's assumed the shader is not in the cache.
194 * Use si_shader_cache_load_shader before calling this.
196 * Returns false on failure, in which case the ir_binary should be freed.
198 bool si_shader_cache_insert_shader(struct si_screen
*sscreen
, void *ir_binary
,
199 struct si_shader
*shader
,
200 bool insert_into_disk_cache
)
203 struct hash_entry
*entry
;
204 uint8_t key
[CACHE_KEY_SIZE
];
206 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
208 return false; /* already added */
210 hw_binary
= si_get_shader_binary(shader
);
214 if (_mesa_hash_table_insert(sscreen
->shader_cache
, ir_binary
,
215 hw_binary
) == NULL
) {
220 if (sscreen
->disk_shader_cache
&& insert_into_disk_cache
) {
221 disk_cache_compute_key(sscreen
->disk_shader_cache
, ir_binary
,
222 *((uint32_t *)ir_binary
), key
);
223 disk_cache_put(sscreen
->disk_shader_cache
, key
, hw_binary
,
224 *((uint32_t *) hw_binary
), NULL
);
230 bool si_shader_cache_load_shader(struct si_screen
*sscreen
, void *ir_binary
,
231 struct si_shader
*shader
)
233 struct hash_entry
*entry
=
234 _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
236 if (sscreen
->disk_shader_cache
) {
237 unsigned char sha1
[CACHE_KEY_SIZE
];
238 size_t tg_size
= *((uint32_t *) ir_binary
);
240 disk_cache_compute_key(sscreen
->disk_shader_cache
,
241 ir_binary
, tg_size
, sha1
);
245 disk_cache_get(sscreen
->disk_shader_cache
,
250 if (binary_size
< sizeof(uint32_t) ||
251 *((uint32_t*)buffer
) != binary_size
) {
252 /* Something has gone wrong discard the item
253 * from the cache and rebuild/link from
256 assert(!"Invalid radeonsi shader disk cache "
259 disk_cache_remove(sscreen
->disk_shader_cache
,
266 if (!si_load_shader_binary(shader
, buffer
)) {
272 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
,
279 if (si_load_shader_binary(shader
, entry
->data
))
284 p_atomic_inc(&sscreen
->num_shader_cache_hits
);
288 static uint32_t si_shader_cache_key_hash(const void *key
)
290 /* The first dword is the key size. */
291 return util_hash_crc32(key
, *(uint32_t*)key
);
294 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
296 uint32_t *keya
= (uint32_t*)a
;
297 uint32_t *keyb
= (uint32_t*)b
;
299 /* The first dword is the key size. */
303 return memcmp(keya
, keyb
, *keya
) == 0;
306 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
308 FREE((void*)entry
->key
);
312 bool si_init_shader_cache(struct si_screen
*sscreen
)
314 (void) mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
315 sscreen
->shader_cache
=
316 _mesa_hash_table_create(NULL
,
317 si_shader_cache_key_hash
,
318 si_shader_cache_key_equals
);
320 return sscreen
->shader_cache
!= NULL
;
323 void si_destroy_shader_cache(struct si_screen
*sscreen
)
325 if (sscreen
->shader_cache
)
326 _mesa_hash_table_destroy(sscreen
->shader_cache
,
327 si_destroy_shader_cache_entry
);
328 mtx_destroy(&sscreen
->shader_cache_mutex
);
333 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
334 const struct si_shader_selector
*tes
,
335 struct si_pm4_state
*pm4
)
337 const struct tgsi_shader_info
*info
= &tes
->info
;
338 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
339 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
340 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
341 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
342 unsigned type
, partitioning
, topology
, distribution_mode
;
344 switch (tes_prim_mode
) {
345 case PIPE_PRIM_LINES
:
346 type
= V_028B6C_TESS_ISOLINE
;
348 case PIPE_PRIM_TRIANGLES
:
349 type
= V_028B6C_TESS_TRIANGLE
;
351 case PIPE_PRIM_QUADS
:
352 type
= V_028B6C_TESS_QUAD
;
359 switch (tes_spacing
) {
360 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
361 partitioning
= V_028B6C_PART_FRAC_ODD
;
363 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
364 partitioning
= V_028B6C_PART_FRAC_EVEN
;
366 case PIPE_TESS_SPACING_EQUAL
:
367 partitioning
= V_028B6C_PART_INTEGER
;
375 topology
= V_028B6C_OUTPUT_POINT
;
376 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
377 topology
= V_028B6C_OUTPUT_LINE
;
378 else if (tes_vertex_order_cw
)
379 /* for some reason, this must be the other way around */
380 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
382 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
384 if (sscreen
->has_distributed_tess
) {
385 if (sscreen
->info
.family
== CHIP_FIJI
||
386 sscreen
->info
.family
>= CHIP_POLARIS10
)
387 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
389 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
391 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
394 pm4
->shader
->vgt_tf_param
= S_028B6C_TYPE(type
) |
395 S_028B6C_PARTITIONING(partitioning
) |
396 S_028B6C_TOPOLOGY(topology
) |
397 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
400 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
401 * whether the "fractional odd" tessellation spacing is used.
403 * Possible VGT configurations and which state should set the register:
405 * Reg set in | VGT shader configuration | Value
406 * ------------------------------------------------------
408 * VS as ES | ES -> GS -> VS | 30
409 * TES as VS | LS -> HS -> VS | 14 or 30
410 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
412 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
414 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
415 struct si_shader_selector
*sel
,
416 struct si_shader
*shader
,
417 struct si_pm4_state
*pm4
)
419 unsigned type
= sel
->type
;
421 if (sscreen
->info
.family
< CHIP_POLARIS10
)
424 /* VS as VS, or VS as ES: */
425 if ((type
== PIPE_SHADER_VERTEX
&&
427 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
428 /* TES as VS, or TES as ES: */
429 type
== PIPE_SHADER_TESS_EVAL
) {
430 unsigned vtx_reuse_depth
= 30;
432 if (type
== PIPE_SHADER_TESS_EVAL
&&
433 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
434 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
435 vtx_reuse_depth
= 14;
438 pm4
->shader
->vgt_vertex_reuse_block_cntl
= vtx_reuse_depth
;
442 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
445 si_pm4_clear_state(shader
->pm4
);
447 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
450 shader
->pm4
->shader
= shader
;
453 fprintf(stderr
, "radeonsi: Failed to create pm4 state.\n");
458 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs
)
460 /* Add the pointer to VBO descriptors. */
461 return num_always_on_user_sgprs
+ 1;
464 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
466 struct si_pm4_state
*pm4
;
467 unsigned vgpr_comp_cnt
;
470 assert(sscreen
->info
.chip_class
<= GFX8
);
472 pm4
= si_get_shader_pm4_state(shader
);
476 va
= shader
->bo
->gpu_address
;
477 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
479 /* We need at least 2 components for LS.
480 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
481 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
483 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
485 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
486 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
488 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
489 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
490 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
491 S_00B528_DX10_CLAMP(1) |
492 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
493 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
)) |
494 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
497 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
499 struct si_pm4_state
*pm4
;
501 unsigned ls_vgpr_comp_cnt
= 0;
503 pm4
= si_get_shader_pm4_state(shader
);
507 va
= shader
->bo
->gpu_address
;
508 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
510 if (sscreen
->info
.chip_class
>= GFX9
) {
511 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
512 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, S_00B414_MEM_BASE(va
>> 40));
514 /* We need at least 2 components for LS.
515 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
516 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
518 ls_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
520 unsigned num_user_sgprs
=
521 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR
);
523 shader
->config
.rsrc2
=
524 S_00B42C_USER_SGPR(num_user_sgprs
) |
525 S_00B42C_USER_SGPR_MSB(num_user_sgprs
>> 5) |
526 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
528 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
529 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, S_00B424_MEM_BASE(va
>> 40));
531 shader
->config
.rsrc2
=
532 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
533 S_00B42C_OC_LDS_EN(1) |
534 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
537 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
538 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
539 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
540 S_00B428_DX10_CLAMP(1) |
541 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
542 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt
));
544 if (sscreen
->info
.chip_class
<= GFX8
) {
545 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
546 shader
->config
.rsrc2
);
550 static void si_emit_shader_es(struct si_context
*sctx
)
552 struct si_shader
*shader
= sctx
->queued
.named
.es
->shader
;
553 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
558 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
559 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
560 shader
->selector
->esgs_itemsize
/ 4);
562 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
563 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
564 SI_TRACKED_VGT_TF_PARAM
,
565 shader
->vgt_tf_param
);
567 if (shader
->vgt_vertex_reuse_block_cntl
)
568 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
569 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
570 shader
->vgt_vertex_reuse_block_cntl
);
572 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
573 sctx
->context_roll
= true;
576 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
578 struct si_pm4_state
*pm4
;
579 unsigned num_user_sgprs
;
580 unsigned vgpr_comp_cnt
;
584 assert(sscreen
->info
.chip_class
<= GFX8
);
586 pm4
= si_get_shader_pm4_state(shader
);
590 pm4
->atom
.emit
= si_emit_shader_es
;
591 va
= shader
->bo
->gpu_address
;
592 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
594 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
595 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
596 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
597 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
598 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
599 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
600 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
602 unreachable("invalid shader selector type");
604 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
606 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
607 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
608 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
609 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
610 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
611 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
612 S_00B328_DX10_CLAMP(1) |
613 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
614 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
615 S_00B32C_USER_SGPR(num_user_sgprs
) |
616 S_00B32C_OC_LDS_EN(oc_lds_en
) |
617 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
619 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
620 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
622 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
625 static unsigned si_conv_prim_to_gs_out(unsigned mode
)
627 static const int prim_conv
[] = {
628 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
629 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
630 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
631 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
632 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
633 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
634 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
635 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
636 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
637 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
638 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
639 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
640 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
641 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
642 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
644 assert(mode
< ARRAY_SIZE(prim_conv
));
646 return prim_conv
[mode
];
649 void gfx9_get_gs_info(struct si_shader_selector
*es
,
650 struct si_shader_selector
*gs
,
651 struct gfx9_gs_info
*out
)
653 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
654 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
655 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
656 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
658 /* All these are in dwords: */
659 /* We can't allow using the whole LDS, because GS waves compete with
660 * other shader stages for LDS space. */
661 const unsigned max_lds_size
= 8 * 1024;
662 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
663 unsigned esgs_lds_size
;
665 /* All these are per subgroup: */
666 const unsigned max_out_prims
= 32 * 1024;
667 const unsigned max_es_verts
= 255;
668 const unsigned ideal_gs_prims
= 64;
669 unsigned max_gs_prims
, gs_prims
;
670 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
672 if (uses_adjacency
|| gs_num_invocations
> 1)
673 max_gs_prims
= 127 / gs_num_invocations
;
677 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
678 * Make sure we don't go over the maximum value.
680 if (gs
->gs_max_out_vertices
> 0) {
681 max_gs_prims
= MIN2(max_gs_prims
,
683 (gs
->gs_max_out_vertices
* gs_num_invocations
));
685 assert(max_gs_prims
> 0);
687 /* If the primitive has adjacency, halve the number of vertices
688 * that will be reused in multiple primitives.
690 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
692 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
693 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
695 /* Compute ESGS LDS size based on the worst case number of ES vertices
696 * needed to create the target number of GS prims per subgroup.
698 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
700 /* If total LDS usage is too big, refactor partitions based on ratio
701 * of ESGS item sizes.
703 if (esgs_lds_size
> max_lds_size
) {
704 /* Our target GS Prims Per Subgroup was too large. Calculate
705 * the maximum number of GS Prims Per Subgroup that will fit
706 * into LDS, capped by the maximum that the hardware can support.
708 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
710 assert(gs_prims
> 0);
711 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
714 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
715 assert(esgs_lds_size
<= max_lds_size
);
718 /* Now calculate remaining ESGS information. */
720 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
722 es_verts
= max_es_verts
;
724 /* Vertices for adjacency primitives are not always reused, so restore
725 * it for ES_VERTS_PER_SUBGRP.
727 min_es_verts
= gs
->gs_input_verts_per_prim
;
729 /* For normal primitives, the VGT only checks if they are past the ES
730 * verts per subgroup after allocating a full GS primitive and if they
731 * are, kick off a new subgroup. But if those additional ES verts are
732 * unique (e.g. not reused) we need to make sure there is enough LDS
733 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
735 es_verts
-= min_es_verts
- 1;
737 out
->es_verts_per_subgroup
= es_verts
;
738 out
->gs_prims_per_subgroup
= gs_prims
;
739 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
740 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
741 gs
->gs_max_out_vertices
;
742 out
->esgs_ring_size
= 4 * esgs_lds_size
;
744 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
747 static void si_emit_shader_gs(struct si_context
*sctx
)
749 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
750 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
755 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
756 * R_028A68_VGT_GSVS_RING_OFFSET_3, R_028A6C_VGT_GS_OUT_PRIM_TYPE */
757 radeon_opt_set_context_reg4(sctx
, R_028A60_VGT_GSVS_RING_OFFSET_1
,
758 SI_TRACKED_VGT_GSVS_RING_OFFSET_1
,
759 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
,
760 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
,
761 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
,
762 shader
->ctx_reg
.gs
.vgt_gs_out_prim_type
);
765 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
766 radeon_opt_set_context_reg(sctx
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
,
767 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE
,
768 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
);
770 /* R_028B38_VGT_GS_MAX_VERT_OUT */
771 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
772 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
773 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
);
775 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
776 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
777 radeon_opt_set_context_reg4(sctx
, R_028B5C_VGT_GS_VERT_ITEMSIZE
,
778 SI_TRACKED_VGT_GS_VERT_ITEMSIZE
,
779 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
,
780 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
,
781 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
,
782 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
);
784 /* R_028B90_VGT_GS_INSTANCE_CNT */
785 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
786 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
787 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
);
789 if (sctx
->chip_class
>= GFX9
) {
790 /* R_028A44_VGT_GS_ONCHIP_CNTL */
791 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
792 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
793 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
);
794 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
795 radeon_opt_set_context_reg(sctx
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
796 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
797 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
);
798 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
799 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
800 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
801 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
);
803 if (shader
->key
.part
.gs
.es
->type
== PIPE_SHADER_TESS_EVAL
)
804 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
805 SI_TRACKED_VGT_TF_PARAM
,
806 shader
->vgt_tf_param
);
807 if (shader
->vgt_vertex_reuse_block_cntl
)
808 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
809 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
810 shader
->vgt_vertex_reuse_block_cntl
);
813 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
814 sctx
->context_roll
= true;
817 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
819 struct si_shader_selector
*sel
= shader
->selector
;
820 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
821 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
822 struct si_pm4_state
*pm4
;
824 unsigned max_stream
= sel
->max_gs_stream
;
827 pm4
= si_get_shader_pm4_state(shader
);
831 pm4
->atom
.emit
= si_emit_shader_gs
;
833 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
834 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
= offset
;
837 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
838 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
= offset
;
841 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
842 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
= offset
;
844 shader
->ctx_reg
.gs
.vgt_gs_out_prim_type
=
845 si_conv_prim_to_gs_out(sel
->gs_output_prim
);
848 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
849 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
= offset
;
851 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
852 assert(offset
< (1 << 15));
854 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
= sel
->gs_max_out_vertices
;
856 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
= num_components
[0];
857 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
= (max_stream
>= 1) ? num_components
[1] : 0;
858 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
= (max_stream
>= 2) ? num_components
[2] : 0;
859 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
= (max_stream
>= 3) ? num_components
[3] : 0;
861 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
= S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
862 S_028B90_ENABLE(gs_num_invocations
> 0);
864 va
= shader
->bo
->gpu_address
;
865 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
867 if (sscreen
->info
.chip_class
>= GFX9
) {
868 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
869 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
870 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
872 if (es_type
== PIPE_SHADER_VERTEX
)
873 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
874 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
875 else if (es_type
== PIPE_SHADER_TESS_EVAL
)
876 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
878 unreachable("invalid shader selector type");
880 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
881 * VGPR[0:4] are always loaded.
883 if (sel
->info
.uses_invocationid
)
884 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
885 else if (sel
->info
.uses_primid
)
886 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
887 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
888 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
890 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
892 unsigned num_user_sgprs
;
893 if (es_type
== PIPE_SHADER_VERTEX
)
894 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
896 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
898 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
899 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, S_00B214_MEM_BASE(va
>> 40));
901 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
902 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
903 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
904 S_00B228_DX10_CLAMP(1) |
905 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
906 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
907 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
908 S_00B22C_USER_SGPR(num_user_sgprs
) |
909 S_00B22C_USER_SGPR_MSB(num_user_sgprs
>> 5) |
910 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
911 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
912 S_00B22C_LDS_SIZE(shader
->config
.lds_size
) |
913 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
915 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
=
916 S_028A44_ES_VERTS_PER_SUBGRP(shader
->gs_info
.es_verts_per_subgroup
) |
917 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->gs_info
.gs_prims_per_subgroup
) |
918 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->gs_info
.gs_inst_prims_in_subgroup
);
919 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
=
920 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader
->gs_info
.max_prims_per_subgroup
);
921 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
=
922 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4;
924 if (es_type
== PIPE_SHADER_TESS_EVAL
)
925 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
927 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
930 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
931 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, S_00B224_MEM_BASE(va
>> 40));
933 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
934 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
935 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
936 S_00B228_DX10_CLAMP(1) |
937 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
938 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
939 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
940 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
944 static void si_emit_shader_vs(struct si_context
*sctx
)
946 struct si_shader
*shader
= sctx
->queued
.named
.vs
->shader
;
947 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
952 radeon_opt_set_context_reg(sctx
, R_028A40_VGT_GS_MODE
,
953 SI_TRACKED_VGT_GS_MODE
,
954 shader
->ctx_reg
.vs
.vgt_gs_mode
);
955 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
956 SI_TRACKED_VGT_PRIMITIVEID_EN
,
957 shader
->ctx_reg
.vs
.vgt_primitiveid_en
);
959 if (sctx
->chip_class
<= GFX8
) {
960 radeon_opt_set_context_reg(sctx
, R_028AB4_VGT_REUSE_OFF
,
961 SI_TRACKED_VGT_REUSE_OFF
,
962 shader
->ctx_reg
.vs
.vgt_reuse_off
);
965 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
966 SI_TRACKED_SPI_VS_OUT_CONFIG
,
967 shader
->ctx_reg
.vs
.spi_vs_out_config
);
969 radeon_opt_set_context_reg(sctx
, R_02870C_SPI_SHADER_POS_FORMAT
,
970 SI_TRACKED_SPI_SHADER_POS_FORMAT
,
971 shader
->ctx_reg
.vs
.spi_shader_pos_format
);
973 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
974 SI_TRACKED_PA_CL_VTE_CNTL
,
975 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
);
977 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
978 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
979 SI_TRACKED_VGT_TF_PARAM
,
980 shader
->vgt_tf_param
);
982 if (shader
->vgt_vertex_reuse_block_cntl
)
983 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
984 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
985 shader
->vgt_vertex_reuse_block_cntl
);
987 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
988 sctx
->context_roll
= true;
992 * Compute the state for \p shader, which will run as a vertex shader on the
995 * If \p gs is non-NULL, it points to the geometry shader for which this shader
996 * is the copy shader.
998 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
999 struct si_shader_selector
*gs
)
1001 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1002 struct si_pm4_state
*pm4
;
1003 unsigned num_user_sgprs
, vgpr_comp_cnt
;
1005 unsigned nparams
, oc_lds_en
;
1006 unsigned window_space
=
1007 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1008 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
1010 pm4
= si_get_shader_pm4_state(shader
);
1014 pm4
->atom
.emit
= si_emit_shader_vs
;
1016 /* We always write VGT_GS_MODE in the VS state, because every switch
1017 * between different shader pipelines involving a different GS or no
1018 * GS at all involves a switch of the VS (different GS use different
1019 * copy shaders). On the other hand, when the API switches from a GS to
1020 * no GS and then back to the same GS used originally, the GS state is
1024 unsigned mode
= V_028A40_GS_OFF
;
1026 /* PrimID needs GS scenario A. */
1028 mode
= V_028A40_GS_SCENARIO_A
;
1030 shader
->ctx_reg
.vs
.vgt_gs_mode
= S_028A40_MODE(mode
);
1031 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= enable_prim_id
;
1033 shader
->ctx_reg
.vs
.vgt_gs_mode
= ac_vgt_gs_mode(gs
->gs_max_out_vertices
,
1034 sscreen
->info
.chip_class
);
1035 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= 0;
1038 if (sscreen
->info
.chip_class
<= GFX8
) {
1039 /* Reuse needs to be set off if we write oViewport. */
1040 shader
->ctx_reg
.vs
.vgt_reuse_off
=
1041 S_028AB4_REUSE_OFF(info
->writes_viewport_index
);
1044 va
= shader
->bo
->gpu_address
;
1045 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1048 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
1049 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
1050 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
1051 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1052 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1053 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1055 vgpr_comp_cnt
= enable_prim_id
? 2 : (shader
->info
.uses_instanceid
? 1 : 0);
1057 if (info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
]) {
1058 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1059 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
1061 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
1063 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
1064 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
1065 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
1067 unreachable("invalid shader selector type");
1069 /* VS is required to export at least one param. */
1070 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1071 shader
->ctx_reg
.vs
.spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
1073 shader
->ctx_reg
.vs
.spi_shader_pos_format
=
1074 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1075 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1076 V_02870C_SPI_SHADER_4COMP
:
1077 V_02870C_SPI_SHADER_NONE
) |
1078 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1079 V_02870C_SPI_SHADER_4COMP
:
1080 V_02870C_SPI_SHADER_NONE
) |
1081 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1082 V_02870C_SPI_SHADER_4COMP
:
1083 V_02870C_SPI_SHADER_NONE
);
1085 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
1087 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
1088 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, S_00B124_MEM_BASE(va
>> 40));
1089 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
1090 S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1091 S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
1092 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
1093 S_00B128_DX10_CLAMP(1) |
1094 S_00B128_FLOAT_MODE(shader
->config
.float_mode
));
1095 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
1096 S_00B12C_USER_SGPR(num_user_sgprs
) |
1097 S_00B12C_OC_LDS_EN(oc_lds_en
) |
1098 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
1099 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
1100 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
1101 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
1102 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
) |
1103 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1106 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1107 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1109 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1110 S_028818_VTX_W0_FMT(1) |
1111 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1112 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1113 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1115 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1116 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
1118 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
1121 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
1123 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
1124 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
1125 !!(info
->colors_read
& 0xf0);
1126 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
1127 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
1129 assert(num_interp
<= 32);
1130 return MIN2(num_interp
, 32);
1133 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
1135 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
1136 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
1138 /* If the i-th target format is set, all previous target formats must
1139 * be non-zero to avoid hangs.
1141 for (i
= 0; i
< num_targets
; i
++)
1142 if (!(value
& (0xf << (i
* 4))))
1143 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
1148 static void si_emit_shader_ps(struct si_context
*sctx
)
1150 struct si_shader
*shader
= sctx
->queued
.named
.ps
->shader
;
1151 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1156 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1157 radeon_opt_set_context_reg2(sctx
, R_0286CC_SPI_PS_INPUT_ENA
,
1158 SI_TRACKED_SPI_PS_INPUT_ENA
,
1159 shader
->ctx_reg
.ps
.spi_ps_input_ena
,
1160 shader
->ctx_reg
.ps
.spi_ps_input_addr
);
1162 radeon_opt_set_context_reg(sctx
, R_0286E0_SPI_BARYC_CNTL
,
1163 SI_TRACKED_SPI_BARYC_CNTL
,
1164 shader
->ctx_reg
.ps
.spi_baryc_cntl
);
1165 radeon_opt_set_context_reg(sctx
, R_0286D8_SPI_PS_IN_CONTROL
,
1166 SI_TRACKED_SPI_PS_IN_CONTROL
,
1167 shader
->ctx_reg
.ps
.spi_ps_in_control
);
1169 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1170 radeon_opt_set_context_reg2(sctx
, R_028710_SPI_SHADER_Z_FORMAT
,
1171 SI_TRACKED_SPI_SHADER_Z_FORMAT
,
1172 shader
->ctx_reg
.ps
.spi_shader_z_format
,
1173 shader
->ctx_reg
.ps
.spi_shader_col_format
);
1175 radeon_opt_set_context_reg(sctx
, R_02823C_CB_SHADER_MASK
,
1176 SI_TRACKED_CB_SHADER_MASK
,
1177 shader
->ctx_reg
.ps
.cb_shader_mask
);
1179 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1180 sctx
->context_roll
= true;
1183 static void si_shader_ps(struct si_shader
*shader
)
1185 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1186 struct si_pm4_state
*pm4
;
1187 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1188 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1190 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1192 /* we need to enable at least one of them, otherwise we hang the GPU */
1193 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1194 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1195 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1196 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1197 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1198 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1199 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1200 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1201 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1202 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
1203 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1204 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1205 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1206 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1208 /* Validate interpolation optimization flags (read as implications). */
1209 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1210 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1211 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1212 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1213 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1214 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1215 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1216 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1217 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1218 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1219 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1220 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1221 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1222 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1223 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1224 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1225 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1226 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1228 /* Validate cases when the optimizations are off (read as implications). */
1229 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1230 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1231 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1232 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1233 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1234 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1236 pm4
= si_get_shader_pm4_state(shader
);
1240 pm4
->atom
.emit
= si_emit_shader_ps
;
1242 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1244 * 0 -> Position = pixel center
1245 * 1 -> Position = pixel centroid
1246 * 2 -> Position = at sample position
1248 * From GLSL 4.5 specification, section 7.1:
1249 * "The variable gl_FragCoord is available as an input variable from
1250 * within fragment shaders and it holds the window relative coordinates
1251 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1252 * value can be for any location within the pixel, or one of the
1253 * fragment samples. The use of centroid does not further restrict
1254 * this value to be inside the current primitive."
1256 * Meaning that centroid has no effect and we can return anything within
1257 * the pixel. Thus, return the value at sample position, because that's
1258 * the most accurate one shaders can get.
1260 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1262 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1263 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1264 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1266 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1267 cb_shader_mask
= ac_get_cb_shader_mask(spi_shader_col_format
);
1269 /* Ensure that some export memory is always allocated, for two reasons:
1271 * 1) Correctness: The hardware ignores the EXEC mask if no export
1272 * memory is allocated, so KILL and alpha test do not work correctly
1274 * 2) Performance: Every shader needs at least a NULL export, even when
1275 * it writes no color/depth output. The NULL export instruction
1276 * stalls without this setting.
1278 * Don't add this to CB_SHADER_MASK.
1280 if (!spi_shader_col_format
&&
1281 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1282 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1284 shader
->ctx_reg
.ps
.spi_ps_input_ena
= input_ena
;
1285 shader
->ctx_reg
.ps
.spi_ps_input_addr
= shader
->config
.spi_ps_input_addr
;
1287 /* Set interpolation controls. */
1288 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
));
1290 shader
->ctx_reg
.ps
.spi_baryc_cntl
= spi_baryc_cntl
;
1291 shader
->ctx_reg
.ps
.spi_ps_in_control
= spi_ps_in_control
;
1292 shader
->ctx_reg
.ps
.spi_shader_z_format
=
1293 ac_get_spi_shader_z_format(info
->writes_z
,
1294 info
->writes_stencil
,
1295 info
->writes_samplemask
);
1296 shader
->ctx_reg
.ps
.spi_shader_col_format
= spi_shader_col_format
;
1297 shader
->ctx_reg
.ps
.cb_shader_mask
= cb_shader_mask
;
1299 va
= shader
->bo
->gpu_address
;
1300 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1301 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1302 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, S_00B024_MEM_BASE(va
>> 40));
1304 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
1305 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1306 S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
1307 S_00B028_DX10_CLAMP(1) |
1308 S_00B028_FLOAT_MODE(shader
->config
.float_mode
));
1309 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1310 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1311 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1312 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1315 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1316 struct si_shader
*shader
)
1318 switch (shader
->selector
->type
) {
1319 case PIPE_SHADER_VERTEX
:
1320 if (shader
->key
.as_ls
)
1321 si_shader_ls(sscreen
, shader
);
1322 else if (shader
->key
.as_es
)
1323 si_shader_es(sscreen
, shader
);
1325 si_shader_vs(sscreen
, shader
, NULL
);
1327 case PIPE_SHADER_TESS_CTRL
:
1328 si_shader_hs(sscreen
, shader
);
1330 case PIPE_SHADER_TESS_EVAL
:
1331 if (shader
->key
.as_es
)
1332 si_shader_es(sscreen
, shader
);
1334 si_shader_vs(sscreen
, shader
, NULL
);
1336 case PIPE_SHADER_GEOMETRY
:
1337 si_shader_gs(sscreen
, shader
);
1339 case PIPE_SHADER_FRAGMENT
:
1340 si_shader_ps(shader
);
1347 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1349 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1350 if (sctx
->queued
.named
.dsa
)
1351 return sctx
->queued
.named
.dsa
->alpha_func
;
1353 return PIPE_FUNC_ALWAYS
;
1356 void si_shader_selector_key_vs(struct si_context
*sctx
,
1357 struct si_shader_selector
*vs
,
1358 struct si_shader_key
*key
,
1359 struct si_vs_prolog_bits
*prolog_key
)
1361 if (!sctx
->vertex_elements
||
1362 vs
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
])
1365 struct si_vertex_elements
*elts
= sctx
->vertex_elements
;
1367 prolog_key
->instance_divisor_is_one
= elts
->instance_divisor_is_one
;
1368 prolog_key
->instance_divisor_is_fetched
= elts
->instance_divisor_is_fetched
;
1369 prolog_key
->unpack_instance_id_from_vertex_id
=
1370 sctx
->prim_discard_cs_instancing
;
1372 /* Prefer a monolithic shader to allow scheduling divisions around
1374 if (prolog_key
->instance_divisor_is_fetched
)
1375 key
->opt
.prefer_mono
= 1;
1377 unsigned count
= MIN2(vs
->info
.num_inputs
, elts
->count
);
1378 unsigned count_mask
= (1 << count
) - 1;
1379 unsigned fix
= elts
->fix_fetch_always
& count_mask
;
1380 unsigned opencode
= elts
->fix_fetch_opencode
& count_mask
;
1382 if (sctx
->vertex_buffer_unaligned
& elts
->vb_alignment_check_mask
) {
1383 uint32_t mask
= elts
->fix_fetch_unaligned
& count_mask
;
1385 unsigned i
= u_bit_scan(&mask
);
1386 unsigned log_hw_load_size
= 1 + ((elts
->hw_load_is_dword
>> i
) & 1);
1387 unsigned vbidx
= elts
->vertex_buffer_index
[i
];
1388 struct pipe_vertex_buffer
*vb
= &sctx
->vertex_buffer
[vbidx
];
1389 unsigned align_mask
= (1 << log_hw_load_size
) - 1;
1390 if (vb
->buffer_offset
& align_mask
||
1391 vb
->stride
& align_mask
) {
1399 unsigned i
= u_bit_scan(&fix
);
1400 key
->mono
.vs_fix_fetch
[i
].bits
= elts
->fix_fetch
[i
];
1402 key
->mono
.vs_fetch_opencode
= opencode
;
1405 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1406 struct si_shader_selector
*vs
,
1407 struct si_shader_key
*key
)
1409 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1411 key
->opt
.clip_disable
=
1412 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1413 (vs
->info
.clipdist_writemask
||
1414 vs
->info
.writes_clipvertex
) &&
1415 !vs
->info
.culldist_writemask
;
1417 /* Find out if PS is disabled. */
1418 bool ps_disabled
= true;
1420 const struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1421 bool alpha_to_coverage
= blend
&& blend
->alpha_to_coverage
;
1422 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1423 ps
->info
.writes_z
||
1424 ps
->info
.writes_stencil
||
1425 ps
->info
.writes_samplemask
||
1426 alpha_to_coverage
||
1427 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1428 unsigned ps_colormask
= si_get_total_colormask(sctx
);
1430 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1433 !ps
->info
.writes_memory
);
1436 /* Find out which VS outputs aren't used by the PS. */
1437 uint64_t outputs_written
= vs
->outputs_written_before_ps
;
1438 uint64_t inputs_read
= 0;
1440 /* Ignore outputs that are not passed from VS to PS. */
1441 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION
, 0, true)) |
1442 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE
, 0, true)) |
1443 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX
, 0, true)));
1446 inputs_read
= ps
->inputs_read
;
1449 uint64_t linked
= outputs_written
& inputs_read
;
1451 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1454 /* Compute the key for the hw shader variant */
1455 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1456 struct si_shader_selector
*sel
,
1457 struct si_shader_key
*key
)
1459 struct si_context
*sctx
= (struct si_context
*)ctx
;
1461 memset(key
, 0, sizeof(*key
));
1463 switch (sel
->type
) {
1464 case PIPE_SHADER_VERTEX
:
1465 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1467 if (sctx
->tes_shader
.cso
)
1469 else if (sctx
->gs_shader
.cso
)
1472 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1474 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1475 key
->mono
.u
.vs_export_prim_id
= 1;
1478 case PIPE_SHADER_TESS_CTRL
:
1479 if (sctx
->chip_class
>= GFX9
) {
1480 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1481 key
, &key
->part
.tcs
.ls_prolog
);
1482 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1484 /* When the LS VGPR fix is needed, monolithic shaders
1486 * - avoid initializing EXEC in both the LS prolog
1487 * and the LS main part when !vs_needs_prolog
1488 * - remove the fixup for unused input VGPRs
1490 key
->part
.tcs
.ls_prolog
.ls_vgpr_fix
= sctx
->ls_vgpr_fix
;
1492 /* The LS output / HS input layout can be communicated
1493 * directly instead of via user SGPRs for merged LS-HS.
1494 * The LS VGPR fix prefers this too.
1496 key
->opt
.prefer_mono
= 1;
1499 key
->part
.tcs
.epilog
.prim_mode
=
1500 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1501 key
->part
.tcs
.epilog
.invoc0_tess_factors_are_def
=
1502 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1503 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1504 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1506 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1507 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1509 case PIPE_SHADER_TESS_EVAL
:
1510 if (sctx
->gs_shader
.cso
)
1513 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1515 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1516 key
->mono
.u
.vs_export_prim_id
= 1;
1519 case PIPE_SHADER_GEOMETRY
:
1520 if (sctx
->chip_class
>= GFX9
) {
1521 if (sctx
->tes_shader
.cso
) {
1522 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1524 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1525 key
, &key
->part
.gs
.vs_prolog
);
1526 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1527 key
->part
.gs
.prolog
.gfx9_prev_is_vs
= 1;
1530 /* Merged ES-GS can have unbalanced wave usage.
1532 * ES threads are per-vertex, while GS threads are
1533 * per-primitive. So without any amplification, there
1534 * are fewer GS threads than ES threads, which can result
1535 * in empty (no-op) GS waves. With too much amplification,
1536 * there are more GS threads than ES threads, which
1537 * can result in empty (no-op) ES waves.
1539 * Non-monolithic shaders are implemented by setting EXEC
1540 * at the beginning of shader parts, and don't jump to
1541 * the end if EXEC is 0.
1543 * Monolithic shaders use conditional blocks, so they can
1544 * jump and skip empty waves of ES or GS. So set this to
1545 * always use optimized variants, which are monolithic.
1547 key
->opt
.prefer_mono
= 1;
1549 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1551 case PIPE_SHADER_FRAGMENT
: {
1552 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1553 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1555 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1556 sel
->info
.colors_written
== 0x1)
1557 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1560 /* Select the shader color format based on whether
1561 * blending or alpha are needed.
1563 key
->part
.ps
.epilog
.spi_shader_col_format
=
1564 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1565 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1566 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1567 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1568 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1569 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1570 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1571 sctx
->framebuffer
.spi_shader_col_format
);
1572 key
->part
.ps
.epilog
.spi_shader_col_format
&= blend
->cb_target_enabled_4bit
;
1574 /* The output for dual source blending should have
1575 * the same format as the first output.
1577 if (blend
->dual_src_blend
)
1578 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1579 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1581 key
->part
.ps
.epilog
.spi_shader_col_format
= sctx
->framebuffer
.spi_shader_col_format
;
1583 /* If alpha-to-coverage is enabled, we have to export alpha
1584 * even if there is no color buffer.
1586 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1587 blend
&& blend
->alpha_to_coverage
)
1588 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1590 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1591 * to the range supported by the type if a channel has less
1592 * than 16 bits and the export format is 16_ABGR.
1594 if (sctx
->chip_class
<= GFX7
&& sctx
->family
!= CHIP_HAWAII
) {
1595 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1596 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1599 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1600 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1601 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1602 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1603 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1606 bool is_poly
= !util_prim_is_points_or_lines(sctx
->current_rast_prim
);
1607 bool is_line
= util_prim_is_lines(sctx
->current_rast_prim
);
1609 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1610 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1612 if (sctx
->queued
.named
.blend
) {
1613 key
->part
.ps
.epilog
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
1614 rs
->multisample_enable
;
1617 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1618 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1619 (is_line
&& rs
->line_smooth
)) &&
1620 sctx
->framebuffer
.nr_samples
<= 1;
1621 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1623 if (sctx
->ps_iter_samples
> 1 &&
1624 sel
->info
.reads_samplemask
) {
1625 key
->part
.ps
.prolog
.samplemask_log_ps_iter
=
1626 util_logbase2(sctx
->ps_iter_samples
);
1629 if (rs
->force_persample_interp
&&
1630 rs
->multisample_enable
&&
1631 sctx
->framebuffer
.nr_samples
> 1 &&
1632 sctx
->ps_iter_samples
> 1) {
1633 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1634 sel
->info
.uses_persp_center
||
1635 sel
->info
.uses_persp_centroid
;
1637 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1638 sel
->info
.uses_linear_center
||
1639 sel
->info
.uses_linear_centroid
;
1640 } else if (rs
->multisample_enable
&&
1641 sctx
->framebuffer
.nr_samples
> 1) {
1642 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
1643 sel
->info
.uses_persp_center
&&
1644 sel
->info
.uses_persp_centroid
;
1645 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
1646 sel
->info
.uses_linear_center
&&
1647 sel
->info
.uses_linear_centroid
;
1649 /* Make sure SPI doesn't compute more than 1 pair
1650 * of (i,j), which is the optimization here. */
1651 key
->part
.ps
.prolog
.force_persp_center_interp
=
1652 sel
->info
.uses_persp_center
+
1653 sel
->info
.uses_persp_centroid
+
1654 sel
->info
.uses_persp_sample
> 1;
1656 key
->part
.ps
.prolog
.force_linear_center_interp
=
1657 sel
->info
.uses_linear_center
+
1658 sel
->info
.uses_linear_centroid
+
1659 sel
->info
.uses_linear_sample
> 1;
1661 if (sel
->info
.opcode_count
[TGSI_OPCODE_INTERP_SAMPLE
])
1662 key
->mono
.u
.ps
.interpolate_at_sample_force_center
= 1;
1665 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
1667 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1668 if (sctx
->ps_uses_fbfetch
&& !sctx
->blitter
->running
) {
1669 struct pipe_surface
*cb0
= sctx
->framebuffer
.state
.cbufs
[0];
1670 struct pipe_resource
*tex
= cb0
->texture
;
1672 /* 1D textures are allocated and used as 2D on GFX9. */
1673 key
->mono
.u
.ps
.fbfetch_msaa
= sctx
->framebuffer
.nr_samples
> 1;
1674 key
->mono
.u
.ps
.fbfetch_is_1D
= sctx
->chip_class
!= GFX9
&&
1675 (tex
->target
== PIPE_TEXTURE_1D
||
1676 tex
->target
== PIPE_TEXTURE_1D_ARRAY
);
1677 key
->mono
.u
.ps
.fbfetch_layered
= tex
->target
== PIPE_TEXTURE_1D_ARRAY
||
1678 tex
->target
== PIPE_TEXTURE_2D_ARRAY
||
1679 tex
->target
== PIPE_TEXTURE_CUBE
||
1680 tex
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
1681 tex
->target
== PIPE_TEXTURE_3D
;
1689 if (unlikely(sctx
->screen
->debug_flags
& DBG(NO_OPT_VARIANT
)))
1690 memset(&key
->opt
, 0, sizeof(key
->opt
));
1693 static void si_build_shader_variant(struct si_shader
*shader
,
1697 struct si_shader_selector
*sel
= shader
->selector
;
1698 struct si_screen
*sscreen
= sel
->screen
;
1699 struct ac_llvm_compiler
*compiler
;
1700 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
1702 if (thread_index
>= 0) {
1704 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler_lowp
));
1705 compiler
= &sscreen
->compiler_lowp
[thread_index
];
1707 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
1708 compiler
= &sscreen
->compiler
[thread_index
];
1713 assert(!low_priority
);
1714 compiler
= shader
->compiler_ctx_state
.compiler
;
1717 if (unlikely(!si_shader_create(sscreen
, compiler
, shader
, debug
))) {
1718 PRINT_ERR("Failed to build shader variant (type=%u)\n",
1720 shader
->compilation_failed
= true;
1724 if (shader
->compiler_ctx_state
.is_debug_context
) {
1725 FILE *f
= open_memstream(&shader
->shader_log
,
1726 &shader
->shader_log_size
);
1728 si_shader_dump(sscreen
, shader
, NULL
, sel
->type
, f
, false);
1733 si_shader_init_pm4_state(sscreen
, shader
);
1736 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
1738 struct si_shader
*shader
= (struct si_shader
*)job
;
1740 assert(thread_index
>= 0);
1742 si_build_shader_variant(shader
, thread_index
, true);
1745 static const struct si_shader_key zeroed
;
1747 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
1748 struct si_shader_selector
*sel
,
1749 struct si_compiler_ctx_state
*compiler_state
,
1750 struct si_shader_key
*key
)
1752 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
1755 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
1760 /* We can leave the fence as permanently signaled because the
1761 * main part becomes visible globally only after it has been
1763 util_queue_fence_init(&main_part
->ready
);
1765 main_part
->selector
= sel
;
1766 main_part
->key
.as_es
= key
->as_es
;
1767 main_part
->key
.as_ls
= key
->as_ls
;
1768 main_part
->is_monolithic
= false;
1770 if (si_compile_tgsi_shader(sscreen
, compiler_state
->compiler
,
1771 main_part
, &compiler_state
->debug
) != 0) {
1781 * Select a shader variant according to the shader key.
1783 * \param optimized_or_none If the key describes an optimized shader variant and
1784 * the compilation isn't finished, don't select any
1785 * shader and return an error.
1787 int si_shader_select_with_key(struct si_screen
*sscreen
,
1788 struct si_shader_ctx_state
*state
,
1789 struct si_compiler_ctx_state
*compiler_state
,
1790 struct si_shader_key
*key
,
1792 bool optimized_or_none
)
1794 struct si_shader_selector
*sel
= state
->cso
;
1795 struct si_shader_selector
*previous_stage_sel
= NULL
;
1796 struct si_shader
*current
= state
->current
;
1797 struct si_shader
*iter
, *shader
= NULL
;
1800 /* Check if we don't need to change anything.
1801 * This path is also used for most shaders that don't need multiple
1802 * variants, it will cost just a computation of the key and this
1804 if (likely(current
&&
1805 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0)) {
1806 if (unlikely(!util_queue_fence_is_signalled(¤t
->ready
))) {
1807 if (current
->is_optimized
) {
1808 if (optimized_or_none
)
1811 memset(&key
->opt
, 0, sizeof(key
->opt
));
1812 goto current_not_ready
;
1815 util_queue_fence_wait(¤t
->ready
);
1818 return current
->compilation_failed
? -1 : 0;
1822 /* This must be done before the mutex is locked, because async GS
1823 * compilation calls this function too, and therefore must enter
1826 * Only wait if we are in a draw call. Don't wait if we are
1827 * in a compiler thread.
1829 if (thread_index
< 0)
1830 util_queue_fence_wait(&sel
->ready
);
1832 mtx_lock(&sel
->mutex
);
1834 /* Find the shader variant. */
1835 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
1836 /* Don't check the "current" shader. We checked it above. */
1837 if (current
!= iter
&&
1838 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
1839 mtx_unlock(&sel
->mutex
);
1841 if (unlikely(!util_queue_fence_is_signalled(&iter
->ready
))) {
1842 /* If it's an optimized shader and its compilation has
1843 * been started but isn't done, use the unoptimized
1844 * shader so as not to cause a stall due to compilation.
1846 if (iter
->is_optimized
) {
1847 if (optimized_or_none
)
1849 memset(&key
->opt
, 0, sizeof(key
->opt
));
1853 util_queue_fence_wait(&iter
->ready
);
1856 if (iter
->compilation_failed
) {
1857 return -1; /* skip the draw call */
1860 state
->current
= iter
;
1865 /* Build a new shader. */
1866 shader
= CALLOC_STRUCT(si_shader
);
1868 mtx_unlock(&sel
->mutex
);
1872 util_queue_fence_init(&shader
->ready
);
1874 shader
->selector
= sel
;
1876 shader
->compiler_ctx_state
= *compiler_state
;
1878 /* If this is a merged shader, get the first shader's selector. */
1879 if (sscreen
->info
.chip_class
>= GFX9
) {
1880 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1881 previous_stage_sel
= key
->part
.tcs
.ls
;
1882 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1883 previous_stage_sel
= key
->part
.gs
.es
;
1885 /* We need to wait for the previous shader. */
1886 if (previous_stage_sel
&& thread_index
< 0)
1887 util_queue_fence_wait(&previous_stage_sel
->ready
);
1890 bool is_pure_monolithic
=
1891 sscreen
->use_monolithic_shaders
||
1892 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
1894 /* Compile the main shader part if it doesn't exist. This can happen
1895 * if the initial guess was wrong.
1897 * The prim discard CS doesn't need the main shader part.
1899 if (!is_pure_monolithic
&&
1900 !key
->opt
.vs_as_prim_discard_cs
) {
1903 /* Make sure the main shader part is present. This is needed
1904 * for shaders that can be compiled as VS, LS, or ES, and only
1905 * one of them is compiled at creation.
1907 * For merged shaders, check that the starting shader's main
1910 if (previous_stage_sel
) {
1911 struct si_shader_key shader1_key
= zeroed
;
1913 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1914 shader1_key
.as_ls
= 1;
1915 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1916 shader1_key
.as_es
= 1;
1920 mtx_lock(&previous_stage_sel
->mutex
);
1921 ok
= si_check_missing_main_part(sscreen
,
1923 compiler_state
, &shader1_key
);
1924 mtx_unlock(&previous_stage_sel
->mutex
);
1926 ok
= si_check_missing_main_part(sscreen
, sel
,
1927 compiler_state
, key
);
1931 mtx_unlock(&sel
->mutex
);
1932 return -ENOMEM
; /* skip the draw call */
1936 /* Keep the reference to the 1st shader of merged shaders, so that
1937 * Gallium can't destroy it before we destroy the 2nd shader.
1939 * Set sctx = NULL, because it's unused if we're not releasing
1940 * the shader, and we don't have any sctx here.
1942 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
1943 previous_stage_sel
);
1945 /* Monolithic-only shaders don't make a distinction between optimized
1946 * and unoptimized. */
1947 shader
->is_monolithic
=
1948 is_pure_monolithic
||
1949 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1951 /* The prim discard CS is always optimized. */
1952 shader
->is_optimized
=
1953 (!is_pure_monolithic
|| key
->opt
.vs_as_prim_discard_cs
) &&
1954 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1956 /* If it's an optimized shader, compile it asynchronously. */
1957 if (shader
->is_optimized
&& thread_index
< 0) {
1958 /* Compile it asynchronously. */
1959 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
,
1960 shader
, &shader
->ready
,
1961 si_build_shader_variant_low_priority
, NULL
);
1963 /* Add only after the ready fence was reset, to guard against a
1964 * race with si_bind_XX_shader. */
1965 if (!sel
->last_variant
) {
1966 sel
->first_variant
= shader
;
1967 sel
->last_variant
= shader
;
1969 sel
->last_variant
->next_variant
= shader
;
1970 sel
->last_variant
= shader
;
1973 /* Use the default (unoptimized) shader for now. */
1974 memset(&key
->opt
, 0, sizeof(key
->opt
));
1975 mtx_unlock(&sel
->mutex
);
1977 if (sscreen
->options
.sync_compile
)
1978 util_queue_fence_wait(&shader
->ready
);
1980 if (optimized_or_none
)
1985 /* Reset the fence before adding to the variant list. */
1986 util_queue_fence_reset(&shader
->ready
);
1988 if (!sel
->last_variant
) {
1989 sel
->first_variant
= shader
;
1990 sel
->last_variant
= shader
;
1992 sel
->last_variant
->next_variant
= shader
;
1993 sel
->last_variant
= shader
;
1996 mtx_unlock(&sel
->mutex
);
1998 assert(!shader
->is_optimized
);
1999 si_build_shader_variant(shader
, thread_index
, false);
2001 util_queue_fence_signal(&shader
->ready
);
2003 if (!shader
->compilation_failed
)
2004 state
->current
= shader
;
2006 return shader
->compilation_failed
? -1 : 0;
2009 static int si_shader_select(struct pipe_context
*ctx
,
2010 struct si_shader_ctx_state
*state
,
2011 struct si_compiler_ctx_state
*compiler_state
)
2013 struct si_context
*sctx
= (struct si_context
*)ctx
;
2014 struct si_shader_key key
;
2016 si_shader_selector_key(ctx
, state
->cso
, &key
);
2017 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
2021 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
2023 struct si_shader_key
*key
)
2025 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
2027 switch (info
->processor
) {
2028 case PIPE_SHADER_VERTEX
:
2029 switch (next_shader
) {
2030 case PIPE_SHADER_GEOMETRY
:
2033 case PIPE_SHADER_TESS_CTRL
:
2034 case PIPE_SHADER_TESS_EVAL
:
2038 /* If POSITION isn't written, it can only be a HW VS
2039 * if streamout is used. If streamout isn't used,
2040 * assume that it's a HW LS. (the next shader is TCS)
2041 * This heuristic is needed for separate shader objects.
2043 if (!info
->writes_position
&& !streamout
)
2048 case PIPE_SHADER_TESS_EVAL
:
2049 if (next_shader
== PIPE_SHADER_GEOMETRY
||
2050 !info
->writes_position
)
2057 * Compile the main shader part or the monolithic shader as part of
2058 * si_shader_selector initialization. Since it can be done asynchronously,
2059 * there is no way to report compile failures to applications.
2061 static void si_init_shader_selector_async(void *job
, int thread_index
)
2063 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
2064 struct si_screen
*sscreen
= sel
->screen
;
2065 struct ac_llvm_compiler
*compiler
;
2066 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
2068 assert(!debug
->debug_message
|| debug
->async
);
2069 assert(thread_index
>= 0);
2070 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2071 compiler
= &sscreen
->compiler
[thread_index
];
2076 /* Compile the main shader part for use with a prolog and/or epilog.
2077 * If this fails, the driver will try to compile a monolithic shader
2080 if (!sscreen
->use_monolithic_shaders
) {
2081 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
2082 void *ir_binary
= NULL
;
2085 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
2089 /* We can leave the fence signaled because use of the default
2090 * main part is guarded by the selector's ready fence. */
2091 util_queue_fence_init(&shader
->ready
);
2093 shader
->selector
= sel
;
2094 shader
->is_monolithic
= false;
2095 si_parse_next_shader_property(&sel
->info
,
2096 sel
->so
.num_outputs
!= 0,
2099 if (sel
->tokens
|| sel
->nir
)
2100 ir_binary
= si_get_ir_binary(sel
);
2102 /* Try to load the shader from the shader cache. */
2103 mtx_lock(&sscreen
->shader_cache_mutex
);
2106 si_shader_cache_load_shader(sscreen
, ir_binary
, shader
)) {
2107 mtx_unlock(&sscreen
->shader_cache_mutex
);
2108 si_shader_dump_stats_for_shader_db(sscreen
, shader
, debug
);
2110 mtx_unlock(&sscreen
->shader_cache_mutex
);
2112 /* Compile the shader if it hasn't been loaded from the cache. */
2113 if (si_compile_tgsi_shader(sscreen
, compiler
, shader
,
2117 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
2122 mtx_lock(&sscreen
->shader_cache_mutex
);
2123 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
, shader
, true))
2125 mtx_unlock(&sscreen
->shader_cache_mutex
);
2129 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
2131 /* Unset "outputs_written" flags for outputs converted to
2132 * DEFAULT_VAL, so that later inter-shader optimizations don't
2133 * try to eliminate outputs that don't exist in the final
2136 * This is only done if non-monolithic shaders are enabled.
2138 if ((sel
->type
== PIPE_SHADER_VERTEX
||
2139 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
2140 !shader
->key
.as_ls
&&
2141 !shader
->key
.as_es
) {
2144 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2145 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
2147 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
2150 unsigned name
= sel
->info
.output_semantic_name
[i
];
2151 unsigned index
= sel
->info
.output_semantic_index
[i
];
2155 case TGSI_SEMANTIC_GENERIC
:
2156 /* don't process indices the function can't handle */
2157 if (index
>= SI_MAX_IO_GENERIC
)
2161 id
= si_shader_io_get_unique_index(name
, index
, true);
2162 sel
->outputs_written_before_ps
&= ~(1ull << id
);
2164 case TGSI_SEMANTIC_POSITION
: /* ignore these */
2165 case TGSI_SEMANTIC_PSIZE
:
2166 case TGSI_SEMANTIC_CLIPVERTEX
:
2167 case TGSI_SEMANTIC_EDGEFLAG
:
2174 /* The GS copy shader is always pre-compiled. */
2175 if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
2176 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, compiler
, sel
, debug
);
2177 if (!sel
->gs_copy_shader
) {
2178 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
2182 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
2186 void si_schedule_initial_compile(struct si_context
*sctx
, unsigned processor
,
2187 struct util_queue_fence
*ready_fence
,
2188 struct si_compiler_ctx_state
*compiler_ctx_state
,
2189 void *job
, util_queue_execute_func execute
)
2191 util_queue_fence_init(ready_fence
);
2193 struct util_async_debug_callback async_debug
;
2195 (sctx
->debug
.debug_message
&& !sctx
->debug
.async
) ||
2197 si_can_dump_shader(sctx
->screen
, processor
);
2200 u_async_debug_init(&async_debug
);
2201 compiler_ctx_state
->debug
= async_debug
.base
;
2204 util_queue_add_job(&sctx
->screen
->shader_compiler_queue
, job
,
2205 ready_fence
, execute
, NULL
);
2208 util_queue_fence_wait(ready_fence
);
2209 u_async_debug_drain(&async_debug
, &sctx
->debug
);
2210 u_async_debug_cleanup(&async_debug
);
2213 if (sctx
->screen
->options
.sync_compile
)
2214 util_queue_fence_wait(ready_fence
);
2217 /* Return descriptor slot usage masks from the given shader info. */
2218 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
2219 uint32_t *const_and_shader_buffers
,
2220 uint64_t *samplers_and_images
)
2222 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_samplers
;
2224 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
2225 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
2226 /* two 8-byte images share one 16-byte slot */
2227 num_images
= align(util_last_bit(info
->images_declared
), 2);
2228 num_samplers
= util_last_bit(info
->samplers_declared
);
2230 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2231 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
2232 *const_and_shader_buffers
=
2233 u_bit_consecutive(start
, num_shaderbufs
+ num_constbufs
);
2235 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2236 start
= si_get_image_slot(num_images
- 1) / 2;
2237 *samplers_and_images
=
2238 u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
2241 static void *si_create_shader_selector(struct pipe_context
*ctx
,
2242 const struct pipe_shader_state
*state
)
2244 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
2245 struct si_context
*sctx
= (struct si_context
*)ctx
;
2246 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
2252 pipe_reference_init(&sel
->reference
, 1);
2253 sel
->screen
= sscreen
;
2254 sel
->compiler_ctx_state
.debug
= sctx
->debug
;
2255 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
2257 sel
->so
= state
->stream_output
;
2259 if (state
->type
== PIPE_SHADER_IR_TGSI
) {
2260 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
2266 tgsi_scan_shader(state
->tokens
, &sel
->info
);
2267 tgsi_scan_tess_ctrl(state
->tokens
, &sel
->info
, &sel
->tcs_info
);
2269 assert(state
->type
== PIPE_SHADER_IR_NIR
);
2271 sel
->nir
= state
->ir
.nir
;
2273 si_nir_opts(sel
->nir
);
2274 si_nir_scan_shader(sel
->nir
, &sel
->info
);
2275 si_nir_scan_tess_ctrl(sel
->nir
, &sel
->tcs_info
);
2278 sel
->type
= sel
->info
.processor
;
2279 p_atomic_inc(&sscreen
->num_shaders_created
);
2280 si_get_active_slot_masks(&sel
->info
,
2281 &sel
->active_const_and_shader_buffers
,
2282 &sel
->active_samplers_and_images
);
2284 /* Record which streamout buffers are enabled. */
2285 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
2286 sel
->enabled_streamout_buffer_mask
|=
2287 (1 << sel
->so
.output
[i
].output_buffer
) <<
2288 (sel
->so
.output
[i
].stream
* 4);
2291 /* The prolog is a no-op if there are no inputs. */
2292 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
2293 sel
->info
.num_inputs
&&
2294 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
2296 sel
->force_correct_derivs_after_kill
=
2297 sel
->type
== PIPE_SHADER_FRAGMENT
&&
2298 sel
->info
.uses_derivatives
&&
2299 sel
->info
.uses_kill
&&
2300 sctx
->screen
->debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
2302 sel
->prim_discard_cs_allowed
=
2303 sel
->type
== PIPE_SHADER_VERTEX
&&
2304 !sel
->info
.uses_bindless_images
&&
2305 !sel
->info
.uses_bindless_samplers
&&
2306 !sel
->info
.writes_memory
&&
2307 !sel
->info
.writes_viewport_index
&&
2308 !sel
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] &&
2309 !sel
->so
.num_outputs
;
2311 /* Set which opcode uses which (i,j) pair. */
2312 if (sel
->info
.uses_persp_opcode_interp_centroid
)
2313 sel
->info
.uses_persp_centroid
= true;
2315 if (sel
->info
.uses_linear_opcode_interp_centroid
)
2316 sel
->info
.uses_linear_centroid
= true;
2318 if (sel
->info
.uses_persp_opcode_interp_offset
||
2319 sel
->info
.uses_persp_opcode_interp_sample
)
2320 sel
->info
.uses_persp_center
= true;
2322 if (sel
->info
.uses_linear_opcode_interp_offset
||
2323 sel
->info
.uses_linear_opcode_interp_sample
)
2324 sel
->info
.uses_linear_center
= true;
2326 switch (sel
->type
) {
2327 case PIPE_SHADER_GEOMETRY
:
2328 sel
->gs_output_prim
=
2329 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
2330 sel
->gs_max_out_vertices
=
2331 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
2332 sel
->gs_num_invocations
=
2333 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2334 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2335 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
2336 sel
->gs_max_out_vertices
;
2338 sel
->max_gs_stream
= 0;
2339 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2340 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
2341 sel
->so
.output
[i
].stream
);
2343 sel
->gs_input_verts_per_prim
=
2344 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2347 case PIPE_SHADER_TESS_CTRL
:
2348 /* Always reserve space for these. */
2349 sel
->patch_outputs_written
|=
2350 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0)) |
2351 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0));
2353 case PIPE_SHADER_VERTEX
:
2354 case PIPE_SHADER_TESS_EVAL
:
2355 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2356 unsigned name
= sel
->info
.output_semantic_name
[i
];
2357 unsigned index
= sel
->info
.output_semantic_index
[i
];
2360 case TGSI_SEMANTIC_TESSINNER
:
2361 case TGSI_SEMANTIC_TESSOUTER
:
2362 case TGSI_SEMANTIC_PATCH
:
2363 sel
->patch_outputs_written
|=
2364 1ull << si_shader_io_get_unique_index_patch(name
, index
);
2367 case TGSI_SEMANTIC_GENERIC
:
2368 /* don't process indices the function can't handle */
2369 if (index
>= SI_MAX_IO_GENERIC
)
2373 sel
->outputs_written
|=
2374 1ull << si_shader_io_get_unique_index(name
, index
, false);
2375 sel
->outputs_written_before_ps
|=
2376 1ull << si_shader_io_get_unique_index(name
, index
, true);
2378 case TGSI_SEMANTIC_EDGEFLAG
:
2382 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2383 sel
->lshs_vertex_stride
= sel
->esgs_itemsize
;
2385 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2386 * will start on a different bank. (except for the maximum 32*16).
2388 if (sel
->lshs_vertex_stride
< 32*16)
2389 sel
->lshs_vertex_stride
+= 4;
2391 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2392 * conflicts, i.e. each vertex will start at a different bank.
2394 if (sctx
->chip_class
>= GFX9
)
2395 sel
->esgs_itemsize
+= 4;
2397 assert(((sel
->esgs_itemsize
/ 4) & C_028AAC_ITEMSIZE
) == 0);
2400 case PIPE_SHADER_FRAGMENT
:
2401 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2402 unsigned name
= sel
->info
.input_semantic_name
[i
];
2403 unsigned index
= sel
->info
.input_semantic_index
[i
];
2406 case TGSI_SEMANTIC_GENERIC
:
2407 /* don't process indices the function can't handle */
2408 if (index
>= SI_MAX_IO_GENERIC
)
2413 1ull << si_shader_io_get_unique_index(name
, index
, true);
2415 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2420 for (i
= 0; i
< 8; i
++)
2421 if (sel
->info
.colors_written
& (1 << i
))
2422 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2424 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2425 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2426 int index
= sel
->info
.input_semantic_index
[i
];
2427 sel
->color_attr_index
[index
] = i
;
2433 /* PA_CL_VS_OUT_CNTL */
2435 sel
->info
.writes_psize
|| sel
->info
.writes_edgeflag
||
2436 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
2437 sel
->pa_cl_vs_out_cntl
=
2438 S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
2439 S_02881C_USE_VTX_EDGE_FLAG(sel
->info
.writes_edgeflag
) |
2440 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
2441 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
2442 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
2443 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
2444 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
?
2445 SIX_BITS
: sel
->info
.clipdist_writemask
;
2446 sel
->culldist_mask
= sel
->info
.culldist_writemask
<<
2447 sel
->info
.num_written_clipdistance
;
2449 /* DB_SHADER_CONTROL */
2450 sel
->db_shader_control
=
2451 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2452 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2453 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2454 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2456 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2457 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2458 sel
->db_shader_control
|=
2459 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2461 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2462 sel
->db_shader_control
|=
2463 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2467 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2469 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2470 * --|-----------|------------|------------|--------------------|-------------------|-------------
2471 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2472 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2473 * 2 | false | true | n/a | LateZ | 1 | 0
2474 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2475 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2477 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2478 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2480 * Don't use ReZ without profiling !!!
2482 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2485 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2487 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2488 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2489 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
2490 } else if (sel
->info
.writes_memory
) {
2492 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
2493 S_02880C_EXEC_ON_HIER_FAIL(1);
2496 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2499 (void) mtx_init(&sel
->mutex
, mtx_plain
);
2501 si_schedule_initial_compile(sctx
, sel
->info
.processor
, &sel
->ready
,
2502 &sel
->compiler_ctx_state
, sel
,
2503 si_init_shader_selector_async
);
2507 static void si_update_streamout_state(struct si_context
*sctx
)
2509 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
2511 if (!shader_with_so
)
2514 sctx
->streamout
.enabled_stream_buffers_mask
=
2515 shader_with_so
->enabled_streamout_buffer_mask
;
2516 sctx
->streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
2519 static void si_update_clip_regs(struct si_context
*sctx
,
2520 struct si_shader_selector
*old_hw_vs
,
2521 struct si_shader
*old_hw_vs_variant
,
2522 struct si_shader_selector
*next_hw_vs
,
2523 struct si_shader
*next_hw_vs_variant
)
2527 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
2528 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
2529 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
2530 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
2531 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
||
2532 !old_hw_vs_variant
||
2533 !next_hw_vs_variant
||
2534 old_hw_vs_variant
->key
.opt
.clip_disable
!=
2535 next_hw_vs_variant
->key
.opt
.clip_disable
))
2536 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
2539 static void si_update_common_shader_state(struct si_context
*sctx
)
2541 sctx
->uses_bindless_samplers
=
2542 si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
2543 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
2544 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
2545 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
2546 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
2547 sctx
->uses_bindless_images
=
2548 si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
2549 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
2550 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
2551 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
2552 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
2553 sctx
->do_update_shaders
= true;
2556 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2558 struct si_context
*sctx
= (struct si_context
*)ctx
;
2559 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2560 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2561 struct si_shader_selector
*sel
= state
;
2563 if (sctx
->vs_shader
.cso
== sel
)
2566 sctx
->vs_shader
.cso
= sel
;
2567 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2568 sctx
->num_vs_blit_sgprs
= sel
? sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
] : 0;
2570 si_update_common_shader_state(sctx
);
2571 si_update_vs_viewport_state(sctx
);
2572 si_set_active_descriptors_for_shader(sctx
, sel
);
2573 si_update_streamout_state(sctx
);
2574 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2575 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2578 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
2580 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
2581 (sctx
->tes_shader
.cso
&&
2582 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
2583 (sctx
->tcs_shader
.cso
&&
2584 sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
2585 (sctx
->gs_shader
.cso
&&
2586 sctx
->gs_shader
.cso
->info
.uses_primid
) ||
2587 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&&
2588 sctx
->ps_shader
.cso
->info
.uses_primid
);
2591 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
2593 struct si_context
*sctx
= (struct si_context
*)ctx
;
2594 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2595 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2596 struct si_shader_selector
*sel
= state
;
2597 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
2599 if (sctx
->gs_shader
.cso
== sel
)
2602 sctx
->gs_shader
.cso
= sel
;
2603 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2604 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
2606 si_update_common_shader_state(sctx
);
2607 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2609 if (enable_changed
) {
2610 si_shader_change_notify(sctx
);
2611 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2612 si_update_tess_uses_prim_id(sctx
);
2614 si_update_vs_viewport_state(sctx
);
2615 si_set_active_descriptors_for_shader(sctx
, sel
);
2616 si_update_streamout_state(sctx
);
2617 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2618 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2621 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
2623 struct si_context
*sctx
= (struct si_context
*)ctx
;
2624 struct si_shader_selector
*sel
= state
;
2625 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
2627 if (sctx
->tcs_shader
.cso
== sel
)
2630 sctx
->tcs_shader
.cso
= sel
;
2631 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2632 si_update_tess_uses_prim_id(sctx
);
2634 si_update_common_shader_state(sctx
);
2637 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
2639 si_set_active_descriptors_for_shader(sctx
, sel
);
2642 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
2644 struct si_context
*sctx
= (struct si_context
*)ctx
;
2645 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2646 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2647 struct si_shader_selector
*sel
= state
;
2648 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
2650 if (sctx
->tes_shader
.cso
== sel
)
2653 sctx
->tes_shader
.cso
= sel
;
2654 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
2655 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
2656 si_update_tess_uses_prim_id(sctx
);
2658 si_update_common_shader_state(sctx
);
2659 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2661 if (enable_changed
) {
2662 si_shader_change_notify(sctx
);
2663 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
2665 si_update_vs_viewport_state(sctx
);
2666 si_set_active_descriptors_for_shader(sctx
, sel
);
2667 si_update_streamout_state(sctx
);
2668 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2669 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2672 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
2674 struct si_context
*sctx
= (struct si_context
*)ctx
;
2675 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
2676 struct si_shader_selector
*sel
= state
;
2678 /* skip if supplied shader is one already in use */
2682 sctx
->ps_shader
.cso
= sel
;
2683 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
2685 si_update_common_shader_state(sctx
);
2687 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2688 si_update_tess_uses_prim_id(sctx
);
2691 old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
2692 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
2694 if (sctx
->screen
->has_out_of_order_rast
&&
2696 old_sel
->info
.writes_memory
!= sel
->info
.writes_memory
||
2697 old_sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] !=
2698 sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]))
2699 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2701 si_set_active_descriptors_for_shader(sctx
, sel
);
2702 si_update_ps_colorbuf0_slot(sctx
);
2705 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
2707 if (shader
->is_optimized
) {
2708 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
,
2712 util_queue_fence_destroy(&shader
->ready
);
2715 switch (shader
->selector
->type
) {
2716 case PIPE_SHADER_VERTEX
:
2717 if (shader
->key
.as_ls
) {
2718 assert(sctx
->chip_class
<= GFX8
);
2719 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
2720 } else if (shader
->key
.as_es
) {
2721 assert(sctx
->chip_class
<= GFX8
);
2722 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2724 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2727 case PIPE_SHADER_TESS_CTRL
:
2728 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
2730 case PIPE_SHADER_TESS_EVAL
:
2731 if (shader
->key
.as_es
) {
2732 assert(sctx
->chip_class
<= GFX8
);
2733 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2735 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2738 case PIPE_SHADER_GEOMETRY
:
2739 if (shader
->is_gs_copy_shader
)
2740 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2742 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
2744 case PIPE_SHADER_FRAGMENT
:
2745 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
2750 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
2751 si_shader_destroy(shader
);
2755 void si_destroy_shader_selector(struct si_context
*sctx
,
2756 struct si_shader_selector
*sel
)
2758 struct si_shader
*p
= sel
->first_variant
, *c
;
2759 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
2760 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
2761 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
2762 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
2763 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
2764 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
2767 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
2769 if (current_shader
[sel
->type
]->cso
== sel
) {
2770 current_shader
[sel
->type
]->cso
= NULL
;
2771 current_shader
[sel
->type
]->current
= NULL
;
2775 c
= p
->next_variant
;
2776 si_delete_shader(sctx
, p
);
2780 if (sel
->main_shader_part
)
2781 si_delete_shader(sctx
, sel
->main_shader_part
);
2782 if (sel
->main_shader_part_ls
)
2783 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
2784 if (sel
->main_shader_part_es
)
2785 si_delete_shader(sctx
, sel
->main_shader_part_es
);
2786 if (sel
->gs_copy_shader
)
2787 si_delete_shader(sctx
, sel
->gs_copy_shader
);
2789 util_queue_fence_destroy(&sel
->ready
);
2790 mtx_destroy(&sel
->mutex
);
2792 ralloc_free(sel
->nir
);
2796 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
2798 struct si_context
*sctx
= (struct si_context
*)ctx
;
2799 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
2801 si_shader_selector_reference(sctx
, &sel
, NULL
);
2804 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
2805 struct si_shader
*vs
, unsigned name
,
2806 unsigned index
, unsigned interpolate
)
2808 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
2809 unsigned j
, offset
, ps_input_cntl
= 0;
2811 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2812 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
) ||
2813 name
== TGSI_SEMANTIC_PRIMID
)
2814 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
2816 if (name
== TGSI_SEMANTIC_PCOORD
||
2817 (name
== TGSI_SEMANTIC_TEXCOORD
&&
2818 sctx
->sprite_coord_enable
& (1 << index
))) {
2819 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
2822 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
2823 if (name
== vsinfo
->output_semantic_name
[j
] &&
2824 index
== vsinfo
->output_semantic_index
[j
]) {
2825 offset
= vs
->info
.vs_output_param_offset
[j
];
2827 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
2828 /* The input is loaded from parameter memory. */
2829 ps_input_cntl
|= S_028644_OFFSET(offset
);
2830 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2831 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
2832 /* This can happen with depth-only rendering. */
2835 /* The input is a DEFAULT_VAL constant. */
2836 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
2837 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
2838 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
2841 ps_input_cntl
= S_028644_OFFSET(0x20) |
2842 S_028644_DEFAULT_VAL(offset
);
2848 if (name
== TGSI_SEMANTIC_PRIMID
)
2849 /* PrimID is written after the last output. */
2850 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
2851 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2852 /* No corresponding output found, load defaults into input.
2853 * Don't set any other bits.
2854 * (FLAT_SHADE=1 completely changes behavior) */
2855 ps_input_cntl
= S_028644_OFFSET(0x20);
2856 /* D3D 9 behaviour. GL is undefined */
2857 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
2858 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
2860 return ps_input_cntl
;
2863 static void si_emit_spi_map(struct si_context
*sctx
)
2865 struct si_shader
*ps
= sctx
->ps_shader
.current
;
2866 struct si_shader
*vs
= si_get_vs_state(sctx
);
2867 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
2868 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
2869 unsigned spi_ps_input_cntl
[32];
2871 if (!ps
|| !ps
->selector
->info
.num_inputs
)
2874 num_interp
= si_get_ps_num_interp(ps
);
2875 assert(num_interp
> 0);
2877 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
2878 unsigned name
= psinfo
->input_semantic_name
[i
];
2879 unsigned index
= psinfo
->input_semantic_index
[i
];
2880 unsigned interpolate
= psinfo
->input_interpolate
[i
];
2882 spi_ps_input_cntl
[num_written
++] = si_get_ps_input_cntl(sctx
, vs
, name
,
2883 index
, interpolate
);
2885 if (name
== TGSI_SEMANTIC_COLOR
) {
2886 assert(index
< ARRAY_SIZE(bcol_interp
));
2887 bcol_interp
[index
] = interpolate
;
2891 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
2892 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
2894 for (i
= 0; i
< 2; i
++) {
2895 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
2898 spi_ps_input_cntl
[num_written
++] =
2899 si_get_ps_input_cntl(sctx
, vs
, bcol
, i
, bcol_interp
[i
]);
2903 assert(num_interp
== num_written
);
2905 /* R_028644_SPI_PS_INPUT_CNTL_0 */
2906 /* Dota 2: Only ~16% of SPI map updates set different values. */
2907 /* Talos: Only ~9% of SPI map updates set different values. */
2908 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
2909 radeon_opt_set_context_regn(sctx
, R_028644_SPI_PS_INPUT_CNTL_0
,
2911 sctx
->tracked_regs
.spi_ps_input_cntl
, num_interp
);
2913 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
2914 sctx
->context_roll
= true;
2918 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2920 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
2922 if (sctx
->init_config_has_vgt_flush
)
2925 /* Done by Vulkan before VGT_FLUSH. */
2926 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2927 si_pm4_cmd_add(sctx
->init_config
,
2928 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2929 si_pm4_cmd_end(sctx
->init_config
, false);
2931 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2932 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2933 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2934 si_pm4_cmd_end(sctx
->init_config
, false);
2935 sctx
->init_config_has_vgt_flush
= true;
2938 /* Initialize state related to ESGS / GSVS ring buffers */
2939 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
2941 struct si_shader_selector
*es
=
2942 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
2943 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
2944 struct si_pm4_state
*pm4
;
2946 /* Chip constants. */
2947 unsigned num_se
= sctx
->screen
->info
.max_se
;
2948 unsigned wave_size
= 64;
2949 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
2950 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
2951 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2953 unsigned gs_vertex_reuse
= (sctx
->chip_class
>= GFX8
? 32 : 16) * num_se
;
2954 unsigned alignment
= 256 * num_se
;
2955 /* The maximum size is 63.999 MB per SE. */
2956 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
2958 /* Calculate the minimum size. */
2959 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
2960 wave_size
, alignment
);
2962 /* These are recommended sizes, not minimum sizes. */
2963 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
2964 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
2965 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
2966 gs
->max_gsvs_emit_size
;
2968 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
2969 esgs_ring_size
= align(esgs_ring_size
, alignment
);
2970 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
2972 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
2973 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
2975 /* Some rings don't have to be allocated if shaders don't use them.
2976 * (e.g. no varyings between ES and GS or GS and VS)
2978 * GFX9 doesn't have the ESGS ring.
2980 bool update_esgs
= sctx
->chip_class
<= GFX8
&&
2982 (!sctx
->esgs_ring
||
2983 sctx
->esgs_ring
->width0
< esgs_ring_size
);
2984 bool update_gsvs
= gsvs_ring_size
&&
2985 (!sctx
->gsvs_ring
||
2986 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
2988 if (!update_esgs
&& !update_gsvs
)
2992 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
2994 pipe_aligned_buffer_create(sctx
->b
.screen
,
2995 SI_RESOURCE_FLAG_UNMAPPABLE
,
2997 esgs_ring_size
, alignment
);
2998 if (!sctx
->esgs_ring
)
3003 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
3005 pipe_aligned_buffer_create(sctx
->b
.screen
,
3006 SI_RESOURCE_FLAG_UNMAPPABLE
,
3008 gsvs_ring_size
, alignment
);
3009 if (!sctx
->gsvs_ring
)
3013 /* Create the "init_config_gs_rings" state. */
3014 pm4
= CALLOC_STRUCT(si_pm4_state
);
3018 if (sctx
->chip_class
>= GFX7
) {
3019 if (sctx
->esgs_ring
) {
3020 assert(sctx
->chip_class
<= GFX8
);
3021 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
3022 sctx
->esgs_ring
->width0
/ 256);
3024 if (sctx
->gsvs_ring
)
3025 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
3026 sctx
->gsvs_ring
->width0
/ 256);
3028 if (sctx
->esgs_ring
)
3029 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
3030 sctx
->esgs_ring
->width0
/ 256);
3031 if (sctx
->gsvs_ring
)
3032 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
3033 sctx
->gsvs_ring
->width0
/ 256);
3036 /* Set the state. */
3037 if (sctx
->init_config_gs_rings
)
3038 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
3039 sctx
->init_config_gs_rings
= pm4
;
3041 if (!sctx
->init_config_has_vgt_flush
) {
3042 si_init_config_add_vgt_flush(sctx
);
3043 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3046 /* Flush the context to re-emit both init_config states. */
3047 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3048 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3050 /* Set ring bindings. */
3051 if (sctx
->esgs_ring
) {
3052 assert(sctx
->chip_class
<= GFX8
);
3053 si_set_ring_buffer(sctx
, SI_ES_RING_ESGS
,
3054 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3055 true, true, 4, 64, 0);
3056 si_set_ring_buffer(sctx
, SI_GS_RING_ESGS
,
3057 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3058 false, false, 0, 0, 0);
3060 if (sctx
->gsvs_ring
) {
3061 si_set_ring_buffer(sctx
, SI_RING_GSVS
,
3062 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
3063 false, false, 0, 0, 0);
3069 static void si_shader_lock(struct si_shader
*shader
)
3071 mtx_lock(&shader
->selector
->mutex
);
3072 if (shader
->previous_stage_sel
) {
3073 assert(shader
->previous_stage_sel
!= shader
->selector
);
3074 mtx_lock(&shader
->previous_stage_sel
->mutex
);
3078 static void si_shader_unlock(struct si_shader
*shader
)
3080 if (shader
->previous_stage_sel
)
3081 mtx_unlock(&shader
->previous_stage_sel
->mutex
);
3082 mtx_unlock(&shader
->selector
->mutex
);
3086 * @returns 1 if \p sel has been updated to use a new scratch buffer
3088 * < 0 if there was a failure
3090 static int si_update_scratch_buffer(struct si_context
*sctx
,
3091 struct si_shader
*shader
)
3093 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
3098 /* This shader doesn't need a scratch buffer */
3099 if (shader
->config
.scratch_bytes_per_wave
== 0)
3102 /* Prevent race conditions when updating:
3103 * - si_shader::scratch_bo
3104 * - si_shader::binary::code
3105 * - si_shader::previous_stage::binary::code.
3107 si_shader_lock(shader
);
3109 /* This shader is already configured to use the current
3110 * scratch buffer. */
3111 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
3112 si_shader_unlock(shader
);
3116 assert(sctx
->scratch_buffer
);
3118 /* Replace the shader bo with a new bo that has the relocs applied. */
3119 if (!si_shader_binary_upload(sctx
->screen
, shader
, scratch_va
)) {
3120 si_shader_unlock(shader
);
3124 /* Update the shader state to use the new shader bo. */
3125 si_shader_init_pm4_state(sctx
->screen
, shader
);
3127 si_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
3129 si_shader_unlock(shader
);
3133 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
3135 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
3138 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
3140 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
3143 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
3145 if (!sctx
->tes_shader
.cso
)
3146 return NULL
; /* tessellation disabled */
3148 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
:
3149 sctx
->fixed_func_tcs_shader
.current
;
3152 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
3156 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
3157 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
3158 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
3159 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
3161 if (sctx
->tes_shader
.cso
) {
3162 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3164 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(tcs
));
3169 static bool si_update_scratch_relocs(struct si_context
*sctx
)
3171 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3174 /* Update the shaders, so that they are using the latest scratch.
3175 * The scratch buffer may have been changed since these shaders were
3176 * last used, so we still need to try to update them, even if they
3177 * require scratch buffers smaller than the current size.
3179 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
3183 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3185 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
3189 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3191 r
= si_update_scratch_buffer(sctx
, tcs
);
3195 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
3197 /* VS can be bound as LS, ES, or VS. */
3198 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
3202 if (sctx
->tes_shader
.current
)
3203 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3204 else if (sctx
->gs_shader
.current
)
3205 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3207 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3210 /* TES can be bound as ES or VS. */
3211 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
3215 if (sctx
->gs_shader
.current
)
3216 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3218 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3224 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
3226 unsigned current_scratch_buffer_size
=
3227 si_get_current_scratch_buffer_size(sctx
);
3228 unsigned scratch_bytes_per_wave
=
3229 si_get_max_scratch_bytes_per_wave(sctx
);
3230 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
3231 sctx
->scratch_waves
;
3232 unsigned spi_tmpring_size
;
3234 if (scratch_needed_size
> 0) {
3235 if (scratch_needed_size
> current_scratch_buffer_size
) {
3236 /* Create a bigger scratch buffer */
3237 si_resource_reference(&sctx
->scratch_buffer
, NULL
);
3239 sctx
->scratch_buffer
=
3240 si_aligned_buffer_create(&sctx
->screen
->b
,
3241 SI_RESOURCE_FLAG_UNMAPPABLE
,
3243 scratch_needed_size
, 256);
3244 if (!sctx
->scratch_buffer
)
3247 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3248 si_context_add_resource_size(sctx
,
3249 &sctx
->scratch_buffer
->b
.b
);
3252 if (!si_update_scratch_relocs(sctx
))
3256 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3257 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
3258 "scratch size should already be aligned correctly.");
3260 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
3261 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
3262 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
3263 sctx
->spi_tmpring_size
= spi_tmpring_size
;
3264 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3269 static void si_init_tess_factor_ring(struct si_context
*sctx
)
3271 assert(!sctx
->tess_rings
);
3273 /* The address must be aligned to 2^19, because the shader only
3274 * receives the high 13 bits.
3276 sctx
->tess_rings
= pipe_aligned_buffer_create(sctx
->b
.screen
,
3277 SI_RESOURCE_FLAG_32BIT
,
3279 sctx
->screen
->tess_offchip_ring_size
+
3280 sctx
->screen
->tess_factor_ring_size
,
3282 if (!sctx
->tess_rings
)
3285 si_init_config_add_vgt_flush(sctx
);
3287 si_pm4_add_bo(sctx
->init_config
, si_resource(sctx
->tess_rings
),
3288 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3290 uint64_t factor_va
= si_resource(sctx
->tess_rings
)->gpu_address
+
3291 sctx
->screen
->tess_offchip_ring_size
;
3293 /* Append these registers to the init config state. */
3294 if (sctx
->chip_class
>= GFX7
) {
3295 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
3296 S_030938_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3297 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
3299 if (sctx
->chip_class
>= GFX9
)
3300 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3301 S_030944_BASE_HI(factor_va
>> 40));
3302 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3303 sctx
->screen
->vgt_hs_offchip_param
);
3305 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
3306 S_008988_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3307 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
3309 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3310 sctx
->screen
->vgt_hs_offchip_param
);
3313 /* Flush the context to re-emit the init_config state.
3314 * This is done only once in a lifetime of a context.
3316 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3317 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3318 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3321 static struct si_pm4_state
*si_build_vgt_shader_config(struct si_screen
*screen
,
3322 union si_vgt_stages_key key
)
3324 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
3325 uint32_t stages
= 0;
3328 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3329 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3332 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3335 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3336 } else if (key
.u
.gs
) {
3337 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3342 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3344 if (screen
->info
.chip_class
>= GFX9
)
3345 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3347 si_pm4_set_reg(pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3351 static void si_update_vgt_shader_config(struct si_context
*sctx
,
3352 union si_vgt_stages_key key
)
3354 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[key
.index
];
3356 if (unlikely(!*pm4
))
3357 *pm4
= si_build_vgt_shader_config(sctx
->screen
, key
);
3358 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3361 bool si_update_shaders(struct si_context
*sctx
)
3363 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3364 struct si_compiler_ctx_state compiler_state
;
3365 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3366 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3367 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
3368 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
3369 union si_vgt_stages_key key
;
3370 unsigned old_spi_shader_col_format
=
3371 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
3374 compiler_state
.compiler
= &sctx
->compiler
;
3375 compiler_state
.debug
= sctx
->debug
;
3376 compiler_state
.is_debug_context
= sctx
->is_debug
;
3380 /* Update stages before GS. */
3381 if (sctx
->tes_shader
.cso
) {
3384 if (!sctx
->tess_rings
) {
3385 si_init_tess_factor_ring(sctx
);
3386 if (!sctx
->tess_rings
)
3391 if (sctx
->chip_class
<= GFX8
) {
3392 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3396 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3399 if (sctx
->tcs_shader
.cso
) {
3400 r
= si_shader_select(ctx
, &sctx
->tcs_shader
,
3404 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3406 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3407 sctx
->fixed_func_tcs_shader
.cso
=
3408 si_create_fixed_func_tcs(sctx
);
3409 if (!sctx
->fixed_func_tcs_shader
.cso
)
3413 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
3417 si_pm4_bind_state(sctx
, hs
,
3418 sctx
->fixed_func_tcs_shader
.current
->pm4
);
3421 if (sctx
->gs_shader
.cso
) {
3423 if (sctx
->chip_class
<= GFX8
) {
3424 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3428 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3432 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3436 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3438 } else if (sctx
->gs_shader
.cso
) {
3439 if (sctx
->chip_class
<= GFX8
) {
3441 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3445 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3447 si_pm4_bind_state(sctx
, ls
, NULL
);
3448 si_pm4_bind_state(sctx
, hs
, NULL
);
3452 r
= si_shader_select(ctx
, &sctx
->vs_shader
, &compiler_state
);
3455 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3456 si_pm4_bind_state(sctx
, ls
, NULL
);
3457 si_pm4_bind_state(sctx
, hs
, NULL
);
3461 if (sctx
->gs_shader
.cso
) {
3464 r
= si_shader_select(ctx
, &sctx
->gs_shader
, &compiler_state
);
3467 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3468 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3470 if (!si_update_gs_ring_buffers(sctx
))
3473 si_pm4_bind_state(sctx
, gs
, NULL
);
3474 if (sctx
->chip_class
<= GFX8
)
3475 si_pm4_bind_state(sctx
, es
, NULL
);
3478 si_update_vgt_shader_config(sctx
, key
);
3480 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
3481 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
3483 if (sctx
->ps_shader
.cso
) {
3484 unsigned db_shader_control
;
3486 r
= si_shader_select(ctx
, &sctx
->ps_shader
, &compiler_state
);
3489 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3492 sctx
->ps_shader
.cso
->db_shader_control
|
3493 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
3495 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
3496 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
3497 sctx
->flatshade
!= rs
->flatshade
) {
3498 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
3499 sctx
->flatshade
= rs
->flatshade
;
3500 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.spi_map
);
3503 if (sctx
->screen
->rbplus_allowed
&&
3504 si_pm4_state_changed(sctx
, ps
) &&
3506 old_spi_shader_col_format
!=
3507 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
3508 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3510 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
3511 sctx
->ps_db_shader_control
= db_shader_control
;
3512 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3513 if (sctx
->screen
->dpbb_allowed
)
3514 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3517 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
3518 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
3519 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3521 if (sctx
->chip_class
== GFX6
)
3522 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3524 if (sctx
->framebuffer
.nr_samples
<= 1)
3525 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
3529 if (si_pm4_state_enabled_and_changed(sctx
, ls
) ||
3530 si_pm4_state_enabled_and_changed(sctx
, hs
) ||
3531 si_pm4_state_enabled_and_changed(sctx
, es
) ||
3532 si_pm4_state_enabled_and_changed(sctx
, gs
) ||
3533 si_pm4_state_enabled_and_changed(sctx
, vs
) ||
3534 si_pm4_state_enabled_and_changed(sctx
, ps
)) {
3535 if (!si_update_spi_tmpring_size(sctx
))
3539 if (sctx
->chip_class
>= GFX7
) {
3540 if (si_pm4_state_enabled_and_changed(sctx
, ls
))
3541 sctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
3542 else if (!sctx
->queued
.named
.ls
)
3543 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_LS
;
3545 if (si_pm4_state_enabled_and_changed(sctx
, hs
))
3546 sctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
3547 else if (!sctx
->queued
.named
.hs
)
3548 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_HS
;
3550 if (si_pm4_state_enabled_and_changed(sctx
, es
))
3551 sctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
3552 else if (!sctx
->queued
.named
.es
)
3553 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_ES
;
3555 if (si_pm4_state_enabled_and_changed(sctx
, gs
))
3556 sctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
3557 else if (!sctx
->queued
.named
.gs
)
3558 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_GS
;
3560 if (si_pm4_state_enabled_and_changed(sctx
, vs
))
3561 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
3562 else if (!sctx
->queued
.named
.vs
)
3563 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VS
;
3565 if (si_pm4_state_enabled_and_changed(sctx
, ps
))
3566 sctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
3567 else if (!sctx
->queued
.named
.ps
)
3568 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_PS
;
3571 sctx
->do_update_shaders
= false;
3575 static void si_emit_scratch_state(struct si_context
*sctx
)
3577 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3579 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3580 sctx
->spi_tmpring_size
);
3582 if (sctx
->scratch_buffer
) {
3583 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3584 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
3585 RADEON_PRIO_SCRATCH_BUFFER
);
3589 void si_init_shader_functions(struct si_context
*sctx
)
3591 sctx
->atoms
.s
.spi_map
.emit
= si_emit_spi_map
;
3592 sctx
->atoms
.s
.scratch_state
.emit
= si_emit_scratch_state
;
3594 sctx
->b
.create_vs_state
= si_create_shader_selector
;
3595 sctx
->b
.create_tcs_state
= si_create_shader_selector
;
3596 sctx
->b
.create_tes_state
= si_create_shader_selector
;
3597 sctx
->b
.create_gs_state
= si_create_shader_selector
;
3598 sctx
->b
.create_fs_state
= si_create_shader_selector
;
3600 sctx
->b
.bind_vs_state
= si_bind_vs_shader
;
3601 sctx
->b
.bind_tcs_state
= si_bind_tcs_shader
;
3602 sctx
->b
.bind_tes_state
= si_bind_tes_shader
;
3603 sctx
->b
.bind_gs_state
= si_bind_gs_shader
;
3604 sctx
->b
.bind_fs_state
= si_bind_ps_shader
;
3606 sctx
->b
.delete_vs_state
= si_delete_shader_selector
;
3607 sctx
->b
.delete_tcs_state
= si_delete_shader_selector
;
3608 sctx
->b
.delete_tes_state
= si_delete_shader_selector
;
3609 sctx
->b
.delete_gs_state
= si_delete_shader_selector
;
3610 sctx
->b
.delete_fs_state
= si_delete_shader_selector
;