2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
45 * Return the IR key for the shader cache.
47 void si_get_ir_cache_key(struct si_shader_selector
*sel
, bool ngg
, bool es
,
48 unsigned char ir_sha1_cache_key
[20])
55 ir_binary
= sel
->tokens
;
56 ir_size
= tgsi_num_tokens(sel
->tokens
) *
57 sizeof(struct tgsi_token
);
62 nir_serialize(&blob
, sel
->nir
, true);
63 ir_binary
= blob
.data
;
67 /* These settings affect the compilation, but they are not derived
68 * from the input shader IR.
70 unsigned shader_variant_flags
= 0;
73 shader_variant_flags
|= 1 << 0;
75 shader_variant_flags
|= 1 << 1;
76 if (si_get_wave_size(sel
->screen
, sel
->type
, ngg
, es
) == 32)
77 shader_variant_flags
|= 1 << 2;
78 if (sel
->force_correct_derivs_after_kill
)
79 shader_variant_flags
|= 1 << 3;
82 _mesa_sha1_init(&ctx
);
83 _mesa_sha1_update(&ctx
, &shader_variant_flags
, 4);
84 _mesa_sha1_update(&ctx
, ir_binary
, ir_size
);
85 if (sel
->type
== PIPE_SHADER_VERTEX
||
86 sel
->type
== PIPE_SHADER_TESS_EVAL
||
87 sel
->type
== PIPE_SHADER_GEOMETRY
)
88 _mesa_sha1_update(&ctx
, &sel
->so
, sizeof(sel
->so
));
89 _mesa_sha1_final(&ctx
, ir_sha1_cache_key
);
95 /** Copy "data" to "ptr" and return the next dword following copied data. */
96 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
98 /* data may be NULL if size == 0 */
100 memcpy(ptr
, data
, size
);
101 ptr
+= DIV_ROUND_UP(size
, 4);
105 /** Read data from "ptr". Return the next dword following the data. */
106 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
108 memcpy(data
, ptr
, size
);
109 ptr
+= DIV_ROUND_UP(size
, 4);
114 * Write the size as uint followed by the data. Return the next dword
115 * following the copied data.
117 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
120 return write_data(ptr
, data
, size
);
124 * Read the size as uint followed by the data. Return both via parameters.
125 * Return the next dword following the data.
127 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
130 assert(*data
== NULL
);
133 *data
= malloc(*size
);
134 return read_data(ptr
, *data
, *size
);
138 * Return the shader binary in a buffer. The first 4 bytes contain its size
141 static void *si_get_shader_binary(struct si_shader
*shader
)
143 /* There is always a size of data followed by the data itself. */
144 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
145 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
147 /* Refuse to allocate overly large buffers and guard against integer
149 if (shader
->binary
.elf_size
> UINT_MAX
/ 4 ||
150 llvm_ir_size
> UINT_MAX
/ 4)
155 4 + /* CRC32 of the data below */
156 align(sizeof(shader
->config
), 4) +
157 align(sizeof(shader
->info
), 4) +
158 4 + align(shader
->binary
.elf_size
, 4) +
159 4 + align(llvm_ir_size
, 4);
160 void *buffer
= CALLOC(1, size
);
161 uint32_t *ptr
= (uint32_t*)buffer
;
167 ptr
++; /* CRC32 is calculated at the end. */
169 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
170 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
171 ptr
= write_chunk(ptr
, shader
->binary
.elf_buffer
, shader
->binary
.elf_size
);
172 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
173 assert((char *)ptr
- (char *)buffer
== size
);
176 ptr
= (uint32_t*)buffer
;
178 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
183 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
185 uint32_t *ptr
= (uint32_t*)binary
;
186 uint32_t size
= *ptr
++;
187 uint32_t crc32
= *ptr
++;
191 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
192 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
196 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
197 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
198 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.elf_buffer
,
200 shader
->binary
.elf_size
= elf_size
;
201 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
207 * Insert a shader into the cache. It's assumed the shader is not in the cache.
208 * Use si_shader_cache_load_shader before calling this.
210 void si_shader_cache_insert_shader(struct si_screen
*sscreen
,
211 unsigned char ir_sha1_cache_key
[20],
212 struct si_shader
*shader
,
213 bool insert_into_disk_cache
)
216 struct hash_entry
*entry
;
217 uint8_t key
[CACHE_KEY_SIZE
];
219 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, ir_sha1_cache_key
);
221 return; /* already added */
223 hw_binary
= si_get_shader_binary(shader
);
227 if (_mesa_hash_table_insert(sscreen
->shader_cache
,
228 mem_dup(ir_sha1_cache_key
, 20),
229 hw_binary
) == NULL
) {
234 if (sscreen
->disk_shader_cache
&& insert_into_disk_cache
) {
235 disk_cache_compute_key(sscreen
->disk_shader_cache
,
236 ir_sha1_cache_key
, 20, key
);
237 disk_cache_put(sscreen
->disk_shader_cache
, key
, hw_binary
,
238 *((uint32_t *) hw_binary
), NULL
);
242 bool si_shader_cache_load_shader(struct si_screen
*sscreen
,
243 unsigned char ir_sha1_cache_key
[20],
244 struct si_shader
*shader
)
246 struct hash_entry
*entry
=
247 _mesa_hash_table_search(sscreen
->shader_cache
, ir_sha1_cache_key
);
249 if (sscreen
->disk_shader_cache
) {
250 unsigned char sha1
[CACHE_KEY_SIZE
];
252 disk_cache_compute_key(sscreen
->disk_shader_cache
,
253 ir_sha1_cache_key
, 20, sha1
);
257 disk_cache_get(sscreen
->disk_shader_cache
,
262 if (binary_size
< sizeof(uint32_t) ||
263 *((uint32_t*)buffer
) != binary_size
) {
264 /* Something has gone wrong discard the item
265 * from the cache and rebuild/link from
268 assert(!"Invalid radeonsi shader disk cache "
271 disk_cache_remove(sscreen
->disk_shader_cache
,
278 if (!si_load_shader_binary(shader
, buffer
)) {
284 si_shader_cache_insert_shader(sscreen
, ir_sha1_cache_key
,
290 if (!si_load_shader_binary(shader
, entry
->data
))
293 p_atomic_inc(&sscreen
->num_shader_cache_hits
);
297 static uint32_t si_shader_cache_key_hash(const void *key
)
299 /* Take the first dword of SHA1. */
300 return *(uint32_t*)key
;
303 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
306 return memcmp(a
, b
, 20) == 0;
309 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
311 FREE((void*)entry
->key
);
315 bool si_init_shader_cache(struct si_screen
*sscreen
)
317 (void) simple_mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
318 sscreen
->shader_cache
=
319 _mesa_hash_table_create(NULL
,
320 si_shader_cache_key_hash
,
321 si_shader_cache_key_equals
);
323 return sscreen
->shader_cache
!= NULL
;
326 void si_destroy_shader_cache(struct si_screen
*sscreen
)
328 if (sscreen
->shader_cache
)
329 _mesa_hash_table_destroy(sscreen
->shader_cache
,
330 si_destroy_shader_cache_entry
);
331 simple_mtx_destroy(&sscreen
->shader_cache_mutex
);
336 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
337 const struct si_shader_selector
*tes
,
338 struct si_pm4_state
*pm4
)
340 const struct tgsi_shader_info
*info
= &tes
->info
;
341 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
342 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
343 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
344 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
345 unsigned type
, partitioning
, topology
, distribution_mode
;
347 switch (tes_prim_mode
) {
348 case PIPE_PRIM_LINES
:
349 type
= V_028B6C_TESS_ISOLINE
;
351 case PIPE_PRIM_TRIANGLES
:
352 type
= V_028B6C_TESS_TRIANGLE
;
354 case PIPE_PRIM_QUADS
:
355 type
= V_028B6C_TESS_QUAD
;
362 switch (tes_spacing
) {
363 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
364 partitioning
= V_028B6C_PART_FRAC_ODD
;
366 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
367 partitioning
= V_028B6C_PART_FRAC_EVEN
;
369 case PIPE_TESS_SPACING_EQUAL
:
370 partitioning
= V_028B6C_PART_INTEGER
;
378 topology
= V_028B6C_OUTPUT_POINT
;
379 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
380 topology
= V_028B6C_OUTPUT_LINE
;
381 else if (tes_vertex_order_cw
)
382 /* for some reason, this must be the other way around */
383 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
385 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
387 if (sscreen
->info
.has_distributed_tess
) {
388 if (sscreen
->info
.family
== CHIP_FIJI
||
389 sscreen
->info
.family
>= CHIP_POLARIS10
)
390 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
392 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
394 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
397 pm4
->shader
->vgt_tf_param
= S_028B6C_TYPE(type
) |
398 S_028B6C_PARTITIONING(partitioning
) |
399 S_028B6C_TOPOLOGY(topology
) |
400 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
403 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
404 * whether the "fractional odd" tessellation spacing is used.
406 * Possible VGT configurations and which state should set the register:
408 * Reg set in | VGT shader configuration | Value
409 * ------------------------------------------------------
411 * VS as ES | ES -> GS -> VS | 30
412 * TES as VS | LS -> HS -> VS | 14 or 30
413 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
415 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
417 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
418 struct si_shader_selector
*sel
,
419 struct si_shader
*shader
,
420 struct si_pm4_state
*pm4
)
422 unsigned type
= sel
->type
;
424 if (sscreen
->info
.family
< CHIP_POLARIS10
||
425 sscreen
->info
.chip_class
>= GFX10
)
428 /* VS as VS, or VS as ES: */
429 if ((type
== PIPE_SHADER_VERTEX
&&
431 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
432 /* TES as VS, or TES as ES: */
433 type
== PIPE_SHADER_TESS_EVAL
) {
434 unsigned vtx_reuse_depth
= 30;
436 if (type
== PIPE_SHADER_TESS_EVAL
&&
437 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
438 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
439 vtx_reuse_depth
= 14;
442 pm4
->shader
->vgt_vertex_reuse_block_cntl
= vtx_reuse_depth
;
446 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
449 si_pm4_clear_state(shader
->pm4
);
451 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
454 shader
->pm4
->shader
= shader
;
457 fprintf(stderr
, "radeonsi: Failed to create pm4 state.\n");
462 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs
)
464 /* Add the pointer to VBO descriptors. */
465 return num_always_on_user_sgprs
+ 1;
468 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
469 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen
*sscreen
,
470 struct si_shader
*shader
, bool legacy_vs_prim_id
)
472 assert(shader
->selector
->type
== PIPE_SHADER_VERTEX
||
473 (shader
->previous_stage_sel
&&
474 shader
->previous_stage_sel
->type
== PIPE_SHADER_VERTEX
));
476 /* GFX6-9 LS (VertexID, RelAutoindex, InstanceID / StepRate0(==1), ...).
477 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID, ...)
478 * GFX10 LS (VertexID, RelAutoindex, UserVGPR1, InstanceID).
479 * GFX10 ES,VS (VertexID, UserVGPR0, UserVGPR1 or VSPrimID, UserVGPR2 or InstanceID)
481 bool is_ls
= shader
->selector
->type
== PIPE_SHADER_TESS_CTRL
|| shader
->key
.as_ls
;
483 if (sscreen
->info
.chip_class
>= GFX10
&& shader
->info
.uses_instanceid
)
485 else if ((is_ls
&& shader
->info
.uses_instanceid
) || legacy_vs_prim_id
)
487 else if (is_ls
|| shader
->info
.uses_instanceid
)
493 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
495 struct si_pm4_state
*pm4
;
498 assert(sscreen
->info
.chip_class
<= GFX8
);
500 pm4
= si_get_shader_pm4_state(shader
);
504 va
= shader
->bo
->gpu_address
;
505 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
507 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
508 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
510 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
511 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
512 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false)) |
513 S_00B528_DX10_CLAMP(1) |
514 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
515 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
)) |
516 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
519 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
521 struct si_pm4_state
*pm4
;
524 pm4
= si_get_shader_pm4_state(shader
);
528 va
= shader
->bo
->gpu_address
;
529 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
531 if (sscreen
->info
.chip_class
>= GFX9
) {
532 if (sscreen
->info
.chip_class
>= GFX10
) {
533 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
534 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
536 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
537 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, S_00B414_MEM_BASE(va
>> 40));
540 unsigned num_user_sgprs
=
541 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR
);
543 shader
->config
.rsrc2
=
544 S_00B42C_USER_SGPR(num_user_sgprs
) |
545 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
547 if (sscreen
->info
.chip_class
>= GFX10
)
548 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
550 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
552 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
553 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, S_00B424_MEM_BASE(va
>> 40));
555 shader
->config
.rsrc2
=
556 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
557 S_00B42C_OC_LDS_EN(1) |
558 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
561 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
562 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) /
563 (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
564 (sscreen
->info
.chip_class
<= GFX9
?
565 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) : 0) |
566 S_00B428_DX10_CLAMP(1) |
567 S_00B428_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
568 S_00B428_WGP_MODE(sscreen
->info
.chip_class
>= GFX10
) |
569 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
570 S_00B428_LS_VGPR_COMP_CNT(sscreen
->info
.chip_class
>= GFX9
?
571 si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false) : 0));
573 if (sscreen
->info
.chip_class
<= GFX8
) {
574 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
575 shader
->config
.rsrc2
);
579 static void si_emit_shader_es(struct si_context
*sctx
)
581 struct si_shader
*shader
= sctx
->queued
.named
.es
->shader
;
582 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
587 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
588 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
589 shader
->selector
->esgs_itemsize
/ 4);
591 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
592 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
593 SI_TRACKED_VGT_TF_PARAM
,
594 shader
->vgt_tf_param
);
596 if (shader
->vgt_vertex_reuse_block_cntl
)
597 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
598 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
599 shader
->vgt_vertex_reuse_block_cntl
);
601 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
602 sctx
->context_roll
= true;
605 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
607 struct si_pm4_state
*pm4
;
608 unsigned num_user_sgprs
;
609 unsigned vgpr_comp_cnt
;
613 assert(sscreen
->info
.chip_class
<= GFX8
);
615 pm4
= si_get_shader_pm4_state(shader
);
619 pm4
->atom
.emit
= si_emit_shader_es
;
620 va
= shader
->bo
->gpu_address
;
621 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
623 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
624 vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false);
625 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
626 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
627 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
628 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
630 unreachable("invalid shader selector type");
632 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
634 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
635 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
636 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
637 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
638 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
639 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
640 S_00B328_DX10_CLAMP(1) |
641 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
642 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
643 S_00B32C_USER_SGPR(num_user_sgprs
) |
644 S_00B32C_OC_LDS_EN(oc_lds_en
) |
645 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
647 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
648 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
650 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
653 void gfx9_get_gs_info(struct si_shader_selector
*es
,
654 struct si_shader_selector
*gs
,
655 struct gfx9_gs_info
*out
)
657 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
658 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
659 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
660 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
662 /* All these are in dwords: */
663 /* We can't allow using the whole LDS, because GS waves compete with
664 * other shader stages for LDS space. */
665 const unsigned max_lds_size
= 8 * 1024;
666 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
667 unsigned esgs_lds_size
;
669 /* All these are per subgroup: */
670 const unsigned max_out_prims
= 32 * 1024;
671 const unsigned max_es_verts
= 255;
672 const unsigned ideal_gs_prims
= 64;
673 unsigned max_gs_prims
, gs_prims
;
674 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
676 if (uses_adjacency
|| gs_num_invocations
> 1)
677 max_gs_prims
= 127 / gs_num_invocations
;
681 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
682 * Make sure we don't go over the maximum value.
684 if (gs
->gs_max_out_vertices
> 0) {
685 max_gs_prims
= MIN2(max_gs_prims
,
687 (gs
->gs_max_out_vertices
* gs_num_invocations
));
689 assert(max_gs_prims
> 0);
691 /* If the primitive has adjacency, halve the number of vertices
692 * that will be reused in multiple primitives.
694 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
696 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
697 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
699 /* Compute ESGS LDS size based on the worst case number of ES vertices
700 * needed to create the target number of GS prims per subgroup.
702 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
704 /* If total LDS usage is too big, refactor partitions based on ratio
705 * of ESGS item sizes.
707 if (esgs_lds_size
> max_lds_size
) {
708 /* Our target GS Prims Per Subgroup was too large. Calculate
709 * the maximum number of GS Prims Per Subgroup that will fit
710 * into LDS, capped by the maximum that the hardware can support.
712 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
714 assert(gs_prims
> 0);
715 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
718 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
719 assert(esgs_lds_size
<= max_lds_size
);
722 /* Now calculate remaining ESGS information. */
724 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
726 es_verts
= max_es_verts
;
728 /* Vertices for adjacency primitives are not always reused, so restore
729 * it for ES_VERTS_PER_SUBGRP.
731 min_es_verts
= gs
->gs_input_verts_per_prim
;
733 /* For normal primitives, the VGT only checks if they are past the ES
734 * verts per subgroup after allocating a full GS primitive and if they
735 * are, kick off a new subgroup. But if those additional ES verts are
736 * unique (e.g. not reused) we need to make sure there is enough LDS
737 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
739 es_verts
-= min_es_verts
- 1;
741 out
->es_verts_per_subgroup
= es_verts
;
742 out
->gs_prims_per_subgroup
= gs_prims
;
743 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
744 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
745 gs
->gs_max_out_vertices
;
746 out
->esgs_ring_size
= 4 * esgs_lds_size
;
748 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
751 static void si_emit_shader_gs(struct si_context
*sctx
)
753 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
754 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
759 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
760 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
761 radeon_opt_set_context_reg3(sctx
, R_028A60_VGT_GSVS_RING_OFFSET_1
,
762 SI_TRACKED_VGT_GSVS_RING_OFFSET_1
,
763 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
,
764 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
,
765 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
);
767 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
768 radeon_opt_set_context_reg(sctx
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
,
769 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE
,
770 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
);
772 /* R_028B38_VGT_GS_MAX_VERT_OUT */
773 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
774 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
775 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
);
777 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
778 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
779 radeon_opt_set_context_reg4(sctx
, R_028B5C_VGT_GS_VERT_ITEMSIZE
,
780 SI_TRACKED_VGT_GS_VERT_ITEMSIZE
,
781 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
,
782 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
,
783 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
,
784 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
);
786 /* R_028B90_VGT_GS_INSTANCE_CNT */
787 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
788 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
789 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
);
791 if (sctx
->chip_class
>= GFX9
) {
792 /* R_028A44_VGT_GS_ONCHIP_CNTL */
793 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
794 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
795 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
);
796 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
797 radeon_opt_set_context_reg(sctx
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
798 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
799 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
);
800 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
801 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
802 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
803 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
);
805 if (shader
->key
.part
.gs
.es
->type
== PIPE_SHADER_TESS_EVAL
)
806 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
807 SI_TRACKED_VGT_TF_PARAM
,
808 shader
->vgt_tf_param
);
809 if (shader
->vgt_vertex_reuse_block_cntl
)
810 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
811 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
812 shader
->vgt_vertex_reuse_block_cntl
);
815 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
816 sctx
->context_roll
= true;
819 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
821 struct si_shader_selector
*sel
= shader
->selector
;
822 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
823 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
824 struct si_pm4_state
*pm4
;
826 unsigned max_stream
= sel
->max_gs_stream
;
829 pm4
= si_get_shader_pm4_state(shader
);
833 pm4
->atom
.emit
= si_emit_shader_gs
;
835 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
836 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
= offset
;
839 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
840 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
= offset
;
843 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
844 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
= offset
;
847 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
848 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
= offset
;
850 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
851 assert(offset
< (1 << 15));
853 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
= sel
->gs_max_out_vertices
;
855 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
= num_components
[0];
856 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
= (max_stream
>= 1) ? num_components
[1] : 0;
857 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
= (max_stream
>= 2) ? num_components
[2] : 0;
858 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
= (max_stream
>= 3) ? num_components
[3] : 0;
860 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
= S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
861 S_028B90_ENABLE(gs_num_invocations
> 0);
863 va
= shader
->bo
->gpu_address
;
864 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
866 if (sscreen
->info
.chip_class
>= GFX9
) {
867 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
868 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
869 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
871 if (es_type
== PIPE_SHADER_VERTEX
) {
872 es_vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false);
873 } else if (es_type
== PIPE_SHADER_TESS_EVAL
)
874 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
876 unreachable("invalid shader selector type");
878 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
879 * VGPR[0:4] are always loaded.
881 if (sel
->info
.uses_invocationid
)
882 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
883 else if (sel
->info
.uses_primid
)
884 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
885 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
886 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
888 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
890 unsigned num_user_sgprs
;
891 if (es_type
== PIPE_SHADER_VERTEX
)
892 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
894 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
896 if (sscreen
->info
.chip_class
>= GFX10
) {
897 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
898 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
900 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
901 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, S_00B214_MEM_BASE(va
>> 40));
905 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
906 S_00B228_DX10_CLAMP(1) |
907 S_00B228_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
908 S_00B228_WGP_MODE(sscreen
->info
.chip_class
>= GFX10
) |
909 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
910 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
912 S_00B22C_USER_SGPR(num_user_sgprs
) |
913 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
914 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
915 S_00B22C_LDS_SIZE(shader
->config
.lds_size
) |
916 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
918 if (sscreen
->info
.chip_class
>= GFX10
) {
919 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
921 rsrc1
|= S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
922 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
925 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, rsrc1
);
926 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
, rsrc2
);
928 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
=
929 S_028A44_ES_VERTS_PER_SUBGRP(shader
->gs_info
.es_verts_per_subgroup
) |
930 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->gs_info
.gs_prims_per_subgroup
) |
931 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->gs_info
.gs_inst_prims_in_subgroup
);
932 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
=
933 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader
->gs_info
.max_prims_per_subgroup
);
934 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
=
935 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4;
937 if (es_type
== PIPE_SHADER_TESS_EVAL
)
938 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
940 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
943 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
944 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, S_00B224_MEM_BASE(va
>> 40));
946 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
947 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
948 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
949 S_00B228_DX10_CLAMP(1) |
950 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
951 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
952 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
953 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
957 /* Common tail code for NGG primitive shaders. */
958 static void gfx10_emit_shader_ngg_tail(struct si_context
*sctx
,
959 struct si_shader
*shader
,
960 unsigned initial_cdw
)
962 radeon_opt_set_context_reg(sctx
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
963 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP
,
964 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
);
965 radeon_opt_set_context_reg(sctx
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
966 SI_TRACKED_GE_NGG_SUBGRP_CNTL
,
967 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
);
968 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
969 SI_TRACKED_VGT_PRIMITIVEID_EN
,
970 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
);
971 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
972 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
973 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
);
974 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
975 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
976 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
);
977 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
978 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
979 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
);
980 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
981 SI_TRACKED_SPI_VS_OUT_CONFIG
,
982 shader
->ctx_reg
.ngg
.spi_vs_out_config
);
983 radeon_opt_set_context_reg2(sctx
, R_028708_SPI_SHADER_IDX_FORMAT
,
984 SI_TRACKED_SPI_SHADER_IDX_FORMAT
,
985 shader
->ctx_reg
.ngg
.spi_shader_idx_format
,
986 shader
->ctx_reg
.ngg
.spi_shader_pos_format
);
987 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
988 SI_TRACKED_PA_CL_VTE_CNTL
,
989 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
);
990 radeon_opt_set_context_reg(sctx
, R_028838_PA_CL_NGG_CNTL
,
991 SI_TRACKED_PA_CL_NGG_CNTL
,
992 shader
->ctx_reg
.ngg
.pa_cl_ngg_cntl
);
994 radeon_opt_set_context_reg_rmw(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
995 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS
,
996 shader
->pa_cl_vs_out_cntl
,
997 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK
);
999 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1000 sctx
->context_roll
= true;
1003 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context
*sctx
)
1005 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1006 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1011 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1014 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context
*sctx
)
1016 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1017 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1022 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1023 SI_TRACKED_VGT_TF_PARAM
,
1024 shader
->vgt_tf_param
);
1026 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1029 static void gfx10_emit_shader_ngg_notess_gs(struct si_context
*sctx
)
1031 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1032 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1037 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
1038 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1039 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1041 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1044 static void gfx10_emit_shader_ngg_tess_gs(struct si_context
*sctx
)
1046 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1047 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1052 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
1053 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1054 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1055 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1056 SI_TRACKED_VGT_TF_PARAM
,
1057 shader
->vgt_tf_param
);
1059 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1062 unsigned si_get_input_prim(const struct si_shader_selector
*gs
)
1064 if (gs
->type
== PIPE_SHADER_GEOMETRY
)
1065 return gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
1067 if (gs
->type
== PIPE_SHADER_TESS_EVAL
) {
1068 if (gs
->info
.properties
[TGSI_PROPERTY_TES_POINT_MODE
])
1069 return PIPE_PRIM_POINTS
;
1070 if (gs
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] == PIPE_PRIM_LINES
)
1071 return PIPE_PRIM_LINES
;
1072 return PIPE_PRIM_TRIANGLES
;
1075 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1076 return PIPE_PRIM_TRIANGLES
; /* worst case for all callers */
1079 static unsigned si_get_vs_out_cntl(const struct si_shader_selector
*sel
, bool ngg
)
1082 sel
->info
.writes_psize
|| (sel
->info
.writes_edgeflag
&& !ngg
) ||
1083 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
1084 return S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
1085 S_02881C_USE_VTX_EDGE_FLAG(sel
->info
.writes_edgeflag
&& !ngg
) |
1086 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
1087 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
1088 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
1089 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
1093 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1096 static void gfx10_shader_ngg(struct si_screen
*sscreen
, struct si_shader
*shader
)
1098 const struct si_shader_selector
*gs_sel
= shader
->selector
;
1099 const struct tgsi_shader_info
*gs_info
= &gs_sel
->info
;
1100 enum pipe_shader_type gs_type
= shader
->selector
->type
;
1101 const struct si_shader_selector
*es_sel
=
1102 shader
->previous_stage_sel
? shader
->previous_stage_sel
: shader
->selector
;
1103 const struct tgsi_shader_info
*es_info
= &es_sel
->info
;
1104 enum pipe_shader_type es_type
= es_sel
->type
;
1105 unsigned num_user_sgprs
;
1106 unsigned nparams
, es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
1108 unsigned window_space
=
1109 gs_info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1110 bool es_enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| es_info
->uses_primid
;
1111 unsigned gs_num_invocations
= MAX2(gs_sel
->gs_num_invocations
, 1);
1112 unsigned input_prim
= si_get_input_prim(gs_sel
);
1113 bool break_wave_at_eoi
= false;
1114 struct si_pm4_state
*pm4
= si_get_shader_pm4_state(shader
);
1118 if (es_type
== PIPE_SHADER_TESS_EVAL
) {
1119 pm4
->atom
.emit
= gs_type
== PIPE_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_tess_gs
1120 : gfx10_emit_shader_ngg_tess_nogs
;
1122 pm4
->atom
.emit
= gs_type
== PIPE_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_notess_gs
1123 : gfx10_emit_shader_ngg_notess_nogs
;
1126 va
= shader
->bo
->gpu_address
;
1127 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1129 if (es_type
== PIPE_SHADER_VERTEX
) {
1130 es_vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false);
1132 if (es_info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
]) {
1133 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1134 es_info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
];
1136 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
1139 assert(es_type
== PIPE_SHADER_TESS_EVAL
);
1140 es_vgpr_comp_cnt
= es_enable_prim_id
? 3 : 2;
1141 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
1143 if (es_enable_prim_id
|| gs_info
->uses_primid
)
1144 break_wave_at_eoi
= true;
1147 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1148 * VGPR[0:4] are always loaded.
1150 * Vertex shaders always need to load VGPR3, because they need to
1151 * pass edge flags for decomposed primitives (such as quads) to the PA
1152 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1154 if (gs_info
->uses_invocationid
|| gs_type
== PIPE_SHADER_VERTEX
)
1155 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID, edge flags. */
1156 else if (gs_info
->uses_primid
)
1157 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
1158 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
1159 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
1161 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
1163 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
1164 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
1165 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
1166 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) /
1167 (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
1168 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
1169 S_00B228_DX10_CLAMP(1) |
1170 S_00B228_MEM_ORDERED(1) |
1171 S_00B228_WGP_MODE(1) |
1172 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
1173 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
1174 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0) |
1175 S_00B22C_USER_SGPR(num_user_sgprs
) |
1176 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
1177 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5) |
1178 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
1179 S_00B22C_LDS_SIZE(shader
->config
.lds_size
));
1181 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1182 shader
->ctx_reg
.ngg
.spi_vs_out_config
=
1183 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
1184 S_0286C4_NO_PC_EXPORT(shader
->info
.nr_param_exports
== 0);
1186 shader
->ctx_reg
.ngg
.spi_shader_idx_format
=
1187 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
);
1188 shader
->ctx_reg
.ngg
.spi_shader_pos_format
=
1189 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1190 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1191 V_02870C_SPI_SHADER_4COMP
:
1192 V_02870C_SPI_SHADER_NONE
) |
1193 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1194 V_02870C_SPI_SHADER_4COMP
:
1195 V_02870C_SPI_SHADER_NONE
) |
1196 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1197 V_02870C_SPI_SHADER_4COMP
:
1198 V_02870C_SPI_SHADER_NONE
);
1200 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
=
1201 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
1202 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id
);
1204 if (gs_type
== PIPE_SHADER_GEOMETRY
) {
1205 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= es_sel
->esgs_itemsize
/ 4;
1206 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
= gs_sel
->gs_max_out_vertices
;
1208 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= 1;
1211 if (es_type
== PIPE_SHADER_TESS_EVAL
)
1212 si_set_tesseval_regs(sscreen
, es_sel
, pm4
);
1214 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
=
1215 S_028A44_ES_VERTS_PER_SUBGRP(shader
->ngg
.hw_max_esverts
) |
1216 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->ngg
.max_gsprims
) |
1217 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->ngg
.max_gsprims
* gs_num_invocations
);
1218 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
=
1219 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader
->ngg
.max_out_verts
);
1220 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
=
1221 S_028B4C_PRIM_AMP_FACTOR(shader
->ngg
.prim_amp_factor
) |
1222 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1223 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
=
1224 S_028B90_CNT(gs_num_invocations
) |
1225 S_028B90_ENABLE(gs_num_invocations
> 1) |
1226 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1227 shader
->ngg
.max_vert_out_per_gs_instance
);
1229 /* Always output hw-generated edge flags and pass them via the prim
1230 * export to prevent drawing lines on internal edges of decomposed
1231 * primitives (such as quads) with polygon mode = lines. Only VS needs
1234 shader
->ctx_reg
.ngg
.pa_cl_ngg_cntl
=
1235 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type
== PIPE_SHADER_VERTEX
);
1236 shader
->pa_cl_vs_out_cntl
= si_get_vs_out_cntl(gs_sel
, true);
1239 S_03096C_PRIM_GRP_SIZE(shader
->ngg
.max_gsprims
) |
1240 S_03096C_VERT_GRP_SIZE(shader
->ngg
.hw_max_esverts
) |
1241 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
1243 /* Bug workaround for a possible hang with non-tessellation cases.
1244 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1246 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1248 if ((sscreen
->info
.family
== CHIP_NAVI10
||
1249 sscreen
->info
.family
== CHIP_NAVI12
||
1250 sscreen
->info
.family
== CHIP_NAVI14
) &&
1251 (es_type
== PIPE_SHADER_VERTEX
|| gs_type
== PIPE_SHADER_VERTEX
) && /* = no tess */
1252 shader
->ngg
.hw_max_esverts
!= 256) {
1253 shader
->ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
1255 if (shader
->ngg
.hw_max_esverts
> 5) {
1257 S_03096C_VERT_GRP_SIZE(shader
->ngg
.hw_max_esverts
- 5);
1262 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1263 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1265 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1266 S_028818_VTX_W0_FMT(1) |
1267 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1268 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1269 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1273 static void si_emit_shader_vs(struct si_context
*sctx
)
1275 struct si_shader
*shader
= sctx
->queued
.named
.vs
->shader
;
1276 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1281 radeon_opt_set_context_reg(sctx
, R_028A40_VGT_GS_MODE
,
1282 SI_TRACKED_VGT_GS_MODE
,
1283 shader
->ctx_reg
.vs
.vgt_gs_mode
);
1284 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
1285 SI_TRACKED_VGT_PRIMITIVEID_EN
,
1286 shader
->ctx_reg
.vs
.vgt_primitiveid_en
);
1288 if (sctx
->chip_class
<= GFX8
) {
1289 radeon_opt_set_context_reg(sctx
, R_028AB4_VGT_REUSE_OFF
,
1290 SI_TRACKED_VGT_REUSE_OFF
,
1291 shader
->ctx_reg
.vs
.vgt_reuse_off
);
1294 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
1295 SI_TRACKED_SPI_VS_OUT_CONFIG
,
1296 shader
->ctx_reg
.vs
.spi_vs_out_config
);
1298 radeon_opt_set_context_reg(sctx
, R_02870C_SPI_SHADER_POS_FORMAT
,
1299 SI_TRACKED_SPI_SHADER_POS_FORMAT
,
1300 shader
->ctx_reg
.vs
.spi_shader_pos_format
);
1302 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
1303 SI_TRACKED_PA_CL_VTE_CNTL
,
1304 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
);
1306 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1307 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1308 SI_TRACKED_VGT_TF_PARAM
,
1309 shader
->vgt_tf_param
);
1311 if (shader
->vgt_vertex_reuse_block_cntl
)
1312 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1313 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1314 shader
->vgt_vertex_reuse_block_cntl
);
1316 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1317 sctx
->context_roll
= true;
1319 /* Required programming for tessellation. (legacy pipeline only) */
1320 if (sctx
->chip_class
== GFX10
&&
1321 shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
1322 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
1323 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
1324 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1325 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1326 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1329 if (sctx
->chip_class
>= GFX10
) {
1330 radeon_opt_set_context_reg_rmw(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
1331 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS
,
1332 shader
->pa_cl_vs_out_cntl
,
1333 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK
);
1338 * Compute the state for \p shader, which will run as a vertex shader on the
1341 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1342 * is the copy shader.
1344 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
1345 struct si_shader_selector
*gs
)
1347 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1348 struct si_pm4_state
*pm4
;
1349 unsigned num_user_sgprs
, vgpr_comp_cnt
;
1351 unsigned nparams
, oc_lds_en
;
1352 unsigned window_space
=
1353 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1354 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
1356 pm4
= si_get_shader_pm4_state(shader
);
1360 pm4
->atom
.emit
= si_emit_shader_vs
;
1362 /* We always write VGT_GS_MODE in the VS state, because every switch
1363 * between different shader pipelines involving a different GS or no
1364 * GS at all involves a switch of the VS (different GS use different
1365 * copy shaders). On the other hand, when the API switches from a GS to
1366 * no GS and then back to the same GS used originally, the GS state is
1370 unsigned mode
= V_028A40_GS_OFF
;
1372 /* PrimID needs GS scenario A. */
1374 mode
= V_028A40_GS_SCENARIO_A
;
1376 shader
->ctx_reg
.vs
.vgt_gs_mode
= S_028A40_MODE(mode
);
1377 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= enable_prim_id
;
1379 shader
->ctx_reg
.vs
.vgt_gs_mode
= ac_vgt_gs_mode(gs
->gs_max_out_vertices
,
1380 sscreen
->info
.chip_class
);
1381 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= 0;
1384 if (sscreen
->info
.chip_class
<= GFX8
) {
1385 /* Reuse needs to be set off if we write oViewport. */
1386 shader
->ctx_reg
.vs
.vgt_reuse_off
=
1387 S_028AB4_REUSE_OFF(info
->writes_viewport_index
);
1390 va
= shader
->bo
->gpu_address
;
1391 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1394 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
1395 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
1396 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
1397 vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, enable_prim_id
);
1399 if (info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
]) {
1400 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1401 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
];
1403 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
1405 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
1406 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
1407 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
1409 unreachable("invalid shader selector type");
1411 /* VS is required to export at least one param. */
1412 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1413 shader
->ctx_reg
.vs
.spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
1415 if (sscreen
->info
.chip_class
>= GFX10
) {
1416 shader
->ctx_reg
.vs
.spi_vs_out_config
|=
1417 S_0286C4_NO_PC_EXPORT(shader
->info
.nr_param_exports
== 0);
1420 shader
->ctx_reg
.vs
.spi_shader_pos_format
=
1421 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1422 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1423 V_02870C_SPI_SHADER_4COMP
:
1424 V_02870C_SPI_SHADER_NONE
) |
1425 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1426 V_02870C_SPI_SHADER_4COMP
:
1427 V_02870C_SPI_SHADER_NONE
) |
1428 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1429 V_02870C_SPI_SHADER_4COMP
:
1430 V_02870C_SPI_SHADER_NONE
);
1431 shader
->pa_cl_vs_out_cntl
= si_get_vs_out_cntl(shader
->selector
, false);
1433 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
1435 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
1436 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, S_00B124_MEM_BASE(va
>> 40));
1438 uint32_t rsrc1
= S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) /
1439 (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
1440 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
1441 S_00B128_DX10_CLAMP(1) |
1442 S_00B128_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1443 S_00B128_FLOAT_MODE(shader
->config
.float_mode
);
1444 uint32_t rsrc2
= S_00B12C_USER_SGPR(num_user_sgprs
) |
1445 S_00B12C_OC_LDS_EN(oc_lds_en
) |
1446 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
1448 if (sscreen
->info
.chip_class
<= GFX9
)
1449 rsrc1
|= S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1451 if (!sscreen
->use_ngg_streamout
) {
1452 rsrc2
|= S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
1453 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
1454 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
1455 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
1456 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
);
1459 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
, rsrc1
);
1460 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
, rsrc2
);
1463 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1464 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1466 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1467 S_028818_VTX_W0_FMT(1) |
1468 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1469 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1470 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1472 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1473 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
1475 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
1478 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
1480 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
1481 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
1482 !!(info
->colors_read
& 0xf0);
1483 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
1484 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
1486 assert(num_interp
<= 32);
1487 return MIN2(num_interp
, 32);
1490 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
1492 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
1493 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
1495 /* If the i-th target format is set, all previous target formats must
1496 * be non-zero to avoid hangs.
1498 for (i
= 0; i
< num_targets
; i
++)
1499 if (!(value
& (0xf << (i
* 4))))
1500 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
1505 static void si_emit_shader_ps(struct si_context
*sctx
)
1507 struct si_shader
*shader
= sctx
->queued
.named
.ps
->shader
;
1508 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1513 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1514 radeon_opt_set_context_reg2(sctx
, R_0286CC_SPI_PS_INPUT_ENA
,
1515 SI_TRACKED_SPI_PS_INPUT_ENA
,
1516 shader
->ctx_reg
.ps
.spi_ps_input_ena
,
1517 shader
->ctx_reg
.ps
.spi_ps_input_addr
);
1519 radeon_opt_set_context_reg(sctx
, R_0286E0_SPI_BARYC_CNTL
,
1520 SI_TRACKED_SPI_BARYC_CNTL
,
1521 shader
->ctx_reg
.ps
.spi_baryc_cntl
);
1522 radeon_opt_set_context_reg(sctx
, R_0286D8_SPI_PS_IN_CONTROL
,
1523 SI_TRACKED_SPI_PS_IN_CONTROL
,
1524 shader
->ctx_reg
.ps
.spi_ps_in_control
);
1526 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1527 radeon_opt_set_context_reg2(sctx
, R_028710_SPI_SHADER_Z_FORMAT
,
1528 SI_TRACKED_SPI_SHADER_Z_FORMAT
,
1529 shader
->ctx_reg
.ps
.spi_shader_z_format
,
1530 shader
->ctx_reg
.ps
.spi_shader_col_format
);
1532 radeon_opt_set_context_reg(sctx
, R_02823C_CB_SHADER_MASK
,
1533 SI_TRACKED_CB_SHADER_MASK
,
1534 shader
->ctx_reg
.ps
.cb_shader_mask
);
1536 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1537 sctx
->context_roll
= true;
1540 static void si_shader_ps(struct si_screen
*sscreen
, struct si_shader
*shader
)
1542 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1543 struct si_pm4_state
*pm4
;
1544 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1545 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1547 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1549 /* we need to enable at least one of them, otherwise we hang the GPU */
1550 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1551 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1552 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1553 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1554 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1555 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1556 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1557 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1558 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1559 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
1560 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1561 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1562 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1563 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1565 /* Validate interpolation optimization flags (read as implications). */
1566 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1567 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1568 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1569 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1570 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1571 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1572 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1573 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1574 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1575 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1576 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1577 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1578 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1579 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1580 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1581 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1582 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1583 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1585 /* Validate cases when the optimizations are off (read as implications). */
1586 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1587 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1588 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1589 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1590 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1591 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1593 pm4
= si_get_shader_pm4_state(shader
);
1597 pm4
->atom
.emit
= si_emit_shader_ps
;
1599 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1601 * 0 -> Position = pixel center
1602 * 1 -> Position = pixel centroid
1603 * 2 -> Position = at sample position
1605 * From GLSL 4.5 specification, section 7.1:
1606 * "The variable gl_FragCoord is available as an input variable from
1607 * within fragment shaders and it holds the window relative coordinates
1608 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1609 * value can be for any location within the pixel, or one of the
1610 * fragment samples. The use of centroid does not further restrict
1611 * this value to be inside the current primitive."
1613 * Meaning that centroid has no effect and we can return anything within
1614 * the pixel. Thus, return the value at sample position, because that's
1615 * the most accurate one shaders can get.
1617 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1619 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1620 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1621 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1623 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1624 cb_shader_mask
= ac_get_cb_shader_mask(spi_shader_col_format
);
1626 /* Ensure that some export memory is always allocated, for two reasons:
1628 * 1) Correctness: The hardware ignores the EXEC mask if no export
1629 * memory is allocated, so KILL and alpha test do not work correctly
1631 * 2) Performance: Every shader needs at least a NULL export, even when
1632 * it writes no color/depth output. The NULL export instruction
1633 * stalls without this setting.
1635 * Don't add this to CB_SHADER_MASK.
1637 * GFX10 supports pixel shaders without exports by setting both
1638 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1639 * instructions if any are present.
1641 if ((sscreen
->info
.chip_class
<= GFX9
||
1643 shader
->key
.part
.ps
.epilog
.alpha_func
!= PIPE_FUNC_ALWAYS
) &&
1644 !spi_shader_col_format
&&
1645 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1646 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1648 shader
->ctx_reg
.ps
.spi_ps_input_ena
= input_ena
;
1649 shader
->ctx_reg
.ps
.spi_ps_input_addr
= shader
->config
.spi_ps_input_addr
;
1651 /* Set interpolation controls. */
1652 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
)) |
1653 S_0286D8_PS_W32_EN(sscreen
->ps_wave_size
== 32);
1655 shader
->ctx_reg
.ps
.spi_baryc_cntl
= spi_baryc_cntl
;
1656 shader
->ctx_reg
.ps
.spi_ps_in_control
= spi_ps_in_control
;
1657 shader
->ctx_reg
.ps
.spi_shader_z_format
=
1658 ac_get_spi_shader_z_format(info
->writes_z
,
1659 info
->writes_stencil
,
1660 info
->writes_samplemask
);
1661 shader
->ctx_reg
.ps
.spi_shader_col_format
= spi_shader_col_format
;
1662 shader
->ctx_reg
.ps
.cb_shader_mask
= cb_shader_mask
;
1664 va
= shader
->bo
->gpu_address
;
1665 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1666 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1667 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, S_00B024_MEM_BASE(va
>> 40));
1670 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) /
1671 (sscreen
->ps_wave_size
== 32 ? 8 : 4)) |
1672 S_00B028_DX10_CLAMP(1) |
1673 S_00B028_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1674 S_00B028_FLOAT_MODE(shader
->config
.float_mode
);
1676 if (sscreen
->info
.chip_class
< GFX10
) {
1677 rsrc1
|= S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1680 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
, rsrc1
);
1681 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1682 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1683 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1684 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1687 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1688 struct si_shader
*shader
)
1690 switch (shader
->selector
->type
) {
1691 case PIPE_SHADER_VERTEX
:
1692 if (shader
->key
.as_ls
)
1693 si_shader_ls(sscreen
, shader
);
1694 else if (shader
->key
.as_es
)
1695 si_shader_es(sscreen
, shader
);
1696 else if (shader
->key
.as_ngg
)
1697 gfx10_shader_ngg(sscreen
, shader
);
1699 si_shader_vs(sscreen
, shader
, NULL
);
1701 case PIPE_SHADER_TESS_CTRL
:
1702 si_shader_hs(sscreen
, shader
);
1704 case PIPE_SHADER_TESS_EVAL
:
1705 if (shader
->key
.as_es
)
1706 si_shader_es(sscreen
, shader
);
1707 else if (shader
->key
.as_ngg
)
1708 gfx10_shader_ngg(sscreen
, shader
);
1710 si_shader_vs(sscreen
, shader
, NULL
);
1712 case PIPE_SHADER_GEOMETRY
:
1713 if (shader
->key
.as_ngg
)
1714 gfx10_shader_ngg(sscreen
, shader
);
1716 si_shader_gs(sscreen
, shader
);
1718 case PIPE_SHADER_FRAGMENT
:
1719 si_shader_ps(sscreen
, shader
);
1726 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1728 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1729 return sctx
->queued
.named
.dsa
->alpha_func
;
1732 void si_shader_selector_key_vs(struct si_context
*sctx
,
1733 struct si_shader_selector
*vs
,
1734 struct si_shader_key
*key
,
1735 struct si_vs_prolog_bits
*prolog_key
)
1737 if (!sctx
->vertex_elements
||
1738 vs
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
])
1741 struct si_vertex_elements
*elts
= sctx
->vertex_elements
;
1743 prolog_key
->instance_divisor_is_one
= elts
->instance_divisor_is_one
;
1744 prolog_key
->instance_divisor_is_fetched
= elts
->instance_divisor_is_fetched
;
1745 prolog_key
->unpack_instance_id_from_vertex_id
=
1746 sctx
->prim_discard_cs_instancing
;
1748 /* Prefer a monolithic shader to allow scheduling divisions around
1750 if (prolog_key
->instance_divisor_is_fetched
)
1751 key
->opt
.prefer_mono
= 1;
1753 unsigned count
= MIN2(vs
->info
.num_inputs
, elts
->count
);
1754 unsigned count_mask
= (1 << count
) - 1;
1755 unsigned fix
= elts
->fix_fetch_always
& count_mask
;
1756 unsigned opencode
= elts
->fix_fetch_opencode
& count_mask
;
1758 if (sctx
->vertex_buffer_unaligned
& elts
->vb_alignment_check_mask
) {
1759 uint32_t mask
= elts
->fix_fetch_unaligned
& count_mask
;
1761 unsigned i
= u_bit_scan(&mask
);
1762 unsigned log_hw_load_size
= 1 + ((elts
->hw_load_is_dword
>> i
) & 1);
1763 unsigned vbidx
= elts
->vertex_buffer_index
[i
];
1764 struct pipe_vertex_buffer
*vb
= &sctx
->vertex_buffer
[vbidx
];
1765 unsigned align_mask
= (1 << log_hw_load_size
) - 1;
1766 if (vb
->buffer_offset
& align_mask
||
1767 vb
->stride
& align_mask
) {
1775 unsigned i
= u_bit_scan(&fix
);
1776 key
->mono
.vs_fix_fetch
[i
].bits
= elts
->fix_fetch
[i
];
1778 key
->mono
.vs_fetch_opencode
= opencode
;
1781 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1782 struct si_shader_selector
*vs
,
1783 struct si_shader_key
*key
)
1785 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1787 key
->opt
.clip_disable
=
1788 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1789 (vs
->info
.clipdist_writemask
||
1790 vs
->info
.writes_clipvertex
) &&
1791 !vs
->info
.culldist_writemask
;
1793 /* Find out if PS is disabled. */
1794 bool ps_disabled
= true;
1796 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1797 ps
->info
.writes_z
||
1798 ps
->info
.writes_stencil
||
1799 ps
->info
.writes_samplemask
||
1800 sctx
->queued
.named
.blend
->alpha_to_coverage
||
1801 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1802 unsigned ps_colormask
= si_get_total_colormask(sctx
);
1804 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1807 !ps
->info
.writes_memory
);
1810 /* Find out which VS outputs aren't used by the PS. */
1811 uint64_t outputs_written
= vs
->outputs_written_before_ps
;
1812 uint64_t inputs_read
= 0;
1814 /* Ignore outputs that are not passed from VS to PS. */
1815 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION
, 0, true)) |
1816 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE
, 0, true)) |
1817 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX
, 0, true)));
1820 inputs_read
= ps
->inputs_read
;
1823 uint64_t linked
= outputs_written
& inputs_read
;
1825 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1828 /* Compute the key for the hw shader variant */
1829 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1830 struct si_shader_selector
*sel
,
1831 union si_vgt_stages_key stages_key
,
1832 struct si_shader_key
*key
)
1834 struct si_context
*sctx
= (struct si_context
*)ctx
;
1836 memset(key
, 0, sizeof(*key
));
1838 switch (sel
->type
) {
1839 case PIPE_SHADER_VERTEX
:
1840 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1842 if (sctx
->tes_shader
.cso
)
1844 else if (sctx
->gs_shader
.cso
) {
1846 key
->as_ngg
= stages_key
.u
.ngg
;
1848 key
->as_ngg
= stages_key
.u
.ngg
;
1849 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1851 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1852 key
->mono
.u
.vs_export_prim_id
= 1;
1855 case PIPE_SHADER_TESS_CTRL
:
1856 if (sctx
->chip_class
>= GFX9
) {
1857 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1858 key
, &key
->part
.tcs
.ls_prolog
);
1859 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1861 /* When the LS VGPR fix is needed, monolithic shaders
1863 * - avoid initializing EXEC in both the LS prolog
1864 * and the LS main part when !vs_needs_prolog
1865 * - remove the fixup for unused input VGPRs
1867 key
->part
.tcs
.ls_prolog
.ls_vgpr_fix
= sctx
->ls_vgpr_fix
;
1869 /* The LS output / HS input layout can be communicated
1870 * directly instead of via user SGPRs for merged LS-HS.
1871 * The LS VGPR fix prefers this too.
1873 key
->opt
.prefer_mono
= 1;
1876 key
->part
.tcs
.epilog
.prim_mode
=
1877 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1878 key
->part
.tcs
.epilog
.invoc0_tess_factors_are_def
=
1879 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1880 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1881 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1883 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1884 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1886 case PIPE_SHADER_TESS_EVAL
:
1887 key
->as_ngg
= stages_key
.u
.ngg
;
1889 if (sctx
->gs_shader
.cso
)
1892 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1894 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1895 key
->mono
.u
.vs_export_prim_id
= 1;
1898 case PIPE_SHADER_GEOMETRY
:
1899 if (sctx
->chip_class
>= GFX9
) {
1900 if (sctx
->tes_shader
.cso
) {
1901 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1903 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1904 key
, &key
->part
.gs
.vs_prolog
);
1905 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1906 key
->part
.gs
.prolog
.gfx9_prev_is_vs
= 1;
1909 key
->as_ngg
= stages_key
.u
.ngg
;
1911 /* Merged ES-GS can have unbalanced wave usage.
1913 * ES threads are per-vertex, while GS threads are
1914 * per-primitive. So without any amplification, there
1915 * are fewer GS threads than ES threads, which can result
1916 * in empty (no-op) GS waves. With too much amplification,
1917 * there are more GS threads than ES threads, which
1918 * can result in empty (no-op) ES waves.
1920 * Non-monolithic shaders are implemented by setting EXEC
1921 * at the beginning of shader parts, and don't jump to
1922 * the end if EXEC is 0.
1924 * Monolithic shaders use conditional blocks, so they can
1925 * jump and skip empty waves of ES or GS. So set this to
1926 * always use optimized variants, which are monolithic.
1928 key
->opt
.prefer_mono
= 1;
1930 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1932 case PIPE_SHADER_FRAGMENT
: {
1933 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1934 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1936 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1937 sel
->info
.colors_written
== 0x1)
1938 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1940 /* Select the shader color format based on whether
1941 * blending or alpha are needed.
1943 key
->part
.ps
.epilog
.spi_shader_col_format
=
1944 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1945 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1946 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1947 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1948 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1949 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1950 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1951 sctx
->framebuffer
.spi_shader_col_format
);
1952 key
->part
.ps
.epilog
.spi_shader_col_format
&= blend
->cb_target_enabled_4bit
;
1954 /* The output for dual source blending should have
1955 * the same format as the first output.
1957 if (blend
->dual_src_blend
) {
1958 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1959 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1962 /* If alpha-to-coverage is enabled, we have to export alpha
1963 * even if there is no color buffer.
1965 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1966 blend
->alpha_to_coverage
)
1967 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1969 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1970 * to the range supported by the type if a channel has less
1971 * than 16 bits and the export format is 16_ABGR.
1973 if (sctx
->chip_class
<= GFX7
&& sctx
->family
!= CHIP_HAWAII
) {
1974 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1975 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1978 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1979 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1980 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1981 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1982 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1985 bool is_poly
= !util_prim_is_points_or_lines(sctx
->current_rast_prim
);
1986 bool is_line
= util_prim_is_lines(sctx
->current_rast_prim
);
1988 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1989 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1991 key
->part
.ps
.epilog
.alpha_to_one
= blend
->alpha_to_one
&&
1992 rs
->multisample_enable
;
1994 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1995 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1996 (is_line
&& rs
->line_smooth
)) &&
1997 sctx
->framebuffer
.nr_samples
<= 1;
1998 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
2000 if (sctx
->ps_iter_samples
> 1 &&
2001 sel
->info
.reads_samplemask
) {
2002 key
->part
.ps
.prolog
.samplemask_log_ps_iter
=
2003 util_logbase2(sctx
->ps_iter_samples
);
2006 if (rs
->force_persample_interp
&&
2007 rs
->multisample_enable
&&
2008 sctx
->framebuffer
.nr_samples
> 1 &&
2009 sctx
->ps_iter_samples
> 1) {
2010 key
->part
.ps
.prolog
.force_persp_sample_interp
=
2011 sel
->info
.uses_persp_center
||
2012 sel
->info
.uses_persp_centroid
;
2014 key
->part
.ps
.prolog
.force_linear_sample_interp
=
2015 sel
->info
.uses_linear_center
||
2016 sel
->info
.uses_linear_centroid
;
2017 } else if (rs
->multisample_enable
&&
2018 sctx
->framebuffer
.nr_samples
> 1) {
2019 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
2020 sel
->info
.uses_persp_center
&&
2021 sel
->info
.uses_persp_centroid
;
2022 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
2023 sel
->info
.uses_linear_center
&&
2024 sel
->info
.uses_linear_centroid
;
2026 /* Make sure SPI doesn't compute more than 1 pair
2027 * of (i,j), which is the optimization here. */
2028 key
->part
.ps
.prolog
.force_persp_center_interp
=
2029 sel
->info
.uses_persp_center
+
2030 sel
->info
.uses_persp_centroid
+
2031 sel
->info
.uses_persp_sample
> 1;
2033 key
->part
.ps
.prolog
.force_linear_center_interp
=
2034 sel
->info
.uses_linear_center
+
2035 sel
->info
.uses_linear_centroid
+
2036 sel
->info
.uses_linear_sample
> 1;
2038 if (sel
->info
.uses_persp_opcode_interp_sample
||
2039 sel
->info
.uses_linear_opcode_interp_sample
)
2040 key
->mono
.u
.ps
.interpolate_at_sample_force_center
= 1;
2043 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
2045 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2046 if (sctx
->ps_uses_fbfetch
&& !sctx
->blitter
->running
) {
2047 struct pipe_surface
*cb0
= sctx
->framebuffer
.state
.cbufs
[0];
2048 struct pipe_resource
*tex
= cb0
->texture
;
2050 /* 1D textures are allocated and used as 2D on GFX9. */
2051 key
->mono
.u
.ps
.fbfetch_msaa
= sctx
->framebuffer
.nr_samples
> 1;
2052 key
->mono
.u
.ps
.fbfetch_is_1D
= sctx
->chip_class
!= GFX9
&&
2053 (tex
->target
== PIPE_TEXTURE_1D
||
2054 tex
->target
== PIPE_TEXTURE_1D_ARRAY
);
2055 key
->mono
.u
.ps
.fbfetch_layered
= tex
->target
== PIPE_TEXTURE_1D_ARRAY
||
2056 tex
->target
== PIPE_TEXTURE_2D_ARRAY
||
2057 tex
->target
== PIPE_TEXTURE_CUBE
||
2058 tex
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
2059 tex
->target
== PIPE_TEXTURE_3D
;
2067 if (unlikely(sctx
->screen
->debug_flags
& DBG(NO_OPT_VARIANT
)))
2068 memset(&key
->opt
, 0, sizeof(key
->opt
));
2071 static void si_build_shader_variant(struct si_shader
*shader
,
2075 struct si_shader_selector
*sel
= shader
->selector
;
2076 struct si_screen
*sscreen
= sel
->screen
;
2077 struct ac_llvm_compiler
*compiler
;
2078 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
2080 if (thread_index
>= 0) {
2082 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler_lowp
));
2083 compiler
= &sscreen
->compiler_lowp
[thread_index
];
2085 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2086 compiler
= &sscreen
->compiler
[thread_index
];
2091 assert(!low_priority
);
2092 compiler
= shader
->compiler_ctx_state
.compiler
;
2095 if (!compiler
->passes
)
2096 si_init_compiler(sscreen
, compiler
);
2098 if (unlikely(!si_shader_create(sscreen
, compiler
, shader
, debug
))) {
2099 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2101 shader
->compilation_failed
= true;
2105 if (shader
->compiler_ctx_state
.is_debug_context
) {
2106 FILE *f
= open_memstream(&shader
->shader_log
,
2107 &shader
->shader_log_size
);
2109 si_shader_dump(sscreen
, shader
, NULL
, f
, false);
2114 si_shader_init_pm4_state(sscreen
, shader
);
2117 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
2119 struct si_shader
*shader
= (struct si_shader
*)job
;
2121 assert(thread_index
>= 0);
2123 si_build_shader_variant(shader
, thread_index
, true);
2126 static const struct si_shader_key zeroed
;
2128 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
2129 struct si_shader_selector
*sel
,
2130 struct si_compiler_ctx_state
*compiler_state
,
2131 struct si_shader_key
*key
)
2133 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
2136 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
2141 /* We can leave the fence as permanently signaled because the
2142 * main part becomes visible globally only after it has been
2144 util_queue_fence_init(&main_part
->ready
);
2146 main_part
->selector
= sel
;
2147 main_part
->key
.as_es
= key
->as_es
;
2148 main_part
->key
.as_ls
= key
->as_ls
;
2149 main_part
->key
.as_ngg
= key
->as_ngg
;
2150 main_part
->is_monolithic
= false;
2152 if (si_compile_tgsi_shader(sscreen
, compiler_state
->compiler
,
2153 main_part
, &compiler_state
->debug
) != 0) {
2163 * Select a shader variant according to the shader key.
2165 * \param optimized_or_none If the key describes an optimized shader variant and
2166 * the compilation isn't finished, don't select any
2167 * shader and return an error.
2169 int si_shader_select_with_key(struct si_screen
*sscreen
,
2170 struct si_shader_ctx_state
*state
,
2171 struct si_compiler_ctx_state
*compiler_state
,
2172 struct si_shader_key
*key
,
2174 bool optimized_or_none
)
2176 struct si_shader_selector
*sel
= state
->cso
;
2177 struct si_shader_selector
*previous_stage_sel
= NULL
;
2178 struct si_shader
*current
= state
->current
;
2179 struct si_shader
*iter
, *shader
= NULL
;
2182 /* Check if we don't need to change anything.
2183 * This path is also used for most shaders that don't need multiple
2184 * variants, it will cost just a computation of the key and this
2186 if (likely(current
&&
2187 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0)) {
2188 if (unlikely(!util_queue_fence_is_signalled(¤t
->ready
))) {
2189 if (current
->is_optimized
) {
2190 if (optimized_or_none
)
2193 memset(&key
->opt
, 0, sizeof(key
->opt
));
2194 goto current_not_ready
;
2197 util_queue_fence_wait(¤t
->ready
);
2200 return current
->compilation_failed
? -1 : 0;
2204 /* This must be done before the mutex is locked, because async GS
2205 * compilation calls this function too, and therefore must enter
2208 * Only wait if we are in a draw call. Don't wait if we are
2209 * in a compiler thread.
2211 if (thread_index
< 0)
2212 util_queue_fence_wait(&sel
->ready
);
2214 simple_mtx_lock(&sel
->mutex
);
2216 /* Find the shader variant. */
2217 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
2218 /* Don't check the "current" shader. We checked it above. */
2219 if (current
!= iter
&&
2220 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
2221 simple_mtx_unlock(&sel
->mutex
);
2223 if (unlikely(!util_queue_fence_is_signalled(&iter
->ready
))) {
2224 /* If it's an optimized shader and its compilation has
2225 * been started but isn't done, use the unoptimized
2226 * shader so as not to cause a stall due to compilation.
2228 if (iter
->is_optimized
) {
2229 if (optimized_or_none
)
2231 memset(&key
->opt
, 0, sizeof(key
->opt
));
2235 util_queue_fence_wait(&iter
->ready
);
2238 if (iter
->compilation_failed
) {
2239 return -1; /* skip the draw call */
2242 state
->current
= iter
;
2247 /* Build a new shader. */
2248 shader
= CALLOC_STRUCT(si_shader
);
2250 simple_mtx_unlock(&sel
->mutex
);
2254 util_queue_fence_init(&shader
->ready
);
2256 shader
->selector
= sel
;
2258 shader
->compiler_ctx_state
= *compiler_state
;
2260 /* If this is a merged shader, get the first shader's selector. */
2261 if (sscreen
->info
.chip_class
>= GFX9
) {
2262 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
2263 previous_stage_sel
= key
->part
.tcs
.ls
;
2264 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
2265 previous_stage_sel
= key
->part
.gs
.es
;
2267 /* We need to wait for the previous shader. */
2268 if (previous_stage_sel
&& thread_index
< 0)
2269 util_queue_fence_wait(&previous_stage_sel
->ready
);
2272 bool is_pure_monolithic
=
2273 sscreen
->use_monolithic_shaders
||
2274 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
2276 /* Compile the main shader part if it doesn't exist. This can happen
2277 * if the initial guess was wrong.
2279 * The prim discard CS doesn't need the main shader part.
2281 if (!is_pure_monolithic
&&
2282 !key
->opt
.vs_as_prim_discard_cs
) {
2285 /* Make sure the main shader part is present. This is needed
2286 * for shaders that can be compiled as VS, LS, or ES, and only
2287 * one of them is compiled at creation.
2289 * It is also needed for GS, which can be compiled as non-NGG
2292 * For merged shaders, check that the starting shader's main
2295 if (previous_stage_sel
) {
2296 struct si_shader_key shader1_key
= zeroed
;
2298 if (sel
->type
== PIPE_SHADER_TESS_CTRL
) {
2299 shader1_key
.as_ls
= 1;
2300 } else if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
2301 shader1_key
.as_es
= 1;
2302 shader1_key
.as_ngg
= key
->as_ngg
; /* for Wave32 vs Wave64 */
2307 simple_mtx_lock(&previous_stage_sel
->mutex
);
2308 ok
= si_check_missing_main_part(sscreen
,
2310 compiler_state
, &shader1_key
);
2311 simple_mtx_unlock(&previous_stage_sel
->mutex
);
2315 ok
= si_check_missing_main_part(sscreen
, sel
,
2316 compiler_state
, key
);
2321 simple_mtx_unlock(&sel
->mutex
);
2322 return -ENOMEM
; /* skip the draw call */
2326 /* Keep the reference to the 1st shader of merged shaders, so that
2327 * Gallium can't destroy it before we destroy the 2nd shader.
2329 * Set sctx = NULL, because it's unused if we're not releasing
2330 * the shader, and we don't have any sctx here.
2332 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
2333 previous_stage_sel
);
2335 /* Monolithic-only shaders don't make a distinction between optimized
2336 * and unoptimized. */
2337 shader
->is_monolithic
=
2338 is_pure_monolithic
||
2339 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2341 /* The prim discard CS is always optimized. */
2342 shader
->is_optimized
=
2343 (!is_pure_monolithic
|| key
->opt
.vs_as_prim_discard_cs
) &&
2344 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2346 /* If it's an optimized shader, compile it asynchronously. */
2347 if (shader
->is_optimized
&& thread_index
< 0) {
2348 /* Compile it asynchronously. */
2349 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
,
2350 shader
, &shader
->ready
,
2351 si_build_shader_variant_low_priority
, NULL
,
2354 /* Add only after the ready fence was reset, to guard against a
2355 * race with si_bind_XX_shader. */
2356 if (!sel
->last_variant
) {
2357 sel
->first_variant
= shader
;
2358 sel
->last_variant
= shader
;
2360 sel
->last_variant
->next_variant
= shader
;
2361 sel
->last_variant
= shader
;
2364 /* Use the default (unoptimized) shader for now. */
2365 memset(&key
->opt
, 0, sizeof(key
->opt
));
2366 simple_mtx_unlock(&sel
->mutex
);
2368 if (sscreen
->options
.sync_compile
)
2369 util_queue_fence_wait(&shader
->ready
);
2371 if (optimized_or_none
)
2376 /* Reset the fence before adding to the variant list. */
2377 util_queue_fence_reset(&shader
->ready
);
2379 if (!sel
->last_variant
) {
2380 sel
->first_variant
= shader
;
2381 sel
->last_variant
= shader
;
2383 sel
->last_variant
->next_variant
= shader
;
2384 sel
->last_variant
= shader
;
2387 simple_mtx_unlock(&sel
->mutex
);
2389 assert(!shader
->is_optimized
);
2390 si_build_shader_variant(shader
, thread_index
, false);
2392 util_queue_fence_signal(&shader
->ready
);
2394 if (!shader
->compilation_failed
)
2395 state
->current
= shader
;
2397 return shader
->compilation_failed
? -1 : 0;
2400 static int si_shader_select(struct pipe_context
*ctx
,
2401 struct si_shader_ctx_state
*state
,
2402 union si_vgt_stages_key stages_key
,
2403 struct si_compiler_ctx_state
*compiler_state
)
2405 struct si_context
*sctx
= (struct si_context
*)ctx
;
2406 struct si_shader_key key
;
2408 si_shader_selector_key(ctx
, state
->cso
, stages_key
, &key
);
2409 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
2413 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
2415 struct si_shader_key
*key
)
2417 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
2419 switch (info
->processor
) {
2420 case PIPE_SHADER_VERTEX
:
2421 switch (next_shader
) {
2422 case PIPE_SHADER_GEOMETRY
:
2425 case PIPE_SHADER_TESS_CTRL
:
2426 case PIPE_SHADER_TESS_EVAL
:
2430 /* If POSITION isn't written, it can only be a HW VS
2431 * if streamout is used. If streamout isn't used,
2432 * assume that it's a HW LS. (the next shader is TCS)
2433 * This heuristic is needed for separate shader objects.
2435 if (!info
->writes_position
&& !streamout
)
2440 case PIPE_SHADER_TESS_EVAL
:
2441 if (next_shader
== PIPE_SHADER_GEOMETRY
||
2442 !info
->writes_position
)
2449 * Compile the main shader part or the monolithic shader as part of
2450 * si_shader_selector initialization. Since it can be done asynchronously,
2451 * there is no way to report compile failures to applications.
2453 static void si_init_shader_selector_async(void *job
, int thread_index
)
2455 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
2456 struct si_screen
*sscreen
= sel
->screen
;
2457 struct ac_llvm_compiler
*compiler
;
2458 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
2460 assert(!debug
->debug_message
|| debug
->async
);
2461 assert(thread_index
>= 0);
2462 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2463 compiler
= &sscreen
->compiler
[thread_index
];
2465 if (!compiler
->passes
)
2466 si_init_compiler(sscreen
, compiler
);
2468 /* Compile the main shader part for use with a prolog and/or epilog.
2469 * If this fails, the driver will try to compile a monolithic shader
2472 if (!sscreen
->use_monolithic_shaders
) {
2473 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
2474 unsigned char ir_sha1_cache_key
[20];
2477 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
2481 /* We can leave the fence signaled because use of the default
2482 * main part is guarded by the selector's ready fence. */
2483 util_queue_fence_init(&shader
->ready
);
2485 shader
->selector
= sel
;
2486 shader
->is_monolithic
= false;
2487 si_parse_next_shader_property(&sel
->info
,
2488 sel
->so
.num_outputs
!= 0,
2491 if (sscreen
->use_ngg
&&
2492 (!sel
->so
.num_outputs
|| sscreen
->use_ngg_streamout
) &&
2493 ((sel
->type
== PIPE_SHADER_VERTEX
&& !shader
->key
.as_ls
) ||
2494 sel
->type
== PIPE_SHADER_TESS_EVAL
||
2495 sel
->type
== PIPE_SHADER_GEOMETRY
))
2496 shader
->key
.as_ngg
= 1;
2498 if (sel
->tokens
|| sel
->nir
) {
2499 si_get_ir_cache_key(sel
, shader
->key
.as_ngg
,
2500 shader
->key
.as_es
, ir_sha1_cache_key
);
2503 /* Try to load the shader from the shader cache. */
2504 simple_mtx_lock(&sscreen
->shader_cache_mutex
);
2506 if (si_shader_cache_load_shader(sscreen
, ir_sha1_cache_key
, shader
)) {
2507 simple_mtx_unlock(&sscreen
->shader_cache_mutex
);
2508 si_shader_dump_stats_for_shader_db(sscreen
, shader
, debug
);
2510 simple_mtx_unlock(&sscreen
->shader_cache_mutex
);
2512 /* Compile the shader if it hasn't been loaded from the cache. */
2513 if (si_compile_tgsi_shader(sscreen
, compiler
, shader
,
2516 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
2520 simple_mtx_lock(&sscreen
->shader_cache_mutex
);
2521 si_shader_cache_insert_shader(sscreen
, ir_sha1_cache_key
,
2523 simple_mtx_unlock(&sscreen
->shader_cache_mutex
);
2526 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
2528 /* Unset "outputs_written" flags for outputs converted to
2529 * DEFAULT_VAL, so that later inter-shader optimizations don't
2530 * try to eliminate outputs that don't exist in the final
2533 * This is only done if non-monolithic shaders are enabled.
2535 if ((sel
->type
== PIPE_SHADER_VERTEX
||
2536 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
2537 !shader
->key
.as_ls
&&
2538 !shader
->key
.as_es
) {
2541 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2542 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
2544 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
2547 unsigned name
= sel
->info
.output_semantic_name
[i
];
2548 unsigned index
= sel
->info
.output_semantic_index
[i
];
2552 case TGSI_SEMANTIC_GENERIC
:
2553 /* don't process indices the function can't handle */
2554 if (index
>= SI_MAX_IO_GENERIC
)
2558 id
= si_shader_io_get_unique_index(name
, index
, true);
2559 sel
->outputs_written_before_ps
&= ~(1ull << id
);
2561 case TGSI_SEMANTIC_POSITION
: /* ignore these */
2562 case TGSI_SEMANTIC_PSIZE
:
2563 case TGSI_SEMANTIC_CLIPVERTEX
:
2564 case TGSI_SEMANTIC_EDGEFLAG
:
2571 /* The GS copy shader is always pre-compiled. */
2572 if (sel
->type
== PIPE_SHADER_GEOMETRY
&&
2573 (!sscreen
->use_ngg
||
2574 !sscreen
->use_ngg_streamout
|| /* also for PRIMITIVES_GENERATED */
2575 sel
->tess_turns_off_ngg
)) {
2576 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, compiler
, sel
, debug
);
2577 if (!sel
->gs_copy_shader
) {
2578 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
2582 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
2586 void si_schedule_initial_compile(struct si_context
*sctx
, unsigned processor
,
2587 struct util_queue_fence
*ready_fence
,
2588 struct si_compiler_ctx_state
*compiler_ctx_state
,
2589 void *job
, util_queue_execute_func execute
)
2591 util_queue_fence_init(ready_fence
);
2593 struct util_async_debug_callback async_debug
;
2595 (sctx
->debug
.debug_message
&& !sctx
->debug
.async
) ||
2597 si_can_dump_shader(sctx
->screen
, processor
);
2600 u_async_debug_init(&async_debug
);
2601 compiler_ctx_state
->debug
= async_debug
.base
;
2604 util_queue_add_job(&sctx
->screen
->shader_compiler_queue
, job
,
2605 ready_fence
, execute
, NULL
, 0);
2608 util_queue_fence_wait(ready_fence
);
2609 u_async_debug_drain(&async_debug
, &sctx
->debug
);
2610 u_async_debug_cleanup(&async_debug
);
2613 if (sctx
->screen
->options
.sync_compile
)
2614 util_queue_fence_wait(ready_fence
);
2617 /* Return descriptor slot usage masks from the given shader info. */
2618 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
2619 uint32_t *const_and_shader_buffers
,
2620 uint64_t *samplers_and_images
)
2622 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_msaa_images
, num_samplers
;
2624 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
2625 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
2626 /* two 8-byte images share one 16-byte slot */
2627 num_images
= align(util_last_bit(info
->images_declared
), 2);
2628 num_msaa_images
= align(util_last_bit(info
->msaa_images_declared
), 2);
2629 num_samplers
= util_last_bit(info
->samplers_declared
);
2631 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2632 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
2633 *const_and_shader_buffers
=
2634 u_bit_consecutive(start
, num_shaderbufs
+ num_constbufs
);
2637 * - fmask[last] ... fmask[0] go to [15-last .. 15]
2638 * - image[last] ... image[0] go to [31-last .. 31]
2639 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
2641 * FMASKs for images are placed separately, because MSAA images are rare,
2642 * and so we can benefit from a better cache hit rate if we keep image
2643 * descriptors together.
2645 if (num_msaa_images
)
2646 num_images
= SI_NUM_IMAGES
+ num_msaa_images
; /* add FMASK descriptors */
2648 start
= si_get_image_slot(num_images
- 1) / 2;
2649 *samplers_and_images
=
2650 u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
2653 static void *si_create_shader_selector(struct pipe_context
*ctx
,
2654 const struct pipe_shader_state
*state
)
2656 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
2657 struct si_context
*sctx
= (struct si_context
*)ctx
;
2658 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
2664 pipe_reference_init(&sel
->reference
, 1);
2665 sel
->screen
= sscreen
;
2666 sel
->compiler_ctx_state
.debug
= sctx
->debug
;
2667 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
2669 sel
->so
= state
->stream_output
;
2671 if (state
->type
== PIPE_SHADER_IR_TGSI
&&
2672 !sscreen
->options
.enable_nir
) {
2673 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
2679 tgsi_scan_shader(state
->tokens
, &sel
->info
);
2680 tgsi_scan_tess_ctrl(state
->tokens
, &sel
->info
, &sel
->tcs_info
);
2682 /* Fixup for TGSI: Set which opcode uses which (i,j) pair. */
2683 if (sel
->info
.uses_persp_opcode_interp_centroid
)
2684 sel
->info
.uses_persp_centroid
= true;
2686 if (sel
->info
.uses_linear_opcode_interp_centroid
)
2687 sel
->info
.uses_linear_centroid
= true;
2689 if (sel
->info
.uses_persp_opcode_interp_offset
||
2690 sel
->info
.uses_persp_opcode_interp_sample
)
2691 sel
->info
.uses_persp_center
= true;
2693 if (sel
->info
.uses_linear_opcode_interp_offset
||
2694 sel
->info
.uses_linear_opcode_interp_sample
)
2695 sel
->info
.uses_linear_center
= true;
2697 if (state
->type
== PIPE_SHADER_IR_TGSI
) {
2698 sel
->nir
= tgsi_to_nir(state
->tokens
, ctx
->screen
);
2700 assert(state
->type
== PIPE_SHADER_IR_NIR
);
2701 sel
->nir
= state
->ir
.nir
;
2704 si_nir_scan_shader(sel
->nir
, &sel
->info
);
2705 si_nir_scan_tess_ctrl(sel
->nir
, &sel
->tcs_info
);
2706 si_nir_adjust_driver_locations(sel
->nir
);
2709 sel
->type
= sel
->info
.processor
;
2710 p_atomic_inc(&sscreen
->num_shaders_created
);
2711 si_get_active_slot_masks(&sel
->info
,
2712 &sel
->active_const_and_shader_buffers
,
2713 &sel
->active_samplers_and_images
);
2715 /* Record which streamout buffers are enabled. */
2716 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
2717 sel
->enabled_streamout_buffer_mask
|=
2718 (1 << sel
->so
.output
[i
].output_buffer
) <<
2719 (sel
->so
.output
[i
].stream
* 4);
2722 /* The prolog is a no-op if there are no inputs. */
2723 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
2724 sel
->info
.num_inputs
&&
2725 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
];
2727 sel
->force_correct_derivs_after_kill
=
2728 sel
->type
== PIPE_SHADER_FRAGMENT
&&
2729 sel
->info
.uses_derivatives
&&
2730 sel
->info
.uses_kill
&&
2731 sctx
->screen
->debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
2733 sel
->prim_discard_cs_allowed
=
2734 sel
->type
== PIPE_SHADER_VERTEX
&&
2735 !sel
->info
.uses_bindless_images
&&
2736 !sel
->info
.uses_bindless_samplers
&&
2737 !sel
->info
.writes_memory
&&
2738 !sel
->info
.writes_viewport_index
&&
2739 !sel
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] &&
2740 !sel
->so
.num_outputs
;
2742 switch (sel
->type
) {
2743 case PIPE_SHADER_GEOMETRY
:
2744 sel
->gs_output_prim
=
2745 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
2747 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2748 sel
->rast_prim
= sel
->gs_output_prim
;
2749 if (util_rast_prim_is_triangles(sel
->rast_prim
))
2750 sel
->rast_prim
= PIPE_PRIM_TRIANGLES
;
2752 sel
->gs_max_out_vertices
=
2753 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
2754 sel
->gs_num_invocations
=
2755 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2756 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2757 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
2758 sel
->gs_max_out_vertices
;
2760 sel
->max_gs_stream
= 0;
2761 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2762 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
2763 sel
->so
.output
[i
].stream
);
2765 sel
->gs_input_verts_per_prim
=
2766 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2768 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2769 sel
->tess_turns_off_ngg
=
2770 (sscreen
->info
.family
== CHIP_NAVI10
||
2771 sscreen
->info
.family
== CHIP_NAVI12
||
2772 sscreen
->info
.family
== CHIP_NAVI14
) &&
2773 sel
->gs_num_invocations
* sel
->gs_max_out_vertices
> 256;
2776 case PIPE_SHADER_TESS_CTRL
:
2777 /* Always reserve space for these. */
2778 sel
->patch_outputs_written
|=
2779 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0)) |
2780 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0));
2782 case PIPE_SHADER_VERTEX
:
2783 case PIPE_SHADER_TESS_EVAL
:
2784 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2785 unsigned name
= sel
->info
.output_semantic_name
[i
];
2786 unsigned index
= sel
->info
.output_semantic_index
[i
];
2789 case TGSI_SEMANTIC_TESSINNER
:
2790 case TGSI_SEMANTIC_TESSOUTER
:
2791 case TGSI_SEMANTIC_PATCH
:
2792 sel
->patch_outputs_written
|=
2793 1ull << si_shader_io_get_unique_index_patch(name
, index
);
2796 case TGSI_SEMANTIC_GENERIC
:
2797 /* don't process indices the function can't handle */
2798 if (index
>= SI_MAX_IO_GENERIC
)
2802 sel
->outputs_written
|=
2803 1ull << si_shader_io_get_unique_index(name
, index
, false);
2804 sel
->outputs_written_before_ps
|=
2805 1ull << si_shader_io_get_unique_index(name
, index
, true);
2807 case TGSI_SEMANTIC_EDGEFLAG
:
2811 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2812 sel
->lshs_vertex_stride
= sel
->esgs_itemsize
;
2814 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2815 * will start on a different bank. (except for the maximum 32*16).
2817 if (sel
->lshs_vertex_stride
< 32*16)
2818 sel
->lshs_vertex_stride
+= 4;
2820 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2821 * conflicts, i.e. each vertex will start at a different bank.
2823 if (sctx
->chip_class
>= GFX9
)
2824 sel
->esgs_itemsize
+= 4;
2826 assert(((sel
->esgs_itemsize
/ 4) & C_028AAC_ITEMSIZE
) == 0);
2829 if (sel
->info
.properties
[TGSI_PROPERTY_TES_POINT_MODE
])
2830 sel
->rast_prim
= PIPE_PRIM_POINTS
;
2831 else if (sel
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] == PIPE_PRIM_LINES
)
2832 sel
->rast_prim
= PIPE_PRIM_LINE_STRIP
;
2834 sel
->rast_prim
= PIPE_PRIM_TRIANGLES
;
2837 case PIPE_SHADER_FRAGMENT
:
2838 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2839 unsigned name
= sel
->info
.input_semantic_name
[i
];
2840 unsigned index
= sel
->info
.input_semantic_index
[i
];
2843 case TGSI_SEMANTIC_GENERIC
:
2844 /* don't process indices the function can't handle */
2845 if (index
>= SI_MAX_IO_GENERIC
)
2850 1ull << si_shader_io_get_unique_index(name
, index
, true);
2852 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2857 for (i
= 0; i
< 8; i
++)
2858 if (sel
->info
.colors_written
& (1 << i
))
2859 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2861 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2862 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2863 int index
= sel
->info
.input_semantic_index
[i
];
2864 sel
->color_attr_index
[index
] = i
;
2871 /* PA_CL_VS_OUT_CNTL */
2872 if (sctx
->chip_class
<= GFX9
)
2873 sel
->pa_cl_vs_out_cntl
= si_get_vs_out_cntl(sel
, false);
2875 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
?
2876 SIX_BITS
: sel
->info
.clipdist_writemask
;
2877 sel
->culldist_mask
= sel
->info
.culldist_writemask
<<
2878 sel
->info
.num_written_clipdistance
;
2880 /* DB_SHADER_CONTROL */
2881 sel
->db_shader_control
=
2882 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2883 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2884 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2885 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2887 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2888 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2889 sel
->db_shader_control
|=
2890 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2892 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2893 sel
->db_shader_control
|=
2894 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2898 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2900 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2901 * --|-----------|------------|------------|--------------------|-------------------|-------------
2902 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2903 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2904 * 2 | false | true | n/a | LateZ | 1 | 0
2905 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2906 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2908 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2909 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2911 * Don't use ReZ without profiling !!!
2913 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2916 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2918 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2919 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2920 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
2921 } else if (sel
->info
.writes_memory
) {
2923 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
2924 S_02880C_EXEC_ON_HIER_FAIL(1);
2927 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2930 if (sel
->info
.properties
[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
])
2931 sel
->db_shader_control
|= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2933 (void) simple_mtx_init(&sel
->mutex
, mtx_plain
);
2935 si_schedule_initial_compile(sctx
, sel
->info
.processor
, &sel
->ready
,
2936 &sel
->compiler_ctx_state
, sel
,
2937 si_init_shader_selector_async
);
2941 static void si_update_streamout_state(struct si_context
*sctx
)
2943 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
2945 if (!shader_with_so
)
2948 sctx
->streamout
.enabled_stream_buffers_mask
=
2949 shader_with_so
->enabled_streamout_buffer_mask
;
2950 sctx
->streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
2953 static void si_update_clip_regs(struct si_context
*sctx
,
2954 struct si_shader_selector
*old_hw_vs
,
2955 struct si_shader
*old_hw_vs_variant
,
2956 struct si_shader_selector
*next_hw_vs
,
2957 struct si_shader
*next_hw_vs_variant
)
2961 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
2962 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
2963 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
2964 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
2965 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
||
2966 !old_hw_vs_variant
||
2967 !next_hw_vs_variant
||
2968 old_hw_vs_variant
->key
.opt
.clip_disable
!=
2969 next_hw_vs_variant
->key
.opt
.clip_disable
))
2970 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
2973 static void si_update_common_shader_state(struct si_context
*sctx
)
2975 sctx
->uses_bindless_samplers
=
2976 si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
2977 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
2978 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
2979 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
2980 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
2981 sctx
->uses_bindless_images
=
2982 si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
2983 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
2984 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
2985 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
2986 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
2987 sctx
->do_update_shaders
= true;
2990 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2992 struct si_context
*sctx
= (struct si_context
*)ctx
;
2993 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2994 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2995 struct si_shader_selector
*sel
= state
;
2997 if (sctx
->vs_shader
.cso
== sel
)
3000 sctx
->vs_shader
.cso
= sel
;
3001 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
3002 sctx
->num_vs_blit_sgprs
= sel
? sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
] : 0;
3004 if (si_update_ngg(sctx
))
3005 si_shader_change_notify(sctx
);
3007 si_update_common_shader_state(sctx
);
3008 si_update_vs_viewport_state(sctx
);
3009 si_set_active_descriptors_for_shader(sctx
, sel
);
3010 si_update_streamout_state(sctx
);
3011 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
3012 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3015 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
3017 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
3018 (sctx
->tes_shader
.cso
&&
3019 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
3020 (sctx
->tcs_shader
.cso
&&
3021 sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
3022 (sctx
->gs_shader
.cso
&&
3023 sctx
->gs_shader
.cso
->info
.uses_primid
) ||
3024 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&&
3025 sctx
->ps_shader
.cso
->info
.uses_primid
);
3028 bool si_update_ngg(struct si_context
*sctx
)
3030 if (!sctx
->screen
->use_ngg
) {
3035 bool new_ngg
= true;
3037 if (sctx
->gs_shader
.cso
&& sctx
->tes_shader
.cso
&&
3038 sctx
->gs_shader
.cso
->tess_turns_off_ngg
) {
3040 } else if (!sctx
->screen
->use_ngg_streamout
) {
3041 struct si_shader_selector
*last
= si_get_vs(sctx
)->cso
;
3043 if ((last
&& last
->so
.num_outputs
) ||
3044 sctx
->streamout
.prims_gen_query_enabled
)
3048 if (new_ngg
!= sctx
->ngg
) {
3049 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3050 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3053 if ((sctx
->family
== CHIP_NAVI10
||
3054 sctx
->family
== CHIP_NAVI12
||
3055 sctx
->family
== CHIP_NAVI14
) &&
3057 sctx
->flags
|= SI_CONTEXT_VGT_FLUSH
;
3059 sctx
->ngg
= new_ngg
;
3060 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
3066 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
3068 struct si_context
*sctx
= (struct si_context
*)ctx
;
3069 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
3070 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
3071 struct si_shader_selector
*sel
= state
;
3072 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
3075 if (sctx
->gs_shader
.cso
== sel
)
3078 sctx
->gs_shader
.cso
= sel
;
3079 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
3080 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
3082 si_update_common_shader_state(sctx
);
3083 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
3085 ngg_changed
= si_update_ngg(sctx
);
3086 if (ngg_changed
|| enable_changed
)
3087 si_shader_change_notify(sctx
);
3088 if (enable_changed
) {
3089 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
3090 si_update_tess_uses_prim_id(sctx
);
3092 si_update_vs_viewport_state(sctx
);
3093 si_set_active_descriptors_for_shader(sctx
, sel
);
3094 si_update_streamout_state(sctx
);
3095 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
3096 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3099 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
3101 struct si_context
*sctx
= (struct si_context
*)ctx
;
3102 struct si_shader_selector
*sel
= state
;
3103 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
3105 if (sctx
->tcs_shader
.cso
== sel
)
3108 sctx
->tcs_shader
.cso
= sel
;
3109 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
3110 si_update_tess_uses_prim_id(sctx
);
3112 si_update_common_shader_state(sctx
);
3115 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
3117 si_set_active_descriptors_for_shader(sctx
, sel
);
3120 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
3122 struct si_context
*sctx
= (struct si_context
*)ctx
;
3123 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
3124 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
3125 struct si_shader_selector
*sel
= state
;
3126 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
3128 if (sctx
->tes_shader
.cso
== sel
)
3131 sctx
->tes_shader
.cso
= sel
;
3132 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
3133 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
3134 si_update_tess_uses_prim_id(sctx
);
3136 si_update_common_shader_state(sctx
);
3137 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
3139 bool ngg_changed
= si_update_ngg(sctx
);
3140 if (ngg_changed
|| enable_changed
)
3141 si_shader_change_notify(sctx
);
3143 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
3144 si_update_vs_viewport_state(sctx
);
3145 si_set_active_descriptors_for_shader(sctx
, sel
);
3146 si_update_streamout_state(sctx
);
3147 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
3148 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3151 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
3153 struct si_context
*sctx
= (struct si_context
*)ctx
;
3154 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
3155 struct si_shader_selector
*sel
= state
;
3157 /* skip if supplied shader is one already in use */
3161 sctx
->ps_shader
.cso
= sel
;
3162 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
3164 si_update_common_shader_state(sctx
);
3166 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
3167 si_update_tess_uses_prim_id(sctx
);
3170 old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
3171 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3173 if (sctx
->screen
->has_out_of_order_rast
&&
3175 old_sel
->info
.writes_memory
!= sel
->info
.writes_memory
||
3176 old_sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] !=
3177 sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]))
3178 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3180 si_set_active_descriptors_for_shader(sctx
, sel
);
3181 si_update_ps_colorbuf0_slot(sctx
);
3184 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
3186 if (shader
->is_optimized
) {
3187 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
,
3191 util_queue_fence_destroy(&shader
->ready
);
3194 /* If destroyed shaders were not unbound, the next compiled
3195 * shader variant could get the same pointer address and so
3196 * binding it to the same shader stage would be considered
3197 * a no-op, causing random behavior.
3199 switch (shader
->selector
->type
) {
3200 case PIPE_SHADER_VERTEX
:
3201 if (shader
->key
.as_ls
) {
3202 assert(sctx
->chip_class
<= GFX8
);
3203 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
3204 } else if (shader
->key
.as_es
) {
3205 assert(sctx
->chip_class
<= GFX8
);
3206 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3207 } else if (shader
->key
.as_ngg
) {
3208 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3210 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3213 case PIPE_SHADER_TESS_CTRL
:
3214 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
3216 case PIPE_SHADER_TESS_EVAL
:
3217 if (shader
->key
.as_es
) {
3218 assert(sctx
->chip_class
<= GFX8
);
3219 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3220 } else if (shader
->key
.as_ngg
) {
3221 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3223 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3226 case PIPE_SHADER_GEOMETRY
:
3227 if (shader
->is_gs_copy_shader
)
3228 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3230 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3232 case PIPE_SHADER_FRAGMENT
:
3233 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
3239 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
3240 si_shader_destroy(shader
);
3244 void si_destroy_shader_selector(struct si_context
*sctx
,
3245 struct si_shader_selector
*sel
)
3247 struct si_shader
*p
= sel
->first_variant
, *c
;
3248 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
3249 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
3250 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
3251 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
3252 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
3253 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
3256 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
3258 if (current_shader
[sel
->type
]->cso
== sel
) {
3259 current_shader
[sel
->type
]->cso
= NULL
;
3260 current_shader
[sel
->type
]->current
= NULL
;
3264 c
= p
->next_variant
;
3265 si_delete_shader(sctx
, p
);
3269 if (sel
->main_shader_part
)
3270 si_delete_shader(sctx
, sel
->main_shader_part
);
3271 if (sel
->main_shader_part_ls
)
3272 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
3273 if (sel
->main_shader_part_es
)
3274 si_delete_shader(sctx
, sel
->main_shader_part_es
);
3275 if (sel
->main_shader_part_ngg
)
3276 si_delete_shader(sctx
, sel
->main_shader_part_ngg
);
3277 if (sel
->gs_copy_shader
)
3278 si_delete_shader(sctx
, sel
->gs_copy_shader
);
3280 util_queue_fence_destroy(&sel
->ready
);
3281 simple_mtx_destroy(&sel
->mutex
);
3283 ralloc_free(sel
->nir
);
3287 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
3289 struct si_context
*sctx
= (struct si_context
*)ctx
;
3290 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
3292 si_shader_selector_reference(sctx
, &sel
, NULL
);
3295 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
3296 struct si_shader
*vs
, unsigned name
,
3297 unsigned index
, unsigned interpolate
)
3299 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
3300 unsigned j
, offset
, ps_input_cntl
= 0;
3302 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
3303 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
) ||
3304 name
== TGSI_SEMANTIC_PRIMID
)
3305 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
3307 if (name
== TGSI_SEMANTIC_PCOORD
||
3308 (name
== TGSI_SEMANTIC_TEXCOORD
&&
3309 sctx
->sprite_coord_enable
& (1 << index
))) {
3310 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
3313 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
3314 if (name
== vsinfo
->output_semantic_name
[j
] &&
3315 index
== vsinfo
->output_semantic_index
[j
]) {
3316 offset
= vs
->info
.vs_output_param_offset
[j
];
3318 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
3319 /* The input is loaded from parameter memory. */
3320 ps_input_cntl
|= S_028644_OFFSET(offset
);
3321 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3322 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
3323 /* This can happen with depth-only rendering. */
3326 /* The input is a DEFAULT_VAL constant. */
3327 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
3328 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
3329 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
3332 ps_input_cntl
= S_028644_OFFSET(0x20) |
3333 S_028644_DEFAULT_VAL(offset
);
3339 if (j
== vsinfo
->num_outputs
&& name
== TGSI_SEMANTIC_PRIMID
)
3340 /* PrimID is written after the last output when HW VS is used. */
3341 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
3342 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3343 /* No corresponding output found, load defaults into input.
3344 * Don't set any other bits.
3345 * (FLAT_SHADE=1 completely changes behavior) */
3346 ps_input_cntl
= S_028644_OFFSET(0x20);
3347 /* D3D 9 behaviour. GL is undefined */
3348 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
3349 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
3351 return ps_input_cntl
;
3354 static void si_emit_spi_map(struct si_context
*sctx
)
3356 struct si_shader
*ps
= sctx
->ps_shader
.current
;
3357 struct si_shader
*vs
= si_get_vs_state(sctx
);
3358 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
3359 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
3360 unsigned spi_ps_input_cntl
[32];
3362 if (!ps
|| !ps
->selector
->info
.num_inputs
)
3365 num_interp
= si_get_ps_num_interp(ps
);
3366 assert(num_interp
> 0);
3368 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
3369 unsigned name
= psinfo
->input_semantic_name
[i
];
3370 unsigned index
= psinfo
->input_semantic_index
[i
];
3371 unsigned interpolate
= psinfo
->input_interpolate
[i
];
3373 spi_ps_input_cntl
[num_written
++] = si_get_ps_input_cntl(sctx
, vs
, name
,
3374 index
, interpolate
);
3376 if (name
== TGSI_SEMANTIC_COLOR
) {
3377 assert(index
< ARRAY_SIZE(bcol_interp
));
3378 bcol_interp
[index
] = interpolate
;
3382 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
3383 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
3385 for (i
= 0; i
< 2; i
++) {
3386 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
3389 spi_ps_input_cntl
[num_written
++] =
3390 si_get_ps_input_cntl(sctx
, vs
, bcol
, i
, bcol_interp
[i
]);
3394 assert(num_interp
== num_written
);
3396 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3397 /* Dota 2: Only ~16% of SPI map updates set different values. */
3398 /* Talos: Only ~9% of SPI map updates set different values. */
3399 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
3400 radeon_opt_set_context_regn(sctx
, R_028644_SPI_PS_INPUT_CNTL_0
,
3402 sctx
->tracked_regs
.spi_ps_input_cntl
, num_interp
);
3404 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
3405 sctx
->context_roll
= true;
3409 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3411 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
3413 if (sctx
->init_config_has_vgt_flush
)
3416 /* Done by Vulkan before VGT_FLUSH. */
3417 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
3418 si_pm4_cmd_add(sctx
->init_config
,
3419 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3420 si_pm4_cmd_end(sctx
->init_config
, false);
3422 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3423 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
3424 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3425 si_pm4_cmd_end(sctx
->init_config
, false);
3426 sctx
->init_config_has_vgt_flush
= true;
3429 /* Initialize state related to ESGS / GSVS ring buffers */
3430 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
3432 struct si_shader_selector
*es
=
3433 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
3434 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
3435 struct si_pm4_state
*pm4
;
3437 /* Chip constants. */
3438 unsigned num_se
= sctx
->screen
->info
.max_se
;
3439 unsigned wave_size
= 64;
3440 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
3441 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3442 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3444 unsigned gs_vertex_reuse
= (sctx
->chip_class
>= GFX8
? 32 : 16) * num_se
;
3445 unsigned alignment
= 256 * num_se
;
3446 /* The maximum size is 63.999 MB per SE. */
3447 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
3449 /* Calculate the minimum size. */
3450 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
3451 wave_size
, alignment
);
3453 /* These are recommended sizes, not minimum sizes. */
3454 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
3455 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
3456 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
3457 gs
->max_gsvs_emit_size
;
3459 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
3460 esgs_ring_size
= align(esgs_ring_size
, alignment
);
3461 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
3463 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
3464 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
3466 /* Some rings don't have to be allocated if shaders don't use them.
3467 * (e.g. no varyings between ES and GS or GS and VS)
3469 * GFX9 doesn't have the ESGS ring.
3471 bool update_esgs
= sctx
->chip_class
<= GFX8
&&
3473 (!sctx
->esgs_ring
||
3474 sctx
->esgs_ring
->width0
< esgs_ring_size
);
3475 bool update_gsvs
= gsvs_ring_size
&&
3476 (!sctx
->gsvs_ring
||
3477 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
3479 if (!update_esgs
&& !update_gsvs
)
3483 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
3485 pipe_aligned_buffer_create(sctx
->b
.screen
,
3486 SI_RESOURCE_FLAG_UNMAPPABLE
,
3489 sctx
->screen
->info
.pte_fragment_size
);
3490 if (!sctx
->esgs_ring
)
3495 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
3497 pipe_aligned_buffer_create(sctx
->b
.screen
,
3498 SI_RESOURCE_FLAG_UNMAPPABLE
,
3501 sctx
->screen
->info
.pte_fragment_size
);
3502 if (!sctx
->gsvs_ring
)
3506 /* Create the "init_config_gs_rings" state. */
3507 pm4
= CALLOC_STRUCT(si_pm4_state
);
3511 if (sctx
->chip_class
>= GFX7
) {
3512 if (sctx
->esgs_ring
) {
3513 assert(sctx
->chip_class
<= GFX8
);
3514 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
3515 sctx
->esgs_ring
->width0
/ 256);
3517 if (sctx
->gsvs_ring
)
3518 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
3519 sctx
->gsvs_ring
->width0
/ 256);
3521 if (sctx
->esgs_ring
)
3522 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
3523 sctx
->esgs_ring
->width0
/ 256);
3524 if (sctx
->gsvs_ring
)
3525 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
3526 sctx
->gsvs_ring
->width0
/ 256);
3529 /* Set the state. */
3530 if (sctx
->init_config_gs_rings
)
3531 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
3532 sctx
->init_config_gs_rings
= pm4
;
3534 if (!sctx
->init_config_has_vgt_flush
) {
3535 si_init_config_add_vgt_flush(sctx
);
3536 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3539 /* Flush the context to re-emit both init_config states. */
3540 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3541 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3543 /* Set ring bindings. */
3544 if (sctx
->esgs_ring
) {
3545 assert(sctx
->chip_class
<= GFX8
);
3546 si_set_ring_buffer(sctx
, SI_ES_RING_ESGS
,
3547 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3548 true, true, 4, 64, 0);
3549 si_set_ring_buffer(sctx
, SI_GS_RING_ESGS
,
3550 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3551 false, false, 0, 0, 0);
3553 if (sctx
->gsvs_ring
) {
3554 si_set_ring_buffer(sctx
, SI_RING_GSVS
,
3555 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
3556 false, false, 0, 0, 0);
3562 static void si_shader_lock(struct si_shader
*shader
)
3564 simple_mtx_lock(&shader
->selector
->mutex
);
3565 if (shader
->previous_stage_sel
) {
3566 assert(shader
->previous_stage_sel
!= shader
->selector
);
3567 simple_mtx_lock(&shader
->previous_stage_sel
->mutex
);
3571 static void si_shader_unlock(struct si_shader
*shader
)
3573 if (shader
->previous_stage_sel
)
3574 simple_mtx_unlock(&shader
->previous_stage_sel
->mutex
);
3575 simple_mtx_unlock(&shader
->selector
->mutex
);
3579 * @returns 1 if \p sel has been updated to use a new scratch buffer
3581 * < 0 if there was a failure
3583 static int si_update_scratch_buffer(struct si_context
*sctx
,
3584 struct si_shader
*shader
)
3586 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
3591 /* This shader doesn't need a scratch buffer */
3592 if (shader
->config
.scratch_bytes_per_wave
== 0)
3595 /* Prevent race conditions when updating:
3596 * - si_shader::scratch_bo
3597 * - si_shader::binary::code
3598 * - si_shader::previous_stage::binary::code.
3600 si_shader_lock(shader
);
3602 /* This shader is already configured to use the current
3603 * scratch buffer. */
3604 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
3605 si_shader_unlock(shader
);
3609 assert(sctx
->scratch_buffer
);
3611 /* Replace the shader bo with a new bo that has the relocs applied. */
3612 if (!si_shader_binary_upload(sctx
->screen
, shader
, scratch_va
)) {
3613 si_shader_unlock(shader
);
3617 /* Update the shader state to use the new shader bo. */
3618 si_shader_init_pm4_state(sctx
->screen
, shader
);
3620 si_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
3622 si_shader_unlock(shader
);
3626 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
3628 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
3631 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
3633 if (!sctx
->tes_shader
.cso
)
3634 return NULL
; /* tessellation disabled */
3636 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
:
3637 sctx
->fixed_func_tcs_shader
.current
;
3640 static bool si_update_scratch_relocs(struct si_context
*sctx
)
3642 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3645 /* Update the shaders, so that they are using the latest scratch.
3646 * The scratch buffer may have been changed since these shaders were
3647 * last used, so we still need to try to update them, even if they
3648 * require scratch buffers smaller than the current size.
3650 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
3654 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3656 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
3660 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3662 r
= si_update_scratch_buffer(sctx
, tcs
);
3666 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
3668 /* VS can be bound as LS, ES, or VS. */
3669 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
3673 if (sctx
->vs_shader
.current
->key
.as_ls
)
3674 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3675 else if (sctx
->vs_shader
.current
->key
.as_es
)
3676 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3677 else if (sctx
->vs_shader
.current
->key
.as_ngg
)
3678 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
3680 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3683 /* TES can be bound as ES or VS. */
3684 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
3688 if (sctx
->tes_shader
.current
->key
.as_es
)
3689 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3690 else if (sctx
->tes_shader
.current
->key
.as_ngg
)
3691 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
3693 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3699 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
3701 /* SPI_TMPRING_SIZE.WAVESIZE must be constant for each scratch buffer.
3702 * There are 2 cases to handle:
3704 * - If the current needed size is less than the maximum seen size,
3705 * use the maximum seen size, so that WAVESIZE remains the same.
3707 * - If the current needed size is greater than the maximum seen size,
3708 * the scratch buffer is reallocated, so we can increase WAVESIZE.
3710 * Shaders that set SCRATCH_EN=0 don't allocate scratch space.
3711 * Otherwise, the number of waves that can use scratch is
3712 * SPI_TMPRING_SIZE.WAVES.
3716 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
3717 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
3718 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
3720 if (sctx
->tes_shader
.cso
) {
3721 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
3722 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(si_get_tcs_current(sctx
)));
3725 sctx
->max_seen_scratch_bytes_per_wave
=
3726 MAX2(sctx
->max_seen_scratch_bytes_per_wave
, bytes
);
3728 unsigned scratch_needed_size
=
3729 sctx
->max_seen_scratch_bytes_per_wave
* sctx
->scratch_waves
;
3730 unsigned spi_tmpring_size
;
3732 if (scratch_needed_size
> 0) {
3733 if (!sctx
->scratch_buffer
||
3734 scratch_needed_size
> sctx
->scratch_buffer
->b
.b
.width0
) {
3735 /* Create a bigger scratch buffer */
3736 si_resource_reference(&sctx
->scratch_buffer
, NULL
);
3738 sctx
->scratch_buffer
=
3739 si_aligned_buffer_create(&sctx
->screen
->b
,
3740 SI_RESOURCE_FLAG_UNMAPPABLE
,
3742 scratch_needed_size
,
3743 sctx
->screen
->info
.pte_fragment_size
);
3744 if (!sctx
->scratch_buffer
)
3747 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3748 si_context_add_resource_size(sctx
,
3749 &sctx
->scratch_buffer
->b
.b
);
3752 if (!si_update_scratch_relocs(sctx
))
3756 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3757 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
3758 "scratch size should already be aligned correctly.");
3760 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
3761 S_0286E8_WAVESIZE(sctx
->max_seen_scratch_bytes_per_wave
>> 10);
3762 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
3763 sctx
->spi_tmpring_size
= spi_tmpring_size
;
3764 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3769 static void si_init_tess_factor_ring(struct si_context
*sctx
)
3771 assert(!sctx
->tess_rings
);
3772 assert(((sctx
->screen
->tess_factor_ring_size
/ 4) & C_030938_SIZE
) == 0);
3774 /* The address must be aligned to 2^19, because the shader only
3775 * receives the high 13 bits.
3777 sctx
->tess_rings
= pipe_aligned_buffer_create(sctx
->b
.screen
,
3778 SI_RESOURCE_FLAG_32BIT
,
3780 sctx
->screen
->tess_offchip_ring_size
+
3781 sctx
->screen
->tess_factor_ring_size
,
3783 if (!sctx
->tess_rings
)
3786 si_init_config_add_vgt_flush(sctx
);
3788 si_pm4_add_bo(sctx
->init_config
, si_resource(sctx
->tess_rings
),
3789 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3791 uint64_t factor_va
= si_resource(sctx
->tess_rings
)->gpu_address
+
3792 sctx
->screen
->tess_offchip_ring_size
;
3794 /* Append these registers to the init config state. */
3795 if (sctx
->chip_class
>= GFX7
) {
3796 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
3797 S_030938_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3798 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
3800 if (sctx
->chip_class
>= GFX10
)
3801 si_pm4_set_reg(sctx
->init_config
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3802 S_030984_BASE_HI(factor_va
>> 40));
3803 else if (sctx
->chip_class
== GFX9
)
3804 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3805 S_030944_BASE_HI(factor_va
>> 40));
3806 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3807 sctx
->screen
->vgt_hs_offchip_param
);
3809 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
3810 S_008988_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3811 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
3813 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3814 sctx
->screen
->vgt_hs_offchip_param
);
3817 /* Flush the context to re-emit the init_config state.
3818 * This is done only once in a lifetime of a context.
3820 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3821 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3822 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3825 static struct si_pm4_state
*si_build_vgt_shader_config(struct si_screen
*screen
,
3826 union si_vgt_stages_key key
)
3828 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
3829 uint32_t stages
= 0;
3832 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3833 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3836 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3839 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
3841 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3842 } else if (key
.u
.gs
) {
3843 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3845 } else if (key
.u
.ngg
) {
3846 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
3850 stages
|= S_028B54_PRIMGEN_EN(1);
3851 if (key
.u
.streamout
)
3852 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
3853 } else if (key
.u
.gs
)
3854 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3856 if (screen
->info
.chip_class
>= GFX9
)
3857 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3859 if (screen
->info
.chip_class
>= GFX10
&& screen
->ge_wave_size
== 32) {
3860 stages
|= S_028B54_HS_W32_EN(1) |
3861 S_028B54_GS_W32_EN(key
.u
.ngg
) | /* legacy GS only supports Wave64 */
3862 S_028B54_VS_W32_EN(1);
3865 si_pm4_set_reg(pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3869 static void si_update_vgt_shader_config(struct si_context
*sctx
,
3870 union si_vgt_stages_key key
)
3872 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[key
.index
];
3874 if (unlikely(!*pm4
))
3875 *pm4
= si_build_vgt_shader_config(sctx
->screen
, key
);
3876 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3879 bool si_update_shaders(struct si_context
*sctx
)
3881 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3882 struct si_compiler_ctx_state compiler_state
;
3883 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3884 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3885 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
3886 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
3887 union si_vgt_stages_key key
;
3888 unsigned old_spi_shader_col_format
=
3889 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
3892 compiler_state
.compiler
= &sctx
->compiler
;
3893 compiler_state
.debug
= sctx
->debug
;
3894 compiler_state
.is_debug_context
= sctx
->is_debug
;
3898 if (sctx
->tes_shader
.cso
)
3900 if (sctx
->gs_shader
.cso
)
3905 key
.u
.streamout
= !!si_get_vs(sctx
)->cso
->so
.num_outputs
;
3908 /* Update TCS and TES. */
3909 if (sctx
->tes_shader
.cso
) {
3910 if (!sctx
->tess_rings
) {
3911 si_init_tess_factor_ring(sctx
);
3912 if (!sctx
->tess_rings
)
3916 if (sctx
->tcs_shader
.cso
) {
3917 r
= si_shader_select(ctx
, &sctx
->tcs_shader
, key
,
3921 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3923 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3924 sctx
->fixed_func_tcs_shader
.cso
=
3925 si_create_fixed_func_tcs(sctx
);
3926 if (!sctx
->fixed_func_tcs_shader
.cso
)
3930 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
3931 key
, &compiler_state
);
3934 si_pm4_bind_state(sctx
, hs
,
3935 sctx
->fixed_func_tcs_shader
.current
->pm4
);
3938 if (!sctx
->gs_shader
.cso
|| sctx
->chip_class
<= GFX8
) {
3939 r
= si_shader_select(ctx
, &sctx
->tes_shader
, key
, &compiler_state
);
3943 if (sctx
->gs_shader
.cso
) {
3945 assert(sctx
->chip_class
<= GFX8
);
3946 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3947 } else if (key
.u
.ngg
) {
3948 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
3950 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3954 if (sctx
->chip_class
<= GFX8
)
3955 si_pm4_bind_state(sctx
, ls
, NULL
);
3956 si_pm4_bind_state(sctx
, hs
, NULL
);
3960 if (sctx
->gs_shader
.cso
) {
3961 r
= si_shader_select(ctx
, &sctx
->gs_shader
, key
, &compiler_state
);
3964 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3966 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3968 if (!si_update_gs_ring_buffers(sctx
))
3971 si_pm4_bind_state(sctx
, vs
, NULL
);
3975 si_pm4_bind_state(sctx
, gs
, NULL
);
3976 if (sctx
->chip_class
<= GFX8
)
3977 si_pm4_bind_state(sctx
, es
, NULL
);
3982 if ((!key
.u
.tess
&& !key
.u
.gs
) || sctx
->chip_class
<= GFX8
) {
3983 r
= si_shader_select(ctx
, &sctx
->vs_shader
, key
, &compiler_state
);
3987 if (!key
.u
.tess
&& !key
.u
.gs
) {
3989 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
3990 si_pm4_bind_state(sctx
, vs
, NULL
);
3992 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3994 } else if (sctx
->tes_shader
.cso
) {
3995 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3997 assert(sctx
->gs_shader
.cso
);
3998 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
4002 si_update_vgt_shader_config(sctx
, key
);
4004 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
4005 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
4007 if (sctx
->ps_shader
.cso
) {
4008 unsigned db_shader_control
;
4010 r
= si_shader_select(ctx
, &sctx
->ps_shader
, key
, &compiler_state
);
4013 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
4016 sctx
->ps_shader
.cso
->db_shader_control
|
4017 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
4019 if (si_pm4_state_changed(sctx
, ps
) ||
4020 si_pm4_state_changed(sctx
, vs
) ||
4021 (key
.u
.ngg
&& si_pm4_state_changed(sctx
, gs
)) ||
4022 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
4023 sctx
->flatshade
!= rs
->flatshade
) {
4024 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
4025 sctx
->flatshade
= rs
->flatshade
;
4026 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.spi_map
);
4029 if (sctx
->screen
->info
.rbplus_allowed
&&
4030 si_pm4_state_changed(sctx
, ps
) &&
4032 old_spi_shader_col_format
!=
4033 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
4034 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
4036 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
4037 sctx
->ps_db_shader_control
= db_shader_control
;
4038 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
4039 if (sctx
->screen
->dpbb_allowed
)
4040 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
4043 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
4044 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
4045 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
4047 if (sctx
->chip_class
== GFX6
)
4048 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
4050 if (sctx
->framebuffer
.nr_samples
<= 1)
4051 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
4055 if (si_pm4_state_enabled_and_changed(sctx
, ls
) ||
4056 si_pm4_state_enabled_and_changed(sctx
, hs
) ||
4057 si_pm4_state_enabled_and_changed(sctx
, es
) ||
4058 si_pm4_state_enabled_and_changed(sctx
, gs
) ||
4059 si_pm4_state_enabled_and_changed(sctx
, vs
) ||
4060 si_pm4_state_enabled_and_changed(sctx
, ps
)) {
4061 if (!si_update_spi_tmpring_size(sctx
))
4065 if (sctx
->chip_class
>= GFX7
) {
4066 if (si_pm4_state_enabled_and_changed(sctx
, ls
))
4067 sctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
4068 else if (!sctx
->queued
.named
.ls
)
4069 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_LS
;
4071 if (si_pm4_state_enabled_and_changed(sctx
, hs
))
4072 sctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
4073 else if (!sctx
->queued
.named
.hs
)
4074 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_HS
;
4076 if (si_pm4_state_enabled_and_changed(sctx
, es
))
4077 sctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
4078 else if (!sctx
->queued
.named
.es
)
4079 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_ES
;
4081 if (si_pm4_state_enabled_and_changed(sctx
, gs
))
4082 sctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
4083 else if (!sctx
->queued
.named
.gs
)
4084 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_GS
;
4086 if (si_pm4_state_enabled_and_changed(sctx
, vs
))
4087 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
4088 else if (!sctx
->queued
.named
.vs
)
4089 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VS
;
4091 if (si_pm4_state_enabled_and_changed(sctx
, ps
))
4092 sctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
4093 else if (!sctx
->queued
.named
.ps
)
4094 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_PS
;
4097 sctx
->do_update_shaders
= false;
4101 static void si_emit_scratch_state(struct si_context
*sctx
)
4103 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4105 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
4106 sctx
->spi_tmpring_size
);
4108 if (sctx
->scratch_buffer
) {
4109 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
4110 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
4111 RADEON_PRIO_SCRATCH_BUFFER
);
4115 void si_init_shader_functions(struct si_context
*sctx
)
4117 sctx
->atoms
.s
.spi_map
.emit
= si_emit_spi_map
;
4118 sctx
->atoms
.s
.scratch_state
.emit
= si_emit_scratch_state
;
4120 sctx
->b
.create_vs_state
= si_create_shader_selector
;
4121 sctx
->b
.create_tcs_state
= si_create_shader_selector
;
4122 sctx
->b
.create_tes_state
= si_create_shader_selector
;
4123 sctx
->b
.create_gs_state
= si_create_shader_selector
;
4124 sctx
->b
.create_fs_state
= si_create_shader_selector
;
4126 sctx
->b
.bind_vs_state
= si_bind_vs_shader
;
4127 sctx
->b
.bind_tcs_state
= si_bind_tcs_shader
;
4128 sctx
->b
.bind_tes_state
= si_bind_tes_shader
;
4129 sctx
->b
.bind_gs_state
= si_bind_gs_shader
;
4130 sctx
->b
.bind_fs_state
= si_bind_ps_shader
;
4132 sctx
->b
.delete_vs_state
= si_delete_shader_selector
;
4133 sctx
->b
.delete_tcs_state
= si_delete_shader_selector
;
4134 sctx
->b
.delete_tes_state
= si_delete_shader_selector
;
4135 sctx
->b
.delete_gs_state
= si_delete_shader_selector
;
4136 sctx
->b
.delete_fs_state
= si_delete_shader_selector
;