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radeonsi: add VS blit shader creation
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "sid.h"
30 #include "gfx9d.h"
31 #include "radeon/r600_cs.h"
32
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/hash_table.h"
36 #include "util/crc32.h"
37 #include "util/u_memory.h"
38 #include "util/u_prim.h"
39
40 #include "util/disk_cache.h"
41 #include "util/mesa-sha1.h"
42 #include "ac_exp_param.h"
43
44 /* SHADER_CACHE */
45
46 /**
47 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
48 * integer.
49 */
50 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
51 {
52 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
53 sizeof(struct tgsi_token);
54 unsigned size = 4 + tgsi_size + sizeof(sel->so);
55 char *result = (char*)MALLOC(size);
56
57 if (!result)
58 return NULL;
59
60 *((uint32_t*)result) = size;
61 memcpy(result + 4, sel->tokens, tgsi_size);
62 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
63 return result;
64 }
65
66 /** Copy "data" to "ptr" and return the next dword following copied data. */
67 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
68 {
69 /* data may be NULL if size == 0 */
70 if (size)
71 memcpy(ptr, data, size);
72 ptr += DIV_ROUND_UP(size, 4);
73 return ptr;
74 }
75
76 /** Read data from "ptr". Return the next dword following the data. */
77 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
78 {
79 memcpy(data, ptr, size);
80 ptr += DIV_ROUND_UP(size, 4);
81 return ptr;
82 }
83
84 /**
85 * Write the size as uint followed by the data. Return the next dword
86 * following the copied data.
87 */
88 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
89 {
90 *ptr++ = size;
91 return write_data(ptr, data, size);
92 }
93
94 /**
95 * Read the size as uint followed by the data. Return both via parameters.
96 * Return the next dword following the data.
97 */
98 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
99 {
100 *size = *ptr++;
101 assert(*data == NULL);
102 if (!*size)
103 return ptr;
104 *data = malloc(*size);
105 return read_data(ptr, *data, *size);
106 }
107
108 /**
109 * Return the shader binary in a buffer. The first 4 bytes contain its size
110 * as integer.
111 */
112 static void *si_get_shader_binary(struct si_shader *shader)
113 {
114 /* There is always a size of data followed by the data itself. */
115 unsigned relocs_size = shader->binary.reloc_count *
116 sizeof(shader->binary.relocs[0]);
117 unsigned disasm_size = shader->binary.disasm_string ?
118 strlen(shader->binary.disasm_string) + 1 : 0;
119 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
120 strlen(shader->binary.llvm_ir_string) + 1 : 0;
121 unsigned size =
122 4 + /* total size */
123 4 + /* CRC32 of the data below */
124 align(sizeof(shader->config), 4) +
125 align(sizeof(shader->info), 4) +
126 4 + align(shader->binary.code_size, 4) +
127 4 + align(shader->binary.rodata_size, 4) +
128 4 + align(relocs_size, 4) +
129 4 + align(disasm_size, 4) +
130 4 + align(llvm_ir_size, 4);
131 void *buffer = CALLOC(1, size);
132 uint32_t *ptr = (uint32_t*)buffer;
133
134 if (!buffer)
135 return NULL;
136
137 *ptr++ = size;
138 ptr++; /* CRC32 is calculated at the end. */
139
140 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
141 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
142 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
143 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
144 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
145 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
146 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
147 assert((char *)ptr - (char *)buffer == size);
148
149 /* Compute CRC32. */
150 ptr = (uint32_t*)buffer;
151 ptr++;
152 *ptr = util_hash_crc32(ptr + 1, size - 8);
153
154 return buffer;
155 }
156
157 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
158 {
159 uint32_t *ptr = (uint32_t*)binary;
160 uint32_t size = *ptr++;
161 uint32_t crc32 = *ptr++;
162 unsigned chunk_size;
163
164 if (util_hash_crc32(ptr, size - 8) != crc32) {
165 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
166 return false;
167 }
168
169 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
170 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
171 ptr = read_chunk(ptr, (void**)&shader->binary.code,
172 &shader->binary.code_size);
173 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
174 &shader->binary.rodata_size);
175 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
176 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
177 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
178 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
179
180 return true;
181 }
182
183 /**
184 * Insert a shader into the cache. It's assumed the shader is not in the cache.
185 * Use si_shader_cache_load_shader before calling this.
186 *
187 * Returns false on failure, in which case the tgsi_binary should be freed.
188 */
189 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
190 void *tgsi_binary,
191 struct si_shader *shader,
192 bool insert_into_disk_cache)
193 {
194 void *hw_binary;
195 struct hash_entry *entry;
196 uint8_t key[CACHE_KEY_SIZE];
197
198 entry = _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
199 if (entry)
200 return false; /* already added */
201
202 hw_binary = si_get_shader_binary(shader);
203 if (!hw_binary)
204 return false;
205
206 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
207 hw_binary) == NULL) {
208 FREE(hw_binary);
209 return false;
210 }
211
212 if (sscreen->b.disk_shader_cache && insert_into_disk_cache) {
213 disk_cache_compute_key(sscreen->b.disk_shader_cache, tgsi_binary,
214 *((uint32_t *)tgsi_binary), key);
215 disk_cache_put(sscreen->b.disk_shader_cache, key, hw_binary,
216 *((uint32_t *) hw_binary), NULL);
217 }
218
219 return true;
220 }
221
222 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
223 void *tgsi_binary,
224 struct si_shader *shader)
225 {
226 struct hash_entry *entry =
227 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
228 if (!entry) {
229 if (sscreen->b.disk_shader_cache) {
230 unsigned char sha1[CACHE_KEY_SIZE];
231 size_t tg_size = *((uint32_t *) tgsi_binary);
232
233 disk_cache_compute_key(sscreen->b.disk_shader_cache,
234 tgsi_binary, tg_size, sha1);
235
236 size_t binary_size;
237 uint8_t *buffer =
238 disk_cache_get(sscreen->b.disk_shader_cache,
239 sha1, &binary_size);
240 if (!buffer)
241 return false;
242
243 if (binary_size < sizeof(uint32_t) ||
244 *((uint32_t*)buffer) != binary_size) {
245 /* Something has gone wrong discard the item
246 * from the cache and rebuild/link from
247 * source.
248 */
249 assert(!"Invalid radeonsi shader disk cache "
250 "item!");
251
252 disk_cache_remove(sscreen->b.disk_shader_cache,
253 sha1);
254 free(buffer);
255
256 return false;
257 }
258
259 if (!si_load_shader_binary(shader, buffer)) {
260 free(buffer);
261 return false;
262 }
263 free(buffer);
264
265 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary,
266 shader, false))
267 FREE(tgsi_binary);
268 } else {
269 return false;
270 }
271 } else {
272 if (si_load_shader_binary(shader, entry->data))
273 FREE(tgsi_binary);
274 else
275 return false;
276 }
277 p_atomic_inc(&sscreen->b.num_shader_cache_hits);
278 return true;
279 }
280
281 static uint32_t si_shader_cache_key_hash(const void *key)
282 {
283 /* The first dword is the key size. */
284 return util_hash_crc32(key, *(uint32_t*)key);
285 }
286
287 static bool si_shader_cache_key_equals(const void *a, const void *b)
288 {
289 uint32_t *keya = (uint32_t*)a;
290 uint32_t *keyb = (uint32_t*)b;
291
292 /* The first dword is the key size. */
293 if (*keya != *keyb)
294 return false;
295
296 return memcmp(keya, keyb, *keya) == 0;
297 }
298
299 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
300 {
301 FREE((void*)entry->key);
302 FREE(entry->data);
303 }
304
305 bool si_init_shader_cache(struct si_screen *sscreen)
306 {
307 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
308 sscreen->shader_cache =
309 _mesa_hash_table_create(NULL,
310 si_shader_cache_key_hash,
311 si_shader_cache_key_equals);
312
313 return sscreen->shader_cache != NULL;
314 }
315
316 void si_destroy_shader_cache(struct si_screen *sscreen)
317 {
318 if (sscreen->shader_cache)
319 _mesa_hash_table_destroy(sscreen->shader_cache,
320 si_destroy_shader_cache_entry);
321 mtx_destroy(&sscreen->shader_cache_mutex);
322 }
323
324 /* SHADER STATES */
325
326 static void si_set_tesseval_regs(struct si_screen *sscreen,
327 struct si_shader_selector *tes,
328 struct si_pm4_state *pm4)
329 {
330 struct tgsi_shader_info *info = &tes->info;
331 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
332 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
333 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
334 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
335 unsigned type, partitioning, topology, distribution_mode;
336
337 switch (tes_prim_mode) {
338 case PIPE_PRIM_LINES:
339 type = V_028B6C_TESS_ISOLINE;
340 break;
341 case PIPE_PRIM_TRIANGLES:
342 type = V_028B6C_TESS_TRIANGLE;
343 break;
344 case PIPE_PRIM_QUADS:
345 type = V_028B6C_TESS_QUAD;
346 break;
347 default:
348 assert(0);
349 return;
350 }
351
352 switch (tes_spacing) {
353 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
354 partitioning = V_028B6C_PART_FRAC_ODD;
355 break;
356 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
357 partitioning = V_028B6C_PART_FRAC_EVEN;
358 break;
359 case PIPE_TESS_SPACING_EQUAL:
360 partitioning = V_028B6C_PART_INTEGER;
361 break;
362 default:
363 assert(0);
364 return;
365 }
366
367 if (tes_point_mode)
368 topology = V_028B6C_OUTPUT_POINT;
369 else if (tes_prim_mode == PIPE_PRIM_LINES)
370 topology = V_028B6C_OUTPUT_LINE;
371 else if (tes_vertex_order_cw)
372 /* for some reason, this must be the other way around */
373 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
374 else
375 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
376
377 if (sscreen->has_distributed_tess) {
378 if (sscreen->b.family == CHIP_FIJI ||
379 sscreen->b.family >= CHIP_POLARIS10)
380 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
381 else
382 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
383 } else
384 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
385
386 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
387 S_028B6C_TYPE(type) |
388 S_028B6C_PARTITIONING(partitioning) |
389 S_028B6C_TOPOLOGY(topology) |
390 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
391 }
392
393 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
394 * whether the "fractional odd" tessellation spacing is used.
395 *
396 * Possible VGT configurations and which state should set the register:
397 *
398 * Reg set in | VGT shader configuration | Value
399 * ------------------------------------------------------
400 * VS as VS | VS | 30
401 * VS as ES | ES -> GS -> VS | 30
402 * TES as VS | LS -> HS -> VS | 14 or 30
403 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
404 *
405 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
406 */
407 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
408 struct si_shader_selector *sel,
409 struct si_shader *shader,
410 struct si_pm4_state *pm4)
411 {
412 unsigned type = sel->type;
413
414 if (sscreen->b.family < CHIP_POLARIS10)
415 return;
416
417 /* VS as VS, or VS as ES: */
418 if ((type == PIPE_SHADER_VERTEX &&
419 (!shader ||
420 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
421 /* TES as VS, or TES as ES: */
422 type == PIPE_SHADER_TESS_EVAL) {
423 unsigned vtx_reuse_depth = 30;
424
425 if (type == PIPE_SHADER_TESS_EVAL &&
426 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
427 PIPE_TESS_SPACING_FRACTIONAL_ODD)
428 vtx_reuse_depth = 14;
429
430 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
431 vtx_reuse_depth);
432 }
433 }
434
435 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
436 {
437 if (shader->pm4)
438 si_pm4_clear_state(shader->pm4);
439 else
440 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
441
442 return shader->pm4;
443 }
444
445 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
446 {
447 struct si_pm4_state *pm4;
448 unsigned vgpr_comp_cnt;
449 uint64_t va;
450
451 assert(sscreen->b.chip_class <= VI);
452
453 pm4 = si_get_shader_pm4_state(shader);
454 if (!pm4)
455 return;
456
457 va = shader->bo->gpu_address;
458 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
459
460 /* We need at least 2 components for LS.
461 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
462 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
463 */
464 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
465
466 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
467 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
468
469 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
470 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
471 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
472 S_00B528_DX10_CLAMP(1) |
473 S_00B528_FLOAT_MODE(shader->config.float_mode);
474 shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR) |
475 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
476 }
477
478 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
479 {
480 struct si_pm4_state *pm4;
481 uint64_t va;
482 unsigned ls_vgpr_comp_cnt = 0;
483
484 pm4 = si_get_shader_pm4_state(shader);
485 if (!pm4)
486 return;
487
488 va = shader->bo->gpu_address;
489 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
490
491 if (sscreen->b.chip_class >= GFX9) {
492 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
493 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, va >> 40);
494
495 /* We need at least 2 components for LS.
496 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
497 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
498 */
499 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
500
501 shader->config.rsrc2 =
502 S_00B42C_USER_SGPR(GFX9_TCS_NUM_USER_SGPR) |
503 S_00B42C_USER_SGPR_MSB(GFX9_TCS_NUM_USER_SGPR >> 5) |
504 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
505 } else {
506 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
507 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
508
509 shader->config.rsrc2 =
510 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
511 S_00B42C_OC_LDS_EN(1) |
512 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
513 }
514
515 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
516 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
517 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
518 S_00B428_DX10_CLAMP(1) |
519 S_00B428_FLOAT_MODE(shader->config.float_mode) |
520 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
521
522 if (sscreen->b.chip_class <= VI) {
523 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
524 shader->config.rsrc2);
525 }
526 }
527
528 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
529 {
530 struct si_pm4_state *pm4;
531 unsigned num_user_sgprs;
532 unsigned vgpr_comp_cnt;
533 uint64_t va;
534 unsigned oc_lds_en;
535
536 assert(sscreen->b.chip_class <= VI);
537
538 pm4 = si_get_shader_pm4_state(shader);
539 if (!pm4)
540 return;
541
542 va = shader->bo->gpu_address;
543 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
544
545 if (shader->selector->type == PIPE_SHADER_VERTEX) {
546 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
547 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
548 num_user_sgprs = SI_VS_NUM_USER_SGPR;
549 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
550 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
551 num_user_sgprs = SI_TES_NUM_USER_SGPR;
552 } else
553 unreachable("invalid shader selector type");
554
555 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
556
557 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
558 shader->selector->esgs_itemsize / 4);
559 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
560 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
561 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
562 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
563 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
564 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
565 S_00B328_DX10_CLAMP(1) |
566 S_00B328_FLOAT_MODE(shader->config.float_mode));
567 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
568 S_00B32C_USER_SGPR(num_user_sgprs) |
569 S_00B32C_OC_LDS_EN(oc_lds_en) |
570 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
571
572 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
573 si_set_tesseval_regs(sscreen, shader->selector, pm4);
574
575 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
576 }
577
578 /**
579 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
580 * geometry shader.
581 */
582 static uint32_t si_vgt_gs_mode(struct si_shader_selector *sel)
583 {
584 enum chip_class chip_class = sel->screen->b.chip_class;
585 unsigned gs_max_vert_out = sel->gs_max_out_vertices;
586 unsigned cut_mode;
587
588 if (gs_max_vert_out <= 128) {
589 cut_mode = V_028A40_GS_CUT_128;
590 } else if (gs_max_vert_out <= 256) {
591 cut_mode = V_028A40_GS_CUT_256;
592 } else if (gs_max_vert_out <= 512) {
593 cut_mode = V_028A40_GS_CUT_512;
594 } else {
595 assert(gs_max_vert_out <= 1024);
596 cut_mode = V_028A40_GS_CUT_1024;
597 }
598
599 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
600 S_028A40_CUT_MODE(cut_mode)|
601 S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) |
602 S_028A40_GS_WRITE_OPTIMIZE(1) |
603 S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
604 }
605
606 struct gfx9_gs_info {
607 unsigned es_verts_per_subgroup;
608 unsigned gs_prims_per_subgroup;
609 unsigned gs_inst_prims_in_subgroup;
610 unsigned max_prims_per_subgroup;
611 unsigned lds_size;
612 };
613
614 static void gfx9_get_gs_info(struct si_shader_selector *es,
615 struct si_shader_selector *gs,
616 struct gfx9_gs_info *out)
617 {
618 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
619 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
620 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
621 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
622
623 /* All these are in dwords: */
624 /* We can't allow using the whole LDS, because GS waves compete with
625 * other shader stages for LDS space. */
626 const unsigned max_lds_size = 8 * 1024;
627 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
628 unsigned esgs_lds_size;
629
630 /* All these are per subgroup: */
631 const unsigned max_out_prims = 32 * 1024;
632 const unsigned max_es_verts = 255;
633 const unsigned ideal_gs_prims = 64;
634 unsigned max_gs_prims, gs_prims;
635 unsigned min_es_verts, es_verts, worst_case_es_verts;
636
637 assert(gs_num_invocations <= 32); /* GL maximum */
638
639 if (uses_adjacency || gs_num_invocations > 1)
640 max_gs_prims = 127 / gs_num_invocations;
641 else
642 max_gs_prims = 255;
643
644 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
645 * Make sure we don't go over the maximum value.
646 */
647 if (gs->gs_max_out_vertices > 0) {
648 max_gs_prims = MIN2(max_gs_prims,
649 max_out_prims /
650 (gs->gs_max_out_vertices * gs_num_invocations));
651 }
652 assert(max_gs_prims > 0);
653
654 /* If the primitive has adjacency, halve the number of vertices
655 * that will be reused in multiple primitives.
656 */
657 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
658
659 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
660 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
661
662 /* Compute ESGS LDS size based on the worst case number of ES vertices
663 * needed to create the target number of GS prims per subgroup.
664 */
665 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
666
667 /* If total LDS usage is too big, refactor partitions based on ratio
668 * of ESGS item sizes.
669 */
670 if (esgs_lds_size > max_lds_size) {
671 /* Our target GS Prims Per Subgroup was too large. Calculate
672 * the maximum number of GS Prims Per Subgroup that will fit
673 * into LDS, capped by the maximum that the hardware can support.
674 */
675 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
676 max_gs_prims);
677 assert(gs_prims > 0);
678 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
679 max_es_verts);
680
681 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
682 assert(esgs_lds_size <= max_lds_size);
683 }
684
685 /* Now calculate remaining ESGS information. */
686 if (esgs_lds_size)
687 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
688 else
689 es_verts = max_es_verts;
690
691 /* Vertices for adjacency primitives are not always reused, so restore
692 * it for ES_VERTS_PER_SUBGRP.
693 */
694 min_es_verts = gs->gs_input_verts_per_prim;
695
696 /* For normal primitives, the VGT only checks if they are past the ES
697 * verts per subgroup after allocating a full GS primitive and if they
698 * are, kick off a new subgroup. But if those additional ES verts are
699 * unique (e.g. not reused) we need to make sure there is enough LDS
700 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
701 */
702 es_verts -= min_es_verts - 1;
703
704 out->es_verts_per_subgroup = es_verts;
705 out->gs_prims_per_subgroup = gs_prims;
706 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
707 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
708 gs->gs_max_out_vertices;
709 out->lds_size = align(esgs_lds_size, 128) / 128;
710
711 assert(out->max_prims_per_subgroup <= max_out_prims);
712 }
713
714 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
715 {
716 struct si_shader_selector *sel = shader->selector;
717 const ubyte *num_components = sel->info.num_stream_output_components;
718 unsigned gs_num_invocations = sel->gs_num_invocations;
719 struct si_pm4_state *pm4;
720 uint64_t va;
721 unsigned max_stream = sel->max_gs_stream;
722 unsigned offset;
723
724 pm4 = si_get_shader_pm4_state(shader);
725 if (!pm4)
726 return;
727
728 offset = num_components[0] * sel->gs_max_out_vertices;
729 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
730 if (max_stream >= 1)
731 offset += num_components[1] * sel->gs_max_out_vertices;
732 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
733 if (max_stream >= 2)
734 offset += num_components[2] * sel->gs_max_out_vertices;
735 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
736 if (max_stream >= 3)
737 offset += num_components[3] * sel->gs_max_out_vertices;
738 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
739
740 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
741 assert(offset < (1 << 15));
742
743 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, sel->gs_max_out_vertices);
744
745 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
746 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
747 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
748 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
749
750 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
751 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
752 S_028B90_ENABLE(gs_num_invocations > 0));
753
754 va = shader->bo->gpu_address;
755 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
756
757 if (sscreen->b.chip_class >= GFX9) {
758 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
759 unsigned es_type = shader->key.part.gs.es->type;
760 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
761 struct gfx9_gs_info gs_info;
762
763 if (es_type == PIPE_SHADER_VERTEX)
764 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
765 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
766 else if (es_type == PIPE_SHADER_TESS_EVAL)
767 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
768 else
769 unreachable("invalid shader selector type");
770
771 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
772 * VGPR[0:4] are always loaded.
773 */
774 if (sel->info.uses_invocationid)
775 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
776 else if (sel->info.uses_primid)
777 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
778 else if (input_prim >= PIPE_PRIM_TRIANGLES)
779 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
780 else
781 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
782
783 gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
784
785 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
786 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, va >> 40);
787
788 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
789 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
790 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
791 S_00B228_DX10_CLAMP(1) |
792 S_00B228_FLOAT_MODE(shader->config.float_mode) |
793 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
794 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
795 S_00B22C_USER_SGPR(GFX9_GS_NUM_USER_SGPR) |
796 S_00B22C_USER_SGPR_MSB(GFX9_GS_NUM_USER_SGPR >> 5) |
797 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
798 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
799 S_00B22C_LDS_SIZE(gs_info.lds_size) |
800 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
801
802 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
803 S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) |
804 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) |
805 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup));
806 si_pm4_set_reg(pm4, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
807 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup));
808 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
809 shader->key.part.gs.es->esgs_itemsize / 4);
810
811 if (es_type == PIPE_SHADER_TESS_EVAL)
812 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
813
814 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
815 NULL, pm4);
816 } else {
817 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
818 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
819
820 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
821 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
822 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
823 S_00B228_DX10_CLAMP(1) |
824 S_00B228_FLOAT_MODE(shader->config.float_mode));
825 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
826 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
827 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
828 }
829 }
830
831 /**
832 * Compute the state for \p shader, which will run as a vertex shader on the
833 * hardware.
834 *
835 * If \p gs is non-NULL, it points to the geometry shader for which this shader
836 * is the copy shader.
837 */
838 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
839 struct si_shader_selector *gs)
840 {
841 const struct tgsi_shader_info *info = &shader->selector->info;
842 struct si_pm4_state *pm4;
843 unsigned num_user_sgprs;
844 unsigned nparams, vgpr_comp_cnt;
845 uint64_t va;
846 unsigned oc_lds_en;
847 unsigned window_space =
848 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
849 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
850
851 pm4 = si_get_shader_pm4_state(shader);
852 if (!pm4)
853 return;
854
855 /* We always write VGT_GS_MODE in the VS state, because every switch
856 * between different shader pipelines involving a different GS or no
857 * GS at all involves a switch of the VS (different GS use different
858 * copy shaders). On the other hand, when the API switches from a GS to
859 * no GS and then back to the same GS used originally, the GS state is
860 * not sent again.
861 */
862 if (!gs) {
863 unsigned mode = V_028A40_GS_OFF;
864
865 /* PrimID needs GS scenario A. */
866 if (enable_prim_id)
867 mode = V_028A40_GS_SCENARIO_A;
868
869 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, S_028A40_MODE(mode));
870 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
871 } else {
872 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
873 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
874 }
875
876 if (sscreen->b.chip_class <= VI) {
877 /* Reuse needs to be set off if we write oViewport. */
878 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF,
879 S_028AB4_REUSE_OFF(info->writes_viewport_index));
880 }
881
882 va = shader->bo->gpu_address;
883 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
884
885 if (gs) {
886 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
887 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
888 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
889 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
890 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
891 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
892 */
893 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
894
895 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
896 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
897 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
898 } else {
899 num_user_sgprs = SI_VS_NUM_USER_SGPR;
900 }
901 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
902 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
903 num_user_sgprs = SI_TES_NUM_USER_SGPR;
904 } else
905 unreachable("invalid shader selector type");
906
907 /* VS is required to export at least one param. */
908 nparams = MAX2(shader->info.nr_param_exports, 1);
909 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
910 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
911
912 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
913 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
914 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
915 V_02870C_SPI_SHADER_4COMP :
916 V_02870C_SPI_SHADER_NONE) |
917 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
918 V_02870C_SPI_SHADER_4COMP :
919 V_02870C_SPI_SHADER_NONE) |
920 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
921 V_02870C_SPI_SHADER_4COMP :
922 V_02870C_SPI_SHADER_NONE));
923
924 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
925
926 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
927 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
928 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
929 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
930 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
931 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
932 S_00B128_DX10_CLAMP(1) |
933 S_00B128_FLOAT_MODE(shader->config.float_mode));
934 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
935 S_00B12C_USER_SGPR(num_user_sgprs) |
936 S_00B12C_OC_LDS_EN(oc_lds_en) |
937 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
938 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
939 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
940 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
941 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
942 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
943 if (window_space)
944 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
945 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
946 else
947 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
948 S_028818_VTX_W0_FMT(1) |
949 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
950 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
951 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
952
953 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
954 si_set_tesseval_regs(sscreen, shader->selector, pm4);
955
956 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
957 }
958
959 static unsigned si_get_ps_num_interp(struct si_shader *ps)
960 {
961 struct tgsi_shader_info *info = &ps->selector->info;
962 unsigned num_colors = !!(info->colors_read & 0x0f) +
963 !!(info->colors_read & 0xf0);
964 unsigned num_interp = ps->selector->info.num_inputs +
965 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
966
967 assert(num_interp <= 32);
968 return MIN2(num_interp, 32);
969 }
970
971 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
972 {
973 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
974 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
975
976 /* If the i-th target format is set, all previous target formats must
977 * be non-zero to avoid hangs.
978 */
979 for (i = 0; i < num_targets; i++)
980 if (!(value & (0xf << (i * 4))))
981 value |= V_028714_SPI_SHADER_32_R << (i * 4);
982
983 return value;
984 }
985
986 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
987 {
988 unsigned i, cb_shader_mask = 0;
989
990 for (i = 0; i < 8; i++) {
991 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
992 case V_028714_SPI_SHADER_ZERO:
993 break;
994 case V_028714_SPI_SHADER_32_R:
995 cb_shader_mask |= 0x1 << (i * 4);
996 break;
997 case V_028714_SPI_SHADER_32_GR:
998 cb_shader_mask |= 0x3 << (i * 4);
999 break;
1000 case V_028714_SPI_SHADER_32_AR:
1001 cb_shader_mask |= 0x9 << (i * 4);
1002 break;
1003 case V_028714_SPI_SHADER_FP16_ABGR:
1004 case V_028714_SPI_SHADER_UNORM16_ABGR:
1005 case V_028714_SPI_SHADER_SNORM16_ABGR:
1006 case V_028714_SPI_SHADER_UINT16_ABGR:
1007 case V_028714_SPI_SHADER_SINT16_ABGR:
1008 case V_028714_SPI_SHADER_32_ABGR:
1009 cb_shader_mask |= 0xf << (i * 4);
1010 break;
1011 default:
1012 assert(0);
1013 }
1014 }
1015 return cb_shader_mask;
1016 }
1017
1018 static void si_shader_ps(struct si_shader *shader)
1019 {
1020 struct tgsi_shader_info *info = &shader->selector->info;
1021 struct si_pm4_state *pm4;
1022 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1023 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1024 uint64_t va;
1025 unsigned input_ena = shader->config.spi_ps_input_ena;
1026
1027 /* we need to enable at least one of them, otherwise we hang the GPU */
1028 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1029 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1030 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1031 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1032 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1033 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1034 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1035 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1036 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1037 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1038 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1039 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1040 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1041 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1042
1043 /* Validate interpolation optimization flags (read as implications). */
1044 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1045 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1046 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1047 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1048 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1049 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1050 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1051 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1052 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1053 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1054 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1055 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1056 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1057 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1058 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1059 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1060 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1061 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1062
1063 /* Validate cases when the optimizations are off (read as implications). */
1064 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1065 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1066 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1067 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1068 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1069 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1070
1071 pm4 = si_get_shader_pm4_state(shader);
1072 if (!pm4)
1073 return;
1074
1075 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1076 * Possible vaules:
1077 * 0 -> Position = pixel center
1078 * 1 -> Position = pixel centroid
1079 * 2 -> Position = at sample position
1080 *
1081 * From GLSL 4.5 specification, section 7.1:
1082 * "The variable gl_FragCoord is available as an input variable from
1083 * within fragment shaders and it holds the window relative coordinates
1084 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1085 * value can be for any location within the pixel, or one of the
1086 * fragment samples. The use of centroid does not further restrict
1087 * this value to be inside the current primitive."
1088 *
1089 * Meaning that centroid has no effect and we can return anything within
1090 * the pixel. Thus, return the value at sample position, because that's
1091 * the most accurate one shaders can get.
1092 */
1093 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1094
1095 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1096 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1097 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1098
1099 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1100 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
1101
1102 /* Ensure that some export memory is always allocated, for two reasons:
1103 *
1104 * 1) Correctness: The hardware ignores the EXEC mask if no export
1105 * memory is allocated, so KILL and alpha test do not work correctly
1106 * without this.
1107 * 2) Performance: Every shader needs at least a NULL export, even when
1108 * it writes no color/depth output. The NULL export instruction
1109 * stalls without this setting.
1110 *
1111 * Don't add this to CB_SHADER_MASK.
1112 */
1113 if (!spi_shader_col_format &&
1114 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1115 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1116
1117 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
1118 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
1119 shader->config.spi_ps_input_addr);
1120
1121 /* Set interpolation controls. */
1122 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1123
1124 /* Set registers. */
1125 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1126 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
1127
1128 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
1129 si_get_spi_shader_z_format(info->writes_z,
1130 info->writes_stencil,
1131 info->writes_samplemask));
1132
1133 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
1134 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
1135
1136 va = shader->bo->gpu_address;
1137 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1138 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1139 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
1140
1141 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1142 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1143 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
1144 S_00B028_DX10_CLAMP(1) |
1145 S_00B028_FLOAT_MODE(shader->config.float_mode));
1146 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1147 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1148 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1149 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1150 }
1151
1152 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1153 struct si_shader *shader)
1154 {
1155 switch (shader->selector->type) {
1156 case PIPE_SHADER_VERTEX:
1157 if (shader->key.as_ls)
1158 si_shader_ls(sscreen, shader);
1159 else if (shader->key.as_es)
1160 si_shader_es(sscreen, shader);
1161 else
1162 si_shader_vs(sscreen, shader, NULL);
1163 break;
1164 case PIPE_SHADER_TESS_CTRL:
1165 si_shader_hs(sscreen, shader);
1166 break;
1167 case PIPE_SHADER_TESS_EVAL:
1168 if (shader->key.as_es)
1169 si_shader_es(sscreen, shader);
1170 else
1171 si_shader_vs(sscreen, shader, NULL);
1172 break;
1173 case PIPE_SHADER_GEOMETRY:
1174 si_shader_gs(sscreen, shader);
1175 break;
1176 case PIPE_SHADER_FRAGMENT:
1177 si_shader_ps(shader);
1178 break;
1179 default:
1180 assert(0);
1181 }
1182 }
1183
1184 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1185 {
1186 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1187 if (sctx->queued.named.dsa)
1188 return sctx->queued.named.dsa->alpha_func;
1189
1190 return PIPE_FUNC_ALWAYS;
1191 }
1192
1193 static void si_shader_selector_key_vs(struct si_context *sctx,
1194 struct si_shader_selector *vs,
1195 struct si_shader_key *key,
1196 struct si_vs_prolog_bits *prolog_key)
1197 {
1198 if (!sctx->vertex_elements)
1199 return;
1200
1201 prolog_key->instance_divisor_is_one =
1202 sctx->vertex_elements->instance_divisor_is_one;
1203 prolog_key->instance_divisor_is_fetched =
1204 sctx->vertex_elements->instance_divisor_is_fetched;
1205
1206 /* Prefer a monolithic shader to allow scheduling divisions around
1207 * VBO loads. */
1208 if (prolog_key->instance_divisor_is_fetched)
1209 key->opt.prefer_mono = 1;
1210
1211 unsigned count = MIN2(vs->info.num_inputs,
1212 sctx->vertex_elements->count);
1213 memcpy(key->mono.vs_fix_fetch, sctx->vertex_elements->fix_fetch, count);
1214 }
1215
1216 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1217 struct si_shader_selector *vs,
1218 struct si_shader_key *key)
1219 {
1220 struct si_shader_selector *ps = sctx->ps_shader.cso;
1221
1222 key->opt.clip_disable =
1223 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1224 (vs->info.clipdist_writemask ||
1225 vs->info.writes_clipvertex) &&
1226 !vs->info.culldist_writemask;
1227
1228 /* Find out if PS is disabled. */
1229 bool ps_disabled = true;
1230 if (ps) {
1231 bool ps_modifies_zs = ps->info.uses_kill ||
1232 ps->info.writes_z ||
1233 ps->info.writes_stencil ||
1234 ps->info.writes_samplemask ||
1235 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1236
1237 unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1238 sctx->queued.named.blend->cb_target_mask;
1239 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1240 ps_colormask &= ps->colors_written_4bit;
1241
1242 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1243 (!ps_colormask &&
1244 !ps_modifies_zs &&
1245 !ps->info.writes_memory);
1246 }
1247
1248 /* Find out which VS outputs aren't used by the PS. */
1249 uint64_t outputs_written = vs->outputs_written;
1250 uint64_t inputs_read = 0;
1251
1252 /* ignore POSITION, PSIZE */
1253 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0) |
1254 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0))));
1255
1256 if (!ps_disabled) {
1257 inputs_read = ps->inputs_read;
1258 }
1259
1260 uint64_t linked = outputs_written & inputs_read;
1261
1262 key->opt.kill_outputs = ~linked & outputs_written;
1263 }
1264
1265 /* Compute the key for the hw shader variant */
1266 static inline void si_shader_selector_key(struct pipe_context *ctx,
1267 struct si_shader_selector *sel,
1268 struct si_shader_key *key)
1269 {
1270 struct si_context *sctx = (struct si_context *)ctx;
1271
1272 memset(key, 0, sizeof(*key));
1273
1274 switch (sel->type) {
1275 case PIPE_SHADER_VERTEX:
1276 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1277
1278 if (sctx->tes_shader.cso)
1279 key->as_ls = 1;
1280 else if (sctx->gs_shader.cso)
1281 key->as_es = 1;
1282 else {
1283 si_shader_selector_key_hw_vs(sctx, sel, key);
1284
1285 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1286 key->mono.u.vs_export_prim_id = 1;
1287 }
1288 break;
1289 case PIPE_SHADER_TESS_CTRL:
1290 if (sctx->b.chip_class >= GFX9) {
1291 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1292 key, &key->part.tcs.ls_prolog);
1293 key->part.tcs.ls = sctx->vs_shader.cso;
1294
1295 /* When the LS VGPR fix is needed, monolithic shaders
1296 * can:
1297 * - avoid initializing EXEC in both the LS prolog
1298 * and the LS main part when !vs_needs_prolog
1299 * - remove the fixup for unused input VGPRs
1300 */
1301 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1302
1303 /* The LS output / HS input layout can be communicated
1304 * directly instead of via user SGPRs for merged LS-HS.
1305 * The LS VGPR fix prefers this too.
1306 */
1307 key->opt.prefer_mono = 1;
1308 }
1309
1310 key->part.tcs.epilog.prim_mode =
1311 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1312 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1313 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1314 key->part.tcs.epilog.tes_reads_tess_factors =
1315 sctx->tes_shader.cso->info.reads_tess_factors;
1316
1317 if (sel == sctx->fixed_func_tcs_shader.cso)
1318 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1319 break;
1320 case PIPE_SHADER_TESS_EVAL:
1321 if (sctx->gs_shader.cso)
1322 key->as_es = 1;
1323 else {
1324 si_shader_selector_key_hw_vs(sctx, sel, key);
1325
1326 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1327 key->mono.u.vs_export_prim_id = 1;
1328 }
1329 break;
1330 case PIPE_SHADER_GEOMETRY:
1331 if (sctx->b.chip_class >= GFX9) {
1332 if (sctx->tes_shader.cso) {
1333 key->part.gs.es = sctx->tes_shader.cso;
1334 } else {
1335 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1336 key, &key->part.gs.vs_prolog);
1337 key->part.gs.es = sctx->vs_shader.cso;
1338 }
1339
1340 /* Merged ES-GS can have unbalanced wave usage.
1341 *
1342 * ES threads are per-vertex, while GS threads are
1343 * per-primitive. So without any amplification, there
1344 * are fewer GS threads than ES threads, which can result
1345 * in empty (no-op) GS waves. With too much amplification,
1346 * there are more GS threads than ES threads, which
1347 * can result in empty (no-op) ES waves.
1348 *
1349 * Non-monolithic shaders are implemented by setting EXEC
1350 * at the beginning of shader parts, and don't jump to
1351 * the end if EXEC is 0.
1352 *
1353 * Monolithic shaders use conditional blocks, so they can
1354 * jump and skip empty waves of ES or GS. So set this to
1355 * always use optimized variants, which are monolithic.
1356 */
1357 key->opt.prefer_mono = 1;
1358 }
1359 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1360 break;
1361 case PIPE_SHADER_FRAGMENT: {
1362 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1363 struct si_state_blend *blend = sctx->queued.named.blend;
1364
1365 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1366 sel->info.colors_written == 0x1)
1367 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1368
1369 if (blend) {
1370 /* Select the shader color format based on whether
1371 * blending or alpha are needed.
1372 */
1373 key->part.ps.epilog.spi_shader_col_format =
1374 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1375 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1376 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1377 sctx->framebuffer.spi_shader_col_format_blend) |
1378 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1379 sctx->framebuffer.spi_shader_col_format_alpha) |
1380 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1381 sctx->framebuffer.spi_shader_col_format);
1382 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1383
1384 /* The output for dual source blending should have
1385 * the same format as the first output.
1386 */
1387 if (blend->dual_src_blend)
1388 key->part.ps.epilog.spi_shader_col_format |=
1389 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1390 } else
1391 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1392
1393 /* If alpha-to-coverage is enabled, we have to export alpha
1394 * even if there is no color buffer.
1395 */
1396 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1397 blend && blend->alpha_to_coverage)
1398 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1399
1400 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1401 * to the range supported by the type if a channel has less
1402 * than 16 bits and the export format is 16_ABGR.
1403 */
1404 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII) {
1405 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1406 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1407 }
1408
1409 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1410 if (!key->part.ps.epilog.last_cbuf) {
1411 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1412 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1413 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1414 }
1415
1416 if (rs) {
1417 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
1418 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
1419 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
1420 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
1421
1422 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1423 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1424
1425 if (sctx->queued.named.blend) {
1426 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1427 rs->multisample_enable;
1428 }
1429
1430 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1431 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1432 (is_line && rs->line_smooth)) &&
1433 sctx->framebuffer.nr_samples <= 1;
1434 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1435
1436 if (sctx->ps_iter_samples > 1 &&
1437 sel->info.reads_samplemask) {
1438 key->part.ps.prolog.samplemask_log_ps_iter =
1439 util_logbase2(util_next_power_of_two(sctx->ps_iter_samples));
1440 }
1441
1442 if (rs->force_persample_interp &&
1443 rs->multisample_enable &&
1444 sctx->framebuffer.nr_samples > 1 &&
1445 sctx->ps_iter_samples > 1) {
1446 key->part.ps.prolog.force_persp_sample_interp =
1447 sel->info.uses_persp_center ||
1448 sel->info.uses_persp_centroid;
1449
1450 key->part.ps.prolog.force_linear_sample_interp =
1451 sel->info.uses_linear_center ||
1452 sel->info.uses_linear_centroid;
1453 } else if (rs->multisample_enable &&
1454 sctx->framebuffer.nr_samples > 1) {
1455 key->part.ps.prolog.bc_optimize_for_persp =
1456 sel->info.uses_persp_center &&
1457 sel->info.uses_persp_centroid;
1458 key->part.ps.prolog.bc_optimize_for_linear =
1459 sel->info.uses_linear_center &&
1460 sel->info.uses_linear_centroid;
1461 } else {
1462 /* Make sure SPI doesn't compute more than 1 pair
1463 * of (i,j), which is the optimization here. */
1464 key->part.ps.prolog.force_persp_center_interp =
1465 sel->info.uses_persp_center +
1466 sel->info.uses_persp_centroid +
1467 sel->info.uses_persp_sample > 1;
1468
1469 key->part.ps.prolog.force_linear_center_interp =
1470 sel->info.uses_linear_center +
1471 sel->info.uses_linear_centroid +
1472 sel->info.uses_linear_sample > 1;
1473
1474 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
1475 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1476 }
1477 }
1478
1479 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1480 break;
1481 }
1482 default:
1483 assert(0);
1484 }
1485
1486 if (unlikely(sctx->screen->b.debug_flags & DBG_NO_OPT_VARIANT))
1487 memset(&key->opt, 0, sizeof(key->opt));
1488 }
1489
1490 static void si_build_shader_variant(struct si_shader *shader,
1491 int thread_index,
1492 bool low_priority)
1493 {
1494 struct si_shader_selector *sel = shader->selector;
1495 struct si_screen *sscreen = sel->screen;
1496 LLVMTargetMachineRef tm;
1497 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1498 int r;
1499
1500 if (thread_index >= 0) {
1501 if (low_priority) {
1502 assert(thread_index < ARRAY_SIZE(sscreen->tm_low_priority));
1503 tm = sscreen->tm_low_priority[thread_index];
1504 } else {
1505 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1506 tm = sscreen->tm[thread_index];
1507 }
1508 if (!debug->async)
1509 debug = NULL;
1510 } else {
1511 assert(!low_priority);
1512 tm = shader->compiler_ctx_state.tm;
1513 }
1514
1515 r = si_shader_create(sscreen, tm, shader, debug);
1516 if (unlikely(r)) {
1517 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1518 sel->type, r);
1519 shader->compilation_failed = true;
1520 return;
1521 }
1522
1523 if (shader->compiler_ctx_state.is_debug_context) {
1524 FILE *f = open_memstream(&shader->shader_log,
1525 &shader->shader_log_size);
1526 if (f) {
1527 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1528 fclose(f);
1529 }
1530 }
1531
1532 si_shader_init_pm4_state(sscreen, shader);
1533 }
1534
1535 static void si_build_shader_variant_low_priority(void *job, int thread_index)
1536 {
1537 struct si_shader *shader = (struct si_shader *)job;
1538
1539 assert(thread_index >= 0);
1540
1541 si_build_shader_variant(shader, thread_index, true);
1542 }
1543
1544 static const struct si_shader_key zeroed;
1545
1546 static bool si_check_missing_main_part(struct si_screen *sscreen,
1547 struct si_shader_selector *sel,
1548 struct si_compiler_ctx_state *compiler_state,
1549 struct si_shader_key *key)
1550 {
1551 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1552
1553 if (!*mainp) {
1554 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1555
1556 if (!main_part)
1557 return false;
1558
1559 main_part->selector = sel;
1560 main_part->key.as_es = key->as_es;
1561 main_part->key.as_ls = key->as_ls;
1562
1563 if (si_compile_tgsi_shader(sscreen, compiler_state->tm,
1564 main_part, false,
1565 &compiler_state->debug) != 0) {
1566 FREE(main_part);
1567 return false;
1568 }
1569 *mainp = main_part;
1570 }
1571 return true;
1572 }
1573
1574 /* Select the hw shader variant depending on the current state. */
1575 static int si_shader_select_with_key(struct si_screen *sscreen,
1576 struct si_shader_ctx_state *state,
1577 struct si_compiler_ctx_state *compiler_state,
1578 struct si_shader_key *key,
1579 int thread_index)
1580 {
1581 struct si_shader_selector *sel = state->cso;
1582 struct si_shader_selector *previous_stage_sel = NULL;
1583 struct si_shader *current = state->current;
1584 struct si_shader *iter, *shader = NULL;
1585
1586 again:
1587 /* Check if we don't need to change anything.
1588 * This path is also used for most shaders that don't need multiple
1589 * variants, it will cost just a computation of the key and this
1590 * test. */
1591 if (likely(current &&
1592 memcmp(&current->key, key, sizeof(*key)) == 0 &&
1593 (!current->is_optimized ||
1594 util_queue_fence_is_signalled(&current->optimized_ready))))
1595 return current->compilation_failed ? -1 : 0;
1596
1597 /* This must be done before the mutex is locked, because async GS
1598 * compilation calls this function too, and therefore must enter
1599 * the mutex first.
1600 *
1601 * Only wait if we are in a draw call. Don't wait if we are
1602 * in a compiler thread.
1603 */
1604 if (thread_index < 0)
1605 util_queue_fence_wait(&sel->ready);
1606
1607 mtx_lock(&sel->mutex);
1608
1609 /* Find the shader variant. */
1610 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1611 /* Don't check the "current" shader. We checked it above. */
1612 if (current != iter &&
1613 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1614 /* If it's an optimized shader and its compilation has
1615 * been started but isn't done, use the unoptimized
1616 * shader so as not to cause a stall due to compilation.
1617 */
1618 if (iter->is_optimized &&
1619 !util_queue_fence_is_signalled(&iter->optimized_ready)) {
1620 memset(&key->opt, 0, sizeof(key->opt));
1621 mtx_unlock(&sel->mutex);
1622 goto again;
1623 }
1624
1625 if (iter->compilation_failed) {
1626 mtx_unlock(&sel->mutex);
1627 return -1; /* skip the draw call */
1628 }
1629
1630 state->current = iter;
1631 mtx_unlock(&sel->mutex);
1632 return 0;
1633 }
1634 }
1635
1636 /* Build a new shader. */
1637 shader = CALLOC_STRUCT(si_shader);
1638 if (!shader) {
1639 mtx_unlock(&sel->mutex);
1640 return -ENOMEM;
1641 }
1642 shader->selector = sel;
1643 shader->key = *key;
1644 shader->compiler_ctx_state = *compiler_state;
1645
1646 /* If this is a merged shader, get the first shader's selector. */
1647 if (sscreen->b.chip_class >= GFX9) {
1648 if (sel->type == PIPE_SHADER_TESS_CTRL)
1649 previous_stage_sel = key->part.tcs.ls;
1650 else if (sel->type == PIPE_SHADER_GEOMETRY)
1651 previous_stage_sel = key->part.gs.es;
1652
1653 /* We need to wait for the previous shader. */
1654 if (previous_stage_sel && thread_index < 0)
1655 util_queue_fence_wait(&previous_stage_sel->ready);
1656 }
1657
1658 /* Compile the main shader part if it doesn't exist. This can happen
1659 * if the initial guess was wrong. */
1660 bool is_pure_monolithic =
1661 sscreen->use_monolithic_shaders ||
1662 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1663
1664 if (!is_pure_monolithic) {
1665 bool ok;
1666
1667 /* Make sure the main shader part is present. This is needed
1668 * for shaders that can be compiled as VS, LS, or ES, and only
1669 * one of them is compiled at creation.
1670 *
1671 * For merged shaders, check that the starting shader's main
1672 * part is present.
1673 */
1674 if (previous_stage_sel) {
1675 struct si_shader_key shader1_key = zeroed;
1676
1677 if (sel->type == PIPE_SHADER_TESS_CTRL)
1678 shader1_key.as_ls = 1;
1679 else if (sel->type == PIPE_SHADER_GEOMETRY)
1680 shader1_key.as_es = 1;
1681 else
1682 assert(0);
1683
1684 mtx_lock(&previous_stage_sel->mutex);
1685 ok = si_check_missing_main_part(sscreen,
1686 previous_stage_sel,
1687 compiler_state, &shader1_key);
1688 mtx_unlock(&previous_stage_sel->mutex);
1689 } else {
1690 ok = si_check_missing_main_part(sscreen, sel,
1691 compiler_state, key);
1692 }
1693 if (!ok) {
1694 FREE(shader);
1695 mtx_unlock(&sel->mutex);
1696 return -ENOMEM; /* skip the draw call */
1697 }
1698 }
1699
1700 /* Keep the reference to the 1st shader of merged shaders, so that
1701 * Gallium can't destroy it before we destroy the 2nd shader.
1702 *
1703 * Set sctx = NULL, because it's unused if we're not releasing
1704 * the shader, and we don't have any sctx here.
1705 */
1706 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
1707 previous_stage_sel);
1708
1709 /* Monolithic-only shaders don't make a distinction between optimized
1710 * and unoptimized. */
1711 shader->is_monolithic =
1712 is_pure_monolithic ||
1713 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1714
1715 shader->is_optimized =
1716 !is_pure_monolithic &&
1717 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1718 if (shader->is_optimized)
1719 util_queue_fence_init(&shader->optimized_ready);
1720
1721 if (!sel->last_variant) {
1722 sel->first_variant = shader;
1723 sel->last_variant = shader;
1724 } else {
1725 sel->last_variant->next_variant = shader;
1726 sel->last_variant = shader;
1727 }
1728
1729 /* If it's an optimized shader, compile it asynchronously. */
1730 if (shader->is_optimized &&
1731 !is_pure_monolithic &&
1732 thread_index < 0) {
1733 /* Compile it asynchronously. */
1734 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
1735 shader, &shader->optimized_ready,
1736 si_build_shader_variant_low_priority, NULL);
1737
1738 /* Use the default (unoptimized) shader for now. */
1739 memset(&key->opt, 0, sizeof(key->opt));
1740 mtx_unlock(&sel->mutex);
1741 goto again;
1742 }
1743
1744 assert(!shader->is_optimized);
1745 si_build_shader_variant(shader, thread_index, false);
1746
1747 if (!shader->compilation_failed)
1748 state->current = shader;
1749
1750 mtx_unlock(&sel->mutex);
1751 return shader->compilation_failed ? -1 : 0;
1752 }
1753
1754 static int si_shader_select(struct pipe_context *ctx,
1755 struct si_shader_ctx_state *state,
1756 struct si_compiler_ctx_state *compiler_state)
1757 {
1758 struct si_context *sctx = (struct si_context *)ctx;
1759 struct si_shader_key key;
1760
1761 si_shader_selector_key(ctx, state->cso, &key);
1762 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1763 &key, -1);
1764 }
1765
1766 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1767 bool streamout,
1768 struct si_shader_key *key)
1769 {
1770 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1771
1772 switch (info->processor) {
1773 case PIPE_SHADER_VERTEX:
1774 switch (next_shader) {
1775 case PIPE_SHADER_GEOMETRY:
1776 key->as_es = 1;
1777 break;
1778 case PIPE_SHADER_TESS_CTRL:
1779 case PIPE_SHADER_TESS_EVAL:
1780 key->as_ls = 1;
1781 break;
1782 default:
1783 /* If POSITION isn't written, it can only be a HW VS
1784 * if streamout is used. If streamout isn't used,
1785 * assume that it's a HW LS. (the next shader is TCS)
1786 * This heuristic is needed for separate shader objects.
1787 */
1788 if (!info->writes_position && !streamout)
1789 key->as_ls = 1;
1790 }
1791 break;
1792
1793 case PIPE_SHADER_TESS_EVAL:
1794 if (next_shader == PIPE_SHADER_GEOMETRY ||
1795 !info->writes_position)
1796 key->as_es = 1;
1797 break;
1798 }
1799 }
1800
1801 /**
1802 * Compile the main shader part or the monolithic shader as part of
1803 * si_shader_selector initialization. Since it can be done asynchronously,
1804 * there is no way to report compile failures to applications.
1805 */
1806 static void si_init_shader_selector_async(void *job, int thread_index)
1807 {
1808 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1809 struct si_screen *sscreen = sel->screen;
1810 LLVMTargetMachineRef tm;
1811 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
1812 unsigned i;
1813
1814 if (thread_index >= 0) {
1815 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1816 tm = sscreen->tm[thread_index];
1817 if (!debug->async)
1818 debug = NULL;
1819 } else {
1820 tm = sel->compiler_ctx_state.tm;
1821 }
1822
1823 /* Compile the main shader part for use with a prolog and/or epilog.
1824 * If this fails, the driver will try to compile a monolithic shader
1825 * on demand.
1826 */
1827 if (!sscreen->use_monolithic_shaders) {
1828 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1829 void *tgsi_binary = NULL;
1830
1831 if (!shader) {
1832 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1833 return;
1834 }
1835
1836 shader->selector = sel;
1837 si_parse_next_shader_property(&sel->info,
1838 sel->so.num_outputs != 0,
1839 &shader->key);
1840
1841 if (sel->tokens)
1842 tgsi_binary = si_get_tgsi_binary(sel);
1843
1844 /* Try to load the shader from the shader cache. */
1845 mtx_lock(&sscreen->shader_cache_mutex);
1846
1847 if (tgsi_binary &&
1848 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1849 mtx_unlock(&sscreen->shader_cache_mutex);
1850 } else {
1851 mtx_unlock(&sscreen->shader_cache_mutex);
1852
1853 /* Compile the shader if it hasn't been loaded from the cache. */
1854 if (si_compile_tgsi_shader(sscreen, tm, shader, false,
1855 debug) != 0) {
1856 FREE(shader);
1857 FREE(tgsi_binary);
1858 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1859 return;
1860 }
1861
1862 if (tgsi_binary) {
1863 mtx_lock(&sscreen->shader_cache_mutex);
1864 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary, shader, true))
1865 FREE(tgsi_binary);
1866 mtx_unlock(&sscreen->shader_cache_mutex);
1867 }
1868 }
1869
1870 *si_get_main_shader_part(sel, &shader->key) = shader;
1871
1872 /* Unset "outputs_written" flags for outputs converted to
1873 * DEFAULT_VAL, so that later inter-shader optimizations don't
1874 * try to eliminate outputs that don't exist in the final
1875 * shader.
1876 *
1877 * This is only done if non-monolithic shaders are enabled.
1878 */
1879 if ((sel->type == PIPE_SHADER_VERTEX ||
1880 sel->type == PIPE_SHADER_TESS_EVAL) &&
1881 !shader->key.as_ls &&
1882 !shader->key.as_es) {
1883 unsigned i;
1884
1885 for (i = 0; i < sel->info.num_outputs; i++) {
1886 unsigned offset = shader->info.vs_output_param_offset[i];
1887
1888 if (offset <= AC_EXP_PARAM_OFFSET_31)
1889 continue;
1890
1891 unsigned name = sel->info.output_semantic_name[i];
1892 unsigned index = sel->info.output_semantic_index[i];
1893 unsigned id;
1894
1895 switch (name) {
1896 case TGSI_SEMANTIC_GENERIC:
1897 /* don't process indices the function can't handle */
1898 if (index >= SI_MAX_IO_GENERIC)
1899 break;
1900 /* fall through */
1901 default:
1902 id = si_shader_io_get_unique_index(name, index);
1903 sel->outputs_written &= ~(1ull << id);
1904 break;
1905 case TGSI_SEMANTIC_POSITION: /* ignore these */
1906 case TGSI_SEMANTIC_PSIZE:
1907 case TGSI_SEMANTIC_CLIPVERTEX:
1908 case TGSI_SEMANTIC_EDGEFLAG:
1909 break;
1910 }
1911 }
1912 }
1913 }
1914
1915 /* Pre-compilation. */
1916 if (sscreen->b.debug_flags & DBG_PRECOMPILE &&
1917 /* GFX9 needs LS or ES for compilation, which we don't have here. */
1918 (sscreen->b.chip_class <= VI ||
1919 (sel->type != PIPE_SHADER_TESS_CTRL &&
1920 sel->type != PIPE_SHADER_GEOMETRY))) {
1921 struct si_shader_ctx_state state = {sel};
1922 struct si_shader_key key;
1923
1924 memset(&key, 0, sizeof(key));
1925 si_parse_next_shader_property(&sel->info,
1926 sel->so.num_outputs != 0,
1927 &key);
1928
1929 /* GFX9 doesn't have LS and ES. */
1930 if (sscreen->b.chip_class >= GFX9) {
1931 key.as_ls = 0;
1932 key.as_es = 0;
1933 }
1934
1935 /* Set reasonable defaults, so that the shader key doesn't
1936 * cause any code to be eliminated.
1937 */
1938 switch (sel->type) {
1939 case PIPE_SHADER_TESS_CTRL:
1940 key.part.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1941 break;
1942 case PIPE_SHADER_FRAGMENT:
1943 key.part.ps.prolog.bc_optimize_for_persp =
1944 sel->info.uses_persp_center &&
1945 sel->info.uses_persp_centroid;
1946 key.part.ps.prolog.bc_optimize_for_linear =
1947 sel->info.uses_linear_center &&
1948 sel->info.uses_linear_centroid;
1949 key.part.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1950 for (i = 0; i < 8; i++)
1951 if (sel->info.colors_written & (1 << i))
1952 key.part.ps.epilog.spi_shader_col_format |=
1953 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1954 break;
1955 }
1956
1957 if (si_shader_select_with_key(sscreen, &state,
1958 &sel->compiler_ctx_state, &key,
1959 thread_index))
1960 fprintf(stderr, "radeonsi: can't create a monolithic shader\n");
1961 }
1962
1963 /* The GS copy shader is always pre-compiled. */
1964 if (sel->type == PIPE_SHADER_GEOMETRY) {
1965 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
1966 if (!sel->gs_copy_shader) {
1967 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
1968 return;
1969 }
1970
1971 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
1972 }
1973 }
1974
1975 /* Return descriptor slot usage masks from the given shader info. */
1976 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
1977 uint32_t *const_and_shader_buffers,
1978 uint64_t *samplers_and_images)
1979 {
1980 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
1981
1982 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
1983 num_constbufs = util_last_bit(info->const_buffers_declared);
1984 /* two 8-byte images share one 16-byte slot */
1985 num_images = align(util_last_bit(info->images_declared), 2);
1986 num_samplers = util_last_bit(info->samplers_declared);
1987
1988 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
1989 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
1990 *const_and_shader_buffers =
1991 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
1992
1993 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
1994 start = si_get_image_slot(num_images - 1) / 2;
1995 *samplers_and_images =
1996 u_bit_consecutive64(start, num_images / 2 + num_samplers);
1997 }
1998
1999 static void *si_create_shader_selector(struct pipe_context *ctx,
2000 const struct pipe_shader_state *state)
2001 {
2002 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2003 struct si_context *sctx = (struct si_context*)ctx;
2004 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2005 int i;
2006
2007 if (!sel)
2008 return NULL;
2009
2010 pipe_reference_init(&sel->reference, 1);
2011 sel->screen = sscreen;
2012 sel->compiler_ctx_state.tm = sctx->tm;
2013 sel->compiler_ctx_state.debug = sctx->b.debug;
2014 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2015
2016 sel->so = state->stream_output;
2017
2018 if (state->type == PIPE_SHADER_IR_TGSI) {
2019 sel->tokens = tgsi_dup_tokens(state->tokens);
2020 if (!sel->tokens) {
2021 FREE(sel);
2022 return NULL;
2023 }
2024
2025 tgsi_scan_shader(state->tokens, &sel->info);
2026 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2027 } else {
2028 assert(state->type == PIPE_SHADER_IR_NIR);
2029
2030 sel->nir = state->ir.nir;
2031
2032 si_nir_scan_shader(sel->nir, &sel->info);
2033
2034 si_lower_nir(sel);
2035 }
2036
2037 sel->type = sel->info.processor;
2038 p_atomic_inc(&sscreen->b.num_shaders_created);
2039 si_get_active_slot_masks(&sel->info,
2040 &sel->active_const_and_shader_buffers,
2041 &sel->active_samplers_and_images);
2042
2043 /* Record which streamout buffers are enabled. */
2044 for (i = 0; i < sel->so.num_outputs; i++) {
2045 sel->enabled_streamout_buffer_mask |=
2046 (1 << sel->so.output[i].output_buffer) <<
2047 (sel->so.output[i].stream * 4);
2048 }
2049
2050 /* The prolog is a no-op if there are no inputs. */
2051 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2052 sel->info.num_inputs &&
2053 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2054
2055 /* Set which opcode uses which (i,j) pair. */
2056 if (sel->info.uses_persp_opcode_interp_centroid)
2057 sel->info.uses_persp_centroid = true;
2058
2059 if (sel->info.uses_linear_opcode_interp_centroid)
2060 sel->info.uses_linear_centroid = true;
2061
2062 if (sel->info.uses_persp_opcode_interp_offset ||
2063 sel->info.uses_persp_opcode_interp_sample)
2064 sel->info.uses_persp_center = true;
2065
2066 if (sel->info.uses_linear_opcode_interp_offset ||
2067 sel->info.uses_linear_opcode_interp_sample)
2068 sel->info.uses_linear_center = true;
2069
2070 switch (sel->type) {
2071 case PIPE_SHADER_GEOMETRY:
2072 sel->gs_output_prim =
2073 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2074 sel->gs_max_out_vertices =
2075 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2076 sel->gs_num_invocations =
2077 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2078 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2079 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2080 sel->gs_max_out_vertices;
2081
2082 sel->max_gs_stream = 0;
2083 for (i = 0; i < sel->so.num_outputs; i++)
2084 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2085 sel->so.output[i].stream);
2086
2087 sel->gs_input_verts_per_prim =
2088 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2089 break;
2090
2091 case PIPE_SHADER_TESS_CTRL:
2092 /* Always reserve space for these. */
2093 sel->patch_outputs_written |=
2094 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2095 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2096 /* fall through */
2097 case PIPE_SHADER_VERTEX:
2098 case PIPE_SHADER_TESS_EVAL:
2099 for (i = 0; i < sel->info.num_outputs; i++) {
2100 unsigned name = sel->info.output_semantic_name[i];
2101 unsigned index = sel->info.output_semantic_index[i];
2102
2103 switch (name) {
2104 case TGSI_SEMANTIC_TESSINNER:
2105 case TGSI_SEMANTIC_TESSOUTER:
2106 case TGSI_SEMANTIC_PATCH:
2107 sel->patch_outputs_written |=
2108 1ull << si_shader_io_get_unique_index_patch(name, index);
2109 break;
2110
2111 case TGSI_SEMANTIC_GENERIC:
2112 /* don't process indices the function can't handle */
2113 if (index >= SI_MAX_IO_GENERIC)
2114 break;
2115 /* fall through */
2116 default:
2117 sel->outputs_written |=
2118 1ull << si_shader_io_get_unique_index(name, index);
2119 break;
2120 case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
2121 case TGSI_SEMANTIC_EDGEFLAG:
2122 break;
2123 }
2124 }
2125 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2126
2127 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2128 * conflicts, i.e. each vertex will start at a different bank.
2129 */
2130 if (sctx->b.chip_class >= GFX9)
2131 sel->esgs_itemsize += 4;
2132 break;
2133
2134 case PIPE_SHADER_FRAGMENT:
2135 for (i = 0; i < sel->info.num_inputs; i++) {
2136 unsigned name = sel->info.input_semantic_name[i];
2137 unsigned index = sel->info.input_semantic_index[i];
2138
2139 switch (name) {
2140 case TGSI_SEMANTIC_GENERIC:
2141 /* don't process indices the function can't handle */
2142 if (index >= SI_MAX_IO_GENERIC)
2143 break;
2144 /* fall through */
2145 default:
2146 sel->inputs_read |=
2147 1ull << si_shader_io_get_unique_index(name, index);
2148 break;
2149 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2150 break;
2151 }
2152 }
2153
2154 for (i = 0; i < 8; i++)
2155 if (sel->info.colors_written & (1 << i))
2156 sel->colors_written_4bit |= 0xf << (4 * i);
2157
2158 for (i = 0; i < sel->info.num_inputs; i++) {
2159 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2160 int index = sel->info.input_semantic_index[i];
2161 sel->color_attr_index[index] = i;
2162 }
2163 }
2164 break;
2165 }
2166
2167 /* PA_CL_VS_OUT_CNTL */
2168 bool misc_vec_ena =
2169 sel->info.writes_psize || sel->info.writes_edgeflag ||
2170 sel->info.writes_layer || sel->info.writes_viewport_index;
2171 sel->pa_cl_vs_out_cntl =
2172 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2173 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2174 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2175 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2176 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2177 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2178 sel->clipdist_mask = sel->info.writes_clipvertex ?
2179 SIX_BITS : sel->info.clipdist_writemask;
2180 sel->culldist_mask = sel->info.culldist_writemask <<
2181 sel->info.num_written_clipdistance;
2182
2183 /* DB_SHADER_CONTROL */
2184 sel->db_shader_control =
2185 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2186 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2187 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2188 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2189
2190 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2191 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2192 sel->db_shader_control |=
2193 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2194 break;
2195 case TGSI_FS_DEPTH_LAYOUT_LESS:
2196 sel->db_shader_control |=
2197 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2198 break;
2199 }
2200
2201 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2202 *
2203 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2204 * --|-----------|------------|------------|--------------------|-------------------|-------------
2205 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2206 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2207 * 2 | false | true | n/a | LateZ | 1 | 0
2208 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2209 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2210 *
2211 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2212 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2213 *
2214 * Don't use ReZ without profiling !!!
2215 *
2216 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2217 * shaders.
2218 */
2219 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2220 /* Cases 3, 4. */
2221 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2222 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2223 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2224 } else if (sel->info.writes_memory) {
2225 /* Case 2. */
2226 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2227 S_02880C_EXEC_ON_HIER_FAIL(1);
2228 } else {
2229 /* Case 1. */
2230 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2231 }
2232
2233 (void) mtx_init(&sel->mutex, mtx_plain);
2234 util_queue_fence_init(&sel->ready);
2235
2236 if ((sctx->b.debug.debug_message && !sctx->b.debug.async) ||
2237 sctx->is_debug ||
2238 si_can_dump_shader(&sscreen->b, sel->info.processor))
2239 si_init_shader_selector_async(sel, -1);
2240 else
2241 util_queue_add_job(&sscreen->shader_compiler_queue, sel,
2242 &sel->ready, si_init_shader_selector_async,
2243 NULL);
2244
2245 return sel;
2246 }
2247
2248 static void si_update_streamout_state(struct si_context *sctx)
2249 {
2250 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2251
2252 if (!shader_with_so)
2253 return;
2254
2255 sctx->b.streamout.enabled_stream_buffers_mask =
2256 shader_with_so->enabled_streamout_buffer_mask;
2257 sctx->b.streamout.stride_in_dw = shader_with_so->so.stride;
2258 }
2259
2260 static void si_update_clip_regs(struct si_context *sctx,
2261 struct si_shader_selector *old_hw_vs,
2262 struct si_shader *old_hw_vs_variant,
2263 struct si_shader_selector *next_hw_vs,
2264 struct si_shader *next_hw_vs_variant)
2265 {
2266 if (next_hw_vs &&
2267 (!old_hw_vs ||
2268 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2269 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2270 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2271 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2272 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2273 !old_hw_vs_variant ||
2274 !next_hw_vs_variant ||
2275 old_hw_vs_variant->key.opt.clip_disable !=
2276 next_hw_vs_variant->key.opt.clip_disable))
2277 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2278 }
2279
2280 static void si_update_common_shader_state(struct si_context *sctx)
2281 {
2282 sctx->uses_bindless_samplers =
2283 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2284 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2285 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2286 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2287 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2288 sctx->uses_bindless_images =
2289 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2290 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2291 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2292 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2293 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2294 sctx->do_update_shaders = true;
2295 }
2296
2297 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2298 {
2299 struct si_context *sctx = (struct si_context *)ctx;
2300 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2301 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2302 struct si_shader_selector *sel = state;
2303
2304 if (sctx->vs_shader.cso == sel)
2305 return;
2306
2307 sctx->vs_shader.cso = sel;
2308 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2309
2310 si_update_common_shader_state(sctx);
2311 si_update_vs_writes_viewport_index(sctx);
2312 si_set_active_descriptors_for_shader(sctx, sel);
2313 si_update_streamout_state(sctx);
2314 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2315 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2316 }
2317
2318 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2319 {
2320 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2321 (sctx->tes_shader.cso &&
2322 sctx->tes_shader.cso->info.uses_primid) ||
2323 (sctx->tcs_shader.cso &&
2324 sctx->tcs_shader.cso->info.uses_primid) ||
2325 (sctx->gs_shader.cso &&
2326 sctx->gs_shader.cso->info.uses_primid) ||
2327 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2328 sctx->ps_shader.cso->info.uses_primid);
2329 }
2330
2331 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2332 {
2333 struct si_context *sctx = (struct si_context *)ctx;
2334 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2335 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2336 struct si_shader_selector *sel = state;
2337 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2338
2339 if (sctx->gs_shader.cso == sel)
2340 return;
2341
2342 sctx->gs_shader.cso = sel;
2343 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2344 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2345
2346 si_update_common_shader_state(sctx);
2347 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2348
2349 if (enable_changed) {
2350 si_shader_change_notify(sctx);
2351 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2352 si_update_tess_uses_prim_id(sctx);
2353 }
2354 si_update_vs_writes_viewport_index(sctx);
2355 si_set_active_descriptors_for_shader(sctx, sel);
2356 si_update_streamout_state(sctx);
2357 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2358 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2359 }
2360
2361 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2362 {
2363 struct si_context *sctx = (struct si_context *)ctx;
2364 struct si_shader_selector *sel = state;
2365 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2366
2367 if (sctx->tcs_shader.cso == sel)
2368 return;
2369
2370 sctx->tcs_shader.cso = sel;
2371 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2372 si_update_tess_uses_prim_id(sctx);
2373
2374 si_update_common_shader_state(sctx);
2375
2376 if (enable_changed)
2377 sctx->last_tcs = NULL; /* invalidate derived tess state */
2378
2379 si_set_active_descriptors_for_shader(sctx, sel);
2380 }
2381
2382 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2383 {
2384 struct si_context *sctx = (struct si_context *)ctx;
2385 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2386 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2387 struct si_shader_selector *sel = state;
2388 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2389
2390 if (sctx->tes_shader.cso == sel)
2391 return;
2392
2393 sctx->tes_shader.cso = sel;
2394 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2395 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2396 si_update_tess_uses_prim_id(sctx);
2397
2398 si_update_common_shader_state(sctx);
2399 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2400
2401 if (enable_changed) {
2402 si_shader_change_notify(sctx);
2403 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2404 }
2405 si_update_vs_writes_viewport_index(sctx);
2406 si_set_active_descriptors_for_shader(sctx, sel);
2407 si_update_streamout_state(sctx);
2408 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2409 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2410 }
2411
2412 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2413 {
2414 struct si_context *sctx = (struct si_context *)ctx;
2415 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
2416 struct si_shader_selector *sel = state;
2417
2418 /* skip if supplied shader is one already in use */
2419 if (old_sel == sel)
2420 return;
2421
2422 sctx->ps_shader.cso = sel;
2423 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2424
2425 si_update_common_shader_state(sctx);
2426 if (sel) {
2427 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2428 si_update_tess_uses_prim_id(sctx);
2429
2430 if (!old_sel ||
2431 old_sel->info.colors_written != sel->info.colors_written)
2432 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2433
2434 if (sctx->screen->has_out_of_order_rast &&
2435 (!old_sel ||
2436 old_sel->info.writes_memory != sel->info.writes_memory ||
2437 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
2438 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
2439 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2440 }
2441 si_set_active_descriptors_for_shader(sctx, sel);
2442 }
2443
2444 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2445 {
2446 if (shader->is_optimized) {
2447 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
2448 &shader->optimized_ready);
2449 util_queue_fence_destroy(&shader->optimized_ready);
2450 }
2451
2452 if (shader->pm4) {
2453 switch (shader->selector->type) {
2454 case PIPE_SHADER_VERTEX:
2455 if (shader->key.as_ls) {
2456 assert(sctx->b.chip_class <= VI);
2457 si_pm4_delete_state(sctx, ls, shader->pm4);
2458 } else if (shader->key.as_es) {
2459 assert(sctx->b.chip_class <= VI);
2460 si_pm4_delete_state(sctx, es, shader->pm4);
2461 } else {
2462 si_pm4_delete_state(sctx, vs, shader->pm4);
2463 }
2464 break;
2465 case PIPE_SHADER_TESS_CTRL:
2466 si_pm4_delete_state(sctx, hs, shader->pm4);
2467 break;
2468 case PIPE_SHADER_TESS_EVAL:
2469 if (shader->key.as_es) {
2470 assert(sctx->b.chip_class <= VI);
2471 si_pm4_delete_state(sctx, es, shader->pm4);
2472 } else {
2473 si_pm4_delete_state(sctx, vs, shader->pm4);
2474 }
2475 break;
2476 case PIPE_SHADER_GEOMETRY:
2477 if (shader->is_gs_copy_shader)
2478 si_pm4_delete_state(sctx, vs, shader->pm4);
2479 else
2480 si_pm4_delete_state(sctx, gs, shader->pm4);
2481 break;
2482 case PIPE_SHADER_FRAGMENT:
2483 si_pm4_delete_state(sctx, ps, shader->pm4);
2484 break;
2485 }
2486 }
2487
2488 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2489 si_shader_destroy(shader);
2490 free(shader);
2491 }
2492
2493 void si_destroy_shader_selector(struct si_context *sctx,
2494 struct si_shader_selector *sel)
2495 {
2496 struct si_shader *p = sel->first_variant, *c;
2497 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2498 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2499 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2500 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2501 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2502 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2503 };
2504
2505 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
2506
2507 if (current_shader[sel->type]->cso == sel) {
2508 current_shader[sel->type]->cso = NULL;
2509 current_shader[sel->type]->current = NULL;
2510 }
2511
2512 while (p) {
2513 c = p->next_variant;
2514 si_delete_shader(sctx, p);
2515 p = c;
2516 }
2517
2518 if (sel->main_shader_part)
2519 si_delete_shader(sctx, sel->main_shader_part);
2520 if (sel->main_shader_part_ls)
2521 si_delete_shader(sctx, sel->main_shader_part_ls);
2522 if (sel->main_shader_part_es)
2523 si_delete_shader(sctx, sel->main_shader_part_es);
2524 if (sel->gs_copy_shader)
2525 si_delete_shader(sctx, sel->gs_copy_shader);
2526
2527 util_queue_fence_destroy(&sel->ready);
2528 mtx_destroy(&sel->mutex);
2529 free(sel->tokens);
2530 ralloc_free(sel->nir);
2531 free(sel);
2532 }
2533
2534 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
2535 {
2536 struct si_context *sctx = (struct si_context *)ctx;
2537 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2538
2539 si_shader_selector_reference(sctx, &sel, NULL);
2540 }
2541
2542 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2543 struct si_shader *vs, unsigned name,
2544 unsigned index, unsigned interpolate)
2545 {
2546 struct tgsi_shader_info *vsinfo = &vs->selector->info;
2547 unsigned j, offset, ps_input_cntl = 0;
2548
2549 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2550 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
2551 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2552
2553 if (name == TGSI_SEMANTIC_PCOORD ||
2554 (name == TGSI_SEMANTIC_TEXCOORD &&
2555 sctx->sprite_coord_enable & (1 << index))) {
2556 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2557 }
2558
2559 for (j = 0; j < vsinfo->num_outputs; j++) {
2560 if (name == vsinfo->output_semantic_name[j] &&
2561 index == vsinfo->output_semantic_index[j]) {
2562 offset = vs->info.vs_output_param_offset[j];
2563
2564 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2565 /* The input is loaded from parameter memory. */
2566 ps_input_cntl |= S_028644_OFFSET(offset);
2567 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2568 if (offset == AC_EXP_PARAM_UNDEFINED) {
2569 /* This can happen with depth-only rendering. */
2570 offset = 0;
2571 } else {
2572 /* The input is a DEFAULT_VAL constant. */
2573 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2574 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2575 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2576 }
2577
2578 ps_input_cntl = S_028644_OFFSET(0x20) |
2579 S_028644_DEFAULT_VAL(offset);
2580 }
2581 break;
2582 }
2583 }
2584
2585 if (name == TGSI_SEMANTIC_PRIMID)
2586 /* PrimID is written after the last output. */
2587 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2588 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2589 /* No corresponding output found, load defaults into input.
2590 * Don't set any other bits.
2591 * (FLAT_SHADE=1 completely changes behavior) */
2592 ps_input_cntl = S_028644_OFFSET(0x20);
2593 /* D3D 9 behaviour. GL is undefined */
2594 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2595 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2596 }
2597 return ps_input_cntl;
2598 }
2599
2600 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
2601 {
2602 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2603 struct si_shader *ps = sctx->ps_shader.current;
2604 struct si_shader *vs = si_get_vs_state(sctx);
2605 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2606 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2607
2608 if (!ps || !ps->selector->info.num_inputs)
2609 return;
2610
2611 num_interp = si_get_ps_num_interp(ps);
2612 assert(num_interp > 0);
2613 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
2614
2615 for (i = 0; i < psinfo->num_inputs; i++) {
2616 unsigned name = psinfo->input_semantic_name[i];
2617 unsigned index = psinfo->input_semantic_index[i];
2618 unsigned interpolate = psinfo->input_interpolate[i];
2619
2620 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
2621 interpolate));
2622 num_written++;
2623
2624 if (name == TGSI_SEMANTIC_COLOR) {
2625 assert(index < ARRAY_SIZE(bcol_interp));
2626 bcol_interp[index] = interpolate;
2627 }
2628 }
2629
2630 if (ps->key.part.ps.prolog.color_two_side) {
2631 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2632
2633 for (i = 0; i < 2; i++) {
2634 if (!(psinfo->colors_read & (0xf << (i * 4))))
2635 continue;
2636
2637 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
2638 i, bcol_interp[i]));
2639 num_written++;
2640 }
2641 }
2642 assert(num_interp == num_written);
2643 }
2644
2645 /**
2646 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2647 */
2648 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2649 {
2650 if (sctx->init_config_has_vgt_flush)
2651 return;
2652
2653 /* Done by Vulkan before VGT_FLUSH. */
2654 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2655 si_pm4_cmd_add(sctx->init_config,
2656 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2657 si_pm4_cmd_end(sctx->init_config, false);
2658
2659 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2660 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2661 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2662 si_pm4_cmd_end(sctx->init_config, false);
2663 sctx->init_config_has_vgt_flush = true;
2664 }
2665
2666 /* Initialize state related to ESGS / GSVS ring buffers */
2667 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2668 {
2669 struct si_shader_selector *es =
2670 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2671 struct si_shader_selector *gs = sctx->gs_shader.cso;
2672 struct si_pm4_state *pm4;
2673
2674 /* Chip constants. */
2675 unsigned num_se = sctx->screen->b.info.max_se;
2676 unsigned wave_size = 64;
2677 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2678 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2679 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2680 */
2681 unsigned gs_vertex_reuse = (sctx->b.chip_class >= VI ? 32 : 16) * num_se;
2682 unsigned alignment = 256 * num_se;
2683 /* The maximum size is 63.999 MB per SE. */
2684 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2685
2686 /* Calculate the minimum size. */
2687 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2688 wave_size, alignment);
2689
2690 /* These are recommended sizes, not minimum sizes. */
2691 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2692 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2693 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2694 gs->max_gsvs_emit_size;
2695
2696 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2697 esgs_ring_size = align(esgs_ring_size, alignment);
2698 gsvs_ring_size = align(gsvs_ring_size, alignment);
2699
2700 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2701 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2702
2703 /* Some rings don't have to be allocated if shaders don't use them.
2704 * (e.g. no varyings between ES and GS or GS and VS)
2705 *
2706 * GFX9 doesn't have the ESGS ring.
2707 */
2708 bool update_esgs = sctx->b.chip_class <= VI &&
2709 esgs_ring_size &&
2710 (!sctx->esgs_ring ||
2711 sctx->esgs_ring->width0 < esgs_ring_size);
2712 bool update_gsvs = gsvs_ring_size &&
2713 (!sctx->gsvs_ring ||
2714 sctx->gsvs_ring->width0 < gsvs_ring_size);
2715
2716 if (!update_esgs && !update_gsvs)
2717 return true;
2718
2719 if (update_esgs) {
2720 pipe_resource_reference(&sctx->esgs_ring, NULL);
2721 sctx->esgs_ring =
2722 si_aligned_buffer_create(sctx->b.b.screen,
2723 R600_RESOURCE_FLAG_UNMAPPABLE,
2724 PIPE_USAGE_DEFAULT,
2725 esgs_ring_size, alignment);
2726 if (!sctx->esgs_ring)
2727 return false;
2728 }
2729
2730 if (update_gsvs) {
2731 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2732 sctx->gsvs_ring =
2733 si_aligned_buffer_create(sctx->b.b.screen,
2734 R600_RESOURCE_FLAG_UNMAPPABLE,
2735 PIPE_USAGE_DEFAULT,
2736 gsvs_ring_size, alignment);
2737 if (!sctx->gsvs_ring)
2738 return false;
2739 }
2740
2741 /* Create the "init_config_gs_rings" state. */
2742 pm4 = CALLOC_STRUCT(si_pm4_state);
2743 if (!pm4)
2744 return false;
2745
2746 if (sctx->b.chip_class >= CIK) {
2747 if (sctx->esgs_ring) {
2748 assert(sctx->b.chip_class <= VI);
2749 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2750 sctx->esgs_ring->width0 / 256);
2751 }
2752 if (sctx->gsvs_ring)
2753 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2754 sctx->gsvs_ring->width0 / 256);
2755 } else {
2756 if (sctx->esgs_ring)
2757 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2758 sctx->esgs_ring->width0 / 256);
2759 if (sctx->gsvs_ring)
2760 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2761 sctx->gsvs_ring->width0 / 256);
2762 }
2763
2764 /* Set the state. */
2765 if (sctx->init_config_gs_rings)
2766 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2767 sctx->init_config_gs_rings = pm4;
2768
2769 if (!sctx->init_config_has_vgt_flush) {
2770 si_init_config_add_vgt_flush(sctx);
2771 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2772 }
2773
2774 /* Flush the context to re-emit both init_config states. */
2775 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2776 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2777
2778 /* Set ring bindings. */
2779 if (sctx->esgs_ring) {
2780 assert(sctx->b.chip_class <= VI);
2781 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
2782 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2783 true, true, 4, 64, 0);
2784 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
2785 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2786 false, false, 0, 0, 0);
2787 }
2788 if (sctx->gsvs_ring) {
2789 si_set_ring_buffer(&sctx->b.b, SI_RING_GSVS,
2790 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2791 false, false, 0, 0, 0);
2792 }
2793
2794 return true;
2795 }
2796
2797 static void si_shader_lock(struct si_shader *shader)
2798 {
2799 mtx_lock(&shader->selector->mutex);
2800 if (shader->previous_stage_sel) {
2801 assert(shader->previous_stage_sel != shader->selector);
2802 mtx_lock(&shader->previous_stage_sel->mutex);
2803 }
2804 }
2805
2806 static void si_shader_unlock(struct si_shader *shader)
2807 {
2808 if (shader->previous_stage_sel)
2809 mtx_unlock(&shader->previous_stage_sel->mutex);
2810 mtx_unlock(&shader->selector->mutex);
2811 }
2812
2813 /**
2814 * @returns 1 if \p sel has been updated to use a new scratch buffer
2815 * 0 if not
2816 * < 0 if there was a failure
2817 */
2818 static int si_update_scratch_buffer(struct si_context *sctx,
2819 struct si_shader *shader)
2820 {
2821 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2822 int r;
2823
2824 if (!shader)
2825 return 0;
2826
2827 /* This shader doesn't need a scratch buffer */
2828 if (shader->config.scratch_bytes_per_wave == 0)
2829 return 0;
2830
2831 /* Prevent race conditions when updating:
2832 * - si_shader::scratch_bo
2833 * - si_shader::binary::code
2834 * - si_shader::previous_stage::binary::code.
2835 */
2836 si_shader_lock(shader);
2837
2838 /* This shader is already configured to use the current
2839 * scratch buffer. */
2840 if (shader->scratch_bo == sctx->scratch_buffer) {
2841 si_shader_unlock(shader);
2842 return 0;
2843 }
2844
2845 assert(sctx->scratch_buffer);
2846
2847 if (shader->previous_stage)
2848 si_shader_apply_scratch_relocs(shader->previous_stage, scratch_va);
2849
2850 si_shader_apply_scratch_relocs(shader, scratch_va);
2851
2852 /* Replace the shader bo with a new bo that has the relocs applied. */
2853 r = si_shader_binary_upload(sctx->screen, shader);
2854 if (r) {
2855 si_shader_unlock(shader);
2856 return r;
2857 }
2858
2859 /* Update the shader state to use the new shader bo. */
2860 si_shader_init_pm4_state(sctx->screen, shader);
2861
2862 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2863
2864 si_shader_unlock(shader);
2865 return 1;
2866 }
2867
2868 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2869 {
2870 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2871 }
2872
2873 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2874 {
2875 return shader ? shader->config.scratch_bytes_per_wave : 0;
2876 }
2877
2878 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
2879 {
2880 if (!sctx->tes_shader.cso)
2881 return NULL; /* tessellation disabled */
2882
2883 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
2884 sctx->fixed_func_tcs_shader.current;
2885 }
2886
2887 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2888 {
2889 unsigned bytes = 0;
2890
2891 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2892 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2893 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2894 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2895
2896 if (sctx->tes_shader.cso) {
2897 struct si_shader *tcs = si_get_tcs_current(sctx);
2898
2899 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
2900 }
2901 return bytes;
2902 }
2903
2904 static bool si_update_scratch_relocs(struct si_context *sctx)
2905 {
2906 struct si_shader *tcs = si_get_tcs_current(sctx);
2907 int r;
2908
2909 /* Update the shaders, so that they are using the latest scratch.
2910 * The scratch buffer may have been changed since these shaders were
2911 * last used, so we still need to try to update them, even if they
2912 * require scratch buffers smaller than the current size.
2913 */
2914 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2915 if (r < 0)
2916 return false;
2917 if (r == 1)
2918 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2919
2920 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2921 if (r < 0)
2922 return false;
2923 if (r == 1)
2924 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2925
2926 r = si_update_scratch_buffer(sctx, tcs);
2927 if (r < 0)
2928 return false;
2929 if (r == 1)
2930 si_pm4_bind_state(sctx, hs, tcs->pm4);
2931
2932 /* VS can be bound as LS, ES, or VS. */
2933 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2934 if (r < 0)
2935 return false;
2936 if (r == 1) {
2937 if (sctx->tes_shader.current)
2938 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2939 else if (sctx->gs_shader.current)
2940 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2941 else
2942 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2943 }
2944
2945 /* TES can be bound as ES or VS. */
2946 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2947 if (r < 0)
2948 return false;
2949 if (r == 1) {
2950 if (sctx->gs_shader.current)
2951 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2952 else
2953 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2954 }
2955
2956 return true;
2957 }
2958
2959 static bool si_update_spi_tmpring_size(struct si_context *sctx)
2960 {
2961 unsigned current_scratch_buffer_size =
2962 si_get_current_scratch_buffer_size(sctx);
2963 unsigned scratch_bytes_per_wave =
2964 si_get_max_scratch_bytes_per_wave(sctx);
2965 unsigned scratch_needed_size = scratch_bytes_per_wave *
2966 sctx->scratch_waves;
2967 unsigned spi_tmpring_size;
2968
2969 if (scratch_needed_size > 0) {
2970 if (scratch_needed_size > current_scratch_buffer_size) {
2971 /* Create a bigger scratch buffer */
2972 r600_resource_reference(&sctx->scratch_buffer, NULL);
2973
2974 sctx->scratch_buffer = (struct r600_resource*)
2975 si_aligned_buffer_create(&sctx->screen->b.b,
2976 R600_RESOURCE_FLAG_UNMAPPABLE,
2977 PIPE_USAGE_DEFAULT,
2978 scratch_needed_size, 256);
2979 if (!sctx->scratch_buffer)
2980 return false;
2981
2982 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2983 r600_context_add_resource_size(&sctx->b.b,
2984 &sctx->scratch_buffer->b.b);
2985 }
2986
2987 if (!si_update_scratch_relocs(sctx))
2988 return false;
2989 }
2990
2991 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2992 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
2993 "scratch size should already be aligned correctly.");
2994
2995 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
2996 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
2997 if (spi_tmpring_size != sctx->spi_tmpring_size) {
2998 sctx->spi_tmpring_size = spi_tmpring_size;
2999 si_mark_atom_dirty(sctx, &sctx->scratch_state);
3000 }
3001 return true;
3002 }
3003
3004 static void si_init_tess_factor_ring(struct si_context *sctx)
3005 {
3006 bool double_offchip_buffers = sctx->b.chip_class >= CIK &&
3007 sctx->b.family != CHIP_CARRIZO &&
3008 sctx->b.family != CHIP_STONEY;
3009 /* This must be one less than the maximum number due to a hw limitation.
3010 * Various hardware bugs in SI, CIK, and GFX9 need this.
3011 */
3012 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
3013 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
3014 sctx->screen->b.info.max_se;
3015 unsigned offchip_granularity;
3016
3017 switch (sctx->screen->tess_offchip_block_dw_size) {
3018 default:
3019 assert(0);
3020 /* fall through */
3021 case 8192:
3022 offchip_granularity = V_03093C_X_8K_DWORDS;
3023 break;
3024 case 4096:
3025 offchip_granularity = V_03093C_X_4K_DWORDS;
3026 break;
3027 }
3028
3029 assert(!sctx->tf_ring);
3030 /* Use 64K alignment for both rings, so that we can pass the address
3031 * to shaders as one SGPR containing bits [16:47].
3032 */
3033 sctx->tf_ring = si_aligned_buffer_create(sctx->b.b.screen,
3034 R600_RESOURCE_FLAG_UNMAPPABLE,
3035 PIPE_USAGE_DEFAULT,
3036 32768 * sctx->screen->b.info.max_se,
3037 64 * 1024);
3038 if (!sctx->tf_ring)
3039 return;
3040
3041 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
3042
3043 sctx->tess_offchip_ring =
3044 si_aligned_buffer_create(sctx->b.b.screen,
3045 R600_RESOURCE_FLAG_UNMAPPABLE,
3046 PIPE_USAGE_DEFAULT,
3047 max_offchip_buffers *
3048 sctx->screen->tess_offchip_block_dw_size * 4,
3049 64 * 1024);
3050 if (!sctx->tess_offchip_ring)
3051 return;
3052
3053 si_init_config_add_vgt_flush(sctx);
3054
3055 uint64_t offchip_va = r600_resource(sctx->tess_offchip_ring)->gpu_address;
3056 uint64_t factor_va = r600_resource(sctx->tf_ring)->gpu_address;
3057 assert((offchip_va & 0xffff) == 0);
3058 assert((factor_va & 0xffff) == 0);
3059
3060 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_offchip_ring),
3061 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3062 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tf_ring),
3063 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3064
3065 /* Append these registers to the init config state. */
3066 if (sctx->b.chip_class >= CIK) {
3067 if (sctx->b.chip_class >= VI)
3068 --max_offchip_buffers;
3069
3070 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3071 S_030938_SIZE(sctx->tf_ring->width0 / 4));
3072 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3073 factor_va >> 8);
3074 if (sctx->b.chip_class >= GFX9)
3075 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3076 factor_va >> 40);
3077 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3078 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
3079 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
3080 } else {
3081 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
3082 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3083 S_008988_SIZE(sctx->tf_ring->width0 / 4));
3084 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3085 factor_va >> 8);
3086 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3087 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
3088 }
3089
3090 if (sctx->b.chip_class >= GFX9) {
3091 si_pm4_set_reg(sctx->init_config,
3092 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
3093 GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
3094 offchip_va >> 16);
3095 si_pm4_set_reg(sctx->init_config,
3096 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
3097 GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
3098 factor_va >> 16);
3099 } else {
3100 si_pm4_set_reg(sctx->init_config,
3101 R_00B430_SPI_SHADER_USER_DATA_HS_0 +
3102 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
3103 offchip_va >> 16);
3104 si_pm4_set_reg(sctx->init_config,
3105 R_00B430_SPI_SHADER_USER_DATA_HS_0 +
3106 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
3107 factor_va >> 16);
3108 }
3109
3110 /* Flush the context to re-emit the init_config state.
3111 * This is done only once in a lifetime of a context.
3112 */
3113 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3114 sctx->b.initial_gfx_cs_size = 0; /* force flush */
3115 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
3116 }
3117
3118 /**
3119 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
3120 * VS passes its outputs to TES directly, so the fixed-function shader only
3121 * has to write TESSOUTER and TESSINNER.
3122 */
3123 static void si_generate_fixed_func_tcs(struct si_context *sctx)
3124 {
3125 struct ureg_src outer, inner;
3126 struct ureg_dst tessouter, tessinner;
3127 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
3128
3129 if (!ureg)
3130 return; /* if we get here, we're screwed */
3131
3132 assert(!sctx->fixed_func_tcs_shader.cso);
3133
3134 outer = ureg_DECL_system_value(ureg,
3135 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
3136 inner = ureg_DECL_system_value(ureg,
3137 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
3138
3139 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
3140 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
3141
3142 ureg_MOV(ureg, tessouter, outer);
3143 ureg_MOV(ureg, tessinner, inner);
3144 ureg_END(ureg);
3145
3146 sctx->fixed_func_tcs_shader.cso =
3147 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
3148 }
3149
3150 static void si_update_vgt_shader_config(struct si_context *sctx)
3151 {
3152 /* Calculate the index of the config.
3153 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3154 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
3155 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
3156
3157 if (!*pm4) {
3158 uint32_t stages = 0;
3159
3160 *pm4 = CALLOC_STRUCT(si_pm4_state);
3161
3162 if (sctx->tes_shader.cso) {
3163 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3164 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3165
3166 if (sctx->gs_shader.cso)
3167 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3168 S_028B54_GS_EN(1) |
3169 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3170 else
3171 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3172 } else if (sctx->gs_shader.cso) {
3173 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3174 S_028B54_GS_EN(1) |
3175 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3176 }
3177
3178 if (sctx->b.chip_class >= GFX9)
3179 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3180
3181 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3182 }
3183 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3184 }
3185
3186 bool si_update_shaders(struct si_context *sctx)
3187 {
3188 struct pipe_context *ctx = (struct pipe_context*)sctx;
3189 struct si_compiler_ctx_state compiler_state;
3190 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3191 struct si_shader *old_vs = si_get_vs_state(sctx);
3192 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3193 struct si_shader *old_ps = sctx->ps_shader.current;
3194 unsigned old_spi_shader_col_format =
3195 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3196 int r;
3197
3198 compiler_state.tm = sctx->tm;
3199 compiler_state.debug = sctx->b.debug;
3200 compiler_state.is_debug_context = sctx->is_debug;
3201
3202 /* Update stages before GS. */
3203 if (sctx->tes_shader.cso) {
3204 if (!sctx->tf_ring) {
3205 si_init_tess_factor_ring(sctx);
3206 if (!sctx->tf_ring)
3207 return false;
3208 }
3209
3210 /* VS as LS */
3211 if (sctx->b.chip_class <= VI) {
3212 r = si_shader_select(ctx, &sctx->vs_shader,
3213 &compiler_state);
3214 if (r)
3215 return false;
3216 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3217 }
3218
3219 if (sctx->tcs_shader.cso) {
3220 r = si_shader_select(ctx, &sctx->tcs_shader,
3221 &compiler_state);
3222 if (r)
3223 return false;
3224 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3225 } else {
3226 if (!sctx->fixed_func_tcs_shader.cso) {
3227 si_generate_fixed_func_tcs(sctx);
3228 if (!sctx->fixed_func_tcs_shader.cso)
3229 return false;
3230 }
3231
3232 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3233 &compiler_state);
3234 if (r)
3235 return false;
3236 si_pm4_bind_state(sctx, hs,
3237 sctx->fixed_func_tcs_shader.current->pm4);
3238 }
3239
3240 if (sctx->gs_shader.cso) {
3241 /* TES as ES */
3242 if (sctx->b.chip_class <= VI) {
3243 r = si_shader_select(ctx, &sctx->tes_shader,
3244 &compiler_state);
3245 if (r)
3246 return false;
3247 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3248 }
3249 } else {
3250 /* TES as VS */
3251 r = si_shader_select(ctx, &sctx->tes_shader,
3252 &compiler_state);
3253 if (r)
3254 return false;
3255 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3256 }
3257 } else if (sctx->gs_shader.cso) {
3258 if (sctx->b.chip_class <= VI) {
3259 /* VS as ES */
3260 r = si_shader_select(ctx, &sctx->vs_shader,
3261 &compiler_state);
3262 if (r)
3263 return false;
3264 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3265
3266 si_pm4_bind_state(sctx, ls, NULL);
3267 si_pm4_bind_state(sctx, hs, NULL);
3268 }
3269 } else {
3270 /* VS as VS */
3271 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
3272 if (r)
3273 return false;
3274 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3275 si_pm4_bind_state(sctx, ls, NULL);
3276 si_pm4_bind_state(sctx, hs, NULL);
3277 }
3278
3279 /* Update GS. */
3280 if (sctx->gs_shader.cso) {
3281 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
3282 if (r)
3283 return false;
3284 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3285 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3286
3287 if (!si_update_gs_ring_buffers(sctx))
3288 return false;
3289 } else {
3290 si_pm4_bind_state(sctx, gs, NULL);
3291 if (sctx->b.chip_class <= VI)
3292 si_pm4_bind_state(sctx, es, NULL);
3293 }
3294
3295 si_update_vgt_shader_config(sctx);
3296
3297 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3298 si_mark_atom_dirty(sctx, &sctx->clip_regs);
3299
3300 if (sctx->ps_shader.cso) {
3301 unsigned db_shader_control;
3302
3303 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
3304 if (r)
3305 return false;
3306 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3307
3308 db_shader_control =
3309 sctx->ps_shader.cso->db_shader_control |
3310 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3311
3312 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3313 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3314 sctx->flatshade != rs->flatshade) {
3315 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3316 sctx->flatshade = rs->flatshade;
3317 si_mark_atom_dirty(sctx, &sctx->spi_map);
3318 }
3319
3320 if (sctx->screen->b.rbplus_allowed &&
3321 si_pm4_state_changed(sctx, ps) &&
3322 (!old_ps ||
3323 old_spi_shader_col_format !=
3324 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3325 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
3326
3327 if (sctx->ps_db_shader_control != db_shader_control) {
3328 sctx->ps_db_shader_control = db_shader_control;
3329 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3330 if (sctx->screen->dpbb_allowed)
3331 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
3332 }
3333
3334 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3335 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3336 si_mark_atom_dirty(sctx, &sctx->msaa_config);
3337
3338 if (sctx->b.chip_class == SI)
3339 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3340
3341 if (sctx->framebuffer.nr_samples <= 1)
3342 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
3343 }
3344 }
3345
3346 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3347 si_pm4_state_enabled_and_changed(sctx, hs) ||
3348 si_pm4_state_enabled_and_changed(sctx, es) ||
3349 si_pm4_state_enabled_and_changed(sctx, gs) ||
3350 si_pm4_state_enabled_and_changed(sctx, vs) ||
3351 si_pm4_state_enabled_and_changed(sctx, ps)) {
3352 if (!si_update_spi_tmpring_size(sctx))
3353 return false;
3354 }
3355
3356 if (sctx->b.chip_class >= CIK) {
3357 if (si_pm4_state_enabled_and_changed(sctx, ls))
3358 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3359 else if (!sctx->queued.named.ls)
3360 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3361
3362 if (si_pm4_state_enabled_and_changed(sctx, hs))
3363 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3364 else if (!sctx->queued.named.hs)
3365 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3366
3367 if (si_pm4_state_enabled_and_changed(sctx, es))
3368 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3369 else if (!sctx->queued.named.es)
3370 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3371
3372 if (si_pm4_state_enabled_and_changed(sctx, gs))
3373 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3374 else if (!sctx->queued.named.gs)
3375 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3376
3377 if (si_pm4_state_enabled_and_changed(sctx, vs))
3378 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3379 else if (!sctx->queued.named.vs)
3380 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3381
3382 if (si_pm4_state_enabled_and_changed(sctx, ps))
3383 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3384 else if (!sctx->queued.named.ps)
3385 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3386 }
3387
3388 sctx->do_update_shaders = false;
3389 return true;
3390 }
3391
3392 static void si_emit_scratch_state(struct si_context *sctx,
3393 struct r600_atom *atom)
3394 {
3395 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3396
3397 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3398 sctx->spi_tmpring_size);
3399
3400 if (sctx->scratch_buffer) {
3401 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
3402 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3403 RADEON_PRIO_SCRATCH_BUFFER);
3404 }
3405 }
3406
3407 void *si_get_blit_vs(struct si_context *sctx, enum blitter_attrib_type type,
3408 unsigned num_layers)
3409 {
3410 struct pipe_context *pipe = &sctx->b.b;
3411 unsigned vs_blit_property;
3412 void **vs;
3413
3414 switch (type) {
3415 case UTIL_BLITTER_ATTRIB_NONE:
3416 vs = num_layers > 1 ? &sctx->vs_blit_pos_layered :
3417 &sctx->vs_blit_pos;
3418 vs_blit_property = SI_VS_BLIT_SGPRS_POS;
3419 break;
3420 case UTIL_BLITTER_ATTRIB_COLOR:
3421 vs = num_layers > 1 ? &sctx->vs_blit_color_layered :
3422 &sctx->vs_blit_color;
3423 vs_blit_property = SI_VS_BLIT_SGPRS_POS_COLOR;
3424 break;
3425 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
3426 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
3427 assert(num_layers == 1);
3428 vs = &sctx->vs_blit_texcoord;
3429 vs_blit_property = SI_VS_BLIT_SGPRS_POS_TEXCOORD;
3430 break;
3431 default:
3432 assert(0);
3433 return NULL;
3434 }
3435 if (*vs)
3436 return *vs;
3437
3438 struct ureg_program *ureg = ureg_create(PIPE_SHADER_VERTEX);
3439 if (!ureg)
3440 return NULL;
3441
3442 /* Tell the shader to load VS inputs from SGPRs: */
3443 ureg_property(ureg, TGSI_PROPERTY_VS_BLIT_SGPRS, vs_blit_property);
3444
3445 /* This is just a pass-through shader with 1-3 MOV instructions. */
3446 ureg_MOV(ureg,
3447 ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0),
3448 ureg_DECL_vs_input(ureg, 0));
3449
3450 if (type != UTIL_BLITTER_ATTRIB_NONE) {
3451 ureg_MOV(ureg,
3452 ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 0),
3453 ureg_DECL_vs_input(ureg, 1));
3454 }
3455
3456 if (num_layers > 1) {
3457 struct ureg_src instance_id =
3458 ureg_DECL_system_value(ureg, TGSI_SEMANTIC_INSTANCEID, 0);
3459 struct ureg_dst layer =
3460 ureg_DECL_output(ureg, TGSI_SEMANTIC_LAYER, 0);
3461
3462 ureg_MOV(ureg, ureg_writemask(layer, TGSI_WRITEMASK_X),
3463 ureg_scalar(instance_id, TGSI_SWIZZLE_X));
3464 }
3465 ureg_END(ureg);
3466
3467 *vs = ureg_create_shader_and_destroy(ureg, pipe);
3468 return *vs;
3469 }
3470
3471 void si_init_shader_functions(struct si_context *sctx)
3472 {
3473 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
3474 si_init_atom(sctx, &sctx->scratch_state, &sctx->atoms.s.scratch_state,
3475 si_emit_scratch_state);
3476
3477 sctx->b.b.create_vs_state = si_create_shader_selector;
3478 sctx->b.b.create_tcs_state = si_create_shader_selector;
3479 sctx->b.b.create_tes_state = si_create_shader_selector;
3480 sctx->b.b.create_gs_state = si_create_shader_selector;
3481 sctx->b.b.create_fs_state = si_create_shader_selector;
3482
3483 sctx->b.b.bind_vs_state = si_bind_vs_shader;
3484 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
3485 sctx->b.b.bind_tes_state = si_bind_tes_shader;
3486 sctx->b.b.bind_gs_state = si_bind_gs_shader;
3487 sctx->b.b.bind_fs_state = si_bind_ps_shader;
3488
3489 sctx->b.b.delete_vs_state = si_delete_shader_selector;
3490 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
3491 sctx->b.b.delete_tes_state = si_delete_shader_selector;
3492 sctx->b.b.delete_gs_state = si_delete_shader_selector;
3493 sctx->b.b.delete_fs_state = si_delete_shader_selector;
3494 }