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radeonsi: fix point sprites
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31
32 #include "tgsi/tgsi_parse.h"
33 #include "util/u_memory.h"
34 #include "util/u_simple_shaders.h"
35
36 static void si_shader_es(struct si_shader *shader)
37 {
38 struct si_pm4_state *pm4;
39 unsigned num_sgprs, num_user_sgprs;
40 unsigned vgpr_comp_cnt;
41 uint64_t va;
42
43 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
44
45 if (pm4 == NULL)
46 return;
47
48 va = shader->bo->gpu_address;
49 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
50
51 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
52
53 num_user_sgprs = SI_VS_NUM_USER_SGPR;
54 num_sgprs = shader->num_sgprs;
55 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
56 if ((num_user_sgprs + 1) > num_sgprs) {
57 /* Last 2 reserved SGPRs are used for VCC */
58 num_sgprs = num_user_sgprs + 1 + 2;
59 }
60 assert(num_sgprs <= 104);
61
62 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
63 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
64 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
65 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
66 S_00B328_SGPRS((num_sgprs - 1) / 8) |
67 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
68 S_00B328_DX10_CLAMP(shader->dx10_clamp_mode));
69 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
70 S_00B32C_USER_SGPR(num_user_sgprs) |
71 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
72 }
73
74 static void si_shader_gs(struct si_shader *shader)
75 {
76 unsigned gs_vert_itemsize = shader->selector->info.num_outputs * (16 >> 2);
77 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
78 unsigned gsvs_itemsize = gs_vert_itemsize * gs_max_vert_out;
79 unsigned cut_mode;
80 struct si_pm4_state *pm4;
81 unsigned num_sgprs, num_user_sgprs;
82 uint64_t va;
83
84 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
85 assert(gsvs_itemsize < (1 << 15));
86
87 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
88
89 if (pm4 == NULL)
90 return;
91
92 if (gs_max_vert_out <= 128) {
93 cut_mode = V_028A40_GS_CUT_128;
94 } else if (gs_max_vert_out <= 256) {
95 cut_mode = V_028A40_GS_CUT_256;
96 } else if (gs_max_vert_out <= 512) {
97 cut_mode = V_028A40_GS_CUT_512;
98 } else {
99 assert(gs_max_vert_out <= 1024);
100 cut_mode = V_028A40_GS_CUT_1024;
101 }
102
103 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
104 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
105 S_028A40_CUT_MODE(cut_mode)|
106 S_028A40_ES_WRITE_OPTIMIZE(1) |
107 S_028A40_GS_WRITE_OPTIMIZE(1));
108
109 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
110 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize);
111 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize);
112
113 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
114 util_bitcount64(shader->selector->gs_used_inputs) * (16 >> 2));
115 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
116
117 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
118
119 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize);
120
121 va = shader->bo->gpu_address;
122 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
123 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
124 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
125
126 num_user_sgprs = SI_GS_NUM_USER_SGPR;
127 num_sgprs = shader->num_sgprs;
128 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
129 if ((num_user_sgprs + 2) > num_sgprs) {
130 /* Last 2 reserved SGPRs are used for VCC */
131 num_sgprs = num_user_sgprs + 2 + 2;
132 }
133 assert(num_sgprs <= 104);
134
135 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
136 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
137 S_00B228_SGPRS((num_sgprs - 1) / 8) |
138 S_00B228_DX10_CLAMP(shader->dx10_clamp_mode));
139 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
140 S_00B22C_USER_SGPR(num_user_sgprs) |
141 S_00B22C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
142 }
143
144 static void si_shader_vs(struct si_shader *shader)
145 {
146 struct tgsi_shader_info *info = &shader->selector->info;
147 struct si_pm4_state *pm4;
148 unsigned num_sgprs, num_user_sgprs;
149 unsigned nparams, i, vgpr_comp_cnt;
150 uint64_t va;
151 unsigned window_space =
152 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
153
154 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
155
156 if (pm4 == NULL)
157 return;
158
159 va = shader->bo->gpu_address;
160 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
161
162 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
163
164 if (shader->is_gs_copy_shader)
165 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
166 else
167 num_user_sgprs = SI_VS_NUM_USER_SGPR;
168
169 num_sgprs = shader->num_sgprs;
170 if (num_user_sgprs > num_sgprs) {
171 /* Last 2 reserved SGPRs are used for VCC */
172 num_sgprs = num_user_sgprs + 2;
173 }
174 assert(num_sgprs <= 104);
175
176 /* Certain attributes (position, psize, etc.) don't count as params.
177 * VS is required to export at least one param and r600_shader_from_tgsi()
178 * takes care of adding a dummy export.
179 */
180 for (nparams = 0, i = 0 ; i < info->num_outputs; i++) {
181 switch (info->output_semantic_name[i]) {
182 case TGSI_SEMANTIC_CLIPVERTEX:
183 case TGSI_SEMANTIC_POSITION:
184 case TGSI_SEMANTIC_PSIZE:
185 break;
186 default:
187 nparams++;
188 }
189 }
190 if (nparams < 1)
191 nparams = 1;
192
193 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
194 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
195
196 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
197 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
198 S_02870C_POS1_EXPORT_FORMAT(shader->nr_pos_exports > 1 ?
199 V_02870C_SPI_SHADER_4COMP :
200 V_02870C_SPI_SHADER_NONE) |
201 S_02870C_POS2_EXPORT_FORMAT(shader->nr_pos_exports > 2 ?
202 V_02870C_SPI_SHADER_4COMP :
203 V_02870C_SPI_SHADER_NONE) |
204 S_02870C_POS3_EXPORT_FORMAT(shader->nr_pos_exports > 3 ?
205 V_02870C_SPI_SHADER_4COMP :
206 V_02870C_SPI_SHADER_NONE));
207
208 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
209 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
210 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
211 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
212 S_00B128_SGPRS((num_sgprs - 1) / 8) |
213 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
214 S_00B128_DX10_CLAMP(shader->dx10_clamp_mode));
215 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
216 S_00B12C_USER_SGPR(num_user_sgprs) |
217 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
218 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
219 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
220 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
221 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
222 S_00B12C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
223 if (window_space)
224 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
225 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
226 else
227 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
228 S_028818_VTX_W0_FMT(1) |
229 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
230 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
231 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
232 }
233
234 static void si_shader_ps(struct si_shader *shader)
235 {
236 struct tgsi_shader_info *info = &shader->selector->info;
237 struct si_pm4_state *pm4;
238 unsigned i, spi_ps_in_control;
239 unsigned num_sgprs, num_user_sgprs;
240 unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
241 uint64_t va;
242
243 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
244
245 if (pm4 == NULL)
246 return;
247
248 for (i = 0; i < info->num_inputs; i++) {
249 switch (info->input_semantic_name[i]) {
250 case TGSI_SEMANTIC_POSITION:
251 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
252 * Possible vaules:
253 * 0 -> Position = pixel center (default)
254 * 1 -> Position = pixel centroid
255 * 2 -> Position = at sample position
256 */
257 switch (info->input_interpolate_loc[i]) {
258 case TGSI_INTERPOLATE_LOC_CENTROID:
259 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
260 break;
261 case TGSI_INTERPOLATE_LOC_SAMPLE:
262 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
263 break;
264 }
265
266 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
267 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
268 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
269 break;
270 }
271 }
272
273 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->nparam) |
274 S_0286D8_BC_OPTIMIZE_DISABLE(1);
275
276 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
277 spi_ps_input_ena = shader->spi_ps_input_ena;
278 /* we need to enable at least one of them, otherwise we hang the GPU */
279 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
280 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
281 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
282 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
283 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
284 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
285 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
286 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
287
288 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
289 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
290 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
291
292 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
293 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
294 shader->spi_shader_col_format);
295 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
296
297 va = shader->bo->gpu_address;
298 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
299 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
300 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
301
302 num_user_sgprs = SI_PS_NUM_USER_SGPR;
303 num_sgprs = shader->num_sgprs;
304 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
305 if ((num_user_sgprs + 1) > num_sgprs) {
306 /* Last 2 reserved SGPRs are used for VCC */
307 num_sgprs = num_user_sgprs + 1 + 2;
308 }
309 assert(num_sgprs <= 104);
310
311 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
312 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
313 S_00B028_SGPRS((num_sgprs - 1) / 8) |
314 S_00B028_DX10_CLAMP(shader->dx10_clamp_mode));
315 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
316 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
317 S_00B02C_USER_SGPR(num_user_sgprs) |
318 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
319 }
320
321 static void si_shader_init_pm4_state(struct si_shader *shader)
322 {
323
324 if (shader->pm4)
325 si_pm4_free_state_simple(shader->pm4);
326
327 switch (shader->selector->type) {
328 case PIPE_SHADER_VERTEX:
329 if (shader->key.vs.as_es)
330 si_shader_es(shader);
331 else
332 si_shader_vs(shader);
333 break;
334 case PIPE_SHADER_GEOMETRY:
335 si_shader_gs(shader);
336 si_shader_vs(shader->gs_copy_shader);
337 break;
338 case PIPE_SHADER_FRAGMENT:
339 si_shader_ps(shader);
340 break;
341 default:
342 assert(0);
343 }
344 }
345
346 /* Compute the key for the hw shader variant */
347 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
348 struct si_shader_selector *sel,
349 union si_shader_key *key)
350 {
351 struct si_context *sctx = (struct si_context *)ctx;
352 memset(key, 0, sizeof(*key));
353
354 if (sel->type == PIPE_SHADER_VERTEX) {
355 unsigned i;
356 if (!sctx->vertex_elements)
357 return;
358
359 for (i = 0; i < sctx->vertex_elements->count; ++i)
360 key->vs.instance_divisors[i] = sctx->vertex_elements->elements[i].instance_divisor;
361
362 if (sctx->gs_shader) {
363 key->vs.as_es = 1;
364 key->vs.gs_used_inputs = sctx->gs_shader->gs_used_inputs;
365 }
366 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
367 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
368 key->ps.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
369 key->ps.export_16bpc = sctx->framebuffer.export_16bpc;
370
371 if (sctx->queued.named.rasterizer) {
372 key->ps.color_two_side = sctx->queued.named.rasterizer->two_side;
373
374 if (sctx->queued.named.blend) {
375 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
376 sctx->queued.named.rasterizer->multisample_enable &&
377 !sctx->framebuffer.cb0_is_integer;
378 }
379
380 key->ps.poly_stipple = sctx->queued.named.rasterizer->poly_stipple_enable &&
381 ((sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
382 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
383 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY);
384 }
385 if (sctx->queued.named.dsa) {
386 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
387
388 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
389 if (sctx->framebuffer.cb0_is_integer)
390 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
391 } else {
392 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
393 }
394 }
395 }
396
397 /* Select the hw shader variant depending on the current state. */
398 static int si_shader_select(struct pipe_context *ctx,
399 struct si_shader_selector *sel)
400 {
401 union si_shader_key key;
402 struct si_shader * shader = NULL;
403 int r;
404
405 si_shader_selector_key(ctx, sel, &key);
406
407 /* Check if we don't need to change anything.
408 * This path is also used for most shaders that don't need multiple
409 * variants, it will cost just a computation of the key and this
410 * test. */
411 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
412 return 0;
413 }
414
415 /* lookup if we have other variants in the list */
416 if (sel->num_shaders > 1) {
417 struct si_shader *p = sel->current, *c = p->next_variant;
418
419 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
420 p = c;
421 c = c->next_variant;
422 }
423
424 if (c) {
425 p->next_variant = c->next_variant;
426 shader = c;
427 }
428 }
429
430 if (shader) {
431 shader->next_variant = sel->current;
432 sel->current = shader;
433 } else {
434 shader = CALLOC(1, sizeof(struct si_shader));
435 shader->selector = sel;
436 shader->key = key;
437
438 shader->next_variant = sel->current;
439 sel->current = shader;
440 r = si_shader_create((struct si_screen*)ctx->screen, shader);
441 if (unlikely(r)) {
442 R600_ERR("Failed to build shader variant (type=%u) %d\n",
443 sel->type, r);
444 sel->current = NULL;
445 FREE(shader);
446 return r;
447 }
448 si_shader_init_pm4_state(shader);
449 sel->num_shaders++;
450 }
451
452 return 0;
453 }
454
455 static void *si_create_shader_state(struct pipe_context *ctx,
456 const struct pipe_shader_state *state,
457 unsigned pipe_shader_type)
458 {
459 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
460 int i;
461
462 sel->type = pipe_shader_type;
463 sel->tokens = tgsi_dup_tokens(state->tokens);
464 sel->so = state->stream_output;
465 tgsi_scan_shader(state->tokens, &sel->info);
466
467 switch (pipe_shader_type) {
468 case PIPE_SHADER_GEOMETRY:
469 sel->gs_output_prim =
470 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
471 sel->gs_max_out_vertices =
472 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
473
474 for (i = 0; i < sel->info.num_inputs; i++) {
475 unsigned name = sel->info.input_semantic_name[i];
476 unsigned index = sel->info.input_semantic_index[i];
477
478 switch (name) {
479 case TGSI_SEMANTIC_PRIMID:
480 break;
481 default:
482 sel->gs_used_inputs |=
483 1llu << si_shader_io_get_unique_index(name, index);
484 }
485 }
486 }
487
488 return sel;
489 }
490
491 static void *si_create_fs_state(struct pipe_context *ctx,
492 const struct pipe_shader_state *state)
493 {
494 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
495 }
496
497 static void *si_create_gs_state(struct pipe_context *ctx,
498 const struct pipe_shader_state *state)
499 {
500 return si_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
501 }
502
503 static void *si_create_vs_state(struct pipe_context *ctx,
504 const struct pipe_shader_state *state)
505 {
506 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
507 }
508
509 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
510 {
511 struct si_context *sctx = (struct si_context *)ctx;
512 struct si_shader_selector *sel = state;
513
514 if (sctx->vs_shader == sel || !sel)
515 return;
516
517 sctx->vs_shader = sel;
518 sctx->clip_regs.dirty = true;
519 }
520
521 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
522 {
523 struct si_context *sctx = (struct si_context *)ctx;
524 struct si_shader_selector *sel = state;
525
526 if (sctx->gs_shader == sel)
527 return;
528
529 sctx->gs_shader = sel;
530 sctx->clip_regs.dirty = true;
531 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
532 }
533
534 static void si_make_dummy_ps(struct si_context *sctx)
535 {
536 if (!sctx->dummy_pixel_shader) {
537 sctx->dummy_pixel_shader =
538 util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
539 TGSI_SEMANTIC_GENERIC,
540 TGSI_INTERPOLATE_CONSTANT);
541 }
542 }
543
544 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
545 {
546 struct si_context *sctx = (struct si_context *)ctx;
547 struct si_shader_selector *sel = state;
548
549 /* skip if supplied shader is one already in use */
550 if (sctx->ps_shader == sel)
551 return;
552
553 /* use a dummy shader if binding a NULL shader */
554 if (!sel) {
555 si_make_dummy_ps(sctx);
556 sel = sctx->dummy_pixel_shader;
557 }
558
559 sctx->ps_shader = sel;
560 }
561
562 static void si_delete_shader_selector(struct pipe_context *ctx,
563 struct si_shader_selector *sel)
564 {
565 struct si_context *sctx = (struct si_context *)ctx;
566 struct si_shader *p = sel->current, *c;
567
568 while (p) {
569 c = p->next_variant;
570 if (sel->type == PIPE_SHADER_GEOMETRY) {
571 si_pm4_delete_state(sctx, gs, p->pm4);
572 si_pm4_delete_state(sctx, vs, p->gs_copy_shader->pm4);
573 } else if (sel->type == PIPE_SHADER_FRAGMENT)
574 si_pm4_delete_state(sctx, ps, p->pm4);
575 else if (p->key.vs.as_es)
576 si_pm4_delete_state(sctx, es, p->pm4);
577 else
578 si_pm4_delete_state(sctx, vs, p->pm4);
579 si_shader_destroy(ctx, p);
580 free(p);
581 p = c;
582 }
583
584 free(sel->tokens);
585 free(sel);
586 }
587
588 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
589 {
590 struct si_context *sctx = (struct si_context *)ctx;
591 struct si_shader_selector *sel = (struct si_shader_selector *)state;
592
593 if (sctx->vs_shader == sel) {
594 sctx->vs_shader = NULL;
595 }
596
597 si_delete_shader_selector(ctx, sel);
598 }
599
600 static void si_delete_gs_shader(struct pipe_context *ctx, void *state)
601 {
602 struct si_context *sctx = (struct si_context *)ctx;
603 struct si_shader_selector *sel = (struct si_shader_selector *)state;
604
605 if (sctx->gs_shader == sel) {
606 sctx->gs_shader = NULL;
607 }
608
609 si_delete_shader_selector(ctx, sel);
610 }
611
612 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
613 {
614 struct si_context *sctx = (struct si_context *)ctx;
615 struct si_shader_selector *sel = (struct si_shader_selector *)state;
616
617 if (sctx->ps_shader == sel) {
618 sctx->ps_shader = NULL;
619 }
620
621 si_delete_shader_selector(ctx, sel);
622 }
623
624 static void si_update_spi_map(struct si_context *sctx)
625 {
626 struct si_shader *ps = sctx->ps_shader->current;
627 struct si_shader *vs = si_get_vs_state(sctx);
628 struct tgsi_shader_info *psinfo = &ps->selector->info;
629 struct tgsi_shader_info *vsinfo = &vs->selector->info;
630 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
631 unsigned i, j, tmp;
632
633 for (i = 0; i < psinfo->num_inputs; i++) {
634 unsigned name = psinfo->input_semantic_name[i];
635 unsigned index = psinfo->input_semantic_index[i];
636 unsigned interpolate = psinfo->input_interpolate[i];
637 unsigned param_offset = ps->ps_input_param_offset[i];
638
639 if (name == TGSI_SEMANTIC_POSITION ||
640 name == TGSI_SEMANTIC_FACE)
641 /* Read from preloaded VGPRs, not parameters */
642 continue;
643
644 bcolor:
645 tmp = 0;
646
647 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
648 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
649 tmp |= S_028644_FLAT_SHADE(1);
650
651 if (name == TGSI_SEMANTIC_GENERIC &&
652 sctx->sprite_coord_enable & (1 << index)) {
653 tmp |= S_028644_PT_SPRITE_TEX(1);
654 }
655
656 for (j = 0; j < vsinfo->num_outputs; j++) {
657 if (name == vsinfo->output_semantic_name[j] &&
658 index == vsinfo->output_semantic_index[j]) {
659 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[j]);
660 break;
661 }
662 }
663
664 if (j == vsinfo->num_outputs & !G_028644_PT_SPRITE_TEX(tmp)) {
665 /* No corresponding output found, load defaults into input.
666 * Don't set any other bits.
667 * (FLAT_SHADE=1 completely changes behavior) */
668 tmp = S_028644_OFFSET(0x20);
669 }
670
671 si_pm4_set_reg(pm4,
672 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
673 tmp);
674
675 if (name == TGSI_SEMANTIC_COLOR &&
676 ps->key.ps.color_two_side) {
677 name = TGSI_SEMANTIC_BCOLOR;
678 param_offset++;
679 goto bcolor;
680 }
681 }
682
683 si_pm4_set_state(sctx, spi, pm4);
684 }
685
686 /* Initialize state related to ESGS / GSVS ring buffers */
687 static void si_init_gs_rings(struct si_context *sctx)
688 {
689 unsigned esgs_ring_size = 128 * 1024;
690 unsigned gsvs_ring_size = 64 * 1024 * 1024;
691
692 assert(!sctx->gs_rings);
693 sctx->gs_rings = CALLOC_STRUCT(si_pm4_state);
694
695 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
696 PIPE_USAGE_DEFAULT, esgs_ring_size);
697
698 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
699 PIPE_USAGE_DEFAULT, gsvs_ring_size);
700
701 if (sctx->b.chip_class >= CIK) {
702 si_pm4_set_reg(sctx->gs_rings, R_030900_VGT_ESGS_RING_SIZE,
703 esgs_ring_size / 256);
704 si_pm4_set_reg(sctx->gs_rings, R_030904_VGT_GSVS_RING_SIZE,
705 gsvs_ring_size / 256);
706 } else {
707 si_pm4_set_reg(sctx->gs_rings, R_0088C8_VGT_ESGS_RING_SIZE,
708 esgs_ring_size / 256);
709 si_pm4_set_reg(sctx->gs_rings, R_0088CC_VGT_GSVS_RING_SIZE,
710 gsvs_ring_size / 256);
711 }
712
713 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
714 sctx->esgs_ring, 0, esgs_ring_size,
715 true, true, 4, 64);
716 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
717 sctx->esgs_ring, 0, esgs_ring_size,
718 false, false, 0, 0);
719 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
720 sctx->gsvs_ring, 0, gsvs_ring_size,
721 false, false, 0, 0);
722 }
723
724 /**
725 * @returns 1 if \p sel has been updated to use a new scratch buffer and 0
726 * otherwise.
727 */
728 static unsigned si_update_scratch_buffer(struct si_context *sctx,
729 struct si_shader_selector *sel)
730 {
731 struct si_shader *shader;
732 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
733 unsigned char *ptr;
734
735 if (!sel)
736 return 0;
737
738 shader = sel->current;
739
740 /* This shader doesn't need a scratch buffer */
741 if (shader->scratch_bytes_per_wave == 0)
742 return 0;
743
744 /* This shader is already configured to use the current
745 * scratch buffer. */
746 if (shader->scratch_bo == sctx->scratch_buffer)
747 return 0;
748
749 assert(sctx->scratch_buffer);
750
751 si_shader_apply_scratch_relocs(sctx, shader, scratch_va);
752
753 /* Replace the shader bo with a new bo that has the relocs applied. */
754 r600_resource_reference(&shader->bo, NULL);
755 shader->bo = si_resource_create_custom(&sctx->screen->b.b, PIPE_USAGE_IMMUTABLE,
756 shader->binary.code_size);
757 ptr = sctx->screen->b.ws->buffer_map(shader->bo->cs_buf, NULL, PIPE_TRANSFER_WRITE);
758 util_memcpy_cpu_to_le32(ptr, shader->binary.code, shader->binary.code_size);
759 sctx->screen->b.ws->buffer_unmap(shader->bo->cs_buf);
760
761 /* Update the shader state to use the new shader bo. */
762 si_shader_init_pm4_state(shader);
763
764 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
765
766 return 1;
767 }
768
769 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
770 {
771 if (!sctx->scratch_buffer)
772 return 0;
773
774 return sctx->scratch_buffer->b.b.width0;
775 }
776
777 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_context *sctx,
778 struct si_shader_selector *sel)
779 {
780 if (!sel)
781 return 0;
782
783 return sel->current->scratch_bytes_per_wave;
784 }
785
786 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
787 {
788
789 return MAX3(si_get_scratch_buffer_bytes_per_wave(sctx, sctx->ps_shader),
790 si_get_scratch_buffer_bytes_per_wave(sctx, sctx->gs_shader),
791 si_get_scratch_buffer_bytes_per_wave(sctx, sctx->vs_shader));
792 }
793
794 static void si_update_spi_tmpring_size(struct si_context *sctx)
795 {
796 unsigned current_scratch_buffer_size =
797 si_get_current_scratch_buffer_size(sctx);
798 unsigned scratch_bytes_per_wave =
799 si_get_max_scratch_bytes_per_wave(sctx);
800 unsigned scratch_needed_size = scratch_bytes_per_wave *
801 sctx->scratch_waves;
802
803 if (scratch_needed_size > 0) {
804
805 if (scratch_needed_size > current_scratch_buffer_size) {
806 /* Create a bigger scratch buffer */
807 pipe_resource_reference(
808 (struct pipe_resource**)&sctx->scratch_buffer,
809 NULL);
810
811 sctx->scratch_buffer =
812 si_resource_create_custom(&sctx->screen->b.b,
813 PIPE_USAGE_DEFAULT, scratch_needed_size);
814 }
815
816 /* Update the shaders, so they are using the latest scratch. The
817 * scratch buffer may have been changed since these shaders were
818 * last used, so we still need to try to update them, even if
819 * they require scratch buffers smaller than the current size.
820 */
821 if (si_update_scratch_buffer(sctx, sctx->ps_shader))
822 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
823 if (si_update_scratch_buffer(sctx, sctx->gs_shader))
824 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
825 if (si_update_scratch_buffer(sctx, sctx->vs_shader))
826 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
827 }
828
829 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
830 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
831 "scratch size should already be aligned correctly.");
832
833 sctx->spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
834 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
835 }
836
837 void si_update_shaders(struct si_context *sctx)
838 {
839 struct pipe_context *ctx = (struct pipe_context*)sctx;
840 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
841
842 if (sctx->gs_shader) {
843 si_shader_select(ctx, sctx->gs_shader);
844 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
845 si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
846
847 sctx->b.streamout.stride_in_dw = sctx->gs_shader->so.stride;
848
849 si_shader_select(ctx, sctx->vs_shader);
850 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
851
852 if (!sctx->gs_rings)
853 si_init_gs_rings(sctx);
854 if (sctx->emitted.named.gs_rings != sctx->gs_rings)
855 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
856 si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
857
858 si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
859 sctx->gsvs_ring,
860 sctx->gs_shader->gs_max_out_vertices *
861 sctx->gs_shader->info.num_outputs * 16,
862 64, true, true, 4, 16);
863
864 if (!sctx->gs_on) {
865 sctx->gs_on = CALLOC_STRUCT(si_pm4_state);
866
867 si_pm4_set_reg(sctx->gs_on, R_028B54_VGT_SHADER_STAGES_EN,
868 S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
869 S_028B54_GS_EN(1) |
870 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER));
871 }
872 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_on);
873 } else {
874 si_shader_select(ctx, sctx->vs_shader);
875 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
876
877 sctx->b.streamout.stride_in_dw = sctx->vs_shader->so.stride;
878
879 if (!sctx->gs_off) {
880 sctx->gs_off = CALLOC_STRUCT(si_pm4_state);
881
882 si_pm4_set_reg(sctx->gs_off, R_028A40_VGT_GS_MODE, 0);
883 si_pm4_set_reg(sctx->gs_off, R_028B54_VGT_SHADER_STAGES_EN, 0);
884 }
885 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_off);
886 si_pm4_bind_state(sctx, gs_rings, NULL);
887 si_pm4_bind_state(sctx, gs, NULL);
888 si_pm4_bind_state(sctx, es, NULL);
889 }
890
891 si_shader_select(ctx, sctx->ps_shader);
892
893 if (!sctx->ps_shader->current) {
894 struct si_shader_selector *sel;
895
896 /* use a dummy shader if compiling the shader (variant) failed */
897 si_make_dummy_ps(sctx);
898 sel = sctx->dummy_pixel_shader;
899 si_shader_select(ctx, sel);
900 sctx->ps_shader->current = sel->current;
901 }
902
903 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
904
905 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
906 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
907 sctx->flatshade != rs->flatshade) {
908 sctx->sprite_coord_enable = rs->sprite_coord_enable;
909 sctx->flatshade = rs->flatshade;
910 si_update_spi_map(sctx);
911 }
912
913 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
914 si_pm4_state_changed(sctx, gs)) {
915 si_update_spi_tmpring_size(sctx);
916 }
917
918 if (sctx->ps_db_shader_control != sctx->ps_shader->current->db_shader_control) {
919 sctx->ps_db_shader_control = sctx->ps_shader->current->db_shader_control;
920 sctx->db_render_state.dirty = true;
921 }
922 }
923
924 void si_init_shader_functions(struct si_context *sctx)
925 {
926 sctx->b.b.create_vs_state = si_create_vs_state;
927 sctx->b.b.create_gs_state = si_create_gs_state;
928 sctx->b.b.create_fs_state = si_create_fs_state;
929
930 sctx->b.b.bind_vs_state = si_bind_vs_shader;
931 sctx->b.b.bind_gs_state = si_bind_gs_shader;
932 sctx->b.b.bind_fs_state = si_bind_ps_shader;
933
934 sctx->b.b.delete_vs_state = si_delete_vs_shader;
935 sctx->b.b.delete_gs_state = si_delete_gs_shader;
936 sctx->b.b.delete_fs_state = si_delete_ps_shader;
937 }