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radeonsi: fix context roll tracking in si_emit_shader_vs
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR key for the shader cache.
45 */
46 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
47 unsigned char ir_sha1_cache_key[20])
48 {
49 struct blob blob = {};
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->nir_binary) {
54 ir_binary = sel->nir_binary;
55 ir_size = sel->nir_size;
56 } else {
57 assert(sel->nir);
58
59 blob_init(&blob);
60 nir_serialize(&blob, sel->nir, true);
61 ir_binary = blob.data;
62 ir_size = blob.size;
63 }
64
65 /* These settings affect the compilation, but they are not derived
66 * from the input shader IR.
67 */
68 unsigned shader_variant_flags = 0;
69
70 if (ngg)
71 shader_variant_flags |= 1 << 0;
72 if (sel->nir)
73 shader_variant_flags |= 1 << 1;
74 if (si_get_wave_size(sel->screen, sel->type, ngg, es) == 32)
75 shader_variant_flags |= 1 << 2;
76 if (sel->force_correct_derivs_after_kill)
77 shader_variant_flags |= 1 << 3;
78
79 struct mesa_sha1 ctx;
80 _mesa_sha1_init(&ctx);
81 _mesa_sha1_update(&ctx, &shader_variant_flags, 4);
82 _mesa_sha1_update(&ctx, ir_binary, ir_size);
83 if (sel->type == PIPE_SHADER_VERTEX ||
84 sel->type == PIPE_SHADER_TESS_EVAL ||
85 sel->type == PIPE_SHADER_GEOMETRY)
86 _mesa_sha1_update(&ctx, &sel->so, sizeof(sel->so));
87 _mesa_sha1_final(&ctx, ir_sha1_cache_key);
88
89 if (ir_binary == blob.data)
90 blob_finish(&blob);
91 }
92
93 /** Copy "data" to "ptr" and return the next dword following copied data. */
94 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
95 {
96 /* data may be NULL if size == 0 */
97 if (size)
98 memcpy(ptr, data, size);
99 ptr += DIV_ROUND_UP(size, 4);
100 return ptr;
101 }
102
103 /** Read data from "ptr". Return the next dword following the data. */
104 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
105 {
106 memcpy(data, ptr, size);
107 ptr += DIV_ROUND_UP(size, 4);
108 return ptr;
109 }
110
111 /**
112 * Write the size as uint followed by the data. Return the next dword
113 * following the copied data.
114 */
115 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
116 {
117 *ptr++ = size;
118 return write_data(ptr, data, size);
119 }
120
121 /**
122 * Read the size as uint followed by the data. Return both via parameters.
123 * Return the next dword following the data.
124 */
125 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
126 {
127 *size = *ptr++;
128 assert(*data == NULL);
129 if (!*size)
130 return ptr;
131 *data = malloc(*size);
132 return read_data(ptr, *data, *size);
133 }
134
135 /**
136 * Return the shader binary in a buffer. The first 4 bytes contain its size
137 * as integer.
138 */
139 static void *si_get_shader_binary(struct si_shader *shader)
140 {
141 /* There is always a size of data followed by the data itself. */
142 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
143 strlen(shader->binary.llvm_ir_string) + 1 : 0;
144
145 /* Refuse to allocate overly large buffers and guard against integer
146 * overflow. */
147 if (shader->binary.elf_size > UINT_MAX / 4 ||
148 llvm_ir_size > UINT_MAX / 4)
149 return NULL;
150
151 unsigned size =
152 4 + /* total size */
153 4 + /* CRC32 of the data below */
154 align(sizeof(shader->config), 4) +
155 align(sizeof(shader->info), 4) +
156 4 + align(shader->binary.elf_size, 4) +
157 4 + align(llvm_ir_size, 4);
158 void *buffer = CALLOC(1, size);
159 uint32_t *ptr = (uint32_t*)buffer;
160
161 if (!buffer)
162 return NULL;
163
164 *ptr++ = size;
165 ptr++; /* CRC32 is calculated at the end. */
166
167 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
168 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
169 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
170 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
171 assert((char *)ptr - (char *)buffer == size);
172
173 /* Compute CRC32. */
174 ptr = (uint32_t*)buffer;
175 ptr++;
176 *ptr = util_hash_crc32(ptr + 1, size - 8);
177
178 return buffer;
179 }
180
181 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
182 {
183 uint32_t *ptr = (uint32_t*)binary;
184 uint32_t size = *ptr++;
185 uint32_t crc32 = *ptr++;
186 unsigned chunk_size;
187 unsigned elf_size;
188
189 if (util_hash_crc32(ptr, size - 8) != crc32) {
190 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
191 return false;
192 }
193
194 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
195 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
196 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
197 &elf_size);
198 shader->binary.elf_size = elf_size;
199 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
200
201 return true;
202 }
203
204 /**
205 * Insert a shader into the cache. It's assumed the shader is not in the cache.
206 * Use si_shader_cache_load_shader before calling this.
207 */
208 void si_shader_cache_insert_shader(struct si_screen *sscreen,
209 unsigned char ir_sha1_cache_key[20],
210 struct si_shader *shader,
211 bool insert_into_disk_cache)
212 {
213 void *hw_binary;
214 struct hash_entry *entry;
215 uint8_t key[CACHE_KEY_SIZE];
216
217 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
218 if (entry)
219 return; /* already added */
220
221 hw_binary = si_get_shader_binary(shader);
222 if (!hw_binary)
223 return;
224
225 if (_mesa_hash_table_insert(sscreen->shader_cache,
226 mem_dup(ir_sha1_cache_key, 20),
227 hw_binary) == NULL) {
228 FREE(hw_binary);
229 return;
230 }
231
232 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
233 disk_cache_compute_key(sscreen->disk_shader_cache,
234 ir_sha1_cache_key, 20, key);
235 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
236 *((uint32_t *) hw_binary), NULL);
237 }
238 }
239
240 bool si_shader_cache_load_shader(struct si_screen *sscreen,
241 unsigned char ir_sha1_cache_key[20],
242 struct si_shader *shader)
243 {
244 struct hash_entry *entry =
245 _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
246 if (!entry) {
247 if (sscreen->disk_shader_cache) {
248 unsigned char sha1[CACHE_KEY_SIZE];
249
250 disk_cache_compute_key(sscreen->disk_shader_cache,
251 ir_sha1_cache_key, 20, sha1);
252
253 size_t binary_size;
254 uint8_t *buffer =
255 disk_cache_get(sscreen->disk_shader_cache,
256 sha1, &binary_size);
257 if (!buffer)
258 return false;
259
260 if (binary_size < sizeof(uint32_t) ||
261 *((uint32_t*)buffer) != binary_size) {
262 /* Something has gone wrong discard the item
263 * from the cache and rebuild/link from
264 * source.
265 */
266 assert(!"Invalid radeonsi shader disk cache "
267 "item!");
268
269 disk_cache_remove(sscreen->disk_shader_cache,
270 sha1);
271 free(buffer);
272
273 return false;
274 }
275
276 if (!si_load_shader_binary(shader, buffer)) {
277 free(buffer);
278 return false;
279 }
280 free(buffer);
281
282 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
283 shader, false);
284 } else {
285 return false;
286 }
287 } else {
288 if (!si_load_shader_binary(shader, entry->data))
289 return false;
290 }
291 p_atomic_inc(&sscreen->num_shader_cache_hits);
292 return true;
293 }
294
295 static uint32_t si_shader_cache_key_hash(const void *key)
296 {
297 /* Take the first dword of SHA1. */
298 return *(uint32_t*)key;
299 }
300
301 static bool si_shader_cache_key_equals(const void *a, const void *b)
302 {
303 /* Compare SHA1s. */
304 return memcmp(a, b, 20) == 0;
305 }
306
307 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
308 {
309 FREE((void*)entry->key);
310 FREE(entry->data);
311 }
312
313 bool si_init_shader_cache(struct si_screen *sscreen)
314 {
315 (void) simple_mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
316 sscreen->shader_cache =
317 _mesa_hash_table_create(NULL,
318 si_shader_cache_key_hash,
319 si_shader_cache_key_equals);
320
321 return sscreen->shader_cache != NULL;
322 }
323
324 void si_destroy_shader_cache(struct si_screen *sscreen)
325 {
326 if (sscreen->shader_cache)
327 _mesa_hash_table_destroy(sscreen->shader_cache,
328 si_destroy_shader_cache_entry);
329 simple_mtx_destroy(&sscreen->shader_cache_mutex);
330 }
331
332 /* SHADER STATES */
333
334 static void si_set_tesseval_regs(struct si_screen *sscreen,
335 const struct si_shader_selector *tes,
336 struct si_pm4_state *pm4)
337 {
338 const struct tgsi_shader_info *info = &tes->info;
339 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
340 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
341 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
342 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
343 unsigned type, partitioning, topology, distribution_mode;
344
345 switch (tes_prim_mode) {
346 case PIPE_PRIM_LINES:
347 type = V_028B6C_TESS_ISOLINE;
348 break;
349 case PIPE_PRIM_TRIANGLES:
350 type = V_028B6C_TESS_TRIANGLE;
351 break;
352 case PIPE_PRIM_QUADS:
353 type = V_028B6C_TESS_QUAD;
354 break;
355 default:
356 assert(0);
357 return;
358 }
359
360 switch (tes_spacing) {
361 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
362 partitioning = V_028B6C_PART_FRAC_ODD;
363 break;
364 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
365 partitioning = V_028B6C_PART_FRAC_EVEN;
366 break;
367 case PIPE_TESS_SPACING_EQUAL:
368 partitioning = V_028B6C_PART_INTEGER;
369 break;
370 default:
371 assert(0);
372 return;
373 }
374
375 if (tes_point_mode)
376 topology = V_028B6C_OUTPUT_POINT;
377 else if (tes_prim_mode == PIPE_PRIM_LINES)
378 topology = V_028B6C_OUTPUT_LINE;
379 else if (tes_vertex_order_cw)
380 /* for some reason, this must be the other way around */
381 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
382 else
383 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
384
385 if (sscreen->info.has_distributed_tess) {
386 if (sscreen->info.family == CHIP_FIJI ||
387 sscreen->info.family >= CHIP_POLARIS10)
388 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
389 else
390 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
391 } else
392 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
393
394 assert(pm4->shader);
395 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
396 S_028B6C_PARTITIONING(partitioning) |
397 S_028B6C_TOPOLOGY(topology) |
398 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
399 }
400
401 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
402 * whether the "fractional odd" tessellation spacing is used.
403 *
404 * Possible VGT configurations and which state should set the register:
405 *
406 * Reg set in | VGT shader configuration | Value
407 * ------------------------------------------------------
408 * VS as VS | VS | 30
409 * VS as ES | ES -> GS -> VS | 30
410 * TES as VS | LS -> HS -> VS | 14 or 30
411 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
412 *
413 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
414 */
415 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
416 struct si_shader_selector *sel,
417 struct si_shader *shader,
418 struct si_pm4_state *pm4)
419 {
420 unsigned type = sel->type;
421
422 if (sscreen->info.family < CHIP_POLARIS10 ||
423 sscreen->info.chip_class >= GFX10)
424 return;
425
426 /* VS as VS, or VS as ES: */
427 if ((type == PIPE_SHADER_VERTEX &&
428 (!shader ||
429 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
430 /* TES as VS, or TES as ES: */
431 type == PIPE_SHADER_TESS_EVAL) {
432 unsigned vtx_reuse_depth = 30;
433
434 if (type == PIPE_SHADER_TESS_EVAL &&
435 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
436 PIPE_TESS_SPACING_FRACTIONAL_ODD)
437 vtx_reuse_depth = 14;
438
439 assert(pm4->shader);
440 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
441 }
442 }
443
444 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
445 {
446 if (shader->pm4)
447 si_pm4_clear_state(shader->pm4);
448 else
449 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
450
451 if (shader->pm4) {
452 shader->pm4->shader = shader;
453 return shader->pm4;
454 } else {
455 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
456 return NULL;
457 }
458 }
459
460 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
461 {
462 /* Add the pointer to VBO descriptors. */
463 return num_always_on_user_sgprs + 1;
464 }
465
466 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
467 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen,
468 struct si_shader *shader, bool legacy_vs_prim_id)
469 {
470 assert(shader->selector->type == PIPE_SHADER_VERTEX ||
471 (shader->previous_stage_sel &&
472 shader->previous_stage_sel->type == PIPE_SHADER_VERTEX));
473
474 /* GFX6-9 LS (VertexID, RelAutoindex, InstanceID / StepRate0(==1), ...).
475 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID, ...)
476 * GFX10 LS (VertexID, RelAutoindex, UserVGPR1, InstanceID).
477 * GFX10 ES,VS (VertexID, UserVGPR0, UserVGPR1 or VSPrimID, UserVGPR2 or InstanceID)
478 */
479 bool is_ls = shader->selector->type == PIPE_SHADER_TESS_CTRL || shader->key.as_ls;
480
481 if (sscreen->info.chip_class >= GFX10 && shader->info.uses_instanceid)
482 return 3;
483 else if ((is_ls && shader->info.uses_instanceid) || legacy_vs_prim_id)
484 return 2;
485 else if (is_ls || shader->info.uses_instanceid)
486 return 1;
487 else
488 return 0;
489 }
490
491 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
492 {
493 struct si_pm4_state *pm4;
494 uint64_t va;
495
496 assert(sscreen->info.chip_class <= GFX8);
497
498 pm4 = si_get_shader_pm4_state(shader);
499 if (!pm4)
500 return;
501
502 va = shader->bo->gpu_address;
503 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
504
505 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
506 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
507
508 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
509 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
510 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen, shader, false)) |
511 S_00B528_DX10_CLAMP(1) |
512 S_00B528_FLOAT_MODE(shader->config.float_mode);
513 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
514 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
515 }
516
517 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
518 {
519 struct si_pm4_state *pm4;
520 uint64_t va;
521
522 pm4 = si_get_shader_pm4_state(shader);
523 if (!pm4)
524 return;
525
526 va = shader->bo->gpu_address;
527 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
528
529 if (sscreen->info.chip_class >= GFX9) {
530 if (sscreen->info.chip_class >= GFX10) {
531 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
532 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
533 } else {
534 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
535 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
536 }
537
538 unsigned num_user_sgprs =
539 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
540
541 shader->config.rsrc2 =
542 S_00B42C_USER_SGPR(num_user_sgprs) |
543 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
544
545 if (sscreen->info.chip_class >= GFX10)
546 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
547 else
548 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
549 } else {
550 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
551 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
552
553 shader->config.rsrc2 =
554 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
555 S_00B42C_OC_LDS_EN(1) |
556 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
557 }
558
559 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
560 S_00B428_VGPRS((shader->config.num_vgprs - 1) /
561 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
562 (sscreen->info.chip_class <= GFX9 ?
563 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
564 S_00B428_DX10_CLAMP(1) |
565 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
566 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
567 S_00B428_FLOAT_MODE(shader->config.float_mode) |
568 S_00B428_LS_VGPR_COMP_CNT(sscreen->info.chip_class >= GFX9 ?
569 si_get_vs_vgpr_comp_cnt(sscreen, shader, false) : 0));
570
571 if (sscreen->info.chip_class <= GFX8) {
572 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
573 shader->config.rsrc2);
574 }
575 }
576
577 static void si_emit_shader_es(struct si_context *sctx)
578 {
579 struct si_shader *shader = sctx->queued.named.es->shader;
580 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
581
582 if (!shader)
583 return;
584
585 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
586 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
587 shader->selector->esgs_itemsize / 4);
588
589 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
590 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
591 SI_TRACKED_VGT_TF_PARAM,
592 shader->vgt_tf_param);
593
594 if (shader->vgt_vertex_reuse_block_cntl)
595 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
596 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
597 shader->vgt_vertex_reuse_block_cntl);
598
599 if (initial_cdw != sctx->gfx_cs->current.cdw)
600 sctx->context_roll = true;
601 }
602
603 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
604 {
605 struct si_pm4_state *pm4;
606 unsigned num_user_sgprs;
607 unsigned vgpr_comp_cnt;
608 uint64_t va;
609 unsigned oc_lds_en;
610
611 assert(sscreen->info.chip_class <= GFX8);
612
613 pm4 = si_get_shader_pm4_state(shader);
614 if (!pm4)
615 return;
616
617 pm4->atom.emit = si_emit_shader_es;
618 va = shader->bo->gpu_address;
619 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
620
621 if (shader->selector->type == PIPE_SHADER_VERTEX) {
622 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
623 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
624 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
625 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
626 num_user_sgprs = SI_TES_NUM_USER_SGPR;
627 } else
628 unreachable("invalid shader selector type");
629
630 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
631
632 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
633 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
634 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
635 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
636 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
637 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
638 S_00B328_DX10_CLAMP(1) |
639 S_00B328_FLOAT_MODE(shader->config.float_mode));
640 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
641 S_00B32C_USER_SGPR(num_user_sgprs) |
642 S_00B32C_OC_LDS_EN(oc_lds_en) |
643 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
644
645 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
646 si_set_tesseval_regs(sscreen, shader->selector, pm4);
647
648 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
649 }
650
651 void gfx9_get_gs_info(struct si_shader_selector *es,
652 struct si_shader_selector *gs,
653 struct gfx9_gs_info *out)
654 {
655 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
656 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
657 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
658 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
659
660 /* All these are in dwords: */
661 /* We can't allow using the whole LDS, because GS waves compete with
662 * other shader stages for LDS space. */
663 const unsigned max_lds_size = 8 * 1024;
664 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
665 unsigned esgs_lds_size;
666
667 /* All these are per subgroup: */
668 const unsigned max_out_prims = 32 * 1024;
669 const unsigned max_es_verts = 255;
670 const unsigned ideal_gs_prims = 64;
671 unsigned max_gs_prims, gs_prims;
672 unsigned min_es_verts, es_verts, worst_case_es_verts;
673
674 if (uses_adjacency || gs_num_invocations > 1)
675 max_gs_prims = 127 / gs_num_invocations;
676 else
677 max_gs_prims = 255;
678
679 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
680 * Make sure we don't go over the maximum value.
681 */
682 if (gs->gs_max_out_vertices > 0) {
683 max_gs_prims = MIN2(max_gs_prims,
684 max_out_prims /
685 (gs->gs_max_out_vertices * gs_num_invocations));
686 }
687 assert(max_gs_prims > 0);
688
689 /* If the primitive has adjacency, halve the number of vertices
690 * that will be reused in multiple primitives.
691 */
692 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
693
694 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
695 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
696
697 /* Compute ESGS LDS size based on the worst case number of ES vertices
698 * needed to create the target number of GS prims per subgroup.
699 */
700 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
701
702 /* If total LDS usage is too big, refactor partitions based on ratio
703 * of ESGS item sizes.
704 */
705 if (esgs_lds_size > max_lds_size) {
706 /* Our target GS Prims Per Subgroup was too large. Calculate
707 * the maximum number of GS Prims Per Subgroup that will fit
708 * into LDS, capped by the maximum that the hardware can support.
709 */
710 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
711 max_gs_prims);
712 assert(gs_prims > 0);
713 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
714 max_es_verts);
715
716 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
717 assert(esgs_lds_size <= max_lds_size);
718 }
719
720 /* Now calculate remaining ESGS information. */
721 if (esgs_lds_size)
722 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
723 else
724 es_verts = max_es_verts;
725
726 /* Vertices for adjacency primitives are not always reused, so restore
727 * it for ES_VERTS_PER_SUBGRP.
728 */
729 min_es_verts = gs->gs_input_verts_per_prim;
730
731 /* For normal primitives, the VGT only checks if they are past the ES
732 * verts per subgroup after allocating a full GS primitive and if they
733 * are, kick off a new subgroup. But if those additional ES verts are
734 * unique (e.g. not reused) we need to make sure there is enough LDS
735 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
736 */
737 es_verts -= min_es_verts - 1;
738
739 out->es_verts_per_subgroup = es_verts;
740 out->gs_prims_per_subgroup = gs_prims;
741 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
742 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
743 gs->gs_max_out_vertices;
744 out->esgs_ring_size = 4 * esgs_lds_size;
745
746 assert(out->max_prims_per_subgroup <= max_out_prims);
747 }
748
749 static void si_emit_shader_gs(struct si_context *sctx)
750 {
751 struct si_shader *shader = sctx->queued.named.gs->shader;
752 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
753
754 if (!shader)
755 return;
756
757 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
758 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
759 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
760 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
761 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
762 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
763 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
764
765 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
766 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
767 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
768 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
769
770 /* R_028B38_VGT_GS_MAX_VERT_OUT */
771 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
772 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
773 shader->ctx_reg.gs.vgt_gs_max_vert_out);
774
775 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
776 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
777 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
778 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
779 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
780 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
781 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
782 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
783
784 /* R_028B90_VGT_GS_INSTANCE_CNT */
785 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
786 SI_TRACKED_VGT_GS_INSTANCE_CNT,
787 shader->ctx_reg.gs.vgt_gs_instance_cnt);
788
789 if (sctx->chip_class >= GFX9) {
790 /* R_028A44_VGT_GS_ONCHIP_CNTL */
791 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
792 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
793 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
794 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
795 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
796 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
797 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
798 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
799 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
800 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
801 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
802
803 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
804 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
805 SI_TRACKED_VGT_TF_PARAM,
806 shader->vgt_tf_param);
807 if (shader->vgt_vertex_reuse_block_cntl)
808 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
809 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
810 shader->vgt_vertex_reuse_block_cntl);
811 }
812
813 if (initial_cdw != sctx->gfx_cs->current.cdw)
814 sctx->context_roll = true;
815 }
816
817 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
818 {
819 struct si_shader_selector *sel = shader->selector;
820 const ubyte *num_components = sel->info.num_stream_output_components;
821 unsigned gs_num_invocations = sel->gs_num_invocations;
822 struct si_pm4_state *pm4;
823 uint64_t va;
824 unsigned max_stream = sel->max_gs_stream;
825 unsigned offset;
826
827 pm4 = si_get_shader_pm4_state(shader);
828 if (!pm4)
829 return;
830
831 pm4->atom.emit = si_emit_shader_gs;
832
833 offset = num_components[0] * sel->gs_max_out_vertices;
834 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
835
836 if (max_stream >= 1)
837 offset += num_components[1] * sel->gs_max_out_vertices;
838 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
839
840 if (max_stream >= 2)
841 offset += num_components[2] * sel->gs_max_out_vertices;
842 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
843
844 if (max_stream >= 3)
845 offset += num_components[3] * sel->gs_max_out_vertices;
846 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
847
848 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
849 assert(offset < (1 << 15));
850
851 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
852
853 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
854 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
855 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
856 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
857
858 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
859 S_028B90_ENABLE(gs_num_invocations > 0);
860
861 va = shader->bo->gpu_address;
862 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
863
864 if (sscreen->info.chip_class >= GFX9) {
865 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
866 unsigned es_type = shader->key.part.gs.es->type;
867 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
868
869 if (es_type == PIPE_SHADER_VERTEX) {
870 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
871 } else if (es_type == PIPE_SHADER_TESS_EVAL)
872 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
873 else
874 unreachable("invalid shader selector type");
875
876 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
877 * VGPR[0:4] are always loaded.
878 */
879 if (sel->info.uses_invocationid)
880 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
881 else if (sel->info.uses_primid)
882 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
883 else if (input_prim >= PIPE_PRIM_TRIANGLES)
884 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
885 else
886 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
887
888 unsigned num_user_sgprs;
889 if (es_type == PIPE_SHADER_VERTEX)
890 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
891 else
892 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
893
894 if (sscreen->info.chip_class >= GFX10) {
895 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
896 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
897 } else {
898 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
899 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
900 }
901
902 uint32_t rsrc1 =
903 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
904 S_00B228_DX10_CLAMP(1) |
905 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
906 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
907 S_00B228_FLOAT_MODE(shader->config.float_mode) |
908 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
909 uint32_t rsrc2 =
910 S_00B22C_USER_SGPR(num_user_sgprs) |
911 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
912 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
913 S_00B22C_LDS_SIZE(shader->config.lds_size) |
914 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
915
916 if (sscreen->info.chip_class >= GFX10) {
917 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
918 } else {
919 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
920 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
921 }
922
923 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
924 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
925
926 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
927 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
928 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
929 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
930 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
931 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
932 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
933 shader->key.part.gs.es->esgs_itemsize / 4;
934
935 if (es_type == PIPE_SHADER_TESS_EVAL)
936 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
937
938 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
939 NULL, pm4);
940 } else {
941 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
942 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
943
944 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
945 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
946 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
947 S_00B228_DX10_CLAMP(1) |
948 S_00B228_FLOAT_MODE(shader->config.float_mode));
949 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
950 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
951 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
952 }
953 }
954
955 /* Common tail code for NGG primitive shaders. */
956 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
957 struct si_shader *shader,
958 unsigned initial_cdw)
959 {
960 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
961 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
962 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
963 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
964 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
965 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
966 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
967 SI_TRACKED_VGT_PRIMITIVEID_EN,
968 shader->ctx_reg.ngg.vgt_primitiveid_en);
969 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
970 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
971 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
972 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
973 SI_TRACKED_VGT_GS_INSTANCE_CNT,
974 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
975 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
976 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
977 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
978 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
979 SI_TRACKED_SPI_VS_OUT_CONFIG,
980 shader->ctx_reg.ngg.spi_vs_out_config);
981 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
982 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
983 shader->ctx_reg.ngg.spi_shader_idx_format,
984 shader->ctx_reg.ngg.spi_shader_pos_format);
985 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
986 SI_TRACKED_PA_CL_VTE_CNTL,
987 shader->ctx_reg.ngg.pa_cl_vte_cntl);
988 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
989 SI_TRACKED_PA_CL_NGG_CNTL,
990 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
991
992 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
993 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
994 shader->pa_cl_vs_out_cntl,
995 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
996
997 if (initial_cdw != sctx->gfx_cs->current.cdw)
998 sctx->context_roll = true;
999 }
1000
1001 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
1002 {
1003 struct si_shader *shader = sctx->queued.named.gs->shader;
1004 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1005
1006 if (!shader)
1007 return;
1008
1009 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1010 }
1011
1012 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1013 {
1014 struct si_shader *shader = sctx->queued.named.gs->shader;
1015 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1016
1017 if (!shader)
1018 return;
1019
1020 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1021 SI_TRACKED_VGT_TF_PARAM,
1022 shader->vgt_tf_param);
1023
1024 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1025 }
1026
1027 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1028 {
1029 struct si_shader *shader = sctx->queued.named.gs->shader;
1030 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1031
1032 if (!shader)
1033 return;
1034
1035 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1036 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1037 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1038
1039 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1040 }
1041
1042 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1043 {
1044 struct si_shader *shader = sctx->queued.named.gs->shader;
1045 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1046
1047 if (!shader)
1048 return;
1049
1050 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1051 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1052 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1053 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1054 SI_TRACKED_VGT_TF_PARAM,
1055 shader->vgt_tf_param);
1056
1057 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1058 }
1059
1060 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1061 {
1062 if (gs->type == PIPE_SHADER_GEOMETRY)
1063 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1064
1065 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1066 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1067 return PIPE_PRIM_POINTS;
1068 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1069 return PIPE_PRIM_LINES;
1070 return PIPE_PRIM_TRIANGLES;
1071 }
1072
1073 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1074 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1075 }
1076
1077 static unsigned si_get_vs_out_cntl(const struct si_shader_selector *sel, bool ngg)
1078 {
1079 bool misc_vec_ena =
1080 sel->info.writes_psize || (sel->info.writes_edgeflag && !ngg) ||
1081 sel->info.writes_layer || sel->info.writes_viewport_index;
1082 return S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
1083 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag && !ngg) |
1084 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
1085 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
1086 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1087 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
1088 }
1089
1090 /**
1091 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1092 * in NGG mode.
1093 */
1094 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1095 {
1096 const struct si_shader_selector *gs_sel = shader->selector;
1097 const struct tgsi_shader_info *gs_info = &gs_sel->info;
1098 enum pipe_shader_type gs_type = shader->selector->type;
1099 const struct si_shader_selector *es_sel =
1100 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1101 const struct tgsi_shader_info *es_info = &es_sel->info;
1102 enum pipe_shader_type es_type = es_sel->type;
1103 unsigned num_user_sgprs;
1104 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1105 uint64_t va;
1106 unsigned window_space =
1107 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1108 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1109 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1110 unsigned input_prim = si_get_input_prim(gs_sel);
1111 bool break_wave_at_eoi = false;
1112 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1113 if (!pm4)
1114 return;
1115
1116 if (es_type == PIPE_SHADER_TESS_EVAL) {
1117 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1118 : gfx10_emit_shader_ngg_tess_nogs;
1119 } else {
1120 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1121 : gfx10_emit_shader_ngg_notess_nogs;
1122 }
1123
1124 va = shader->bo->gpu_address;
1125 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1126
1127 if (es_type == PIPE_SHADER_VERTEX) {
1128 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
1129
1130 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1131 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1132 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1133 } else {
1134 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
1135 }
1136 } else {
1137 assert(es_type == PIPE_SHADER_TESS_EVAL);
1138 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1139 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1140
1141 if (es_enable_prim_id || gs_info->uses_primid)
1142 break_wave_at_eoi = true;
1143 }
1144
1145 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1146 * VGPR[0:4] are always loaded.
1147 *
1148 * Vertex shaders always need to load VGPR3, because they need to
1149 * pass edge flags for decomposed primitives (such as quads) to the PA
1150 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1151 */
1152 if (gs_info->uses_invocationid || gs_type == PIPE_SHADER_VERTEX)
1153 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1154 else if (gs_info->uses_primid)
1155 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1156 else if (input_prim >= PIPE_PRIM_TRIANGLES)
1157 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1158 else
1159 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1160
1161 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1162 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1163 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1164 S_00B228_VGPRS((shader->config.num_vgprs - 1) /
1165 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1166 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1167 S_00B228_DX10_CLAMP(1) |
1168 S_00B228_MEM_ORDERED(1) |
1169 S_00B228_WGP_MODE(1) |
1170 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1171 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1172 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1173 S_00B22C_USER_SGPR(num_user_sgprs) |
1174 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1175 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1176 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1177 S_00B22C_LDS_SIZE(shader->config.lds_size));
1178
1179 nparams = MAX2(shader->info.nr_param_exports, 1);
1180 shader->ctx_reg.ngg.spi_vs_out_config =
1181 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1182 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1183
1184 shader->ctx_reg.ngg.spi_shader_idx_format =
1185 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1186 shader->ctx_reg.ngg.spi_shader_pos_format =
1187 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1188 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1189 V_02870C_SPI_SHADER_4COMP :
1190 V_02870C_SPI_SHADER_NONE) |
1191 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1192 V_02870C_SPI_SHADER_4COMP :
1193 V_02870C_SPI_SHADER_NONE) |
1194 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1195 V_02870C_SPI_SHADER_4COMP :
1196 V_02870C_SPI_SHADER_NONE);
1197
1198 shader->ctx_reg.ngg.vgt_primitiveid_en =
1199 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1200 S_028A84_NGG_DISABLE_PROVOK_REUSE(shader->key.mono.u.vs_export_prim_id ||
1201 gs_sel->info.writes_primid);
1202
1203 if (gs_type == PIPE_SHADER_GEOMETRY) {
1204 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1205 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1206 } else {
1207 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1208 }
1209
1210 if (es_type == PIPE_SHADER_TESS_EVAL)
1211 si_set_tesseval_regs(sscreen, es_sel, pm4);
1212
1213 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1214 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1215 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1216 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1217 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1218 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1219 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1220 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1221 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1222 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1223 S_028B90_CNT(gs_num_invocations) |
1224 S_028B90_ENABLE(gs_num_invocations > 1) |
1225 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1226 shader->ngg.max_vert_out_per_gs_instance);
1227
1228 /* Always output hw-generated edge flags and pass them via the prim
1229 * export to prevent drawing lines on internal edges of decomposed
1230 * primitives (such as quads) with polygon mode = lines. Only VS needs
1231 * this.
1232 */
1233 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1234 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
1235 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(gs_sel, true);
1236
1237 shader->ge_cntl =
1238 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1239 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
1240 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1241
1242 /* Bug workaround for a possible hang with non-tessellation cases.
1243 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1244 *
1245 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1246 */
1247 if ((sscreen->info.family == CHIP_NAVI10 ||
1248 sscreen->info.family == CHIP_NAVI12 ||
1249 sscreen->info.family == CHIP_NAVI14) &&
1250 (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
1251 shader->ngg.hw_max_esverts != 256) {
1252 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1253
1254 if (shader->ngg.hw_max_esverts > 5) {
1255 shader->ge_cntl |=
1256 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1257 }
1258 }
1259
1260 if (window_space) {
1261 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1262 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1263 } else {
1264 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1265 S_028818_VTX_W0_FMT(1) |
1266 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1267 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1268 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1269 }
1270 }
1271
1272 static void si_emit_shader_vs(struct si_context *sctx)
1273 {
1274 struct si_shader *shader = sctx->queued.named.vs->shader;
1275 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1276
1277 if (!shader)
1278 return;
1279
1280 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1281 SI_TRACKED_VGT_GS_MODE,
1282 shader->ctx_reg.vs.vgt_gs_mode);
1283 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1284 SI_TRACKED_VGT_PRIMITIVEID_EN,
1285 shader->ctx_reg.vs.vgt_primitiveid_en);
1286
1287 if (sctx->chip_class <= GFX8) {
1288 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1289 SI_TRACKED_VGT_REUSE_OFF,
1290 shader->ctx_reg.vs.vgt_reuse_off);
1291 }
1292
1293 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1294 SI_TRACKED_SPI_VS_OUT_CONFIG,
1295 shader->ctx_reg.vs.spi_vs_out_config);
1296
1297 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1298 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1299 shader->ctx_reg.vs.spi_shader_pos_format);
1300
1301 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1302 SI_TRACKED_PA_CL_VTE_CNTL,
1303 shader->ctx_reg.vs.pa_cl_vte_cntl);
1304
1305 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1306 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1307 SI_TRACKED_VGT_TF_PARAM,
1308 shader->vgt_tf_param);
1309
1310 if (shader->vgt_vertex_reuse_block_cntl)
1311 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1312 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1313 shader->vgt_vertex_reuse_block_cntl);
1314
1315 /* Required programming for tessellation. (legacy pipeline only) */
1316 if (sctx->chip_class == GFX10 &&
1317 shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1318 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1319 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1320 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1321 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1322 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1323 }
1324
1325 if (sctx->chip_class >= GFX10) {
1326 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1327 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
1328 shader->pa_cl_vs_out_cntl,
1329 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1330 }
1331
1332 if (initial_cdw != sctx->gfx_cs->current.cdw)
1333 sctx->context_roll = true;
1334 }
1335
1336 /**
1337 * Compute the state for \p shader, which will run as a vertex shader on the
1338 * hardware.
1339 *
1340 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1341 * is the copy shader.
1342 */
1343 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1344 struct si_shader_selector *gs)
1345 {
1346 const struct tgsi_shader_info *info = &shader->selector->info;
1347 struct si_pm4_state *pm4;
1348 unsigned num_user_sgprs, vgpr_comp_cnt;
1349 uint64_t va;
1350 unsigned nparams, oc_lds_en;
1351 unsigned window_space =
1352 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1353 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1354
1355 pm4 = si_get_shader_pm4_state(shader);
1356 if (!pm4)
1357 return;
1358
1359 pm4->atom.emit = si_emit_shader_vs;
1360
1361 /* We always write VGT_GS_MODE in the VS state, because every switch
1362 * between different shader pipelines involving a different GS or no
1363 * GS at all involves a switch of the VS (different GS use different
1364 * copy shaders). On the other hand, when the API switches from a GS to
1365 * no GS and then back to the same GS used originally, the GS state is
1366 * not sent again.
1367 */
1368 if (!gs) {
1369 unsigned mode = V_028A40_GS_OFF;
1370
1371 /* PrimID needs GS scenario A. */
1372 if (enable_prim_id)
1373 mode = V_028A40_GS_SCENARIO_A;
1374
1375 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1376 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1377 } else {
1378 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1379 sscreen->info.chip_class);
1380 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1381 }
1382
1383 if (sscreen->info.chip_class <= GFX8) {
1384 /* Reuse needs to be set off if we write oViewport. */
1385 shader->ctx_reg.vs.vgt_reuse_off =
1386 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1387 }
1388
1389 va = shader->bo->gpu_address;
1390 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1391
1392 if (gs) {
1393 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1394 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1395 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1396 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
1397
1398 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1399 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1400 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1401 } else {
1402 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1403 }
1404 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1405 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1406 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1407 } else
1408 unreachable("invalid shader selector type");
1409
1410 /* VS is required to export at least one param. */
1411 nparams = MAX2(shader->info.nr_param_exports, 1);
1412 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1413
1414 if (sscreen->info.chip_class >= GFX10) {
1415 shader->ctx_reg.vs.spi_vs_out_config |=
1416 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1417 }
1418
1419 shader->ctx_reg.vs.spi_shader_pos_format =
1420 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1421 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1422 V_02870C_SPI_SHADER_4COMP :
1423 V_02870C_SPI_SHADER_NONE) |
1424 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1425 V_02870C_SPI_SHADER_4COMP :
1426 V_02870C_SPI_SHADER_NONE) |
1427 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1428 V_02870C_SPI_SHADER_4COMP :
1429 V_02870C_SPI_SHADER_NONE);
1430 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, false);
1431
1432 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1433
1434 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1435 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1436
1437 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
1438 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1439 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1440 S_00B128_DX10_CLAMP(1) |
1441 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1442 S_00B128_FLOAT_MODE(shader->config.float_mode);
1443 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1444 S_00B12C_OC_LDS_EN(oc_lds_en) |
1445 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1446
1447 if (sscreen->info.chip_class <= GFX9)
1448 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1449
1450 if (!sscreen->use_ngg_streamout) {
1451 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1452 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1453 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1454 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1455 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1456 }
1457
1458 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1459 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1460
1461 if (window_space)
1462 shader->ctx_reg.vs.pa_cl_vte_cntl =
1463 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1464 else
1465 shader->ctx_reg.vs.pa_cl_vte_cntl =
1466 S_028818_VTX_W0_FMT(1) |
1467 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1468 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1469 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1470
1471 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1472 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1473
1474 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1475 }
1476
1477 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1478 {
1479 struct tgsi_shader_info *info = &ps->selector->info;
1480 unsigned num_colors = !!(info->colors_read & 0x0f) +
1481 !!(info->colors_read & 0xf0);
1482 unsigned num_interp = ps->selector->info.num_inputs +
1483 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1484
1485 assert(num_interp <= 32);
1486 return MIN2(num_interp, 32);
1487 }
1488
1489 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1490 {
1491 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1492 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1493
1494 /* If the i-th target format is set, all previous target formats must
1495 * be non-zero to avoid hangs.
1496 */
1497 for (i = 0; i < num_targets; i++)
1498 if (!(value & (0xf << (i * 4))))
1499 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1500
1501 return value;
1502 }
1503
1504 static void si_emit_shader_ps(struct si_context *sctx)
1505 {
1506 struct si_shader *shader = sctx->queued.named.ps->shader;
1507 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1508
1509 if (!shader)
1510 return;
1511
1512 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1513 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1514 SI_TRACKED_SPI_PS_INPUT_ENA,
1515 shader->ctx_reg.ps.spi_ps_input_ena,
1516 shader->ctx_reg.ps.spi_ps_input_addr);
1517
1518 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1519 SI_TRACKED_SPI_BARYC_CNTL,
1520 shader->ctx_reg.ps.spi_baryc_cntl);
1521 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1522 SI_TRACKED_SPI_PS_IN_CONTROL,
1523 shader->ctx_reg.ps.spi_ps_in_control);
1524
1525 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1526 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1527 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1528 shader->ctx_reg.ps.spi_shader_z_format,
1529 shader->ctx_reg.ps.spi_shader_col_format);
1530
1531 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1532 SI_TRACKED_CB_SHADER_MASK,
1533 shader->ctx_reg.ps.cb_shader_mask);
1534
1535 if (initial_cdw != sctx->gfx_cs->current.cdw)
1536 sctx->context_roll = true;
1537 }
1538
1539 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1540 {
1541 struct tgsi_shader_info *info = &shader->selector->info;
1542 struct si_pm4_state *pm4;
1543 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1544 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1545 uint64_t va;
1546 unsigned input_ena = shader->config.spi_ps_input_ena;
1547
1548 /* we need to enable at least one of them, otherwise we hang the GPU */
1549 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1550 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1551 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1552 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1553 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1554 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1555 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1556 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1557 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1558 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1559 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1560 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1561 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1562 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1563
1564 /* Validate interpolation optimization flags (read as implications). */
1565 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1566 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1567 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1568 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1569 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1570 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1571 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1572 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1573 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1574 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1575 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1576 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1577 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1578 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1579 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1580 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1581 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1582 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1583
1584 /* Validate cases when the optimizations are off (read as implications). */
1585 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1586 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1587 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1588 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1589 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1590 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1591
1592 pm4 = si_get_shader_pm4_state(shader);
1593 if (!pm4)
1594 return;
1595
1596 pm4->atom.emit = si_emit_shader_ps;
1597
1598 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1599 * Possible vaules:
1600 * 0 -> Position = pixel center
1601 * 1 -> Position = pixel centroid
1602 * 2 -> Position = at sample position
1603 *
1604 * From GLSL 4.5 specification, section 7.1:
1605 * "The variable gl_FragCoord is available as an input variable from
1606 * within fragment shaders and it holds the window relative coordinates
1607 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1608 * value can be for any location within the pixel, or one of the
1609 * fragment samples. The use of centroid does not further restrict
1610 * this value to be inside the current primitive."
1611 *
1612 * Meaning that centroid has no effect and we can return anything within
1613 * the pixel. Thus, return the value at sample position, because that's
1614 * the most accurate one shaders can get.
1615 */
1616 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1617
1618 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1619 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1620 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1621
1622 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1623 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1624
1625 /* Ensure that some export memory is always allocated, for two reasons:
1626 *
1627 * 1) Correctness: The hardware ignores the EXEC mask if no export
1628 * memory is allocated, so KILL and alpha test do not work correctly
1629 * without this.
1630 * 2) Performance: Every shader needs at least a NULL export, even when
1631 * it writes no color/depth output. The NULL export instruction
1632 * stalls without this setting.
1633 *
1634 * Don't add this to CB_SHADER_MASK.
1635 *
1636 * GFX10 supports pixel shaders without exports by setting both
1637 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1638 * instructions if any are present.
1639 */
1640 if ((sscreen->info.chip_class <= GFX9 ||
1641 info->uses_kill ||
1642 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1643 !spi_shader_col_format &&
1644 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1645 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1646
1647 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1648 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1649
1650 /* Set interpolation controls. */
1651 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1652 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1653
1654 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1655 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1656 shader->ctx_reg.ps.spi_shader_z_format =
1657 ac_get_spi_shader_z_format(info->writes_z,
1658 info->writes_stencil,
1659 info->writes_samplemask);
1660 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1661 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1662
1663 va = shader->bo->gpu_address;
1664 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1665 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1666 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1667
1668 uint32_t rsrc1 =
1669 S_00B028_VGPRS((shader->config.num_vgprs - 1) /
1670 (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1671 S_00B028_DX10_CLAMP(1) |
1672 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1673 S_00B028_FLOAT_MODE(shader->config.float_mode);
1674
1675 if (sscreen->info.chip_class < GFX10) {
1676 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1677 }
1678
1679 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1680 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1681 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1682 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1683 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1684 }
1685
1686 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1687 struct si_shader *shader)
1688 {
1689 switch (shader->selector->type) {
1690 case PIPE_SHADER_VERTEX:
1691 if (shader->key.as_ls)
1692 si_shader_ls(sscreen, shader);
1693 else if (shader->key.as_es)
1694 si_shader_es(sscreen, shader);
1695 else if (shader->key.as_ngg)
1696 gfx10_shader_ngg(sscreen, shader);
1697 else
1698 si_shader_vs(sscreen, shader, NULL);
1699 break;
1700 case PIPE_SHADER_TESS_CTRL:
1701 si_shader_hs(sscreen, shader);
1702 break;
1703 case PIPE_SHADER_TESS_EVAL:
1704 if (shader->key.as_es)
1705 si_shader_es(sscreen, shader);
1706 else if (shader->key.as_ngg)
1707 gfx10_shader_ngg(sscreen, shader);
1708 else
1709 si_shader_vs(sscreen, shader, NULL);
1710 break;
1711 case PIPE_SHADER_GEOMETRY:
1712 if (shader->key.as_ngg)
1713 gfx10_shader_ngg(sscreen, shader);
1714 else
1715 si_shader_gs(sscreen, shader);
1716 break;
1717 case PIPE_SHADER_FRAGMENT:
1718 si_shader_ps(sscreen, shader);
1719 break;
1720 default:
1721 assert(0);
1722 }
1723 }
1724
1725 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1726 {
1727 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1728 return sctx->queued.named.dsa->alpha_func;
1729 }
1730
1731 void si_shader_selector_key_vs(struct si_context *sctx,
1732 struct si_shader_selector *vs,
1733 struct si_shader_key *key,
1734 struct si_vs_prolog_bits *prolog_key)
1735 {
1736 if (!sctx->vertex_elements ||
1737 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
1738 return;
1739
1740 struct si_vertex_elements *elts = sctx->vertex_elements;
1741
1742 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1743 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1744 prolog_key->unpack_instance_id_from_vertex_id =
1745 sctx->prim_discard_cs_instancing;
1746
1747 /* Prefer a monolithic shader to allow scheduling divisions around
1748 * VBO loads. */
1749 if (prolog_key->instance_divisor_is_fetched)
1750 key->opt.prefer_mono = 1;
1751
1752 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1753 unsigned count_mask = (1 << count) - 1;
1754 unsigned fix = elts->fix_fetch_always & count_mask;
1755 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1756
1757 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1758 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1759 while (mask) {
1760 unsigned i = u_bit_scan(&mask);
1761 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1762 unsigned vbidx = elts->vertex_buffer_index[i];
1763 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1764 unsigned align_mask = (1 << log_hw_load_size) - 1;
1765 if (vb->buffer_offset & align_mask ||
1766 vb->stride & align_mask) {
1767 fix |= 1 << i;
1768 opencode |= 1 << i;
1769 }
1770 }
1771 }
1772
1773 while (fix) {
1774 unsigned i = u_bit_scan(&fix);
1775 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1776 }
1777 key->mono.vs_fetch_opencode = opencode;
1778 }
1779
1780 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1781 struct si_shader_selector *vs,
1782 struct si_shader_key *key)
1783 {
1784 struct si_shader_selector *ps = sctx->ps_shader.cso;
1785
1786 key->opt.clip_disable =
1787 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1788 (vs->info.clipdist_writemask ||
1789 vs->info.writes_clipvertex) &&
1790 !vs->info.culldist_writemask;
1791
1792 /* Find out if PS is disabled. */
1793 bool ps_disabled = true;
1794 if (ps) {
1795 bool ps_modifies_zs = ps->info.uses_kill ||
1796 ps->info.writes_z ||
1797 ps->info.writes_stencil ||
1798 ps->info.writes_samplemask ||
1799 sctx->queued.named.blend->alpha_to_coverage ||
1800 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1801 unsigned ps_colormask = si_get_total_colormask(sctx);
1802
1803 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1804 (!ps_colormask &&
1805 !ps_modifies_zs &&
1806 !ps->info.writes_memory);
1807 }
1808
1809 /* Find out which VS outputs aren't used by the PS. */
1810 uint64_t outputs_written = vs->outputs_written_before_ps;
1811 uint64_t inputs_read = 0;
1812
1813 /* Ignore outputs that are not passed from VS to PS. */
1814 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1815 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1816 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1817
1818 if (!ps_disabled) {
1819 inputs_read = ps->inputs_read;
1820 }
1821
1822 uint64_t linked = outputs_written & inputs_read;
1823
1824 key->opt.kill_outputs = ~linked & outputs_written;
1825 }
1826
1827 /* Compute the key for the hw shader variant */
1828 static inline void si_shader_selector_key(struct pipe_context *ctx,
1829 struct si_shader_selector *sel,
1830 union si_vgt_stages_key stages_key,
1831 struct si_shader_key *key)
1832 {
1833 struct si_context *sctx = (struct si_context *)ctx;
1834
1835 memset(key, 0, sizeof(*key));
1836
1837 switch (sel->type) {
1838 case PIPE_SHADER_VERTEX:
1839 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1840
1841 if (sctx->tes_shader.cso)
1842 key->as_ls = 1;
1843 else if (sctx->gs_shader.cso) {
1844 key->as_es = 1;
1845 key->as_ngg = stages_key.u.ngg;
1846 } else {
1847 key->as_ngg = stages_key.u.ngg;
1848 si_shader_selector_key_hw_vs(sctx, sel, key);
1849
1850 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1851 key->mono.u.vs_export_prim_id = 1;
1852 }
1853 break;
1854 case PIPE_SHADER_TESS_CTRL:
1855 if (sctx->chip_class >= GFX9) {
1856 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1857 key, &key->part.tcs.ls_prolog);
1858 key->part.tcs.ls = sctx->vs_shader.cso;
1859
1860 /* When the LS VGPR fix is needed, monolithic shaders
1861 * can:
1862 * - avoid initializing EXEC in both the LS prolog
1863 * and the LS main part when !vs_needs_prolog
1864 * - remove the fixup for unused input VGPRs
1865 */
1866 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1867
1868 /* The LS output / HS input layout can be communicated
1869 * directly instead of via user SGPRs for merged LS-HS.
1870 * The LS VGPR fix prefers this too.
1871 */
1872 key->opt.prefer_mono = 1;
1873 }
1874
1875 key->part.tcs.epilog.prim_mode =
1876 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1877 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1878 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1879 key->part.tcs.epilog.tes_reads_tess_factors =
1880 sctx->tes_shader.cso->info.reads_tess_factors;
1881
1882 if (sel == sctx->fixed_func_tcs_shader.cso)
1883 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1884 break;
1885 case PIPE_SHADER_TESS_EVAL:
1886 key->as_ngg = stages_key.u.ngg;
1887
1888 if (sctx->gs_shader.cso)
1889 key->as_es = 1;
1890 else {
1891 si_shader_selector_key_hw_vs(sctx, sel, key);
1892
1893 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1894 key->mono.u.vs_export_prim_id = 1;
1895 }
1896 break;
1897 case PIPE_SHADER_GEOMETRY:
1898 if (sctx->chip_class >= GFX9) {
1899 if (sctx->tes_shader.cso) {
1900 key->part.gs.es = sctx->tes_shader.cso;
1901 } else {
1902 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1903 key, &key->part.gs.vs_prolog);
1904 key->part.gs.es = sctx->vs_shader.cso;
1905 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1906 }
1907
1908 key->as_ngg = stages_key.u.ngg;
1909
1910 /* Merged ES-GS can have unbalanced wave usage.
1911 *
1912 * ES threads are per-vertex, while GS threads are
1913 * per-primitive. So without any amplification, there
1914 * are fewer GS threads than ES threads, which can result
1915 * in empty (no-op) GS waves. With too much amplification,
1916 * there are more GS threads than ES threads, which
1917 * can result in empty (no-op) ES waves.
1918 *
1919 * Non-monolithic shaders are implemented by setting EXEC
1920 * at the beginning of shader parts, and don't jump to
1921 * the end if EXEC is 0.
1922 *
1923 * Monolithic shaders use conditional blocks, so they can
1924 * jump and skip empty waves of ES or GS. So set this to
1925 * always use optimized variants, which are monolithic.
1926 */
1927 key->opt.prefer_mono = 1;
1928 }
1929 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1930 break;
1931 case PIPE_SHADER_FRAGMENT: {
1932 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1933 struct si_state_blend *blend = sctx->queued.named.blend;
1934
1935 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1936 sel->info.colors_written == 0x1)
1937 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1938
1939 /* Select the shader color format based on whether
1940 * blending or alpha are needed.
1941 */
1942 key->part.ps.epilog.spi_shader_col_format =
1943 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1944 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1945 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1946 sctx->framebuffer.spi_shader_col_format_blend) |
1947 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1948 sctx->framebuffer.spi_shader_col_format_alpha) |
1949 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1950 sctx->framebuffer.spi_shader_col_format);
1951 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1952
1953 /* The output for dual source blending should have
1954 * the same format as the first output.
1955 */
1956 if (blend->dual_src_blend) {
1957 key->part.ps.epilog.spi_shader_col_format |=
1958 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1959 }
1960
1961 /* If alpha-to-coverage is enabled, we have to export alpha
1962 * even if there is no color buffer.
1963 */
1964 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1965 blend->alpha_to_coverage)
1966 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1967
1968 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1969 * to the range supported by the type if a channel has less
1970 * than 16 bits and the export format is 16_ABGR.
1971 */
1972 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1973 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1974 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1975 }
1976
1977 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1978 if (!key->part.ps.epilog.last_cbuf) {
1979 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1980 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1981 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1982 }
1983
1984 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1985 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1986
1987 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1988 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1989
1990 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one &&
1991 rs->multisample_enable;
1992
1993 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1994 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1995 (is_line && rs->line_smooth)) &&
1996 sctx->framebuffer.nr_samples <= 1;
1997 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1998
1999 if (sctx->ps_iter_samples > 1 &&
2000 sel->info.reads_samplemask) {
2001 key->part.ps.prolog.samplemask_log_ps_iter =
2002 util_logbase2(sctx->ps_iter_samples);
2003 }
2004
2005 if (rs->force_persample_interp &&
2006 rs->multisample_enable &&
2007 sctx->framebuffer.nr_samples > 1 &&
2008 sctx->ps_iter_samples > 1) {
2009 key->part.ps.prolog.force_persp_sample_interp =
2010 sel->info.uses_persp_center ||
2011 sel->info.uses_persp_centroid;
2012
2013 key->part.ps.prolog.force_linear_sample_interp =
2014 sel->info.uses_linear_center ||
2015 sel->info.uses_linear_centroid;
2016 } else if (rs->multisample_enable &&
2017 sctx->framebuffer.nr_samples > 1) {
2018 key->part.ps.prolog.bc_optimize_for_persp =
2019 sel->info.uses_persp_center &&
2020 sel->info.uses_persp_centroid;
2021 key->part.ps.prolog.bc_optimize_for_linear =
2022 sel->info.uses_linear_center &&
2023 sel->info.uses_linear_centroid;
2024 } else {
2025 /* Make sure SPI doesn't compute more than 1 pair
2026 * of (i,j), which is the optimization here. */
2027 key->part.ps.prolog.force_persp_center_interp =
2028 sel->info.uses_persp_center +
2029 sel->info.uses_persp_centroid +
2030 sel->info.uses_persp_sample > 1;
2031
2032 key->part.ps.prolog.force_linear_center_interp =
2033 sel->info.uses_linear_center +
2034 sel->info.uses_linear_centroid +
2035 sel->info.uses_linear_sample > 1;
2036
2037 if (sel->info.uses_persp_opcode_interp_sample ||
2038 sel->info.uses_linear_opcode_interp_sample)
2039 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2040 }
2041
2042 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2043
2044 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2045 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2046 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2047 struct pipe_resource *tex = cb0->texture;
2048
2049 /* 1D textures are allocated and used as 2D on GFX9. */
2050 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2051 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2052 (tex->target == PIPE_TEXTURE_1D ||
2053 tex->target == PIPE_TEXTURE_1D_ARRAY);
2054 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2055 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2056 tex->target == PIPE_TEXTURE_CUBE ||
2057 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2058 tex->target == PIPE_TEXTURE_3D;
2059 }
2060 break;
2061 }
2062 default:
2063 assert(0);
2064 }
2065
2066 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2067 memset(&key->opt, 0, sizeof(key->opt));
2068 }
2069
2070 static void si_build_shader_variant(struct si_shader *shader,
2071 int thread_index,
2072 bool low_priority)
2073 {
2074 struct si_shader_selector *sel = shader->selector;
2075 struct si_screen *sscreen = sel->screen;
2076 struct ac_llvm_compiler *compiler;
2077 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2078
2079 if (thread_index >= 0) {
2080 if (low_priority) {
2081 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2082 compiler = &sscreen->compiler_lowp[thread_index];
2083 } else {
2084 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2085 compiler = &sscreen->compiler[thread_index];
2086 }
2087 if (!debug->async)
2088 debug = NULL;
2089 } else {
2090 assert(!low_priority);
2091 compiler = shader->compiler_ctx_state.compiler;
2092 }
2093
2094 if (!compiler->passes)
2095 si_init_compiler(sscreen, compiler);
2096
2097 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
2098 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2099 sel->type);
2100 shader->compilation_failed = true;
2101 return;
2102 }
2103
2104 if (shader->compiler_ctx_state.is_debug_context) {
2105 FILE *f = open_memstream(&shader->shader_log,
2106 &shader->shader_log_size);
2107 if (f) {
2108 si_shader_dump(sscreen, shader, NULL, f, false);
2109 fclose(f);
2110 }
2111 }
2112
2113 si_shader_init_pm4_state(sscreen, shader);
2114 }
2115
2116 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2117 {
2118 struct si_shader *shader = (struct si_shader *)job;
2119
2120 assert(thread_index >= 0);
2121
2122 si_build_shader_variant(shader, thread_index, true);
2123 }
2124
2125 static const struct si_shader_key zeroed;
2126
2127 static bool si_check_missing_main_part(struct si_screen *sscreen,
2128 struct si_shader_selector *sel,
2129 struct si_compiler_ctx_state *compiler_state,
2130 struct si_shader_key *key)
2131 {
2132 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2133
2134 if (!*mainp) {
2135 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2136
2137 if (!main_part)
2138 return false;
2139
2140 /* We can leave the fence as permanently signaled because the
2141 * main part becomes visible globally only after it has been
2142 * compiled. */
2143 util_queue_fence_init(&main_part->ready);
2144
2145 main_part->selector = sel;
2146 main_part->key.as_es = key->as_es;
2147 main_part->key.as_ls = key->as_ls;
2148 main_part->key.as_ngg = key->as_ngg;
2149 main_part->is_monolithic = false;
2150
2151 if (si_compile_shader(sscreen, compiler_state->compiler,
2152 main_part, &compiler_state->debug) != 0) {
2153 FREE(main_part);
2154 return false;
2155 }
2156 *mainp = main_part;
2157 }
2158 return true;
2159 }
2160
2161 /**
2162 * Select a shader variant according to the shader key.
2163 *
2164 * \param optimized_or_none If the key describes an optimized shader variant and
2165 * the compilation isn't finished, don't select any
2166 * shader and return an error.
2167 */
2168 int si_shader_select_with_key(struct si_screen *sscreen,
2169 struct si_shader_ctx_state *state,
2170 struct si_compiler_ctx_state *compiler_state,
2171 struct si_shader_key *key,
2172 int thread_index,
2173 bool optimized_or_none)
2174 {
2175 struct si_shader_selector *sel = state->cso;
2176 struct si_shader_selector *previous_stage_sel = NULL;
2177 struct si_shader *current = state->current;
2178 struct si_shader *iter, *shader = NULL;
2179
2180 again:
2181 /* Check if we don't need to change anything.
2182 * This path is also used for most shaders that don't need multiple
2183 * variants, it will cost just a computation of the key and this
2184 * test. */
2185 if (likely(current &&
2186 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2187 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2188 if (current->is_optimized) {
2189 if (optimized_or_none)
2190 return -1;
2191
2192 memset(&key->opt, 0, sizeof(key->opt));
2193 goto current_not_ready;
2194 }
2195
2196 util_queue_fence_wait(&current->ready);
2197 }
2198
2199 return current->compilation_failed ? -1 : 0;
2200 }
2201 current_not_ready:
2202
2203 /* This must be done before the mutex is locked, because async GS
2204 * compilation calls this function too, and therefore must enter
2205 * the mutex first.
2206 *
2207 * Only wait if we are in a draw call. Don't wait if we are
2208 * in a compiler thread.
2209 */
2210 if (thread_index < 0)
2211 util_queue_fence_wait(&sel->ready);
2212
2213 simple_mtx_lock(&sel->mutex);
2214
2215 /* Find the shader variant. */
2216 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2217 /* Don't check the "current" shader. We checked it above. */
2218 if (current != iter &&
2219 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2220 simple_mtx_unlock(&sel->mutex);
2221
2222 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2223 /* If it's an optimized shader and its compilation has
2224 * been started but isn't done, use the unoptimized
2225 * shader so as not to cause a stall due to compilation.
2226 */
2227 if (iter->is_optimized) {
2228 if (optimized_or_none)
2229 return -1;
2230 memset(&key->opt, 0, sizeof(key->opt));
2231 goto again;
2232 }
2233
2234 util_queue_fence_wait(&iter->ready);
2235 }
2236
2237 if (iter->compilation_failed) {
2238 return -1; /* skip the draw call */
2239 }
2240
2241 state->current = iter;
2242 return 0;
2243 }
2244 }
2245
2246 /* Build a new shader. */
2247 shader = CALLOC_STRUCT(si_shader);
2248 if (!shader) {
2249 simple_mtx_unlock(&sel->mutex);
2250 return -ENOMEM;
2251 }
2252
2253 util_queue_fence_init(&shader->ready);
2254
2255 shader->selector = sel;
2256 shader->key = *key;
2257 shader->compiler_ctx_state = *compiler_state;
2258
2259 /* If this is a merged shader, get the first shader's selector. */
2260 if (sscreen->info.chip_class >= GFX9) {
2261 if (sel->type == PIPE_SHADER_TESS_CTRL)
2262 previous_stage_sel = key->part.tcs.ls;
2263 else if (sel->type == PIPE_SHADER_GEOMETRY)
2264 previous_stage_sel = key->part.gs.es;
2265
2266 /* We need to wait for the previous shader. */
2267 if (previous_stage_sel && thread_index < 0)
2268 util_queue_fence_wait(&previous_stage_sel->ready);
2269 }
2270
2271 bool is_pure_monolithic =
2272 sscreen->use_monolithic_shaders ||
2273 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2274
2275 /* Compile the main shader part if it doesn't exist. This can happen
2276 * if the initial guess was wrong.
2277 *
2278 * The prim discard CS doesn't need the main shader part.
2279 */
2280 if (!is_pure_monolithic &&
2281 !key->opt.vs_as_prim_discard_cs) {
2282 bool ok = true;
2283
2284 /* Make sure the main shader part is present. This is needed
2285 * for shaders that can be compiled as VS, LS, or ES, and only
2286 * one of them is compiled at creation.
2287 *
2288 * It is also needed for GS, which can be compiled as non-NGG
2289 * and NGG.
2290 *
2291 * For merged shaders, check that the starting shader's main
2292 * part is present.
2293 */
2294 if (previous_stage_sel) {
2295 struct si_shader_key shader1_key = zeroed;
2296
2297 if (sel->type == PIPE_SHADER_TESS_CTRL) {
2298 shader1_key.as_ls = 1;
2299 } else if (sel->type == PIPE_SHADER_GEOMETRY) {
2300 shader1_key.as_es = 1;
2301 shader1_key.as_ngg = key->as_ngg; /* for Wave32 vs Wave64 */
2302 } else {
2303 assert(0);
2304 }
2305
2306 simple_mtx_lock(&previous_stage_sel->mutex);
2307 ok = si_check_missing_main_part(sscreen,
2308 previous_stage_sel,
2309 compiler_state, &shader1_key);
2310 simple_mtx_unlock(&previous_stage_sel->mutex);
2311 }
2312
2313 if (ok) {
2314 ok = si_check_missing_main_part(sscreen, sel,
2315 compiler_state, key);
2316 }
2317
2318 if (!ok) {
2319 FREE(shader);
2320 simple_mtx_unlock(&sel->mutex);
2321 return -ENOMEM; /* skip the draw call */
2322 }
2323 }
2324
2325 /* Keep the reference to the 1st shader of merged shaders, so that
2326 * Gallium can't destroy it before we destroy the 2nd shader.
2327 *
2328 * Set sctx = NULL, because it's unused if we're not releasing
2329 * the shader, and we don't have any sctx here.
2330 */
2331 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2332 previous_stage_sel);
2333
2334 /* Monolithic-only shaders don't make a distinction between optimized
2335 * and unoptimized. */
2336 shader->is_monolithic =
2337 is_pure_monolithic ||
2338 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2339
2340 /* The prim discard CS is always optimized. */
2341 shader->is_optimized =
2342 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2343 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2344
2345 /* If it's an optimized shader, compile it asynchronously. */
2346 if (shader->is_optimized && thread_index < 0) {
2347 /* Compile it asynchronously. */
2348 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2349 shader, &shader->ready,
2350 si_build_shader_variant_low_priority, NULL,
2351 0);
2352
2353 /* Add only after the ready fence was reset, to guard against a
2354 * race with si_bind_XX_shader. */
2355 if (!sel->last_variant) {
2356 sel->first_variant = shader;
2357 sel->last_variant = shader;
2358 } else {
2359 sel->last_variant->next_variant = shader;
2360 sel->last_variant = shader;
2361 }
2362
2363 /* Use the default (unoptimized) shader for now. */
2364 memset(&key->opt, 0, sizeof(key->opt));
2365 simple_mtx_unlock(&sel->mutex);
2366
2367 if (sscreen->options.sync_compile)
2368 util_queue_fence_wait(&shader->ready);
2369
2370 if (optimized_or_none)
2371 return -1;
2372 goto again;
2373 }
2374
2375 /* Reset the fence before adding to the variant list. */
2376 util_queue_fence_reset(&shader->ready);
2377
2378 if (!sel->last_variant) {
2379 sel->first_variant = shader;
2380 sel->last_variant = shader;
2381 } else {
2382 sel->last_variant->next_variant = shader;
2383 sel->last_variant = shader;
2384 }
2385
2386 simple_mtx_unlock(&sel->mutex);
2387
2388 assert(!shader->is_optimized);
2389 si_build_shader_variant(shader, thread_index, false);
2390
2391 util_queue_fence_signal(&shader->ready);
2392
2393 if (!shader->compilation_failed)
2394 state->current = shader;
2395
2396 return shader->compilation_failed ? -1 : 0;
2397 }
2398
2399 static int si_shader_select(struct pipe_context *ctx,
2400 struct si_shader_ctx_state *state,
2401 union si_vgt_stages_key stages_key,
2402 struct si_compiler_ctx_state *compiler_state)
2403 {
2404 struct si_context *sctx = (struct si_context *)ctx;
2405 struct si_shader_key key;
2406
2407 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2408 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2409 &key, -1, false);
2410 }
2411
2412 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2413 bool streamout,
2414 struct si_shader_key *key)
2415 {
2416 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2417
2418 switch (info->processor) {
2419 case PIPE_SHADER_VERTEX:
2420 switch (next_shader) {
2421 case PIPE_SHADER_GEOMETRY:
2422 key->as_es = 1;
2423 break;
2424 case PIPE_SHADER_TESS_CTRL:
2425 case PIPE_SHADER_TESS_EVAL:
2426 key->as_ls = 1;
2427 break;
2428 default:
2429 /* If POSITION isn't written, it can only be a HW VS
2430 * if streamout is used. If streamout isn't used,
2431 * assume that it's a HW LS. (the next shader is TCS)
2432 * This heuristic is needed for separate shader objects.
2433 */
2434 if (!info->writes_position && !streamout)
2435 key->as_ls = 1;
2436 }
2437 break;
2438
2439 case PIPE_SHADER_TESS_EVAL:
2440 if (next_shader == PIPE_SHADER_GEOMETRY ||
2441 !info->writes_position)
2442 key->as_es = 1;
2443 break;
2444 }
2445 }
2446
2447 /**
2448 * Compile the main shader part or the monolithic shader as part of
2449 * si_shader_selector initialization. Since it can be done asynchronously,
2450 * there is no way to report compile failures to applications.
2451 */
2452 static void si_init_shader_selector_async(void *job, int thread_index)
2453 {
2454 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2455 struct si_screen *sscreen = sel->screen;
2456 struct ac_llvm_compiler *compiler;
2457 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2458
2459 assert(!debug->debug_message || debug->async);
2460 assert(thread_index >= 0);
2461 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2462 compiler = &sscreen->compiler[thread_index];
2463
2464 if (!compiler->passes)
2465 si_init_compiler(sscreen, compiler);
2466
2467 /* Serialize NIR to save memory. Monolithic shader variants
2468 * have to deserialize NIR before compilation.
2469 */
2470 if (sel->nir) {
2471 struct blob blob;
2472 size_t size;
2473
2474 blob_init(&blob);
2475 /* true = remove optional debugging data to increase
2476 * the likehood of getting more shader cache hits.
2477 * It also drops variable names, so we'll save more memory.
2478 */
2479 nir_serialize(&blob, sel->nir, true);
2480 blob_finish_get_buffer(&blob, &sel->nir_binary, &size);
2481 sel->nir_size = size;
2482 }
2483
2484 /* Compile the main shader part for use with a prolog and/or epilog.
2485 * If this fails, the driver will try to compile a monolithic shader
2486 * on demand.
2487 */
2488 if (!sscreen->use_monolithic_shaders) {
2489 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2490 unsigned char ir_sha1_cache_key[20];
2491
2492 if (!shader) {
2493 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2494 return;
2495 }
2496
2497 /* We can leave the fence signaled because use of the default
2498 * main part is guarded by the selector's ready fence. */
2499 util_queue_fence_init(&shader->ready);
2500
2501 shader->selector = sel;
2502 shader->is_monolithic = false;
2503 si_parse_next_shader_property(&sel->info,
2504 sel->so.num_outputs != 0,
2505 &shader->key);
2506
2507 if (sscreen->use_ngg &&
2508 (!sel->so.num_outputs || sscreen->use_ngg_streamout) &&
2509 ((sel->type == PIPE_SHADER_VERTEX && !shader->key.as_ls) ||
2510 sel->type == PIPE_SHADER_TESS_EVAL ||
2511 sel->type == PIPE_SHADER_GEOMETRY))
2512 shader->key.as_ngg = 1;
2513
2514 if (sel->nir) {
2515 si_get_ir_cache_key(sel, shader->key.as_ngg,
2516 shader->key.as_es, ir_sha1_cache_key);
2517 }
2518
2519 /* Try to load the shader from the shader cache. */
2520 simple_mtx_lock(&sscreen->shader_cache_mutex);
2521
2522 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
2523 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2524 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2525 } else {
2526 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2527
2528 /* Compile the shader if it hasn't been loaded from the cache. */
2529 if (si_compile_shader(sscreen, compiler, shader,
2530 debug) != 0) {
2531 FREE(shader);
2532 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2533 return;
2534 }
2535
2536 simple_mtx_lock(&sscreen->shader_cache_mutex);
2537 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
2538 shader, true);
2539 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2540 }
2541
2542 *si_get_main_shader_part(sel, &shader->key) = shader;
2543
2544 /* Unset "outputs_written" flags for outputs converted to
2545 * DEFAULT_VAL, so that later inter-shader optimizations don't
2546 * try to eliminate outputs that don't exist in the final
2547 * shader.
2548 *
2549 * This is only done if non-monolithic shaders are enabled.
2550 */
2551 if ((sel->type == PIPE_SHADER_VERTEX ||
2552 sel->type == PIPE_SHADER_TESS_EVAL) &&
2553 !shader->key.as_ls &&
2554 !shader->key.as_es) {
2555 unsigned i;
2556
2557 for (i = 0; i < sel->info.num_outputs; i++) {
2558 unsigned offset = shader->info.vs_output_param_offset[i];
2559
2560 if (offset <= AC_EXP_PARAM_OFFSET_31)
2561 continue;
2562
2563 unsigned name = sel->info.output_semantic_name[i];
2564 unsigned index = sel->info.output_semantic_index[i];
2565 unsigned id;
2566
2567 switch (name) {
2568 case TGSI_SEMANTIC_GENERIC:
2569 /* don't process indices the function can't handle */
2570 if (index >= SI_MAX_IO_GENERIC)
2571 break;
2572 /* fall through */
2573 default:
2574 id = si_shader_io_get_unique_index(name, index, true);
2575 sel->outputs_written_before_ps &= ~(1ull << id);
2576 break;
2577 case TGSI_SEMANTIC_POSITION: /* ignore these */
2578 case TGSI_SEMANTIC_PSIZE:
2579 case TGSI_SEMANTIC_CLIPVERTEX:
2580 case TGSI_SEMANTIC_EDGEFLAG:
2581 break;
2582 }
2583 }
2584 }
2585 }
2586
2587 /* The GS copy shader is always pre-compiled. */
2588 if (sel->type == PIPE_SHADER_GEOMETRY &&
2589 (!sscreen->use_ngg ||
2590 !sscreen->use_ngg_streamout || /* also for PRIMITIVES_GENERATED */
2591 sel->tess_turns_off_ngg)) {
2592 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2593 if (!sel->gs_copy_shader) {
2594 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2595 return;
2596 }
2597
2598 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2599 }
2600
2601 /* Free NIR. We only keep serialized NIR after this point. */
2602 if (sel->nir) {
2603 ralloc_free(sel->nir);
2604 sel->nir = NULL;
2605 }
2606 }
2607
2608 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2609 struct util_queue_fence *ready_fence,
2610 struct si_compiler_ctx_state *compiler_ctx_state,
2611 void *job, util_queue_execute_func execute)
2612 {
2613 util_queue_fence_init(ready_fence);
2614
2615 struct util_async_debug_callback async_debug;
2616 bool debug =
2617 (sctx->debug.debug_message && !sctx->debug.async) ||
2618 sctx->is_debug ||
2619 si_can_dump_shader(sctx->screen, processor);
2620
2621 if (debug) {
2622 u_async_debug_init(&async_debug);
2623 compiler_ctx_state->debug = async_debug.base;
2624 }
2625
2626 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2627 ready_fence, execute, NULL, 0);
2628
2629 if (debug) {
2630 util_queue_fence_wait(ready_fence);
2631 u_async_debug_drain(&async_debug, &sctx->debug);
2632 u_async_debug_cleanup(&async_debug);
2633 }
2634
2635 if (sctx->screen->options.sync_compile)
2636 util_queue_fence_wait(ready_fence);
2637 }
2638
2639 /* Return descriptor slot usage masks from the given shader info. */
2640 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2641 uint32_t *const_and_shader_buffers,
2642 uint64_t *samplers_and_images)
2643 {
2644 unsigned start, num_shaderbufs, num_constbufs, num_images, num_msaa_images, num_samplers;
2645
2646 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2647 num_constbufs = util_last_bit(info->const_buffers_declared);
2648 /* two 8-byte images share one 16-byte slot */
2649 num_images = align(util_last_bit(info->images_declared), 2);
2650 num_msaa_images = align(util_last_bit(info->msaa_images_declared), 2);
2651 num_samplers = util_last_bit(info->samplers_declared);
2652
2653 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2654 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2655 *const_and_shader_buffers =
2656 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2657
2658 /* The layout is:
2659 * - fmask[last] ... fmask[0] go to [15-last .. 15]
2660 * - image[last] ... image[0] go to [31-last .. 31]
2661 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
2662 *
2663 * FMASKs for images are placed separately, because MSAA images are rare,
2664 * and so we can benefit from a better cache hit rate if we keep image
2665 * descriptors together.
2666 */
2667 if (num_msaa_images)
2668 num_images = SI_NUM_IMAGES + num_msaa_images; /* add FMASK descriptors */
2669
2670 start = si_get_image_slot(num_images - 1) / 2;
2671 *samplers_and_images =
2672 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2673 }
2674
2675 static void *si_create_shader_selector(struct pipe_context *ctx,
2676 const struct pipe_shader_state *state)
2677 {
2678 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2679 struct si_context *sctx = (struct si_context*)ctx;
2680 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2681 int i;
2682
2683 if (!sel)
2684 return NULL;
2685
2686 pipe_reference_init(&sel->reference, 1);
2687 sel->screen = sscreen;
2688 sel->compiler_ctx_state.debug = sctx->debug;
2689 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2690
2691 sel->so = state->stream_output;
2692
2693 if (state->type == PIPE_SHADER_IR_TGSI) {
2694 sel->nir = tgsi_to_nir(state->tokens, ctx->screen);
2695 } else {
2696 assert(state->type == PIPE_SHADER_IR_NIR);
2697 sel->nir = state->ir.nir;
2698 }
2699
2700 si_nir_scan_shader(sel->nir, &sel->info);
2701 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2702 si_nir_adjust_driver_locations(sel->nir);
2703
2704 sel->type = sel->info.processor;
2705 p_atomic_inc(&sscreen->num_shaders_created);
2706 si_get_active_slot_masks(&sel->info,
2707 &sel->active_const_and_shader_buffers,
2708 &sel->active_samplers_and_images);
2709
2710 /* Record which streamout buffers are enabled. */
2711 for (i = 0; i < sel->so.num_outputs; i++) {
2712 sel->enabled_streamout_buffer_mask |=
2713 (1 << sel->so.output[i].output_buffer) <<
2714 (sel->so.output[i].stream * 4);
2715 }
2716
2717 /* The prolog is a no-op if there are no inputs. */
2718 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2719 sel->info.num_inputs &&
2720 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
2721
2722 sel->force_correct_derivs_after_kill =
2723 sel->type == PIPE_SHADER_FRAGMENT &&
2724 sel->info.uses_derivatives &&
2725 sel->info.uses_kill &&
2726 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2727
2728 sel->prim_discard_cs_allowed =
2729 sel->type == PIPE_SHADER_VERTEX &&
2730 !sel->info.uses_bindless_images &&
2731 !sel->info.uses_bindless_samplers &&
2732 !sel->info.writes_memory &&
2733 !sel->info.writes_viewport_index &&
2734 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2735 !sel->so.num_outputs;
2736
2737 switch (sel->type) {
2738 case PIPE_SHADER_GEOMETRY:
2739 sel->gs_output_prim =
2740 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2741
2742 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2743 sel->rast_prim = sel->gs_output_prim;
2744 if (util_rast_prim_is_triangles(sel->rast_prim))
2745 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2746
2747 sel->gs_max_out_vertices =
2748 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2749 sel->gs_num_invocations =
2750 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2751 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2752 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2753 sel->gs_max_out_vertices;
2754
2755 sel->max_gs_stream = 0;
2756 for (i = 0; i < sel->so.num_outputs; i++)
2757 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2758 sel->so.output[i].stream);
2759
2760 sel->gs_input_verts_per_prim =
2761 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2762
2763 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2764 sel->tess_turns_off_ngg =
2765 sscreen->info.chip_class == GFX10 &&
2766 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2767 break;
2768
2769 case PIPE_SHADER_TESS_CTRL:
2770 /* Always reserve space for these. */
2771 sel->patch_outputs_written |=
2772 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2773 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2774 /* fall through */
2775 case PIPE_SHADER_VERTEX:
2776 case PIPE_SHADER_TESS_EVAL:
2777 for (i = 0; i < sel->info.num_outputs; i++) {
2778 unsigned name = sel->info.output_semantic_name[i];
2779 unsigned index = sel->info.output_semantic_index[i];
2780
2781 switch (name) {
2782 case TGSI_SEMANTIC_TESSINNER:
2783 case TGSI_SEMANTIC_TESSOUTER:
2784 case TGSI_SEMANTIC_PATCH:
2785 sel->patch_outputs_written |=
2786 1ull << si_shader_io_get_unique_index_patch(name, index);
2787 break;
2788
2789 case TGSI_SEMANTIC_GENERIC:
2790 /* don't process indices the function can't handle */
2791 if (index >= SI_MAX_IO_GENERIC)
2792 break;
2793 /* fall through */
2794 default:
2795 sel->outputs_written |=
2796 1ull << si_shader_io_get_unique_index(name, index, false);
2797 sel->outputs_written_before_ps |=
2798 1ull << si_shader_io_get_unique_index(name, index, true);
2799 break;
2800 case TGSI_SEMANTIC_EDGEFLAG:
2801 break;
2802 }
2803 }
2804 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2805 sel->lshs_vertex_stride = sel->esgs_itemsize;
2806
2807 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2808 * will start on a different bank. (except for the maximum 32*16).
2809 */
2810 if (sel->lshs_vertex_stride < 32*16)
2811 sel->lshs_vertex_stride += 4;
2812
2813 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2814 * conflicts, i.e. each vertex will start at a different bank.
2815 */
2816 if (sctx->chip_class >= GFX9)
2817 sel->esgs_itemsize += 4;
2818
2819 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2820
2821 /* Only for TES: */
2822 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2823 sel->rast_prim = PIPE_PRIM_POINTS;
2824 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2825 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2826 else
2827 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2828 break;
2829
2830 case PIPE_SHADER_FRAGMENT:
2831 for (i = 0; i < sel->info.num_inputs; i++) {
2832 unsigned name = sel->info.input_semantic_name[i];
2833 unsigned index = sel->info.input_semantic_index[i];
2834
2835 switch (name) {
2836 case TGSI_SEMANTIC_GENERIC:
2837 /* don't process indices the function can't handle */
2838 if (index >= SI_MAX_IO_GENERIC)
2839 break;
2840 /* fall through */
2841 default:
2842 sel->inputs_read |=
2843 1ull << si_shader_io_get_unique_index(name, index, true);
2844 break;
2845 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2846 break;
2847 }
2848 }
2849
2850 for (i = 0; i < 8; i++)
2851 if (sel->info.colors_written & (1 << i))
2852 sel->colors_written_4bit |= 0xf << (4 * i);
2853
2854 for (i = 0; i < sel->info.num_inputs; i++) {
2855 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2856 int index = sel->info.input_semantic_index[i];
2857 sel->color_attr_index[index] = i;
2858 }
2859 }
2860 break;
2861 default:;
2862 }
2863
2864 /* PA_CL_VS_OUT_CNTL */
2865 if (sctx->chip_class <= GFX9)
2866 sel->pa_cl_vs_out_cntl = si_get_vs_out_cntl(sel, false);
2867
2868 sel->clipdist_mask = sel->info.writes_clipvertex ?
2869 SIX_BITS : sel->info.clipdist_writemask;
2870 sel->culldist_mask = sel->info.culldist_writemask <<
2871 sel->info.num_written_clipdistance;
2872
2873 /* DB_SHADER_CONTROL */
2874 sel->db_shader_control =
2875 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2876 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2877 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2878 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2879
2880 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2881 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2882 sel->db_shader_control |=
2883 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2884 break;
2885 case TGSI_FS_DEPTH_LAYOUT_LESS:
2886 sel->db_shader_control |=
2887 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2888 break;
2889 }
2890
2891 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2892 *
2893 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2894 * --|-----------|------------|------------|--------------------|-------------------|-------------
2895 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2896 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2897 * 2 | false | true | n/a | LateZ | 1 | 0
2898 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2899 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2900 *
2901 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2902 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2903 *
2904 * Don't use ReZ without profiling !!!
2905 *
2906 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2907 * shaders.
2908 */
2909 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2910 /* Cases 3, 4. */
2911 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2912 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2913 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2914 } else if (sel->info.writes_memory) {
2915 /* Case 2. */
2916 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2917 S_02880C_EXEC_ON_HIER_FAIL(1);
2918 } else {
2919 /* Case 1. */
2920 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2921 }
2922
2923 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
2924 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2925
2926 (void) simple_mtx_init(&sel->mutex, mtx_plain);
2927
2928 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2929 &sel->compiler_ctx_state, sel,
2930 si_init_shader_selector_async);
2931 return sel;
2932 }
2933
2934 static void si_update_streamout_state(struct si_context *sctx)
2935 {
2936 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2937
2938 if (!shader_with_so)
2939 return;
2940
2941 sctx->streamout.enabled_stream_buffers_mask =
2942 shader_with_so->enabled_streamout_buffer_mask;
2943 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2944 }
2945
2946 static void si_update_clip_regs(struct si_context *sctx,
2947 struct si_shader_selector *old_hw_vs,
2948 struct si_shader *old_hw_vs_variant,
2949 struct si_shader_selector *next_hw_vs,
2950 struct si_shader *next_hw_vs_variant)
2951 {
2952 if (next_hw_vs &&
2953 (!old_hw_vs ||
2954 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2955 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2956 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2957 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2958 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2959 !old_hw_vs_variant ||
2960 !next_hw_vs_variant ||
2961 old_hw_vs_variant->key.opt.clip_disable !=
2962 next_hw_vs_variant->key.opt.clip_disable))
2963 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2964 }
2965
2966 static void si_update_common_shader_state(struct si_context *sctx)
2967 {
2968 sctx->uses_bindless_samplers =
2969 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2970 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2971 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2972 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2973 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2974 sctx->uses_bindless_images =
2975 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2976 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2977 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2978 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2979 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2980 sctx->do_update_shaders = true;
2981 }
2982
2983 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2984 {
2985 struct si_context *sctx = (struct si_context *)ctx;
2986 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2987 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2988 struct si_shader_selector *sel = state;
2989
2990 if (sctx->vs_shader.cso == sel)
2991 return;
2992
2993 sctx->vs_shader.cso = sel;
2994 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2995 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] : 0;
2996
2997 if (si_update_ngg(sctx))
2998 si_shader_change_notify(sctx);
2999
3000 si_update_common_shader_state(sctx);
3001 si_update_vs_viewport_state(sctx);
3002 si_set_active_descriptors_for_shader(sctx, sel);
3003 si_update_streamout_state(sctx);
3004 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3005 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3006 }
3007
3008 static void si_update_tess_uses_prim_id(struct si_context *sctx)
3009 {
3010 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
3011 (sctx->tes_shader.cso &&
3012 sctx->tes_shader.cso->info.uses_primid) ||
3013 (sctx->tcs_shader.cso &&
3014 sctx->tcs_shader.cso->info.uses_primid) ||
3015 (sctx->gs_shader.cso &&
3016 sctx->gs_shader.cso->info.uses_primid) ||
3017 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
3018 sctx->ps_shader.cso->info.uses_primid);
3019 }
3020
3021 bool si_update_ngg(struct si_context *sctx)
3022 {
3023 if (!sctx->screen->use_ngg) {
3024 assert(!sctx->ngg);
3025 return false;
3026 }
3027
3028 bool new_ngg = true;
3029
3030 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
3031 sctx->gs_shader.cso->tess_turns_off_ngg) {
3032 new_ngg = false;
3033 } else if (!sctx->screen->use_ngg_streamout) {
3034 struct si_shader_selector *last = si_get_vs(sctx)->cso;
3035
3036 if ((last && last->so.num_outputs) ||
3037 sctx->streamout.prims_gen_query_enabled)
3038 new_ngg = false;
3039 }
3040
3041 if (new_ngg != sctx->ngg) {
3042 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3043 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3044 * pointers are set.
3045 */
3046 if ((sctx->family == CHIP_NAVI10 ||
3047 sctx->family == CHIP_NAVI12 ||
3048 sctx->family == CHIP_NAVI14) &&
3049 !new_ngg)
3050 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
3051
3052 sctx->ngg = new_ngg;
3053 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3054 return true;
3055 }
3056 return false;
3057 }
3058
3059 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3060 {
3061 struct si_context *sctx = (struct si_context *)ctx;
3062 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3063 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3064 struct si_shader_selector *sel = state;
3065 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3066 bool ngg_changed;
3067
3068 if (sctx->gs_shader.cso == sel)
3069 return;
3070
3071 sctx->gs_shader.cso = sel;
3072 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3073 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3074
3075 si_update_common_shader_state(sctx);
3076 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3077
3078 ngg_changed = si_update_ngg(sctx);
3079 if (ngg_changed || enable_changed)
3080 si_shader_change_notify(sctx);
3081 if (enable_changed) {
3082 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3083 si_update_tess_uses_prim_id(sctx);
3084 }
3085 si_update_vs_viewport_state(sctx);
3086 si_set_active_descriptors_for_shader(sctx, sel);
3087 si_update_streamout_state(sctx);
3088 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3089 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3090 }
3091
3092 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3093 {
3094 struct si_context *sctx = (struct si_context *)ctx;
3095 struct si_shader_selector *sel = state;
3096 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3097
3098 if (sctx->tcs_shader.cso == sel)
3099 return;
3100
3101 sctx->tcs_shader.cso = sel;
3102 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3103 si_update_tess_uses_prim_id(sctx);
3104
3105 si_update_common_shader_state(sctx);
3106
3107 if (enable_changed)
3108 sctx->last_tcs = NULL; /* invalidate derived tess state */
3109
3110 si_set_active_descriptors_for_shader(sctx, sel);
3111 }
3112
3113 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3114 {
3115 struct si_context *sctx = (struct si_context *)ctx;
3116 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3117 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3118 struct si_shader_selector *sel = state;
3119 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3120
3121 if (sctx->tes_shader.cso == sel)
3122 return;
3123
3124 sctx->tes_shader.cso = sel;
3125 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3126 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3127 si_update_tess_uses_prim_id(sctx);
3128
3129 si_update_common_shader_state(sctx);
3130 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3131
3132 bool ngg_changed = si_update_ngg(sctx);
3133 if (ngg_changed || enable_changed)
3134 si_shader_change_notify(sctx);
3135 if (enable_changed)
3136 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3137 si_update_vs_viewport_state(sctx);
3138 si_set_active_descriptors_for_shader(sctx, sel);
3139 si_update_streamout_state(sctx);
3140 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3141 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3142 }
3143
3144 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3145 {
3146 struct si_context *sctx = (struct si_context *)ctx;
3147 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3148 struct si_shader_selector *sel = state;
3149
3150 /* skip if supplied shader is one already in use */
3151 if (old_sel == sel)
3152 return;
3153
3154 sctx->ps_shader.cso = sel;
3155 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3156
3157 si_update_common_shader_state(sctx);
3158 if (sel) {
3159 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3160 si_update_tess_uses_prim_id(sctx);
3161
3162 if (!old_sel ||
3163 old_sel->info.colors_written != sel->info.colors_written)
3164 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3165
3166 if (sctx->screen->has_out_of_order_rast &&
3167 (!old_sel ||
3168 old_sel->info.writes_memory != sel->info.writes_memory ||
3169 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3170 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3171 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3172 }
3173 si_set_active_descriptors_for_shader(sctx, sel);
3174 si_update_ps_colorbuf0_slot(sctx);
3175 }
3176
3177 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3178 {
3179 if (shader->is_optimized) {
3180 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3181 &shader->ready);
3182 }
3183
3184 util_queue_fence_destroy(&shader->ready);
3185
3186 if (shader->pm4) {
3187 /* If destroyed shaders were not unbound, the next compiled
3188 * shader variant could get the same pointer address and so
3189 * binding it to the same shader stage would be considered
3190 * a no-op, causing random behavior.
3191 */
3192 switch (shader->selector->type) {
3193 case PIPE_SHADER_VERTEX:
3194 if (shader->key.as_ls) {
3195 assert(sctx->chip_class <= GFX8);
3196 si_pm4_delete_state(sctx, ls, shader->pm4);
3197 } else if (shader->key.as_es) {
3198 assert(sctx->chip_class <= GFX8);
3199 si_pm4_delete_state(sctx, es, shader->pm4);
3200 } else if (shader->key.as_ngg) {
3201 si_pm4_delete_state(sctx, gs, shader->pm4);
3202 } else {
3203 si_pm4_delete_state(sctx, vs, shader->pm4);
3204 }
3205 break;
3206 case PIPE_SHADER_TESS_CTRL:
3207 si_pm4_delete_state(sctx, hs, shader->pm4);
3208 break;
3209 case PIPE_SHADER_TESS_EVAL:
3210 if (shader->key.as_es) {
3211 assert(sctx->chip_class <= GFX8);
3212 si_pm4_delete_state(sctx, es, shader->pm4);
3213 } else if (shader->key.as_ngg) {
3214 si_pm4_delete_state(sctx, gs, shader->pm4);
3215 } else {
3216 si_pm4_delete_state(sctx, vs, shader->pm4);
3217 }
3218 break;
3219 case PIPE_SHADER_GEOMETRY:
3220 if (shader->is_gs_copy_shader)
3221 si_pm4_delete_state(sctx, vs, shader->pm4);
3222 else
3223 si_pm4_delete_state(sctx, gs, shader->pm4);
3224 break;
3225 case PIPE_SHADER_FRAGMENT:
3226 si_pm4_delete_state(sctx, ps, shader->pm4);
3227 break;
3228 default:;
3229 }
3230 }
3231
3232 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3233 si_shader_destroy(shader);
3234 free(shader);
3235 }
3236
3237 void si_destroy_shader_selector(struct si_context *sctx,
3238 struct si_shader_selector *sel)
3239 {
3240 struct si_shader *p = sel->first_variant, *c;
3241 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3242 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3243 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3244 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3245 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3246 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3247 };
3248
3249 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3250
3251 if (current_shader[sel->type]->cso == sel) {
3252 current_shader[sel->type]->cso = NULL;
3253 current_shader[sel->type]->current = NULL;
3254 }
3255
3256 while (p) {
3257 c = p->next_variant;
3258 si_delete_shader(sctx, p);
3259 p = c;
3260 }
3261
3262 if (sel->main_shader_part)
3263 si_delete_shader(sctx, sel->main_shader_part);
3264 if (sel->main_shader_part_ls)
3265 si_delete_shader(sctx, sel->main_shader_part_ls);
3266 if (sel->main_shader_part_es)
3267 si_delete_shader(sctx, sel->main_shader_part_es);
3268 if (sel->main_shader_part_ngg)
3269 si_delete_shader(sctx, sel->main_shader_part_ngg);
3270 if (sel->gs_copy_shader)
3271 si_delete_shader(sctx, sel->gs_copy_shader);
3272
3273 util_queue_fence_destroy(&sel->ready);
3274 simple_mtx_destroy(&sel->mutex);
3275 ralloc_free(sel->nir);
3276 free(sel->nir_binary);
3277 free(sel);
3278 }
3279
3280 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3281 {
3282 struct si_context *sctx = (struct si_context *)ctx;
3283 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3284
3285 si_shader_selector_reference(sctx, &sel, NULL);
3286 }
3287
3288 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3289 struct si_shader *vs, unsigned name,
3290 unsigned index, unsigned interpolate)
3291 {
3292 struct tgsi_shader_info *vsinfo = &vs->selector->info;
3293 unsigned j, offset, ps_input_cntl = 0;
3294
3295 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3296 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3297 name == TGSI_SEMANTIC_PRIMID)
3298 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3299
3300 if (name == TGSI_SEMANTIC_PCOORD ||
3301 (name == TGSI_SEMANTIC_TEXCOORD &&
3302 sctx->sprite_coord_enable & (1 << index))) {
3303 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3304 }
3305
3306 for (j = 0; j < vsinfo->num_outputs; j++) {
3307 if (name == vsinfo->output_semantic_name[j] &&
3308 index == vsinfo->output_semantic_index[j]) {
3309 offset = vs->info.vs_output_param_offset[j];
3310
3311 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3312 /* The input is loaded from parameter memory. */
3313 ps_input_cntl |= S_028644_OFFSET(offset);
3314 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3315 if (offset == AC_EXP_PARAM_UNDEFINED) {
3316 /* This can happen with depth-only rendering. */
3317 offset = 0;
3318 } else {
3319 /* The input is a DEFAULT_VAL constant. */
3320 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3321 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3322 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3323 }
3324
3325 ps_input_cntl = S_028644_OFFSET(0x20) |
3326 S_028644_DEFAULT_VAL(offset);
3327 }
3328 break;
3329 }
3330 }
3331
3332 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3333 /* PrimID is written after the last output when HW VS is used. */
3334 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3335 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3336 /* No corresponding output found, load defaults into input.
3337 * Don't set any other bits.
3338 * (FLAT_SHADE=1 completely changes behavior) */
3339 ps_input_cntl = S_028644_OFFSET(0x20);
3340 /* D3D 9 behaviour. GL is undefined */
3341 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3342 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3343 }
3344 return ps_input_cntl;
3345 }
3346
3347 static void si_emit_spi_map(struct si_context *sctx)
3348 {
3349 struct si_shader *ps = sctx->ps_shader.current;
3350 struct si_shader *vs = si_get_vs_state(sctx);
3351 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3352 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3353 unsigned spi_ps_input_cntl[32];
3354
3355 if (!ps || !ps->selector->info.num_inputs)
3356 return;
3357
3358 num_interp = si_get_ps_num_interp(ps);
3359 assert(num_interp > 0);
3360
3361 for (i = 0; i < psinfo->num_inputs; i++) {
3362 unsigned name = psinfo->input_semantic_name[i];
3363 unsigned index = psinfo->input_semantic_index[i];
3364 unsigned interpolate = psinfo->input_interpolate[i];
3365
3366 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3367 index, interpolate);
3368
3369 if (name == TGSI_SEMANTIC_COLOR) {
3370 assert(index < ARRAY_SIZE(bcol_interp));
3371 bcol_interp[index] = interpolate;
3372 }
3373 }
3374
3375 if (ps->key.part.ps.prolog.color_two_side) {
3376 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3377
3378 for (i = 0; i < 2; i++) {
3379 if (!(psinfo->colors_read & (0xf << (i * 4))))
3380 continue;
3381
3382 spi_ps_input_cntl[num_written++] =
3383 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3384
3385 }
3386 }
3387 assert(num_interp == num_written);
3388
3389 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3390 /* Dota 2: Only ~16% of SPI map updates set different values. */
3391 /* Talos: Only ~9% of SPI map updates set different values. */
3392 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3393 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3394 spi_ps_input_cntl,
3395 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3396
3397 if (initial_cdw != sctx->gfx_cs->current.cdw)
3398 sctx->context_roll = true;
3399 }
3400
3401 /**
3402 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3403 */
3404 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3405 {
3406 if (sctx->init_config_has_vgt_flush)
3407 return;
3408
3409 /* Done by Vulkan before VGT_FLUSH. */
3410 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3411 si_pm4_cmd_add(sctx->init_config,
3412 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3413 si_pm4_cmd_end(sctx->init_config, false);
3414
3415 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3416 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3417 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3418 si_pm4_cmd_end(sctx->init_config, false);
3419 sctx->init_config_has_vgt_flush = true;
3420 }
3421
3422 /* Initialize state related to ESGS / GSVS ring buffers */
3423 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3424 {
3425 struct si_shader_selector *es =
3426 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3427 struct si_shader_selector *gs = sctx->gs_shader.cso;
3428 struct si_pm4_state *pm4;
3429
3430 /* Chip constants. */
3431 unsigned num_se = sctx->screen->info.max_se;
3432 unsigned wave_size = 64;
3433 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3434 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3435 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3436 */
3437 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3438 unsigned alignment = 256 * num_se;
3439 /* The maximum size is 63.999 MB per SE. */
3440 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3441
3442 /* Calculate the minimum size. */
3443 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3444 wave_size, alignment);
3445
3446 /* These are recommended sizes, not minimum sizes. */
3447 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3448 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3449 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3450 gs->max_gsvs_emit_size;
3451
3452 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3453 esgs_ring_size = align(esgs_ring_size, alignment);
3454 gsvs_ring_size = align(gsvs_ring_size, alignment);
3455
3456 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3457 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3458
3459 /* Some rings don't have to be allocated if shaders don't use them.
3460 * (e.g. no varyings between ES and GS or GS and VS)
3461 *
3462 * GFX9 doesn't have the ESGS ring.
3463 */
3464 bool update_esgs = sctx->chip_class <= GFX8 &&
3465 esgs_ring_size &&
3466 (!sctx->esgs_ring ||
3467 sctx->esgs_ring->width0 < esgs_ring_size);
3468 bool update_gsvs = gsvs_ring_size &&
3469 (!sctx->gsvs_ring ||
3470 sctx->gsvs_ring->width0 < gsvs_ring_size);
3471
3472 if (!update_esgs && !update_gsvs)
3473 return true;
3474
3475 if (update_esgs) {
3476 pipe_resource_reference(&sctx->esgs_ring, NULL);
3477 sctx->esgs_ring =
3478 pipe_aligned_buffer_create(sctx->b.screen,
3479 SI_RESOURCE_FLAG_UNMAPPABLE,
3480 PIPE_USAGE_DEFAULT,
3481 esgs_ring_size,
3482 sctx->screen->info.pte_fragment_size);
3483 if (!sctx->esgs_ring)
3484 return false;
3485 }
3486
3487 if (update_gsvs) {
3488 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3489 sctx->gsvs_ring =
3490 pipe_aligned_buffer_create(sctx->b.screen,
3491 SI_RESOURCE_FLAG_UNMAPPABLE,
3492 PIPE_USAGE_DEFAULT,
3493 gsvs_ring_size,
3494 sctx->screen->info.pte_fragment_size);
3495 if (!sctx->gsvs_ring)
3496 return false;
3497 }
3498
3499 /* Create the "init_config_gs_rings" state. */
3500 pm4 = CALLOC_STRUCT(si_pm4_state);
3501 if (!pm4)
3502 return false;
3503
3504 if (sctx->chip_class >= GFX7) {
3505 if (sctx->esgs_ring) {
3506 assert(sctx->chip_class <= GFX8);
3507 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3508 sctx->esgs_ring->width0 / 256);
3509 }
3510 if (sctx->gsvs_ring)
3511 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3512 sctx->gsvs_ring->width0 / 256);
3513 } else {
3514 if (sctx->esgs_ring)
3515 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3516 sctx->esgs_ring->width0 / 256);
3517 if (sctx->gsvs_ring)
3518 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3519 sctx->gsvs_ring->width0 / 256);
3520 }
3521
3522 /* Set the state. */
3523 if (sctx->init_config_gs_rings)
3524 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3525 sctx->init_config_gs_rings = pm4;
3526
3527 if (!sctx->init_config_has_vgt_flush) {
3528 si_init_config_add_vgt_flush(sctx);
3529 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3530 }
3531
3532 /* Flush the context to re-emit both init_config states. */
3533 sctx->initial_gfx_cs_size = 0; /* force flush */
3534 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3535
3536 /* Set ring bindings. */
3537 if (sctx->esgs_ring) {
3538 assert(sctx->chip_class <= GFX8);
3539 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3540 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3541 true, true, 4, 64, 0);
3542 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3543 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3544 false, false, 0, 0, 0);
3545 }
3546 if (sctx->gsvs_ring) {
3547 si_set_ring_buffer(sctx, SI_RING_GSVS,
3548 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3549 false, false, 0, 0, 0);
3550 }
3551
3552 return true;
3553 }
3554
3555 static void si_shader_lock(struct si_shader *shader)
3556 {
3557 simple_mtx_lock(&shader->selector->mutex);
3558 if (shader->previous_stage_sel) {
3559 assert(shader->previous_stage_sel != shader->selector);
3560 simple_mtx_lock(&shader->previous_stage_sel->mutex);
3561 }
3562 }
3563
3564 static void si_shader_unlock(struct si_shader *shader)
3565 {
3566 if (shader->previous_stage_sel)
3567 simple_mtx_unlock(&shader->previous_stage_sel->mutex);
3568 simple_mtx_unlock(&shader->selector->mutex);
3569 }
3570
3571 /**
3572 * @returns 1 if \p sel has been updated to use a new scratch buffer
3573 * 0 if not
3574 * < 0 if there was a failure
3575 */
3576 static int si_update_scratch_buffer(struct si_context *sctx,
3577 struct si_shader *shader)
3578 {
3579 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3580
3581 if (!shader)
3582 return 0;
3583
3584 /* This shader doesn't need a scratch buffer */
3585 if (shader->config.scratch_bytes_per_wave == 0)
3586 return 0;
3587
3588 /* Prevent race conditions when updating:
3589 * - si_shader::scratch_bo
3590 * - si_shader::binary::code
3591 * - si_shader::previous_stage::binary::code.
3592 */
3593 si_shader_lock(shader);
3594
3595 /* This shader is already configured to use the current
3596 * scratch buffer. */
3597 if (shader->scratch_bo == sctx->scratch_buffer) {
3598 si_shader_unlock(shader);
3599 return 0;
3600 }
3601
3602 assert(sctx->scratch_buffer);
3603
3604 /* Replace the shader bo with a new bo that has the relocs applied. */
3605 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3606 si_shader_unlock(shader);
3607 return -1;
3608 }
3609
3610 /* Update the shader state to use the new shader bo. */
3611 si_shader_init_pm4_state(sctx->screen, shader);
3612
3613 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3614
3615 si_shader_unlock(shader);
3616 return 1;
3617 }
3618
3619 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3620 {
3621 return shader ? shader->config.scratch_bytes_per_wave : 0;
3622 }
3623
3624 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3625 {
3626 if (!sctx->tes_shader.cso)
3627 return NULL; /* tessellation disabled */
3628
3629 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3630 sctx->fixed_func_tcs_shader.current;
3631 }
3632
3633 static bool si_update_scratch_relocs(struct si_context *sctx)
3634 {
3635 struct si_shader *tcs = si_get_tcs_current(sctx);
3636 int r;
3637
3638 /* Update the shaders, so that they are using the latest scratch.
3639 * The scratch buffer may have been changed since these shaders were
3640 * last used, so we still need to try to update them, even if they
3641 * require scratch buffers smaller than the current size.
3642 */
3643 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3644 if (r < 0)
3645 return false;
3646 if (r == 1)
3647 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3648
3649 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3650 if (r < 0)
3651 return false;
3652 if (r == 1)
3653 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3654
3655 r = si_update_scratch_buffer(sctx, tcs);
3656 if (r < 0)
3657 return false;
3658 if (r == 1)
3659 si_pm4_bind_state(sctx, hs, tcs->pm4);
3660
3661 /* VS can be bound as LS, ES, or VS. */
3662 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3663 if (r < 0)
3664 return false;
3665 if (r == 1) {
3666 if (sctx->vs_shader.current->key.as_ls)
3667 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3668 else if (sctx->vs_shader.current->key.as_es)
3669 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3670 else if (sctx->vs_shader.current->key.as_ngg)
3671 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3672 else
3673 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3674 }
3675
3676 /* TES can be bound as ES or VS. */
3677 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3678 if (r < 0)
3679 return false;
3680 if (r == 1) {
3681 if (sctx->tes_shader.current->key.as_es)
3682 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3683 else if (sctx->tes_shader.current->key.as_ngg)
3684 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3685 else
3686 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3687 }
3688
3689 return true;
3690 }
3691
3692 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3693 {
3694 /* SPI_TMPRING_SIZE.WAVESIZE must be constant for each scratch buffer.
3695 * There are 2 cases to handle:
3696 *
3697 * - If the current needed size is less than the maximum seen size,
3698 * use the maximum seen size, so that WAVESIZE remains the same.
3699 *
3700 * - If the current needed size is greater than the maximum seen size,
3701 * the scratch buffer is reallocated, so we can increase WAVESIZE.
3702 *
3703 * Shaders that set SCRATCH_EN=0 don't allocate scratch space.
3704 * Otherwise, the number of waves that can use scratch is
3705 * SPI_TMPRING_SIZE.WAVES.
3706 */
3707 unsigned bytes = 0;
3708
3709 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3710 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3711 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3712
3713 if (sctx->tes_shader.cso) {
3714 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3715 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(si_get_tcs_current(sctx)));
3716 }
3717
3718 sctx->max_seen_scratch_bytes_per_wave =
3719 MAX2(sctx->max_seen_scratch_bytes_per_wave, bytes);
3720
3721 unsigned scratch_needed_size =
3722 sctx->max_seen_scratch_bytes_per_wave * sctx->scratch_waves;
3723 unsigned spi_tmpring_size;
3724
3725 if (scratch_needed_size > 0) {
3726 if (!sctx->scratch_buffer ||
3727 scratch_needed_size > sctx->scratch_buffer->b.b.width0) {
3728 /* Create a bigger scratch buffer */
3729 si_resource_reference(&sctx->scratch_buffer, NULL);
3730
3731 sctx->scratch_buffer =
3732 si_aligned_buffer_create(&sctx->screen->b,
3733 SI_RESOURCE_FLAG_UNMAPPABLE,
3734 PIPE_USAGE_DEFAULT,
3735 scratch_needed_size,
3736 sctx->screen->info.pte_fragment_size);
3737 if (!sctx->scratch_buffer)
3738 return false;
3739
3740 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3741 si_context_add_resource_size(sctx,
3742 &sctx->scratch_buffer->b.b);
3743 }
3744
3745 if (!si_update_scratch_relocs(sctx))
3746 return false;
3747 }
3748
3749 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3750 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3751 "scratch size should already be aligned correctly.");
3752
3753 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3754 S_0286E8_WAVESIZE(sctx->max_seen_scratch_bytes_per_wave >> 10);
3755 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3756 sctx->spi_tmpring_size = spi_tmpring_size;
3757 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3758 }
3759 return true;
3760 }
3761
3762 static void si_init_tess_factor_ring(struct si_context *sctx)
3763 {
3764 assert(!sctx->tess_rings);
3765 assert(((sctx->screen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
3766
3767 /* The address must be aligned to 2^19, because the shader only
3768 * receives the high 13 bits.
3769 */
3770 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3771 SI_RESOURCE_FLAG_32BIT,
3772 PIPE_USAGE_DEFAULT,
3773 sctx->screen->tess_offchip_ring_size +
3774 sctx->screen->tess_factor_ring_size,
3775 1 << 19);
3776 if (!sctx->tess_rings)
3777 return;
3778
3779 si_init_config_add_vgt_flush(sctx);
3780
3781 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3782 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3783
3784 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3785 sctx->screen->tess_offchip_ring_size;
3786
3787 /* Append these registers to the init config state. */
3788 if (sctx->chip_class >= GFX7) {
3789 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3790 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3791 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3792 factor_va >> 8);
3793 if (sctx->chip_class >= GFX10)
3794 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3795 S_030984_BASE_HI(factor_va >> 40));
3796 else if (sctx->chip_class == GFX9)
3797 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3798 S_030944_BASE_HI(factor_va >> 40));
3799 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3800 sctx->screen->vgt_hs_offchip_param);
3801 } else {
3802 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3803 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3804 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3805 factor_va >> 8);
3806 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3807 sctx->screen->vgt_hs_offchip_param);
3808 }
3809
3810 /* Flush the context to re-emit the init_config state.
3811 * This is done only once in a lifetime of a context.
3812 */
3813 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3814 sctx->initial_gfx_cs_size = 0; /* force flush */
3815 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3816 }
3817
3818 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3819 union si_vgt_stages_key key)
3820 {
3821 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3822 uint32_t stages = 0;
3823
3824 if (key.u.tess) {
3825 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3826 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3827
3828 if (key.u.gs)
3829 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3830 S_028B54_GS_EN(1);
3831 else if (key.u.ngg)
3832 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3833 else
3834 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3835 } else if (key.u.gs) {
3836 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3837 S_028B54_GS_EN(1);
3838 } else if (key.u.ngg) {
3839 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3840 }
3841
3842 if (key.u.ngg) {
3843 stages |= S_028B54_PRIMGEN_EN(1) |
3844 S_028B54_NGG_WAVE_ID_EN(key.u.streamout) |
3845 S_028B54_PRIMGEN_PASSTHRU_EN(key.u.ngg_passthrough);
3846 } else if (key.u.gs)
3847 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3848
3849 if (screen->info.chip_class >= GFX9)
3850 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3851
3852 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
3853 stages |= S_028B54_HS_W32_EN(1) |
3854 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3855 S_028B54_VS_W32_EN(1);
3856 }
3857
3858 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3859 return pm4;
3860 }
3861
3862 static void si_update_vgt_shader_config(struct si_context *sctx,
3863 union si_vgt_stages_key key)
3864 {
3865 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3866
3867 if (unlikely(!*pm4))
3868 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3869 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3870 }
3871
3872 bool si_update_shaders(struct si_context *sctx)
3873 {
3874 struct pipe_context *ctx = (struct pipe_context*)sctx;
3875 struct si_compiler_ctx_state compiler_state;
3876 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3877 struct si_shader *old_vs = si_get_vs_state(sctx);
3878 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3879 struct si_shader *old_ps = sctx->ps_shader.current;
3880 union si_vgt_stages_key key;
3881 unsigned old_spi_shader_col_format =
3882 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3883 int r;
3884
3885 if (!sctx->compiler.passes)
3886 si_init_compiler(sctx->screen, &sctx->compiler);
3887
3888 compiler_state.compiler = &sctx->compiler;
3889 compiler_state.debug = sctx->debug;
3890 compiler_state.is_debug_context = sctx->is_debug;
3891
3892 key.index = 0;
3893
3894 if (sctx->tes_shader.cso)
3895 key.u.tess = 1;
3896 if (sctx->gs_shader.cso)
3897 key.u.gs = 1;
3898
3899 if (sctx->ngg) {
3900 key.u.ngg = 1;
3901 key.u.streamout = !!si_get_vs(sctx)->cso->so.num_outputs;
3902 }
3903
3904 /* Update TCS and TES. */
3905 if (sctx->tes_shader.cso) {
3906 if (!sctx->tess_rings) {
3907 si_init_tess_factor_ring(sctx);
3908 if (!sctx->tess_rings)
3909 return false;
3910 }
3911
3912 if (sctx->tcs_shader.cso) {
3913 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3914 &compiler_state);
3915 if (r)
3916 return false;
3917 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3918 } else {
3919 if (!sctx->fixed_func_tcs_shader.cso) {
3920 sctx->fixed_func_tcs_shader.cso =
3921 si_create_fixed_func_tcs(sctx);
3922 if (!sctx->fixed_func_tcs_shader.cso)
3923 return false;
3924 }
3925
3926 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3927 key, &compiler_state);
3928 if (r)
3929 return false;
3930 si_pm4_bind_state(sctx, hs,
3931 sctx->fixed_func_tcs_shader.current->pm4);
3932 }
3933
3934 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3935 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3936 if (r)
3937 return false;
3938
3939 if (sctx->gs_shader.cso) {
3940 /* TES as ES */
3941 assert(sctx->chip_class <= GFX8);
3942 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3943 } else if (key.u.ngg) {
3944 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3945 } else {
3946 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3947 }
3948 }
3949 } else {
3950 if (sctx->chip_class <= GFX8)
3951 si_pm4_bind_state(sctx, ls, NULL);
3952 si_pm4_bind_state(sctx, hs, NULL);
3953 }
3954
3955 /* Update GS. */
3956 if (sctx->gs_shader.cso) {
3957 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3958 if (r)
3959 return false;
3960 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3961 if (!key.u.ngg) {
3962 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3963
3964 if (!si_update_gs_ring_buffers(sctx))
3965 return false;
3966 } else {
3967 si_pm4_bind_state(sctx, vs, NULL);
3968 }
3969 } else {
3970 if (!key.u.ngg) {
3971 si_pm4_bind_state(sctx, gs, NULL);
3972 if (sctx->chip_class <= GFX8)
3973 si_pm4_bind_state(sctx, es, NULL);
3974 }
3975 }
3976
3977 /* Update VS. */
3978 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
3979 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
3980 if (r)
3981 return false;
3982
3983 if (!key.u.tess && !key.u.gs) {
3984 if (key.u.ngg) {
3985 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3986 si_pm4_bind_state(sctx, vs, NULL);
3987 } else {
3988 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3989 }
3990 } else if (sctx->tes_shader.cso) {
3991 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3992 } else {
3993 assert(sctx->gs_shader.cso);
3994 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3995 }
3996 }
3997
3998 /* This must be done after the shader variant is selected. */
3999 if (sctx->ngg)
4000 key.u.ngg_passthrough = gfx10_is_ngg_passthrough(si_get_vs(sctx)->current);
4001
4002 si_update_vgt_shader_config(sctx, key);
4003
4004 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
4005 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
4006
4007 if (sctx->ps_shader.cso) {
4008 unsigned db_shader_control;
4009
4010 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
4011 if (r)
4012 return false;
4013 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
4014
4015 db_shader_control =
4016 sctx->ps_shader.cso->db_shader_control |
4017 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
4018
4019 if (si_pm4_state_changed(sctx, ps) ||
4020 si_pm4_state_changed(sctx, vs) ||
4021 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
4022 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
4023 sctx->flatshade != rs->flatshade) {
4024 sctx->sprite_coord_enable = rs->sprite_coord_enable;
4025 sctx->flatshade = rs->flatshade;
4026 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
4027 }
4028
4029 if (sctx->screen->info.rbplus_allowed &&
4030 si_pm4_state_changed(sctx, ps) &&
4031 (!old_ps ||
4032 old_spi_shader_col_format !=
4033 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
4034 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
4035
4036 if (sctx->ps_db_shader_control != db_shader_control) {
4037 sctx->ps_db_shader_control = db_shader_control;
4038 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4039 if (sctx->screen->dpbb_allowed)
4040 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
4041 }
4042
4043 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
4044 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
4045 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
4046
4047 if (sctx->chip_class == GFX6)
4048 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4049
4050 if (sctx->framebuffer.nr_samples <= 1)
4051 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
4052 }
4053 }
4054
4055 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
4056 si_pm4_state_enabled_and_changed(sctx, hs) ||
4057 si_pm4_state_enabled_and_changed(sctx, es) ||
4058 si_pm4_state_enabled_and_changed(sctx, gs) ||
4059 si_pm4_state_enabled_and_changed(sctx, vs) ||
4060 si_pm4_state_enabled_and_changed(sctx, ps)) {
4061 if (!si_update_spi_tmpring_size(sctx))
4062 return false;
4063 }
4064
4065 if (sctx->chip_class >= GFX7) {
4066 if (si_pm4_state_enabled_and_changed(sctx, ls))
4067 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
4068 else if (!sctx->queued.named.ls)
4069 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
4070
4071 if (si_pm4_state_enabled_and_changed(sctx, hs))
4072 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
4073 else if (!sctx->queued.named.hs)
4074 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
4075
4076 if (si_pm4_state_enabled_and_changed(sctx, es))
4077 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4078 else if (!sctx->queued.named.es)
4079 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4080
4081 if (si_pm4_state_enabled_and_changed(sctx, gs))
4082 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4083 else if (!sctx->queued.named.gs)
4084 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4085
4086 if (si_pm4_state_enabled_and_changed(sctx, vs))
4087 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4088 else if (!sctx->queued.named.vs)
4089 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4090
4091 if (si_pm4_state_enabled_and_changed(sctx, ps))
4092 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4093 else if (!sctx->queued.named.ps)
4094 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4095 }
4096
4097 sctx->do_update_shaders = false;
4098 return true;
4099 }
4100
4101 static void si_emit_scratch_state(struct si_context *sctx)
4102 {
4103 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4104
4105 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4106 sctx->spi_tmpring_size);
4107
4108 if (sctx->scratch_buffer) {
4109 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4110 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4111 RADEON_PRIO_SCRATCH_BUFFER);
4112 }
4113 }
4114
4115 void si_init_shader_functions(struct si_context *sctx)
4116 {
4117 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4118 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4119
4120 sctx->b.create_vs_state = si_create_shader_selector;
4121 sctx->b.create_tcs_state = si_create_shader_selector;
4122 sctx->b.create_tes_state = si_create_shader_selector;
4123 sctx->b.create_gs_state = si_create_shader_selector;
4124 sctx->b.create_fs_state = si_create_shader_selector;
4125
4126 sctx->b.bind_vs_state = si_bind_vs_shader;
4127 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4128 sctx->b.bind_tes_state = si_bind_tes_shader;
4129 sctx->b.bind_gs_state = si_bind_gs_shader;
4130 sctx->b.bind_fs_state = si_bind_ps_shader;
4131
4132 sctx->b.delete_vs_state = si_delete_shader_selector;
4133 sctx->b.delete_tcs_state = si_delete_shader_selector;
4134 sctx->b.delete_tes_state = si_delete_shader_selector;
4135 sctx->b.delete_gs_state = si_delete_shader_selector;
4136 sctx->b.delete_fs_state = si_delete_shader_selector;
4137 }