2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "ac_exp_param.h"
26 #include "ac_shader_util.h"
27 #include "compiler/nir/nir_serialize.h"
28 #include "nir/tgsi_to_nir.h"
29 #include "si_build_pm4.h"
31 #include "util/crc32.h"
32 #include "util/disk_cache.h"
33 #include "util/hash_table.h"
34 #include "util/mesa-sha1.h"
35 #include "util/u_async_debug.h"
36 #include "util/u_memory.h"
37 #include "util/u_prim.h"
38 #include "tgsi/tgsi_from_mesa.h"
43 * Return the IR key for the shader cache.
45 void si_get_ir_cache_key(struct si_shader_selector
*sel
, bool ngg
, bool es
,
46 unsigned char ir_sha1_cache_key
[20])
48 struct blob blob
= {};
52 if (sel
->nir_binary
) {
53 ir_binary
= sel
->nir_binary
;
54 ir_size
= sel
->nir_size
;
59 nir_serialize(&blob
, sel
->nir
, true);
60 ir_binary
= blob
.data
;
64 /* These settings affect the compilation, but they are not derived
65 * from the input shader IR.
67 unsigned shader_variant_flags
= 0;
70 shader_variant_flags
|= 1 << 0;
72 shader_variant_flags
|= 1 << 1;
73 if (si_get_wave_size(sel
->screen
, sel
->info
.stage
, ngg
, es
, false, false) == 32)
74 shader_variant_flags
|= 1 << 2;
75 if (sel
->info
.stage
== MESA_SHADER_FRAGMENT
&& sel
->info
.uses_derivatives
&& sel
->info
.uses_kill
&&
76 sel
->screen
->debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
))
77 shader_variant_flags
|= 1 << 3;
79 /* This varies depending on whether compute-based culling is enabled. */
80 shader_variant_flags
|= sel
->screen
->num_vbos_in_user_sgprs
<< 4;
83 _mesa_sha1_init(&ctx
);
84 _mesa_sha1_update(&ctx
, &shader_variant_flags
, 4);
85 _mesa_sha1_update(&ctx
, ir_binary
, ir_size
);
86 if (sel
->info
.stage
== MESA_SHADER_VERTEX
|| sel
->info
.stage
== MESA_SHADER_TESS_EVAL
||
87 sel
->info
.stage
== MESA_SHADER_GEOMETRY
)
88 _mesa_sha1_update(&ctx
, &sel
->so
, sizeof(sel
->so
));
89 _mesa_sha1_final(&ctx
, ir_sha1_cache_key
);
91 if (ir_binary
== blob
.data
)
95 /** Copy "data" to "ptr" and return the next dword following copied data. */
96 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
98 /* data may be NULL if size == 0 */
100 memcpy(ptr
, data
, size
);
101 ptr
+= DIV_ROUND_UP(size
, 4);
105 /** Read data from "ptr". Return the next dword following the data. */
106 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
108 memcpy(data
, ptr
, size
);
109 ptr
+= DIV_ROUND_UP(size
, 4);
114 * Write the size as uint followed by the data. Return the next dword
115 * following the copied data.
117 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
120 return write_data(ptr
, data
, size
);
124 * Read the size as uint followed by the data. Return both via parameters.
125 * Return the next dword following the data.
127 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
130 assert(*data
== NULL
);
133 *data
= malloc(*size
);
134 return read_data(ptr
, *data
, *size
);
138 * Return the shader binary in a buffer. The first 4 bytes contain its size
141 static void *si_get_shader_binary(struct si_shader
*shader
)
143 /* There is always a size of data followed by the data itself. */
144 unsigned llvm_ir_size
=
145 shader
->binary
.llvm_ir_string
? strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
147 /* Refuse to allocate overly large buffers and guard against integer
149 if (shader
->binary
.elf_size
> UINT_MAX
/ 4 || llvm_ir_size
> UINT_MAX
/ 4)
152 unsigned size
= 4 + /* total size */
153 4 + /* CRC32 of the data below */
154 align(sizeof(shader
->config
), 4) + align(sizeof(shader
->info
), 4) + 4 +
155 align(shader
->binary
.elf_size
, 4) + 4 + align(llvm_ir_size
, 4);
156 void *buffer
= CALLOC(1, size
);
157 uint32_t *ptr
= (uint32_t *)buffer
;
163 ptr
++; /* CRC32 is calculated at the end. */
165 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
166 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
167 ptr
= write_chunk(ptr
, shader
->binary
.elf_buffer
, shader
->binary
.elf_size
);
168 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
169 assert((char *)ptr
- (char *)buffer
== size
);
172 ptr
= (uint32_t *)buffer
;
174 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
179 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
181 uint32_t *ptr
= (uint32_t *)binary
;
182 uint32_t size
= *ptr
++;
183 uint32_t crc32
= *ptr
++;
187 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
188 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
192 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
193 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
194 ptr
= read_chunk(ptr
, (void **)&shader
->binary
.elf_buffer
, &elf_size
);
195 shader
->binary
.elf_size
= elf_size
;
196 ptr
= read_chunk(ptr
, (void **)&shader
->binary
.llvm_ir_string
, &chunk_size
);
202 * Insert a shader into the cache. It's assumed the shader is not in the cache.
203 * Use si_shader_cache_load_shader before calling this.
205 void si_shader_cache_insert_shader(struct si_screen
*sscreen
, unsigned char ir_sha1_cache_key
[20],
206 struct si_shader
*shader
, bool insert_into_disk_cache
)
209 struct hash_entry
*entry
;
210 uint8_t key
[CACHE_KEY_SIZE
];
212 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, ir_sha1_cache_key
);
214 return; /* already added */
216 hw_binary
= si_get_shader_binary(shader
);
220 if (_mesa_hash_table_insert(sscreen
->shader_cache
, mem_dup(ir_sha1_cache_key
, 20), hw_binary
) ==
226 if (sscreen
->disk_shader_cache
&& insert_into_disk_cache
) {
227 disk_cache_compute_key(sscreen
->disk_shader_cache
, ir_sha1_cache_key
, 20, key
);
228 disk_cache_put(sscreen
->disk_shader_cache
, key
, hw_binary
, *((uint32_t *)hw_binary
), NULL
);
232 bool si_shader_cache_load_shader(struct si_screen
*sscreen
, unsigned char ir_sha1_cache_key
[20],
233 struct si_shader
*shader
)
235 struct hash_entry
*entry
= _mesa_hash_table_search(sscreen
->shader_cache
, ir_sha1_cache_key
);
238 if (si_load_shader_binary(shader
, entry
->data
)) {
239 p_atomic_inc(&sscreen
->num_memory_shader_cache_hits
);
243 p_atomic_inc(&sscreen
->num_memory_shader_cache_misses
);
245 if (!sscreen
->disk_shader_cache
)
248 unsigned char sha1
[CACHE_KEY_SIZE
];
249 disk_cache_compute_key(sscreen
->disk_shader_cache
, ir_sha1_cache_key
, 20, sha1
);
252 uint8_t *buffer
= disk_cache_get(sscreen
->disk_shader_cache
, sha1
, &binary_size
);
254 if (binary_size
>= sizeof(uint32_t) && *((uint32_t *)buffer
) == binary_size
) {
255 if (si_load_shader_binary(shader
, buffer
)) {
257 si_shader_cache_insert_shader(sscreen
, ir_sha1_cache_key
, shader
, false);
258 p_atomic_inc(&sscreen
->num_disk_shader_cache_hits
);
262 /* Something has gone wrong discard the item from the cache and
263 * rebuild/link from source.
265 assert(!"Invalid radeonsi shader disk cache item!");
266 disk_cache_remove(sscreen
->disk_shader_cache
, sha1
);
271 p_atomic_inc(&sscreen
->num_disk_shader_cache_misses
);
275 static uint32_t si_shader_cache_key_hash(const void *key
)
277 /* Take the first dword of SHA1. */
278 return *(uint32_t *)key
;
281 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
284 return memcmp(a
, b
, 20) == 0;
287 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
289 FREE((void *)entry
->key
);
293 bool si_init_shader_cache(struct si_screen
*sscreen
)
295 (void)simple_mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
296 sscreen
->shader_cache
=
297 _mesa_hash_table_create(NULL
, si_shader_cache_key_hash
, si_shader_cache_key_equals
);
299 return sscreen
->shader_cache
!= NULL
;
302 void si_destroy_shader_cache(struct si_screen
*sscreen
)
304 if (sscreen
->shader_cache
)
305 _mesa_hash_table_destroy(sscreen
->shader_cache
, si_destroy_shader_cache_entry
);
306 simple_mtx_destroy(&sscreen
->shader_cache_mutex
);
311 static void si_set_tesseval_regs(struct si_screen
*sscreen
, const struct si_shader_selector
*tes
,
312 struct si_pm4_state
*pm4
)
314 const struct si_shader_info
*info
= &tes
->info
;
315 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
316 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
317 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
318 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
319 unsigned type
, partitioning
, topology
, distribution_mode
;
321 switch (tes_prim_mode
) {
322 case PIPE_PRIM_LINES
:
323 type
= V_028B6C_TESS_ISOLINE
;
325 case PIPE_PRIM_TRIANGLES
:
326 type
= V_028B6C_TESS_TRIANGLE
;
328 case PIPE_PRIM_QUADS
:
329 type
= V_028B6C_TESS_QUAD
;
336 switch (tes_spacing
) {
337 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
338 partitioning
= V_028B6C_PART_FRAC_ODD
;
340 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
341 partitioning
= V_028B6C_PART_FRAC_EVEN
;
343 case PIPE_TESS_SPACING_EQUAL
:
344 partitioning
= V_028B6C_PART_INTEGER
;
352 topology
= V_028B6C_OUTPUT_POINT
;
353 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
354 topology
= V_028B6C_OUTPUT_LINE
;
355 else if (tes_vertex_order_cw
)
356 /* for some reason, this must be the other way around */
357 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
359 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
361 if (sscreen
->info
.has_distributed_tess
) {
362 if (sscreen
->info
.family
== CHIP_FIJI
|| sscreen
->info
.family
>= CHIP_POLARIS10
)
363 distribution_mode
= V_028B6C_TRAPEZOIDS
;
365 distribution_mode
= V_028B6C_DONUTS
;
367 distribution_mode
= V_028B6C_NO_DIST
;
370 pm4
->shader
->vgt_tf_param
= S_028B6C_TYPE(type
) | S_028B6C_PARTITIONING(partitioning
) |
371 S_028B6C_TOPOLOGY(topology
) |
372 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
375 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
376 * whether the "fractional odd" tessellation spacing is used.
378 * Possible VGT configurations and which state should set the register:
380 * Reg set in | VGT shader configuration | Value
381 * ------------------------------------------------------
383 * VS as ES | ES -> GS -> VS | 30
384 * TES as VS | LS -> HS -> VS | 14 or 30
385 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
387 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
389 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
, struct si_shader_selector
*sel
,
390 struct si_shader
*shader
, struct si_pm4_state
*pm4
)
392 if (sscreen
->info
.family
< CHIP_POLARIS10
|| sscreen
->info
.chip_class
>= GFX10
)
395 /* VS as VS, or VS as ES: */
396 if ((sel
->info
.stage
== MESA_SHADER_VERTEX
&&
397 (!shader
|| (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
398 /* TES as VS, or TES as ES: */
399 sel
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
400 unsigned vtx_reuse_depth
= 30;
402 if (sel
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
403 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] == PIPE_TESS_SPACING_FRACTIONAL_ODD
)
404 vtx_reuse_depth
= 14;
407 pm4
->shader
->vgt_vertex_reuse_block_cntl
= vtx_reuse_depth
;
411 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
414 si_pm4_clear_state(shader
->pm4
);
416 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
419 shader
->pm4
->shader
= shader
;
422 fprintf(stderr
, "radeonsi: Failed to create pm4 state.\n");
427 static unsigned si_get_num_vs_user_sgprs(struct si_shader
*shader
,
428 unsigned num_always_on_user_sgprs
)
430 struct si_shader_selector
*vs
=
431 shader
->previous_stage_sel
? shader
->previous_stage_sel
: shader
->selector
;
432 unsigned num_vbos_in_user_sgprs
= vs
->num_vbos_in_user_sgprs
;
434 /* 1 SGPR is reserved for the vertex buffer pointer. */
435 assert(num_always_on_user_sgprs
<= SI_SGPR_VS_VB_DESCRIPTOR_FIRST
- 1);
437 if (num_vbos_in_user_sgprs
)
438 return SI_SGPR_VS_VB_DESCRIPTOR_FIRST
+ num_vbos_in_user_sgprs
* 4;
440 /* Add the pointer to VBO descriptors. */
441 return num_always_on_user_sgprs
+ 1;
444 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
445 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen
*sscreen
, struct si_shader
*shader
,
446 bool legacy_vs_prim_id
)
448 assert(shader
->selector
->info
.stage
== MESA_SHADER_VERTEX
||
449 (shader
->previous_stage_sel
&& shader
->previous_stage_sel
->info
.stage
== MESA_SHADER_VERTEX
));
451 /* GFX6-9 LS (VertexID, RelAutoindex, InstanceID / StepRate0(==1), ...).
452 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID, ...)
453 * GFX10 LS (VertexID, RelAutoindex, UserVGPR1, InstanceID).
454 * GFX10 ES,VS (VertexID, UserVGPR0, UserVGPR1 or VSPrimID, UserVGPR2 or
457 bool is_ls
= shader
->selector
->info
.stage
== MESA_SHADER_TESS_CTRL
|| shader
->key
.as_ls
;
459 if (sscreen
->info
.chip_class
>= GFX10
&& shader
->info
.uses_instanceid
)
461 else if ((is_ls
&& shader
->info
.uses_instanceid
) || legacy_vs_prim_id
)
463 else if (is_ls
|| shader
->info
.uses_instanceid
)
469 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
471 struct si_pm4_state
*pm4
;
474 assert(sscreen
->info
.chip_class
<= GFX8
);
476 pm4
= si_get_shader_pm4_state(shader
);
480 va
= shader
->bo
->gpu_address
;
481 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
482 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
484 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
485 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
486 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false)) |
487 S_00B528_DX10_CLAMP(1) | S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
488 shader
->config
.rsrc2
=
489 S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(shader
, SI_VS_NUM_USER_SGPR
)) |
490 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
493 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
495 struct si_pm4_state
*pm4
;
498 pm4
= si_get_shader_pm4_state(shader
);
502 va
= shader
->bo
->gpu_address
;
504 if (sscreen
->info
.chip_class
>= GFX9
) {
505 if (sscreen
->info
.chip_class
>= GFX10
) {
506 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
507 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
509 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
510 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, S_00B414_MEM_BASE(va
>> 40));
513 unsigned num_user_sgprs
= si_get_num_vs_user_sgprs(shader
, GFX9_TCS_NUM_USER_SGPR
);
515 shader
->config
.rsrc2
= S_00B42C_USER_SGPR(num_user_sgprs
) |
516 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
518 if (sscreen
->info
.chip_class
>= GFX10
)
519 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
521 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
523 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
524 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, S_00B424_MEM_BASE(va
>> 40));
526 shader
->config
.rsrc2
= S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) | S_00B42C_OC_LDS_EN(1) |
527 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
531 pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
532 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
533 (sscreen
->info
.chip_class
<= GFX9
? S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8)
535 S_00B428_DX10_CLAMP(1) | S_00B428_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
536 S_00B428_WGP_MODE(sscreen
->info
.chip_class
>= GFX10
) |
537 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
538 S_00B428_LS_VGPR_COMP_CNT(sscreen
->info
.chip_class
>= GFX9
539 ? si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false)
542 if (sscreen
->info
.chip_class
<= GFX8
) {
543 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
, shader
->config
.rsrc2
);
547 static void si_emit_shader_es(struct si_context
*sctx
)
549 struct si_shader
*shader
= sctx
->queued
.named
.es
->shader
;
550 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
555 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
556 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
557 shader
->selector
->esgs_itemsize
/ 4);
559 if (shader
->selector
->info
.stage
== MESA_SHADER_TESS_EVAL
)
560 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
, SI_TRACKED_VGT_TF_PARAM
,
561 shader
->vgt_tf_param
);
563 if (shader
->vgt_vertex_reuse_block_cntl
)
564 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
565 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
566 shader
->vgt_vertex_reuse_block_cntl
);
568 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
569 sctx
->context_roll
= true;
572 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
574 struct si_pm4_state
*pm4
;
575 unsigned num_user_sgprs
;
576 unsigned vgpr_comp_cnt
;
580 assert(sscreen
->info
.chip_class
<= GFX8
);
582 pm4
= si_get_shader_pm4_state(shader
);
586 pm4
->atom
.emit
= si_emit_shader_es
;
587 va
= shader
->bo
->gpu_address
;
589 if (shader
->selector
->info
.stage
== MESA_SHADER_VERTEX
) {
590 vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false);
591 num_user_sgprs
= si_get_num_vs_user_sgprs(shader
, SI_VS_NUM_USER_SGPR
);
592 } else if (shader
->selector
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
593 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
594 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
596 unreachable("invalid shader selector type");
598 oc_lds_en
= shader
->selector
->info
.stage
== MESA_SHADER_TESS_EVAL
? 1 : 0;
600 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
601 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
602 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
603 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
604 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
605 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) | S_00B328_DX10_CLAMP(1) |
606 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
607 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
608 S_00B32C_USER_SGPR(num_user_sgprs
) | S_00B32C_OC_LDS_EN(oc_lds_en
) |
609 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
611 if (shader
->selector
->info
.stage
== MESA_SHADER_TESS_EVAL
)
612 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
614 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
617 void gfx9_get_gs_info(struct si_shader_selector
*es
, struct si_shader_selector
*gs
,
618 struct gfx9_gs_info
*out
)
620 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
621 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
622 bool uses_adjacency
=
623 input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&& input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
625 /* All these are in dwords: */
626 /* We can't allow using the whole LDS, because GS waves compete with
627 * other shader stages for LDS space. */
628 const unsigned max_lds_size
= 8 * 1024;
629 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
630 unsigned esgs_lds_size
;
632 /* All these are per subgroup: */
633 const unsigned max_out_prims
= 32 * 1024;
634 const unsigned max_es_verts
= 255;
635 const unsigned ideal_gs_prims
= 64;
636 unsigned max_gs_prims
, gs_prims
;
637 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
639 if (uses_adjacency
|| gs_num_invocations
> 1)
640 max_gs_prims
= 127 / gs_num_invocations
;
644 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
645 * Make sure we don't go over the maximum value.
647 if (gs
->gs_max_out_vertices
> 0) {
649 MIN2(max_gs_prims
, max_out_prims
/ (gs
->gs_max_out_vertices
* gs_num_invocations
));
651 assert(max_gs_prims
> 0);
653 /* If the primitive has adjacency, halve the number of vertices
654 * that will be reused in multiple primitives.
656 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
658 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
659 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
661 /* Compute ESGS LDS size based on the worst case number of ES vertices
662 * needed to create the target number of GS prims per subgroup.
664 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
666 /* If total LDS usage is too big, refactor partitions based on ratio
667 * of ESGS item sizes.
669 if (esgs_lds_size
> max_lds_size
) {
670 /* Our target GS Prims Per Subgroup was too large. Calculate
671 * the maximum number of GS Prims Per Subgroup that will fit
672 * into LDS, capped by the maximum that the hardware can support.
674 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)), max_gs_prims
);
675 assert(gs_prims
> 0);
676 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
678 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
679 assert(esgs_lds_size
<= max_lds_size
);
682 /* Now calculate remaining ESGS information. */
684 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
686 es_verts
= max_es_verts
;
688 /* Vertices for adjacency primitives are not always reused, so restore
689 * it for ES_VERTS_PER_SUBGRP.
691 min_es_verts
= gs
->gs_input_verts_per_prim
;
693 /* For normal primitives, the VGT only checks if they are past the ES
694 * verts per subgroup after allocating a full GS primitive and if they
695 * are, kick off a new subgroup. But if those additional ES verts are
696 * unique (e.g. not reused) we need to make sure there is enough LDS
697 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
699 es_verts
-= min_es_verts
- 1;
701 out
->es_verts_per_subgroup
= es_verts
;
702 out
->gs_prims_per_subgroup
= gs_prims
;
703 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
704 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
* gs
->gs_max_out_vertices
;
705 out
->esgs_ring_size
= esgs_lds_size
;
707 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
710 static void si_emit_shader_gs(struct si_context
*sctx
)
712 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
713 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
718 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
719 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
720 radeon_opt_set_context_reg3(
721 sctx
, R_028A60_VGT_GSVS_RING_OFFSET_1
, SI_TRACKED_VGT_GSVS_RING_OFFSET_1
,
722 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
, shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
,
723 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
);
725 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
726 radeon_opt_set_context_reg(sctx
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
,
727 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE
,
728 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
);
730 /* R_028B38_VGT_GS_MAX_VERT_OUT */
731 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
, SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
732 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
);
734 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
735 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
736 radeon_opt_set_context_reg4(
737 sctx
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, SI_TRACKED_VGT_GS_VERT_ITEMSIZE
,
738 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
, shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
,
739 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
, shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
);
741 /* R_028B90_VGT_GS_INSTANCE_CNT */
742 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
, SI_TRACKED_VGT_GS_INSTANCE_CNT
,
743 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
);
745 if (sctx
->chip_class
>= GFX9
) {
746 /* R_028A44_VGT_GS_ONCHIP_CNTL */
747 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
, SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
748 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
);
749 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
750 radeon_opt_set_context_reg(sctx
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
751 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
752 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
);
753 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
754 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
755 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
756 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
);
758 if (shader
->key
.part
.gs
.es
->info
.stage
== MESA_SHADER_TESS_EVAL
)
759 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
, SI_TRACKED_VGT_TF_PARAM
,
760 shader
->vgt_tf_param
);
761 if (shader
->vgt_vertex_reuse_block_cntl
)
762 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
763 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
764 shader
->vgt_vertex_reuse_block_cntl
);
767 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
768 sctx
->context_roll
= true;
771 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
773 struct si_shader_selector
*sel
= shader
->selector
;
774 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
775 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
776 struct si_pm4_state
*pm4
;
778 unsigned max_stream
= sel
->max_gs_stream
;
781 pm4
= si_get_shader_pm4_state(shader
);
785 pm4
->atom
.emit
= si_emit_shader_gs
;
787 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
788 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
= offset
;
791 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
792 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
= offset
;
795 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
796 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
= offset
;
799 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
800 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
= offset
;
802 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
803 assert(offset
< (1 << 15));
805 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
= sel
->gs_max_out_vertices
;
807 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
= num_components
[0];
808 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
= (max_stream
>= 1) ? num_components
[1] : 0;
809 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
= (max_stream
>= 2) ? num_components
[2] : 0;
810 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
= (max_stream
>= 3) ? num_components
[3] : 0;
812 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
=
813 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) | S_028B90_ENABLE(gs_num_invocations
> 0);
815 va
= shader
->bo
->gpu_address
;
817 if (sscreen
->info
.chip_class
>= GFX9
) {
818 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
819 gl_shader_stage es_stage
= shader
->key
.part
.gs
.es
->info
.stage
;
820 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
822 if (es_stage
== MESA_SHADER_VERTEX
) {
823 es_vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false);
824 } else if (es_stage
== MESA_SHADER_TESS_EVAL
)
825 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
827 unreachable("invalid shader selector type");
829 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
830 * VGPR[0:4] are always loaded.
832 if (sel
->info
.uses_invocationid
)
833 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
834 else if (sel
->info
.uses_primid
)
835 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
836 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
837 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
839 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
841 unsigned num_user_sgprs
;
842 if (es_stage
== MESA_SHADER_VERTEX
)
843 num_user_sgprs
= si_get_num_vs_user_sgprs(shader
, GFX9_VSGS_NUM_USER_SGPR
);
845 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
847 if (sscreen
->info
.chip_class
>= GFX10
) {
848 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
849 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
851 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
852 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, S_00B214_MEM_BASE(va
>> 40));
855 uint32_t rsrc1
= S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) | S_00B228_DX10_CLAMP(1) |
856 S_00B228_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
857 S_00B228_WGP_MODE(sscreen
->info
.chip_class
>= GFX10
) |
858 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
859 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
860 uint32_t rsrc2
= S_00B22C_USER_SGPR(num_user_sgprs
) |
861 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
862 S_00B22C_OC_LDS_EN(es_stage
== MESA_SHADER_TESS_EVAL
) |
863 S_00B22C_LDS_SIZE(shader
->config
.lds_size
) |
864 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
866 if (sscreen
->info
.chip_class
>= GFX10
) {
867 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
869 rsrc1
|= S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
870 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
873 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, rsrc1
);
874 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
, rsrc2
);
876 if (sscreen
->info
.chip_class
>= GFX10
) {
877 si_pm4_set_reg(pm4
, R_00B204_SPI_SHADER_PGM_RSRC4_GS
,
878 S_00B204_CU_EN(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0));
881 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
=
882 S_028A44_ES_VERTS_PER_SUBGRP(shader
->gs_info
.es_verts_per_subgroup
) |
883 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->gs_info
.gs_prims_per_subgroup
) |
884 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->gs_info
.gs_inst_prims_in_subgroup
);
885 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
=
886 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader
->gs_info
.max_prims_per_subgroup
);
887 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
= shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4;
889 if (es_stage
== MESA_SHADER_TESS_EVAL
)
890 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
892 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
, NULL
, pm4
);
894 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
895 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, S_00B224_MEM_BASE(va
>> 40));
897 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
898 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
899 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
900 S_00B228_DX10_CLAMP(1) | S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
901 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
902 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
903 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
907 static void gfx10_emit_ge_pc_alloc(struct si_context
*sctx
, unsigned value
)
909 enum si_tracked_reg reg
= SI_TRACKED_GE_PC_ALLOC
;
911 if (((sctx
->tracked_regs
.reg_saved
>> reg
) & 0x1) != 0x1 ||
912 sctx
->tracked_regs
.reg_value
[reg
] != value
) {
913 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
915 if (sctx
->chip_class
== GFX10
) {
916 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
917 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
918 radeon_emit(cs
, EVENT_TYPE(V_028A90_SQ_NON_EVENT
) | EVENT_INDEX(0));
921 radeon_set_uconfig_reg(cs
, R_030980_GE_PC_ALLOC
, value
);
923 sctx
->tracked_regs
.reg_saved
|= 0x1ull
<< reg
;
924 sctx
->tracked_regs
.reg_value
[reg
] = value
;
928 /* Common tail code for NGG primitive shaders. */
929 static void gfx10_emit_shader_ngg_tail(struct si_context
*sctx
, struct si_shader
*shader
,
930 unsigned initial_cdw
)
932 radeon_opt_set_context_reg(sctx
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
933 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP
,
934 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
);
935 radeon_opt_set_context_reg(sctx
, R_028B4C_GE_NGG_SUBGRP_CNTL
, SI_TRACKED_GE_NGG_SUBGRP_CNTL
,
936 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
);
937 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
, SI_TRACKED_VGT_PRIMITIVEID_EN
,
938 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
);
939 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
, SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
940 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
);
941 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
, SI_TRACKED_VGT_GS_INSTANCE_CNT
,
942 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
);
943 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
944 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
945 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
);
946 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
, SI_TRACKED_SPI_VS_OUT_CONFIG
,
947 shader
->ctx_reg
.ngg
.spi_vs_out_config
);
948 radeon_opt_set_context_reg2(
949 sctx
, R_028708_SPI_SHADER_IDX_FORMAT
, SI_TRACKED_SPI_SHADER_IDX_FORMAT
,
950 shader
->ctx_reg
.ngg
.spi_shader_idx_format
, shader
->ctx_reg
.ngg
.spi_shader_pos_format
);
951 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
, SI_TRACKED_PA_CL_VTE_CNTL
,
952 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
);
953 radeon_opt_set_context_reg(sctx
, R_028838_PA_CL_NGG_CNTL
, SI_TRACKED_PA_CL_NGG_CNTL
,
954 shader
->ctx_reg
.ngg
.pa_cl_ngg_cntl
);
956 radeon_opt_set_context_reg_rmw(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
957 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS
, shader
->pa_cl_vs_out_cntl
,
958 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK
);
960 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
961 sctx
->context_roll
= true;
963 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
964 gfx10_emit_ge_pc_alloc(sctx
, shader
->ctx_reg
.ngg
.ge_pc_alloc
);
967 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context
*sctx
)
969 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
970 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
975 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
978 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context
*sctx
)
980 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
981 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
986 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
, SI_TRACKED_VGT_TF_PARAM
,
987 shader
->vgt_tf_param
);
989 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
992 static void gfx10_emit_shader_ngg_notess_gs(struct si_context
*sctx
)
994 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
995 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1000 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
, SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1001 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1003 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1006 static void gfx10_emit_shader_ngg_tess_gs(struct si_context
*sctx
)
1008 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1009 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1014 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
, SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1015 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1016 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
, SI_TRACKED_VGT_TF_PARAM
,
1017 shader
->vgt_tf_param
);
1019 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1022 unsigned si_get_input_prim(const struct si_shader_selector
*gs
)
1024 if (gs
->info
.stage
== MESA_SHADER_GEOMETRY
)
1025 return gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
1027 if (gs
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
1028 if (gs
->info
.properties
[TGSI_PROPERTY_TES_POINT_MODE
])
1029 return PIPE_PRIM_POINTS
;
1030 if (gs
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] == PIPE_PRIM_LINES
)
1031 return PIPE_PRIM_LINES
;
1032 return PIPE_PRIM_TRIANGLES
;
1035 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1036 return PIPE_PRIM_TRIANGLES
; /* worst case for all callers */
1039 static unsigned si_get_vs_out_cntl(const struct si_shader_selector
*sel
, bool ngg
)
1041 bool misc_vec_ena
= sel
->info
.writes_psize
|| (sel
->info
.writes_edgeflag
&& !ngg
) ||
1042 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
1043 return S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
1044 S_02881C_USE_VTX_EDGE_FLAG(sel
->info
.writes_edgeflag
&& !ngg
) |
1045 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
1046 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
1047 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
1048 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
1052 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1055 static void gfx10_shader_ngg(struct si_screen
*sscreen
, struct si_shader
*shader
)
1057 const struct si_shader_selector
*gs_sel
= shader
->selector
;
1058 const struct si_shader_info
*gs_info
= &gs_sel
->info
;
1059 const gl_shader_stage gs_stage
= shader
->selector
->info
.stage
;
1060 const struct si_shader_selector
*es_sel
=
1061 shader
->previous_stage_sel
? shader
->previous_stage_sel
: shader
->selector
;
1062 const struct si_shader_info
*es_info
= &es_sel
->info
;
1063 const gl_shader_stage es_stage
= es_sel
->info
.stage
;
1064 unsigned num_user_sgprs
;
1065 unsigned nparams
, es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
1067 unsigned window_space
= gs_info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1068 bool es_enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| es_info
->uses_primid
;
1069 unsigned gs_num_invocations
= MAX2(gs_sel
->gs_num_invocations
, 1);
1070 unsigned input_prim
= si_get_input_prim(gs_sel
);
1071 bool break_wave_at_eoi
= false;
1072 struct si_pm4_state
*pm4
= si_get_shader_pm4_state(shader
);
1076 if (es_stage
== MESA_SHADER_TESS_EVAL
) {
1077 pm4
->atom
.emit
= gs_stage
== MESA_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_tess_gs
1078 : gfx10_emit_shader_ngg_tess_nogs
;
1080 pm4
->atom
.emit
= gs_stage
== MESA_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_notess_gs
1081 : gfx10_emit_shader_ngg_notess_nogs
;
1084 va
= shader
->bo
->gpu_address
;
1086 if (es_stage
== MESA_SHADER_VERTEX
) {
1087 es_vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false);
1089 if (es_info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
]) {
1091 SI_SGPR_VS_BLIT_DATA
+ es_info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
];
1093 num_user_sgprs
= si_get_num_vs_user_sgprs(shader
, GFX9_VSGS_NUM_USER_SGPR
);
1096 assert(es_stage
== MESA_SHADER_TESS_EVAL
);
1097 es_vgpr_comp_cnt
= es_enable_prim_id
? 3 : 2;
1098 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
1100 if (es_enable_prim_id
|| gs_info
->uses_primid
)
1101 break_wave_at_eoi
= true;
1104 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1105 * VGPR[0:4] are always loaded.
1107 * Vertex shaders always need to load VGPR3, because they need to
1108 * pass edge flags for decomposed primitives (such as quads) to the PA
1109 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1111 if (gs_info
->uses_invocationid
||
1112 (gs_stage
== MESA_SHADER_VERTEX
&& !gfx10_is_ngg_passthrough(shader
)))
1113 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID, edge flags. */
1114 else if ((gs_stage
== MESA_SHADER_GEOMETRY
&& gs_info
->uses_primid
) ||
1115 (gs_stage
== MESA_SHADER_VERTEX
&& shader
->key
.mono
.u
.vs_export_prim_id
))
1116 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
1117 else if (input_prim
>= PIPE_PRIM_TRIANGLES
&& !gfx10_is_ngg_passthrough(shader
))
1118 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
1120 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
1122 unsigned wave_size
= si_get_shader_wave_size(shader
);
1124 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
1125 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
1127 pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
1128 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / (wave_size
== 32 ? 8 : 4)) |
1129 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) | S_00B228_DX10_CLAMP(1) |
1130 S_00B228_MEM_ORDERED(1) | S_00B228_WGP_MODE(1) |
1131 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
1132 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
1133 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0) |
1134 S_00B22C_USER_SGPR(num_user_sgprs
) |
1135 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
1136 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5) |
1137 S_00B22C_OC_LDS_EN(es_stage
== MESA_SHADER_TESS_EVAL
) |
1138 S_00B22C_LDS_SIZE(shader
->config
.lds_size
));
1140 /* Determine LATE_ALLOC_GS. */
1141 unsigned num_cu_per_sh
= sscreen
->info
.min_good_cu_per_sa
;
1142 unsigned late_alloc_wave64
; /* The limit is per SA. */
1144 /* For Wave32, the hw will launch twice the number of late
1145 * alloc waves, so 1 == 2x wave32.
1147 * Don't use late alloc for NGG on Navi14 due to a hw bug.
1149 if (sscreen
->info
.family
== CHIP_NAVI14
|| !sscreen
->info
.use_late_alloc
)
1150 late_alloc_wave64
= 0;
1151 else if (num_cu_per_sh
<= 6)
1152 late_alloc_wave64
= num_cu_per_sh
- 2; /* All CUs enabled */
1153 else if (shader
->key
.opt
.ngg_culling
& SI_NGG_CULL_GS_FAST_LAUNCH_ALL
)
1154 late_alloc_wave64
= (num_cu_per_sh
- 2) * 6;
1156 late_alloc_wave64
= (num_cu_per_sh
- 2) * 4;
1158 /* Limit LATE_ALLOC_GS for prevent a hang (hw bug). */
1159 if (sscreen
->info
.chip_class
== GFX10
)
1160 late_alloc_wave64
= MIN2(late_alloc_wave64
, 64);
1163 pm4
, R_00B204_SPI_SHADER_PGM_RSRC4_GS
,
1164 S_00B204_CU_EN(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64
));
1166 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1167 shader
->ctx_reg
.ngg
.spi_vs_out_config
=
1168 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
1169 S_0286C4_NO_PC_EXPORT(shader
->info
.nr_param_exports
== 0);
1171 shader
->ctx_reg
.ngg
.spi_shader_idx_format
=
1172 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
);
1173 shader
->ctx_reg
.ngg
.spi_shader_pos_format
=
1174 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1175 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ? V_02870C_SPI_SHADER_4COMP
1176 : V_02870C_SPI_SHADER_NONE
) |
1177 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ? V_02870C_SPI_SHADER_4COMP
1178 : V_02870C_SPI_SHADER_NONE
) |
1179 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ? V_02870C_SPI_SHADER_4COMP
1180 : V_02870C_SPI_SHADER_NONE
);
1182 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
=
1183 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
1184 S_028A84_NGG_DISABLE_PROVOK_REUSE(shader
->key
.mono
.u
.vs_export_prim_id
||
1185 gs_sel
->info
.writes_primid
);
1187 if (gs_stage
== MESA_SHADER_GEOMETRY
) {
1188 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= es_sel
->esgs_itemsize
/ 4;
1189 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
= gs_sel
->gs_max_out_vertices
;
1191 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= 1;
1194 if (es_stage
== MESA_SHADER_TESS_EVAL
)
1195 si_set_tesseval_regs(sscreen
, es_sel
, pm4
);
1197 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
=
1198 S_028A44_ES_VERTS_PER_SUBGRP(shader
->ngg
.hw_max_esverts
) |
1199 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->ngg
.max_gsprims
) |
1200 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->ngg
.max_gsprims
* gs_num_invocations
);
1201 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
=
1202 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader
->ngg
.max_out_verts
);
1203 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
= S_028B4C_PRIM_AMP_FACTOR(shader
->ngg
.prim_amp_factor
) |
1204 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1205 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
=
1206 S_028B90_CNT(gs_num_invocations
) | S_028B90_ENABLE(gs_num_invocations
> 1) |
1207 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(shader
->ngg
.max_vert_out_per_gs_instance
);
1209 /* Always output hw-generated edge flags and pass them via the prim
1210 * export to prevent drawing lines on internal edges of decomposed
1211 * primitives (such as quads) with polygon mode = lines. Only VS needs
1214 shader
->ctx_reg
.ngg
.pa_cl_ngg_cntl
=
1215 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_stage
== MESA_SHADER_VERTEX
) |
1216 /* Reuse for NGG. */
1217 S_028838_VERTEX_REUSE_DEPTH(sscreen
->info
.chip_class
>= GFX10_3
? 30 : 0);
1218 shader
->pa_cl_vs_out_cntl
= si_get_vs_out_cntl(gs_sel
, true);
1220 /* Oversubscribe PC. This improves performance when there are too many varyings. */
1221 float oversub_pc_factor
= 0.25;
1223 if (shader
->key
.opt
.ngg_culling
) {
1224 /* Be more aggressive with NGG culling. */
1225 if (shader
->info
.nr_param_exports
> 4)
1226 oversub_pc_factor
= 1;
1227 else if (shader
->info
.nr_param_exports
> 2)
1228 oversub_pc_factor
= 0.75;
1230 oversub_pc_factor
= 0.5;
1233 unsigned oversub_pc_lines
= sscreen
->info
.pc_lines
* oversub_pc_factor
;
1234 shader
->ctx_reg
.ngg
.ge_pc_alloc
= S_030980_OVERSUB_EN(sscreen
->info
.use_late_alloc
) |
1235 S_030980_NUM_PC_LINES(oversub_pc_lines
- 1);
1237 if (shader
->key
.opt
.ngg_culling
& SI_NGG_CULL_GS_FAST_LAUNCH_TRI_LIST
) {
1238 shader
->ge_cntl
= S_03096C_PRIM_GRP_SIZE(shader
->ngg
.max_gsprims
) |
1239 S_03096C_VERT_GRP_SIZE(shader
->ngg
.max_gsprims
* 3);
1240 } else if (shader
->key
.opt
.ngg_culling
& SI_NGG_CULL_GS_FAST_LAUNCH_TRI_STRIP
) {
1241 shader
->ge_cntl
= S_03096C_PRIM_GRP_SIZE(shader
->ngg
.max_gsprims
) |
1242 S_03096C_VERT_GRP_SIZE(shader
->ngg
.max_gsprims
+ 2);
1244 shader
->ge_cntl
= S_03096C_PRIM_GRP_SIZE(shader
->ngg
.max_gsprims
) |
1245 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
1246 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
1248 /* Bug workaround for a possible hang with non-tessellation cases.
1249 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1251 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1253 if ((sscreen
->info
.chip_class
== GFX10
) &&
1254 (es_stage
== MESA_SHADER_VERTEX
|| gs_stage
== MESA_SHADER_VERTEX
) && /* = no tess */
1255 shader
->ngg
.hw_max_esverts
!= 256) {
1256 shader
->ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
1258 if (shader
->ngg
.hw_max_esverts
> 5) {
1259 shader
->ge_cntl
|= S_03096C_VERT_GRP_SIZE(shader
->ngg
.hw_max_esverts
- 5);
1265 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
= S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1267 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1268 S_028818_VTX_W0_FMT(1) | S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1269 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1270 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1274 static void si_emit_shader_vs(struct si_context
*sctx
)
1276 struct si_shader
*shader
= sctx
->queued
.named
.vs
->shader
;
1277 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1282 radeon_opt_set_context_reg(sctx
, R_028A40_VGT_GS_MODE
, SI_TRACKED_VGT_GS_MODE
,
1283 shader
->ctx_reg
.vs
.vgt_gs_mode
);
1284 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
, SI_TRACKED_VGT_PRIMITIVEID_EN
,
1285 shader
->ctx_reg
.vs
.vgt_primitiveid_en
);
1287 if (sctx
->chip_class
<= GFX8
) {
1288 radeon_opt_set_context_reg(sctx
, R_028AB4_VGT_REUSE_OFF
, SI_TRACKED_VGT_REUSE_OFF
,
1289 shader
->ctx_reg
.vs
.vgt_reuse_off
);
1292 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
, SI_TRACKED_SPI_VS_OUT_CONFIG
,
1293 shader
->ctx_reg
.vs
.spi_vs_out_config
);
1295 radeon_opt_set_context_reg(sctx
, R_02870C_SPI_SHADER_POS_FORMAT
,
1296 SI_TRACKED_SPI_SHADER_POS_FORMAT
,
1297 shader
->ctx_reg
.vs
.spi_shader_pos_format
);
1299 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
, SI_TRACKED_PA_CL_VTE_CNTL
,
1300 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
);
1302 if (shader
->selector
->info
.stage
== MESA_SHADER_TESS_EVAL
)
1303 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
, SI_TRACKED_VGT_TF_PARAM
,
1304 shader
->vgt_tf_param
);
1306 if (shader
->vgt_vertex_reuse_block_cntl
)
1307 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1308 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1309 shader
->vgt_vertex_reuse_block_cntl
);
1311 /* Required programming for tessellation. (legacy pipeline only) */
1312 if (sctx
->chip_class
>= GFX10
&& shader
->selector
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
1313 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
1314 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
1315 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1316 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1317 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1320 if (sctx
->chip_class
>= GFX10
) {
1321 radeon_opt_set_context_reg_rmw(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
1322 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS
, shader
->pa_cl_vs_out_cntl
,
1323 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK
);
1326 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1327 sctx
->context_roll
= true;
1329 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1330 if (sctx
->chip_class
>= GFX10
)
1331 gfx10_emit_ge_pc_alloc(sctx
, shader
->ctx_reg
.vs
.ge_pc_alloc
);
1335 * Compute the state for \p shader, which will run as a vertex shader on the
1338 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1339 * is the copy shader.
1341 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
1342 struct si_shader_selector
*gs
)
1344 const struct si_shader_info
*info
= &shader
->selector
->info
;
1345 struct si_pm4_state
*pm4
;
1346 unsigned num_user_sgprs
, vgpr_comp_cnt
;
1348 unsigned nparams
, oc_lds_en
;
1349 unsigned window_space
= info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1350 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
1352 pm4
= si_get_shader_pm4_state(shader
);
1356 pm4
->atom
.emit
= si_emit_shader_vs
;
1358 /* We always write VGT_GS_MODE in the VS state, because every switch
1359 * between different shader pipelines involving a different GS or no
1360 * GS at all involves a switch of the VS (different GS use different
1361 * copy shaders). On the other hand, when the API switches from a GS to
1362 * no GS and then back to the same GS used originally, the GS state is
1366 unsigned mode
= V_028A40_GS_OFF
;
1368 /* PrimID needs GS scenario A. */
1370 mode
= V_028A40_GS_SCENARIO_A
;
1372 shader
->ctx_reg
.vs
.vgt_gs_mode
= S_028A40_MODE(mode
);
1373 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= enable_prim_id
;
1375 shader
->ctx_reg
.vs
.vgt_gs_mode
=
1376 ac_vgt_gs_mode(gs
->gs_max_out_vertices
, sscreen
->info
.chip_class
);
1377 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= 0;
1380 if (sscreen
->info
.chip_class
<= GFX8
) {
1381 /* Reuse needs to be set off if we write oViewport. */
1382 shader
->ctx_reg
.vs
.vgt_reuse_off
= S_028AB4_REUSE_OFF(info
->writes_viewport_index
);
1385 va
= shader
->bo
->gpu_address
;
1388 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
1389 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
1390 } else if (shader
->selector
->info
.stage
== MESA_SHADER_VERTEX
) {
1391 vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, enable_prim_id
);
1393 if (info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
]) {
1394 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+ info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
];
1396 num_user_sgprs
= si_get_num_vs_user_sgprs(shader
, SI_VS_NUM_USER_SGPR
);
1398 } else if (shader
->selector
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
1399 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
1400 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
1402 unreachable("invalid shader selector type");
1404 /* VS is required to export at least one param. */
1405 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1406 shader
->ctx_reg
.vs
.spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
1408 if (sscreen
->info
.chip_class
>= GFX10
) {
1409 shader
->ctx_reg
.vs
.spi_vs_out_config
|=
1410 S_0286C4_NO_PC_EXPORT(shader
->info
.nr_param_exports
== 0);
1413 shader
->ctx_reg
.vs
.spi_shader_pos_format
=
1414 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1415 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ? V_02870C_SPI_SHADER_4COMP
1416 : V_02870C_SPI_SHADER_NONE
) |
1417 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ? V_02870C_SPI_SHADER_4COMP
1418 : V_02870C_SPI_SHADER_NONE
) |
1419 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ? V_02870C_SPI_SHADER_4COMP
1420 : V_02870C_SPI_SHADER_NONE
);
1421 shader
->ctx_reg
.vs
.ge_pc_alloc
= S_030980_OVERSUB_EN(sscreen
->info
.use_late_alloc
) |
1422 S_030980_NUM_PC_LINES(sscreen
->info
.pc_lines
/ 4 - 1);
1423 shader
->pa_cl_vs_out_cntl
= si_get_vs_out_cntl(shader
->selector
, false);
1425 oc_lds_en
= shader
->selector
->info
.stage
== MESA_SHADER_TESS_EVAL
? 1 : 0;
1427 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
1428 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, S_00B124_MEM_BASE(va
>> 40));
1431 S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
1432 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) | S_00B128_DX10_CLAMP(1) |
1433 S_00B128_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1434 S_00B128_FLOAT_MODE(shader
->config
.float_mode
);
1435 uint32_t rsrc2
= S_00B12C_USER_SGPR(num_user_sgprs
) | S_00B12C_OC_LDS_EN(oc_lds_en
) |
1436 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
1438 if (sscreen
->info
.chip_class
>= GFX10
)
1439 rsrc2
|= S_00B12C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
1440 else if (sscreen
->info
.chip_class
== GFX9
)
1441 rsrc2
|= S_00B12C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
1443 if (sscreen
->info
.chip_class
<= GFX9
)
1444 rsrc1
|= S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1446 if (!sscreen
->use_ngg_streamout
) {
1447 rsrc2
|= S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
1448 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
1449 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
1450 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
1451 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
);
1454 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
, rsrc1
);
1455 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
, rsrc2
);
1458 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
= S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1460 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1461 S_028818_VTX_W0_FMT(1) | S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1462 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1463 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1465 if (shader
->selector
->info
.stage
== MESA_SHADER_TESS_EVAL
)
1466 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
1468 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
1471 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
1473 struct si_shader_info
*info
= &ps
->selector
->info
;
1474 unsigned num_colors
= !!(info
->colors_read
& 0x0f) + !!(info
->colors_read
& 0xf0);
1475 unsigned num_interp
=
1476 ps
->selector
->info
.num_inputs
+ (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
1478 assert(num_interp
<= 32);
1479 return MIN2(num_interp
, 32);
1482 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
1484 unsigned spi_shader_col_format
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
1485 unsigned value
= 0, num_mrts
= 0;
1486 unsigned i
, num_targets
= (util_last_bit(spi_shader_col_format
) + 3) / 4;
1488 /* Remove holes in spi_shader_col_format. */
1489 for (i
= 0; i
< num_targets
; i
++) {
1490 unsigned spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
1493 value
|= spi_format
<< (num_mrts
* 4);
1501 static void si_emit_shader_ps(struct si_context
*sctx
)
1503 struct si_shader
*shader
= sctx
->queued
.named
.ps
->shader
;
1504 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1509 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1510 radeon_opt_set_context_reg2(sctx
, R_0286CC_SPI_PS_INPUT_ENA
, SI_TRACKED_SPI_PS_INPUT_ENA
,
1511 shader
->ctx_reg
.ps
.spi_ps_input_ena
,
1512 shader
->ctx_reg
.ps
.spi_ps_input_addr
);
1514 radeon_opt_set_context_reg(sctx
, R_0286E0_SPI_BARYC_CNTL
, SI_TRACKED_SPI_BARYC_CNTL
,
1515 shader
->ctx_reg
.ps
.spi_baryc_cntl
);
1516 radeon_opt_set_context_reg(sctx
, R_0286D8_SPI_PS_IN_CONTROL
, SI_TRACKED_SPI_PS_IN_CONTROL
,
1517 shader
->ctx_reg
.ps
.spi_ps_in_control
);
1519 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1520 radeon_opt_set_context_reg2(sctx
, R_028710_SPI_SHADER_Z_FORMAT
, SI_TRACKED_SPI_SHADER_Z_FORMAT
,
1521 shader
->ctx_reg
.ps
.spi_shader_z_format
,
1522 shader
->ctx_reg
.ps
.spi_shader_col_format
);
1524 radeon_opt_set_context_reg(sctx
, R_02823C_CB_SHADER_MASK
, SI_TRACKED_CB_SHADER_MASK
,
1525 shader
->ctx_reg
.ps
.cb_shader_mask
);
1527 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1528 sctx
->context_roll
= true;
1531 static void si_shader_ps(struct si_screen
*sscreen
, struct si_shader
*shader
)
1533 struct si_shader_info
*info
= &shader
->selector
->info
;
1534 struct si_pm4_state
*pm4
;
1535 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1536 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1538 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1540 /* we need to enable at least one of them, otherwise we hang the GPU */
1541 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) || G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1542 G_0286CC_PERSP_CENTROID_ENA(input_ena
) || G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1543 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) || G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1544 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) || G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1545 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1546 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) || G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1547 G_0286CC_PERSP_CENTER_ENA(input_ena
) || G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1548 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1550 /* Validate interpolation optimization flags (read as implications). */
1551 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1552 (G_0286CC_PERSP_CENTER_ENA(input_ena
) && G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1553 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1554 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) && G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1555 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1556 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) && !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1557 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1558 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) && !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1559 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1560 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) && !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1561 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1562 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) && !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1564 /* Validate cases when the optimizations are off (read as implications). */
1565 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1566 !G_0286CC_PERSP_CENTER_ENA(input_ena
) || !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1567 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1568 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) || !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1570 pm4
= si_get_shader_pm4_state(shader
);
1574 pm4
->atom
.emit
= si_emit_shader_ps
;
1576 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1578 * 0 -> Position = pixel center
1579 * 1 -> Position = pixel centroid
1580 * 2 -> Position = at sample position
1582 * From GLSL 4.5 specification, section 7.1:
1583 * "The variable gl_FragCoord is available as an input variable from
1584 * within fragment shaders and it holds the window relative coordinates
1585 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1586 * value can be for any location within the pixel, or one of the
1587 * fragment samples. The use of centroid does not further restrict
1588 * this value to be inside the current primitive."
1590 * Meaning that centroid has no effect and we can return anything within
1591 * the pixel. Thus, return the value at sample position, because that's
1592 * the most accurate one shaders can get.
1594 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1596 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] == TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1597 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1599 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1600 cb_shader_mask
= ac_get_cb_shader_mask(shader
->key
.part
.ps
.epilog
.spi_shader_col_format
);
1602 /* Ensure that some export memory is always allocated, for two reasons:
1604 * 1) Correctness: The hardware ignores the EXEC mask if no export
1605 * memory is allocated, so KILL and alpha test do not work correctly
1607 * 2) Performance: Every shader needs at least a NULL export, even when
1608 * it writes no color/depth output. The NULL export instruction
1609 * stalls without this setting.
1611 * Don't add this to CB_SHADER_MASK.
1613 * GFX10 supports pixel shaders without exports by setting both
1614 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1615 * instructions if any are present.
1617 if ((sscreen
->info
.chip_class
<= GFX9
|| info
->uses_kill
||
1618 shader
->key
.part
.ps
.epilog
.alpha_func
!= PIPE_FUNC_ALWAYS
) &&
1619 !spi_shader_col_format
&& !info
->writes_z
&& !info
->writes_stencil
&&
1620 !info
->writes_samplemask
)
1621 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1623 shader
->ctx_reg
.ps
.spi_ps_input_ena
= input_ena
;
1624 shader
->ctx_reg
.ps
.spi_ps_input_addr
= shader
->config
.spi_ps_input_addr
;
1626 /* Set interpolation controls. */
1627 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
)) |
1628 S_0286D8_PS_W32_EN(sscreen
->ps_wave_size
== 32);
1630 shader
->ctx_reg
.ps
.spi_baryc_cntl
= spi_baryc_cntl
;
1631 shader
->ctx_reg
.ps
.spi_ps_in_control
= spi_ps_in_control
;
1632 shader
->ctx_reg
.ps
.spi_shader_z_format
=
1633 ac_get_spi_shader_z_format(info
->writes_z
, info
->writes_stencil
, info
->writes_samplemask
);
1634 shader
->ctx_reg
.ps
.spi_shader_col_format
= spi_shader_col_format
;
1635 shader
->ctx_reg
.ps
.cb_shader_mask
= cb_shader_mask
;
1637 va
= shader
->bo
->gpu_address
;
1638 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1639 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, S_00B024_MEM_BASE(va
>> 40));
1642 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / (sscreen
->ps_wave_size
== 32 ? 8 : 4)) |
1643 S_00B028_DX10_CLAMP(1) | S_00B028_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1644 S_00B028_FLOAT_MODE(shader
->config
.float_mode
);
1646 if (sscreen
->info
.chip_class
< GFX10
) {
1647 rsrc1
|= S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1650 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
, rsrc1
);
1651 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1652 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1653 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1654 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1657 static void si_shader_init_pm4_state(struct si_screen
*sscreen
, struct si_shader
*shader
)
1659 switch (shader
->selector
->info
.stage
) {
1660 case MESA_SHADER_VERTEX
:
1661 if (shader
->key
.as_ls
)
1662 si_shader_ls(sscreen
, shader
);
1663 else if (shader
->key
.as_es
)
1664 si_shader_es(sscreen
, shader
);
1665 else if (shader
->key
.as_ngg
)
1666 gfx10_shader_ngg(sscreen
, shader
);
1668 si_shader_vs(sscreen
, shader
, NULL
);
1670 case MESA_SHADER_TESS_CTRL
:
1671 si_shader_hs(sscreen
, shader
);
1673 case MESA_SHADER_TESS_EVAL
:
1674 if (shader
->key
.as_es
)
1675 si_shader_es(sscreen
, shader
);
1676 else if (shader
->key
.as_ngg
)
1677 gfx10_shader_ngg(sscreen
, shader
);
1679 si_shader_vs(sscreen
, shader
, NULL
);
1681 case MESA_SHADER_GEOMETRY
:
1682 if (shader
->key
.as_ngg
)
1683 gfx10_shader_ngg(sscreen
, shader
);
1685 si_shader_gs(sscreen
, shader
);
1687 case MESA_SHADER_FRAGMENT
:
1688 si_shader_ps(sscreen
, shader
);
1695 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1697 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1698 return sctx
->queued
.named
.dsa
->alpha_func
;
1701 void si_shader_selector_key_vs(struct si_context
*sctx
, struct si_shader_selector
*vs
,
1702 struct si_shader_key
*key
, struct si_vs_prolog_bits
*prolog_key
)
1704 if (!sctx
->vertex_elements
|| vs
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
])
1707 struct si_vertex_elements
*elts
= sctx
->vertex_elements
;
1709 prolog_key
->instance_divisor_is_one
= elts
->instance_divisor_is_one
;
1710 prolog_key
->instance_divisor_is_fetched
= elts
->instance_divisor_is_fetched
;
1711 prolog_key
->unpack_instance_id_from_vertex_id
= sctx
->prim_discard_cs_instancing
;
1713 /* Prefer a monolithic shader to allow scheduling divisions around
1715 if (prolog_key
->instance_divisor_is_fetched
)
1716 key
->opt
.prefer_mono
= 1;
1718 unsigned count
= MIN2(vs
->info
.num_inputs
, elts
->count
);
1719 unsigned count_mask
= (1 << count
) - 1;
1720 unsigned fix
= elts
->fix_fetch_always
& count_mask
;
1721 unsigned opencode
= elts
->fix_fetch_opencode
& count_mask
;
1723 if (sctx
->vertex_buffer_unaligned
& elts
->vb_alignment_check_mask
) {
1724 uint32_t mask
= elts
->fix_fetch_unaligned
& count_mask
;
1726 unsigned i
= u_bit_scan(&mask
);
1727 unsigned log_hw_load_size
= 1 + ((elts
->hw_load_is_dword
>> i
) & 1);
1728 unsigned vbidx
= elts
->vertex_buffer_index
[i
];
1729 struct pipe_vertex_buffer
*vb
= &sctx
->vertex_buffer
[vbidx
];
1730 unsigned align_mask
= (1 << log_hw_load_size
) - 1;
1731 if (vb
->buffer_offset
& align_mask
|| vb
->stride
& align_mask
) {
1739 unsigned i
= u_bit_scan(&fix
);
1740 key
->mono
.vs_fix_fetch
[i
].bits
= elts
->fix_fetch
[i
];
1742 key
->mono
.vs_fetch_opencode
= opencode
;
1745 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
, struct si_shader_selector
*vs
,
1746 struct si_shader_key
*key
)
1748 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1750 key
->opt
.clip_disable
= sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1751 (vs
->info
.clipdist_writemask
|| vs
->info
.writes_clipvertex
) &&
1752 !vs
->info
.culldist_writemask
;
1754 /* Find out if PS is disabled. */
1755 bool ps_disabled
= true;
1757 bool ps_modifies_zs
= ps
->info
.uses_kill
|| ps
->info
.writes_z
|| ps
->info
.writes_stencil
||
1758 ps
->info
.writes_samplemask
||
1759 sctx
->queued
.named
.blend
->alpha_to_coverage
||
1760 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1761 unsigned ps_colormask
= si_get_total_colormask(sctx
);
1763 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1764 (!ps_colormask
&& !ps_modifies_zs
&& !ps
->info
.writes_memory
);
1767 /* Find out which VS outputs aren't used by the PS. */
1768 uint64_t outputs_written
= vs
->outputs_written_before_ps
;
1769 uint64_t inputs_read
= 0;
1771 /* Ignore outputs that are not passed from VS to PS. */
1772 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(VARYING_SLOT_POS
, true)) |
1773 (1ull << si_shader_io_get_unique_index(VARYING_SLOT_PSIZ
, true)) |
1774 (1ull << si_shader_io_get_unique_index(VARYING_SLOT_CLIP_VERTEX
, true)));
1777 inputs_read
= ps
->inputs_read
;
1780 uint64_t linked
= outputs_written
& inputs_read
;
1782 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1783 key
->opt
.ngg_culling
= sctx
->ngg_culling
;
1786 /* Compute the key for the hw shader variant */
1787 static inline void si_shader_selector_key(struct pipe_context
*ctx
, struct si_shader_selector
*sel
,
1788 union si_vgt_stages_key stages_key
,
1789 struct si_shader_key
*key
)
1791 struct si_context
*sctx
= (struct si_context
*)ctx
;
1793 memset(key
, 0, sizeof(*key
));
1795 switch (sel
->info
.stage
) {
1796 case MESA_SHADER_VERTEX
:
1797 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1799 if (sctx
->tes_shader
.cso
)
1801 else if (sctx
->gs_shader
.cso
) {
1803 key
->as_ngg
= stages_key
.u
.ngg
;
1805 key
->as_ngg
= stages_key
.u
.ngg
;
1806 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1808 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1809 key
->mono
.u
.vs_export_prim_id
= 1;
1812 case MESA_SHADER_TESS_CTRL
:
1813 if (sctx
->chip_class
>= GFX9
) {
1814 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
, key
, &key
->part
.tcs
.ls_prolog
);
1815 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1817 /* When the LS VGPR fix is needed, monolithic shaders
1819 * - avoid initializing EXEC in both the LS prolog
1820 * and the LS main part when !vs_needs_prolog
1821 * - remove the fixup for unused input VGPRs
1823 key
->part
.tcs
.ls_prolog
.ls_vgpr_fix
= sctx
->ls_vgpr_fix
;
1825 /* The LS output / HS input layout can be communicated
1826 * directly instead of via user SGPRs for merged LS-HS.
1827 * The LS VGPR fix prefers this too.
1829 key
->opt
.prefer_mono
= 1;
1832 key
->part
.tcs
.epilog
.prim_mode
=
1833 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1834 key
->part
.tcs
.epilog
.invoc0_tess_factors_are_def
=
1835 sel
->info
.tessfactors_are_def_in_all_invocs
;
1836 key
->part
.tcs
.epilog
.tes_reads_tess_factors
= sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1838 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1839 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1841 case MESA_SHADER_TESS_EVAL
:
1842 key
->as_ngg
= stages_key
.u
.ngg
;
1844 if (sctx
->gs_shader
.cso
)
1847 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1849 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1850 key
->mono
.u
.vs_export_prim_id
= 1;
1853 case MESA_SHADER_GEOMETRY
:
1854 if (sctx
->chip_class
>= GFX9
) {
1855 if (sctx
->tes_shader
.cso
) {
1856 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1858 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
, key
, &key
->part
.gs
.vs_prolog
);
1859 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1860 key
->part
.gs
.prolog
.gfx9_prev_is_vs
= 1;
1863 key
->as_ngg
= stages_key
.u
.ngg
;
1865 /* Merged ES-GS can have unbalanced wave usage.
1867 * ES threads are per-vertex, while GS threads are
1868 * per-primitive. So without any amplification, there
1869 * are fewer GS threads than ES threads, which can result
1870 * in empty (no-op) GS waves. With too much amplification,
1871 * there are more GS threads than ES threads, which
1872 * can result in empty (no-op) ES waves.
1874 * Non-monolithic shaders are implemented by setting EXEC
1875 * at the beginning of shader parts, and don't jump to
1876 * the end if EXEC is 0.
1878 * Monolithic shaders use conditional blocks, so they can
1879 * jump and skip empty waves of ES or GS. So set this to
1880 * always use optimized variants, which are monolithic.
1882 key
->opt
.prefer_mono
= 1;
1884 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1886 case MESA_SHADER_FRAGMENT
: {
1887 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1888 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1890 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1891 sel
->info
.colors_written
== 0x1)
1892 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1894 /* Select the shader color format based on whether
1895 * blending or alpha are needed.
1897 key
->part
.ps
.epilog
.spi_shader_col_format
=
1898 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1899 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1900 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1901 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1902 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1903 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1904 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1905 sctx
->framebuffer
.spi_shader_col_format
);
1906 key
->part
.ps
.epilog
.spi_shader_col_format
&= blend
->cb_target_enabled_4bit
;
1908 /* The output for dual source blending should have
1909 * the same format as the first output.
1911 if (blend
->dual_src_blend
) {
1912 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1913 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1916 /* If alpha-to-coverage is enabled, we have to export alpha
1917 * even if there is no color buffer.
1919 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) && blend
->alpha_to_coverage
)
1920 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1922 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1923 * to the range supported by the type if a channel has less
1924 * than 16 bits and the export format is 16_ABGR.
1926 if (sctx
->chip_class
<= GFX7
&& sctx
->family
!= CHIP_HAWAII
) {
1927 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1928 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1931 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1932 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1933 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1934 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1935 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1938 bool is_poly
= !util_prim_is_points_or_lines(sctx
->current_rast_prim
);
1939 bool is_line
= util_prim_is_lines(sctx
->current_rast_prim
);
1941 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1942 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1944 key
->part
.ps
.epilog
.alpha_to_one
= blend
->alpha_to_one
&& rs
->multisample_enable
;
1946 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1947 key
->part
.ps
.epilog
.poly_line_smoothing
=
1948 ((is_poly
&& rs
->poly_smooth
) || (is_line
&& rs
->line_smooth
)) &&
1949 sctx
->framebuffer
.nr_samples
<= 1;
1950 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1952 if (sctx
->ps_iter_samples
> 1 && sel
->info
.reads_samplemask
) {
1953 key
->part
.ps
.prolog
.samplemask_log_ps_iter
= util_logbase2(sctx
->ps_iter_samples
);
1956 if (rs
->force_persample_interp
&& rs
->multisample_enable
&&
1957 sctx
->framebuffer
.nr_samples
> 1 && sctx
->ps_iter_samples
> 1) {
1958 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1959 sel
->info
.uses_persp_center
|| sel
->info
.uses_persp_centroid
;
1961 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1962 sel
->info
.uses_linear_center
|| sel
->info
.uses_linear_centroid
;
1963 } else if (rs
->multisample_enable
&& sctx
->framebuffer
.nr_samples
> 1) {
1964 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
1965 sel
->info
.uses_persp_center
&& sel
->info
.uses_persp_centroid
;
1966 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
1967 sel
->info
.uses_linear_center
&& sel
->info
.uses_linear_centroid
;
1969 /* Make sure SPI doesn't compute more than 1 pair
1970 * of (i,j), which is the optimization here. */
1971 key
->part
.ps
.prolog
.force_persp_center_interp
= sel
->info
.uses_persp_center
+
1972 sel
->info
.uses_persp_centroid
+
1973 sel
->info
.uses_persp_sample
>
1976 key
->part
.ps
.prolog
.force_linear_center_interp
= sel
->info
.uses_linear_center
+
1977 sel
->info
.uses_linear_centroid
+
1978 sel
->info
.uses_linear_sample
>
1981 if (sel
->info
.uses_persp_opcode_interp_sample
||
1982 sel
->info
.uses_linear_opcode_interp_sample
)
1983 key
->mono
.u
.ps
.interpolate_at_sample_force_center
= 1;
1986 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
1988 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1989 if (sctx
->ps_uses_fbfetch
&& !sctx
->blitter
->running
) {
1990 struct pipe_surface
*cb0
= sctx
->framebuffer
.state
.cbufs
[0];
1991 struct pipe_resource
*tex
= cb0
->texture
;
1993 /* 1D textures are allocated and used as 2D on GFX9. */
1994 key
->mono
.u
.ps
.fbfetch_msaa
= sctx
->framebuffer
.nr_samples
> 1;
1995 key
->mono
.u
.ps
.fbfetch_is_1D
=
1996 sctx
->chip_class
!= GFX9
&&
1997 (tex
->target
== PIPE_TEXTURE_1D
|| tex
->target
== PIPE_TEXTURE_1D_ARRAY
);
1998 key
->mono
.u
.ps
.fbfetch_layered
=
1999 tex
->target
== PIPE_TEXTURE_1D_ARRAY
|| tex
->target
== PIPE_TEXTURE_2D_ARRAY
||
2000 tex
->target
== PIPE_TEXTURE_CUBE
|| tex
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
2001 tex
->target
== PIPE_TEXTURE_3D
;
2009 if (unlikely(sctx
->screen
->debug_flags
& DBG(NO_OPT_VARIANT
)))
2010 memset(&key
->opt
, 0, sizeof(key
->opt
));
2013 static void si_build_shader_variant(struct si_shader
*shader
, int thread_index
, bool low_priority
)
2015 struct si_shader_selector
*sel
= shader
->selector
;
2016 struct si_screen
*sscreen
= sel
->screen
;
2017 struct ac_llvm_compiler
*compiler
;
2018 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
2020 if (thread_index
>= 0) {
2022 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler_lowp
));
2023 compiler
= &sscreen
->compiler_lowp
[thread_index
];
2025 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2026 compiler
= &sscreen
->compiler
[thread_index
];
2031 assert(!low_priority
);
2032 compiler
= shader
->compiler_ctx_state
.compiler
;
2035 if (!compiler
->passes
)
2036 si_init_compiler(sscreen
, compiler
);
2038 if (unlikely(!si_create_shader_variant(sscreen
, compiler
, shader
, debug
))) {
2039 PRINT_ERR("Failed to build shader variant (type=%u)\n", sel
->info
.stage
);
2040 shader
->compilation_failed
= true;
2044 if (shader
->compiler_ctx_state
.is_debug_context
) {
2045 FILE *f
= open_memstream(&shader
->shader_log
, &shader
->shader_log_size
);
2047 si_shader_dump(sscreen
, shader
, NULL
, f
, false);
2052 si_shader_init_pm4_state(sscreen
, shader
);
2055 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
2057 struct si_shader
*shader
= (struct si_shader
*)job
;
2059 assert(thread_index
>= 0);
2061 si_build_shader_variant(shader
, thread_index
, true);
2064 static const struct si_shader_key zeroed
;
2066 static bool si_check_missing_main_part(struct si_screen
*sscreen
, struct si_shader_selector
*sel
,
2067 struct si_compiler_ctx_state
*compiler_state
,
2068 struct si_shader_key
*key
)
2070 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
2073 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
2078 /* We can leave the fence as permanently signaled because the
2079 * main part becomes visible globally only after it has been
2081 util_queue_fence_init(&main_part
->ready
);
2083 main_part
->selector
= sel
;
2084 main_part
->key
.as_es
= key
->as_es
;
2085 main_part
->key
.as_ls
= key
->as_ls
;
2086 main_part
->key
.as_ngg
= key
->as_ngg
;
2087 main_part
->is_monolithic
= false;
2089 if (!si_compile_shader(sscreen
, compiler_state
->compiler
, main_part
,
2090 &compiler_state
->debug
)) {
2100 * Select a shader variant according to the shader key.
2102 * \param optimized_or_none If the key describes an optimized shader variant and
2103 * the compilation isn't finished, don't select any
2104 * shader and return an error.
2106 int si_shader_select_with_key(struct si_screen
*sscreen
, struct si_shader_ctx_state
*state
,
2107 struct si_compiler_ctx_state
*compiler_state
,
2108 struct si_shader_key
*key
, int thread_index
, bool optimized_or_none
)
2110 struct si_shader_selector
*sel
= state
->cso
;
2111 struct si_shader_selector
*previous_stage_sel
= NULL
;
2112 struct si_shader
*current
= state
->current
;
2113 struct si_shader
*iter
, *shader
= NULL
;
2116 /* Check if we don't need to change anything.
2117 * This path is also used for most shaders that don't need multiple
2118 * variants, it will cost just a computation of the key and this
2120 if (likely(current
&& memcmp(¤t
->key
, key
, sizeof(*key
)) == 0)) {
2121 if (unlikely(!util_queue_fence_is_signalled(¤t
->ready
))) {
2122 if (current
->is_optimized
) {
2123 if (optimized_or_none
)
2126 memset(&key
->opt
, 0, sizeof(key
->opt
));
2127 goto current_not_ready
;
2130 util_queue_fence_wait(¤t
->ready
);
2133 return current
->compilation_failed
? -1 : 0;
2137 /* This must be done before the mutex is locked, because async GS
2138 * compilation calls this function too, and therefore must enter
2141 * Only wait if we are in a draw call. Don't wait if we are
2142 * in a compiler thread.
2144 if (thread_index
< 0)
2145 util_queue_fence_wait(&sel
->ready
);
2147 simple_mtx_lock(&sel
->mutex
);
2149 /* Find the shader variant. */
2150 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
2151 /* Don't check the "current" shader. We checked it above. */
2152 if (current
!= iter
&& memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
2153 simple_mtx_unlock(&sel
->mutex
);
2155 if (unlikely(!util_queue_fence_is_signalled(&iter
->ready
))) {
2156 /* If it's an optimized shader and its compilation has
2157 * been started but isn't done, use the unoptimized
2158 * shader so as not to cause a stall due to compilation.
2160 if (iter
->is_optimized
) {
2161 if (optimized_or_none
)
2163 memset(&key
->opt
, 0, sizeof(key
->opt
));
2167 util_queue_fence_wait(&iter
->ready
);
2170 if (iter
->compilation_failed
) {
2171 return -1; /* skip the draw call */
2174 state
->current
= iter
;
2179 /* Build a new shader. */
2180 shader
= CALLOC_STRUCT(si_shader
);
2182 simple_mtx_unlock(&sel
->mutex
);
2186 util_queue_fence_init(&shader
->ready
);
2188 shader
->selector
= sel
;
2190 shader
->compiler_ctx_state
= *compiler_state
;
2192 /* If this is a merged shader, get the first shader's selector. */
2193 if (sscreen
->info
.chip_class
>= GFX9
) {
2194 if (sel
->info
.stage
== MESA_SHADER_TESS_CTRL
)
2195 previous_stage_sel
= key
->part
.tcs
.ls
;
2196 else if (sel
->info
.stage
== MESA_SHADER_GEOMETRY
)
2197 previous_stage_sel
= key
->part
.gs
.es
;
2199 /* We need to wait for the previous shader. */
2200 if (previous_stage_sel
&& thread_index
< 0)
2201 util_queue_fence_wait(&previous_stage_sel
->ready
);
2204 bool is_pure_monolithic
=
2205 sscreen
->use_monolithic_shaders
|| memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
2207 /* Compile the main shader part if it doesn't exist. This can happen
2208 * if the initial guess was wrong.
2210 * The prim discard CS doesn't need the main shader part.
2212 if (!is_pure_monolithic
&& !key
->opt
.vs_as_prim_discard_cs
) {
2215 /* Make sure the main shader part is present. This is needed
2216 * for shaders that can be compiled as VS, LS, or ES, and only
2217 * one of them is compiled at creation.
2219 * It is also needed for GS, which can be compiled as non-NGG
2222 * For merged shaders, check that the starting shader's main
2225 if (previous_stage_sel
) {
2226 struct si_shader_key shader1_key
= zeroed
;
2228 if (sel
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
2229 shader1_key
.as_ls
= 1;
2230 } else if (sel
->info
.stage
== MESA_SHADER_GEOMETRY
) {
2231 shader1_key
.as_es
= 1;
2232 shader1_key
.as_ngg
= key
->as_ngg
; /* for Wave32 vs Wave64 */
2237 simple_mtx_lock(&previous_stage_sel
->mutex
);
2238 ok
= si_check_missing_main_part(sscreen
, previous_stage_sel
, compiler_state
, &shader1_key
);
2239 simple_mtx_unlock(&previous_stage_sel
->mutex
);
2243 ok
= si_check_missing_main_part(sscreen
, sel
, compiler_state
, key
);
2248 simple_mtx_unlock(&sel
->mutex
);
2249 return -ENOMEM
; /* skip the draw call */
2253 /* Keep the reference to the 1st shader of merged shaders, so that
2254 * Gallium can't destroy it before we destroy the 2nd shader.
2256 * Set sctx = NULL, because it's unused if we're not releasing
2257 * the shader, and we don't have any sctx here.
2259 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
, previous_stage_sel
);
2261 /* Monolithic-only shaders don't make a distinction between optimized
2262 * and unoptimized. */
2263 shader
->is_monolithic
=
2264 is_pure_monolithic
|| memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2266 /* The prim discard CS is always optimized. */
2267 shader
->is_optimized
= (!is_pure_monolithic
|| key
->opt
.vs_as_prim_discard_cs
) &&
2268 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2270 /* If it's an optimized shader, compile it asynchronously. */
2271 if (shader
->is_optimized
&& thread_index
< 0) {
2272 /* Compile it asynchronously. */
2273 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
, shader
, &shader
->ready
,
2274 si_build_shader_variant_low_priority
, NULL
, 0);
2276 /* Add only after the ready fence was reset, to guard against a
2277 * race with si_bind_XX_shader. */
2278 if (!sel
->last_variant
) {
2279 sel
->first_variant
= shader
;
2280 sel
->last_variant
= shader
;
2282 sel
->last_variant
->next_variant
= shader
;
2283 sel
->last_variant
= shader
;
2286 /* Use the default (unoptimized) shader for now. */
2287 memset(&key
->opt
, 0, sizeof(key
->opt
));
2288 simple_mtx_unlock(&sel
->mutex
);
2290 if (sscreen
->options
.sync_compile
)
2291 util_queue_fence_wait(&shader
->ready
);
2293 if (optimized_or_none
)
2298 /* Reset the fence before adding to the variant list. */
2299 util_queue_fence_reset(&shader
->ready
);
2301 if (!sel
->last_variant
) {
2302 sel
->first_variant
= shader
;
2303 sel
->last_variant
= shader
;
2305 sel
->last_variant
->next_variant
= shader
;
2306 sel
->last_variant
= shader
;
2309 simple_mtx_unlock(&sel
->mutex
);
2311 assert(!shader
->is_optimized
);
2312 si_build_shader_variant(shader
, thread_index
, false);
2314 util_queue_fence_signal(&shader
->ready
);
2316 if (!shader
->compilation_failed
)
2317 state
->current
= shader
;
2319 return shader
->compilation_failed
? -1 : 0;
2322 static int si_shader_select(struct pipe_context
*ctx
, struct si_shader_ctx_state
*state
,
2323 union si_vgt_stages_key stages_key
,
2324 struct si_compiler_ctx_state
*compiler_state
)
2326 struct si_context
*sctx
= (struct si_context
*)ctx
;
2327 struct si_shader_key key
;
2329 si_shader_selector_key(ctx
, state
->cso
, stages_key
, &key
);
2330 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
, &key
, -1, false);
2333 static void si_parse_next_shader_property(const struct si_shader_info
*info
, bool streamout
,
2334 struct si_shader_key
*key
)
2336 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
2338 switch (info
->stage
) {
2339 case MESA_SHADER_VERTEX
:
2340 switch (next_shader
) {
2341 case PIPE_SHADER_GEOMETRY
:
2344 case PIPE_SHADER_TESS_CTRL
:
2345 case PIPE_SHADER_TESS_EVAL
:
2349 /* If POSITION isn't written, it can only be a HW VS
2350 * if streamout is used. If streamout isn't used,
2351 * assume that it's a HW LS. (the next shader is TCS)
2352 * This heuristic is needed for separate shader objects.
2354 if (!info
->writes_position
&& !streamout
)
2359 case MESA_SHADER_TESS_EVAL
:
2360 if (next_shader
== PIPE_SHADER_GEOMETRY
|| !info
->writes_position
)
2369 * Compile the main shader part or the monolithic shader as part of
2370 * si_shader_selector initialization. Since it can be done asynchronously,
2371 * there is no way to report compile failures to applications.
2373 static void si_init_shader_selector_async(void *job
, int thread_index
)
2375 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
2376 struct si_screen
*sscreen
= sel
->screen
;
2377 struct ac_llvm_compiler
*compiler
;
2378 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
2380 assert(!debug
->debug_message
|| debug
->async
);
2381 assert(thread_index
>= 0);
2382 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2383 compiler
= &sscreen
->compiler
[thread_index
];
2385 if (!compiler
->passes
)
2386 si_init_compiler(sscreen
, compiler
);
2388 /* Serialize NIR to save memory. Monolithic shader variants
2389 * have to deserialize NIR before compilation.
2396 /* true = remove optional debugging data to increase
2397 * the likehood of getting more shader cache hits.
2398 * It also drops variable names, so we'll save more memory.
2400 nir_serialize(&blob
, sel
->nir
, true);
2401 blob_finish_get_buffer(&blob
, &sel
->nir_binary
, &size
);
2402 sel
->nir_size
= size
;
2405 /* Compile the main shader part for use with a prolog and/or epilog.
2406 * If this fails, the driver will try to compile a monolithic shader
2409 if (!sscreen
->use_monolithic_shaders
) {
2410 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
2411 unsigned char ir_sha1_cache_key
[20];
2414 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
2418 /* We can leave the fence signaled because use of the default
2419 * main part is guarded by the selector's ready fence. */
2420 util_queue_fence_init(&shader
->ready
);
2422 shader
->selector
= sel
;
2423 shader
->is_monolithic
= false;
2424 si_parse_next_shader_property(&sel
->info
, sel
->so
.num_outputs
!= 0, &shader
->key
);
2426 if (sscreen
->use_ngg
&& (!sel
->so
.num_outputs
|| sscreen
->use_ngg_streamout
) &&
2427 ((sel
->info
.stage
== MESA_SHADER_VERTEX
&& !shader
->key
.as_ls
) ||
2428 sel
->info
.stage
== MESA_SHADER_TESS_EVAL
|| sel
->info
.stage
== MESA_SHADER_GEOMETRY
))
2429 shader
->key
.as_ngg
= 1;
2432 si_get_ir_cache_key(sel
, shader
->key
.as_ngg
, shader
->key
.as_es
, ir_sha1_cache_key
);
2435 /* Try to load the shader from the shader cache. */
2436 simple_mtx_lock(&sscreen
->shader_cache_mutex
);
2438 if (si_shader_cache_load_shader(sscreen
, ir_sha1_cache_key
, shader
)) {
2439 simple_mtx_unlock(&sscreen
->shader_cache_mutex
);
2440 si_shader_dump_stats_for_shader_db(sscreen
, shader
, debug
);
2442 simple_mtx_unlock(&sscreen
->shader_cache_mutex
);
2444 /* Compile the shader if it hasn't been loaded from the cache. */
2445 if (!si_compile_shader(sscreen
, compiler
, shader
, debug
)) {
2447 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
2451 simple_mtx_lock(&sscreen
->shader_cache_mutex
);
2452 si_shader_cache_insert_shader(sscreen
, ir_sha1_cache_key
, shader
, true);
2453 simple_mtx_unlock(&sscreen
->shader_cache_mutex
);
2456 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
2458 /* Unset "outputs_written" flags for outputs converted to
2459 * DEFAULT_VAL, so that later inter-shader optimizations don't
2460 * try to eliminate outputs that don't exist in the final
2463 * This is only done if non-monolithic shaders are enabled.
2465 if ((sel
->info
.stage
== MESA_SHADER_VERTEX
|| sel
->info
.stage
== MESA_SHADER_TESS_EVAL
) &&
2466 !shader
->key
.as_ls
&& !shader
->key
.as_es
) {
2469 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2470 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
2472 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
2475 unsigned semantic
= sel
->info
.output_semantic
[i
];
2478 if (semantic
< VARYING_SLOT_MAX
&&
2479 semantic
!= VARYING_SLOT_POS
&&
2480 semantic
!= VARYING_SLOT_PSIZ
&&
2481 semantic
!= VARYING_SLOT_CLIP_VERTEX
&&
2482 semantic
!= VARYING_SLOT_EDGE
) {
2483 id
= si_shader_io_get_unique_index(semantic
, true);
2484 sel
->outputs_written_before_ps
&= ~(1ull << id
);
2490 /* The GS copy shader is always pre-compiled. */
2491 if (sel
->info
.stage
== MESA_SHADER_GEOMETRY
&&
2492 (!sscreen
->use_ngg
|| !sscreen
->use_ngg_streamout
|| /* also for PRIMITIVES_GENERATED */
2493 sel
->tess_turns_off_ngg
)) {
2494 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, compiler
, sel
, debug
);
2495 if (!sel
->gs_copy_shader
) {
2496 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
2500 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
2503 /* Free NIR. We only keep serialized NIR after this point. */
2505 ralloc_free(sel
->nir
);
2510 void si_schedule_initial_compile(struct si_context
*sctx
, gl_shader_stage stage
,
2511 struct util_queue_fence
*ready_fence
,
2512 struct si_compiler_ctx_state
*compiler_ctx_state
, void *job
,
2513 util_queue_execute_func execute
)
2515 util_queue_fence_init(ready_fence
);
2517 struct util_async_debug_callback async_debug
;
2518 bool debug
= (sctx
->debug
.debug_message
&& !sctx
->debug
.async
) || sctx
->is_debug
||
2519 si_can_dump_shader(sctx
->screen
, stage
);
2522 u_async_debug_init(&async_debug
);
2523 compiler_ctx_state
->debug
= async_debug
.base
;
2526 util_queue_add_job(&sctx
->screen
->shader_compiler_queue
, job
, ready_fence
, execute
, NULL
, 0);
2529 util_queue_fence_wait(ready_fence
);
2530 u_async_debug_drain(&async_debug
, &sctx
->debug
);
2531 u_async_debug_cleanup(&async_debug
);
2534 if (sctx
->screen
->options
.sync_compile
)
2535 util_queue_fence_wait(ready_fence
);
2538 /* Return descriptor slot usage masks from the given shader info. */
2539 void si_get_active_slot_masks(const struct si_shader_info
*info
, uint64_t *const_and_shader_buffers
,
2540 uint64_t *samplers_and_images
)
2542 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_msaa_images
, num_samplers
;
2544 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
2545 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
2546 /* two 8-byte images share one 16-byte slot */
2547 num_images
= align(util_last_bit(info
->images_declared
), 2);
2548 num_msaa_images
= align(util_last_bit(info
->msaa_images_declared
), 2);
2549 num_samplers
= util_last_bit(info
->samplers_declared
);
2551 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2552 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
2553 *const_and_shader_buffers
= u_bit_consecutive64(start
, num_shaderbufs
+ num_constbufs
);
2556 * - fmask[last] ... fmask[0] go to [15-last .. 15]
2557 * - image[last] ... image[0] go to [31-last .. 31]
2558 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
2560 * FMASKs for images are placed separately, because MSAA images are rare,
2561 * and so we can benefit from a better cache hit rate if we keep image
2562 * descriptors together.
2564 if (num_msaa_images
)
2565 num_images
= SI_NUM_IMAGES
+ num_msaa_images
; /* add FMASK descriptors */
2567 start
= si_get_image_slot(num_images
- 1) / 2;
2568 *samplers_and_images
= u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
2571 static void *si_create_shader_selector(struct pipe_context
*ctx
,
2572 const struct pipe_shader_state
*state
)
2574 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
2575 struct si_context
*sctx
= (struct si_context
*)ctx
;
2576 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
2582 sel
->screen
= sscreen
;
2583 sel
->compiler_ctx_state
.debug
= sctx
->debug
;
2584 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
2586 sel
->so
= state
->stream_output
;
2588 if (state
->type
== PIPE_SHADER_IR_TGSI
) {
2589 sel
->nir
= tgsi_to_nir(state
->tokens
, ctx
->screen
, true);
2591 assert(state
->type
== PIPE_SHADER_IR_NIR
);
2592 sel
->nir
= state
->ir
.nir
;
2595 si_nir_scan_shader(sel
->nir
, &sel
->info
);
2597 const enum pipe_shader_type type
= pipe_shader_type_from_mesa(sel
->info
.stage
);
2598 sel
->const_and_shader_buf_descriptors_index
=
2599 si_const_and_shader_buffer_descriptors_idx(type
);
2600 sel
->sampler_and_images_descriptors_index
=
2601 si_sampler_and_image_descriptors_idx(type
);
2603 p_atomic_inc(&sscreen
->num_shaders_created
);
2604 si_get_active_slot_masks(&sel
->info
, &sel
->active_const_and_shader_buffers
,
2605 &sel
->active_samplers_and_images
);
2607 /* Record which streamout buffers are enabled. */
2608 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
2609 sel
->enabled_streamout_buffer_mask
|= (1 << sel
->so
.output
[i
].output_buffer
)
2610 << (sel
->so
.output
[i
].stream
* 4);
2613 sel
->num_vs_inputs
=
2614 sel
->info
.stage
== MESA_SHADER_VERTEX
&& !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
]
2615 ? sel
->info
.num_inputs
2617 sel
->num_vbos_in_user_sgprs
= MIN2(sel
->num_vs_inputs
, sscreen
->num_vbos_in_user_sgprs
);
2619 /* The prolog is a no-op if there are no inputs. */
2620 sel
->vs_needs_prolog
= sel
->info
.stage
== MESA_SHADER_VERTEX
&& sel
->info
.num_inputs
&&
2621 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
];
2623 sel
->prim_discard_cs_allowed
=
2624 sel
->info
.stage
== MESA_SHADER_VERTEX
&& !sel
->info
.uses_bindless_images
&&
2625 !sel
->info
.uses_bindless_samplers
&& !sel
->info
.writes_memory
&&
2626 !sel
->info
.writes_viewport_index
&&
2627 !sel
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] && !sel
->so
.num_outputs
;
2629 switch (sel
->info
.stage
) {
2630 case MESA_SHADER_GEOMETRY
:
2631 sel
->gs_output_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
2633 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2634 sel
->rast_prim
= sel
->gs_output_prim
;
2635 if (util_rast_prim_is_triangles(sel
->rast_prim
))
2636 sel
->rast_prim
= PIPE_PRIM_TRIANGLES
;
2638 sel
->gs_max_out_vertices
= sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
2639 sel
->gs_num_invocations
= sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2640 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2641 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
* sel
->gs_max_out_vertices
;
2643 sel
->max_gs_stream
= 0;
2644 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2645 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
, sel
->so
.output
[i
].stream
);
2647 sel
->gs_input_verts_per_prim
=
2648 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2650 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation so
2651 * we can't split workgroups. Disable ngg if any of the following conditions is true:
2652 * - num_invocations * gs_max_out_vertices > 256
2653 * - LDS usage is too high
2655 sel
->tess_turns_off_ngg
= sscreen
->info
.chip_class
>= GFX10
&&
2656 (sel
->gs_num_invocations
* sel
->gs_max_out_vertices
> 256 ||
2657 sel
->gs_num_invocations
* sel
->gs_max_out_vertices
*
2658 (sel
->info
.num_outputs
* 4 + 1) > 6500 /* max dw per GS primitive */);
2661 case MESA_SHADER_TESS_CTRL
:
2662 /* Always reserve space for these. */
2663 sel
->patch_outputs_written
|=
2664 (1ull << si_shader_io_get_unique_index_patch(VARYING_SLOT_TESS_LEVEL_INNER
)) |
2665 (1ull << si_shader_io_get_unique_index_patch(VARYING_SLOT_TESS_LEVEL_OUTER
));
2667 case MESA_SHADER_VERTEX
:
2668 case MESA_SHADER_TESS_EVAL
:
2669 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2670 unsigned semantic
= sel
->info
.output_semantic
[i
];
2672 if (semantic
== VARYING_SLOT_TESS_LEVEL_INNER
||
2673 semantic
== VARYING_SLOT_TESS_LEVEL_OUTER
||
2674 (semantic
>= VARYING_SLOT_PATCH0
&& semantic
< VARYING_SLOT_TESS_MAX
)) {
2675 sel
->patch_outputs_written
|= 1ull << si_shader_io_get_unique_index_patch(semantic
);
2676 } else if (semantic
< VARYING_SLOT_MAX
&&
2677 semantic
!= VARYING_SLOT_EDGE
) {
2678 sel
->outputs_written
|= 1ull << si_shader_io_get_unique_index(semantic
, false);
2679 sel
->outputs_written_before_ps
|= 1ull
2680 << si_shader_io_get_unique_index(semantic
, true);
2683 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2684 sel
->lshs_vertex_stride
= sel
->esgs_itemsize
;
2686 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2687 * will start on a different bank. (except for the maximum 32*16).
2689 if (sel
->lshs_vertex_stride
< 32 * 16)
2690 sel
->lshs_vertex_stride
+= 4;
2692 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2693 * conflicts, i.e. each vertex will start at a different bank.
2695 if (sctx
->chip_class
>= GFX9
)
2696 sel
->esgs_itemsize
+= 4;
2698 assert(((sel
->esgs_itemsize
/ 4) & C_028AAC_ITEMSIZE
) == 0);
2701 if (sel
->info
.properties
[TGSI_PROPERTY_TES_POINT_MODE
])
2702 sel
->rast_prim
= PIPE_PRIM_POINTS
;
2703 else if (sel
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] == PIPE_PRIM_LINES
)
2704 sel
->rast_prim
= PIPE_PRIM_LINE_STRIP
;
2706 sel
->rast_prim
= PIPE_PRIM_TRIANGLES
;
2709 case MESA_SHADER_FRAGMENT
:
2710 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2711 unsigned semantic
= sel
->info
.input_semantic
[i
];
2713 if (semantic
< VARYING_SLOT_MAX
&&
2714 semantic
!= VARYING_SLOT_PNTC
) {
2715 sel
->inputs_read
|= 1ull << si_shader_io_get_unique_index(semantic
, true);
2719 for (i
= 0; i
< 8; i
++)
2720 if (sel
->info
.colors_written
& (1 << i
))
2721 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2723 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2724 if (sel
->info
.input_semantic
[i
] == VARYING_SLOT_COL0
)
2725 sel
->color_attr_index
[0] = i
;
2726 else if (sel
->info
.input_semantic
[i
] == VARYING_SLOT_COL1
)
2727 sel
->color_attr_index
[1] = i
;
2733 sel
->ngg_culling_allowed
=
2734 sscreen
->info
.chip_class
>= GFX10
&&
2735 sscreen
->info
.has_dedicated_vram
&&
2736 sscreen
->use_ngg_culling
&&
2737 (sel
->info
.stage
== MESA_SHADER_VERTEX
||
2738 (sel
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
2739 (sscreen
->always_use_ngg_culling_all
||
2740 sscreen
->always_use_ngg_culling_tess
))) &&
2741 sel
->info
.writes_position
&&
2742 !sel
->info
.writes_viewport_index
&& /* cull only against viewport 0 */
2743 !sel
->info
.writes_memory
&& !sel
->so
.num_outputs
&&
2744 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
] &&
2745 !sel
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
2747 /* PA_CL_VS_OUT_CNTL */
2748 if (sctx
->chip_class
<= GFX9
)
2749 sel
->pa_cl_vs_out_cntl
= si_get_vs_out_cntl(sel
, false);
2751 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
? SIX_BITS
: sel
->info
.clipdist_writemask
;
2752 sel
->culldist_mask
= sel
->info
.culldist_writemask
<< sel
->info
.num_written_clipdistance
;
2754 /* DB_SHADER_CONTROL */
2755 sel
->db_shader_control
= S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2756 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2757 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2758 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2760 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2761 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2762 sel
->db_shader_control
|= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2764 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2765 sel
->db_shader_control
|= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2769 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2771 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2772 * --|-----------|------------|------------|--------------------|-------------------|-------------
2773 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2774 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2775 * 2 | false | true | n/a | LateZ | 1 | 0
2776 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2777 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2779 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2780 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2782 * Don't use ReZ without profiling !!!
2784 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2787 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2789 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2790 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2791 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
2792 } else if (sel
->info
.writes_memory
) {
2794 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) | S_02880C_EXEC_ON_HIER_FAIL(1);
2797 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2800 if (sel
->info
.properties
[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
])
2801 sel
->db_shader_control
|= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2803 (void)simple_mtx_init(&sel
->mutex
, mtx_plain
);
2805 si_schedule_initial_compile(sctx
, sel
->info
.stage
, &sel
->ready
, &sel
->compiler_ctx_state
,
2806 sel
, si_init_shader_selector_async
);
2810 static void *si_create_shader(struct pipe_context
*ctx
, const struct pipe_shader_state
*state
)
2812 struct si_context
*sctx
= (struct si_context
*)ctx
;
2813 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
2815 struct si_shader_selector
*sel
= (struct si_shader_selector
*)util_live_shader_cache_get(
2816 ctx
, &sscreen
->live_shader_cache
, state
, &cache_hit
);
2818 if (sel
&& cache_hit
&& sctx
->debug
.debug_message
) {
2819 if (sel
->main_shader_part
)
2820 si_shader_dump_stats_for_shader_db(sscreen
, sel
->main_shader_part
, &sctx
->debug
);
2821 if (sel
->main_shader_part_ls
)
2822 si_shader_dump_stats_for_shader_db(sscreen
, sel
->main_shader_part_ls
, &sctx
->debug
);
2823 if (sel
->main_shader_part_es
)
2824 si_shader_dump_stats_for_shader_db(sscreen
, sel
->main_shader_part_es
, &sctx
->debug
);
2825 if (sel
->main_shader_part_ngg
)
2826 si_shader_dump_stats_for_shader_db(sscreen
, sel
->main_shader_part_ngg
, &sctx
->debug
);
2827 if (sel
->main_shader_part_ngg_es
)
2828 si_shader_dump_stats_for_shader_db(sscreen
, sel
->main_shader_part_ngg_es
, &sctx
->debug
);
2833 static void si_update_streamout_state(struct si_context
*sctx
)
2835 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
2837 if (!shader_with_so
)
2840 sctx
->streamout
.enabled_stream_buffers_mask
= shader_with_so
->enabled_streamout_buffer_mask
;
2841 sctx
->streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
2844 static void si_update_clip_regs(struct si_context
*sctx
, struct si_shader_selector
*old_hw_vs
,
2845 struct si_shader
*old_hw_vs_variant
,
2846 struct si_shader_selector
*next_hw_vs
,
2847 struct si_shader
*next_hw_vs_variant
)
2851 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
2852 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
2853 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
2854 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
2855 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
|| !old_hw_vs_variant
||
2856 !next_hw_vs_variant
||
2857 old_hw_vs_variant
->key
.opt
.clip_disable
!= next_hw_vs_variant
->key
.opt
.clip_disable
))
2858 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
2861 static void si_update_common_shader_state(struct si_context
*sctx
)
2863 sctx
->uses_bindless_samplers
= si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
2864 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
2865 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
2866 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
2867 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
2868 sctx
->uses_bindless_images
= si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
2869 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
2870 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
2871 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
2872 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
2873 sctx
->do_update_shaders
= true;
2876 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2878 struct si_context
*sctx
= (struct si_context
*)ctx
;
2879 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2880 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2881 struct si_shader_selector
*sel
= state
;
2883 if (sctx
->vs_shader
.cso
== sel
)
2886 sctx
->vs_shader
.cso
= sel
;
2887 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2888 sctx
->num_vs_blit_sgprs
= sel
? sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
] : 0;
2890 if (si_update_ngg(sctx
))
2891 si_shader_change_notify(sctx
);
2893 si_update_common_shader_state(sctx
);
2894 si_update_vs_viewport_state(sctx
);
2895 si_set_active_descriptors_for_shader(sctx
, sel
);
2896 si_update_streamout_state(sctx
);
2897 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
, si_get_vs(sctx
)->cso
,
2898 si_get_vs_state(sctx
));
2901 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
2903 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
2904 (sctx
->tes_shader
.cso
&& sctx
->tes_shader
.cso
->info
.uses_primid
) ||
2905 (sctx
->tcs_shader
.cso
&& sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
2906 (sctx
->gs_shader
.cso
&& sctx
->gs_shader
.cso
->info
.uses_primid
) ||
2907 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
);
2910 bool si_update_ngg(struct si_context
*sctx
)
2912 if (!sctx
->screen
->use_ngg
) {
2917 bool new_ngg
= true;
2919 if (sctx
->gs_shader
.cso
&& sctx
->tes_shader
.cso
&& sctx
->gs_shader
.cso
->tess_turns_off_ngg
) {
2921 } else if (!sctx
->screen
->use_ngg_streamout
) {
2922 struct si_shader_selector
*last
= si_get_vs(sctx
)->cso
;
2924 if ((last
&& last
->so
.num_outputs
) || sctx
->streamout
.prims_gen_query_enabled
)
2928 if (new_ngg
!= sctx
->ngg
) {
2929 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
2930 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
2933 if (sctx
->chip_class
== GFX10
&& !new_ngg
)
2934 sctx
->flags
|= SI_CONTEXT_VGT_FLUSH
;
2936 sctx
->ngg
= new_ngg
;
2937 sctx
->last_gs_out_prim
= -1; /* reset this so that it gets updated */
2943 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
2945 struct si_context
*sctx
= (struct si_context
*)ctx
;
2946 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2947 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2948 struct si_shader_selector
*sel
= state
;
2949 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
2952 if (sctx
->gs_shader
.cso
== sel
)
2955 sctx
->gs_shader
.cso
= sel
;
2956 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2957 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
2959 si_update_common_shader_state(sctx
);
2960 sctx
->last_gs_out_prim
= -1; /* reset this so that it gets updated */
2962 ngg_changed
= si_update_ngg(sctx
);
2963 if (ngg_changed
|| enable_changed
)
2964 si_shader_change_notify(sctx
);
2965 if (enable_changed
) {
2966 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2967 si_update_tess_uses_prim_id(sctx
);
2969 si_update_vs_viewport_state(sctx
);
2970 si_set_active_descriptors_for_shader(sctx
, sel
);
2971 si_update_streamout_state(sctx
);
2972 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
, si_get_vs(sctx
)->cso
,
2973 si_get_vs_state(sctx
));
2976 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
2978 struct si_context
*sctx
= (struct si_context
*)ctx
;
2979 struct si_shader_selector
*sel
= state
;
2980 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
2982 if (sctx
->tcs_shader
.cso
== sel
)
2985 sctx
->tcs_shader
.cso
= sel
;
2986 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2987 si_update_tess_uses_prim_id(sctx
);
2989 si_update_common_shader_state(sctx
);
2992 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
2994 si_set_active_descriptors_for_shader(sctx
, sel
);
2997 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
2999 struct si_context
*sctx
= (struct si_context
*)ctx
;
3000 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
3001 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
3002 struct si_shader_selector
*sel
= state
;
3003 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
3005 if (sctx
->tes_shader
.cso
== sel
)
3008 sctx
->tes_shader
.cso
= sel
;
3009 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
3010 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
3011 si_update_tess_uses_prim_id(sctx
);
3013 si_update_common_shader_state(sctx
);
3014 sctx
->last_gs_out_prim
= -1; /* reset this so that it gets updated */
3016 bool ngg_changed
= si_update_ngg(sctx
);
3017 if (ngg_changed
|| enable_changed
)
3018 si_shader_change_notify(sctx
);
3020 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
3021 si_update_vs_viewport_state(sctx
);
3022 si_set_active_descriptors_for_shader(sctx
, sel
);
3023 si_update_streamout_state(sctx
);
3024 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
, si_get_vs(sctx
)->cso
,
3025 si_get_vs_state(sctx
));
3028 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
3030 struct si_context
*sctx
= (struct si_context
*)ctx
;
3031 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
3032 struct si_shader_selector
*sel
= state
;
3034 /* skip if supplied shader is one already in use */
3038 sctx
->ps_shader
.cso
= sel
;
3039 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
3041 si_update_common_shader_state(sctx
);
3043 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
3044 si_update_tess_uses_prim_id(sctx
);
3046 if (!old_sel
|| old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
3047 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3049 if (sctx
->screen
->has_out_of_order_rast
&&
3050 (!old_sel
|| old_sel
->info
.writes_memory
!= sel
->info
.writes_memory
||
3051 old_sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] !=
3052 sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]))
3053 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3055 si_set_active_descriptors_for_shader(sctx
, sel
);
3056 si_update_ps_colorbuf0_slot(sctx
);
3059 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
3061 if (shader
->is_optimized
) {
3062 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
, &shader
->ready
);
3065 util_queue_fence_destroy(&shader
->ready
);
3068 /* If destroyed shaders were not unbound, the next compiled
3069 * shader variant could get the same pointer address and so
3070 * binding it to the same shader stage would be considered
3071 * a no-op, causing random behavior.
3073 switch (shader
->selector
->info
.stage
) {
3074 case MESA_SHADER_VERTEX
:
3075 if (shader
->key
.as_ls
) {
3076 assert(sctx
->chip_class
<= GFX8
);
3077 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
3078 } else if (shader
->key
.as_es
) {
3079 assert(sctx
->chip_class
<= GFX8
);
3080 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3081 } else if (shader
->key
.as_ngg
) {
3082 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3084 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3087 case MESA_SHADER_TESS_CTRL
:
3088 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
3090 case MESA_SHADER_TESS_EVAL
:
3091 if (shader
->key
.as_es
) {
3092 assert(sctx
->chip_class
<= GFX8
);
3093 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3094 } else if (shader
->key
.as_ngg
) {
3095 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3097 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3100 case MESA_SHADER_GEOMETRY
:
3101 if (shader
->is_gs_copy_shader
)
3102 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3104 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3106 case MESA_SHADER_FRAGMENT
:
3107 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
3113 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
3114 si_shader_destroy(shader
);
3118 static void si_destroy_shader_selector(struct pipe_context
*ctx
, void *cso
)
3120 struct si_context
*sctx
= (struct si_context
*)ctx
;
3121 struct si_shader_selector
*sel
= (struct si_shader_selector
*)cso
;
3122 struct si_shader
*p
= sel
->first_variant
, *c
;
3123 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
3124 [MESA_SHADER_VERTEX
] = &sctx
->vs_shader
,
3125 [MESA_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
3126 [MESA_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
3127 [MESA_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
3128 [MESA_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
3131 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
3133 if (current_shader
[sel
->info
.stage
]->cso
== sel
) {
3134 current_shader
[sel
->info
.stage
]->cso
= NULL
;
3135 current_shader
[sel
->info
.stage
]->current
= NULL
;
3139 c
= p
->next_variant
;
3140 si_delete_shader(sctx
, p
);
3144 if (sel
->main_shader_part
)
3145 si_delete_shader(sctx
, sel
->main_shader_part
);
3146 if (sel
->main_shader_part_ls
)
3147 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
3148 if (sel
->main_shader_part_es
)
3149 si_delete_shader(sctx
, sel
->main_shader_part_es
);
3150 if (sel
->main_shader_part_ngg
)
3151 si_delete_shader(sctx
, sel
->main_shader_part_ngg
);
3152 if (sel
->gs_copy_shader
)
3153 si_delete_shader(sctx
, sel
->gs_copy_shader
);
3155 util_queue_fence_destroy(&sel
->ready
);
3156 simple_mtx_destroy(&sel
->mutex
);
3157 ralloc_free(sel
->nir
);
3158 free(sel
->nir_binary
);
3162 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
3164 struct si_context
*sctx
= (struct si_context
*)ctx
;
3165 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
3167 si_shader_selector_reference(sctx
, &sel
, NULL
);
3170 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
, struct si_shader
*vs
,
3171 unsigned semantic
, enum glsl_interp_mode interpolate
)
3173 struct si_shader_info
*vsinfo
= &vs
->selector
->info
;
3174 unsigned offset
, ps_input_cntl
= 0;
3176 if (interpolate
== INTERP_MODE_FLAT
||
3177 (interpolate
== INTERP_MODE_COLOR
&& sctx
->flatshade
) ||
3178 semantic
== VARYING_SLOT_PRIMITIVE_ID
)
3179 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
3181 if (semantic
== VARYING_SLOT_PNTC
||
3182 (semantic
>= VARYING_SLOT_TEX0
&& semantic
<= VARYING_SLOT_TEX7
&&
3183 sctx
->sprite_coord_enable
& (1 << (semantic
- VARYING_SLOT_TEX0
)))) {
3184 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
3187 int vs_slot
= vsinfo
->output_semantic_to_slot
[semantic
];
3189 offset
= vs
->info
.vs_output_param_offset
[vs_slot
];
3191 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
3192 /* The input is loaded from parameter memory. */
3193 ps_input_cntl
|= S_028644_OFFSET(offset
);
3194 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3195 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
3196 /* This can happen with depth-only rendering. */
3199 /* The input is a DEFAULT_VAL constant. */
3200 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
3201 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
3202 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
3205 ps_input_cntl
= S_028644_OFFSET(0x20) | S_028644_DEFAULT_VAL(offset
);
3208 /* VS output not found. */
3209 if (semantic
== VARYING_SLOT_PRIMITIVE_ID
) {
3210 /* PrimID is written after the last output when HW VS is used. */
3211 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
3212 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3213 /* No corresponding output found, load defaults into input.
3214 * Don't set any other bits.
3215 * (FLAT_SHADE=1 completely changes behavior) */
3216 ps_input_cntl
= S_028644_OFFSET(0x20);
3217 /* D3D 9 behaviour. GL is undefined */
3218 if (semantic
== VARYING_SLOT_COL0
)
3219 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
3223 return ps_input_cntl
;
3226 static void si_emit_spi_map(struct si_context
*sctx
)
3228 struct si_shader
*ps
= sctx
->ps_shader
.current
;
3229 struct si_shader
*vs
= si_get_vs_state(sctx
);
3230 struct si_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
3231 unsigned i
, num_interp
, num_written
= 0;
3232 unsigned spi_ps_input_cntl
[32];
3234 if (!ps
|| !ps
->selector
->info
.num_inputs
)
3237 num_interp
= si_get_ps_num_interp(ps
);
3238 assert(num_interp
> 0);
3240 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
3241 unsigned semantic
= psinfo
->input_semantic
[i
];
3242 unsigned interpolate
= psinfo
->input_interpolate
[i
];
3244 spi_ps_input_cntl
[num_written
++] = si_get_ps_input_cntl(sctx
, vs
, semantic
, interpolate
);
3247 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
3248 for (i
= 0; i
< 2; i
++) {
3249 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
3252 unsigned semantic
= VARYING_SLOT_BFC0
+ i
;
3253 spi_ps_input_cntl
[num_written
++] = si_get_ps_input_cntl(sctx
, vs
, semantic
,
3254 psinfo
->color_interpolate
[i
]);
3257 assert(num_interp
== num_written
);
3259 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3260 /* Dota 2: Only ~16% of SPI map updates set different values. */
3261 /* Talos: Only ~9% of SPI map updates set different values. */
3262 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
3263 radeon_opt_set_context_regn(sctx
, R_028644_SPI_PS_INPUT_CNTL_0
, spi_ps_input_cntl
,
3264 sctx
->tracked_regs
.spi_ps_input_cntl
, num_interp
);
3266 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
3267 sctx
->context_roll
= true;
3271 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3273 static void si_cs_preamble_add_vgt_flush(struct si_context
*sctx
)
3275 /* We shouldn't get here if registers are shadowed. */
3276 assert(!sctx
->shadowed_regs
);
3278 if (sctx
->cs_preamble_has_vgt_flush
)
3281 /* Done by Vulkan before VGT_FLUSH. */
3282 si_pm4_cmd_add(sctx
->cs_preamble_state
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3283 si_pm4_cmd_add(sctx
->cs_preamble_state
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3285 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3286 si_pm4_cmd_add(sctx
->cs_preamble_state
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3287 si_pm4_cmd_add(sctx
->cs_preamble_state
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3288 sctx
->cs_preamble_has_vgt_flush
= true;
3292 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3294 static void si_emit_vgt_flush(struct radeon_cmdbuf
*cs
)
3296 /* This is required before VGT_FLUSH. */
3297 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3298 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3300 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3301 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3302 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3305 /* Initialize state related to ESGS / GSVS ring buffers */
3306 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
3308 struct si_shader_selector
*es
=
3309 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
3310 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
3311 struct si_pm4_state
*pm4
;
3313 /* Chip constants. */
3314 unsigned num_se
= sctx
->screen
->info
.max_se
;
3315 unsigned wave_size
= 64;
3316 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
3317 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3318 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3320 unsigned gs_vertex_reuse
= (sctx
->chip_class
>= GFX8
? 32 : 16) * num_se
;
3321 unsigned alignment
= 256 * num_se
;
3322 /* The maximum size is 63.999 MB per SE. */
3323 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
3325 /* Calculate the minimum size. */
3326 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
* wave_size
, alignment
);
3328 /* These are recommended sizes, not minimum sizes. */
3329 unsigned esgs_ring_size
=
3330 max_gs_waves
* 2 * wave_size
* es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
3331 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
* gs
->max_gsvs_emit_size
;
3333 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
3334 esgs_ring_size
= align(esgs_ring_size
, alignment
);
3335 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
3337 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
3338 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
3340 /* Some rings don't have to be allocated if shaders don't use them.
3341 * (e.g. no varyings between ES and GS or GS and VS)
3343 * GFX9 doesn't have the ESGS ring.
3345 bool update_esgs
= sctx
->chip_class
<= GFX8
&& esgs_ring_size
&&
3346 (!sctx
->esgs_ring
|| sctx
->esgs_ring
->width0
< esgs_ring_size
);
3348 gsvs_ring_size
&& (!sctx
->gsvs_ring
|| sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
3350 if (!update_esgs
&& !update_gsvs
)
3354 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
3356 pipe_aligned_buffer_create(sctx
->b
.screen
, SI_RESOURCE_FLAG_UNMAPPABLE
, PIPE_USAGE_DEFAULT
,
3357 esgs_ring_size
, sctx
->screen
->info
.pte_fragment_size
);
3358 if (!sctx
->esgs_ring
)
3363 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
3365 pipe_aligned_buffer_create(sctx
->b
.screen
, SI_RESOURCE_FLAG_UNMAPPABLE
, PIPE_USAGE_DEFAULT
,
3366 gsvs_ring_size
, sctx
->screen
->info
.pte_fragment_size
);
3367 if (!sctx
->gsvs_ring
)
3371 /* Set ring bindings. */
3372 if (sctx
->esgs_ring
) {
3373 assert(sctx
->chip_class
<= GFX8
);
3374 si_set_ring_buffer(sctx
, SI_ES_RING_ESGS
, sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
, true,
3376 si_set_ring_buffer(sctx
, SI_GS_RING_ESGS
, sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
, false,
3379 if (sctx
->gsvs_ring
) {
3380 si_set_ring_buffer(sctx
, SI_RING_GSVS
, sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
, false,
3384 if (sctx
->shadowed_regs
) {
3385 /* These registers will be shadowed, so set them only once. */
3386 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3388 assert(sctx
->chip_class
>= GFX7
);
3390 si_emit_vgt_flush(cs
);
3392 /* Set the GS registers. */
3393 if (sctx
->esgs_ring
) {
3394 assert(sctx
->chip_class
<= GFX8
);
3395 radeon_set_uconfig_reg(cs
, R_030900_VGT_ESGS_RING_SIZE
,
3396 sctx
->esgs_ring
->width0
/ 256);
3398 if (sctx
->gsvs_ring
) {
3399 radeon_set_uconfig_reg(cs
, R_030904_VGT_GSVS_RING_SIZE
,
3400 sctx
->gsvs_ring
->width0
/ 256);
3405 /* The codepath without register shadowing. */
3406 /* Create the "cs_preamble_gs_rings" state. */
3407 pm4
= CALLOC_STRUCT(si_pm4_state
);
3411 if (sctx
->chip_class
>= GFX7
) {
3412 if (sctx
->esgs_ring
) {
3413 assert(sctx
->chip_class
<= GFX8
);
3414 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
, sctx
->esgs_ring
->width0
/ 256);
3416 if (sctx
->gsvs_ring
)
3417 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
, sctx
->gsvs_ring
->width0
/ 256);
3419 if (sctx
->esgs_ring
)
3420 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
, sctx
->esgs_ring
->width0
/ 256);
3421 if (sctx
->gsvs_ring
)
3422 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
, sctx
->gsvs_ring
->width0
/ 256);
3425 /* Set the state. */
3426 if (sctx
->cs_preamble_gs_rings
)
3427 si_pm4_free_state(sctx
, sctx
->cs_preamble_gs_rings
, ~0);
3428 sctx
->cs_preamble_gs_rings
= pm4
;
3430 si_cs_preamble_add_vgt_flush(sctx
);
3432 /* Flush the context to re-emit both cs_preamble states. */
3433 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3434 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3439 static void si_shader_lock(struct si_shader
*shader
)
3441 simple_mtx_lock(&shader
->selector
->mutex
);
3442 if (shader
->previous_stage_sel
) {
3443 assert(shader
->previous_stage_sel
!= shader
->selector
);
3444 simple_mtx_lock(&shader
->previous_stage_sel
->mutex
);
3448 static void si_shader_unlock(struct si_shader
*shader
)
3450 if (shader
->previous_stage_sel
)
3451 simple_mtx_unlock(&shader
->previous_stage_sel
->mutex
);
3452 simple_mtx_unlock(&shader
->selector
->mutex
);
3456 * @returns 1 if \p sel has been updated to use a new scratch buffer
3458 * < 0 if there was a failure
3460 static int si_update_scratch_buffer(struct si_context
*sctx
, struct si_shader
*shader
)
3462 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
3467 /* This shader doesn't need a scratch buffer */
3468 if (shader
->config
.scratch_bytes_per_wave
== 0)
3471 /* Prevent race conditions when updating:
3472 * - si_shader::scratch_bo
3473 * - si_shader::binary::code
3474 * - si_shader::previous_stage::binary::code.
3476 si_shader_lock(shader
);
3478 /* This shader is already configured to use the current
3479 * scratch buffer. */
3480 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
3481 si_shader_unlock(shader
);
3485 assert(sctx
->scratch_buffer
);
3487 /* Replace the shader bo with a new bo that has the relocs applied. */
3488 if (!si_shader_binary_upload(sctx
->screen
, shader
, scratch_va
)) {
3489 si_shader_unlock(shader
);
3493 /* Update the shader state to use the new shader bo. */
3494 si_shader_init_pm4_state(sctx
->screen
, shader
);
3496 si_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
3498 si_shader_unlock(shader
);
3502 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
3504 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
3507 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
3509 if (!sctx
->tes_shader
.cso
)
3510 return NULL
; /* tessellation disabled */
3512 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
: sctx
->fixed_func_tcs_shader
.current
;
3515 static bool si_update_scratch_relocs(struct si_context
*sctx
)
3517 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3520 /* Update the shaders, so that they are using the latest scratch.
3521 * The scratch buffer may have been changed since these shaders were
3522 * last used, so we still need to try to update them, even if they
3523 * require scratch buffers smaller than the current size.
3525 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
3529 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3531 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
3535 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3537 r
= si_update_scratch_buffer(sctx
, tcs
);
3541 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
3543 /* VS can be bound as LS, ES, or VS. */
3544 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
3548 if (sctx
->vs_shader
.current
->key
.as_ls
)
3549 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3550 else if (sctx
->vs_shader
.current
->key
.as_es
)
3551 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3552 else if (sctx
->vs_shader
.current
->key
.as_ngg
)
3553 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
3555 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3558 /* TES can be bound as ES or VS. */
3559 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
3563 if (sctx
->tes_shader
.current
->key
.as_es
)
3564 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3565 else if (sctx
->tes_shader
.current
->key
.as_ngg
)
3566 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
3568 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3574 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
3576 /* SPI_TMPRING_SIZE.WAVESIZE must be constant for each scratch buffer.
3577 * There are 2 cases to handle:
3579 * - If the current needed size is less than the maximum seen size,
3580 * use the maximum seen size, so that WAVESIZE remains the same.
3582 * - If the current needed size is greater than the maximum seen size,
3583 * the scratch buffer is reallocated, so we can increase WAVESIZE.
3585 * Shaders that set SCRATCH_EN=0 don't allocate scratch space.
3586 * Otherwise, the number of waves that can use scratch is
3587 * SPI_TMPRING_SIZE.WAVES.
3591 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
3592 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
3593 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
3595 if (sctx
->tes_shader
.cso
) {
3596 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
3597 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(si_get_tcs_current(sctx
)));
3600 sctx
->max_seen_scratch_bytes_per_wave
= MAX2(sctx
->max_seen_scratch_bytes_per_wave
, bytes
);
3602 unsigned scratch_needed_size
= sctx
->max_seen_scratch_bytes_per_wave
* sctx
->scratch_waves
;
3603 unsigned spi_tmpring_size
;
3605 if (scratch_needed_size
> 0) {
3606 if (!sctx
->scratch_buffer
|| scratch_needed_size
> sctx
->scratch_buffer
->b
.b
.width0
) {
3607 /* Create a bigger scratch buffer */
3608 si_resource_reference(&sctx
->scratch_buffer
, NULL
);
3610 sctx
->scratch_buffer
= si_aligned_buffer_create(
3611 &sctx
->screen
->b
, SI_RESOURCE_FLAG_UNMAPPABLE
, PIPE_USAGE_DEFAULT
, scratch_needed_size
,
3612 sctx
->screen
->info
.pte_fragment_size
);
3613 if (!sctx
->scratch_buffer
)
3616 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3617 si_context_add_resource_size(sctx
, &sctx
->scratch_buffer
->b
.b
);
3620 if (!si_update_scratch_relocs(sctx
))
3624 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3625 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
3626 "scratch size should already be aligned correctly.");
3628 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
3629 S_0286E8_WAVESIZE(sctx
->max_seen_scratch_bytes_per_wave
>> 10);
3630 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
3631 sctx
->spi_tmpring_size
= spi_tmpring_size
;
3632 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3637 static void si_init_tess_factor_ring(struct si_context
*sctx
)
3639 assert(!sctx
->tess_rings
);
3640 assert(((sctx
->screen
->tess_factor_ring_size
/ 4) & C_030938_SIZE
) == 0);
3642 /* The address must be aligned to 2^19, because the shader only
3643 * receives the high 13 bits.
3645 sctx
->tess_rings
= pipe_aligned_buffer_create(
3646 sctx
->b
.screen
, SI_RESOURCE_FLAG_32BIT
, PIPE_USAGE_DEFAULT
,
3647 sctx
->screen
->tess_offchip_ring_size
+ sctx
->screen
->tess_factor_ring_size
, 1 << 19);
3648 if (!sctx
->tess_rings
)
3651 uint64_t factor_va
=
3652 si_resource(sctx
->tess_rings
)->gpu_address
+ sctx
->screen
->tess_offchip_ring_size
;
3654 if (sctx
->shadowed_regs
) {
3655 /* These registers will be shadowed, so set them only once. */
3656 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3658 assert(sctx
->chip_class
>= GFX7
);
3660 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, si_resource(sctx
->tess_rings
),
3661 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3662 si_emit_vgt_flush(cs
);
3664 /* Set tessellation registers. */
3665 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
3666 S_030938_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3667 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
, factor_va
>> 8);
3668 if (sctx
->chip_class
>= GFX10
) {
3669 radeon_set_uconfig_reg(cs
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3670 S_030984_BASE_HI(factor_va
>> 40));
3671 } else if (sctx
->chip_class
== GFX9
) {
3672 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3673 S_030944_BASE_HI(factor_va
>> 40));
3675 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3676 sctx
->screen
->vgt_hs_offchip_param
);
3680 /* The codepath without register shadowing. */
3681 si_cs_preamble_add_vgt_flush(sctx
);
3683 /* Append these registers to the init config state. */
3684 if (sctx
->chip_class
>= GFX7
) {
3685 si_pm4_set_reg(sctx
->cs_preamble_state
, R_030938_VGT_TF_RING_SIZE
,
3686 S_030938_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3687 si_pm4_set_reg(sctx
->cs_preamble_state
, R_030940_VGT_TF_MEMORY_BASE
, factor_va
>> 8);
3688 if (sctx
->chip_class
>= GFX10
)
3689 si_pm4_set_reg(sctx
->cs_preamble_state
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3690 S_030984_BASE_HI(factor_va
>> 40));
3691 else if (sctx
->chip_class
== GFX9
)
3692 si_pm4_set_reg(sctx
->cs_preamble_state
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3693 S_030944_BASE_HI(factor_va
>> 40));
3694 si_pm4_set_reg(sctx
->cs_preamble_state
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3695 sctx
->screen
->vgt_hs_offchip_param
);
3697 si_pm4_set_reg(sctx
->cs_preamble_state
, R_008988_VGT_TF_RING_SIZE
,
3698 S_008988_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3699 si_pm4_set_reg(sctx
->cs_preamble_state
, R_0089B8_VGT_TF_MEMORY_BASE
, factor_va
>> 8);
3700 si_pm4_set_reg(sctx
->cs_preamble_state
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3701 sctx
->screen
->vgt_hs_offchip_param
);
3704 /* Flush the context to re-emit the cs_preamble state.
3705 * This is done only once in a lifetime of a context.
3707 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3708 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3711 static struct si_pm4_state
*si_build_vgt_shader_config(struct si_screen
*screen
,
3712 union si_vgt_stages_key key
)
3714 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
3715 uint32_t stages
= 0;
3718 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) | S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3721 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) | S_028B54_GS_EN(1);
3723 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
3725 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3726 } else if (key
.u
.gs
) {
3727 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) | S_028B54_GS_EN(1);
3728 } else if (key
.u
.ngg
) {
3729 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
3733 stages
|= S_028B54_PRIMGEN_EN(1) | S_028B54_GS_FAST_LAUNCH(key
.u
.ngg_gs_fast_launch
) |
3734 S_028B54_NGG_WAVE_ID_EN(key
.u
.streamout
) |
3735 S_028B54_PRIMGEN_PASSTHRU_EN(key
.u
.ngg_passthrough
);
3736 } else if (key
.u
.gs
)
3737 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3739 if (screen
->info
.chip_class
>= GFX9
)
3740 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3742 if (screen
->info
.chip_class
>= GFX10
&&
3743 /* GS fast launch hangs with Wave64, so always use Wave32. */
3744 (screen
->ge_wave_size
== 32 || (key
.u
.ngg
&& key
.u
.ngg_gs_fast_launch
))) {
3745 stages
|= S_028B54_HS_W32_EN(1) |
3746 S_028B54_GS_W32_EN(key
.u
.ngg
) | /* legacy GS only supports Wave64 */
3747 S_028B54_VS_W32_EN(1);
3750 si_pm4_set_reg(pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3754 static void si_update_vgt_shader_config(struct si_context
*sctx
, union si_vgt_stages_key key
)
3756 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[key
.index
];
3758 if (unlikely(!*pm4
))
3759 *pm4
= si_build_vgt_shader_config(sctx
->screen
, key
);
3760 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3763 bool si_update_shaders(struct si_context
*sctx
)
3765 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3766 struct si_compiler_ctx_state compiler_state
;
3767 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3768 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3769 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
3770 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
3771 union si_vgt_stages_key key
;
3772 unsigned old_spi_shader_col_format
=
3773 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
3776 if (!sctx
->compiler
.passes
)
3777 si_init_compiler(sctx
->screen
, &sctx
->compiler
);
3779 compiler_state
.compiler
= &sctx
->compiler
;
3780 compiler_state
.debug
= sctx
->debug
;
3781 compiler_state
.is_debug_context
= sctx
->is_debug
;
3785 if (sctx
->tes_shader
.cso
)
3787 if (sctx
->gs_shader
.cso
)
3792 key
.u
.streamout
= !!si_get_vs(sctx
)->cso
->so
.num_outputs
;
3795 /* Update TCS and TES. */
3796 if (sctx
->tes_shader
.cso
) {
3797 if (!sctx
->tess_rings
) {
3798 si_init_tess_factor_ring(sctx
);
3799 if (!sctx
->tess_rings
)
3803 if (sctx
->tcs_shader
.cso
) {
3804 r
= si_shader_select(ctx
, &sctx
->tcs_shader
, key
, &compiler_state
);
3807 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3809 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3810 sctx
->fixed_func_tcs_shader
.cso
= si_create_fixed_func_tcs(sctx
);
3811 if (!sctx
->fixed_func_tcs_shader
.cso
)
3815 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
, key
, &compiler_state
);
3818 si_pm4_bind_state(sctx
, hs
, sctx
->fixed_func_tcs_shader
.current
->pm4
);
3821 if (!sctx
->gs_shader
.cso
|| sctx
->chip_class
<= GFX8
) {
3822 r
= si_shader_select(ctx
, &sctx
->tes_shader
, key
, &compiler_state
);
3826 if (sctx
->gs_shader
.cso
) {
3828 assert(sctx
->chip_class
<= GFX8
);
3829 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3830 } else if (key
.u
.ngg
) {
3831 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
3833 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3837 if (sctx
->chip_class
<= GFX8
)
3838 si_pm4_bind_state(sctx
, ls
, NULL
);
3839 si_pm4_bind_state(sctx
, hs
, NULL
);
3843 if (sctx
->gs_shader
.cso
) {
3844 r
= si_shader_select(ctx
, &sctx
->gs_shader
, key
, &compiler_state
);
3847 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3849 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3851 if (!si_update_gs_ring_buffers(sctx
))
3854 si_pm4_bind_state(sctx
, vs
, NULL
);
3858 si_pm4_bind_state(sctx
, gs
, NULL
);
3859 if (sctx
->chip_class
<= GFX8
)
3860 si_pm4_bind_state(sctx
, es
, NULL
);
3865 if ((!key
.u
.tess
&& !key
.u
.gs
) || sctx
->chip_class
<= GFX8
) {
3866 r
= si_shader_select(ctx
, &sctx
->vs_shader
, key
, &compiler_state
);
3870 if (!key
.u
.tess
&& !key
.u
.gs
) {
3872 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
3873 si_pm4_bind_state(sctx
, vs
, NULL
);
3875 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3877 } else if (sctx
->tes_shader
.cso
) {
3878 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3880 assert(sctx
->gs_shader
.cso
);
3881 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3885 /* This must be done after the shader variant is selected. */
3887 struct si_shader
*vs
= si_get_vs(sctx
)->current
;
3889 key
.u
.ngg_passthrough
= gfx10_is_ngg_passthrough(vs
);
3890 key
.u
.ngg_gs_fast_launch
= !!(vs
->key
.opt
.ngg_culling
& SI_NGG_CULL_GS_FAST_LAUNCH_ALL
);
3893 si_update_vgt_shader_config(sctx
, key
);
3895 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
3896 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
3898 if (sctx
->ps_shader
.cso
) {
3899 unsigned db_shader_control
;
3901 r
= si_shader_select(ctx
, &sctx
->ps_shader
, key
, &compiler_state
);
3904 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3906 db_shader_control
= sctx
->ps_shader
.cso
->db_shader_control
|
3907 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
3909 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
3910 (key
.u
.ngg
&& si_pm4_state_changed(sctx
, gs
)) ||
3911 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
3912 sctx
->flatshade
!= rs
->flatshade
) {
3913 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
3914 sctx
->flatshade
= rs
->flatshade
;
3915 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.spi_map
);
3918 if (sctx
->screen
->info
.rbplus_allowed
&& si_pm4_state_changed(sctx
, ps
) &&
3919 (!old_ps
|| old_spi_shader_col_format
!=
3920 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
3921 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3923 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
3924 sctx
->ps_db_shader_control
= db_shader_control
;
3925 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3926 if (sctx
->screen
->dpbb_allowed
)
3927 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3930 if (sctx
->smoothing_enabled
!=
3931 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
3932 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
3933 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3935 if (sctx
->chip_class
== GFX6
)
3936 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3938 if (sctx
->framebuffer
.nr_samples
<= 1)
3939 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
3943 if (si_pm4_state_enabled_and_changed(sctx
, ls
) || si_pm4_state_enabled_and_changed(sctx
, hs
) ||
3944 si_pm4_state_enabled_and_changed(sctx
, es
) || si_pm4_state_enabled_and_changed(sctx
, gs
) ||
3945 si_pm4_state_enabled_and_changed(sctx
, vs
) || si_pm4_state_enabled_and_changed(sctx
, ps
)) {
3946 if (!si_update_spi_tmpring_size(sctx
))
3950 if (sctx
->chip_class
>= GFX7
) {
3951 if (si_pm4_state_enabled_and_changed(sctx
, ls
))
3952 sctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
3953 else if (!sctx
->queued
.named
.ls
)
3954 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_LS
;
3956 if (si_pm4_state_enabled_and_changed(sctx
, hs
))
3957 sctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
3958 else if (!sctx
->queued
.named
.hs
)
3959 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_HS
;
3961 if (si_pm4_state_enabled_and_changed(sctx
, es
))
3962 sctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
3963 else if (!sctx
->queued
.named
.es
)
3964 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_ES
;
3966 if (si_pm4_state_enabled_and_changed(sctx
, gs
))
3967 sctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
3968 else if (!sctx
->queued
.named
.gs
)
3969 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_GS
;
3971 if (si_pm4_state_enabled_and_changed(sctx
, vs
))
3972 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
3973 else if (!sctx
->queued
.named
.vs
)
3974 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VS
;
3976 if (si_pm4_state_enabled_and_changed(sctx
, ps
))
3977 sctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
3978 else if (!sctx
->queued
.named
.ps
)
3979 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_PS
;
3982 sctx
->do_update_shaders
= false;
3986 static void si_emit_scratch_state(struct si_context
*sctx
)
3988 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3990 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
, sctx
->spi_tmpring_size
);
3992 if (sctx
->scratch_buffer
) {
3993 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
3994 RADEON_PRIO_SCRATCH_BUFFER
);
3998 void si_init_screen_live_shader_cache(struct si_screen
*sscreen
)
4000 util_live_shader_cache_init(&sscreen
->live_shader_cache
, si_create_shader_selector
,
4001 si_destroy_shader_selector
);
4004 void si_init_shader_functions(struct si_context
*sctx
)
4006 sctx
->atoms
.s
.spi_map
.emit
= si_emit_spi_map
;
4007 sctx
->atoms
.s
.scratch_state
.emit
= si_emit_scratch_state
;
4009 sctx
->b
.create_vs_state
= si_create_shader
;
4010 sctx
->b
.create_tcs_state
= si_create_shader
;
4011 sctx
->b
.create_tes_state
= si_create_shader
;
4012 sctx
->b
.create_gs_state
= si_create_shader
;
4013 sctx
->b
.create_fs_state
= si_create_shader
;
4015 sctx
->b
.bind_vs_state
= si_bind_vs_shader
;
4016 sctx
->b
.bind_tcs_state
= si_bind_tcs_shader
;
4017 sctx
->b
.bind_tes_state
= si_bind_tes_shader
;
4018 sctx
->b
.bind_gs_state
= si_bind_gs_shader
;
4019 sctx
->b
.bind_fs_state
= si_bind_ps_shader
;
4021 sctx
->b
.delete_vs_state
= si_delete_shader_selector
;
4022 sctx
->b
.delete_tcs_state
= si_delete_shader_selector
;
4023 sctx
->b
.delete_tes_state
= si_delete_shader_selector
;
4024 sctx
->b
.delete_gs_state
= si_delete_shader_selector
;
4025 sctx
->b
.delete_fs_state
= si_delete_shader_selector
;