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radeonsi: always interpolate PrimID as flat
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
45 * size as integer.
46 */
47 void *si_get_ir_binary(struct si_shader_selector *sel)
48 {
49 struct blob blob;
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->tokens) {
54 ir_binary = sel->tokens;
55 ir_size = tgsi_num_tokens(sel->tokens) *
56 sizeof(struct tgsi_token);
57 } else {
58 assert(sel->nir);
59
60 blob_init(&blob);
61 nir_serialize(&blob, sel->nir);
62 ir_binary = blob.data;
63 ir_size = blob.size;
64 }
65
66 unsigned size = 4 + ir_size + sizeof(sel->so);
67 char *result = (char*)MALLOC(size);
68 if (!result)
69 return NULL;
70
71 *((uint32_t*)result) = size;
72 memcpy(result + 4, ir_binary, ir_size);
73 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
74
75 if (sel->nir)
76 blob_finish(&blob);
77
78 return result;
79 }
80
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
83 {
84 /* data may be NULL if size == 0 */
85 if (size)
86 memcpy(ptr, data, size);
87 ptr += DIV_ROUND_UP(size, 4);
88 return ptr;
89 }
90
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
93 {
94 memcpy(data, ptr, size);
95 ptr += DIV_ROUND_UP(size, 4);
96 return ptr;
97 }
98
99 /**
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
102 */
103 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
104 {
105 *ptr++ = size;
106 return write_data(ptr, data, size);
107 }
108
109 /**
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
112 */
113 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
114 {
115 *size = *ptr++;
116 assert(*data == NULL);
117 if (!*size)
118 return ptr;
119 *data = malloc(*size);
120 return read_data(ptr, *data, *size);
121 }
122
123 /**
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
125 * as integer.
126 */
127 static void *si_get_shader_binary(struct si_shader *shader)
128 {
129 /* There is always a size of data followed by the data itself. */
130 unsigned relocs_size = shader->binary.reloc_count *
131 sizeof(shader->binary.relocs[0]);
132 unsigned disasm_size = shader->binary.disasm_string ?
133 strlen(shader->binary.disasm_string) + 1 : 0;
134 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
135 strlen(shader->binary.llvm_ir_string) + 1 : 0;
136 unsigned size =
137 4 + /* total size */
138 4 + /* CRC32 of the data below */
139 align(sizeof(shader->config), 4) +
140 align(sizeof(shader->info), 4) +
141 4 + align(shader->binary.code_size, 4) +
142 4 + align(shader->binary.rodata_size, 4) +
143 4 + align(relocs_size, 4) +
144 4 + align(disasm_size, 4) +
145 4 + align(llvm_ir_size, 4);
146 void *buffer = CALLOC(1, size);
147 uint32_t *ptr = (uint32_t*)buffer;
148
149 if (!buffer)
150 return NULL;
151
152 *ptr++ = size;
153 ptr++; /* CRC32 is calculated at the end. */
154
155 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
156 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
157 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
158 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
159 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
160 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
161 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
162 assert((char *)ptr - (char *)buffer == size);
163
164 /* Compute CRC32. */
165 ptr = (uint32_t*)buffer;
166 ptr++;
167 *ptr = util_hash_crc32(ptr + 1, size - 8);
168
169 return buffer;
170 }
171
172 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
173 {
174 uint32_t *ptr = (uint32_t*)binary;
175 uint32_t size = *ptr++;
176 uint32_t crc32 = *ptr++;
177 unsigned chunk_size;
178
179 if (util_hash_crc32(ptr, size - 8) != crc32) {
180 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
181 return false;
182 }
183
184 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
185 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
186 ptr = read_chunk(ptr, (void**)&shader->binary.code,
187 &shader->binary.code_size);
188 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
189 &shader->binary.rodata_size);
190 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
191 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
192 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
193 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
194
195 return true;
196 }
197
198 /**
199 * Insert a shader into the cache. It's assumed the shader is not in the cache.
200 * Use si_shader_cache_load_shader before calling this.
201 *
202 * Returns false on failure, in which case the ir_binary should be freed.
203 */
204 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
205 struct si_shader *shader,
206 bool insert_into_disk_cache)
207 {
208 void *hw_binary;
209 struct hash_entry *entry;
210 uint8_t key[CACHE_KEY_SIZE];
211
212 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
213 if (entry)
214 return false; /* already added */
215
216 hw_binary = si_get_shader_binary(shader);
217 if (!hw_binary)
218 return false;
219
220 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
221 hw_binary) == NULL) {
222 FREE(hw_binary);
223 return false;
224 }
225
226 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
227 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
228 *((uint32_t *)ir_binary), key);
229 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
230 *((uint32_t *) hw_binary), NULL);
231 }
232
233 return true;
234 }
235
236 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
237 struct si_shader *shader)
238 {
239 struct hash_entry *entry =
240 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
241 if (!entry) {
242 if (sscreen->disk_shader_cache) {
243 unsigned char sha1[CACHE_KEY_SIZE];
244 size_t tg_size = *((uint32_t *) ir_binary);
245
246 disk_cache_compute_key(sscreen->disk_shader_cache,
247 ir_binary, tg_size, sha1);
248
249 size_t binary_size;
250 uint8_t *buffer =
251 disk_cache_get(sscreen->disk_shader_cache,
252 sha1, &binary_size);
253 if (!buffer)
254 return false;
255
256 if (binary_size < sizeof(uint32_t) ||
257 *((uint32_t*)buffer) != binary_size) {
258 /* Something has gone wrong discard the item
259 * from the cache and rebuild/link from
260 * source.
261 */
262 assert(!"Invalid radeonsi shader disk cache "
263 "item!");
264
265 disk_cache_remove(sscreen->disk_shader_cache,
266 sha1);
267 free(buffer);
268
269 return false;
270 }
271
272 if (!si_load_shader_binary(shader, buffer)) {
273 free(buffer);
274 return false;
275 }
276 free(buffer);
277
278 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
279 shader, false))
280 FREE(ir_binary);
281 } else {
282 return false;
283 }
284 } else {
285 if (si_load_shader_binary(shader, entry->data))
286 FREE(ir_binary);
287 else
288 return false;
289 }
290 p_atomic_inc(&sscreen->num_shader_cache_hits);
291 return true;
292 }
293
294 static uint32_t si_shader_cache_key_hash(const void *key)
295 {
296 /* The first dword is the key size. */
297 return util_hash_crc32(key, *(uint32_t*)key);
298 }
299
300 static bool si_shader_cache_key_equals(const void *a, const void *b)
301 {
302 uint32_t *keya = (uint32_t*)a;
303 uint32_t *keyb = (uint32_t*)b;
304
305 /* The first dword is the key size. */
306 if (*keya != *keyb)
307 return false;
308
309 return memcmp(keya, keyb, *keya) == 0;
310 }
311
312 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
313 {
314 FREE((void*)entry->key);
315 FREE(entry->data);
316 }
317
318 bool si_init_shader_cache(struct si_screen *sscreen)
319 {
320 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
321 sscreen->shader_cache =
322 _mesa_hash_table_create(NULL,
323 si_shader_cache_key_hash,
324 si_shader_cache_key_equals);
325
326 return sscreen->shader_cache != NULL;
327 }
328
329 void si_destroy_shader_cache(struct si_screen *sscreen)
330 {
331 if (sscreen->shader_cache)
332 _mesa_hash_table_destroy(sscreen->shader_cache,
333 si_destroy_shader_cache_entry);
334 mtx_destroy(&sscreen->shader_cache_mutex);
335 }
336
337 /* SHADER STATES */
338
339 static void si_set_tesseval_regs(struct si_screen *sscreen,
340 const struct si_shader_selector *tes,
341 struct si_pm4_state *pm4)
342 {
343 const struct tgsi_shader_info *info = &tes->info;
344 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
345 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
346 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
347 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
348 unsigned type, partitioning, topology, distribution_mode;
349
350 switch (tes_prim_mode) {
351 case PIPE_PRIM_LINES:
352 type = V_028B6C_TESS_ISOLINE;
353 break;
354 case PIPE_PRIM_TRIANGLES:
355 type = V_028B6C_TESS_TRIANGLE;
356 break;
357 case PIPE_PRIM_QUADS:
358 type = V_028B6C_TESS_QUAD;
359 break;
360 default:
361 assert(0);
362 return;
363 }
364
365 switch (tes_spacing) {
366 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
367 partitioning = V_028B6C_PART_FRAC_ODD;
368 break;
369 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
370 partitioning = V_028B6C_PART_FRAC_EVEN;
371 break;
372 case PIPE_TESS_SPACING_EQUAL:
373 partitioning = V_028B6C_PART_INTEGER;
374 break;
375 default:
376 assert(0);
377 return;
378 }
379
380 if (tes_point_mode)
381 topology = V_028B6C_OUTPUT_POINT;
382 else if (tes_prim_mode == PIPE_PRIM_LINES)
383 topology = V_028B6C_OUTPUT_LINE;
384 else if (tes_vertex_order_cw)
385 /* for some reason, this must be the other way around */
386 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
387 else
388 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
389
390 if (sscreen->has_distributed_tess) {
391 if (sscreen->info.family == CHIP_FIJI ||
392 sscreen->info.family >= CHIP_POLARIS10)
393 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
394 else
395 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
396 } else
397 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
398
399 assert(pm4->shader);
400 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
401 S_028B6C_PARTITIONING(partitioning) |
402 S_028B6C_TOPOLOGY(topology) |
403 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
404 }
405
406 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
407 * whether the "fractional odd" tessellation spacing is used.
408 *
409 * Possible VGT configurations and which state should set the register:
410 *
411 * Reg set in | VGT shader configuration | Value
412 * ------------------------------------------------------
413 * VS as VS | VS | 30
414 * VS as ES | ES -> GS -> VS | 30
415 * TES as VS | LS -> HS -> VS | 14 or 30
416 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
417 *
418 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
419 */
420 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
421 struct si_shader_selector *sel,
422 struct si_shader *shader,
423 struct si_pm4_state *pm4)
424 {
425 unsigned type = sel->type;
426
427 if (sscreen->info.family < CHIP_POLARIS10)
428 return;
429
430 /* VS as VS, or VS as ES: */
431 if ((type == PIPE_SHADER_VERTEX &&
432 (!shader ||
433 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
434 /* TES as VS, or TES as ES: */
435 type == PIPE_SHADER_TESS_EVAL) {
436 unsigned vtx_reuse_depth = 30;
437
438 if (type == PIPE_SHADER_TESS_EVAL &&
439 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
440 PIPE_TESS_SPACING_FRACTIONAL_ODD)
441 vtx_reuse_depth = 14;
442
443 assert(pm4->shader);
444 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
445 }
446 }
447
448 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
449 {
450 if (shader->pm4)
451 si_pm4_clear_state(shader->pm4);
452 else
453 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
454
455 if (shader->pm4) {
456 shader->pm4->shader = shader;
457 return shader->pm4;
458 } else {
459 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
460 return NULL;
461 }
462 }
463
464 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
465 {
466 /* Add the pointer to VBO descriptors. */
467 return num_always_on_user_sgprs + 1;
468 }
469
470 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
471 {
472 struct si_pm4_state *pm4;
473 unsigned vgpr_comp_cnt;
474 uint64_t va;
475
476 assert(sscreen->info.chip_class <= GFX8);
477
478 pm4 = si_get_shader_pm4_state(shader);
479 if (!pm4)
480 return;
481
482 va = shader->bo->gpu_address;
483 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
484
485 /* We need at least 2 components for LS.
486 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
487 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
488 */
489 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
490
491 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
492 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
493
494 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
495 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
496 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
497 S_00B528_DX10_CLAMP(1) |
498 S_00B528_FLOAT_MODE(shader->config.float_mode);
499 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
500 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
501 }
502
503 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
504 {
505 struct si_pm4_state *pm4;
506 uint64_t va;
507 unsigned ls_vgpr_comp_cnt = 0;
508
509 pm4 = si_get_shader_pm4_state(shader);
510 if (!pm4)
511 return;
512
513 va = shader->bo->gpu_address;
514 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
515
516 if (sscreen->info.chip_class >= GFX9) {
517 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
518 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
519
520 /* We need at least 2 components for LS.
521 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
522 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
523 */
524 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
525
526 unsigned num_user_sgprs =
527 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
528
529 shader->config.rsrc2 =
530 S_00B42C_USER_SGPR(num_user_sgprs) |
531 S_00B42C_USER_SGPR_MSB(num_user_sgprs >> 5) |
532 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
533 } else {
534 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
535 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
536
537 shader->config.rsrc2 =
538 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
539 S_00B42C_OC_LDS_EN(1) |
540 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
541 }
542
543 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
544 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
545 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
546 S_00B428_DX10_CLAMP(1) |
547 S_00B428_FLOAT_MODE(shader->config.float_mode) |
548 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
549
550 if (sscreen->info.chip_class <= GFX8) {
551 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
552 shader->config.rsrc2);
553 }
554 }
555
556 static void si_emit_shader_es(struct si_context *sctx)
557 {
558 struct si_shader *shader = sctx->queued.named.es->shader;
559 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
560
561 if (!shader)
562 return;
563
564 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
565 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
566 shader->selector->esgs_itemsize / 4);
567
568 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
569 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
570 SI_TRACKED_VGT_TF_PARAM,
571 shader->vgt_tf_param);
572
573 if (shader->vgt_vertex_reuse_block_cntl)
574 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
575 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
576 shader->vgt_vertex_reuse_block_cntl);
577
578 if (initial_cdw != sctx->gfx_cs->current.cdw)
579 sctx->context_roll = true;
580 }
581
582 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
583 {
584 struct si_pm4_state *pm4;
585 unsigned num_user_sgprs;
586 unsigned vgpr_comp_cnt;
587 uint64_t va;
588 unsigned oc_lds_en;
589
590 assert(sscreen->info.chip_class <= GFX8);
591
592 pm4 = si_get_shader_pm4_state(shader);
593 if (!pm4)
594 return;
595
596 pm4->atom.emit = si_emit_shader_es;
597 va = shader->bo->gpu_address;
598 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
599
600 if (shader->selector->type == PIPE_SHADER_VERTEX) {
601 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
602 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
603 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
604 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
605 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
606 num_user_sgprs = SI_TES_NUM_USER_SGPR;
607 } else
608 unreachable("invalid shader selector type");
609
610 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
611
612 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
613 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
614 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
615 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
616 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
617 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
618 S_00B328_DX10_CLAMP(1) |
619 S_00B328_FLOAT_MODE(shader->config.float_mode));
620 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
621 S_00B32C_USER_SGPR(num_user_sgprs) |
622 S_00B32C_OC_LDS_EN(oc_lds_en) |
623 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
624
625 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
626 si_set_tesseval_regs(sscreen, shader->selector, pm4);
627
628 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
629 }
630
631 static unsigned si_conv_prim_to_gs_out(unsigned mode)
632 {
633 static const int prim_conv[] = {
634 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
635 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
636 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
637 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
638 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
639 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
640 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
641 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
642 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
643 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
644 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
645 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
646 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
647 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
648 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
649 };
650 assert(mode < ARRAY_SIZE(prim_conv));
651
652 return prim_conv[mode];
653 }
654
655 struct gfx9_gs_info {
656 unsigned es_verts_per_subgroup;
657 unsigned gs_prims_per_subgroup;
658 unsigned gs_inst_prims_in_subgroup;
659 unsigned max_prims_per_subgroup;
660 unsigned lds_size;
661 };
662
663 static void gfx9_get_gs_info(struct si_shader_selector *es,
664 struct si_shader_selector *gs,
665 struct gfx9_gs_info *out)
666 {
667 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
668 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
669 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
670 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
671
672 /* All these are in dwords: */
673 /* We can't allow using the whole LDS, because GS waves compete with
674 * other shader stages for LDS space. */
675 const unsigned max_lds_size = 8 * 1024;
676 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
677 unsigned esgs_lds_size;
678
679 /* All these are per subgroup: */
680 const unsigned max_out_prims = 32 * 1024;
681 const unsigned max_es_verts = 255;
682 const unsigned ideal_gs_prims = 64;
683 unsigned max_gs_prims, gs_prims;
684 unsigned min_es_verts, es_verts, worst_case_es_verts;
685
686 if (uses_adjacency || gs_num_invocations > 1)
687 max_gs_prims = 127 / gs_num_invocations;
688 else
689 max_gs_prims = 255;
690
691 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
692 * Make sure we don't go over the maximum value.
693 */
694 if (gs->gs_max_out_vertices > 0) {
695 max_gs_prims = MIN2(max_gs_prims,
696 max_out_prims /
697 (gs->gs_max_out_vertices * gs_num_invocations));
698 }
699 assert(max_gs_prims > 0);
700
701 /* If the primitive has adjacency, halve the number of vertices
702 * that will be reused in multiple primitives.
703 */
704 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
705
706 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
707 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
708
709 /* Compute ESGS LDS size based on the worst case number of ES vertices
710 * needed to create the target number of GS prims per subgroup.
711 */
712 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
713
714 /* If total LDS usage is too big, refactor partitions based on ratio
715 * of ESGS item sizes.
716 */
717 if (esgs_lds_size > max_lds_size) {
718 /* Our target GS Prims Per Subgroup was too large. Calculate
719 * the maximum number of GS Prims Per Subgroup that will fit
720 * into LDS, capped by the maximum that the hardware can support.
721 */
722 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
723 max_gs_prims);
724 assert(gs_prims > 0);
725 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
726 max_es_verts);
727
728 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
729 assert(esgs_lds_size <= max_lds_size);
730 }
731
732 /* Now calculate remaining ESGS information. */
733 if (esgs_lds_size)
734 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
735 else
736 es_verts = max_es_verts;
737
738 /* Vertices for adjacency primitives are not always reused, so restore
739 * it for ES_VERTS_PER_SUBGRP.
740 */
741 min_es_verts = gs->gs_input_verts_per_prim;
742
743 /* For normal primitives, the VGT only checks if they are past the ES
744 * verts per subgroup after allocating a full GS primitive and if they
745 * are, kick off a new subgroup. But if those additional ES verts are
746 * unique (e.g. not reused) we need to make sure there is enough LDS
747 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
748 */
749 es_verts -= min_es_verts - 1;
750
751 out->es_verts_per_subgroup = es_verts;
752 out->gs_prims_per_subgroup = gs_prims;
753 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
754 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
755 gs->gs_max_out_vertices;
756 out->lds_size = align(esgs_lds_size, 128) / 128;
757
758 assert(out->max_prims_per_subgroup <= max_out_prims);
759 }
760
761 static void si_emit_shader_gs(struct si_context *sctx)
762 {
763 struct si_shader *shader = sctx->queued.named.gs->shader;
764 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
765
766 if (!shader)
767 return;
768
769 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
770 * R_028A68_VGT_GSVS_RING_OFFSET_3, R_028A6C_VGT_GS_OUT_PRIM_TYPE */
771 radeon_opt_set_context_reg4(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
772 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
773 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
774 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
775 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3,
776 shader->ctx_reg.gs.vgt_gs_out_prim_type);
777
778
779 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
780 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
781 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
782 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
783
784 /* R_028B38_VGT_GS_MAX_VERT_OUT */
785 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
786 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
787 shader->ctx_reg.gs.vgt_gs_max_vert_out);
788
789 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
790 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
791 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
792 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
793 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
794 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
795 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
796 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
797
798 /* R_028B90_VGT_GS_INSTANCE_CNT */
799 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
800 SI_TRACKED_VGT_GS_INSTANCE_CNT,
801 shader->ctx_reg.gs.vgt_gs_instance_cnt);
802
803 if (sctx->chip_class >= GFX9) {
804 /* R_028A44_VGT_GS_ONCHIP_CNTL */
805 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
806 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
807 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
808 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
809 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
810 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
811 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
812 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
813 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
814 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
815 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
816
817 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
818 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
819 SI_TRACKED_VGT_TF_PARAM,
820 shader->vgt_tf_param);
821 if (shader->vgt_vertex_reuse_block_cntl)
822 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
823 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
824 shader->vgt_vertex_reuse_block_cntl);
825 }
826
827 if (initial_cdw != sctx->gfx_cs->current.cdw)
828 sctx->context_roll = true;
829 }
830
831 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
832 {
833 struct si_shader_selector *sel = shader->selector;
834 const ubyte *num_components = sel->info.num_stream_output_components;
835 unsigned gs_num_invocations = sel->gs_num_invocations;
836 struct si_pm4_state *pm4;
837 uint64_t va;
838 unsigned max_stream = sel->max_gs_stream;
839 unsigned offset;
840
841 pm4 = si_get_shader_pm4_state(shader);
842 if (!pm4)
843 return;
844
845 pm4->atom.emit = si_emit_shader_gs;
846
847 offset = num_components[0] * sel->gs_max_out_vertices;
848 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
849
850 if (max_stream >= 1)
851 offset += num_components[1] * sel->gs_max_out_vertices;
852 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
853
854 if (max_stream >= 2)
855 offset += num_components[2] * sel->gs_max_out_vertices;
856 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
857
858 shader->ctx_reg.gs.vgt_gs_out_prim_type =
859 si_conv_prim_to_gs_out(sel->gs_output_prim);
860
861 if (max_stream >= 3)
862 offset += num_components[3] * sel->gs_max_out_vertices;
863 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
864
865 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
866 assert(offset < (1 << 15));
867
868 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
869
870 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
871 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
872 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
873 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
874
875 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
876 S_028B90_ENABLE(gs_num_invocations > 0);
877
878 va = shader->bo->gpu_address;
879 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
880
881 if (sscreen->info.chip_class >= GFX9) {
882 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
883 unsigned es_type = shader->key.part.gs.es->type;
884 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
885 struct gfx9_gs_info gs_info;
886
887 if (es_type == PIPE_SHADER_VERTEX)
888 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
889 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
890 else if (es_type == PIPE_SHADER_TESS_EVAL)
891 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
892 else
893 unreachable("invalid shader selector type");
894
895 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
896 * VGPR[0:4] are always loaded.
897 */
898 if (sel->info.uses_invocationid)
899 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
900 else if (sel->info.uses_primid)
901 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
902 else if (input_prim >= PIPE_PRIM_TRIANGLES)
903 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
904 else
905 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
906
907 unsigned num_user_sgprs;
908 if (es_type == PIPE_SHADER_VERTEX)
909 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
910 else
911 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
912
913 gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
914
915 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
916 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
917
918 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
919 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
920 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
921 S_00B228_DX10_CLAMP(1) |
922 S_00B228_FLOAT_MODE(shader->config.float_mode) |
923 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
924 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
925 S_00B22C_USER_SGPR(num_user_sgprs) |
926 S_00B22C_USER_SGPR_MSB(num_user_sgprs >> 5) |
927 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
928 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
929 S_00B22C_LDS_SIZE(gs_info.lds_size) |
930 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
931
932 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
933 S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) |
934 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) |
935 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup);
936 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
937 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup);
938 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
939 shader->key.part.gs.es->esgs_itemsize / 4;
940
941 if (es_type == PIPE_SHADER_TESS_EVAL)
942 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
943
944 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
945 NULL, pm4);
946 } else {
947 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
948 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
949
950 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
951 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
952 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
953 S_00B228_DX10_CLAMP(1) |
954 S_00B228_FLOAT_MODE(shader->config.float_mode));
955 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
956 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
957 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
958 }
959 }
960
961 static void si_emit_shader_vs(struct si_context *sctx)
962 {
963 struct si_shader *shader = sctx->queued.named.vs->shader;
964 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
965
966 if (!shader)
967 return;
968
969 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
970 SI_TRACKED_VGT_GS_MODE,
971 shader->ctx_reg.vs.vgt_gs_mode);
972 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
973 SI_TRACKED_VGT_PRIMITIVEID_EN,
974 shader->ctx_reg.vs.vgt_primitiveid_en);
975
976 if (sctx->chip_class <= GFX8) {
977 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
978 SI_TRACKED_VGT_REUSE_OFF,
979 shader->ctx_reg.vs.vgt_reuse_off);
980 }
981
982 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
983 SI_TRACKED_SPI_VS_OUT_CONFIG,
984 shader->ctx_reg.vs.spi_vs_out_config);
985
986 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
987 SI_TRACKED_SPI_SHADER_POS_FORMAT,
988 shader->ctx_reg.vs.spi_shader_pos_format);
989
990 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
991 SI_TRACKED_PA_CL_VTE_CNTL,
992 shader->ctx_reg.vs.pa_cl_vte_cntl);
993
994 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
995 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
996 SI_TRACKED_VGT_TF_PARAM,
997 shader->vgt_tf_param);
998
999 if (shader->vgt_vertex_reuse_block_cntl)
1000 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1001 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1002 shader->vgt_vertex_reuse_block_cntl);
1003
1004 if (initial_cdw != sctx->gfx_cs->current.cdw)
1005 sctx->context_roll = true;
1006 }
1007
1008 /**
1009 * Compute the state for \p shader, which will run as a vertex shader on the
1010 * hardware.
1011 *
1012 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1013 * is the copy shader.
1014 */
1015 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1016 struct si_shader_selector *gs)
1017 {
1018 const struct tgsi_shader_info *info = &shader->selector->info;
1019 struct si_pm4_state *pm4;
1020 unsigned num_user_sgprs, vgpr_comp_cnt;
1021 uint64_t va;
1022 unsigned nparams, oc_lds_en;
1023 unsigned window_space =
1024 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1025 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1026
1027 pm4 = si_get_shader_pm4_state(shader);
1028 if (!pm4)
1029 return;
1030
1031 pm4->atom.emit = si_emit_shader_vs;
1032
1033 /* We always write VGT_GS_MODE in the VS state, because every switch
1034 * between different shader pipelines involving a different GS or no
1035 * GS at all involves a switch of the VS (different GS use different
1036 * copy shaders). On the other hand, when the API switches from a GS to
1037 * no GS and then back to the same GS used originally, the GS state is
1038 * not sent again.
1039 */
1040 if (!gs) {
1041 unsigned mode = V_028A40_GS_OFF;
1042
1043 /* PrimID needs GS scenario A. */
1044 if (enable_prim_id)
1045 mode = V_028A40_GS_SCENARIO_A;
1046
1047 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1048 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1049 } else {
1050 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1051 sscreen->info.chip_class);
1052 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1053 }
1054
1055 if (sscreen->info.chip_class <= GFX8) {
1056 /* Reuse needs to be set off if we write oViewport. */
1057 shader->ctx_reg.vs.vgt_reuse_off =
1058 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1059 }
1060
1061 va = shader->bo->gpu_address;
1062 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1063
1064 if (gs) {
1065 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1066 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1067 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1068 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1069 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1070 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1071 */
1072 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1073
1074 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1075 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1076 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1077 } else {
1078 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1079 }
1080 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1081 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1082 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1083 } else
1084 unreachable("invalid shader selector type");
1085
1086 /* VS is required to export at least one param. */
1087 nparams = MAX2(shader->info.nr_param_exports, 1);
1088 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1089
1090 shader->ctx_reg.vs.spi_shader_pos_format =
1091 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1092 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1093 V_02870C_SPI_SHADER_4COMP :
1094 V_02870C_SPI_SHADER_NONE) |
1095 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1096 V_02870C_SPI_SHADER_4COMP :
1097 V_02870C_SPI_SHADER_NONE) |
1098 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1099 V_02870C_SPI_SHADER_4COMP :
1100 V_02870C_SPI_SHADER_NONE);
1101
1102 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1103
1104 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1105 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1106 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
1107 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
1108 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
1109 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1110 S_00B128_DX10_CLAMP(1) |
1111 S_00B128_FLOAT_MODE(shader->config.float_mode));
1112 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
1113 S_00B12C_USER_SGPR(num_user_sgprs) |
1114 S_00B12C_OC_LDS_EN(oc_lds_en) |
1115 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1116 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1117 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1118 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1119 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
1120 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1121
1122 if (window_space)
1123 shader->ctx_reg.vs.pa_cl_vte_cntl =
1124 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1125 else
1126 shader->ctx_reg.vs.pa_cl_vte_cntl =
1127 S_028818_VTX_W0_FMT(1) |
1128 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1129 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1130 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1131
1132 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1133 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1134
1135 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1136 }
1137
1138 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1139 {
1140 struct tgsi_shader_info *info = &ps->selector->info;
1141 unsigned num_colors = !!(info->colors_read & 0x0f) +
1142 !!(info->colors_read & 0xf0);
1143 unsigned num_interp = ps->selector->info.num_inputs +
1144 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1145
1146 assert(num_interp <= 32);
1147 return MIN2(num_interp, 32);
1148 }
1149
1150 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1151 {
1152 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1153 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1154
1155 /* If the i-th target format is set, all previous target formats must
1156 * be non-zero to avoid hangs.
1157 */
1158 for (i = 0; i < num_targets; i++)
1159 if (!(value & (0xf << (i * 4))))
1160 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1161
1162 return value;
1163 }
1164
1165 static void si_emit_shader_ps(struct si_context *sctx)
1166 {
1167 struct si_shader *shader = sctx->queued.named.ps->shader;
1168 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1169
1170 if (!shader)
1171 return;
1172
1173 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1174 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1175 SI_TRACKED_SPI_PS_INPUT_ENA,
1176 shader->ctx_reg.ps.spi_ps_input_ena,
1177 shader->ctx_reg.ps.spi_ps_input_addr);
1178
1179 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1180 SI_TRACKED_SPI_BARYC_CNTL,
1181 shader->ctx_reg.ps.spi_baryc_cntl);
1182 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1183 SI_TRACKED_SPI_PS_IN_CONTROL,
1184 shader->ctx_reg.ps.spi_ps_in_control);
1185
1186 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1187 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1188 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1189 shader->ctx_reg.ps.spi_shader_z_format,
1190 shader->ctx_reg.ps.spi_shader_col_format);
1191
1192 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1193 SI_TRACKED_CB_SHADER_MASK,
1194 shader->ctx_reg.ps.cb_shader_mask);
1195
1196 if (initial_cdw != sctx->gfx_cs->current.cdw)
1197 sctx->context_roll = true;
1198 }
1199
1200 static void si_shader_ps(struct si_shader *shader)
1201 {
1202 struct tgsi_shader_info *info = &shader->selector->info;
1203 struct si_pm4_state *pm4;
1204 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1205 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1206 uint64_t va;
1207 unsigned input_ena = shader->config.spi_ps_input_ena;
1208
1209 /* we need to enable at least one of them, otherwise we hang the GPU */
1210 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1211 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1212 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1213 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1214 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1215 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1216 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1217 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1218 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1219 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1220 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1221 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1222 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1223 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1224
1225 /* Validate interpolation optimization flags (read as implications). */
1226 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1227 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1228 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1229 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1230 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1231 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1232 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1233 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1234 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1235 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1236 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1237 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1238 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1239 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1240 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1241 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1242 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1243 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1244
1245 /* Validate cases when the optimizations are off (read as implications). */
1246 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1247 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1248 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1249 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1250 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1251 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1252
1253 pm4 = si_get_shader_pm4_state(shader);
1254 if (!pm4)
1255 return;
1256
1257 pm4->atom.emit = si_emit_shader_ps;
1258
1259 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1260 * Possible vaules:
1261 * 0 -> Position = pixel center
1262 * 1 -> Position = pixel centroid
1263 * 2 -> Position = at sample position
1264 *
1265 * From GLSL 4.5 specification, section 7.1:
1266 * "The variable gl_FragCoord is available as an input variable from
1267 * within fragment shaders and it holds the window relative coordinates
1268 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1269 * value can be for any location within the pixel, or one of the
1270 * fragment samples. The use of centroid does not further restrict
1271 * this value to be inside the current primitive."
1272 *
1273 * Meaning that centroid has no effect and we can return anything within
1274 * the pixel. Thus, return the value at sample position, because that's
1275 * the most accurate one shaders can get.
1276 */
1277 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1278
1279 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1280 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1281 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1282
1283 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1284 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1285
1286 /* Ensure that some export memory is always allocated, for two reasons:
1287 *
1288 * 1) Correctness: The hardware ignores the EXEC mask if no export
1289 * memory is allocated, so KILL and alpha test do not work correctly
1290 * without this.
1291 * 2) Performance: Every shader needs at least a NULL export, even when
1292 * it writes no color/depth output. The NULL export instruction
1293 * stalls without this setting.
1294 *
1295 * Don't add this to CB_SHADER_MASK.
1296 */
1297 if (!spi_shader_col_format &&
1298 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1299 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1300
1301 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1302 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1303
1304 /* Set interpolation controls. */
1305 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1306
1307 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1308 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1309 shader->ctx_reg.ps.spi_shader_z_format =
1310 ac_get_spi_shader_z_format(info->writes_z,
1311 info->writes_stencil,
1312 info->writes_samplemask);
1313 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1314 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1315
1316 va = shader->bo->gpu_address;
1317 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1318 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1319 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1320
1321 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1322 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1323 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
1324 S_00B028_DX10_CLAMP(1) |
1325 S_00B028_FLOAT_MODE(shader->config.float_mode));
1326 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1327 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1328 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1329 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1330 }
1331
1332 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1333 struct si_shader *shader)
1334 {
1335 switch (shader->selector->type) {
1336 case PIPE_SHADER_VERTEX:
1337 if (shader->key.as_ls)
1338 si_shader_ls(sscreen, shader);
1339 else if (shader->key.as_es)
1340 si_shader_es(sscreen, shader);
1341 else
1342 si_shader_vs(sscreen, shader, NULL);
1343 break;
1344 case PIPE_SHADER_TESS_CTRL:
1345 si_shader_hs(sscreen, shader);
1346 break;
1347 case PIPE_SHADER_TESS_EVAL:
1348 if (shader->key.as_es)
1349 si_shader_es(sscreen, shader);
1350 else
1351 si_shader_vs(sscreen, shader, NULL);
1352 break;
1353 case PIPE_SHADER_GEOMETRY:
1354 si_shader_gs(sscreen, shader);
1355 break;
1356 case PIPE_SHADER_FRAGMENT:
1357 si_shader_ps(shader);
1358 break;
1359 default:
1360 assert(0);
1361 }
1362 }
1363
1364 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1365 {
1366 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1367 if (sctx->queued.named.dsa)
1368 return sctx->queued.named.dsa->alpha_func;
1369
1370 return PIPE_FUNC_ALWAYS;
1371 }
1372
1373 void si_shader_selector_key_vs(struct si_context *sctx,
1374 struct si_shader_selector *vs,
1375 struct si_shader_key *key,
1376 struct si_vs_prolog_bits *prolog_key)
1377 {
1378 if (!sctx->vertex_elements ||
1379 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS])
1380 return;
1381
1382 struct si_vertex_elements *elts = sctx->vertex_elements;
1383
1384 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1385 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1386 prolog_key->unpack_instance_id_from_vertex_id =
1387 sctx->prim_discard_cs_instancing;
1388
1389 /* Prefer a monolithic shader to allow scheduling divisions around
1390 * VBO loads. */
1391 if (prolog_key->instance_divisor_is_fetched)
1392 key->opt.prefer_mono = 1;
1393
1394 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1395 unsigned count_mask = (1 << count) - 1;
1396 unsigned fix = elts->fix_fetch_always & count_mask;
1397 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1398
1399 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1400 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1401 while (mask) {
1402 unsigned i = u_bit_scan(&mask);
1403 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1404 unsigned vbidx = elts->vertex_buffer_index[i];
1405 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1406 unsigned align_mask = (1 << log_hw_load_size) - 1;
1407 if (vb->buffer_offset & align_mask ||
1408 vb->stride & align_mask) {
1409 fix |= 1 << i;
1410 opencode |= 1 << i;
1411 }
1412 }
1413 }
1414
1415 while (fix) {
1416 unsigned i = u_bit_scan(&fix);
1417 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1418 }
1419 key->mono.vs_fetch_opencode = opencode;
1420 }
1421
1422 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1423 struct si_shader_selector *vs,
1424 struct si_shader_key *key)
1425 {
1426 struct si_shader_selector *ps = sctx->ps_shader.cso;
1427
1428 key->opt.clip_disable =
1429 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1430 (vs->info.clipdist_writemask ||
1431 vs->info.writes_clipvertex) &&
1432 !vs->info.culldist_writemask;
1433
1434 /* Find out if PS is disabled. */
1435 bool ps_disabled = true;
1436 if (ps) {
1437 const struct si_state_blend *blend = sctx->queued.named.blend;
1438 bool alpha_to_coverage = blend && blend->alpha_to_coverage;
1439 bool ps_modifies_zs = ps->info.uses_kill ||
1440 ps->info.writes_z ||
1441 ps->info.writes_stencil ||
1442 ps->info.writes_samplemask ||
1443 alpha_to_coverage ||
1444 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1445 unsigned ps_colormask = si_get_total_colormask(sctx);
1446
1447 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1448 (!ps_colormask &&
1449 !ps_modifies_zs &&
1450 !ps->info.writes_memory);
1451 }
1452
1453 /* Find out which VS outputs aren't used by the PS. */
1454 uint64_t outputs_written = vs->outputs_written_before_ps;
1455 uint64_t inputs_read = 0;
1456
1457 /* Ignore outputs that are not passed from VS to PS. */
1458 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1459 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1460 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1461
1462 if (!ps_disabled) {
1463 inputs_read = ps->inputs_read;
1464 }
1465
1466 uint64_t linked = outputs_written & inputs_read;
1467
1468 key->opt.kill_outputs = ~linked & outputs_written;
1469 }
1470
1471 /* Compute the key for the hw shader variant */
1472 static inline void si_shader_selector_key(struct pipe_context *ctx,
1473 struct si_shader_selector *sel,
1474 struct si_shader_key *key)
1475 {
1476 struct si_context *sctx = (struct si_context *)ctx;
1477
1478 memset(key, 0, sizeof(*key));
1479
1480 switch (sel->type) {
1481 case PIPE_SHADER_VERTEX:
1482 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1483
1484 if (sctx->tes_shader.cso)
1485 key->as_ls = 1;
1486 else if (sctx->gs_shader.cso)
1487 key->as_es = 1;
1488 else {
1489 si_shader_selector_key_hw_vs(sctx, sel, key);
1490
1491 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1492 key->mono.u.vs_export_prim_id = 1;
1493 }
1494 break;
1495 case PIPE_SHADER_TESS_CTRL:
1496 if (sctx->chip_class >= GFX9) {
1497 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1498 key, &key->part.tcs.ls_prolog);
1499 key->part.tcs.ls = sctx->vs_shader.cso;
1500
1501 /* When the LS VGPR fix is needed, monolithic shaders
1502 * can:
1503 * - avoid initializing EXEC in both the LS prolog
1504 * and the LS main part when !vs_needs_prolog
1505 * - remove the fixup for unused input VGPRs
1506 */
1507 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1508
1509 /* The LS output / HS input layout can be communicated
1510 * directly instead of via user SGPRs for merged LS-HS.
1511 * The LS VGPR fix prefers this too.
1512 */
1513 key->opt.prefer_mono = 1;
1514 }
1515
1516 key->part.tcs.epilog.prim_mode =
1517 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1518 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1519 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1520 key->part.tcs.epilog.tes_reads_tess_factors =
1521 sctx->tes_shader.cso->info.reads_tess_factors;
1522
1523 if (sel == sctx->fixed_func_tcs_shader.cso)
1524 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1525 break;
1526 case PIPE_SHADER_TESS_EVAL:
1527 if (sctx->gs_shader.cso)
1528 key->as_es = 1;
1529 else {
1530 si_shader_selector_key_hw_vs(sctx, sel, key);
1531
1532 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1533 key->mono.u.vs_export_prim_id = 1;
1534 }
1535 break;
1536 case PIPE_SHADER_GEOMETRY:
1537 if (sctx->chip_class >= GFX9) {
1538 if (sctx->tes_shader.cso) {
1539 key->part.gs.es = sctx->tes_shader.cso;
1540 } else {
1541 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1542 key, &key->part.gs.vs_prolog);
1543 key->part.gs.es = sctx->vs_shader.cso;
1544 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1545 }
1546
1547 /* Merged ES-GS can have unbalanced wave usage.
1548 *
1549 * ES threads are per-vertex, while GS threads are
1550 * per-primitive. So without any amplification, there
1551 * are fewer GS threads than ES threads, which can result
1552 * in empty (no-op) GS waves. With too much amplification,
1553 * there are more GS threads than ES threads, which
1554 * can result in empty (no-op) ES waves.
1555 *
1556 * Non-monolithic shaders are implemented by setting EXEC
1557 * at the beginning of shader parts, and don't jump to
1558 * the end if EXEC is 0.
1559 *
1560 * Monolithic shaders use conditional blocks, so they can
1561 * jump and skip empty waves of ES or GS. So set this to
1562 * always use optimized variants, which are monolithic.
1563 */
1564 key->opt.prefer_mono = 1;
1565 }
1566 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1567 break;
1568 case PIPE_SHADER_FRAGMENT: {
1569 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1570 struct si_state_blend *blend = sctx->queued.named.blend;
1571
1572 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1573 sel->info.colors_written == 0x1)
1574 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1575
1576 if (blend) {
1577 /* Select the shader color format based on whether
1578 * blending or alpha are needed.
1579 */
1580 key->part.ps.epilog.spi_shader_col_format =
1581 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1582 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1583 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1584 sctx->framebuffer.spi_shader_col_format_blend) |
1585 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1586 sctx->framebuffer.spi_shader_col_format_alpha) |
1587 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1588 sctx->framebuffer.spi_shader_col_format);
1589 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1590
1591 /* The output for dual source blending should have
1592 * the same format as the first output.
1593 */
1594 if (blend->dual_src_blend)
1595 key->part.ps.epilog.spi_shader_col_format |=
1596 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1597 } else
1598 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1599
1600 /* If alpha-to-coverage is enabled, we have to export alpha
1601 * even if there is no color buffer.
1602 */
1603 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1604 blend && blend->alpha_to_coverage)
1605 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1606
1607 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1608 * to the range supported by the type if a channel has less
1609 * than 16 bits and the export format is 16_ABGR.
1610 */
1611 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1612 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1613 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1614 }
1615
1616 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1617 if (!key->part.ps.epilog.last_cbuf) {
1618 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1619 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1620 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1621 }
1622
1623 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1624 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1625
1626 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1627 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1628
1629 if (sctx->queued.named.blend) {
1630 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1631 rs->multisample_enable;
1632 }
1633
1634 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1635 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1636 (is_line && rs->line_smooth)) &&
1637 sctx->framebuffer.nr_samples <= 1;
1638 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1639
1640 if (sctx->ps_iter_samples > 1 &&
1641 sel->info.reads_samplemask) {
1642 key->part.ps.prolog.samplemask_log_ps_iter =
1643 util_logbase2(sctx->ps_iter_samples);
1644 }
1645
1646 if (rs->force_persample_interp &&
1647 rs->multisample_enable &&
1648 sctx->framebuffer.nr_samples > 1 &&
1649 sctx->ps_iter_samples > 1) {
1650 key->part.ps.prolog.force_persp_sample_interp =
1651 sel->info.uses_persp_center ||
1652 sel->info.uses_persp_centroid;
1653
1654 key->part.ps.prolog.force_linear_sample_interp =
1655 sel->info.uses_linear_center ||
1656 sel->info.uses_linear_centroid;
1657 } else if (rs->multisample_enable &&
1658 sctx->framebuffer.nr_samples > 1) {
1659 key->part.ps.prolog.bc_optimize_for_persp =
1660 sel->info.uses_persp_center &&
1661 sel->info.uses_persp_centroid;
1662 key->part.ps.prolog.bc_optimize_for_linear =
1663 sel->info.uses_linear_center &&
1664 sel->info.uses_linear_centroid;
1665 } else {
1666 /* Make sure SPI doesn't compute more than 1 pair
1667 * of (i,j), which is the optimization here. */
1668 key->part.ps.prolog.force_persp_center_interp =
1669 sel->info.uses_persp_center +
1670 sel->info.uses_persp_centroid +
1671 sel->info.uses_persp_sample > 1;
1672
1673 key->part.ps.prolog.force_linear_center_interp =
1674 sel->info.uses_linear_center +
1675 sel->info.uses_linear_centroid +
1676 sel->info.uses_linear_sample > 1;
1677
1678 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
1679 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1680 }
1681
1682 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1683
1684 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1685 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
1686 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
1687 struct pipe_resource *tex = cb0->texture;
1688
1689 /* 1D textures are allocated and used as 2D on GFX9. */
1690 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
1691 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
1692 (tex->target == PIPE_TEXTURE_1D ||
1693 tex->target == PIPE_TEXTURE_1D_ARRAY);
1694 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
1695 tex->target == PIPE_TEXTURE_2D_ARRAY ||
1696 tex->target == PIPE_TEXTURE_CUBE ||
1697 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
1698 tex->target == PIPE_TEXTURE_3D;
1699 }
1700 break;
1701 }
1702 default:
1703 assert(0);
1704 }
1705
1706 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
1707 memset(&key->opt, 0, sizeof(key->opt));
1708 }
1709
1710 static void si_build_shader_variant(struct si_shader *shader,
1711 int thread_index,
1712 bool low_priority)
1713 {
1714 struct si_shader_selector *sel = shader->selector;
1715 struct si_screen *sscreen = sel->screen;
1716 struct ac_llvm_compiler *compiler;
1717 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1718 int r;
1719
1720 if (thread_index >= 0) {
1721 if (low_priority) {
1722 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
1723 compiler = &sscreen->compiler_lowp[thread_index];
1724 } else {
1725 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
1726 compiler = &sscreen->compiler[thread_index];
1727 }
1728 if (!debug->async)
1729 debug = NULL;
1730 } else {
1731 assert(!low_priority);
1732 compiler = shader->compiler_ctx_state.compiler;
1733 }
1734
1735 r = si_shader_create(sscreen, compiler, shader, debug);
1736 if (unlikely(r)) {
1737 PRINT_ERR("Failed to build shader variant (type=%u) %d\n",
1738 sel->type, r);
1739 shader->compilation_failed = true;
1740 return;
1741 }
1742
1743 if (shader->compiler_ctx_state.is_debug_context) {
1744 FILE *f = open_memstream(&shader->shader_log,
1745 &shader->shader_log_size);
1746 if (f) {
1747 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1748 fclose(f);
1749 }
1750 }
1751
1752 si_shader_init_pm4_state(sscreen, shader);
1753 }
1754
1755 static void si_build_shader_variant_low_priority(void *job, int thread_index)
1756 {
1757 struct si_shader *shader = (struct si_shader *)job;
1758
1759 assert(thread_index >= 0);
1760
1761 si_build_shader_variant(shader, thread_index, true);
1762 }
1763
1764 static const struct si_shader_key zeroed;
1765
1766 static bool si_check_missing_main_part(struct si_screen *sscreen,
1767 struct si_shader_selector *sel,
1768 struct si_compiler_ctx_state *compiler_state,
1769 struct si_shader_key *key)
1770 {
1771 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1772
1773 if (!*mainp) {
1774 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1775
1776 if (!main_part)
1777 return false;
1778
1779 /* We can leave the fence as permanently signaled because the
1780 * main part becomes visible globally only after it has been
1781 * compiled. */
1782 util_queue_fence_init(&main_part->ready);
1783
1784 main_part->selector = sel;
1785 main_part->key.as_es = key->as_es;
1786 main_part->key.as_ls = key->as_ls;
1787 main_part->is_monolithic = false;
1788
1789 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
1790 main_part, &compiler_state->debug) != 0) {
1791 FREE(main_part);
1792 return false;
1793 }
1794 *mainp = main_part;
1795 }
1796 return true;
1797 }
1798
1799 /**
1800 * Select a shader variant according to the shader key.
1801 *
1802 * \param optimized_or_none If the key describes an optimized shader variant and
1803 * the compilation isn't finished, don't select any
1804 * shader and return an error.
1805 */
1806 int si_shader_select_with_key(struct si_screen *sscreen,
1807 struct si_shader_ctx_state *state,
1808 struct si_compiler_ctx_state *compiler_state,
1809 struct si_shader_key *key,
1810 int thread_index,
1811 bool optimized_or_none)
1812 {
1813 struct si_shader_selector *sel = state->cso;
1814 struct si_shader_selector *previous_stage_sel = NULL;
1815 struct si_shader *current = state->current;
1816 struct si_shader *iter, *shader = NULL;
1817
1818 again:
1819 /* Check if we don't need to change anything.
1820 * This path is also used for most shaders that don't need multiple
1821 * variants, it will cost just a computation of the key and this
1822 * test. */
1823 if (likely(current &&
1824 memcmp(&current->key, key, sizeof(*key)) == 0)) {
1825 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
1826 if (current->is_optimized) {
1827 if (optimized_or_none)
1828 return -1;
1829
1830 memset(&key->opt, 0, sizeof(key->opt));
1831 goto current_not_ready;
1832 }
1833
1834 util_queue_fence_wait(&current->ready);
1835 }
1836
1837 return current->compilation_failed ? -1 : 0;
1838 }
1839 current_not_ready:
1840
1841 /* This must be done before the mutex is locked, because async GS
1842 * compilation calls this function too, and therefore must enter
1843 * the mutex first.
1844 *
1845 * Only wait if we are in a draw call. Don't wait if we are
1846 * in a compiler thread.
1847 */
1848 if (thread_index < 0)
1849 util_queue_fence_wait(&sel->ready);
1850
1851 mtx_lock(&sel->mutex);
1852
1853 /* Find the shader variant. */
1854 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1855 /* Don't check the "current" shader. We checked it above. */
1856 if (current != iter &&
1857 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1858 mtx_unlock(&sel->mutex);
1859
1860 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
1861 /* If it's an optimized shader and its compilation has
1862 * been started but isn't done, use the unoptimized
1863 * shader so as not to cause a stall due to compilation.
1864 */
1865 if (iter->is_optimized) {
1866 if (optimized_or_none)
1867 return -1;
1868 memset(&key->opt, 0, sizeof(key->opt));
1869 goto again;
1870 }
1871
1872 util_queue_fence_wait(&iter->ready);
1873 }
1874
1875 if (iter->compilation_failed) {
1876 return -1; /* skip the draw call */
1877 }
1878
1879 state->current = iter;
1880 return 0;
1881 }
1882 }
1883
1884 /* Build a new shader. */
1885 shader = CALLOC_STRUCT(si_shader);
1886 if (!shader) {
1887 mtx_unlock(&sel->mutex);
1888 return -ENOMEM;
1889 }
1890
1891 util_queue_fence_init(&shader->ready);
1892
1893 shader->selector = sel;
1894 shader->key = *key;
1895 shader->compiler_ctx_state = *compiler_state;
1896
1897 /* If this is a merged shader, get the first shader's selector. */
1898 if (sscreen->info.chip_class >= GFX9) {
1899 if (sel->type == PIPE_SHADER_TESS_CTRL)
1900 previous_stage_sel = key->part.tcs.ls;
1901 else if (sel->type == PIPE_SHADER_GEOMETRY)
1902 previous_stage_sel = key->part.gs.es;
1903
1904 /* We need to wait for the previous shader. */
1905 if (previous_stage_sel && thread_index < 0)
1906 util_queue_fence_wait(&previous_stage_sel->ready);
1907 }
1908
1909 bool is_pure_monolithic =
1910 sscreen->use_monolithic_shaders ||
1911 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1912
1913 /* Compile the main shader part if it doesn't exist. This can happen
1914 * if the initial guess was wrong.
1915 *
1916 * The prim discard CS doesn't need the main shader part.
1917 */
1918 if (!is_pure_monolithic &&
1919 !key->opt.vs_as_prim_discard_cs) {
1920 bool ok;
1921
1922 /* Make sure the main shader part is present. This is needed
1923 * for shaders that can be compiled as VS, LS, or ES, and only
1924 * one of them is compiled at creation.
1925 *
1926 * For merged shaders, check that the starting shader's main
1927 * part is present.
1928 */
1929 if (previous_stage_sel) {
1930 struct si_shader_key shader1_key = zeroed;
1931
1932 if (sel->type == PIPE_SHADER_TESS_CTRL)
1933 shader1_key.as_ls = 1;
1934 else if (sel->type == PIPE_SHADER_GEOMETRY)
1935 shader1_key.as_es = 1;
1936 else
1937 assert(0);
1938
1939 mtx_lock(&previous_stage_sel->mutex);
1940 ok = si_check_missing_main_part(sscreen,
1941 previous_stage_sel,
1942 compiler_state, &shader1_key);
1943 mtx_unlock(&previous_stage_sel->mutex);
1944 } else {
1945 ok = si_check_missing_main_part(sscreen, sel,
1946 compiler_state, key);
1947 }
1948 if (!ok) {
1949 FREE(shader);
1950 mtx_unlock(&sel->mutex);
1951 return -ENOMEM; /* skip the draw call */
1952 }
1953 }
1954
1955 /* Keep the reference to the 1st shader of merged shaders, so that
1956 * Gallium can't destroy it before we destroy the 2nd shader.
1957 *
1958 * Set sctx = NULL, because it's unused if we're not releasing
1959 * the shader, and we don't have any sctx here.
1960 */
1961 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
1962 previous_stage_sel);
1963
1964 /* Monolithic-only shaders don't make a distinction between optimized
1965 * and unoptimized. */
1966 shader->is_monolithic =
1967 is_pure_monolithic ||
1968 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1969
1970 /* The prim discard CS is always optimized. */
1971 shader->is_optimized =
1972 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
1973 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1974
1975 /* If it's an optimized shader, compile it asynchronously. */
1976 if (shader->is_optimized && thread_index < 0) {
1977 /* Compile it asynchronously. */
1978 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
1979 shader, &shader->ready,
1980 si_build_shader_variant_low_priority, NULL);
1981
1982 /* Add only after the ready fence was reset, to guard against a
1983 * race with si_bind_XX_shader. */
1984 if (!sel->last_variant) {
1985 sel->first_variant = shader;
1986 sel->last_variant = shader;
1987 } else {
1988 sel->last_variant->next_variant = shader;
1989 sel->last_variant = shader;
1990 }
1991
1992 /* Use the default (unoptimized) shader for now. */
1993 memset(&key->opt, 0, sizeof(key->opt));
1994 mtx_unlock(&sel->mutex);
1995
1996 if (sscreen->options.sync_compile)
1997 util_queue_fence_wait(&shader->ready);
1998
1999 if (optimized_or_none)
2000 return -1;
2001 goto again;
2002 }
2003
2004 /* Reset the fence before adding to the variant list. */
2005 util_queue_fence_reset(&shader->ready);
2006
2007 if (!sel->last_variant) {
2008 sel->first_variant = shader;
2009 sel->last_variant = shader;
2010 } else {
2011 sel->last_variant->next_variant = shader;
2012 sel->last_variant = shader;
2013 }
2014
2015 mtx_unlock(&sel->mutex);
2016
2017 assert(!shader->is_optimized);
2018 si_build_shader_variant(shader, thread_index, false);
2019
2020 util_queue_fence_signal(&shader->ready);
2021
2022 if (!shader->compilation_failed)
2023 state->current = shader;
2024
2025 return shader->compilation_failed ? -1 : 0;
2026 }
2027
2028 static int si_shader_select(struct pipe_context *ctx,
2029 struct si_shader_ctx_state *state,
2030 struct si_compiler_ctx_state *compiler_state)
2031 {
2032 struct si_context *sctx = (struct si_context *)ctx;
2033 struct si_shader_key key;
2034
2035 si_shader_selector_key(ctx, state->cso, &key);
2036 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2037 &key, -1, false);
2038 }
2039
2040 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2041 bool streamout,
2042 struct si_shader_key *key)
2043 {
2044 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2045
2046 switch (info->processor) {
2047 case PIPE_SHADER_VERTEX:
2048 switch (next_shader) {
2049 case PIPE_SHADER_GEOMETRY:
2050 key->as_es = 1;
2051 break;
2052 case PIPE_SHADER_TESS_CTRL:
2053 case PIPE_SHADER_TESS_EVAL:
2054 key->as_ls = 1;
2055 break;
2056 default:
2057 /* If POSITION isn't written, it can only be a HW VS
2058 * if streamout is used. If streamout isn't used,
2059 * assume that it's a HW LS. (the next shader is TCS)
2060 * This heuristic is needed for separate shader objects.
2061 */
2062 if (!info->writes_position && !streamout)
2063 key->as_ls = 1;
2064 }
2065 break;
2066
2067 case PIPE_SHADER_TESS_EVAL:
2068 if (next_shader == PIPE_SHADER_GEOMETRY ||
2069 !info->writes_position)
2070 key->as_es = 1;
2071 break;
2072 }
2073 }
2074
2075 /**
2076 * Compile the main shader part or the monolithic shader as part of
2077 * si_shader_selector initialization. Since it can be done asynchronously,
2078 * there is no way to report compile failures to applications.
2079 */
2080 static void si_init_shader_selector_async(void *job, int thread_index)
2081 {
2082 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2083 struct si_screen *sscreen = sel->screen;
2084 struct ac_llvm_compiler *compiler;
2085 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2086
2087 assert(!debug->debug_message || debug->async);
2088 assert(thread_index >= 0);
2089 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2090 compiler = &sscreen->compiler[thread_index];
2091
2092 if (sel->nir)
2093 si_lower_nir(sel);
2094
2095 /* Compile the main shader part for use with a prolog and/or epilog.
2096 * If this fails, the driver will try to compile a monolithic shader
2097 * on demand.
2098 */
2099 if (!sscreen->use_monolithic_shaders) {
2100 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2101 void *ir_binary = NULL;
2102
2103 if (!shader) {
2104 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2105 return;
2106 }
2107
2108 /* We can leave the fence signaled because use of the default
2109 * main part is guarded by the selector's ready fence. */
2110 util_queue_fence_init(&shader->ready);
2111
2112 shader->selector = sel;
2113 shader->is_monolithic = false;
2114 si_parse_next_shader_property(&sel->info,
2115 sel->so.num_outputs != 0,
2116 &shader->key);
2117
2118 if (sel->tokens || sel->nir)
2119 ir_binary = si_get_ir_binary(sel);
2120
2121 /* Try to load the shader from the shader cache. */
2122 mtx_lock(&sscreen->shader_cache_mutex);
2123
2124 if (ir_binary &&
2125 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2126 mtx_unlock(&sscreen->shader_cache_mutex);
2127 si_shader_dump_stats_for_shader_db(shader, debug);
2128 } else {
2129 mtx_unlock(&sscreen->shader_cache_mutex);
2130
2131 /* Compile the shader if it hasn't been loaded from the cache. */
2132 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2133 debug) != 0) {
2134 FREE(shader);
2135 FREE(ir_binary);
2136 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2137 return;
2138 }
2139
2140 if (ir_binary) {
2141 mtx_lock(&sscreen->shader_cache_mutex);
2142 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2143 FREE(ir_binary);
2144 mtx_unlock(&sscreen->shader_cache_mutex);
2145 }
2146 }
2147
2148 *si_get_main_shader_part(sel, &shader->key) = shader;
2149
2150 /* Unset "outputs_written" flags for outputs converted to
2151 * DEFAULT_VAL, so that later inter-shader optimizations don't
2152 * try to eliminate outputs that don't exist in the final
2153 * shader.
2154 *
2155 * This is only done if non-monolithic shaders are enabled.
2156 */
2157 if ((sel->type == PIPE_SHADER_VERTEX ||
2158 sel->type == PIPE_SHADER_TESS_EVAL) &&
2159 !shader->key.as_ls &&
2160 !shader->key.as_es) {
2161 unsigned i;
2162
2163 for (i = 0; i < sel->info.num_outputs; i++) {
2164 unsigned offset = shader->info.vs_output_param_offset[i];
2165
2166 if (offset <= AC_EXP_PARAM_OFFSET_31)
2167 continue;
2168
2169 unsigned name = sel->info.output_semantic_name[i];
2170 unsigned index = sel->info.output_semantic_index[i];
2171 unsigned id;
2172
2173 switch (name) {
2174 case TGSI_SEMANTIC_GENERIC:
2175 /* don't process indices the function can't handle */
2176 if (index >= SI_MAX_IO_GENERIC)
2177 break;
2178 /* fall through */
2179 default:
2180 id = si_shader_io_get_unique_index(name, index, true);
2181 sel->outputs_written_before_ps &= ~(1ull << id);
2182 break;
2183 case TGSI_SEMANTIC_POSITION: /* ignore these */
2184 case TGSI_SEMANTIC_PSIZE:
2185 case TGSI_SEMANTIC_CLIPVERTEX:
2186 case TGSI_SEMANTIC_EDGEFLAG:
2187 break;
2188 }
2189 }
2190 }
2191 }
2192
2193 /* The GS copy shader is always pre-compiled. */
2194 if (sel->type == PIPE_SHADER_GEOMETRY) {
2195 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2196 if (!sel->gs_copy_shader) {
2197 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2198 return;
2199 }
2200
2201 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2202 }
2203 }
2204
2205 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2206 struct util_queue_fence *ready_fence,
2207 struct si_compiler_ctx_state *compiler_ctx_state,
2208 void *job, util_queue_execute_func execute)
2209 {
2210 util_queue_fence_init(ready_fence);
2211
2212 struct util_async_debug_callback async_debug;
2213 bool debug =
2214 (sctx->debug.debug_message && !sctx->debug.async) ||
2215 sctx->is_debug ||
2216 si_can_dump_shader(sctx->screen, processor);
2217
2218 if (debug) {
2219 u_async_debug_init(&async_debug);
2220 compiler_ctx_state->debug = async_debug.base;
2221 }
2222
2223 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2224 ready_fence, execute, NULL);
2225
2226 if (debug) {
2227 util_queue_fence_wait(ready_fence);
2228 u_async_debug_drain(&async_debug, &sctx->debug);
2229 u_async_debug_cleanup(&async_debug);
2230 }
2231
2232 if (sctx->screen->options.sync_compile)
2233 util_queue_fence_wait(ready_fence);
2234 }
2235
2236 /* Return descriptor slot usage masks from the given shader info. */
2237 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2238 uint32_t *const_and_shader_buffers,
2239 uint64_t *samplers_and_images)
2240 {
2241 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2242
2243 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2244 num_constbufs = util_last_bit(info->const_buffers_declared);
2245 /* two 8-byte images share one 16-byte slot */
2246 num_images = align(util_last_bit(info->images_declared), 2);
2247 num_samplers = util_last_bit(info->samplers_declared);
2248
2249 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2250 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2251 *const_and_shader_buffers =
2252 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2253
2254 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2255 start = si_get_image_slot(num_images - 1) / 2;
2256 *samplers_and_images =
2257 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2258 }
2259
2260 static void *si_create_shader_selector(struct pipe_context *ctx,
2261 const struct pipe_shader_state *state)
2262 {
2263 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2264 struct si_context *sctx = (struct si_context*)ctx;
2265 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2266 int i;
2267
2268 if (!sel)
2269 return NULL;
2270
2271 pipe_reference_init(&sel->reference, 1);
2272 sel->screen = sscreen;
2273 sel->compiler_ctx_state.debug = sctx->debug;
2274 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2275
2276 sel->so = state->stream_output;
2277
2278 if (state->type == PIPE_SHADER_IR_TGSI) {
2279 sel->tokens = tgsi_dup_tokens(state->tokens);
2280 if (!sel->tokens) {
2281 FREE(sel);
2282 return NULL;
2283 }
2284
2285 tgsi_scan_shader(state->tokens, &sel->info);
2286 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2287 } else {
2288 assert(state->type == PIPE_SHADER_IR_NIR);
2289
2290 sel->nir = state->ir.nir;
2291
2292 si_nir_opts(sel->nir);
2293 si_nir_scan_shader(sel->nir, &sel->info);
2294 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2295 }
2296
2297 sel->type = sel->info.processor;
2298 p_atomic_inc(&sscreen->num_shaders_created);
2299 si_get_active_slot_masks(&sel->info,
2300 &sel->active_const_and_shader_buffers,
2301 &sel->active_samplers_and_images);
2302
2303 /* Record which streamout buffers are enabled. */
2304 for (i = 0; i < sel->so.num_outputs; i++) {
2305 sel->enabled_streamout_buffer_mask |=
2306 (1 << sel->so.output[i].output_buffer) <<
2307 (sel->so.output[i].stream * 4);
2308 }
2309
2310 /* The prolog is a no-op if there are no inputs. */
2311 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2312 sel->info.num_inputs &&
2313 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2314
2315 sel->force_correct_derivs_after_kill =
2316 sel->type == PIPE_SHADER_FRAGMENT &&
2317 sel->info.uses_derivatives &&
2318 sel->info.uses_kill &&
2319 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2320
2321 sel->prim_discard_cs_allowed =
2322 sel->type == PIPE_SHADER_VERTEX &&
2323 !sel->info.uses_bindless_images &&
2324 !sel->info.uses_bindless_samplers &&
2325 !sel->info.writes_memory &&
2326 !sel->info.writes_viewport_index &&
2327 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2328 !sel->so.num_outputs;
2329
2330 /* Set which opcode uses which (i,j) pair. */
2331 if (sel->info.uses_persp_opcode_interp_centroid)
2332 sel->info.uses_persp_centroid = true;
2333
2334 if (sel->info.uses_linear_opcode_interp_centroid)
2335 sel->info.uses_linear_centroid = true;
2336
2337 if (sel->info.uses_persp_opcode_interp_offset ||
2338 sel->info.uses_persp_opcode_interp_sample)
2339 sel->info.uses_persp_center = true;
2340
2341 if (sel->info.uses_linear_opcode_interp_offset ||
2342 sel->info.uses_linear_opcode_interp_sample)
2343 sel->info.uses_linear_center = true;
2344
2345 switch (sel->type) {
2346 case PIPE_SHADER_GEOMETRY:
2347 sel->gs_output_prim =
2348 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2349 sel->gs_max_out_vertices =
2350 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2351 sel->gs_num_invocations =
2352 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2353 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2354 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2355 sel->gs_max_out_vertices;
2356
2357 sel->max_gs_stream = 0;
2358 for (i = 0; i < sel->so.num_outputs; i++)
2359 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2360 sel->so.output[i].stream);
2361
2362 sel->gs_input_verts_per_prim =
2363 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2364 break;
2365
2366 case PIPE_SHADER_TESS_CTRL:
2367 /* Always reserve space for these. */
2368 sel->patch_outputs_written |=
2369 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2370 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2371 /* fall through */
2372 case PIPE_SHADER_VERTEX:
2373 case PIPE_SHADER_TESS_EVAL:
2374 for (i = 0; i < sel->info.num_outputs; i++) {
2375 unsigned name = sel->info.output_semantic_name[i];
2376 unsigned index = sel->info.output_semantic_index[i];
2377
2378 switch (name) {
2379 case TGSI_SEMANTIC_TESSINNER:
2380 case TGSI_SEMANTIC_TESSOUTER:
2381 case TGSI_SEMANTIC_PATCH:
2382 sel->patch_outputs_written |=
2383 1ull << si_shader_io_get_unique_index_patch(name, index);
2384 break;
2385
2386 case TGSI_SEMANTIC_GENERIC:
2387 /* don't process indices the function can't handle */
2388 if (index >= SI_MAX_IO_GENERIC)
2389 break;
2390 /* fall through */
2391 default:
2392 sel->outputs_written |=
2393 1ull << si_shader_io_get_unique_index(name, index, false);
2394 sel->outputs_written_before_ps |=
2395 1ull << si_shader_io_get_unique_index(name, index, true);
2396 break;
2397 case TGSI_SEMANTIC_EDGEFLAG:
2398 break;
2399 }
2400 }
2401 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2402 sel->lshs_vertex_stride = sel->esgs_itemsize;
2403
2404 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2405 * will start on a different bank. (except for the maximum 32*16).
2406 */
2407 if (sel->lshs_vertex_stride < 32*16)
2408 sel->lshs_vertex_stride += 4;
2409
2410 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2411 * conflicts, i.e. each vertex will start at a different bank.
2412 */
2413 if (sctx->chip_class >= GFX9)
2414 sel->esgs_itemsize += 4;
2415
2416 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2417 break;
2418
2419 case PIPE_SHADER_FRAGMENT:
2420 for (i = 0; i < sel->info.num_inputs; i++) {
2421 unsigned name = sel->info.input_semantic_name[i];
2422 unsigned index = sel->info.input_semantic_index[i];
2423
2424 switch (name) {
2425 case TGSI_SEMANTIC_GENERIC:
2426 /* don't process indices the function can't handle */
2427 if (index >= SI_MAX_IO_GENERIC)
2428 break;
2429 /* fall through */
2430 default:
2431 sel->inputs_read |=
2432 1ull << si_shader_io_get_unique_index(name, index, true);
2433 break;
2434 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2435 break;
2436 }
2437 }
2438
2439 for (i = 0; i < 8; i++)
2440 if (sel->info.colors_written & (1 << i))
2441 sel->colors_written_4bit |= 0xf << (4 * i);
2442
2443 for (i = 0; i < sel->info.num_inputs; i++) {
2444 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2445 int index = sel->info.input_semantic_index[i];
2446 sel->color_attr_index[index] = i;
2447 }
2448 }
2449 break;
2450 }
2451
2452 /* PA_CL_VS_OUT_CNTL */
2453 bool misc_vec_ena =
2454 sel->info.writes_psize || sel->info.writes_edgeflag ||
2455 sel->info.writes_layer || sel->info.writes_viewport_index;
2456 sel->pa_cl_vs_out_cntl =
2457 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2458 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2459 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2460 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2461 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2462 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2463 sel->clipdist_mask = sel->info.writes_clipvertex ?
2464 SIX_BITS : sel->info.clipdist_writemask;
2465 sel->culldist_mask = sel->info.culldist_writemask <<
2466 sel->info.num_written_clipdistance;
2467
2468 /* DB_SHADER_CONTROL */
2469 sel->db_shader_control =
2470 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2471 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2472 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2473 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2474
2475 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2476 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2477 sel->db_shader_control |=
2478 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2479 break;
2480 case TGSI_FS_DEPTH_LAYOUT_LESS:
2481 sel->db_shader_control |=
2482 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2483 break;
2484 }
2485
2486 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2487 *
2488 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2489 * --|-----------|------------|------------|--------------------|-------------------|-------------
2490 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2491 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2492 * 2 | false | true | n/a | LateZ | 1 | 0
2493 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2494 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2495 *
2496 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2497 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2498 *
2499 * Don't use ReZ without profiling !!!
2500 *
2501 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2502 * shaders.
2503 */
2504 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2505 /* Cases 3, 4. */
2506 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2507 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2508 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2509 } else if (sel->info.writes_memory) {
2510 /* Case 2. */
2511 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2512 S_02880C_EXEC_ON_HIER_FAIL(1);
2513 } else {
2514 /* Case 1. */
2515 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2516 }
2517
2518 (void) mtx_init(&sel->mutex, mtx_plain);
2519
2520 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2521 &sel->compiler_ctx_state, sel,
2522 si_init_shader_selector_async);
2523 return sel;
2524 }
2525
2526 static void si_update_streamout_state(struct si_context *sctx)
2527 {
2528 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2529
2530 if (!shader_with_so)
2531 return;
2532
2533 sctx->streamout.enabled_stream_buffers_mask =
2534 shader_with_so->enabled_streamout_buffer_mask;
2535 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2536 }
2537
2538 static void si_update_clip_regs(struct si_context *sctx,
2539 struct si_shader_selector *old_hw_vs,
2540 struct si_shader *old_hw_vs_variant,
2541 struct si_shader_selector *next_hw_vs,
2542 struct si_shader *next_hw_vs_variant)
2543 {
2544 if (next_hw_vs &&
2545 (!old_hw_vs ||
2546 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2547 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2548 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2549 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2550 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2551 !old_hw_vs_variant ||
2552 !next_hw_vs_variant ||
2553 old_hw_vs_variant->key.opt.clip_disable !=
2554 next_hw_vs_variant->key.opt.clip_disable))
2555 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2556 }
2557
2558 static void si_update_common_shader_state(struct si_context *sctx)
2559 {
2560 sctx->uses_bindless_samplers =
2561 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2562 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2563 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2564 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2565 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2566 sctx->uses_bindless_images =
2567 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2568 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2569 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2570 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2571 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2572 sctx->do_update_shaders = true;
2573 }
2574
2575 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2576 {
2577 struct si_context *sctx = (struct si_context *)ctx;
2578 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2579 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2580 struct si_shader_selector *sel = state;
2581
2582 if (sctx->vs_shader.cso == sel)
2583 return;
2584
2585 sctx->vs_shader.cso = sel;
2586 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2587 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2588
2589 si_update_common_shader_state(sctx);
2590 si_update_vs_viewport_state(sctx);
2591 si_set_active_descriptors_for_shader(sctx, sel);
2592 si_update_streamout_state(sctx);
2593 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2594 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2595 }
2596
2597 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2598 {
2599 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2600 (sctx->tes_shader.cso &&
2601 sctx->tes_shader.cso->info.uses_primid) ||
2602 (sctx->tcs_shader.cso &&
2603 sctx->tcs_shader.cso->info.uses_primid) ||
2604 (sctx->gs_shader.cso &&
2605 sctx->gs_shader.cso->info.uses_primid) ||
2606 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2607 sctx->ps_shader.cso->info.uses_primid);
2608 }
2609
2610 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2611 {
2612 struct si_context *sctx = (struct si_context *)ctx;
2613 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2614 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2615 struct si_shader_selector *sel = state;
2616 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2617
2618 if (sctx->gs_shader.cso == sel)
2619 return;
2620
2621 sctx->gs_shader.cso = sel;
2622 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2623 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2624
2625 si_update_common_shader_state(sctx);
2626 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2627
2628 if (enable_changed) {
2629 si_shader_change_notify(sctx);
2630 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2631 si_update_tess_uses_prim_id(sctx);
2632 }
2633 si_update_vs_viewport_state(sctx);
2634 si_set_active_descriptors_for_shader(sctx, sel);
2635 si_update_streamout_state(sctx);
2636 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2637 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2638 }
2639
2640 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2641 {
2642 struct si_context *sctx = (struct si_context *)ctx;
2643 struct si_shader_selector *sel = state;
2644 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2645
2646 if (sctx->tcs_shader.cso == sel)
2647 return;
2648
2649 sctx->tcs_shader.cso = sel;
2650 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2651 si_update_tess_uses_prim_id(sctx);
2652
2653 si_update_common_shader_state(sctx);
2654
2655 if (enable_changed)
2656 sctx->last_tcs = NULL; /* invalidate derived tess state */
2657
2658 si_set_active_descriptors_for_shader(sctx, sel);
2659 }
2660
2661 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2662 {
2663 struct si_context *sctx = (struct si_context *)ctx;
2664 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2665 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2666 struct si_shader_selector *sel = state;
2667 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2668
2669 if (sctx->tes_shader.cso == sel)
2670 return;
2671
2672 sctx->tes_shader.cso = sel;
2673 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2674 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2675 si_update_tess_uses_prim_id(sctx);
2676
2677 si_update_common_shader_state(sctx);
2678 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2679
2680 if (enable_changed) {
2681 si_shader_change_notify(sctx);
2682 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2683 }
2684 si_update_vs_viewport_state(sctx);
2685 si_set_active_descriptors_for_shader(sctx, sel);
2686 si_update_streamout_state(sctx);
2687 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2688 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2689 }
2690
2691 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2692 {
2693 struct si_context *sctx = (struct si_context *)ctx;
2694 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
2695 struct si_shader_selector *sel = state;
2696
2697 /* skip if supplied shader is one already in use */
2698 if (old_sel == sel)
2699 return;
2700
2701 sctx->ps_shader.cso = sel;
2702 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2703
2704 si_update_common_shader_state(sctx);
2705 if (sel) {
2706 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2707 si_update_tess_uses_prim_id(sctx);
2708
2709 if (!old_sel ||
2710 old_sel->info.colors_written != sel->info.colors_written)
2711 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2712
2713 if (sctx->screen->has_out_of_order_rast &&
2714 (!old_sel ||
2715 old_sel->info.writes_memory != sel->info.writes_memory ||
2716 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
2717 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
2718 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2719 }
2720 si_set_active_descriptors_for_shader(sctx, sel);
2721 si_update_ps_colorbuf0_slot(sctx);
2722 }
2723
2724 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2725 {
2726 if (shader->is_optimized) {
2727 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
2728 &shader->ready);
2729 }
2730
2731 util_queue_fence_destroy(&shader->ready);
2732
2733 if (shader->pm4) {
2734 switch (shader->selector->type) {
2735 case PIPE_SHADER_VERTEX:
2736 if (shader->key.as_ls) {
2737 assert(sctx->chip_class <= GFX8);
2738 si_pm4_delete_state(sctx, ls, shader->pm4);
2739 } else if (shader->key.as_es) {
2740 assert(sctx->chip_class <= GFX8);
2741 si_pm4_delete_state(sctx, es, shader->pm4);
2742 } else {
2743 si_pm4_delete_state(sctx, vs, shader->pm4);
2744 }
2745 break;
2746 case PIPE_SHADER_TESS_CTRL:
2747 si_pm4_delete_state(sctx, hs, shader->pm4);
2748 break;
2749 case PIPE_SHADER_TESS_EVAL:
2750 if (shader->key.as_es) {
2751 assert(sctx->chip_class <= GFX8);
2752 si_pm4_delete_state(sctx, es, shader->pm4);
2753 } else {
2754 si_pm4_delete_state(sctx, vs, shader->pm4);
2755 }
2756 break;
2757 case PIPE_SHADER_GEOMETRY:
2758 if (shader->is_gs_copy_shader)
2759 si_pm4_delete_state(sctx, vs, shader->pm4);
2760 else
2761 si_pm4_delete_state(sctx, gs, shader->pm4);
2762 break;
2763 case PIPE_SHADER_FRAGMENT:
2764 si_pm4_delete_state(sctx, ps, shader->pm4);
2765 break;
2766 }
2767 }
2768
2769 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2770 si_shader_destroy(shader);
2771 free(shader);
2772 }
2773
2774 void si_destroy_shader_selector(struct si_context *sctx,
2775 struct si_shader_selector *sel)
2776 {
2777 struct si_shader *p = sel->first_variant, *c;
2778 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2779 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2780 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2781 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2782 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2783 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2784 };
2785
2786 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
2787
2788 if (current_shader[sel->type]->cso == sel) {
2789 current_shader[sel->type]->cso = NULL;
2790 current_shader[sel->type]->current = NULL;
2791 }
2792
2793 while (p) {
2794 c = p->next_variant;
2795 si_delete_shader(sctx, p);
2796 p = c;
2797 }
2798
2799 if (sel->main_shader_part)
2800 si_delete_shader(sctx, sel->main_shader_part);
2801 if (sel->main_shader_part_ls)
2802 si_delete_shader(sctx, sel->main_shader_part_ls);
2803 if (sel->main_shader_part_es)
2804 si_delete_shader(sctx, sel->main_shader_part_es);
2805 if (sel->gs_copy_shader)
2806 si_delete_shader(sctx, sel->gs_copy_shader);
2807
2808 util_queue_fence_destroy(&sel->ready);
2809 mtx_destroy(&sel->mutex);
2810 free(sel->tokens);
2811 ralloc_free(sel->nir);
2812 free(sel);
2813 }
2814
2815 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
2816 {
2817 struct si_context *sctx = (struct si_context *)ctx;
2818 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2819
2820 si_shader_selector_reference(sctx, &sel, NULL);
2821 }
2822
2823 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2824 struct si_shader *vs, unsigned name,
2825 unsigned index, unsigned interpolate)
2826 {
2827 struct tgsi_shader_info *vsinfo = &vs->selector->info;
2828 unsigned j, offset, ps_input_cntl = 0;
2829
2830 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2831 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
2832 name == TGSI_SEMANTIC_PRIMID)
2833 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2834
2835 if (name == TGSI_SEMANTIC_PCOORD ||
2836 (name == TGSI_SEMANTIC_TEXCOORD &&
2837 sctx->sprite_coord_enable & (1 << index))) {
2838 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2839 }
2840
2841 for (j = 0; j < vsinfo->num_outputs; j++) {
2842 if (name == vsinfo->output_semantic_name[j] &&
2843 index == vsinfo->output_semantic_index[j]) {
2844 offset = vs->info.vs_output_param_offset[j];
2845
2846 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2847 /* The input is loaded from parameter memory. */
2848 ps_input_cntl |= S_028644_OFFSET(offset);
2849 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2850 if (offset == AC_EXP_PARAM_UNDEFINED) {
2851 /* This can happen with depth-only rendering. */
2852 offset = 0;
2853 } else {
2854 /* The input is a DEFAULT_VAL constant. */
2855 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2856 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2857 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2858 }
2859
2860 ps_input_cntl = S_028644_OFFSET(0x20) |
2861 S_028644_DEFAULT_VAL(offset);
2862 }
2863 break;
2864 }
2865 }
2866
2867 if (name == TGSI_SEMANTIC_PRIMID)
2868 /* PrimID is written after the last output. */
2869 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2870 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2871 /* No corresponding output found, load defaults into input.
2872 * Don't set any other bits.
2873 * (FLAT_SHADE=1 completely changes behavior) */
2874 ps_input_cntl = S_028644_OFFSET(0x20);
2875 /* D3D 9 behaviour. GL is undefined */
2876 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2877 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2878 }
2879 return ps_input_cntl;
2880 }
2881
2882 static void si_emit_spi_map(struct si_context *sctx)
2883 {
2884 struct si_shader *ps = sctx->ps_shader.current;
2885 struct si_shader *vs = si_get_vs_state(sctx);
2886 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2887 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2888 unsigned spi_ps_input_cntl[32];
2889
2890 if (!ps || !ps->selector->info.num_inputs)
2891 return;
2892
2893 num_interp = si_get_ps_num_interp(ps);
2894 assert(num_interp > 0);
2895
2896 for (i = 0; i < psinfo->num_inputs; i++) {
2897 unsigned name = psinfo->input_semantic_name[i];
2898 unsigned index = psinfo->input_semantic_index[i];
2899 unsigned interpolate = psinfo->input_interpolate[i];
2900
2901 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
2902 index, interpolate);
2903
2904 if (name == TGSI_SEMANTIC_COLOR) {
2905 assert(index < ARRAY_SIZE(bcol_interp));
2906 bcol_interp[index] = interpolate;
2907 }
2908 }
2909
2910 if (ps->key.part.ps.prolog.color_two_side) {
2911 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2912
2913 for (i = 0; i < 2; i++) {
2914 if (!(psinfo->colors_read & (0xf << (i * 4))))
2915 continue;
2916
2917 spi_ps_input_cntl[num_written++] =
2918 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
2919
2920 }
2921 }
2922 assert(num_interp == num_written);
2923
2924 /* R_028644_SPI_PS_INPUT_CNTL_0 */
2925 /* Dota 2: Only ~16% of SPI map updates set different values. */
2926 /* Talos: Only ~9% of SPI map updates set different values. */
2927 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
2928 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
2929 spi_ps_input_cntl,
2930 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
2931
2932 if (initial_cdw != sctx->gfx_cs->current.cdw)
2933 sctx->context_roll = true;
2934 }
2935
2936 /**
2937 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2938 */
2939 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2940 {
2941 if (sctx->init_config_has_vgt_flush)
2942 return;
2943
2944 /* Done by Vulkan before VGT_FLUSH. */
2945 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2946 si_pm4_cmd_add(sctx->init_config,
2947 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2948 si_pm4_cmd_end(sctx->init_config, false);
2949
2950 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2951 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2952 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2953 si_pm4_cmd_end(sctx->init_config, false);
2954 sctx->init_config_has_vgt_flush = true;
2955 }
2956
2957 /* Initialize state related to ESGS / GSVS ring buffers */
2958 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2959 {
2960 struct si_shader_selector *es =
2961 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2962 struct si_shader_selector *gs = sctx->gs_shader.cso;
2963 struct si_pm4_state *pm4;
2964
2965 /* Chip constants. */
2966 unsigned num_se = sctx->screen->info.max_se;
2967 unsigned wave_size = 64;
2968 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2969 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
2970 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2971 */
2972 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
2973 unsigned alignment = 256 * num_se;
2974 /* The maximum size is 63.999 MB per SE. */
2975 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2976
2977 /* Calculate the minimum size. */
2978 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2979 wave_size, alignment);
2980
2981 /* These are recommended sizes, not minimum sizes. */
2982 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2983 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2984 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2985 gs->max_gsvs_emit_size;
2986
2987 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2988 esgs_ring_size = align(esgs_ring_size, alignment);
2989 gsvs_ring_size = align(gsvs_ring_size, alignment);
2990
2991 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2992 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2993
2994 /* Some rings don't have to be allocated if shaders don't use them.
2995 * (e.g. no varyings between ES and GS or GS and VS)
2996 *
2997 * GFX9 doesn't have the ESGS ring.
2998 */
2999 bool update_esgs = sctx->chip_class <= GFX8 &&
3000 esgs_ring_size &&
3001 (!sctx->esgs_ring ||
3002 sctx->esgs_ring->width0 < esgs_ring_size);
3003 bool update_gsvs = gsvs_ring_size &&
3004 (!sctx->gsvs_ring ||
3005 sctx->gsvs_ring->width0 < gsvs_ring_size);
3006
3007 if (!update_esgs && !update_gsvs)
3008 return true;
3009
3010 if (update_esgs) {
3011 pipe_resource_reference(&sctx->esgs_ring, NULL);
3012 sctx->esgs_ring =
3013 pipe_aligned_buffer_create(sctx->b.screen,
3014 SI_RESOURCE_FLAG_UNMAPPABLE,
3015 PIPE_USAGE_DEFAULT,
3016 esgs_ring_size, alignment);
3017 if (!sctx->esgs_ring)
3018 return false;
3019 }
3020
3021 if (update_gsvs) {
3022 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3023 sctx->gsvs_ring =
3024 pipe_aligned_buffer_create(sctx->b.screen,
3025 SI_RESOURCE_FLAG_UNMAPPABLE,
3026 PIPE_USAGE_DEFAULT,
3027 gsvs_ring_size, alignment);
3028 if (!sctx->gsvs_ring)
3029 return false;
3030 }
3031
3032 /* Create the "init_config_gs_rings" state. */
3033 pm4 = CALLOC_STRUCT(si_pm4_state);
3034 if (!pm4)
3035 return false;
3036
3037 if (sctx->chip_class >= GFX7) {
3038 if (sctx->esgs_ring) {
3039 assert(sctx->chip_class <= GFX8);
3040 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3041 sctx->esgs_ring->width0 / 256);
3042 }
3043 if (sctx->gsvs_ring)
3044 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3045 sctx->gsvs_ring->width0 / 256);
3046 } else {
3047 if (sctx->esgs_ring)
3048 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3049 sctx->esgs_ring->width0 / 256);
3050 if (sctx->gsvs_ring)
3051 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3052 sctx->gsvs_ring->width0 / 256);
3053 }
3054
3055 /* Set the state. */
3056 if (sctx->init_config_gs_rings)
3057 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3058 sctx->init_config_gs_rings = pm4;
3059
3060 if (!sctx->init_config_has_vgt_flush) {
3061 si_init_config_add_vgt_flush(sctx);
3062 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3063 }
3064
3065 /* Flush the context to re-emit both init_config states. */
3066 sctx->initial_gfx_cs_size = 0; /* force flush */
3067 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3068
3069 /* Set ring bindings. */
3070 if (sctx->esgs_ring) {
3071 assert(sctx->chip_class <= GFX8);
3072 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3073 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3074 true, true, 4, 64, 0);
3075 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3076 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3077 false, false, 0, 0, 0);
3078 }
3079 if (sctx->gsvs_ring) {
3080 si_set_ring_buffer(sctx, SI_RING_GSVS,
3081 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3082 false, false, 0, 0, 0);
3083 }
3084
3085 return true;
3086 }
3087
3088 static void si_shader_lock(struct si_shader *shader)
3089 {
3090 mtx_lock(&shader->selector->mutex);
3091 if (shader->previous_stage_sel) {
3092 assert(shader->previous_stage_sel != shader->selector);
3093 mtx_lock(&shader->previous_stage_sel->mutex);
3094 }
3095 }
3096
3097 static void si_shader_unlock(struct si_shader *shader)
3098 {
3099 if (shader->previous_stage_sel)
3100 mtx_unlock(&shader->previous_stage_sel->mutex);
3101 mtx_unlock(&shader->selector->mutex);
3102 }
3103
3104 /**
3105 * @returns 1 if \p sel has been updated to use a new scratch buffer
3106 * 0 if not
3107 * < 0 if there was a failure
3108 */
3109 static int si_update_scratch_buffer(struct si_context *sctx,
3110 struct si_shader *shader)
3111 {
3112 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3113 int r;
3114
3115 if (!shader)
3116 return 0;
3117
3118 /* This shader doesn't need a scratch buffer */
3119 if (shader->config.scratch_bytes_per_wave == 0)
3120 return 0;
3121
3122 /* Prevent race conditions when updating:
3123 * - si_shader::scratch_bo
3124 * - si_shader::binary::code
3125 * - si_shader::previous_stage::binary::code.
3126 */
3127 si_shader_lock(shader);
3128
3129 /* This shader is already configured to use the current
3130 * scratch buffer. */
3131 if (shader->scratch_bo == sctx->scratch_buffer) {
3132 si_shader_unlock(shader);
3133 return 0;
3134 }
3135
3136 assert(sctx->scratch_buffer);
3137
3138 if (shader->previous_stage)
3139 si_shader_apply_scratch_relocs(shader->previous_stage, scratch_va);
3140
3141 si_shader_apply_scratch_relocs(shader, scratch_va);
3142
3143 /* Replace the shader bo with a new bo that has the relocs applied. */
3144 r = si_shader_binary_upload(sctx->screen, shader);
3145 if (r) {
3146 si_shader_unlock(shader);
3147 return r;
3148 }
3149
3150 /* Update the shader state to use the new shader bo. */
3151 si_shader_init_pm4_state(sctx->screen, shader);
3152
3153 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3154
3155 si_shader_unlock(shader);
3156 return 1;
3157 }
3158
3159 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3160 {
3161 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3162 }
3163
3164 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3165 {
3166 return shader ? shader->config.scratch_bytes_per_wave : 0;
3167 }
3168
3169 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3170 {
3171 if (!sctx->tes_shader.cso)
3172 return NULL; /* tessellation disabled */
3173
3174 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3175 sctx->fixed_func_tcs_shader.current;
3176 }
3177
3178 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3179 {
3180 unsigned bytes = 0;
3181
3182 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3183 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3184 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3185 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3186
3187 if (sctx->tes_shader.cso) {
3188 struct si_shader *tcs = si_get_tcs_current(sctx);
3189
3190 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3191 }
3192 return bytes;
3193 }
3194
3195 static bool si_update_scratch_relocs(struct si_context *sctx)
3196 {
3197 struct si_shader *tcs = si_get_tcs_current(sctx);
3198 int r;
3199
3200 /* Update the shaders, so that they are using the latest scratch.
3201 * The scratch buffer may have been changed since these shaders were
3202 * last used, so we still need to try to update them, even if they
3203 * require scratch buffers smaller than the current size.
3204 */
3205 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3206 if (r < 0)
3207 return false;
3208 if (r == 1)
3209 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3210
3211 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3212 if (r < 0)
3213 return false;
3214 if (r == 1)
3215 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3216
3217 r = si_update_scratch_buffer(sctx, tcs);
3218 if (r < 0)
3219 return false;
3220 if (r == 1)
3221 si_pm4_bind_state(sctx, hs, tcs->pm4);
3222
3223 /* VS can be bound as LS, ES, or VS. */
3224 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3225 if (r < 0)
3226 return false;
3227 if (r == 1) {
3228 if (sctx->tes_shader.current)
3229 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3230 else if (sctx->gs_shader.current)
3231 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3232 else
3233 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3234 }
3235
3236 /* TES can be bound as ES or VS. */
3237 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3238 if (r < 0)
3239 return false;
3240 if (r == 1) {
3241 if (sctx->gs_shader.current)
3242 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3243 else
3244 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3245 }
3246
3247 return true;
3248 }
3249
3250 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3251 {
3252 unsigned current_scratch_buffer_size =
3253 si_get_current_scratch_buffer_size(sctx);
3254 unsigned scratch_bytes_per_wave =
3255 si_get_max_scratch_bytes_per_wave(sctx);
3256 unsigned scratch_needed_size = scratch_bytes_per_wave *
3257 sctx->scratch_waves;
3258 unsigned spi_tmpring_size;
3259
3260 if (scratch_needed_size > 0) {
3261 if (scratch_needed_size > current_scratch_buffer_size) {
3262 /* Create a bigger scratch buffer */
3263 si_resource_reference(&sctx->scratch_buffer, NULL);
3264
3265 sctx->scratch_buffer =
3266 si_aligned_buffer_create(&sctx->screen->b,
3267 SI_RESOURCE_FLAG_UNMAPPABLE,
3268 PIPE_USAGE_DEFAULT,
3269 scratch_needed_size, 256);
3270 if (!sctx->scratch_buffer)
3271 return false;
3272
3273 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3274 si_context_add_resource_size(sctx,
3275 &sctx->scratch_buffer->b.b);
3276 }
3277
3278 if (!si_update_scratch_relocs(sctx))
3279 return false;
3280 }
3281
3282 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3283 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3284 "scratch size should already be aligned correctly.");
3285
3286 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3287 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3288 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3289 sctx->spi_tmpring_size = spi_tmpring_size;
3290 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3291 }
3292 return true;
3293 }
3294
3295 static void si_init_tess_factor_ring(struct si_context *sctx)
3296 {
3297 assert(!sctx->tess_rings);
3298
3299 /* The address must be aligned to 2^19, because the shader only
3300 * receives the high 13 bits.
3301 */
3302 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3303 SI_RESOURCE_FLAG_32BIT,
3304 PIPE_USAGE_DEFAULT,
3305 sctx->screen->tess_offchip_ring_size +
3306 sctx->screen->tess_factor_ring_size,
3307 1 << 19);
3308 if (!sctx->tess_rings)
3309 return;
3310
3311 si_init_config_add_vgt_flush(sctx);
3312
3313 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3314 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3315
3316 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3317 sctx->screen->tess_offchip_ring_size;
3318
3319 /* Append these registers to the init config state. */
3320 if (sctx->chip_class >= GFX7) {
3321 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3322 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3323 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3324 factor_va >> 8);
3325 if (sctx->chip_class >= GFX9)
3326 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3327 S_030944_BASE_HI(factor_va >> 40));
3328 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3329 sctx->screen->vgt_hs_offchip_param);
3330 } else {
3331 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3332 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3333 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3334 factor_va >> 8);
3335 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3336 sctx->screen->vgt_hs_offchip_param);
3337 }
3338
3339 /* Flush the context to re-emit the init_config state.
3340 * This is done only once in a lifetime of a context.
3341 */
3342 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3343 sctx->initial_gfx_cs_size = 0; /* force flush */
3344 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3345 }
3346
3347 static void si_update_vgt_shader_config(struct si_context *sctx)
3348 {
3349 /* Calculate the index of the config.
3350 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3351 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
3352 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
3353
3354 if (!*pm4) {
3355 uint32_t stages = 0;
3356
3357 *pm4 = CALLOC_STRUCT(si_pm4_state);
3358
3359 if (sctx->tes_shader.cso) {
3360 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3361 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3362
3363 if (sctx->gs_shader.cso)
3364 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3365 S_028B54_GS_EN(1) |
3366 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3367 else
3368 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3369 } else if (sctx->gs_shader.cso) {
3370 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3371 S_028B54_GS_EN(1) |
3372 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3373 }
3374
3375 if (sctx->chip_class >= GFX9)
3376 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3377
3378 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3379 }
3380 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3381 }
3382
3383 bool si_update_shaders(struct si_context *sctx)
3384 {
3385 struct pipe_context *ctx = (struct pipe_context*)sctx;
3386 struct si_compiler_ctx_state compiler_state;
3387 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3388 struct si_shader *old_vs = si_get_vs_state(sctx);
3389 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3390 struct si_shader *old_ps = sctx->ps_shader.current;
3391 unsigned old_spi_shader_col_format =
3392 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3393 int r;
3394
3395 compiler_state.compiler = &sctx->compiler;
3396 compiler_state.debug = sctx->debug;
3397 compiler_state.is_debug_context = sctx->is_debug;
3398
3399 /* Update stages before GS. */
3400 if (sctx->tes_shader.cso) {
3401 if (!sctx->tess_rings) {
3402 si_init_tess_factor_ring(sctx);
3403 if (!sctx->tess_rings)
3404 return false;
3405 }
3406
3407 /* VS as LS */
3408 if (sctx->chip_class <= GFX8) {
3409 r = si_shader_select(ctx, &sctx->vs_shader,
3410 &compiler_state);
3411 if (r)
3412 return false;
3413 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3414 }
3415
3416 if (sctx->tcs_shader.cso) {
3417 r = si_shader_select(ctx, &sctx->tcs_shader,
3418 &compiler_state);
3419 if (r)
3420 return false;
3421 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3422 } else {
3423 if (!sctx->fixed_func_tcs_shader.cso) {
3424 sctx->fixed_func_tcs_shader.cso =
3425 si_create_fixed_func_tcs(sctx);
3426 if (!sctx->fixed_func_tcs_shader.cso)
3427 return false;
3428 }
3429
3430 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3431 &compiler_state);
3432 if (r)
3433 return false;
3434 si_pm4_bind_state(sctx, hs,
3435 sctx->fixed_func_tcs_shader.current->pm4);
3436 }
3437
3438 if (sctx->gs_shader.cso) {
3439 /* TES as ES */
3440 if (sctx->chip_class <= GFX8) {
3441 r = si_shader_select(ctx, &sctx->tes_shader,
3442 &compiler_state);
3443 if (r)
3444 return false;
3445 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3446 }
3447 } else {
3448 /* TES as VS */
3449 r = si_shader_select(ctx, &sctx->tes_shader,
3450 &compiler_state);
3451 if (r)
3452 return false;
3453 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3454 }
3455 } else if (sctx->gs_shader.cso) {
3456 if (sctx->chip_class <= GFX8) {
3457 /* VS as ES */
3458 r = si_shader_select(ctx, &sctx->vs_shader,
3459 &compiler_state);
3460 if (r)
3461 return false;
3462 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3463
3464 si_pm4_bind_state(sctx, ls, NULL);
3465 si_pm4_bind_state(sctx, hs, NULL);
3466 }
3467 } else {
3468 /* VS as VS */
3469 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
3470 if (r)
3471 return false;
3472 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3473 si_pm4_bind_state(sctx, ls, NULL);
3474 si_pm4_bind_state(sctx, hs, NULL);
3475 }
3476
3477 /* Update GS. */
3478 if (sctx->gs_shader.cso) {
3479 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
3480 if (r)
3481 return false;
3482 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3483 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3484
3485 if (!si_update_gs_ring_buffers(sctx))
3486 return false;
3487 } else {
3488 si_pm4_bind_state(sctx, gs, NULL);
3489 if (sctx->chip_class <= GFX8)
3490 si_pm4_bind_state(sctx, es, NULL);
3491 }
3492
3493 si_update_vgt_shader_config(sctx);
3494
3495 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3496 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3497
3498 if (sctx->ps_shader.cso) {
3499 unsigned db_shader_control;
3500
3501 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
3502 if (r)
3503 return false;
3504 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3505
3506 db_shader_control =
3507 sctx->ps_shader.cso->db_shader_control |
3508 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3509
3510 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3511 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3512 sctx->flatshade != rs->flatshade) {
3513 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3514 sctx->flatshade = rs->flatshade;
3515 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3516 }
3517
3518 if (sctx->screen->rbplus_allowed &&
3519 si_pm4_state_changed(sctx, ps) &&
3520 (!old_ps ||
3521 old_spi_shader_col_format !=
3522 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3523 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3524
3525 if (sctx->ps_db_shader_control != db_shader_control) {
3526 sctx->ps_db_shader_control = db_shader_control;
3527 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3528 if (sctx->screen->dpbb_allowed)
3529 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3530 }
3531
3532 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3533 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3534 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3535
3536 if (sctx->chip_class == GFX6)
3537 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3538
3539 if (sctx->framebuffer.nr_samples <= 1)
3540 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3541 }
3542 }
3543
3544 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3545 si_pm4_state_enabled_and_changed(sctx, hs) ||
3546 si_pm4_state_enabled_and_changed(sctx, es) ||
3547 si_pm4_state_enabled_and_changed(sctx, gs) ||
3548 si_pm4_state_enabled_and_changed(sctx, vs) ||
3549 si_pm4_state_enabled_and_changed(sctx, ps)) {
3550 if (!si_update_spi_tmpring_size(sctx))
3551 return false;
3552 }
3553
3554 if (sctx->chip_class >= GFX7) {
3555 if (si_pm4_state_enabled_and_changed(sctx, ls))
3556 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3557 else if (!sctx->queued.named.ls)
3558 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3559
3560 if (si_pm4_state_enabled_and_changed(sctx, hs))
3561 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3562 else if (!sctx->queued.named.hs)
3563 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3564
3565 if (si_pm4_state_enabled_and_changed(sctx, es))
3566 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3567 else if (!sctx->queued.named.es)
3568 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3569
3570 if (si_pm4_state_enabled_and_changed(sctx, gs))
3571 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3572 else if (!sctx->queued.named.gs)
3573 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3574
3575 if (si_pm4_state_enabled_and_changed(sctx, vs))
3576 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3577 else if (!sctx->queued.named.vs)
3578 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3579
3580 if (si_pm4_state_enabled_and_changed(sctx, ps))
3581 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3582 else if (!sctx->queued.named.ps)
3583 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3584 }
3585
3586 sctx->do_update_shaders = false;
3587 return true;
3588 }
3589
3590 static void si_emit_scratch_state(struct si_context *sctx)
3591 {
3592 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3593
3594 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3595 sctx->spi_tmpring_size);
3596
3597 if (sctx->scratch_buffer) {
3598 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3599 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3600 RADEON_PRIO_SCRATCH_BUFFER);
3601 }
3602 }
3603
3604 void si_init_shader_functions(struct si_context *sctx)
3605 {
3606 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
3607 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
3608
3609 sctx->b.create_vs_state = si_create_shader_selector;
3610 sctx->b.create_tcs_state = si_create_shader_selector;
3611 sctx->b.create_tes_state = si_create_shader_selector;
3612 sctx->b.create_gs_state = si_create_shader_selector;
3613 sctx->b.create_fs_state = si_create_shader_selector;
3614
3615 sctx->b.bind_vs_state = si_bind_vs_shader;
3616 sctx->b.bind_tcs_state = si_bind_tcs_shader;
3617 sctx->b.bind_tes_state = si_bind_tes_shader;
3618 sctx->b.bind_gs_state = si_bind_gs_shader;
3619 sctx->b.bind_fs_state = si_bind_ps_shader;
3620
3621 sctx->b.delete_vs_state = si_delete_shader_selector;
3622 sctx->b.delete_tcs_state = si_delete_shader_selector;
3623 sctx->b.delete_tes_state = si_delete_shader_selector;
3624 sctx->b.delete_gs_state = si_delete_shader_selector;
3625 sctx->b.delete_fs_state = si_delete_shader_selector;
3626 }