2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_ureg.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
45 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
48 static void *si_get_ir_binary(struct si_shader_selector
*sel
)
55 ir_binary
= sel
->tokens
;
56 ir_size
= tgsi_num_tokens(sel
->tokens
) *
57 sizeof(struct tgsi_token
);
62 nir_serialize(&blob
, sel
->nir
);
63 ir_binary
= blob
.data
;
67 unsigned size
= 4 + ir_size
+ sizeof(sel
->so
);
68 char *result
= (char*)MALLOC(size
);
72 *((uint32_t*)result
) = size
;
73 memcpy(result
+ 4, ir_binary
, ir_size
);
74 memcpy(result
+ 4 + ir_size
, &sel
->so
, sizeof(sel
->so
));
82 /** Copy "data" to "ptr" and return the next dword following copied data. */
83 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
85 /* data may be NULL if size == 0 */
87 memcpy(ptr
, data
, size
);
88 ptr
+= DIV_ROUND_UP(size
, 4);
92 /** Read data from "ptr". Return the next dword following the data. */
93 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
95 memcpy(data
, ptr
, size
);
96 ptr
+= DIV_ROUND_UP(size
, 4);
101 * Write the size as uint followed by the data. Return the next dword
102 * following the copied data.
104 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
107 return write_data(ptr
, data
, size
);
111 * Read the size as uint followed by the data. Return both via parameters.
112 * Return the next dword following the data.
114 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
117 assert(*data
== NULL
);
120 *data
= malloc(*size
);
121 return read_data(ptr
, *data
, *size
);
125 * Return the shader binary in a buffer. The first 4 bytes contain its size
128 static void *si_get_shader_binary(struct si_shader
*shader
)
130 /* There is always a size of data followed by the data itself. */
131 unsigned relocs_size
= shader
->binary
.reloc_count
*
132 sizeof(shader
->binary
.relocs
[0]);
133 unsigned disasm_size
= shader
->binary
.disasm_string
?
134 strlen(shader
->binary
.disasm_string
) + 1 : 0;
135 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
136 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
139 4 + /* CRC32 of the data below */
140 align(sizeof(shader
->config
), 4) +
141 align(sizeof(shader
->info
), 4) +
142 4 + align(shader
->binary
.code_size
, 4) +
143 4 + align(shader
->binary
.rodata_size
, 4) +
144 4 + align(relocs_size
, 4) +
145 4 + align(disasm_size
, 4) +
146 4 + align(llvm_ir_size
, 4);
147 void *buffer
= CALLOC(1, size
);
148 uint32_t *ptr
= (uint32_t*)buffer
;
154 ptr
++; /* CRC32 is calculated at the end. */
156 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
157 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
158 ptr
= write_chunk(ptr
, shader
->binary
.code
, shader
->binary
.code_size
);
159 ptr
= write_chunk(ptr
, shader
->binary
.rodata
, shader
->binary
.rodata_size
);
160 ptr
= write_chunk(ptr
, shader
->binary
.relocs
, relocs_size
);
161 ptr
= write_chunk(ptr
, shader
->binary
.disasm_string
, disasm_size
);
162 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
163 assert((char *)ptr
- (char *)buffer
== size
);
166 ptr
= (uint32_t*)buffer
;
168 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
173 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
175 uint32_t *ptr
= (uint32_t*)binary
;
176 uint32_t size
= *ptr
++;
177 uint32_t crc32
= *ptr
++;
180 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
181 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
185 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
186 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
187 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.code
,
188 &shader
->binary
.code_size
);
189 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.rodata
,
190 &shader
->binary
.rodata_size
);
191 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.relocs
, &chunk_size
);
192 shader
->binary
.reloc_count
= chunk_size
/ sizeof(shader
->binary
.relocs
[0]);
193 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.disasm_string
, &chunk_size
);
194 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
200 * Insert a shader into the cache. It's assumed the shader is not in the cache.
201 * Use si_shader_cache_load_shader before calling this.
203 * Returns false on failure, in which case the ir_binary should be freed.
205 static bool si_shader_cache_insert_shader(struct si_screen
*sscreen
,
207 struct si_shader
*shader
,
208 bool insert_into_disk_cache
)
211 struct hash_entry
*entry
;
212 uint8_t key
[CACHE_KEY_SIZE
];
214 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
216 return false; /* already added */
218 hw_binary
= si_get_shader_binary(shader
);
222 if (_mesa_hash_table_insert(sscreen
->shader_cache
, ir_binary
,
223 hw_binary
) == NULL
) {
228 if (sscreen
->disk_shader_cache
&& insert_into_disk_cache
) {
229 disk_cache_compute_key(sscreen
->disk_shader_cache
, ir_binary
,
230 *((uint32_t *)ir_binary
), key
);
231 disk_cache_put(sscreen
->disk_shader_cache
, key
, hw_binary
,
232 *((uint32_t *) hw_binary
), NULL
);
238 static bool si_shader_cache_load_shader(struct si_screen
*sscreen
,
240 struct si_shader
*shader
)
242 struct hash_entry
*entry
=
243 _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
245 if (sscreen
->disk_shader_cache
) {
246 unsigned char sha1
[CACHE_KEY_SIZE
];
247 size_t tg_size
= *((uint32_t *) ir_binary
);
249 disk_cache_compute_key(sscreen
->disk_shader_cache
,
250 ir_binary
, tg_size
, sha1
);
254 disk_cache_get(sscreen
->disk_shader_cache
,
259 if (binary_size
< sizeof(uint32_t) ||
260 *((uint32_t*)buffer
) != binary_size
) {
261 /* Something has gone wrong discard the item
262 * from the cache and rebuild/link from
265 assert(!"Invalid radeonsi shader disk cache "
268 disk_cache_remove(sscreen
->disk_shader_cache
,
275 if (!si_load_shader_binary(shader
, buffer
)) {
281 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
,
288 if (si_load_shader_binary(shader
, entry
->data
))
293 p_atomic_inc(&sscreen
->num_shader_cache_hits
);
297 static uint32_t si_shader_cache_key_hash(const void *key
)
299 /* The first dword is the key size. */
300 return util_hash_crc32(key
, *(uint32_t*)key
);
303 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
305 uint32_t *keya
= (uint32_t*)a
;
306 uint32_t *keyb
= (uint32_t*)b
;
308 /* The first dword is the key size. */
312 return memcmp(keya
, keyb
, *keya
) == 0;
315 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
317 FREE((void*)entry
->key
);
321 bool si_init_shader_cache(struct si_screen
*sscreen
)
323 (void) mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
324 sscreen
->shader_cache
=
325 _mesa_hash_table_create(NULL
,
326 si_shader_cache_key_hash
,
327 si_shader_cache_key_equals
);
329 return sscreen
->shader_cache
!= NULL
;
332 void si_destroy_shader_cache(struct si_screen
*sscreen
)
334 if (sscreen
->shader_cache
)
335 _mesa_hash_table_destroy(sscreen
->shader_cache
,
336 si_destroy_shader_cache_entry
);
337 mtx_destroy(&sscreen
->shader_cache_mutex
);
342 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
343 struct si_shader_selector
*tes
,
344 struct si_pm4_state
*pm4
)
346 struct tgsi_shader_info
*info
= &tes
->info
;
347 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
348 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
349 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
350 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
351 unsigned type
, partitioning
, topology
, distribution_mode
;
353 switch (tes_prim_mode
) {
354 case PIPE_PRIM_LINES
:
355 type
= V_028B6C_TESS_ISOLINE
;
357 case PIPE_PRIM_TRIANGLES
:
358 type
= V_028B6C_TESS_TRIANGLE
;
360 case PIPE_PRIM_QUADS
:
361 type
= V_028B6C_TESS_QUAD
;
368 switch (tes_spacing
) {
369 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
370 partitioning
= V_028B6C_PART_FRAC_ODD
;
372 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
373 partitioning
= V_028B6C_PART_FRAC_EVEN
;
375 case PIPE_TESS_SPACING_EQUAL
:
376 partitioning
= V_028B6C_PART_INTEGER
;
384 topology
= V_028B6C_OUTPUT_POINT
;
385 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
386 topology
= V_028B6C_OUTPUT_LINE
;
387 else if (tes_vertex_order_cw
)
388 /* for some reason, this must be the other way around */
389 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
391 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
393 if (sscreen
->has_distributed_tess
) {
394 if (sscreen
->info
.family
== CHIP_FIJI
||
395 sscreen
->info
.family
>= CHIP_POLARIS10
)
396 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
398 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
400 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
402 si_pm4_set_reg(pm4
, R_028B6C_VGT_TF_PARAM
,
403 S_028B6C_TYPE(type
) |
404 S_028B6C_PARTITIONING(partitioning
) |
405 S_028B6C_TOPOLOGY(topology
) |
406 S_028B6C_DISTRIBUTION_MODE(distribution_mode
));
409 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
410 * whether the "fractional odd" tessellation spacing is used.
412 * Possible VGT configurations and which state should set the register:
414 * Reg set in | VGT shader configuration | Value
415 * ------------------------------------------------------
417 * VS as ES | ES -> GS -> VS | 30
418 * TES as VS | LS -> HS -> VS | 14 or 30
419 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
421 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
423 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
424 struct si_shader_selector
*sel
,
425 struct si_shader
*shader
,
426 struct si_pm4_state
*pm4
)
428 unsigned type
= sel
->type
;
430 if (sscreen
->info
.family
< CHIP_POLARIS10
)
433 /* VS as VS, or VS as ES: */
434 if ((type
== PIPE_SHADER_VERTEX
&&
436 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
437 /* TES as VS, or TES as ES: */
438 type
== PIPE_SHADER_TESS_EVAL
) {
439 unsigned vtx_reuse_depth
= 30;
441 if (type
== PIPE_SHADER_TESS_EVAL
&&
442 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
443 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
444 vtx_reuse_depth
= 14;
446 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
451 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
454 si_pm4_clear_state(shader
->pm4
);
456 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
461 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs
)
463 /* Add the pointer to VBO descriptors. */
464 if (HAVE_32BIT_POINTERS
) {
465 return num_always_on_user_sgprs
+ 1;
467 assert(num_always_on_user_sgprs
% 2 == 0);
468 return num_always_on_user_sgprs
+ 2;
472 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
474 struct si_pm4_state
*pm4
;
475 unsigned vgpr_comp_cnt
;
478 assert(sscreen
->info
.chip_class
<= VI
);
480 pm4
= si_get_shader_pm4_state(shader
);
484 va
= shader
->bo
->gpu_address
;
485 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
487 /* We need at least 2 components for LS.
488 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
489 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
491 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
493 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
494 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
496 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
497 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
498 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
499 S_00B528_DX10_CLAMP(1) |
500 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
501 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
)) |
502 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
505 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
507 struct si_pm4_state
*pm4
;
509 unsigned ls_vgpr_comp_cnt
= 0;
511 pm4
= si_get_shader_pm4_state(shader
);
515 va
= shader
->bo
->gpu_address
;
516 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
518 if (sscreen
->info
.chip_class
>= GFX9
) {
519 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
520 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, S_00B414_MEM_BASE(va
>> 40));
522 /* We need at least 2 components for LS.
523 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
524 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
526 ls_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
528 unsigned num_user_sgprs
=
529 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR
);
531 shader
->config
.rsrc2
=
532 S_00B42C_USER_SGPR(num_user_sgprs
) |
533 S_00B42C_USER_SGPR_MSB(num_user_sgprs
>> 5) |
534 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
536 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
537 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, S_00B424_MEM_BASE(va
>> 40));
539 shader
->config
.rsrc2
=
540 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
541 S_00B42C_OC_LDS_EN(1) |
542 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
545 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
546 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
547 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
548 S_00B428_DX10_CLAMP(1) |
549 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
550 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt
));
552 if (sscreen
->info
.chip_class
<= VI
) {
553 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
554 shader
->config
.rsrc2
);
558 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
560 struct si_pm4_state
*pm4
;
561 unsigned num_user_sgprs
;
562 unsigned vgpr_comp_cnt
;
566 assert(sscreen
->info
.chip_class
<= VI
);
568 pm4
= si_get_shader_pm4_state(shader
);
572 va
= shader
->bo
->gpu_address
;
573 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
575 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
576 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
577 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
578 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
579 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
580 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
581 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
583 unreachable("invalid shader selector type");
585 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
587 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
588 shader
->selector
->esgs_itemsize
/ 4);
589 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
590 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
591 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
592 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
593 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
594 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
595 S_00B328_DX10_CLAMP(1) |
596 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
597 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
598 S_00B32C_USER_SGPR(num_user_sgprs
) |
599 S_00B32C_OC_LDS_EN(oc_lds_en
) |
600 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
602 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
603 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
605 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
608 struct gfx9_gs_info
{
609 unsigned es_verts_per_subgroup
;
610 unsigned gs_prims_per_subgroup
;
611 unsigned gs_inst_prims_in_subgroup
;
612 unsigned max_prims_per_subgroup
;
616 static void gfx9_get_gs_info(struct si_shader_selector
*es
,
617 struct si_shader_selector
*gs
,
618 struct gfx9_gs_info
*out
)
620 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
621 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
622 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
623 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
625 /* All these are in dwords: */
626 /* We can't allow using the whole LDS, because GS waves compete with
627 * other shader stages for LDS space. */
628 const unsigned max_lds_size
= 8 * 1024;
629 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
630 unsigned esgs_lds_size
;
632 /* All these are per subgroup: */
633 const unsigned max_out_prims
= 32 * 1024;
634 const unsigned max_es_verts
= 255;
635 const unsigned ideal_gs_prims
= 64;
636 unsigned max_gs_prims
, gs_prims
;
637 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
639 assert(gs_num_invocations
<= 32); /* GL maximum */
641 if (uses_adjacency
|| gs_num_invocations
> 1)
642 max_gs_prims
= 127 / gs_num_invocations
;
646 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
647 * Make sure we don't go over the maximum value.
649 if (gs
->gs_max_out_vertices
> 0) {
650 max_gs_prims
= MIN2(max_gs_prims
,
652 (gs
->gs_max_out_vertices
* gs_num_invocations
));
654 assert(max_gs_prims
> 0);
656 /* If the primitive has adjacency, halve the number of vertices
657 * that will be reused in multiple primitives.
659 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
661 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
662 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
664 /* Compute ESGS LDS size based on the worst case number of ES vertices
665 * needed to create the target number of GS prims per subgroup.
667 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
669 /* If total LDS usage is too big, refactor partitions based on ratio
670 * of ESGS item sizes.
672 if (esgs_lds_size
> max_lds_size
) {
673 /* Our target GS Prims Per Subgroup was too large. Calculate
674 * the maximum number of GS Prims Per Subgroup that will fit
675 * into LDS, capped by the maximum that the hardware can support.
677 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
679 assert(gs_prims
> 0);
680 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
683 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
684 assert(esgs_lds_size
<= max_lds_size
);
687 /* Now calculate remaining ESGS information. */
689 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
691 es_verts
= max_es_verts
;
693 /* Vertices for adjacency primitives are not always reused, so restore
694 * it for ES_VERTS_PER_SUBGRP.
696 min_es_verts
= gs
->gs_input_verts_per_prim
;
698 /* For normal primitives, the VGT only checks if they are past the ES
699 * verts per subgroup after allocating a full GS primitive and if they
700 * are, kick off a new subgroup. But if those additional ES verts are
701 * unique (e.g. not reused) we need to make sure there is enough LDS
702 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
704 es_verts
-= min_es_verts
- 1;
706 out
->es_verts_per_subgroup
= es_verts
;
707 out
->gs_prims_per_subgroup
= gs_prims
;
708 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
709 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
710 gs
->gs_max_out_vertices
;
711 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
713 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
716 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
718 struct si_shader_selector
*sel
= shader
->selector
;
719 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
720 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
721 struct si_pm4_state
*pm4
;
723 unsigned max_stream
= sel
->max_gs_stream
;
726 pm4
= si_get_shader_pm4_state(shader
);
730 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
731 si_pm4_set_reg(pm4
, R_028A60_VGT_GSVS_RING_OFFSET_1
, offset
);
733 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
734 si_pm4_set_reg(pm4
, R_028A64_VGT_GSVS_RING_OFFSET_2
, offset
);
736 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
737 si_pm4_set_reg(pm4
, R_028A68_VGT_GSVS_RING_OFFSET_3
, offset
);
739 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
740 si_pm4_set_reg(pm4
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
742 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
743 assert(offset
< (1 << 15));
745 si_pm4_set_reg(pm4
, R_028B38_VGT_GS_MAX_VERT_OUT
, sel
->gs_max_out_vertices
);
747 si_pm4_set_reg(pm4
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, num_components
[0]);
748 si_pm4_set_reg(pm4
, R_028B60_VGT_GS_VERT_ITEMSIZE_1
, (max_stream
>= 1) ? num_components
[1] : 0);
749 si_pm4_set_reg(pm4
, R_028B64_VGT_GS_VERT_ITEMSIZE_2
, (max_stream
>= 2) ? num_components
[2] : 0);
750 si_pm4_set_reg(pm4
, R_028B68_VGT_GS_VERT_ITEMSIZE_3
, (max_stream
>= 3) ? num_components
[3] : 0);
752 si_pm4_set_reg(pm4
, R_028B90_VGT_GS_INSTANCE_CNT
,
753 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
754 S_028B90_ENABLE(gs_num_invocations
> 0));
756 va
= shader
->bo
->gpu_address
;
757 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
759 if (sscreen
->info
.chip_class
>= GFX9
) {
760 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
761 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
762 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
763 struct gfx9_gs_info gs_info
;
765 if (es_type
== PIPE_SHADER_VERTEX
)
766 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
767 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
768 else if (es_type
== PIPE_SHADER_TESS_EVAL
)
769 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
771 unreachable("invalid shader selector type");
773 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
774 * VGPR[0:4] are always loaded.
776 if (sel
->info
.uses_invocationid
)
777 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
778 else if (sel
->info
.uses_primid
)
779 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
780 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
781 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
783 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
785 unsigned num_user_sgprs
;
786 if (es_type
== PIPE_SHADER_VERTEX
)
787 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
789 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
791 gfx9_get_gs_info(shader
->key
.part
.gs
.es
, sel
, &gs_info
);
793 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
794 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, S_00B214_MEM_BASE(va
>> 40));
796 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
797 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
798 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
799 S_00B228_DX10_CLAMP(1) |
800 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
801 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
802 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
803 S_00B22C_USER_SGPR(num_user_sgprs
) |
804 S_00B22C_USER_SGPR_MSB(num_user_sgprs
>> 5) |
805 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
806 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
807 S_00B22C_LDS_SIZE(gs_info
.lds_size
) |
808 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
810 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
811 S_028A44_ES_VERTS_PER_SUBGRP(gs_info
.es_verts_per_subgroup
) |
812 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info
.gs_prims_per_subgroup
) |
813 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info
.gs_inst_prims_in_subgroup
));
814 si_pm4_set_reg(pm4
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
815 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info
.max_prims_per_subgroup
));
816 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
817 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4);
819 if (es_type
== PIPE_SHADER_TESS_EVAL
)
820 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
822 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
825 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
826 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, S_00B224_MEM_BASE(va
>> 40));
828 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
829 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
830 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
831 S_00B228_DX10_CLAMP(1) |
832 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
833 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
834 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
835 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
840 * Compute the state for \p shader, which will run as a vertex shader on the
843 * If \p gs is non-NULL, it points to the geometry shader for which this shader
844 * is the copy shader.
846 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
847 struct si_shader_selector
*gs
)
849 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
850 struct si_pm4_state
*pm4
;
851 unsigned num_user_sgprs
;
852 unsigned nparams
, vgpr_comp_cnt
;
855 unsigned window_space
=
856 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
857 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
859 pm4
= si_get_shader_pm4_state(shader
);
863 /* We always write VGT_GS_MODE in the VS state, because every switch
864 * between different shader pipelines involving a different GS or no
865 * GS at all involves a switch of the VS (different GS use different
866 * copy shaders). On the other hand, when the API switches from a GS to
867 * no GS and then back to the same GS used originally, the GS state is
871 unsigned mode
= V_028A40_GS_OFF
;
873 /* PrimID needs GS scenario A. */
875 mode
= V_028A40_GS_SCENARIO_A
;
877 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, S_028A40_MODE(mode
));
878 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, enable_prim_id
);
880 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
,
881 ac_vgt_gs_mode(gs
->gs_max_out_vertices
,
882 sscreen
->info
.chip_class
));
883 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
886 if (sscreen
->info
.chip_class
<= VI
) {
887 /* Reuse needs to be set off if we write oViewport. */
888 si_pm4_set_reg(pm4
, R_028AB4_VGT_REUSE_OFF
,
889 S_028AB4_REUSE_OFF(info
->writes_viewport_index
));
892 va
= shader
->bo
->gpu_address
;
893 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
896 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
897 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
898 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
899 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
900 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
901 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
903 vgpr_comp_cnt
= enable_prim_id
? 2 : (shader
->info
.uses_instanceid
? 1 : 0);
905 if (info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
]) {
906 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
907 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
909 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
911 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
912 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
913 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
915 unreachable("invalid shader selector type");
917 /* VS is required to export at least one param. */
918 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
919 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
920 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
922 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
923 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
924 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
925 V_02870C_SPI_SHADER_4COMP
:
926 V_02870C_SPI_SHADER_NONE
) |
927 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
928 V_02870C_SPI_SHADER_4COMP
:
929 V_02870C_SPI_SHADER_NONE
) |
930 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
931 V_02870C_SPI_SHADER_4COMP
:
932 V_02870C_SPI_SHADER_NONE
));
934 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
936 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
937 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, S_00B124_MEM_BASE(va
>> 40));
938 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
939 S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
940 S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
941 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
942 S_00B128_DX10_CLAMP(1) |
943 S_00B128_FLOAT_MODE(shader
->config
.float_mode
));
944 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
945 S_00B12C_USER_SGPR(num_user_sgprs
) |
946 S_00B12C_OC_LDS_EN(oc_lds_en
) |
947 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
948 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
949 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
950 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
951 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
) |
952 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
954 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
955 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
957 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
958 S_028818_VTX_W0_FMT(1) |
959 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
960 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
961 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
963 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
964 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
966 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
969 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
971 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
972 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
973 !!(info
->colors_read
& 0xf0);
974 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
975 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
977 assert(num_interp
<= 32);
978 return MIN2(num_interp
, 32);
981 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
983 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
984 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
986 /* If the i-th target format is set, all previous target formats must
987 * be non-zero to avoid hangs.
989 for (i
= 0; i
< num_targets
; i
++)
990 if (!(value
& (0xf << (i
* 4))))
991 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
996 static void si_shader_ps(struct si_shader
*shader
)
998 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
999 struct si_pm4_state
*pm4
;
1000 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1001 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1003 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1005 /* we need to enable at least one of them, otherwise we hang the GPU */
1006 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1007 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1008 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1009 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1010 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1011 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1012 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1013 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1014 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1015 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
1016 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1017 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1018 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1019 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1021 /* Validate interpolation optimization flags (read as implications). */
1022 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1023 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1024 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1025 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1026 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1027 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1028 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1029 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1030 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1031 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1032 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1033 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1034 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1035 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1036 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1037 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1038 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1039 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1041 /* Validate cases when the optimizations are off (read as implications). */
1042 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1043 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1044 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1045 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1046 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1047 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1049 pm4
= si_get_shader_pm4_state(shader
);
1053 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1055 * 0 -> Position = pixel center
1056 * 1 -> Position = pixel centroid
1057 * 2 -> Position = at sample position
1059 * From GLSL 4.5 specification, section 7.1:
1060 * "The variable gl_FragCoord is available as an input variable from
1061 * within fragment shaders and it holds the window relative coordinates
1062 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1063 * value can be for any location within the pixel, or one of the
1064 * fragment samples. The use of centroid does not further restrict
1065 * this value to be inside the current primitive."
1067 * Meaning that centroid has no effect and we can return anything within
1068 * the pixel. Thus, return the value at sample position, because that's
1069 * the most accurate one shaders can get.
1071 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1073 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1074 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1075 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1077 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1078 cb_shader_mask
= ac_get_cb_shader_mask(spi_shader_col_format
);
1080 /* Ensure that some export memory is always allocated, for two reasons:
1082 * 1) Correctness: The hardware ignores the EXEC mask if no export
1083 * memory is allocated, so KILL and alpha test do not work correctly
1085 * 2) Performance: Every shader needs at least a NULL export, even when
1086 * it writes no color/depth output. The NULL export instruction
1087 * stalls without this setting.
1089 * Don't add this to CB_SHADER_MASK.
1091 if (!spi_shader_col_format
&&
1092 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1093 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1095 si_pm4_set_reg(pm4
, R_0286CC_SPI_PS_INPUT_ENA
, input_ena
);
1096 si_pm4_set_reg(pm4
, R_0286D0_SPI_PS_INPUT_ADDR
,
1097 shader
->config
.spi_ps_input_addr
);
1099 /* Set interpolation controls. */
1100 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
));
1102 /* Set registers. */
1103 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
1104 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
1106 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
,
1107 ac_get_spi_shader_z_format(info
->writes_z
,
1108 info
->writes_stencil
,
1109 info
->writes_samplemask
));
1111 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
, spi_shader_col_format
);
1112 si_pm4_set_reg(pm4
, R_02823C_CB_SHADER_MASK
, cb_shader_mask
);
1114 va
= shader
->bo
->gpu_address
;
1115 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1116 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1117 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, S_00B024_MEM_BASE(va
>> 40));
1119 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
1120 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1121 S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
1122 S_00B028_DX10_CLAMP(1) |
1123 S_00B028_FLOAT_MODE(shader
->config
.float_mode
));
1124 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1125 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1126 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1127 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1130 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1131 struct si_shader
*shader
)
1133 switch (shader
->selector
->type
) {
1134 case PIPE_SHADER_VERTEX
:
1135 if (shader
->key
.as_ls
)
1136 si_shader_ls(sscreen
, shader
);
1137 else if (shader
->key
.as_es
)
1138 si_shader_es(sscreen
, shader
);
1140 si_shader_vs(sscreen
, shader
, NULL
);
1142 case PIPE_SHADER_TESS_CTRL
:
1143 si_shader_hs(sscreen
, shader
);
1145 case PIPE_SHADER_TESS_EVAL
:
1146 if (shader
->key
.as_es
)
1147 si_shader_es(sscreen
, shader
);
1149 si_shader_vs(sscreen
, shader
, NULL
);
1151 case PIPE_SHADER_GEOMETRY
:
1152 si_shader_gs(sscreen
, shader
);
1154 case PIPE_SHADER_FRAGMENT
:
1155 si_shader_ps(shader
);
1162 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1164 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1165 if (sctx
->queued
.named
.dsa
)
1166 return sctx
->queued
.named
.dsa
->alpha_func
;
1168 return PIPE_FUNC_ALWAYS
;
1171 static void si_shader_selector_key_vs(struct si_context
*sctx
,
1172 struct si_shader_selector
*vs
,
1173 struct si_shader_key
*key
,
1174 struct si_vs_prolog_bits
*prolog_key
)
1176 if (!sctx
->vertex_elements
)
1179 prolog_key
->instance_divisor_is_one
=
1180 sctx
->vertex_elements
->instance_divisor_is_one
;
1181 prolog_key
->instance_divisor_is_fetched
=
1182 sctx
->vertex_elements
->instance_divisor_is_fetched
;
1184 /* Prefer a monolithic shader to allow scheduling divisions around
1186 if (prolog_key
->instance_divisor_is_fetched
)
1187 key
->opt
.prefer_mono
= 1;
1189 unsigned count
= MIN2(vs
->info
.num_inputs
,
1190 sctx
->vertex_elements
->count
);
1191 memcpy(key
->mono
.vs_fix_fetch
, sctx
->vertex_elements
->fix_fetch
, count
);
1194 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1195 struct si_shader_selector
*vs
,
1196 struct si_shader_key
*key
)
1198 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1200 key
->opt
.clip_disable
=
1201 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1202 (vs
->info
.clipdist_writemask
||
1203 vs
->info
.writes_clipvertex
) &&
1204 !vs
->info
.culldist_writemask
;
1206 /* Find out if PS is disabled. */
1207 bool ps_disabled
= true;
1209 const struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1210 bool alpha_to_coverage
= blend
&& blend
->alpha_to_coverage
;
1211 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1212 ps
->info
.writes_z
||
1213 ps
->info
.writes_stencil
||
1214 ps
->info
.writes_samplemask
||
1215 alpha_to_coverage
||
1216 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1217 unsigned ps_colormask
= si_get_total_colormask(sctx
);
1219 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1222 !ps
->info
.writes_memory
);
1225 /* Find out which VS outputs aren't used by the PS. */
1226 uint64_t outputs_written
= vs
->outputs_written_before_ps
;
1227 uint64_t inputs_read
= 0;
1229 /* Ignore outputs that are not passed from VS to PS. */
1230 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION
, 0, true)) |
1231 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE
, 0, true)) |
1232 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX
, 0, true)));
1235 inputs_read
= ps
->inputs_read
;
1238 uint64_t linked
= outputs_written
& inputs_read
;
1240 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1243 /* Compute the key for the hw shader variant */
1244 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1245 struct si_shader_selector
*sel
,
1246 struct si_shader_key
*key
)
1248 struct si_context
*sctx
= (struct si_context
*)ctx
;
1250 memset(key
, 0, sizeof(*key
));
1252 switch (sel
->type
) {
1253 case PIPE_SHADER_VERTEX
:
1254 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1256 if (sctx
->tes_shader
.cso
)
1258 else if (sctx
->gs_shader
.cso
)
1261 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1263 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1264 key
->mono
.u
.vs_export_prim_id
= 1;
1267 case PIPE_SHADER_TESS_CTRL
:
1268 if (sctx
->chip_class
>= GFX9
) {
1269 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1270 key
, &key
->part
.tcs
.ls_prolog
);
1271 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1273 /* When the LS VGPR fix is needed, monolithic shaders
1275 * - avoid initializing EXEC in both the LS prolog
1276 * and the LS main part when !vs_needs_prolog
1277 * - remove the fixup for unused input VGPRs
1279 key
->part
.tcs
.ls_prolog
.ls_vgpr_fix
= sctx
->ls_vgpr_fix
;
1281 /* The LS output / HS input layout can be communicated
1282 * directly instead of via user SGPRs for merged LS-HS.
1283 * The LS VGPR fix prefers this too.
1285 key
->opt
.prefer_mono
= 1;
1288 key
->part
.tcs
.epilog
.prim_mode
=
1289 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1290 key
->part
.tcs
.epilog
.invoc0_tess_factors_are_def
=
1291 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1292 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1293 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1295 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1296 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1298 case PIPE_SHADER_TESS_EVAL
:
1299 if (sctx
->gs_shader
.cso
)
1302 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1304 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1305 key
->mono
.u
.vs_export_prim_id
= 1;
1308 case PIPE_SHADER_GEOMETRY
:
1309 if (sctx
->chip_class
>= GFX9
) {
1310 if (sctx
->tes_shader
.cso
) {
1311 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1313 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1314 key
, &key
->part
.gs
.vs_prolog
);
1315 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1316 key
->part
.gs
.prolog
.gfx9_prev_is_vs
= 1;
1319 /* Merged ES-GS can have unbalanced wave usage.
1321 * ES threads are per-vertex, while GS threads are
1322 * per-primitive. So without any amplification, there
1323 * are fewer GS threads than ES threads, which can result
1324 * in empty (no-op) GS waves. With too much amplification,
1325 * there are more GS threads than ES threads, which
1326 * can result in empty (no-op) ES waves.
1328 * Non-monolithic shaders are implemented by setting EXEC
1329 * at the beginning of shader parts, and don't jump to
1330 * the end if EXEC is 0.
1332 * Monolithic shaders use conditional blocks, so they can
1333 * jump and skip empty waves of ES or GS. So set this to
1334 * always use optimized variants, which are monolithic.
1336 key
->opt
.prefer_mono
= 1;
1338 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1340 case PIPE_SHADER_FRAGMENT
: {
1341 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1342 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1344 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1345 sel
->info
.colors_written
== 0x1)
1346 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1349 /* Select the shader color format based on whether
1350 * blending or alpha are needed.
1352 key
->part
.ps
.epilog
.spi_shader_col_format
=
1353 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1354 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1355 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1356 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1357 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1358 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1359 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1360 sctx
->framebuffer
.spi_shader_col_format
);
1361 key
->part
.ps
.epilog
.spi_shader_col_format
&= blend
->cb_target_enabled_4bit
;
1363 /* The output for dual source blending should have
1364 * the same format as the first output.
1366 if (blend
->dual_src_blend
)
1367 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1368 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1370 key
->part
.ps
.epilog
.spi_shader_col_format
= sctx
->framebuffer
.spi_shader_col_format
;
1372 /* If alpha-to-coverage is enabled, we have to export alpha
1373 * even if there is no color buffer.
1375 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1376 blend
&& blend
->alpha_to_coverage
)
1377 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1379 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1380 * to the range supported by the type if a channel has less
1381 * than 16 bits and the export format is 16_ABGR.
1383 if (sctx
->chip_class
<= CIK
&& sctx
->family
!= CHIP_HAWAII
) {
1384 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1385 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1388 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1389 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1390 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1391 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1392 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1396 bool is_poly
= (sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES
&&
1397 sctx
->current_rast_prim
<= PIPE_PRIM_POLYGON
) ||
1398 sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES_ADJACENCY
;
1399 bool is_line
= !is_poly
&& sctx
->current_rast_prim
!= PIPE_PRIM_POINTS
;
1401 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1402 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1404 if (sctx
->queued
.named
.blend
) {
1405 key
->part
.ps
.epilog
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
1406 rs
->multisample_enable
;
1409 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1410 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1411 (is_line
&& rs
->line_smooth
)) &&
1412 sctx
->framebuffer
.nr_samples
<= 1;
1413 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1415 if (sctx
->ps_iter_samples
> 1 &&
1416 sel
->info
.reads_samplemask
) {
1417 key
->part
.ps
.prolog
.samplemask_log_ps_iter
=
1418 util_logbase2(sctx
->ps_iter_samples
);
1421 if (rs
->force_persample_interp
&&
1422 rs
->multisample_enable
&&
1423 sctx
->framebuffer
.nr_samples
> 1 &&
1424 sctx
->ps_iter_samples
> 1) {
1425 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1426 sel
->info
.uses_persp_center
||
1427 sel
->info
.uses_persp_centroid
;
1429 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1430 sel
->info
.uses_linear_center
||
1431 sel
->info
.uses_linear_centroid
;
1432 } else if (rs
->multisample_enable
&&
1433 sctx
->framebuffer
.nr_samples
> 1) {
1434 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
1435 sel
->info
.uses_persp_center
&&
1436 sel
->info
.uses_persp_centroid
;
1437 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
1438 sel
->info
.uses_linear_center
&&
1439 sel
->info
.uses_linear_centroid
;
1441 /* Make sure SPI doesn't compute more than 1 pair
1442 * of (i,j), which is the optimization here. */
1443 key
->part
.ps
.prolog
.force_persp_center_interp
=
1444 sel
->info
.uses_persp_center
+
1445 sel
->info
.uses_persp_centroid
+
1446 sel
->info
.uses_persp_sample
> 1;
1448 key
->part
.ps
.prolog
.force_linear_center_interp
=
1449 sel
->info
.uses_linear_center
+
1450 sel
->info
.uses_linear_centroid
+
1451 sel
->info
.uses_linear_sample
> 1;
1453 if (sel
->info
.opcode_count
[TGSI_OPCODE_INTERP_SAMPLE
])
1454 key
->mono
.u
.ps
.interpolate_at_sample_force_center
= 1;
1458 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
1460 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1461 if (sctx
->ps_uses_fbfetch
) {
1462 struct pipe_surface
*cb0
= sctx
->framebuffer
.state
.cbufs
[0];
1463 struct pipe_resource
*tex
= cb0
->texture
;
1465 /* 1D textures are allocated and used as 2D on GFX9. */
1466 key
->mono
.u
.ps
.fbfetch_msaa
= sctx
->framebuffer
.nr_samples
> 1;
1467 key
->mono
.u
.ps
.fbfetch_is_1D
= sctx
->chip_class
!= GFX9
&&
1468 (tex
->target
== PIPE_TEXTURE_1D
||
1469 tex
->target
== PIPE_TEXTURE_1D_ARRAY
);
1470 key
->mono
.u
.ps
.fbfetch_layered
= tex
->target
== PIPE_TEXTURE_1D_ARRAY
||
1471 tex
->target
== PIPE_TEXTURE_2D_ARRAY
||
1472 tex
->target
== PIPE_TEXTURE_CUBE
||
1473 tex
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
1474 tex
->target
== PIPE_TEXTURE_3D
;
1482 if (unlikely(sctx
->screen
->debug_flags
& DBG(NO_OPT_VARIANT
)))
1483 memset(&key
->opt
, 0, sizeof(key
->opt
));
1486 static void si_build_shader_variant(struct si_shader
*shader
,
1490 struct si_shader_selector
*sel
= shader
->selector
;
1491 struct si_screen
*sscreen
= sel
->screen
;
1492 struct si_compiler
*compiler
;
1493 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
1496 if (thread_index
>= 0) {
1498 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler_lowp
));
1499 compiler
= &sscreen
->compiler_lowp
[thread_index
];
1501 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
1502 compiler
= &sscreen
->compiler
[thread_index
];
1507 assert(!low_priority
);
1508 compiler
= shader
->compiler_ctx_state
.compiler
;
1511 r
= si_shader_create(sscreen
, compiler
, shader
, debug
);
1513 PRINT_ERR("Failed to build shader variant (type=%u) %d\n",
1515 shader
->compilation_failed
= true;
1519 if (shader
->compiler_ctx_state
.is_debug_context
) {
1520 FILE *f
= open_memstream(&shader
->shader_log
,
1521 &shader
->shader_log_size
);
1523 si_shader_dump(sscreen
, shader
, NULL
, sel
->type
, f
, false);
1528 si_shader_init_pm4_state(sscreen
, shader
);
1531 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
1533 struct si_shader
*shader
= (struct si_shader
*)job
;
1535 assert(thread_index
>= 0);
1537 si_build_shader_variant(shader
, thread_index
, true);
1540 static const struct si_shader_key zeroed
;
1542 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
1543 struct si_shader_selector
*sel
,
1544 struct si_compiler_ctx_state
*compiler_state
,
1545 struct si_shader_key
*key
)
1547 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
1550 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
1555 /* We can leave the fence as permanently signaled because the
1556 * main part becomes visible globally only after it has been
1558 util_queue_fence_init(&main_part
->ready
);
1560 main_part
->selector
= sel
;
1561 main_part
->key
.as_es
= key
->as_es
;
1562 main_part
->key
.as_ls
= key
->as_ls
;
1564 if (si_compile_tgsi_shader(sscreen
, compiler_state
->compiler
,
1566 &compiler_state
->debug
) != 0) {
1575 /* Select the hw shader variant depending on the current state. */
1576 static int si_shader_select_with_key(struct si_screen
*sscreen
,
1577 struct si_shader_ctx_state
*state
,
1578 struct si_compiler_ctx_state
*compiler_state
,
1579 struct si_shader_key
*key
,
1582 struct si_shader_selector
*sel
= state
->cso
;
1583 struct si_shader_selector
*previous_stage_sel
= NULL
;
1584 struct si_shader
*current
= state
->current
;
1585 struct si_shader
*iter
, *shader
= NULL
;
1588 /* Check if we don't need to change anything.
1589 * This path is also used for most shaders that don't need multiple
1590 * variants, it will cost just a computation of the key and this
1592 if (likely(current
&&
1593 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0)) {
1594 if (unlikely(!util_queue_fence_is_signalled(¤t
->ready
))) {
1595 if (current
->is_optimized
) {
1596 memset(&key
->opt
, 0, sizeof(key
->opt
));
1597 goto current_not_ready
;
1600 util_queue_fence_wait(¤t
->ready
);
1603 return current
->compilation_failed
? -1 : 0;
1607 /* This must be done before the mutex is locked, because async GS
1608 * compilation calls this function too, and therefore must enter
1611 * Only wait if we are in a draw call. Don't wait if we are
1612 * in a compiler thread.
1614 if (thread_index
< 0)
1615 util_queue_fence_wait(&sel
->ready
);
1617 mtx_lock(&sel
->mutex
);
1619 /* Find the shader variant. */
1620 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
1621 /* Don't check the "current" shader. We checked it above. */
1622 if (current
!= iter
&&
1623 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
1624 mtx_unlock(&sel
->mutex
);
1626 if (unlikely(!util_queue_fence_is_signalled(&iter
->ready
))) {
1627 /* If it's an optimized shader and its compilation has
1628 * been started but isn't done, use the unoptimized
1629 * shader so as not to cause a stall due to compilation.
1631 if (iter
->is_optimized
) {
1632 memset(&key
->opt
, 0, sizeof(key
->opt
));
1636 util_queue_fence_wait(&iter
->ready
);
1639 if (iter
->compilation_failed
) {
1640 return -1; /* skip the draw call */
1643 state
->current
= iter
;
1648 /* Build a new shader. */
1649 shader
= CALLOC_STRUCT(si_shader
);
1651 mtx_unlock(&sel
->mutex
);
1655 util_queue_fence_init(&shader
->ready
);
1657 shader
->selector
= sel
;
1659 shader
->compiler_ctx_state
= *compiler_state
;
1661 /* If this is a merged shader, get the first shader's selector. */
1662 if (sscreen
->info
.chip_class
>= GFX9
) {
1663 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1664 previous_stage_sel
= key
->part
.tcs
.ls
;
1665 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1666 previous_stage_sel
= key
->part
.gs
.es
;
1668 /* We need to wait for the previous shader. */
1669 if (previous_stage_sel
&& thread_index
< 0)
1670 util_queue_fence_wait(&previous_stage_sel
->ready
);
1673 /* Compile the main shader part if it doesn't exist. This can happen
1674 * if the initial guess was wrong. */
1675 bool is_pure_monolithic
=
1676 sscreen
->use_monolithic_shaders
||
1677 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
1679 if (!is_pure_monolithic
) {
1682 /* Make sure the main shader part is present. This is needed
1683 * for shaders that can be compiled as VS, LS, or ES, and only
1684 * one of them is compiled at creation.
1686 * For merged shaders, check that the starting shader's main
1689 if (previous_stage_sel
) {
1690 struct si_shader_key shader1_key
= zeroed
;
1692 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1693 shader1_key
.as_ls
= 1;
1694 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1695 shader1_key
.as_es
= 1;
1699 mtx_lock(&previous_stage_sel
->mutex
);
1700 ok
= si_check_missing_main_part(sscreen
,
1702 compiler_state
, &shader1_key
);
1703 mtx_unlock(&previous_stage_sel
->mutex
);
1705 ok
= si_check_missing_main_part(sscreen
, sel
,
1706 compiler_state
, key
);
1710 mtx_unlock(&sel
->mutex
);
1711 return -ENOMEM
; /* skip the draw call */
1715 /* Keep the reference to the 1st shader of merged shaders, so that
1716 * Gallium can't destroy it before we destroy the 2nd shader.
1718 * Set sctx = NULL, because it's unused if we're not releasing
1719 * the shader, and we don't have any sctx here.
1721 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
1722 previous_stage_sel
);
1724 /* Monolithic-only shaders don't make a distinction between optimized
1725 * and unoptimized. */
1726 shader
->is_monolithic
=
1727 is_pure_monolithic
||
1728 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1730 shader
->is_optimized
=
1731 !is_pure_monolithic
&&
1732 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1734 /* If it's an optimized shader, compile it asynchronously. */
1735 if (shader
->is_optimized
&&
1736 !is_pure_monolithic
&&
1738 /* Compile it asynchronously. */
1739 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
,
1740 shader
, &shader
->ready
,
1741 si_build_shader_variant_low_priority
, NULL
);
1743 /* Add only after the ready fence was reset, to guard against a
1744 * race with si_bind_XX_shader. */
1745 if (!sel
->last_variant
) {
1746 sel
->first_variant
= shader
;
1747 sel
->last_variant
= shader
;
1749 sel
->last_variant
->next_variant
= shader
;
1750 sel
->last_variant
= shader
;
1753 /* Use the default (unoptimized) shader for now. */
1754 memset(&key
->opt
, 0, sizeof(key
->opt
));
1755 mtx_unlock(&sel
->mutex
);
1759 /* Reset the fence before adding to the variant list. */
1760 util_queue_fence_reset(&shader
->ready
);
1762 if (!sel
->last_variant
) {
1763 sel
->first_variant
= shader
;
1764 sel
->last_variant
= shader
;
1766 sel
->last_variant
->next_variant
= shader
;
1767 sel
->last_variant
= shader
;
1770 mtx_unlock(&sel
->mutex
);
1772 assert(!shader
->is_optimized
);
1773 si_build_shader_variant(shader
, thread_index
, false);
1775 util_queue_fence_signal(&shader
->ready
);
1777 if (!shader
->compilation_failed
)
1778 state
->current
= shader
;
1780 return shader
->compilation_failed
? -1 : 0;
1783 static int si_shader_select(struct pipe_context
*ctx
,
1784 struct si_shader_ctx_state
*state
,
1785 struct si_compiler_ctx_state
*compiler_state
)
1787 struct si_context
*sctx
= (struct si_context
*)ctx
;
1788 struct si_shader_key key
;
1790 si_shader_selector_key(ctx
, state
->cso
, &key
);
1791 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
1795 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
1797 struct si_shader_key
*key
)
1799 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
1801 switch (info
->processor
) {
1802 case PIPE_SHADER_VERTEX
:
1803 switch (next_shader
) {
1804 case PIPE_SHADER_GEOMETRY
:
1807 case PIPE_SHADER_TESS_CTRL
:
1808 case PIPE_SHADER_TESS_EVAL
:
1812 /* If POSITION isn't written, it can only be a HW VS
1813 * if streamout is used. If streamout isn't used,
1814 * assume that it's a HW LS. (the next shader is TCS)
1815 * This heuristic is needed for separate shader objects.
1817 if (!info
->writes_position
&& !streamout
)
1822 case PIPE_SHADER_TESS_EVAL
:
1823 if (next_shader
== PIPE_SHADER_GEOMETRY
||
1824 !info
->writes_position
)
1831 * Compile the main shader part or the monolithic shader as part of
1832 * si_shader_selector initialization. Since it can be done asynchronously,
1833 * there is no way to report compile failures to applications.
1835 static void si_init_shader_selector_async(void *job
, int thread_index
)
1837 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
1838 struct si_screen
*sscreen
= sel
->screen
;
1839 struct si_compiler
*compiler
;
1840 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
1842 assert(!debug
->debug_message
|| debug
->async
);
1843 assert(thread_index
>= 0);
1844 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
1845 compiler
= &sscreen
->compiler
[thread_index
];
1847 /* Compile the main shader part for use with a prolog and/or epilog.
1848 * If this fails, the driver will try to compile a monolithic shader
1851 if (!sscreen
->use_monolithic_shaders
) {
1852 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
1853 void *ir_binary
= NULL
;
1856 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
1860 /* We can leave the fence signaled because use of the default
1861 * main part is guarded by the selector's ready fence. */
1862 util_queue_fence_init(&shader
->ready
);
1864 shader
->selector
= sel
;
1865 si_parse_next_shader_property(&sel
->info
,
1866 sel
->so
.num_outputs
!= 0,
1869 if (sel
->tokens
|| sel
->nir
)
1870 ir_binary
= si_get_ir_binary(sel
);
1872 /* Try to load the shader from the shader cache. */
1873 mtx_lock(&sscreen
->shader_cache_mutex
);
1876 si_shader_cache_load_shader(sscreen
, ir_binary
, shader
)) {
1877 mtx_unlock(&sscreen
->shader_cache_mutex
);
1878 si_shader_dump_stats_for_shader_db(shader
, debug
);
1880 mtx_unlock(&sscreen
->shader_cache_mutex
);
1882 /* Compile the shader if it hasn't been loaded from the cache. */
1883 if (si_compile_tgsi_shader(sscreen
, compiler
, shader
, false,
1887 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
1892 mtx_lock(&sscreen
->shader_cache_mutex
);
1893 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
, shader
, true))
1895 mtx_unlock(&sscreen
->shader_cache_mutex
);
1899 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
1901 /* Unset "outputs_written" flags for outputs converted to
1902 * DEFAULT_VAL, so that later inter-shader optimizations don't
1903 * try to eliminate outputs that don't exist in the final
1906 * This is only done if non-monolithic shaders are enabled.
1908 if ((sel
->type
== PIPE_SHADER_VERTEX
||
1909 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
1910 !shader
->key
.as_ls
&&
1911 !shader
->key
.as_es
) {
1914 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
1915 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
1917 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
1920 unsigned name
= sel
->info
.output_semantic_name
[i
];
1921 unsigned index
= sel
->info
.output_semantic_index
[i
];
1925 case TGSI_SEMANTIC_GENERIC
:
1926 /* don't process indices the function can't handle */
1927 if (index
>= SI_MAX_IO_GENERIC
)
1931 id
= si_shader_io_get_unique_index(name
, index
, true);
1932 sel
->outputs_written_before_ps
&= ~(1ull << id
);
1934 case TGSI_SEMANTIC_POSITION
: /* ignore these */
1935 case TGSI_SEMANTIC_PSIZE
:
1936 case TGSI_SEMANTIC_CLIPVERTEX
:
1937 case TGSI_SEMANTIC_EDGEFLAG
:
1944 /* The GS copy shader is always pre-compiled. */
1945 if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
1946 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, compiler
, sel
, debug
);
1947 if (!sel
->gs_copy_shader
) {
1948 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
1952 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
1956 /* Return descriptor slot usage masks from the given shader info. */
1957 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
1958 uint32_t *const_and_shader_buffers
,
1959 uint64_t *samplers_and_images
)
1961 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_samplers
;
1963 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
1964 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
1965 /* two 8-byte images share one 16-byte slot */
1966 num_images
= align(util_last_bit(info
->images_declared
), 2);
1967 num_samplers
= util_last_bit(info
->samplers_declared
);
1969 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
1970 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
1971 *const_and_shader_buffers
=
1972 u_bit_consecutive(start
, num_shaderbufs
+ num_constbufs
);
1974 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
1975 start
= si_get_image_slot(num_images
- 1) / 2;
1976 *samplers_and_images
=
1977 u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
1980 static void *si_create_shader_selector(struct pipe_context
*ctx
,
1981 const struct pipe_shader_state
*state
)
1983 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
1984 struct si_context
*sctx
= (struct si_context
*)ctx
;
1985 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
1991 pipe_reference_init(&sel
->reference
, 1);
1992 sel
->screen
= sscreen
;
1993 sel
->compiler_ctx_state
.debug
= sctx
->debug
;
1994 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
1996 sel
->so
= state
->stream_output
;
1998 if (state
->type
== PIPE_SHADER_IR_TGSI
) {
1999 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
2005 tgsi_scan_shader(state
->tokens
, &sel
->info
);
2006 tgsi_scan_tess_ctrl(state
->tokens
, &sel
->info
, &sel
->tcs_info
);
2008 assert(state
->type
== PIPE_SHADER_IR_NIR
);
2010 sel
->nir
= state
->ir
.nir
;
2012 si_nir_scan_shader(sel
->nir
, &sel
->info
);
2013 si_nir_scan_tess_ctrl(sel
->nir
, &sel
->info
, &sel
->tcs_info
);
2018 sel
->type
= sel
->info
.processor
;
2019 p_atomic_inc(&sscreen
->num_shaders_created
);
2020 si_get_active_slot_masks(&sel
->info
,
2021 &sel
->active_const_and_shader_buffers
,
2022 &sel
->active_samplers_and_images
);
2024 /* Record which streamout buffers are enabled. */
2025 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
2026 sel
->enabled_streamout_buffer_mask
|=
2027 (1 << sel
->so
.output
[i
].output_buffer
) <<
2028 (sel
->so
.output
[i
].stream
* 4);
2031 /* The prolog is a no-op if there are no inputs. */
2032 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
2033 sel
->info
.num_inputs
&&
2034 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
2036 sel
->force_correct_derivs_after_kill
=
2037 sel
->type
== PIPE_SHADER_FRAGMENT
&&
2038 sel
->info
.uses_derivatives
&&
2039 sel
->info
.uses_kill
&&
2040 sctx
->screen
->debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
2042 /* Set which opcode uses which (i,j) pair. */
2043 if (sel
->info
.uses_persp_opcode_interp_centroid
)
2044 sel
->info
.uses_persp_centroid
= true;
2046 if (sel
->info
.uses_linear_opcode_interp_centroid
)
2047 sel
->info
.uses_linear_centroid
= true;
2049 if (sel
->info
.uses_persp_opcode_interp_offset
||
2050 sel
->info
.uses_persp_opcode_interp_sample
)
2051 sel
->info
.uses_persp_center
= true;
2053 if (sel
->info
.uses_linear_opcode_interp_offset
||
2054 sel
->info
.uses_linear_opcode_interp_sample
)
2055 sel
->info
.uses_linear_center
= true;
2057 switch (sel
->type
) {
2058 case PIPE_SHADER_GEOMETRY
:
2059 sel
->gs_output_prim
=
2060 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
2061 sel
->gs_max_out_vertices
=
2062 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
2063 sel
->gs_num_invocations
=
2064 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2065 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2066 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
2067 sel
->gs_max_out_vertices
;
2069 sel
->max_gs_stream
= 0;
2070 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2071 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
2072 sel
->so
.output
[i
].stream
);
2074 sel
->gs_input_verts_per_prim
=
2075 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2078 case PIPE_SHADER_TESS_CTRL
:
2079 /* Always reserve space for these. */
2080 sel
->patch_outputs_written
|=
2081 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0)) |
2082 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0));
2084 case PIPE_SHADER_VERTEX
:
2085 case PIPE_SHADER_TESS_EVAL
:
2086 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2087 unsigned name
= sel
->info
.output_semantic_name
[i
];
2088 unsigned index
= sel
->info
.output_semantic_index
[i
];
2091 case TGSI_SEMANTIC_TESSINNER
:
2092 case TGSI_SEMANTIC_TESSOUTER
:
2093 case TGSI_SEMANTIC_PATCH
:
2094 sel
->patch_outputs_written
|=
2095 1ull << si_shader_io_get_unique_index_patch(name
, index
);
2098 case TGSI_SEMANTIC_GENERIC
:
2099 /* don't process indices the function can't handle */
2100 if (index
>= SI_MAX_IO_GENERIC
)
2104 sel
->outputs_written
|=
2105 1ull << si_shader_io_get_unique_index(name
, index
, false);
2106 sel
->outputs_written_before_ps
|=
2107 1ull << si_shader_io_get_unique_index(name
, index
, true);
2109 case TGSI_SEMANTIC_EDGEFLAG
:
2113 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2115 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2116 * conflicts, i.e. each vertex will start at a different bank.
2118 if (sctx
->chip_class
>= GFX9
)
2119 sel
->esgs_itemsize
+= 4;
2121 assert(((sel
->esgs_itemsize
/ 4) & C_028AAC_ITEMSIZE
) == 0);
2124 case PIPE_SHADER_FRAGMENT
:
2125 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2126 unsigned name
= sel
->info
.input_semantic_name
[i
];
2127 unsigned index
= sel
->info
.input_semantic_index
[i
];
2130 case TGSI_SEMANTIC_GENERIC
:
2131 /* don't process indices the function can't handle */
2132 if (index
>= SI_MAX_IO_GENERIC
)
2137 1ull << si_shader_io_get_unique_index(name
, index
, true);
2139 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2144 for (i
= 0; i
< 8; i
++)
2145 if (sel
->info
.colors_written
& (1 << i
))
2146 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2148 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2149 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2150 int index
= sel
->info
.input_semantic_index
[i
];
2151 sel
->color_attr_index
[index
] = i
;
2157 /* PA_CL_VS_OUT_CNTL */
2159 sel
->info
.writes_psize
|| sel
->info
.writes_edgeflag
||
2160 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
2161 sel
->pa_cl_vs_out_cntl
=
2162 S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
2163 S_02881C_USE_VTX_EDGE_FLAG(sel
->info
.writes_edgeflag
) |
2164 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
2165 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
2166 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
2167 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
2168 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
?
2169 SIX_BITS
: sel
->info
.clipdist_writemask
;
2170 sel
->culldist_mask
= sel
->info
.culldist_writemask
<<
2171 sel
->info
.num_written_clipdistance
;
2173 /* DB_SHADER_CONTROL */
2174 sel
->db_shader_control
=
2175 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2176 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2177 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2178 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2180 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2181 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2182 sel
->db_shader_control
|=
2183 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2185 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2186 sel
->db_shader_control
|=
2187 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2191 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2193 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2194 * --|-----------|------------|------------|--------------------|-------------------|-------------
2195 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2196 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2197 * 2 | false | true | n/a | LateZ | 1 | 0
2198 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2199 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2201 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2202 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2204 * Don't use ReZ without profiling !!!
2206 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2209 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2211 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2212 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2213 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
2214 } else if (sel
->info
.writes_memory
) {
2216 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
2217 S_02880C_EXEC_ON_HIER_FAIL(1);
2220 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2223 (void) mtx_init(&sel
->mutex
, mtx_plain
);
2224 util_queue_fence_init(&sel
->ready
);
2226 struct util_async_debug_callback async_debug
;
2228 (sctx
->debug
.debug_message
&& !sctx
->debug
.async
) ||
2230 si_can_dump_shader(sscreen
, sel
->info
.processor
);
2233 u_async_debug_init(&async_debug
);
2234 sel
->compiler_ctx_state
.debug
= async_debug
.base
;
2237 util_queue_add_job(&sscreen
->shader_compiler_queue
, sel
,
2238 &sel
->ready
, si_init_shader_selector_async
,
2242 util_queue_fence_wait(&sel
->ready
);
2243 u_async_debug_drain(&async_debug
, &sctx
->debug
);
2244 u_async_debug_cleanup(&async_debug
);
2250 static void si_update_streamout_state(struct si_context
*sctx
)
2252 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
2254 if (!shader_with_so
)
2257 sctx
->streamout
.enabled_stream_buffers_mask
=
2258 shader_with_so
->enabled_streamout_buffer_mask
;
2259 sctx
->streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
2262 static void si_update_clip_regs(struct si_context
*sctx
,
2263 struct si_shader_selector
*old_hw_vs
,
2264 struct si_shader
*old_hw_vs_variant
,
2265 struct si_shader_selector
*next_hw_vs
,
2266 struct si_shader
*next_hw_vs_variant
)
2270 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
2271 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
2272 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
2273 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
2274 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
||
2275 !old_hw_vs_variant
||
2276 !next_hw_vs_variant
||
2277 old_hw_vs_variant
->key
.opt
.clip_disable
!=
2278 next_hw_vs_variant
->key
.opt
.clip_disable
))
2279 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
2282 static void si_update_common_shader_state(struct si_context
*sctx
)
2284 sctx
->uses_bindless_samplers
=
2285 si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
2286 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
2287 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
2288 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
2289 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
2290 sctx
->uses_bindless_images
=
2291 si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
2292 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
2293 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
2294 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
2295 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
2296 sctx
->do_update_shaders
= true;
2299 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2301 struct si_context
*sctx
= (struct si_context
*)ctx
;
2302 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2303 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2304 struct si_shader_selector
*sel
= state
;
2306 if (sctx
->vs_shader
.cso
== sel
)
2309 sctx
->vs_shader
.cso
= sel
;
2310 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2311 sctx
->num_vs_blit_sgprs
= sel
? sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
] : 0;
2313 si_update_common_shader_state(sctx
);
2314 si_update_vs_viewport_state(sctx
);
2315 si_set_active_descriptors_for_shader(sctx
, sel
);
2316 si_update_streamout_state(sctx
);
2317 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2318 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2321 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
2323 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
2324 (sctx
->tes_shader
.cso
&&
2325 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
2326 (sctx
->tcs_shader
.cso
&&
2327 sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
2328 (sctx
->gs_shader
.cso
&&
2329 sctx
->gs_shader
.cso
->info
.uses_primid
) ||
2330 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&&
2331 sctx
->ps_shader
.cso
->info
.uses_primid
);
2334 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
2336 struct si_context
*sctx
= (struct si_context
*)ctx
;
2337 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2338 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2339 struct si_shader_selector
*sel
= state
;
2340 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
2342 if (sctx
->gs_shader
.cso
== sel
)
2345 sctx
->gs_shader
.cso
= sel
;
2346 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2347 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
2349 si_update_common_shader_state(sctx
);
2350 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2352 if (enable_changed
) {
2353 si_shader_change_notify(sctx
);
2354 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2355 si_update_tess_uses_prim_id(sctx
);
2357 si_update_vs_viewport_state(sctx
);
2358 si_set_active_descriptors_for_shader(sctx
, sel
);
2359 si_update_streamout_state(sctx
);
2360 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2361 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2364 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
2366 struct si_context
*sctx
= (struct si_context
*)ctx
;
2367 struct si_shader_selector
*sel
= state
;
2368 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
2370 if (sctx
->tcs_shader
.cso
== sel
)
2373 sctx
->tcs_shader
.cso
= sel
;
2374 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2375 si_update_tess_uses_prim_id(sctx
);
2377 si_update_common_shader_state(sctx
);
2380 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
2382 si_set_active_descriptors_for_shader(sctx
, sel
);
2385 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
2387 struct si_context
*sctx
= (struct si_context
*)ctx
;
2388 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2389 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2390 struct si_shader_selector
*sel
= state
;
2391 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
2393 if (sctx
->tes_shader
.cso
== sel
)
2396 sctx
->tes_shader
.cso
= sel
;
2397 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
2398 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
2399 si_update_tess_uses_prim_id(sctx
);
2401 si_update_common_shader_state(sctx
);
2402 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2404 if (enable_changed
) {
2405 si_shader_change_notify(sctx
);
2406 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
2408 si_update_vs_viewport_state(sctx
);
2409 si_set_active_descriptors_for_shader(sctx
, sel
);
2410 si_update_streamout_state(sctx
);
2411 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2412 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2415 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
2417 struct si_context
*sctx
= (struct si_context
*)ctx
;
2418 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
2419 struct si_shader_selector
*sel
= state
;
2421 /* skip if supplied shader is one already in use */
2425 sctx
->ps_shader
.cso
= sel
;
2426 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
2428 si_update_common_shader_state(sctx
);
2430 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2431 si_update_tess_uses_prim_id(sctx
);
2434 old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
2435 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
2437 if (sctx
->screen
->has_out_of_order_rast
&&
2439 old_sel
->info
.writes_memory
!= sel
->info
.writes_memory
||
2440 old_sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] !=
2441 sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]))
2442 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2444 si_set_active_descriptors_for_shader(sctx
, sel
);
2445 si_update_ps_colorbuf0_slot(sctx
);
2448 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
2450 if (shader
->is_optimized
) {
2451 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
,
2455 util_queue_fence_destroy(&shader
->ready
);
2458 switch (shader
->selector
->type
) {
2459 case PIPE_SHADER_VERTEX
:
2460 if (shader
->key
.as_ls
) {
2461 assert(sctx
->chip_class
<= VI
);
2462 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
2463 } else if (shader
->key
.as_es
) {
2464 assert(sctx
->chip_class
<= VI
);
2465 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2467 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2470 case PIPE_SHADER_TESS_CTRL
:
2471 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
2473 case PIPE_SHADER_TESS_EVAL
:
2474 if (shader
->key
.as_es
) {
2475 assert(sctx
->chip_class
<= VI
);
2476 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2478 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2481 case PIPE_SHADER_GEOMETRY
:
2482 if (shader
->is_gs_copy_shader
)
2483 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2485 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
2487 case PIPE_SHADER_FRAGMENT
:
2488 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
2493 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
2494 si_shader_destroy(shader
);
2498 void si_destroy_shader_selector(struct si_context
*sctx
,
2499 struct si_shader_selector
*sel
)
2501 struct si_shader
*p
= sel
->first_variant
, *c
;
2502 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
2503 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
2504 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
2505 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
2506 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
2507 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
2510 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
2512 if (current_shader
[sel
->type
]->cso
== sel
) {
2513 current_shader
[sel
->type
]->cso
= NULL
;
2514 current_shader
[sel
->type
]->current
= NULL
;
2518 c
= p
->next_variant
;
2519 si_delete_shader(sctx
, p
);
2523 if (sel
->main_shader_part
)
2524 si_delete_shader(sctx
, sel
->main_shader_part
);
2525 if (sel
->main_shader_part_ls
)
2526 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
2527 if (sel
->main_shader_part_es
)
2528 si_delete_shader(sctx
, sel
->main_shader_part_es
);
2529 if (sel
->gs_copy_shader
)
2530 si_delete_shader(sctx
, sel
->gs_copy_shader
);
2532 util_queue_fence_destroy(&sel
->ready
);
2533 mtx_destroy(&sel
->mutex
);
2535 ralloc_free(sel
->nir
);
2539 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
2541 struct si_context
*sctx
= (struct si_context
*)ctx
;
2542 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
2544 si_shader_selector_reference(sctx
, &sel
, NULL
);
2547 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
2548 struct si_shader
*vs
, unsigned name
,
2549 unsigned index
, unsigned interpolate
)
2551 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
2552 unsigned j
, offset
, ps_input_cntl
= 0;
2554 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2555 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
))
2556 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
2558 if (name
== TGSI_SEMANTIC_PCOORD
||
2559 (name
== TGSI_SEMANTIC_TEXCOORD
&&
2560 sctx
->sprite_coord_enable
& (1 << index
))) {
2561 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
2564 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
2565 if (name
== vsinfo
->output_semantic_name
[j
] &&
2566 index
== vsinfo
->output_semantic_index
[j
]) {
2567 offset
= vs
->info
.vs_output_param_offset
[j
];
2569 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
2570 /* The input is loaded from parameter memory. */
2571 ps_input_cntl
|= S_028644_OFFSET(offset
);
2572 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2573 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
2574 /* This can happen with depth-only rendering. */
2577 /* The input is a DEFAULT_VAL constant. */
2578 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
2579 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
2580 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
2583 ps_input_cntl
= S_028644_OFFSET(0x20) |
2584 S_028644_DEFAULT_VAL(offset
);
2590 if (name
== TGSI_SEMANTIC_PRIMID
)
2591 /* PrimID is written after the last output. */
2592 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
2593 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2594 /* No corresponding output found, load defaults into input.
2595 * Don't set any other bits.
2596 * (FLAT_SHADE=1 completely changes behavior) */
2597 ps_input_cntl
= S_028644_OFFSET(0x20);
2598 /* D3D 9 behaviour. GL is undefined */
2599 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
2600 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
2602 return ps_input_cntl
;
2605 static void si_emit_spi_map(struct si_context
*sctx
)
2607 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
2608 struct si_shader
*ps
= sctx
->ps_shader
.current
;
2609 struct si_shader
*vs
= si_get_vs_state(sctx
);
2610 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
2611 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
2613 if (!ps
|| !ps
->selector
->info
.num_inputs
)
2616 num_interp
= si_get_ps_num_interp(ps
);
2617 assert(num_interp
> 0);
2618 radeon_set_context_reg_seq(cs
, R_028644_SPI_PS_INPUT_CNTL_0
, num_interp
);
2620 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
2621 unsigned name
= psinfo
->input_semantic_name
[i
];
2622 unsigned index
= psinfo
->input_semantic_index
[i
];
2623 unsigned interpolate
= psinfo
->input_interpolate
[i
];
2625 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, name
, index
,
2629 if (name
== TGSI_SEMANTIC_COLOR
) {
2630 assert(index
< ARRAY_SIZE(bcol_interp
));
2631 bcol_interp
[index
] = interpolate
;
2635 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
2636 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
2638 for (i
= 0; i
< 2; i
++) {
2639 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
2642 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, bcol
,
2643 i
, bcol_interp
[i
]));
2647 assert(num_interp
== num_written
);
2651 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2653 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
2655 if (sctx
->init_config_has_vgt_flush
)
2658 /* Done by Vulkan before VGT_FLUSH. */
2659 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2660 si_pm4_cmd_add(sctx
->init_config
,
2661 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2662 si_pm4_cmd_end(sctx
->init_config
, false);
2664 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2665 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2666 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2667 si_pm4_cmd_end(sctx
->init_config
, false);
2668 sctx
->init_config_has_vgt_flush
= true;
2671 /* Initialize state related to ESGS / GSVS ring buffers */
2672 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
2674 struct si_shader_selector
*es
=
2675 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
2676 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
2677 struct si_pm4_state
*pm4
;
2679 /* Chip constants. */
2680 unsigned num_se
= sctx
->screen
->info
.max_se
;
2681 unsigned wave_size
= 64;
2682 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
2683 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2684 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2686 unsigned gs_vertex_reuse
= (sctx
->chip_class
>= VI
? 32 : 16) * num_se
;
2687 unsigned alignment
= 256 * num_se
;
2688 /* The maximum size is 63.999 MB per SE. */
2689 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
2691 /* Calculate the minimum size. */
2692 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
2693 wave_size
, alignment
);
2695 /* These are recommended sizes, not minimum sizes. */
2696 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
2697 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
2698 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
2699 gs
->max_gsvs_emit_size
;
2701 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
2702 esgs_ring_size
= align(esgs_ring_size
, alignment
);
2703 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
2705 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
2706 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
2708 /* Some rings don't have to be allocated if shaders don't use them.
2709 * (e.g. no varyings between ES and GS or GS and VS)
2711 * GFX9 doesn't have the ESGS ring.
2713 bool update_esgs
= sctx
->chip_class
<= VI
&&
2715 (!sctx
->esgs_ring
||
2716 sctx
->esgs_ring
->width0
< esgs_ring_size
);
2717 bool update_gsvs
= gsvs_ring_size
&&
2718 (!sctx
->gsvs_ring
||
2719 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
2721 if (!update_esgs
&& !update_gsvs
)
2725 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
2727 pipe_aligned_buffer_create(sctx
->b
.screen
,
2728 SI_RESOURCE_FLAG_UNMAPPABLE
,
2730 esgs_ring_size
, alignment
);
2731 if (!sctx
->esgs_ring
)
2736 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
2738 pipe_aligned_buffer_create(sctx
->b
.screen
,
2739 SI_RESOURCE_FLAG_UNMAPPABLE
,
2741 gsvs_ring_size
, alignment
);
2742 if (!sctx
->gsvs_ring
)
2746 /* Create the "init_config_gs_rings" state. */
2747 pm4
= CALLOC_STRUCT(si_pm4_state
);
2751 if (sctx
->chip_class
>= CIK
) {
2752 if (sctx
->esgs_ring
) {
2753 assert(sctx
->chip_class
<= VI
);
2754 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
2755 sctx
->esgs_ring
->width0
/ 256);
2757 if (sctx
->gsvs_ring
)
2758 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
2759 sctx
->gsvs_ring
->width0
/ 256);
2761 if (sctx
->esgs_ring
)
2762 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
2763 sctx
->esgs_ring
->width0
/ 256);
2764 if (sctx
->gsvs_ring
)
2765 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
2766 sctx
->gsvs_ring
->width0
/ 256);
2769 /* Set the state. */
2770 if (sctx
->init_config_gs_rings
)
2771 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
2772 sctx
->init_config_gs_rings
= pm4
;
2774 if (!sctx
->init_config_has_vgt_flush
) {
2775 si_init_config_add_vgt_flush(sctx
);
2776 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
2779 /* Flush the context to re-emit both init_config states. */
2780 sctx
->initial_gfx_cs_size
= 0; /* force flush */
2781 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
2783 /* Set ring bindings. */
2784 if (sctx
->esgs_ring
) {
2785 assert(sctx
->chip_class
<= VI
);
2786 si_set_ring_buffer(sctx
, SI_ES_RING_ESGS
,
2787 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2788 true, true, 4, 64, 0);
2789 si_set_ring_buffer(sctx
, SI_GS_RING_ESGS
,
2790 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2791 false, false, 0, 0, 0);
2793 if (sctx
->gsvs_ring
) {
2794 si_set_ring_buffer(sctx
, SI_RING_GSVS
,
2795 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
2796 false, false, 0, 0, 0);
2802 static void si_shader_lock(struct si_shader
*shader
)
2804 mtx_lock(&shader
->selector
->mutex
);
2805 if (shader
->previous_stage_sel
) {
2806 assert(shader
->previous_stage_sel
!= shader
->selector
);
2807 mtx_lock(&shader
->previous_stage_sel
->mutex
);
2811 static void si_shader_unlock(struct si_shader
*shader
)
2813 if (shader
->previous_stage_sel
)
2814 mtx_unlock(&shader
->previous_stage_sel
->mutex
);
2815 mtx_unlock(&shader
->selector
->mutex
);
2819 * @returns 1 if \p sel has been updated to use a new scratch buffer
2821 * < 0 if there was a failure
2823 static int si_update_scratch_buffer(struct si_context
*sctx
,
2824 struct si_shader
*shader
)
2826 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
2832 /* This shader doesn't need a scratch buffer */
2833 if (shader
->config
.scratch_bytes_per_wave
== 0)
2836 /* Prevent race conditions when updating:
2837 * - si_shader::scratch_bo
2838 * - si_shader::binary::code
2839 * - si_shader::previous_stage::binary::code.
2841 si_shader_lock(shader
);
2843 /* This shader is already configured to use the current
2844 * scratch buffer. */
2845 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
2846 si_shader_unlock(shader
);
2850 assert(sctx
->scratch_buffer
);
2852 if (shader
->previous_stage
)
2853 si_shader_apply_scratch_relocs(shader
->previous_stage
, scratch_va
);
2855 si_shader_apply_scratch_relocs(shader
, scratch_va
);
2857 /* Replace the shader bo with a new bo that has the relocs applied. */
2858 r
= si_shader_binary_upload(sctx
->screen
, shader
);
2860 si_shader_unlock(shader
);
2864 /* Update the shader state to use the new shader bo. */
2865 si_shader_init_pm4_state(sctx
->screen
, shader
);
2867 r600_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
2869 si_shader_unlock(shader
);
2873 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
2875 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
2878 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
2880 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
2883 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
2885 if (!sctx
->tes_shader
.cso
)
2886 return NULL
; /* tessellation disabled */
2888 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
:
2889 sctx
->fixed_func_tcs_shader
.current
;
2892 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
2896 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
2897 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
2898 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
2899 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
2901 if (sctx
->tes_shader
.cso
) {
2902 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
2904 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(tcs
));
2909 static bool si_update_scratch_relocs(struct si_context
*sctx
)
2911 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
2914 /* Update the shaders, so that they are using the latest scratch.
2915 * The scratch buffer may have been changed since these shaders were
2916 * last used, so we still need to try to update them, even if they
2917 * require scratch buffers smaller than the current size.
2919 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
2923 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
2925 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
2929 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
2931 r
= si_update_scratch_buffer(sctx
, tcs
);
2935 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
2937 /* VS can be bound as LS, ES, or VS. */
2938 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
2942 if (sctx
->tes_shader
.current
)
2943 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
2944 else if (sctx
->gs_shader
.current
)
2945 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
2947 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
2950 /* TES can be bound as ES or VS. */
2951 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
2955 if (sctx
->gs_shader
.current
)
2956 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
2958 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
2964 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
2966 unsigned current_scratch_buffer_size
=
2967 si_get_current_scratch_buffer_size(sctx
);
2968 unsigned scratch_bytes_per_wave
=
2969 si_get_max_scratch_bytes_per_wave(sctx
);
2970 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
2971 sctx
->scratch_waves
;
2972 unsigned spi_tmpring_size
;
2974 if (scratch_needed_size
> 0) {
2975 if (scratch_needed_size
> current_scratch_buffer_size
) {
2976 /* Create a bigger scratch buffer */
2977 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
2979 sctx
->scratch_buffer
=
2980 si_aligned_buffer_create(&sctx
->screen
->b
,
2981 SI_RESOURCE_FLAG_UNMAPPABLE
,
2983 scratch_needed_size
, 256);
2984 if (!sctx
->scratch_buffer
)
2987 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
2988 si_context_add_resource_size(sctx
,
2989 &sctx
->scratch_buffer
->b
.b
);
2992 if (!si_update_scratch_relocs(sctx
))
2996 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2997 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
2998 "scratch size should already be aligned correctly.");
3000 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
3001 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
3002 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
3003 sctx
->spi_tmpring_size
= spi_tmpring_size
;
3004 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3009 static void si_init_tess_factor_ring(struct si_context
*sctx
)
3011 assert(!sctx
->tess_rings
);
3013 /* The address must be aligned to 2^19, because the shader only
3014 * receives the high 13 bits.
3016 sctx
->tess_rings
= pipe_aligned_buffer_create(sctx
->b
.screen
,
3017 SI_RESOURCE_FLAG_32BIT
,
3019 sctx
->screen
->tess_offchip_ring_size
+
3020 sctx
->screen
->tess_factor_ring_size
,
3022 if (!sctx
->tess_rings
)
3025 si_init_config_add_vgt_flush(sctx
);
3027 si_pm4_add_bo(sctx
->init_config
, r600_resource(sctx
->tess_rings
),
3028 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3030 uint64_t factor_va
= r600_resource(sctx
->tess_rings
)->gpu_address
+
3031 sctx
->screen
->tess_offchip_ring_size
;
3033 /* Append these registers to the init config state. */
3034 if (sctx
->chip_class
>= CIK
) {
3035 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
3036 S_030938_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3037 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
3039 if (sctx
->chip_class
>= GFX9
)
3040 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3041 S_030944_BASE_HI(factor_va
>> 40));
3042 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3043 sctx
->screen
->vgt_hs_offchip_param
);
3045 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
3046 S_008988_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3047 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
3049 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3050 sctx
->screen
->vgt_hs_offchip_param
);
3053 /* Flush the context to re-emit the init_config state.
3054 * This is done only once in a lifetime of a context.
3056 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3057 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3058 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3062 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
3063 * VS passes its outputs to TES directly, so the fixed-function shader only
3064 * has to write TESSOUTER and TESSINNER.
3066 static void si_generate_fixed_func_tcs(struct si_context
*sctx
)
3068 struct ureg_src outer
, inner
;
3069 struct ureg_dst tessouter
, tessinner
;
3070 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
3073 return; /* if we get here, we're screwed */
3075 assert(!sctx
->fixed_func_tcs_shader
.cso
);
3077 outer
= ureg_DECL_system_value(ureg
,
3078 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
, 0);
3079 inner
= ureg_DECL_system_value(ureg
,
3080 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
, 0);
3082 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
3083 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
3085 ureg_MOV(ureg
, tessouter
, outer
);
3086 ureg_MOV(ureg
, tessinner
, inner
);
3089 sctx
->fixed_func_tcs_shader
.cso
=
3090 ureg_create_shader_and_destroy(ureg
, &sctx
->b
);
3093 static void si_update_vgt_shader_config(struct si_context
*sctx
)
3095 /* Calculate the index of the config.
3096 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3097 unsigned index
= 2*!!sctx
->tes_shader
.cso
+ !!sctx
->gs_shader
.cso
;
3098 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[index
];
3101 uint32_t stages
= 0;
3103 *pm4
= CALLOC_STRUCT(si_pm4_state
);
3105 if (sctx
->tes_shader
.cso
) {
3106 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3107 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3109 if (sctx
->gs_shader
.cso
)
3110 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3112 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3114 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3115 } else if (sctx
->gs_shader
.cso
) {
3116 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3118 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3121 if (sctx
->chip_class
>= GFX9
)
3122 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3124 si_pm4_set_reg(*pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3126 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3129 bool si_update_shaders(struct si_context
*sctx
)
3131 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3132 struct si_compiler_ctx_state compiler_state
;
3133 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3134 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3135 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
3136 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
3137 unsigned old_spi_shader_col_format
=
3138 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
3141 compiler_state
.compiler
= &sctx
->compiler
;
3142 compiler_state
.debug
= sctx
->debug
;
3143 compiler_state
.is_debug_context
= sctx
->is_debug
;
3145 /* Update stages before GS. */
3146 if (sctx
->tes_shader
.cso
) {
3147 if (!sctx
->tess_rings
) {
3148 si_init_tess_factor_ring(sctx
);
3149 if (!sctx
->tess_rings
)
3154 if (sctx
->chip_class
<= VI
) {
3155 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3159 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3162 if (sctx
->tcs_shader
.cso
) {
3163 r
= si_shader_select(ctx
, &sctx
->tcs_shader
,
3167 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3169 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3170 si_generate_fixed_func_tcs(sctx
);
3171 if (!sctx
->fixed_func_tcs_shader
.cso
)
3175 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
3179 si_pm4_bind_state(sctx
, hs
,
3180 sctx
->fixed_func_tcs_shader
.current
->pm4
);
3183 if (sctx
->gs_shader
.cso
) {
3185 if (sctx
->chip_class
<= VI
) {
3186 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3190 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3194 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3198 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3200 } else if (sctx
->gs_shader
.cso
) {
3201 if (sctx
->chip_class
<= VI
) {
3203 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3207 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3209 si_pm4_bind_state(sctx
, ls
, NULL
);
3210 si_pm4_bind_state(sctx
, hs
, NULL
);
3214 r
= si_shader_select(ctx
, &sctx
->vs_shader
, &compiler_state
);
3217 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3218 si_pm4_bind_state(sctx
, ls
, NULL
);
3219 si_pm4_bind_state(sctx
, hs
, NULL
);
3223 if (sctx
->gs_shader
.cso
) {
3224 r
= si_shader_select(ctx
, &sctx
->gs_shader
, &compiler_state
);
3227 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3228 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3230 if (!si_update_gs_ring_buffers(sctx
))
3233 si_pm4_bind_state(sctx
, gs
, NULL
);
3234 if (sctx
->chip_class
<= VI
)
3235 si_pm4_bind_state(sctx
, es
, NULL
);
3238 si_update_vgt_shader_config(sctx
);
3240 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
3241 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
3243 if (sctx
->ps_shader
.cso
) {
3244 unsigned db_shader_control
;
3246 r
= si_shader_select(ctx
, &sctx
->ps_shader
, &compiler_state
);
3249 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3252 sctx
->ps_shader
.cso
->db_shader_control
|
3253 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
3255 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
3256 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
3257 sctx
->flatshade
!= rs
->flatshade
) {
3258 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
3259 sctx
->flatshade
= rs
->flatshade
;
3260 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.spi_map
);
3263 if (sctx
->screen
->rbplus_allowed
&&
3264 si_pm4_state_changed(sctx
, ps
) &&
3266 old_spi_shader_col_format
!=
3267 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
3268 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3270 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
3271 sctx
->ps_db_shader_control
= db_shader_control
;
3272 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3273 if (sctx
->screen
->dpbb_allowed
)
3274 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3277 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
3278 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
3279 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3281 if (sctx
->chip_class
== SI
)
3282 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3284 if (sctx
->framebuffer
.nr_samples
<= 1)
3285 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
3289 if (si_pm4_state_enabled_and_changed(sctx
, ls
) ||
3290 si_pm4_state_enabled_and_changed(sctx
, hs
) ||
3291 si_pm4_state_enabled_and_changed(sctx
, es
) ||
3292 si_pm4_state_enabled_and_changed(sctx
, gs
) ||
3293 si_pm4_state_enabled_and_changed(sctx
, vs
) ||
3294 si_pm4_state_enabled_and_changed(sctx
, ps
)) {
3295 if (!si_update_spi_tmpring_size(sctx
))
3299 if (sctx
->chip_class
>= CIK
) {
3300 if (si_pm4_state_enabled_and_changed(sctx
, ls
))
3301 sctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
3302 else if (!sctx
->queued
.named
.ls
)
3303 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_LS
;
3305 if (si_pm4_state_enabled_and_changed(sctx
, hs
))
3306 sctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
3307 else if (!sctx
->queued
.named
.hs
)
3308 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_HS
;
3310 if (si_pm4_state_enabled_and_changed(sctx
, es
))
3311 sctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
3312 else if (!sctx
->queued
.named
.es
)
3313 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_ES
;
3315 if (si_pm4_state_enabled_and_changed(sctx
, gs
))
3316 sctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
3317 else if (!sctx
->queued
.named
.gs
)
3318 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_GS
;
3320 if (si_pm4_state_enabled_and_changed(sctx
, vs
))
3321 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
3322 else if (!sctx
->queued
.named
.vs
)
3323 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VS
;
3325 if (si_pm4_state_enabled_and_changed(sctx
, ps
))
3326 sctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
3327 else if (!sctx
->queued
.named
.ps
)
3328 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_PS
;
3331 sctx
->do_update_shaders
= false;
3335 static void si_emit_scratch_state(struct si_context
*sctx
)
3337 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
3339 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3340 sctx
->spi_tmpring_size
);
3342 if (sctx
->scratch_buffer
) {
3343 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3344 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
3345 RADEON_PRIO_SCRATCH_BUFFER
);
3349 void *si_get_blit_vs(struct si_context
*sctx
, enum blitter_attrib_type type
,
3350 unsigned num_layers
)
3352 unsigned vs_blit_property
;
3356 case UTIL_BLITTER_ATTRIB_NONE
:
3357 vs
= num_layers
> 1 ? &sctx
->vs_blit_pos_layered
:
3359 vs_blit_property
= SI_VS_BLIT_SGPRS_POS
;
3361 case UTIL_BLITTER_ATTRIB_COLOR
:
3362 vs
= num_layers
> 1 ? &sctx
->vs_blit_color_layered
:
3363 &sctx
->vs_blit_color
;
3364 vs_blit_property
= SI_VS_BLIT_SGPRS_POS_COLOR
;
3366 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY
:
3367 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW
:
3368 assert(num_layers
== 1);
3369 vs
= &sctx
->vs_blit_texcoord
;
3370 vs_blit_property
= SI_VS_BLIT_SGPRS_POS_TEXCOORD
;
3379 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_VERTEX
);
3383 /* Tell the shader to load VS inputs from SGPRs: */
3384 ureg_property(ureg
, TGSI_PROPERTY_VS_BLIT_SGPRS
, vs_blit_property
);
3385 ureg_property(ureg
, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
, true);
3387 /* This is just a pass-through shader with 1-3 MOV instructions. */
3389 ureg_DECL_output(ureg
, TGSI_SEMANTIC_POSITION
, 0),
3390 ureg_DECL_vs_input(ureg
, 0));
3392 if (type
!= UTIL_BLITTER_ATTRIB_NONE
) {
3394 ureg_DECL_output(ureg
, TGSI_SEMANTIC_GENERIC
, 0),
3395 ureg_DECL_vs_input(ureg
, 1));
3398 if (num_layers
> 1) {
3399 struct ureg_src instance_id
=
3400 ureg_DECL_system_value(ureg
, TGSI_SEMANTIC_INSTANCEID
, 0);
3401 struct ureg_dst layer
=
3402 ureg_DECL_output(ureg
, TGSI_SEMANTIC_LAYER
, 0);
3404 ureg_MOV(ureg
, ureg_writemask(layer
, TGSI_WRITEMASK_X
),
3405 ureg_scalar(instance_id
, TGSI_SWIZZLE_X
));
3409 *vs
= ureg_create_shader_and_destroy(ureg
, &sctx
->b
);
3413 void si_init_shader_functions(struct si_context
*sctx
)
3415 sctx
->atoms
.s
.spi_map
.emit
= si_emit_spi_map
;
3416 sctx
->atoms
.s
.scratch_state
.emit
= si_emit_scratch_state
;
3418 sctx
->b
.create_vs_state
= si_create_shader_selector
;
3419 sctx
->b
.create_tcs_state
= si_create_shader_selector
;
3420 sctx
->b
.create_tes_state
= si_create_shader_selector
;
3421 sctx
->b
.create_gs_state
= si_create_shader_selector
;
3422 sctx
->b
.create_fs_state
= si_create_shader_selector
;
3424 sctx
->b
.bind_vs_state
= si_bind_vs_shader
;
3425 sctx
->b
.bind_tcs_state
= si_bind_tcs_shader
;
3426 sctx
->b
.bind_tes_state
= si_bind_tes_shader
;
3427 sctx
->b
.bind_gs_state
= si_bind_gs_shader
;
3428 sctx
->b
.bind_fs_state
= si_bind_ps_shader
;
3430 sctx
->b
.delete_vs_state
= si_delete_shader_selector
;
3431 sctx
->b
.delete_tcs_state
= si_delete_shader_selector
;
3432 sctx
->b
.delete_tes_state
= si_delete_shader_selector
;
3433 sctx
->b
.delete_gs_state
= si_delete_shader_selector
;
3434 sctx
->b
.delete_fs_state
= si_delete_shader_selector
;