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radeonsi: lower discard to demote when FS_CORRECT_DERIVS_AFTER_KILL is enabled
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR key for the shader cache.
45 */
46 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
47 unsigned char ir_sha1_cache_key[20])
48 {
49 struct blob blob = {};
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->nir_binary) {
54 ir_binary = sel->nir_binary;
55 ir_size = sel->nir_size;
56 } else {
57 assert(sel->nir);
58
59 blob_init(&blob);
60 nir_serialize(&blob, sel->nir, true);
61 ir_binary = blob.data;
62 ir_size = blob.size;
63 }
64
65 /* These settings affect the compilation, but they are not derived
66 * from the input shader IR.
67 */
68 unsigned shader_variant_flags = 0;
69
70 if (ngg)
71 shader_variant_flags |= 1 << 0;
72 if (sel->nir)
73 shader_variant_flags |= 1 << 1;
74 if (si_get_wave_size(sel->screen, sel->type, ngg, es) == 32)
75 shader_variant_flags |= 1 << 2;
76 if (sel->type == PIPE_SHADER_FRAGMENT &&
77 sel->info.uses_derivatives &&
78 sel->info.uses_kill &&
79 sel->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL))
80 shader_variant_flags |= 1 << 3;
81
82 struct mesa_sha1 ctx;
83 _mesa_sha1_init(&ctx);
84 _mesa_sha1_update(&ctx, &shader_variant_flags, 4);
85 _mesa_sha1_update(&ctx, ir_binary, ir_size);
86 if (sel->type == PIPE_SHADER_VERTEX ||
87 sel->type == PIPE_SHADER_TESS_EVAL ||
88 sel->type == PIPE_SHADER_GEOMETRY)
89 _mesa_sha1_update(&ctx, &sel->so, sizeof(sel->so));
90 _mesa_sha1_final(&ctx, ir_sha1_cache_key);
91
92 if (ir_binary == blob.data)
93 blob_finish(&blob);
94 }
95
96 /** Copy "data" to "ptr" and return the next dword following copied data. */
97 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
98 {
99 /* data may be NULL if size == 0 */
100 if (size)
101 memcpy(ptr, data, size);
102 ptr += DIV_ROUND_UP(size, 4);
103 return ptr;
104 }
105
106 /** Read data from "ptr". Return the next dword following the data. */
107 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
108 {
109 memcpy(data, ptr, size);
110 ptr += DIV_ROUND_UP(size, 4);
111 return ptr;
112 }
113
114 /**
115 * Write the size as uint followed by the data. Return the next dword
116 * following the copied data.
117 */
118 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
119 {
120 *ptr++ = size;
121 return write_data(ptr, data, size);
122 }
123
124 /**
125 * Read the size as uint followed by the data. Return both via parameters.
126 * Return the next dword following the data.
127 */
128 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
129 {
130 *size = *ptr++;
131 assert(*data == NULL);
132 if (!*size)
133 return ptr;
134 *data = malloc(*size);
135 return read_data(ptr, *data, *size);
136 }
137
138 /**
139 * Return the shader binary in a buffer. The first 4 bytes contain its size
140 * as integer.
141 */
142 static void *si_get_shader_binary(struct si_shader *shader)
143 {
144 /* There is always a size of data followed by the data itself. */
145 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
146 strlen(shader->binary.llvm_ir_string) + 1 : 0;
147
148 /* Refuse to allocate overly large buffers and guard against integer
149 * overflow. */
150 if (shader->binary.elf_size > UINT_MAX / 4 ||
151 llvm_ir_size > UINT_MAX / 4)
152 return NULL;
153
154 unsigned size =
155 4 + /* total size */
156 4 + /* CRC32 of the data below */
157 align(sizeof(shader->config), 4) +
158 align(sizeof(shader->info), 4) +
159 4 + align(shader->binary.elf_size, 4) +
160 4 + align(llvm_ir_size, 4);
161 void *buffer = CALLOC(1, size);
162 uint32_t *ptr = (uint32_t*)buffer;
163
164 if (!buffer)
165 return NULL;
166
167 *ptr++ = size;
168 ptr++; /* CRC32 is calculated at the end. */
169
170 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
171 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
172 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
173 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
174 assert((char *)ptr - (char *)buffer == size);
175
176 /* Compute CRC32. */
177 ptr = (uint32_t*)buffer;
178 ptr++;
179 *ptr = util_hash_crc32(ptr + 1, size - 8);
180
181 return buffer;
182 }
183
184 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
185 {
186 uint32_t *ptr = (uint32_t*)binary;
187 uint32_t size = *ptr++;
188 uint32_t crc32 = *ptr++;
189 unsigned chunk_size;
190 unsigned elf_size;
191
192 if (util_hash_crc32(ptr, size - 8) != crc32) {
193 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
194 return false;
195 }
196
197 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
198 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
199 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
200 &elf_size);
201 shader->binary.elf_size = elf_size;
202 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
203
204 return true;
205 }
206
207 /**
208 * Insert a shader into the cache. It's assumed the shader is not in the cache.
209 * Use si_shader_cache_load_shader before calling this.
210 */
211 void si_shader_cache_insert_shader(struct si_screen *sscreen,
212 unsigned char ir_sha1_cache_key[20],
213 struct si_shader *shader,
214 bool insert_into_disk_cache)
215 {
216 void *hw_binary;
217 struct hash_entry *entry;
218 uint8_t key[CACHE_KEY_SIZE];
219
220 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
221 if (entry)
222 return; /* already added */
223
224 hw_binary = si_get_shader_binary(shader);
225 if (!hw_binary)
226 return;
227
228 if (_mesa_hash_table_insert(sscreen->shader_cache,
229 mem_dup(ir_sha1_cache_key, 20),
230 hw_binary) == NULL) {
231 FREE(hw_binary);
232 return;
233 }
234
235 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
236 disk_cache_compute_key(sscreen->disk_shader_cache,
237 ir_sha1_cache_key, 20, key);
238 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
239 *((uint32_t *) hw_binary), NULL);
240 }
241 }
242
243 bool si_shader_cache_load_shader(struct si_screen *sscreen,
244 unsigned char ir_sha1_cache_key[20],
245 struct si_shader *shader)
246 {
247 struct hash_entry *entry =
248 _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
249
250 if (entry) {
251 if (si_load_shader_binary(shader, entry->data)) {
252 p_atomic_inc(&sscreen->num_memory_shader_cache_hits);
253 return true;
254 }
255 }
256 p_atomic_inc(&sscreen->num_memory_shader_cache_misses);
257
258 if (!sscreen->disk_shader_cache)
259 return false;
260
261 unsigned char sha1[CACHE_KEY_SIZE];
262 disk_cache_compute_key(sscreen->disk_shader_cache, ir_sha1_cache_key,
263 20, sha1);
264
265 size_t binary_size;
266 uint8_t *buffer = disk_cache_get(sscreen->disk_shader_cache, sha1,
267 &binary_size);
268 if (buffer) {
269 if (binary_size >= sizeof(uint32_t) &&
270 *((uint32_t*)buffer) == binary_size) {
271 if (si_load_shader_binary(shader, buffer)) {
272 free(buffer);
273 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
274 shader, false);
275 p_atomic_inc(&sscreen->num_disk_shader_cache_hits);
276 return true;
277 }
278 } else {
279 /* Something has gone wrong discard the item from the cache and
280 * rebuild/link from source.
281 */
282 assert(!"Invalid radeonsi shader disk cache item!");
283 disk_cache_remove(sscreen->disk_shader_cache, sha1);
284 }
285 }
286
287 free(buffer);
288 p_atomic_inc(&sscreen->num_disk_shader_cache_misses);
289 return false;
290 }
291
292 static uint32_t si_shader_cache_key_hash(const void *key)
293 {
294 /* Take the first dword of SHA1. */
295 return *(uint32_t*)key;
296 }
297
298 static bool si_shader_cache_key_equals(const void *a, const void *b)
299 {
300 /* Compare SHA1s. */
301 return memcmp(a, b, 20) == 0;
302 }
303
304 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
305 {
306 FREE((void*)entry->key);
307 FREE(entry->data);
308 }
309
310 bool si_init_shader_cache(struct si_screen *sscreen)
311 {
312 (void) simple_mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
313 sscreen->shader_cache =
314 _mesa_hash_table_create(NULL,
315 si_shader_cache_key_hash,
316 si_shader_cache_key_equals);
317
318 return sscreen->shader_cache != NULL;
319 }
320
321 void si_destroy_shader_cache(struct si_screen *sscreen)
322 {
323 if (sscreen->shader_cache)
324 _mesa_hash_table_destroy(sscreen->shader_cache,
325 si_destroy_shader_cache_entry);
326 simple_mtx_destroy(&sscreen->shader_cache_mutex);
327 }
328
329 /* SHADER STATES */
330
331 static void si_set_tesseval_regs(struct si_screen *sscreen,
332 const struct si_shader_selector *tes,
333 struct si_pm4_state *pm4)
334 {
335 const struct si_shader_info *info = &tes->info;
336 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
337 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
338 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
339 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
340 unsigned type, partitioning, topology, distribution_mode;
341
342 switch (tes_prim_mode) {
343 case PIPE_PRIM_LINES:
344 type = V_028B6C_TESS_ISOLINE;
345 break;
346 case PIPE_PRIM_TRIANGLES:
347 type = V_028B6C_TESS_TRIANGLE;
348 break;
349 case PIPE_PRIM_QUADS:
350 type = V_028B6C_TESS_QUAD;
351 break;
352 default:
353 assert(0);
354 return;
355 }
356
357 switch (tes_spacing) {
358 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
359 partitioning = V_028B6C_PART_FRAC_ODD;
360 break;
361 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
362 partitioning = V_028B6C_PART_FRAC_EVEN;
363 break;
364 case PIPE_TESS_SPACING_EQUAL:
365 partitioning = V_028B6C_PART_INTEGER;
366 break;
367 default:
368 assert(0);
369 return;
370 }
371
372 if (tes_point_mode)
373 topology = V_028B6C_OUTPUT_POINT;
374 else if (tes_prim_mode == PIPE_PRIM_LINES)
375 topology = V_028B6C_OUTPUT_LINE;
376 else if (tes_vertex_order_cw)
377 /* for some reason, this must be the other way around */
378 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
379 else
380 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
381
382 if (sscreen->info.has_distributed_tess) {
383 if (sscreen->info.family == CHIP_FIJI ||
384 sscreen->info.family >= CHIP_POLARIS10)
385 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
386 else
387 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
388 } else
389 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
390
391 assert(pm4->shader);
392 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
393 S_028B6C_PARTITIONING(partitioning) |
394 S_028B6C_TOPOLOGY(topology) |
395 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
396 }
397
398 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
399 * whether the "fractional odd" tessellation spacing is used.
400 *
401 * Possible VGT configurations and which state should set the register:
402 *
403 * Reg set in | VGT shader configuration | Value
404 * ------------------------------------------------------
405 * VS as VS | VS | 30
406 * VS as ES | ES -> GS -> VS | 30
407 * TES as VS | LS -> HS -> VS | 14 or 30
408 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
409 *
410 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
411 */
412 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
413 struct si_shader_selector *sel,
414 struct si_shader *shader,
415 struct si_pm4_state *pm4)
416 {
417 unsigned type = sel->type;
418
419 if (sscreen->info.family < CHIP_POLARIS10 ||
420 sscreen->info.chip_class >= GFX10)
421 return;
422
423 /* VS as VS, or VS as ES: */
424 if ((type == PIPE_SHADER_VERTEX &&
425 (!shader ||
426 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
427 /* TES as VS, or TES as ES: */
428 type == PIPE_SHADER_TESS_EVAL) {
429 unsigned vtx_reuse_depth = 30;
430
431 if (type == PIPE_SHADER_TESS_EVAL &&
432 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
433 PIPE_TESS_SPACING_FRACTIONAL_ODD)
434 vtx_reuse_depth = 14;
435
436 assert(pm4->shader);
437 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
438 }
439 }
440
441 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
442 {
443 if (shader->pm4)
444 si_pm4_clear_state(shader->pm4);
445 else
446 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
447
448 if (shader->pm4) {
449 shader->pm4->shader = shader;
450 return shader->pm4;
451 } else {
452 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
453 return NULL;
454 }
455 }
456
457 static unsigned si_get_num_vs_user_sgprs(struct si_shader *shader,
458 unsigned num_always_on_user_sgprs)
459 {
460 struct si_shader_selector *vs = shader->previous_stage_sel ?
461 shader->previous_stage_sel : shader->selector;
462 unsigned num_vbos_in_user_sgprs = vs->num_vbos_in_user_sgprs;
463
464 /* 1 SGPR is reserved for the vertex buffer pointer. */
465 assert(num_always_on_user_sgprs <= SI_SGPR_VS_VB_DESCRIPTOR_FIRST - 1);
466
467 if (num_vbos_in_user_sgprs)
468 return SI_SGPR_VS_VB_DESCRIPTOR_FIRST + num_vbos_in_user_sgprs * 4;
469
470 /* Add the pointer to VBO descriptors. */
471 return num_always_on_user_sgprs + 1;
472 }
473
474 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
475 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen,
476 struct si_shader *shader, bool legacy_vs_prim_id)
477 {
478 assert(shader->selector->type == PIPE_SHADER_VERTEX ||
479 (shader->previous_stage_sel &&
480 shader->previous_stage_sel->type == PIPE_SHADER_VERTEX));
481
482 /* GFX6-9 LS (VertexID, RelAutoindex, InstanceID / StepRate0(==1), ...).
483 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID, ...)
484 * GFX10 LS (VertexID, RelAutoindex, UserVGPR1, InstanceID).
485 * GFX10 ES,VS (VertexID, UserVGPR0, UserVGPR1 or VSPrimID, UserVGPR2 or InstanceID)
486 */
487 bool is_ls = shader->selector->type == PIPE_SHADER_TESS_CTRL || shader->key.as_ls;
488
489 if (sscreen->info.chip_class >= GFX10 && shader->info.uses_instanceid)
490 return 3;
491 else if ((is_ls && shader->info.uses_instanceid) || legacy_vs_prim_id)
492 return 2;
493 else if (is_ls || shader->info.uses_instanceid)
494 return 1;
495 else
496 return 0;
497 }
498
499 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
500 {
501 struct si_pm4_state *pm4;
502 uint64_t va;
503
504 assert(sscreen->info.chip_class <= GFX8);
505
506 pm4 = si_get_shader_pm4_state(shader);
507 if (!pm4)
508 return;
509
510 va = shader->bo->gpu_address;
511 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
512
513 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
514 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
515
516 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
517 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
518 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen, shader, false)) |
519 S_00B528_DX10_CLAMP(1) |
520 S_00B528_FLOAT_MODE(shader->config.float_mode);
521 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR)) |
522 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
523 }
524
525 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
526 {
527 struct si_pm4_state *pm4;
528 uint64_t va;
529
530 pm4 = si_get_shader_pm4_state(shader);
531 if (!pm4)
532 return;
533
534 va = shader->bo->gpu_address;
535 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
536
537 if (sscreen->info.chip_class >= GFX9) {
538 if (sscreen->info.chip_class >= GFX10) {
539 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
540 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
541 } else {
542 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
543 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
544 }
545
546 unsigned num_user_sgprs =
547 si_get_num_vs_user_sgprs(shader, GFX9_TCS_NUM_USER_SGPR);
548
549 shader->config.rsrc2 =
550 S_00B42C_USER_SGPR(num_user_sgprs) |
551 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
552
553 if (sscreen->info.chip_class >= GFX10)
554 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
555 else
556 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
557 } else {
558 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
559 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
560
561 shader->config.rsrc2 =
562 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
563 S_00B42C_OC_LDS_EN(1) |
564 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
565 }
566
567 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
568 S_00B428_VGPRS((shader->config.num_vgprs - 1) /
569 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
570 (sscreen->info.chip_class <= GFX9 ?
571 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
572 S_00B428_DX10_CLAMP(1) |
573 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
574 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
575 S_00B428_FLOAT_MODE(shader->config.float_mode) |
576 S_00B428_LS_VGPR_COMP_CNT(sscreen->info.chip_class >= GFX9 ?
577 si_get_vs_vgpr_comp_cnt(sscreen, shader, false) : 0));
578
579 if (sscreen->info.chip_class <= GFX8) {
580 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
581 shader->config.rsrc2);
582 }
583 }
584
585 static void si_emit_shader_es(struct si_context *sctx)
586 {
587 struct si_shader *shader = sctx->queued.named.es->shader;
588 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
589
590 if (!shader)
591 return;
592
593 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
594 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
595 shader->selector->esgs_itemsize / 4);
596
597 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
598 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
599 SI_TRACKED_VGT_TF_PARAM,
600 shader->vgt_tf_param);
601
602 if (shader->vgt_vertex_reuse_block_cntl)
603 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
604 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
605 shader->vgt_vertex_reuse_block_cntl);
606
607 if (initial_cdw != sctx->gfx_cs->current.cdw)
608 sctx->context_roll = true;
609 }
610
611 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
612 {
613 struct si_pm4_state *pm4;
614 unsigned num_user_sgprs;
615 unsigned vgpr_comp_cnt;
616 uint64_t va;
617 unsigned oc_lds_en;
618
619 assert(sscreen->info.chip_class <= GFX8);
620
621 pm4 = si_get_shader_pm4_state(shader);
622 if (!pm4)
623 return;
624
625 pm4->atom.emit = si_emit_shader_es;
626 va = shader->bo->gpu_address;
627 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
628
629 if (shader->selector->type == PIPE_SHADER_VERTEX) {
630 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
631 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
632 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
633 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
634 num_user_sgprs = SI_TES_NUM_USER_SGPR;
635 } else
636 unreachable("invalid shader selector type");
637
638 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
639
640 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
641 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
642 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
643 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
644 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
645 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
646 S_00B328_DX10_CLAMP(1) |
647 S_00B328_FLOAT_MODE(shader->config.float_mode));
648 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
649 S_00B32C_USER_SGPR(num_user_sgprs) |
650 S_00B32C_OC_LDS_EN(oc_lds_en) |
651 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
652
653 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
654 si_set_tesseval_regs(sscreen, shader->selector, pm4);
655
656 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
657 }
658
659 void gfx9_get_gs_info(struct si_shader_selector *es,
660 struct si_shader_selector *gs,
661 struct gfx9_gs_info *out)
662 {
663 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
664 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
665 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
666 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
667
668 /* All these are in dwords: */
669 /* We can't allow using the whole LDS, because GS waves compete with
670 * other shader stages for LDS space. */
671 const unsigned max_lds_size = 8 * 1024;
672 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
673 unsigned esgs_lds_size;
674
675 /* All these are per subgroup: */
676 const unsigned max_out_prims = 32 * 1024;
677 const unsigned max_es_verts = 255;
678 const unsigned ideal_gs_prims = 64;
679 unsigned max_gs_prims, gs_prims;
680 unsigned min_es_verts, es_verts, worst_case_es_verts;
681
682 if (uses_adjacency || gs_num_invocations > 1)
683 max_gs_prims = 127 / gs_num_invocations;
684 else
685 max_gs_prims = 255;
686
687 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
688 * Make sure we don't go over the maximum value.
689 */
690 if (gs->gs_max_out_vertices > 0) {
691 max_gs_prims = MIN2(max_gs_prims,
692 max_out_prims /
693 (gs->gs_max_out_vertices * gs_num_invocations));
694 }
695 assert(max_gs_prims > 0);
696
697 /* If the primitive has adjacency, halve the number of vertices
698 * that will be reused in multiple primitives.
699 */
700 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
701
702 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
703 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
704
705 /* Compute ESGS LDS size based on the worst case number of ES vertices
706 * needed to create the target number of GS prims per subgroup.
707 */
708 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
709
710 /* If total LDS usage is too big, refactor partitions based on ratio
711 * of ESGS item sizes.
712 */
713 if (esgs_lds_size > max_lds_size) {
714 /* Our target GS Prims Per Subgroup was too large. Calculate
715 * the maximum number of GS Prims Per Subgroup that will fit
716 * into LDS, capped by the maximum that the hardware can support.
717 */
718 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
719 max_gs_prims);
720 assert(gs_prims > 0);
721 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
722 max_es_verts);
723
724 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
725 assert(esgs_lds_size <= max_lds_size);
726 }
727
728 /* Now calculate remaining ESGS information. */
729 if (esgs_lds_size)
730 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
731 else
732 es_verts = max_es_verts;
733
734 /* Vertices for adjacency primitives are not always reused, so restore
735 * it for ES_VERTS_PER_SUBGRP.
736 */
737 min_es_verts = gs->gs_input_verts_per_prim;
738
739 /* For normal primitives, the VGT only checks if they are past the ES
740 * verts per subgroup after allocating a full GS primitive and if they
741 * are, kick off a new subgroup. But if those additional ES verts are
742 * unique (e.g. not reused) we need to make sure there is enough LDS
743 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
744 */
745 es_verts -= min_es_verts - 1;
746
747 out->es_verts_per_subgroup = es_verts;
748 out->gs_prims_per_subgroup = gs_prims;
749 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
750 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
751 gs->gs_max_out_vertices;
752 out->esgs_ring_size = 4 * esgs_lds_size;
753
754 assert(out->max_prims_per_subgroup <= max_out_prims);
755 }
756
757 static void si_emit_shader_gs(struct si_context *sctx)
758 {
759 struct si_shader *shader = sctx->queued.named.gs->shader;
760 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
761
762 if (!shader)
763 return;
764
765 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
766 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
767 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
768 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
769 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
770 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
771 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
772
773 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
774 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
775 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
776 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
777
778 /* R_028B38_VGT_GS_MAX_VERT_OUT */
779 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
780 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
781 shader->ctx_reg.gs.vgt_gs_max_vert_out);
782
783 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
784 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
785 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
786 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
787 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
788 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
789 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
790 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
791
792 /* R_028B90_VGT_GS_INSTANCE_CNT */
793 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
794 SI_TRACKED_VGT_GS_INSTANCE_CNT,
795 shader->ctx_reg.gs.vgt_gs_instance_cnt);
796
797 if (sctx->chip_class >= GFX9) {
798 /* R_028A44_VGT_GS_ONCHIP_CNTL */
799 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
800 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
801 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
802 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
803 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
804 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
805 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
806 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
807 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
808 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
809 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
810
811 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
812 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
813 SI_TRACKED_VGT_TF_PARAM,
814 shader->vgt_tf_param);
815 if (shader->vgt_vertex_reuse_block_cntl)
816 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
817 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
818 shader->vgt_vertex_reuse_block_cntl);
819 }
820
821 if (initial_cdw != sctx->gfx_cs->current.cdw)
822 sctx->context_roll = true;
823 }
824
825 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
826 {
827 struct si_shader_selector *sel = shader->selector;
828 const ubyte *num_components = sel->info.num_stream_output_components;
829 unsigned gs_num_invocations = sel->gs_num_invocations;
830 struct si_pm4_state *pm4;
831 uint64_t va;
832 unsigned max_stream = sel->max_gs_stream;
833 unsigned offset;
834
835 pm4 = si_get_shader_pm4_state(shader);
836 if (!pm4)
837 return;
838
839 pm4->atom.emit = si_emit_shader_gs;
840
841 offset = num_components[0] * sel->gs_max_out_vertices;
842 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
843
844 if (max_stream >= 1)
845 offset += num_components[1] * sel->gs_max_out_vertices;
846 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
847
848 if (max_stream >= 2)
849 offset += num_components[2] * sel->gs_max_out_vertices;
850 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
851
852 if (max_stream >= 3)
853 offset += num_components[3] * sel->gs_max_out_vertices;
854 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
855
856 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
857 assert(offset < (1 << 15));
858
859 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
860
861 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
862 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
863 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
864 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
865
866 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
867 S_028B90_ENABLE(gs_num_invocations > 0);
868
869 va = shader->bo->gpu_address;
870 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
871
872 if (sscreen->info.chip_class >= GFX9) {
873 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
874 unsigned es_type = shader->key.part.gs.es->type;
875 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
876
877 if (es_type == PIPE_SHADER_VERTEX) {
878 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
879 } else if (es_type == PIPE_SHADER_TESS_EVAL)
880 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
881 else
882 unreachable("invalid shader selector type");
883
884 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
885 * VGPR[0:4] are always loaded.
886 */
887 if (sel->info.uses_invocationid)
888 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
889 else if (sel->info.uses_primid)
890 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
891 else if (input_prim >= PIPE_PRIM_TRIANGLES)
892 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
893 else
894 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
895
896 unsigned num_user_sgprs;
897 if (es_type == PIPE_SHADER_VERTEX)
898 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
899 else
900 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
901
902 if (sscreen->info.chip_class >= GFX10) {
903 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
904 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
905 } else {
906 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
907 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
908 }
909
910 uint32_t rsrc1 =
911 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
912 S_00B228_DX10_CLAMP(1) |
913 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
914 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
915 S_00B228_FLOAT_MODE(shader->config.float_mode) |
916 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
917 uint32_t rsrc2 =
918 S_00B22C_USER_SGPR(num_user_sgprs) |
919 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
920 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
921 S_00B22C_LDS_SIZE(shader->config.lds_size) |
922 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
923
924 if (sscreen->info.chip_class >= GFX10) {
925 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
926 } else {
927 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
928 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
929 }
930
931 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
932 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
933
934 if (sscreen->info.chip_class >= GFX10) {
935 si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
936 S_00B204_CU_EN(0xffff) |
937 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0));
938 }
939
940 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
941 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
942 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
943 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
944 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
945 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
946 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
947 shader->key.part.gs.es->esgs_itemsize / 4;
948
949 if (es_type == PIPE_SHADER_TESS_EVAL)
950 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
951
952 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
953 NULL, pm4);
954 } else {
955 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
956 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
957
958 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
959 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
960 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
961 S_00B228_DX10_CLAMP(1) |
962 S_00B228_FLOAT_MODE(shader->config.float_mode));
963 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
964 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
965 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
966 }
967 }
968
969 static void gfx10_emit_ge_pc_alloc(struct si_context *sctx, unsigned value)
970 {
971 enum si_tracked_reg reg = SI_TRACKED_GE_PC_ALLOC;
972
973 if (((sctx->tracked_regs.reg_saved >> reg) & 0x1) != 0x1 ||
974 sctx->tracked_regs.reg_value[reg] != value) {
975 struct radeon_cmdbuf *cs = sctx->gfx_cs;
976
977 if (sctx->family == CHIP_NAVI10 ||
978 sctx->family == CHIP_NAVI12 ||
979 sctx->family == CHIP_NAVI14) {
980 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
981 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
982 radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
983 }
984
985 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC, value);
986
987 sctx->tracked_regs.reg_saved |= 0x1ull << reg;
988 sctx->tracked_regs.reg_value[reg] = value;
989 }
990 }
991
992 /* Common tail code for NGG primitive shaders. */
993 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
994 struct si_shader *shader,
995 unsigned initial_cdw)
996 {
997 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
998 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
999 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
1000 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
1001 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
1002 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
1003 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1004 SI_TRACKED_VGT_PRIMITIVEID_EN,
1005 shader->ctx_reg.ngg.vgt_primitiveid_en);
1006 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1007 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1008 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
1009 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
1010 SI_TRACKED_VGT_GS_INSTANCE_CNT,
1011 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
1012 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
1013 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
1014 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
1015 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1016 SI_TRACKED_SPI_VS_OUT_CONFIG,
1017 shader->ctx_reg.ngg.spi_vs_out_config);
1018 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
1019 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
1020 shader->ctx_reg.ngg.spi_shader_idx_format,
1021 shader->ctx_reg.ngg.spi_shader_pos_format);
1022 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1023 SI_TRACKED_PA_CL_VTE_CNTL,
1024 shader->ctx_reg.ngg.pa_cl_vte_cntl);
1025 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
1026 SI_TRACKED_PA_CL_NGG_CNTL,
1027 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
1028
1029 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1030 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
1031 shader->pa_cl_vs_out_cntl,
1032 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1033
1034 if (initial_cdw != sctx->gfx_cs->current.cdw)
1035 sctx->context_roll = true;
1036
1037 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1038 gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.ngg.ge_pc_alloc);
1039 }
1040
1041 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
1042 {
1043 struct si_shader *shader = sctx->queued.named.gs->shader;
1044 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1045
1046 if (!shader)
1047 return;
1048
1049 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1050 }
1051
1052 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1053 {
1054 struct si_shader *shader = sctx->queued.named.gs->shader;
1055 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1056
1057 if (!shader)
1058 return;
1059
1060 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1061 SI_TRACKED_VGT_TF_PARAM,
1062 shader->vgt_tf_param);
1063
1064 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1065 }
1066
1067 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1068 {
1069 struct si_shader *shader = sctx->queued.named.gs->shader;
1070 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1071
1072 if (!shader)
1073 return;
1074
1075 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1076 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1077 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1078
1079 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1080 }
1081
1082 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1083 {
1084 struct si_shader *shader = sctx->queued.named.gs->shader;
1085 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1086
1087 if (!shader)
1088 return;
1089
1090 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1091 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1092 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1093 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1094 SI_TRACKED_VGT_TF_PARAM,
1095 shader->vgt_tf_param);
1096
1097 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1098 }
1099
1100 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1101 {
1102 if (gs->type == PIPE_SHADER_GEOMETRY)
1103 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1104
1105 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1106 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1107 return PIPE_PRIM_POINTS;
1108 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1109 return PIPE_PRIM_LINES;
1110 return PIPE_PRIM_TRIANGLES;
1111 }
1112
1113 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1114 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1115 }
1116
1117 static unsigned si_get_vs_out_cntl(const struct si_shader_selector *sel, bool ngg)
1118 {
1119 bool misc_vec_ena =
1120 sel->info.writes_psize || (sel->info.writes_edgeflag && !ngg) ||
1121 sel->info.writes_layer || sel->info.writes_viewport_index;
1122 return S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
1123 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag && !ngg) |
1124 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
1125 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
1126 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1127 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
1128 }
1129
1130 /**
1131 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1132 * in NGG mode.
1133 */
1134 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1135 {
1136 const struct si_shader_selector *gs_sel = shader->selector;
1137 const struct si_shader_info *gs_info = &gs_sel->info;
1138 enum pipe_shader_type gs_type = shader->selector->type;
1139 const struct si_shader_selector *es_sel =
1140 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1141 const struct si_shader_info *es_info = &es_sel->info;
1142 enum pipe_shader_type es_type = es_sel->type;
1143 unsigned num_user_sgprs;
1144 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1145 uint64_t va;
1146 unsigned window_space =
1147 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1148 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1149 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1150 unsigned input_prim = si_get_input_prim(gs_sel);
1151 bool break_wave_at_eoi = false;
1152 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1153 if (!pm4)
1154 return;
1155
1156 if (es_type == PIPE_SHADER_TESS_EVAL) {
1157 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1158 : gfx10_emit_shader_ngg_tess_nogs;
1159 } else {
1160 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1161 : gfx10_emit_shader_ngg_notess_nogs;
1162 }
1163
1164 va = shader->bo->gpu_address;
1165 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1166
1167 if (es_type == PIPE_SHADER_VERTEX) {
1168 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
1169
1170 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1171 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1172 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1173 } else {
1174 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
1175 }
1176 } else {
1177 assert(es_type == PIPE_SHADER_TESS_EVAL);
1178 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1179 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1180
1181 if (es_enable_prim_id || gs_info->uses_primid)
1182 break_wave_at_eoi = true;
1183 }
1184
1185 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1186 * VGPR[0:4] are always loaded.
1187 *
1188 * Vertex shaders always need to load VGPR3, because they need to
1189 * pass edge flags for decomposed primitives (such as quads) to the PA
1190 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1191 */
1192 if (gs_info->uses_invocationid ||
1193 (gs_type == PIPE_SHADER_VERTEX && !gfx10_is_ngg_passthrough(shader)))
1194 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1195 else if ((gs_type == PIPE_SHADER_GEOMETRY && gs_info->uses_primid) ||
1196 (gs_type == PIPE_SHADER_VERTEX && shader->key.mono.u.vs_export_prim_id))
1197 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1198 else if (input_prim >= PIPE_PRIM_TRIANGLES && !gfx10_is_ngg_passthrough(shader))
1199 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1200 else
1201 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1202
1203 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1204 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1205 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1206 S_00B228_VGPRS((shader->config.num_vgprs - 1) /
1207 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1208 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1209 S_00B228_DX10_CLAMP(1) |
1210 S_00B228_MEM_ORDERED(1) |
1211 S_00B228_WGP_MODE(1) |
1212 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1213 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1214 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1215 S_00B22C_USER_SGPR(num_user_sgprs) |
1216 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1217 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1218 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1219 S_00B22C_LDS_SIZE(shader->config.lds_size));
1220
1221 /* Determine LATE_ALLOC_GS. */
1222 unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
1223 unsigned late_alloc_wave64; /* The limit is per SH. */
1224
1225 /* For Wave32, the hw will launch twice the number of late
1226 * alloc waves, so 1 == 2x wave32.
1227 *
1228 * Don't use late alloc for NGG on Navi14 due to a hw bug.
1229 */
1230 if (sscreen->info.family == CHIP_NAVI14)
1231 late_alloc_wave64 = 0;
1232 else if (num_cu_per_sh <= 6)
1233 late_alloc_wave64 = num_cu_per_sh - 2; /* All CUs enabled */
1234 else if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL)
1235 late_alloc_wave64 = (num_cu_per_sh - 2) * 6;
1236 else
1237 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
1238
1239 si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1240 S_00B204_CU_EN(0xffff) |
1241 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64));
1242
1243 nparams = MAX2(shader->info.nr_param_exports, 1);
1244 shader->ctx_reg.ngg.spi_vs_out_config =
1245 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1246 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1247
1248 shader->ctx_reg.ngg.spi_shader_idx_format =
1249 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1250 shader->ctx_reg.ngg.spi_shader_pos_format =
1251 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1252 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1253 V_02870C_SPI_SHADER_4COMP :
1254 V_02870C_SPI_SHADER_NONE) |
1255 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1256 V_02870C_SPI_SHADER_4COMP :
1257 V_02870C_SPI_SHADER_NONE) |
1258 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1259 V_02870C_SPI_SHADER_4COMP :
1260 V_02870C_SPI_SHADER_NONE);
1261
1262 shader->ctx_reg.ngg.vgt_primitiveid_en =
1263 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1264 S_028A84_NGG_DISABLE_PROVOK_REUSE(shader->key.mono.u.vs_export_prim_id ||
1265 gs_sel->info.writes_primid);
1266
1267 if (gs_type == PIPE_SHADER_GEOMETRY) {
1268 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1269 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1270 } else {
1271 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1272 }
1273
1274 if (es_type == PIPE_SHADER_TESS_EVAL)
1275 si_set_tesseval_regs(sscreen, es_sel, pm4);
1276
1277 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1278 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1279 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1280 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1281 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1282 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1283 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1284 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1285 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1286 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1287 S_028B90_CNT(gs_num_invocations) |
1288 S_028B90_ENABLE(gs_num_invocations > 1) |
1289 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1290 shader->ngg.max_vert_out_per_gs_instance);
1291
1292 /* Always output hw-generated edge flags and pass them via the prim
1293 * export to prevent drawing lines on internal edges of decomposed
1294 * primitives (such as quads) with polygon mode = lines. Only VS needs
1295 * this.
1296 */
1297 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1298 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
1299 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(gs_sel, true);
1300
1301 /* Oversubscribe PC. This improves performance when there are too many varyings. */
1302 float oversub_pc_factor = 0.25;
1303
1304 if (shader->key.opt.ngg_culling) {
1305 /* Be more aggressive with NGG culling. */
1306 if (shader->info.nr_param_exports > 4)
1307 oversub_pc_factor = 1;
1308 else if (shader->info.nr_param_exports > 2)
1309 oversub_pc_factor = 0.75;
1310 else
1311 oversub_pc_factor = 0.5;
1312 }
1313
1314 unsigned oversub_pc_lines = sscreen->info.pc_lines * oversub_pc_factor;
1315 shader->ctx_reg.ngg.ge_pc_alloc = S_030980_OVERSUB_EN(1) |
1316 S_030980_NUM_PC_LINES(oversub_pc_lines - 1);
1317
1318 if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_TRI_LIST) {
1319 shader->ge_cntl =
1320 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1321 S_03096C_VERT_GRP_SIZE(shader->ngg.max_gsprims * 3);
1322 } else if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_TRI_STRIP) {
1323 shader->ge_cntl =
1324 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1325 S_03096C_VERT_GRP_SIZE(shader->ngg.max_gsprims + 2);
1326 } else {
1327 shader->ge_cntl =
1328 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1329 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
1330 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1331
1332 /* Bug workaround for a possible hang with non-tessellation cases.
1333 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1334 *
1335 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1336 */
1337 if ((sscreen->info.family == CHIP_NAVI10 ||
1338 sscreen->info.family == CHIP_NAVI12 ||
1339 sscreen->info.family == CHIP_NAVI14) &&
1340 (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
1341 shader->ngg.hw_max_esverts != 256) {
1342 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1343
1344 if (shader->ngg.hw_max_esverts > 5) {
1345 shader->ge_cntl |=
1346 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1347 }
1348 }
1349 }
1350
1351 if (window_space) {
1352 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1353 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1354 } else {
1355 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1356 S_028818_VTX_W0_FMT(1) |
1357 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1358 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1359 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1360 }
1361 }
1362
1363 static void si_emit_shader_vs(struct si_context *sctx)
1364 {
1365 struct si_shader *shader = sctx->queued.named.vs->shader;
1366 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1367
1368 if (!shader)
1369 return;
1370
1371 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1372 SI_TRACKED_VGT_GS_MODE,
1373 shader->ctx_reg.vs.vgt_gs_mode);
1374 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1375 SI_TRACKED_VGT_PRIMITIVEID_EN,
1376 shader->ctx_reg.vs.vgt_primitiveid_en);
1377
1378 if (sctx->chip_class <= GFX8) {
1379 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1380 SI_TRACKED_VGT_REUSE_OFF,
1381 shader->ctx_reg.vs.vgt_reuse_off);
1382 }
1383
1384 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1385 SI_TRACKED_SPI_VS_OUT_CONFIG,
1386 shader->ctx_reg.vs.spi_vs_out_config);
1387
1388 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1389 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1390 shader->ctx_reg.vs.spi_shader_pos_format);
1391
1392 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1393 SI_TRACKED_PA_CL_VTE_CNTL,
1394 shader->ctx_reg.vs.pa_cl_vte_cntl);
1395
1396 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1397 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1398 SI_TRACKED_VGT_TF_PARAM,
1399 shader->vgt_tf_param);
1400
1401 if (shader->vgt_vertex_reuse_block_cntl)
1402 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1403 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1404 shader->vgt_vertex_reuse_block_cntl);
1405
1406 /* Required programming for tessellation. (legacy pipeline only) */
1407 if (sctx->chip_class == GFX10 &&
1408 shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1409 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1410 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1411 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1412 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1413 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1414 }
1415
1416 if (sctx->chip_class >= GFX10) {
1417 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1418 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
1419 shader->pa_cl_vs_out_cntl,
1420 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1421 }
1422
1423 if (initial_cdw != sctx->gfx_cs->current.cdw)
1424 sctx->context_roll = true;
1425
1426 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1427 if (sctx->chip_class >= GFX10)
1428 gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.vs.ge_pc_alloc);
1429 }
1430
1431 /**
1432 * Compute the state for \p shader, which will run as a vertex shader on the
1433 * hardware.
1434 *
1435 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1436 * is the copy shader.
1437 */
1438 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1439 struct si_shader_selector *gs)
1440 {
1441 const struct si_shader_info *info = &shader->selector->info;
1442 struct si_pm4_state *pm4;
1443 unsigned num_user_sgprs, vgpr_comp_cnt;
1444 uint64_t va;
1445 unsigned nparams, oc_lds_en;
1446 unsigned window_space =
1447 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1448 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1449
1450 pm4 = si_get_shader_pm4_state(shader);
1451 if (!pm4)
1452 return;
1453
1454 pm4->atom.emit = si_emit_shader_vs;
1455
1456 /* We always write VGT_GS_MODE in the VS state, because every switch
1457 * between different shader pipelines involving a different GS or no
1458 * GS at all involves a switch of the VS (different GS use different
1459 * copy shaders). On the other hand, when the API switches from a GS to
1460 * no GS and then back to the same GS used originally, the GS state is
1461 * not sent again.
1462 */
1463 if (!gs) {
1464 unsigned mode = V_028A40_GS_OFF;
1465
1466 /* PrimID needs GS scenario A. */
1467 if (enable_prim_id)
1468 mode = V_028A40_GS_SCENARIO_A;
1469
1470 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1471 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1472 } else {
1473 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1474 sscreen->info.chip_class);
1475 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1476 }
1477
1478 if (sscreen->info.chip_class <= GFX8) {
1479 /* Reuse needs to be set off if we write oViewport. */
1480 shader->ctx_reg.vs.vgt_reuse_off =
1481 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1482 }
1483
1484 va = shader->bo->gpu_address;
1485 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1486
1487 if (gs) {
1488 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1489 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1490 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1491 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
1492
1493 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1494 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1495 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1496 } else {
1497 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
1498 }
1499 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1500 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1501 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1502 } else
1503 unreachable("invalid shader selector type");
1504
1505 /* VS is required to export at least one param. */
1506 nparams = MAX2(shader->info.nr_param_exports, 1);
1507 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1508
1509 if (sscreen->info.chip_class >= GFX10) {
1510 shader->ctx_reg.vs.spi_vs_out_config |=
1511 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1512 }
1513
1514 shader->ctx_reg.vs.spi_shader_pos_format =
1515 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1516 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1517 V_02870C_SPI_SHADER_4COMP :
1518 V_02870C_SPI_SHADER_NONE) |
1519 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1520 V_02870C_SPI_SHADER_4COMP :
1521 V_02870C_SPI_SHADER_NONE) |
1522 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1523 V_02870C_SPI_SHADER_4COMP :
1524 V_02870C_SPI_SHADER_NONE);
1525 shader->ctx_reg.vs.ge_pc_alloc = S_030980_OVERSUB_EN(1) |
1526 S_030980_NUM_PC_LINES(sscreen->info.pc_lines / 4 - 1);
1527 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, false);
1528
1529 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1530
1531 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1532 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1533
1534 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
1535 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1536 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1537 S_00B128_DX10_CLAMP(1) |
1538 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1539 S_00B128_FLOAT_MODE(shader->config.float_mode);
1540 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1541 S_00B12C_OC_LDS_EN(oc_lds_en) |
1542 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1543
1544 if (sscreen->info.chip_class >= GFX10)
1545 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
1546 else if (sscreen->info.chip_class == GFX9)
1547 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
1548
1549 if (sscreen->info.chip_class <= GFX9)
1550 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1551
1552 if (!sscreen->use_ngg_streamout) {
1553 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1554 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1555 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1556 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1557 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1558 }
1559
1560 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1561 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1562
1563 if (window_space)
1564 shader->ctx_reg.vs.pa_cl_vte_cntl =
1565 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1566 else
1567 shader->ctx_reg.vs.pa_cl_vte_cntl =
1568 S_028818_VTX_W0_FMT(1) |
1569 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1570 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1571 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1572
1573 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1574 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1575
1576 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1577 }
1578
1579 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1580 {
1581 struct si_shader_info *info = &ps->selector->info;
1582 unsigned num_colors = !!(info->colors_read & 0x0f) +
1583 !!(info->colors_read & 0xf0);
1584 unsigned num_interp = ps->selector->info.num_inputs +
1585 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1586
1587 assert(num_interp <= 32);
1588 return MIN2(num_interp, 32);
1589 }
1590
1591 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1592 {
1593 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1594 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1595
1596 /* If the i-th target format is set, all previous target formats must
1597 * be non-zero to avoid hangs.
1598 */
1599 for (i = 0; i < num_targets; i++)
1600 if (!(value & (0xf << (i * 4))))
1601 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1602
1603 return value;
1604 }
1605
1606 static void si_emit_shader_ps(struct si_context *sctx)
1607 {
1608 struct si_shader *shader = sctx->queued.named.ps->shader;
1609 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1610
1611 if (!shader)
1612 return;
1613
1614 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1615 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1616 SI_TRACKED_SPI_PS_INPUT_ENA,
1617 shader->ctx_reg.ps.spi_ps_input_ena,
1618 shader->ctx_reg.ps.spi_ps_input_addr);
1619
1620 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1621 SI_TRACKED_SPI_BARYC_CNTL,
1622 shader->ctx_reg.ps.spi_baryc_cntl);
1623 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1624 SI_TRACKED_SPI_PS_IN_CONTROL,
1625 shader->ctx_reg.ps.spi_ps_in_control);
1626
1627 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1628 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1629 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1630 shader->ctx_reg.ps.spi_shader_z_format,
1631 shader->ctx_reg.ps.spi_shader_col_format);
1632
1633 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1634 SI_TRACKED_CB_SHADER_MASK,
1635 shader->ctx_reg.ps.cb_shader_mask);
1636
1637 if (initial_cdw != sctx->gfx_cs->current.cdw)
1638 sctx->context_roll = true;
1639 }
1640
1641 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1642 {
1643 struct si_shader_info *info = &shader->selector->info;
1644 struct si_pm4_state *pm4;
1645 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1646 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1647 uint64_t va;
1648 unsigned input_ena = shader->config.spi_ps_input_ena;
1649
1650 /* we need to enable at least one of them, otherwise we hang the GPU */
1651 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1652 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1653 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1654 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1655 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1656 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1657 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1658 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1659 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1660 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1661 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1662 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1663 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1664 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1665
1666 /* Validate interpolation optimization flags (read as implications). */
1667 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1668 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1669 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1670 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1671 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1672 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1673 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1674 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1675 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1676 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1677 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1678 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1679 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1680 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1681 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1682 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1683 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1684 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1685
1686 /* Validate cases when the optimizations are off (read as implications). */
1687 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1688 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1689 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1690 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1691 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1692 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1693
1694 pm4 = si_get_shader_pm4_state(shader);
1695 if (!pm4)
1696 return;
1697
1698 pm4->atom.emit = si_emit_shader_ps;
1699
1700 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1701 * Possible vaules:
1702 * 0 -> Position = pixel center
1703 * 1 -> Position = pixel centroid
1704 * 2 -> Position = at sample position
1705 *
1706 * From GLSL 4.5 specification, section 7.1:
1707 * "The variable gl_FragCoord is available as an input variable from
1708 * within fragment shaders and it holds the window relative coordinates
1709 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1710 * value can be for any location within the pixel, or one of the
1711 * fragment samples. The use of centroid does not further restrict
1712 * this value to be inside the current primitive."
1713 *
1714 * Meaning that centroid has no effect and we can return anything within
1715 * the pixel. Thus, return the value at sample position, because that's
1716 * the most accurate one shaders can get.
1717 */
1718 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1719
1720 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1721 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1722 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1723
1724 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1725 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1726
1727 /* Ensure that some export memory is always allocated, for two reasons:
1728 *
1729 * 1) Correctness: The hardware ignores the EXEC mask if no export
1730 * memory is allocated, so KILL and alpha test do not work correctly
1731 * without this.
1732 * 2) Performance: Every shader needs at least a NULL export, even when
1733 * it writes no color/depth output. The NULL export instruction
1734 * stalls without this setting.
1735 *
1736 * Don't add this to CB_SHADER_MASK.
1737 *
1738 * GFX10 supports pixel shaders without exports by setting both
1739 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1740 * instructions if any are present.
1741 */
1742 if ((sscreen->info.chip_class <= GFX9 ||
1743 info->uses_kill ||
1744 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1745 !spi_shader_col_format &&
1746 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1747 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1748
1749 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1750 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1751
1752 /* Set interpolation controls. */
1753 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1754 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1755
1756 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1757 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1758 shader->ctx_reg.ps.spi_shader_z_format =
1759 ac_get_spi_shader_z_format(info->writes_z,
1760 info->writes_stencil,
1761 info->writes_samplemask);
1762 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1763 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1764
1765 va = shader->bo->gpu_address;
1766 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1767 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1768 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1769
1770 uint32_t rsrc1 =
1771 S_00B028_VGPRS((shader->config.num_vgprs - 1) /
1772 (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1773 S_00B028_DX10_CLAMP(1) |
1774 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1775 S_00B028_FLOAT_MODE(shader->config.float_mode);
1776
1777 if (sscreen->info.chip_class < GFX10) {
1778 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1779 }
1780
1781 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1782 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1783 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1784 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1785 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1786 }
1787
1788 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1789 struct si_shader *shader)
1790 {
1791 switch (shader->selector->type) {
1792 case PIPE_SHADER_VERTEX:
1793 if (shader->key.as_ls)
1794 si_shader_ls(sscreen, shader);
1795 else if (shader->key.as_es)
1796 si_shader_es(sscreen, shader);
1797 else if (shader->key.as_ngg)
1798 gfx10_shader_ngg(sscreen, shader);
1799 else
1800 si_shader_vs(sscreen, shader, NULL);
1801 break;
1802 case PIPE_SHADER_TESS_CTRL:
1803 si_shader_hs(sscreen, shader);
1804 break;
1805 case PIPE_SHADER_TESS_EVAL:
1806 if (shader->key.as_es)
1807 si_shader_es(sscreen, shader);
1808 else if (shader->key.as_ngg)
1809 gfx10_shader_ngg(sscreen, shader);
1810 else
1811 si_shader_vs(sscreen, shader, NULL);
1812 break;
1813 case PIPE_SHADER_GEOMETRY:
1814 if (shader->key.as_ngg)
1815 gfx10_shader_ngg(sscreen, shader);
1816 else
1817 si_shader_gs(sscreen, shader);
1818 break;
1819 case PIPE_SHADER_FRAGMENT:
1820 si_shader_ps(sscreen, shader);
1821 break;
1822 default:
1823 assert(0);
1824 }
1825 }
1826
1827 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1828 {
1829 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1830 return sctx->queued.named.dsa->alpha_func;
1831 }
1832
1833 void si_shader_selector_key_vs(struct si_context *sctx,
1834 struct si_shader_selector *vs,
1835 struct si_shader_key *key,
1836 struct si_vs_prolog_bits *prolog_key)
1837 {
1838 if (!sctx->vertex_elements ||
1839 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
1840 return;
1841
1842 struct si_vertex_elements *elts = sctx->vertex_elements;
1843
1844 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1845 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1846 prolog_key->unpack_instance_id_from_vertex_id =
1847 sctx->prim_discard_cs_instancing;
1848
1849 /* Prefer a monolithic shader to allow scheduling divisions around
1850 * VBO loads. */
1851 if (prolog_key->instance_divisor_is_fetched)
1852 key->opt.prefer_mono = 1;
1853
1854 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1855 unsigned count_mask = (1 << count) - 1;
1856 unsigned fix = elts->fix_fetch_always & count_mask;
1857 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1858
1859 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1860 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1861 while (mask) {
1862 unsigned i = u_bit_scan(&mask);
1863 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1864 unsigned vbidx = elts->vertex_buffer_index[i];
1865 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1866 unsigned align_mask = (1 << log_hw_load_size) - 1;
1867 if (vb->buffer_offset & align_mask ||
1868 vb->stride & align_mask) {
1869 fix |= 1 << i;
1870 opencode |= 1 << i;
1871 }
1872 }
1873 }
1874
1875 while (fix) {
1876 unsigned i = u_bit_scan(&fix);
1877 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1878 }
1879 key->mono.vs_fetch_opencode = opencode;
1880 }
1881
1882 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1883 struct si_shader_selector *vs,
1884 struct si_shader_key *key)
1885 {
1886 struct si_shader_selector *ps = sctx->ps_shader.cso;
1887
1888 key->opt.clip_disable =
1889 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1890 (vs->info.clipdist_writemask ||
1891 vs->info.writes_clipvertex) &&
1892 !vs->info.culldist_writemask;
1893
1894 /* Find out if PS is disabled. */
1895 bool ps_disabled = true;
1896 if (ps) {
1897 bool ps_modifies_zs = ps->info.uses_kill ||
1898 ps->info.writes_z ||
1899 ps->info.writes_stencil ||
1900 ps->info.writes_samplemask ||
1901 sctx->queued.named.blend->alpha_to_coverage ||
1902 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1903 unsigned ps_colormask = si_get_total_colormask(sctx);
1904
1905 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1906 (!ps_colormask &&
1907 !ps_modifies_zs &&
1908 !ps->info.writes_memory);
1909 }
1910
1911 /* Find out which VS outputs aren't used by the PS. */
1912 uint64_t outputs_written = vs->outputs_written_before_ps;
1913 uint64_t inputs_read = 0;
1914
1915 /* Ignore outputs that are not passed from VS to PS. */
1916 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1917 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1918 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1919
1920 if (!ps_disabled) {
1921 inputs_read = ps->inputs_read;
1922 }
1923
1924 uint64_t linked = outputs_written & inputs_read;
1925
1926 key->opt.kill_outputs = ~linked & outputs_written;
1927 key->opt.ngg_culling = sctx->ngg_culling;
1928 }
1929
1930 /* Compute the key for the hw shader variant */
1931 static inline void si_shader_selector_key(struct pipe_context *ctx,
1932 struct si_shader_selector *sel,
1933 union si_vgt_stages_key stages_key,
1934 struct si_shader_key *key)
1935 {
1936 struct si_context *sctx = (struct si_context *)ctx;
1937
1938 memset(key, 0, sizeof(*key));
1939
1940 switch (sel->type) {
1941 case PIPE_SHADER_VERTEX:
1942 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1943
1944 if (sctx->tes_shader.cso)
1945 key->as_ls = 1;
1946 else if (sctx->gs_shader.cso) {
1947 key->as_es = 1;
1948 key->as_ngg = stages_key.u.ngg;
1949 } else {
1950 key->as_ngg = stages_key.u.ngg;
1951 si_shader_selector_key_hw_vs(sctx, sel, key);
1952
1953 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1954 key->mono.u.vs_export_prim_id = 1;
1955 }
1956 break;
1957 case PIPE_SHADER_TESS_CTRL:
1958 if (sctx->chip_class >= GFX9) {
1959 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1960 key, &key->part.tcs.ls_prolog);
1961 key->part.tcs.ls = sctx->vs_shader.cso;
1962
1963 /* When the LS VGPR fix is needed, monolithic shaders
1964 * can:
1965 * - avoid initializing EXEC in both the LS prolog
1966 * and the LS main part when !vs_needs_prolog
1967 * - remove the fixup for unused input VGPRs
1968 */
1969 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1970
1971 /* The LS output / HS input layout can be communicated
1972 * directly instead of via user SGPRs for merged LS-HS.
1973 * The LS VGPR fix prefers this too.
1974 */
1975 key->opt.prefer_mono = 1;
1976 }
1977
1978 key->part.tcs.epilog.prim_mode =
1979 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1980 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1981 sel->info.tessfactors_are_def_in_all_invocs;
1982 key->part.tcs.epilog.tes_reads_tess_factors =
1983 sctx->tes_shader.cso->info.reads_tess_factors;
1984
1985 if (sel == sctx->fixed_func_tcs_shader.cso)
1986 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1987 break;
1988 case PIPE_SHADER_TESS_EVAL:
1989 key->as_ngg = stages_key.u.ngg;
1990
1991 if (sctx->gs_shader.cso)
1992 key->as_es = 1;
1993 else {
1994 si_shader_selector_key_hw_vs(sctx, sel, key);
1995
1996 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1997 key->mono.u.vs_export_prim_id = 1;
1998 }
1999 break;
2000 case PIPE_SHADER_GEOMETRY:
2001 if (sctx->chip_class >= GFX9) {
2002 if (sctx->tes_shader.cso) {
2003 key->part.gs.es = sctx->tes_shader.cso;
2004 } else {
2005 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
2006 key, &key->part.gs.vs_prolog);
2007 key->part.gs.es = sctx->vs_shader.cso;
2008 key->part.gs.prolog.gfx9_prev_is_vs = 1;
2009 }
2010
2011 key->as_ngg = stages_key.u.ngg;
2012
2013 /* Merged ES-GS can have unbalanced wave usage.
2014 *
2015 * ES threads are per-vertex, while GS threads are
2016 * per-primitive. So without any amplification, there
2017 * are fewer GS threads than ES threads, which can result
2018 * in empty (no-op) GS waves. With too much amplification,
2019 * there are more GS threads than ES threads, which
2020 * can result in empty (no-op) ES waves.
2021 *
2022 * Non-monolithic shaders are implemented by setting EXEC
2023 * at the beginning of shader parts, and don't jump to
2024 * the end if EXEC is 0.
2025 *
2026 * Monolithic shaders use conditional blocks, so they can
2027 * jump and skip empty waves of ES or GS. So set this to
2028 * always use optimized variants, which are monolithic.
2029 */
2030 key->opt.prefer_mono = 1;
2031 }
2032 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
2033 break;
2034 case PIPE_SHADER_FRAGMENT: {
2035 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2036 struct si_state_blend *blend = sctx->queued.named.blend;
2037
2038 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
2039 sel->info.colors_written == 0x1)
2040 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
2041
2042 /* Select the shader color format based on whether
2043 * blending or alpha are needed.
2044 */
2045 key->part.ps.epilog.spi_shader_col_format =
2046 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
2047 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
2048 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
2049 sctx->framebuffer.spi_shader_col_format_blend) |
2050 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
2051 sctx->framebuffer.spi_shader_col_format_alpha) |
2052 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
2053 sctx->framebuffer.spi_shader_col_format);
2054 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
2055
2056 /* The output for dual source blending should have
2057 * the same format as the first output.
2058 */
2059 if (blend->dual_src_blend) {
2060 key->part.ps.epilog.spi_shader_col_format |=
2061 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
2062 }
2063
2064 /* If alpha-to-coverage is enabled, we have to export alpha
2065 * even if there is no color buffer.
2066 */
2067 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
2068 blend->alpha_to_coverage)
2069 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
2070
2071 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
2072 * to the range supported by the type if a channel has less
2073 * than 16 bits and the export format is 16_ABGR.
2074 */
2075 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
2076 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
2077 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
2078 }
2079
2080 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
2081 if (!key->part.ps.epilog.last_cbuf) {
2082 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
2083 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
2084 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
2085 }
2086
2087 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
2088 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
2089
2090 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
2091 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
2092
2093 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one &&
2094 rs->multisample_enable;
2095
2096 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
2097 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
2098 (is_line && rs->line_smooth)) &&
2099 sctx->framebuffer.nr_samples <= 1;
2100 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
2101
2102 if (sctx->ps_iter_samples > 1 &&
2103 sel->info.reads_samplemask) {
2104 key->part.ps.prolog.samplemask_log_ps_iter =
2105 util_logbase2(sctx->ps_iter_samples);
2106 }
2107
2108 if (rs->force_persample_interp &&
2109 rs->multisample_enable &&
2110 sctx->framebuffer.nr_samples > 1 &&
2111 sctx->ps_iter_samples > 1) {
2112 key->part.ps.prolog.force_persp_sample_interp =
2113 sel->info.uses_persp_center ||
2114 sel->info.uses_persp_centroid;
2115
2116 key->part.ps.prolog.force_linear_sample_interp =
2117 sel->info.uses_linear_center ||
2118 sel->info.uses_linear_centroid;
2119 } else if (rs->multisample_enable &&
2120 sctx->framebuffer.nr_samples > 1) {
2121 key->part.ps.prolog.bc_optimize_for_persp =
2122 sel->info.uses_persp_center &&
2123 sel->info.uses_persp_centroid;
2124 key->part.ps.prolog.bc_optimize_for_linear =
2125 sel->info.uses_linear_center &&
2126 sel->info.uses_linear_centroid;
2127 } else {
2128 /* Make sure SPI doesn't compute more than 1 pair
2129 * of (i,j), which is the optimization here. */
2130 key->part.ps.prolog.force_persp_center_interp =
2131 sel->info.uses_persp_center +
2132 sel->info.uses_persp_centroid +
2133 sel->info.uses_persp_sample > 1;
2134
2135 key->part.ps.prolog.force_linear_center_interp =
2136 sel->info.uses_linear_center +
2137 sel->info.uses_linear_centroid +
2138 sel->info.uses_linear_sample > 1;
2139
2140 if (sel->info.uses_persp_opcode_interp_sample ||
2141 sel->info.uses_linear_opcode_interp_sample)
2142 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2143 }
2144
2145 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2146
2147 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2148 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2149 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2150 struct pipe_resource *tex = cb0->texture;
2151
2152 /* 1D textures are allocated and used as 2D on GFX9. */
2153 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2154 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2155 (tex->target == PIPE_TEXTURE_1D ||
2156 tex->target == PIPE_TEXTURE_1D_ARRAY);
2157 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2158 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2159 tex->target == PIPE_TEXTURE_CUBE ||
2160 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2161 tex->target == PIPE_TEXTURE_3D;
2162 }
2163 break;
2164 }
2165 default:
2166 assert(0);
2167 }
2168
2169 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2170 memset(&key->opt, 0, sizeof(key->opt));
2171 }
2172
2173 static void si_build_shader_variant(struct si_shader *shader,
2174 int thread_index,
2175 bool low_priority)
2176 {
2177 struct si_shader_selector *sel = shader->selector;
2178 struct si_screen *sscreen = sel->screen;
2179 struct ac_llvm_compiler *compiler;
2180 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2181
2182 if (thread_index >= 0) {
2183 if (low_priority) {
2184 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2185 compiler = &sscreen->compiler_lowp[thread_index];
2186 } else {
2187 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2188 compiler = &sscreen->compiler[thread_index];
2189 }
2190 if (!debug->async)
2191 debug = NULL;
2192 } else {
2193 assert(!low_priority);
2194 compiler = shader->compiler_ctx_state.compiler;
2195 }
2196
2197 if (!compiler->passes)
2198 si_init_compiler(sscreen, compiler);
2199
2200 if (unlikely(!si_create_shader_variant(sscreen, compiler, shader, debug))) {
2201 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2202 sel->type);
2203 shader->compilation_failed = true;
2204 return;
2205 }
2206
2207 if (shader->compiler_ctx_state.is_debug_context) {
2208 FILE *f = open_memstream(&shader->shader_log,
2209 &shader->shader_log_size);
2210 if (f) {
2211 si_shader_dump(sscreen, shader, NULL, f, false);
2212 fclose(f);
2213 }
2214 }
2215
2216 si_shader_init_pm4_state(sscreen, shader);
2217 }
2218
2219 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2220 {
2221 struct si_shader *shader = (struct si_shader *)job;
2222
2223 assert(thread_index >= 0);
2224
2225 si_build_shader_variant(shader, thread_index, true);
2226 }
2227
2228 static const struct si_shader_key zeroed;
2229
2230 static bool si_check_missing_main_part(struct si_screen *sscreen,
2231 struct si_shader_selector *sel,
2232 struct si_compiler_ctx_state *compiler_state,
2233 struct si_shader_key *key)
2234 {
2235 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2236
2237 if (!*mainp) {
2238 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2239
2240 if (!main_part)
2241 return false;
2242
2243 /* We can leave the fence as permanently signaled because the
2244 * main part becomes visible globally only after it has been
2245 * compiled. */
2246 util_queue_fence_init(&main_part->ready);
2247
2248 main_part->selector = sel;
2249 main_part->key.as_es = key->as_es;
2250 main_part->key.as_ls = key->as_ls;
2251 main_part->key.as_ngg = key->as_ngg;
2252 main_part->is_monolithic = false;
2253
2254 if (!si_compile_shader(sscreen, compiler_state->compiler,
2255 main_part, &compiler_state->debug)) {
2256 FREE(main_part);
2257 return false;
2258 }
2259 *mainp = main_part;
2260 }
2261 return true;
2262 }
2263
2264 /**
2265 * Select a shader variant according to the shader key.
2266 *
2267 * \param optimized_or_none If the key describes an optimized shader variant and
2268 * the compilation isn't finished, don't select any
2269 * shader and return an error.
2270 */
2271 int si_shader_select_with_key(struct si_screen *sscreen,
2272 struct si_shader_ctx_state *state,
2273 struct si_compiler_ctx_state *compiler_state,
2274 struct si_shader_key *key,
2275 int thread_index,
2276 bool optimized_or_none)
2277 {
2278 struct si_shader_selector *sel = state->cso;
2279 struct si_shader_selector *previous_stage_sel = NULL;
2280 struct si_shader *current = state->current;
2281 struct si_shader *iter, *shader = NULL;
2282
2283 again:
2284 /* Check if we don't need to change anything.
2285 * This path is also used for most shaders that don't need multiple
2286 * variants, it will cost just a computation of the key and this
2287 * test. */
2288 if (likely(current &&
2289 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2290 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2291 if (current->is_optimized) {
2292 if (optimized_or_none)
2293 return -1;
2294
2295 memset(&key->opt, 0, sizeof(key->opt));
2296 goto current_not_ready;
2297 }
2298
2299 util_queue_fence_wait(&current->ready);
2300 }
2301
2302 return current->compilation_failed ? -1 : 0;
2303 }
2304 current_not_ready:
2305
2306 /* This must be done before the mutex is locked, because async GS
2307 * compilation calls this function too, and therefore must enter
2308 * the mutex first.
2309 *
2310 * Only wait if we are in a draw call. Don't wait if we are
2311 * in a compiler thread.
2312 */
2313 if (thread_index < 0)
2314 util_queue_fence_wait(&sel->ready);
2315
2316 simple_mtx_lock(&sel->mutex);
2317
2318 /* Find the shader variant. */
2319 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2320 /* Don't check the "current" shader. We checked it above. */
2321 if (current != iter &&
2322 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2323 simple_mtx_unlock(&sel->mutex);
2324
2325 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2326 /* If it's an optimized shader and its compilation has
2327 * been started but isn't done, use the unoptimized
2328 * shader so as not to cause a stall due to compilation.
2329 */
2330 if (iter->is_optimized) {
2331 if (optimized_or_none)
2332 return -1;
2333 memset(&key->opt, 0, sizeof(key->opt));
2334 goto again;
2335 }
2336
2337 util_queue_fence_wait(&iter->ready);
2338 }
2339
2340 if (iter->compilation_failed) {
2341 return -1; /* skip the draw call */
2342 }
2343
2344 state->current = iter;
2345 return 0;
2346 }
2347 }
2348
2349 /* Build a new shader. */
2350 shader = CALLOC_STRUCT(si_shader);
2351 if (!shader) {
2352 simple_mtx_unlock(&sel->mutex);
2353 return -ENOMEM;
2354 }
2355
2356 util_queue_fence_init(&shader->ready);
2357
2358 shader->selector = sel;
2359 shader->key = *key;
2360 shader->compiler_ctx_state = *compiler_state;
2361
2362 /* If this is a merged shader, get the first shader's selector. */
2363 if (sscreen->info.chip_class >= GFX9) {
2364 if (sel->type == PIPE_SHADER_TESS_CTRL)
2365 previous_stage_sel = key->part.tcs.ls;
2366 else if (sel->type == PIPE_SHADER_GEOMETRY)
2367 previous_stage_sel = key->part.gs.es;
2368
2369 /* We need to wait for the previous shader. */
2370 if (previous_stage_sel && thread_index < 0)
2371 util_queue_fence_wait(&previous_stage_sel->ready);
2372 }
2373
2374 bool is_pure_monolithic =
2375 sscreen->use_monolithic_shaders ||
2376 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2377
2378 /* Compile the main shader part if it doesn't exist. This can happen
2379 * if the initial guess was wrong.
2380 *
2381 * The prim discard CS doesn't need the main shader part.
2382 */
2383 if (!is_pure_monolithic &&
2384 !key->opt.vs_as_prim_discard_cs) {
2385 bool ok = true;
2386
2387 /* Make sure the main shader part is present. This is needed
2388 * for shaders that can be compiled as VS, LS, or ES, and only
2389 * one of them is compiled at creation.
2390 *
2391 * It is also needed for GS, which can be compiled as non-NGG
2392 * and NGG.
2393 *
2394 * For merged shaders, check that the starting shader's main
2395 * part is present.
2396 */
2397 if (previous_stage_sel) {
2398 struct si_shader_key shader1_key = zeroed;
2399
2400 if (sel->type == PIPE_SHADER_TESS_CTRL) {
2401 shader1_key.as_ls = 1;
2402 } else if (sel->type == PIPE_SHADER_GEOMETRY) {
2403 shader1_key.as_es = 1;
2404 shader1_key.as_ngg = key->as_ngg; /* for Wave32 vs Wave64 */
2405 } else {
2406 assert(0);
2407 }
2408
2409 simple_mtx_lock(&previous_stage_sel->mutex);
2410 ok = si_check_missing_main_part(sscreen,
2411 previous_stage_sel,
2412 compiler_state, &shader1_key);
2413 simple_mtx_unlock(&previous_stage_sel->mutex);
2414 }
2415
2416 if (ok) {
2417 ok = si_check_missing_main_part(sscreen, sel,
2418 compiler_state, key);
2419 }
2420
2421 if (!ok) {
2422 FREE(shader);
2423 simple_mtx_unlock(&sel->mutex);
2424 return -ENOMEM; /* skip the draw call */
2425 }
2426 }
2427
2428 /* Keep the reference to the 1st shader of merged shaders, so that
2429 * Gallium can't destroy it before we destroy the 2nd shader.
2430 *
2431 * Set sctx = NULL, because it's unused if we're not releasing
2432 * the shader, and we don't have any sctx here.
2433 */
2434 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2435 previous_stage_sel);
2436
2437 /* Monolithic-only shaders don't make a distinction between optimized
2438 * and unoptimized. */
2439 shader->is_monolithic =
2440 is_pure_monolithic ||
2441 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2442
2443 /* The prim discard CS is always optimized. */
2444 shader->is_optimized =
2445 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2446 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2447
2448 /* If it's an optimized shader, compile it asynchronously. */
2449 if (shader->is_optimized && thread_index < 0) {
2450 /* Compile it asynchronously. */
2451 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2452 shader, &shader->ready,
2453 si_build_shader_variant_low_priority, NULL,
2454 0);
2455
2456 /* Add only after the ready fence was reset, to guard against a
2457 * race with si_bind_XX_shader. */
2458 if (!sel->last_variant) {
2459 sel->first_variant = shader;
2460 sel->last_variant = shader;
2461 } else {
2462 sel->last_variant->next_variant = shader;
2463 sel->last_variant = shader;
2464 }
2465
2466 /* Use the default (unoptimized) shader for now. */
2467 memset(&key->opt, 0, sizeof(key->opt));
2468 simple_mtx_unlock(&sel->mutex);
2469
2470 if (sscreen->options.sync_compile)
2471 util_queue_fence_wait(&shader->ready);
2472
2473 if (optimized_or_none)
2474 return -1;
2475 goto again;
2476 }
2477
2478 /* Reset the fence before adding to the variant list. */
2479 util_queue_fence_reset(&shader->ready);
2480
2481 if (!sel->last_variant) {
2482 sel->first_variant = shader;
2483 sel->last_variant = shader;
2484 } else {
2485 sel->last_variant->next_variant = shader;
2486 sel->last_variant = shader;
2487 }
2488
2489 simple_mtx_unlock(&sel->mutex);
2490
2491 assert(!shader->is_optimized);
2492 si_build_shader_variant(shader, thread_index, false);
2493
2494 util_queue_fence_signal(&shader->ready);
2495
2496 if (!shader->compilation_failed)
2497 state->current = shader;
2498
2499 return shader->compilation_failed ? -1 : 0;
2500 }
2501
2502 static int si_shader_select(struct pipe_context *ctx,
2503 struct si_shader_ctx_state *state,
2504 union si_vgt_stages_key stages_key,
2505 struct si_compiler_ctx_state *compiler_state)
2506 {
2507 struct si_context *sctx = (struct si_context *)ctx;
2508 struct si_shader_key key;
2509
2510 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2511 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2512 &key, -1, false);
2513 }
2514
2515 static void si_parse_next_shader_property(const struct si_shader_info *info,
2516 bool streamout,
2517 struct si_shader_key *key)
2518 {
2519 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2520
2521 switch (info->processor) {
2522 case PIPE_SHADER_VERTEX:
2523 switch (next_shader) {
2524 case PIPE_SHADER_GEOMETRY:
2525 key->as_es = 1;
2526 break;
2527 case PIPE_SHADER_TESS_CTRL:
2528 case PIPE_SHADER_TESS_EVAL:
2529 key->as_ls = 1;
2530 break;
2531 default:
2532 /* If POSITION isn't written, it can only be a HW VS
2533 * if streamout is used. If streamout isn't used,
2534 * assume that it's a HW LS. (the next shader is TCS)
2535 * This heuristic is needed for separate shader objects.
2536 */
2537 if (!info->writes_position && !streamout)
2538 key->as_ls = 1;
2539 }
2540 break;
2541
2542 case PIPE_SHADER_TESS_EVAL:
2543 if (next_shader == PIPE_SHADER_GEOMETRY ||
2544 !info->writes_position)
2545 key->as_es = 1;
2546 break;
2547 }
2548 }
2549
2550 /**
2551 * Compile the main shader part or the monolithic shader as part of
2552 * si_shader_selector initialization. Since it can be done asynchronously,
2553 * there is no way to report compile failures to applications.
2554 */
2555 static void si_init_shader_selector_async(void *job, int thread_index)
2556 {
2557 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2558 struct si_screen *sscreen = sel->screen;
2559 struct ac_llvm_compiler *compiler;
2560 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2561
2562 assert(!debug->debug_message || debug->async);
2563 assert(thread_index >= 0);
2564 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2565 compiler = &sscreen->compiler[thread_index];
2566
2567 if (!compiler->passes)
2568 si_init_compiler(sscreen, compiler);
2569
2570 /* Serialize NIR to save memory. Monolithic shader variants
2571 * have to deserialize NIR before compilation.
2572 */
2573 if (sel->nir) {
2574 struct blob blob;
2575 size_t size;
2576
2577 blob_init(&blob);
2578 /* true = remove optional debugging data to increase
2579 * the likehood of getting more shader cache hits.
2580 * It also drops variable names, so we'll save more memory.
2581 */
2582 nir_serialize(&blob, sel->nir, true);
2583 blob_finish_get_buffer(&blob, &sel->nir_binary, &size);
2584 sel->nir_size = size;
2585 }
2586
2587 /* Compile the main shader part for use with a prolog and/or epilog.
2588 * If this fails, the driver will try to compile a monolithic shader
2589 * on demand.
2590 */
2591 if (!sscreen->use_monolithic_shaders) {
2592 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2593 unsigned char ir_sha1_cache_key[20];
2594
2595 if (!shader) {
2596 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2597 return;
2598 }
2599
2600 /* We can leave the fence signaled because use of the default
2601 * main part is guarded by the selector's ready fence. */
2602 util_queue_fence_init(&shader->ready);
2603
2604 shader->selector = sel;
2605 shader->is_monolithic = false;
2606 si_parse_next_shader_property(&sel->info,
2607 sel->so.num_outputs != 0,
2608 &shader->key);
2609
2610 if (sscreen->use_ngg &&
2611 (!sel->so.num_outputs || sscreen->use_ngg_streamout) &&
2612 ((sel->type == PIPE_SHADER_VERTEX && !shader->key.as_ls) ||
2613 sel->type == PIPE_SHADER_TESS_EVAL ||
2614 sel->type == PIPE_SHADER_GEOMETRY))
2615 shader->key.as_ngg = 1;
2616
2617 if (sel->nir) {
2618 si_get_ir_cache_key(sel, shader->key.as_ngg,
2619 shader->key.as_es, ir_sha1_cache_key);
2620 }
2621
2622 /* Try to load the shader from the shader cache. */
2623 simple_mtx_lock(&sscreen->shader_cache_mutex);
2624
2625 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
2626 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2627 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2628 } else {
2629 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2630
2631 /* Compile the shader if it hasn't been loaded from the cache. */
2632 if (!si_compile_shader(sscreen, compiler, shader, debug)) {
2633 FREE(shader);
2634 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2635 return;
2636 }
2637
2638 simple_mtx_lock(&sscreen->shader_cache_mutex);
2639 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
2640 shader, true);
2641 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2642 }
2643
2644 *si_get_main_shader_part(sel, &shader->key) = shader;
2645
2646 /* Unset "outputs_written" flags for outputs converted to
2647 * DEFAULT_VAL, so that later inter-shader optimizations don't
2648 * try to eliminate outputs that don't exist in the final
2649 * shader.
2650 *
2651 * This is only done if non-monolithic shaders are enabled.
2652 */
2653 if ((sel->type == PIPE_SHADER_VERTEX ||
2654 sel->type == PIPE_SHADER_TESS_EVAL) &&
2655 !shader->key.as_ls &&
2656 !shader->key.as_es) {
2657 unsigned i;
2658
2659 for (i = 0; i < sel->info.num_outputs; i++) {
2660 unsigned offset = shader->info.vs_output_param_offset[i];
2661
2662 if (offset <= AC_EXP_PARAM_OFFSET_31)
2663 continue;
2664
2665 unsigned name = sel->info.output_semantic_name[i];
2666 unsigned index = sel->info.output_semantic_index[i];
2667 unsigned id;
2668
2669 switch (name) {
2670 case TGSI_SEMANTIC_GENERIC:
2671 /* don't process indices the function can't handle */
2672 if (index >= SI_MAX_IO_GENERIC)
2673 break;
2674 /* fall through */
2675 default:
2676 id = si_shader_io_get_unique_index(name, index, true);
2677 sel->outputs_written_before_ps &= ~(1ull << id);
2678 break;
2679 case TGSI_SEMANTIC_POSITION: /* ignore these */
2680 case TGSI_SEMANTIC_PSIZE:
2681 case TGSI_SEMANTIC_CLIPVERTEX:
2682 case TGSI_SEMANTIC_EDGEFLAG:
2683 break;
2684 }
2685 }
2686 }
2687 }
2688
2689 /* The GS copy shader is always pre-compiled. */
2690 if (sel->type == PIPE_SHADER_GEOMETRY &&
2691 (!sscreen->use_ngg ||
2692 !sscreen->use_ngg_streamout || /* also for PRIMITIVES_GENERATED */
2693 sel->tess_turns_off_ngg)) {
2694 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2695 if (!sel->gs_copy_shader) {
2696 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2697 return;
2698 }
2699
2700 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2701 }
2702
2703 /* Free NIR. We only keep serialized NIR after this point. */
2704 if (sel->nir) {
2705 ralloc_free(sel->nir);
2706 sel->nir = NULL;
2707 }
2708 }
2709
2710 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2711 struct util_queue_fence *ready_fence,
2712 struct si_compiler_ctx_state *compiler_ctx_state,
2713 void *job, util_queue_execute_func execute)
2714 {
2715 util_queue_fence_init(ready_fence);
2716
2717 struct util_async_debug_callback async_debug;
2718 bool debug =
2719 (sctx->debug.debug_message && !sctx->debug.async) ||
2720 sctx->is_debug ||
2721 si_can_dump_shader(sctx->screen, processor);
2722
2723 if (debug) {
2724 u_async_debug_init(&async_debug);
2725 compiler_ctx_state->debug = async_debug.base;
2726 }
2727
2728 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2729 ready_fence, execute, NULL, 0);
2730
2731 if (debug) {
2732 util_queue_fence_wait(ready_fence);
2733 u_async_debug_drain(&async_debug, &sctx->debug);
2734 u_async_debug_cleanup(&async_debug);
2735 }
2736
2737 if (sctx->screen->options.sync_compile)
2738 util_queue_fence_wait(ready_fence);
2739 }
2740
2741 /* Return descriptor slot usage masks from the given shader info. */
2742 void si_get_active_slot_masks(const struct si_shader_info *info,
2743 uint32_t *const_and_shader_buffers,
2744 uint64_t *samplers_and_images)
2745 {
2746 unsigned start, num_shaderbufs, num_constbufs, num_images, num_msaa_images, num_samplers;
2747
2748 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2749 num_constbufs = util_last_bit(info->const_buffers_declared);
2750 /* two 8-byte images share one 16-byte slot */
2751 num_images = align(util_last_bit(info->images_declared), 2);
2752 num_msaa_images = align(util_last_bit(info->msaa_images_declared), 2);
2753 num_samplers = util_last_bit(info->samplers_declared);
2754
2755 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2756 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2757 *const_and_shader_buffers =
2758 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2759
2760 /* The layout is:
2761 * - fmask[last] ... fmask[0] go to [15-last .. 15]
2762 * - image[last] ... image[0] go to [31-last .. 31]
2763 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
2764 *
2765 * FMASKs for images are placed separately, because MSAA images are rare,
2766 * and so we can benefit from a better cache hit rate if we keep image
2767 * descriptors together.
2768 */
2769 if (num_msaa_images)
2770 num_images = SI_NUM_IMAGES + num_msaa_images; /* add FMASK descriptors */
2771
2772 start = si_get_image_slot(num_images - 1) / 2;
2773 *samplers_and_images =
2774 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2775 }
2776
2777 static void *si_create_shader_selector(struct pipe_context *ctx,
2778 const struct pipe_shader_state *state)
2779 {
2780 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2781 struct si_context *sctx = (struct si_context*)ctx;
2782 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2783 int i;
2784
2785 if (!sel)
2786 return NULL;
2787
2788 sel->screen = sscreen;
2789 sel->compiler_ctx_state.debug = sctx->debug;
2790 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2791
2792 sel->so = state->stream_output;
2793
2794 if (state->type == PIPE_SHADER_IR_TGSI) {
2795 sel->nir = tgsi_to_nir(state->tokens, ctx->screen);
2796 } else {
2797 assert(state->type == PIPE_SHADER_IR_NIR);
2798 sel->nir = state->ir.nir;
2799 }
2800
2801 si_nir_scan_shader(sel->nir, &sel->info);
2802 si_nir_adjust_driver_locations(sel->nir);
2803
2804 sel->type = sel->info.processor;
2805 p_atomic_inc(&sscreen->num_shaders_created);
2806 si_get_active_slot_masks(&sel->info,
2807 &sel->active_const_and_shader_buffers,
2808 &sel->active_samplers_and_images);
2809
2810 /* Record which streamout buffers are enabled. */
2811 for (i = 0; i < sel->so.num_outputs; i++) {
2812 sel->enabled_streamout_buffer_mask |=
2813 (1 << sel->so.output[i].output_buffer) <<
2814 (sel->so.output[i].stream * 4);
2815 }
2816
2817 sel->num_vs_inputs = sel->type == PIPE_SHADER_VERTEX &&
2818 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] ?
2819 sel->info.num_inputs : 0;
2820 sel->num_vbos_in_user_sgprs =
2821 MIN2(sel->num_vs_inputs, sscreen->num_vbos_in_user_sgprs);
2822
2823 /* The prolog is a no-op if there are no inputs. */
2824 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2825 sel->info.num_inputs &&
2826 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
2827
2828 sel->prim_discard_cs_allowed =
2829 sel->type == PIPE_SHADER_VERTEX &&
2830 !sel->info.uses_bindless_images &&
2831 !sel->info.uses_bindless_samplers &&
2832 !sel->info.writes_memory &&
2833 !sel->info.writes_viewport_index &&
2834 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2835 !sel->so.num_outputs;
2836
2837 switch (sel->type) {
2838 case PIPE_SHADER_GEOMETRY:
2839 sel->gs_output_prim =
2840 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2841
2842 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2843 sel->rast_prim = sel->gs_output_prim;
2844 if (util_rast_prim_is_triangles(sel->rast_prim))
2845 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2846
2847 sel->gs_max_out_vertices =
2848 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2849 sel->gs_num_invocations =
2850 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2851 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2852 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2853 sel->gs_max_out_vertices;
2854
2855 sel->max_gs_stream = 0;
2856 for (i = 0; i < sel->so.num_outputs; i++)
2857 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2858 sel->so.output[i].stream);
2859
2860 sel->gs_input_verts_per_prim =
2861 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2862
2863 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2864 sel->tess_turns_off_ngg =
2865 sscreen->info.chip_class == GFX10 &&
2866 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2867 break;
2868
2869 case PIPE_SHADER_TESS_CTRL:
2870 /* Always reserve space for these. */
2871 sel->patch_outputs_written |=
2872 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2873 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2874 /* fall through */
2875 case PIPE_SHADER_VERTEX:
2876 case PIPE_SHADER_TESS_EVAL:
2877 for (i = 0; i < sel->info.num_outputs; i++) {
2878 unsigned name = sel->info.output_semantic_name[i];
2879 unsigned index = sel->info.output_semantic_index[i];
2880
2881 switch (name) {
2882 case TGSI_SEMANTIC_TESSINNER:
2883 case TGSI_SEMANTIC_TESSOUTER:
2884 case TGSI_SEMANTIC_PATCH:
2885 sel->patch_outputs_written |=
2886 1ull << si_shader_io_get_unique_index_patch(name, index);
2887 break;
2888
2889 case TGSI_SEMANTIC_GENERIC:
2890 /* don't process indices the function can't handle */
2891 if (index >= SI_MAX_IO_GENERIC)
2892 break;
2893 /* fall through */
2894 default:
2895 sel->outputs_written |=
2896 1ull << si_shader_io_get_unique_index(name, index, false);
2897 sel->outputs_written_before_ps |=
2898 1ull << si_shader_io_get_unique_index(name, index, true);
2899 break;
2900 case TGSI_SEMANTIC_EDGEFLAG:
2901 break;
2902 }
2903 }
2904 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2905 sel->lshs_vertex_stride = sel->esgs_itemsize;
2906
2907 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2908 * will start on a different bank. (except for the maximum 32*16).
2909 */
2910 if (sel->lshs_vertex_stride < 32*16)
2911 sel->lshs_vertex_stride += 4;
2912
2913 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2914 * conflicts, i.e. each vertex will start at a different bank.
2915 */
2916 if (sctx->chip_class >= GFX9)
2917 sel->esgs_itemsize += 4;
2918
2919 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2920
2921 /* Only for TES: */
2922 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2923 sel->rast_prim = PIPE_PRIM_POINTS;
2924 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2925 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2926 else
2927 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2928 break;
2929
2930 case PIPE_SHADER_FRAGMENT:
2931 for (i = 0; i < sel->info.num_inputs; i++) {
2932 unsigned name = sel->info.input_semantic_name[i];
2933 unsigned index = sel->info.input_semantic_index[i];
2934
2935 switch (name) {
2936 case TGSI_SEMANTIC_GENERIC:
2937 /* don't process indices the function can't handle */
2938 if (index >= SI_MAX_IO_GENERIC)
2939 break;
2940 /* fall through */
2941 default:
2942 sel->inputs_read |=
2943 1ull << si_shader_io_get_unique_index(name, index, true);
2944 break;
2945 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2946 break;
2947 }
2948 }
2949
2950 for (i = 0; i < 8; i++)
2951 if (sel->info.colors_written & (1 << i))
2952 sel->colors_written_4bit |= 0xf << (4 * i);
2953
2954 for (i = 0; i < sel->info.num_inputs; i++) {
2955 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2956 int index = sel->info.input_semantic_index[i];
2957 sel->color_attr_index[index] = i;
2958 }
2959 }
2960 break;
2961 default:;
2962 }
2963
2964 sel->ngg_culling_allowed =
2965 sscreen->info.chip_class == GFX10 &&
2966 sscreen->info.has_dedicated_vram &&
2967 sscreen->use_ngg_culling &&
2968 /* Disallow TES by default, because TessMark results are mixed. */
2969 (sel->type == PIPE_SHADER_VERTEX ||
2970 (sscreen->always_use_ngg_culling && sel->type == PIPE_SHADER_TESS_EVAL)) &&
2971 sel->info.writes_position &&
2972 !sel->info.writes_viewport_index && /* cull only against viewport 0 */
2973 !sel->info.writes_memory &&
2974 !sel->so.num_outputs &&
2975 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] &&
2976 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
2977
2978 /* PA_CL_VS_OUT_CNTL */
2979 if (sctx->chip_class <= GFX9)
2980 sel->pa_cl_vs_out_cntl = si_get_vs_out_cntl(sel, false);
2981
2982 sel->clipdist_mask = sel->info.writes_clipvertex ?
2983 SIX_BITS : sel->info.clipdist_writemask;
2984 sel->culldist_mask = sel->info.culldist_writemask <<
2985 sel->info.num_written_clipdistance;
2986
2987 /* DB_SHADER_CONTROL */
2988 sel->db_shader_control =
2989 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2990 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2991 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2992 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2993
2994 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2995 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2996 sel->db_shader_control |=
2997 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2998 break;
2999 case TGSI_FS_DEPTH_LAYOUT_LESS:
3000 sel->db_shader_control |=
3001 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3002 break;
3003 }
3004
3005 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
3006 *
3007 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
3008 * --|-----------|------------|------------|--------------------|-------------------|-------------
3009 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
3010 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
3011 * 2 | false | true | n/a | LateZ | 1 | 0
3012 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
3013 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
3014 *
3015 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
3016 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
3017 *
3018 * Don't use ReZ without profiling !!!
3019 *
3020 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
3021 * shaders.
3022 */
3023 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
3024 /* Cases 3, 4. */
3025 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
3026 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
3027 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
3028 } else if (sel->info.writes_memory) {
3029 /* Case 2. */
3030 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
3031 S_02880C_EXEC_ON_HIER_FAIL(1);
3032 } else {
3033 /* Case 1. */
3034 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3035 }
3036
3037 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
3038 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
3039
3040 (void) simple_mtx_init(&sel->mutex, mtx_plain);
3041
3042 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
3043 &sel->compiler_ctx_state, sel,
3044 si_init_shader_selector_async);
3045 return sel;
3046 }
3047
3048 static void *si_create_shader(struct pipe_context *ctx,
3049 const struct pipe_shader_state *state)
3050 {
3051 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
3052
3053 return util_live_shader_cache_get(ctx, &sscreen->live_shader_cache, state);
3054 }
3055
3056 static void si_update_streamout_state(struct si_context *sctx)
3057 {
3058 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
3059
3060 if (!shader_with_so)
3061 return;
3062
3063 sctx->streamout.enabled_stream_buffers_mask =
3064 shader_with_so->enabled_streamout_buffer_mask;
3065 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
3066 }
3067
3068 static void si_update_clip_regs(struct si_context *sctx,
3069 struct si_shader_selector *old_hw_vs,
3070 struct si_shader *old_hw_vs_variant,
3071 struct si_shader_selector *next_hw_vs,
3072 struct si_shader *next_hw_vs_variant)
3073 {
3074 if (next_hw_vs &&
3075 (!old_hw_vs ||
3076 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
3077 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
3078 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
3079 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
3080 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
3081 !old_hw_vs_variant ||
3082 !next_hw_vs_variant ||
3083 old_hw_vs_variant->key.opt.clip_disable !=
3084 next_hw_vs_variant->key.opt.clip_disable))
3085 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3086 }
3087
3088 static void si_update_common_shader_state(struct si_context *sctx)
3089 {
3090 sctx->uses_bindless_samplers =
3091 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
3092 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
3093 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
3094 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
3095 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
3096 sctx->uses_bindless_images =
3097 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
3098 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
3099 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
3100 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
3101 si_shader_uses_bindless_images(sctx->tes_shader.cso);
3102 sctx->do_update_shaders = true;
3103 }
3104
3105 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
3106 {
3107 struct si_context *sctx = (struct si_context *)ctx;
3108 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3109 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3110 struct si_shader_selector *sel = state;
3111
3112 if (sctx->vs_shader.cso == sel)
3113 return;
3114
3115 sctx->vs_shader.cso = sel;
3116 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
3117 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] : 0;
3118
3119 if (si_update_ngg(sctx))
3120 si_shader_change_notify(sctx);
3121
3122 si_update_common_shader_state(sctx);
3123 si_update_vs_viewport_state(sctx);
3124 si_set_active_descriptors_for_shader(sctx, sel);
3125 si_update_streamout_state(sctx);
3126 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3127 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3128 }
3129
3130 static void si_update_tess_uses_prim_id(struct si_context *sctx)
3131 {
3132 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
3133 (sctx->tes_shader.cso &&
3134 sctx->tes_shader.cso->info.uses_primid) ||
3135 (sctx->tcs_shader.cso &&
3136 sctx->tcs_shader.cso->info.uses_primid) ||
3137 (sctx->gs_shader.cso &&
3138 sctx->gs_shader.cso->info.uses_primid) ||
3139 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
3140 sctx->ps_shader.cso->info.uses_primid);
3141 }
3142
3143 bool si_update_ngg(struct si_context *sctx)
3144 {
3145 if (!sctx->screen->use_ngg) {
3146 assert(!sctx->ngg);
3147 return false;
3148 }
3149
3150 bool new_ngg = true;
3151
3152 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
3153 sctx->gs_shader.cso->tess_turns_off_ngg) {
3154 new_ngg = false;
3155 } else if (!sctx->screen->use_ngg_streamout) {
3156 struct si_shader_selector *last = si_get_vs(sctx)->cso;
3157
3158 if ((last && last->so.num_outputs) ||
3159 sctx->streamout.prims_gen_query_enabled)
3160 new_ngg = false;
3161 }
3162
3163 if (new_ngg != sctx->ngg) {
3164 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3165 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3166 * pointers are set.
3167 */
3168 if ((sctx->family == CHIP_NAVI10 ||
3169 sctx->family == CHIP_NAVI12 ||
3170 sctx->family == CHIP_NAVI14) &&
3171 !new_ngg)
3172 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
3173
3174 sctx->ngg = new_ngg;
3175 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3176 return true;
3177 }
3178 return false;
3179 }
3180
3181 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3182 {
3183 struct si_context *sctx = (struct si_context *)ctx;
3184 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3185 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3186 struct si_shader_selector *sel = state;
3187 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3188 bool ngg_changed;
3189
3190 if (sctx->gs_shader.cso == sel)
3191 return;
3192
3193 sctx->gs_shader.cso = sel;
3194 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3195 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3196
3197 si_update_common_shader_state(sctx);
3198 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3199
3200 ngg_changed = si_update_ngg(sctx);
3201 if (ngg_changed || enable_changed)
3202 si_shader_change_notify(sctx);
3203 if (enable_changed) {
3204 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3205 si_update_tess_uses_prim_id(sctx);
3206 }
3207 si_update_vs_viewport_state(sctx);
3208 si_set_active_descriptors_for_shader(sctx, sel);
3209 si_update_streamout_state(sctx);
3210 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3211 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3212 }
3213
3214 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3215 {
3216 struct si_context *sctx = (struct si_context *)ctx;
3217 struct si_shader_selector *sel = state;
3218 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3219
3220 if (sctx->tcs_shader.cso == sel)
3221 return;
3222
3223 sctx->tcs_shader.cso = sel;
3224 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3225 si_update_tess_uses_prim_id(sctx);
3226
3227 si_update_common_shader_state(sctx);
3228
3229 if (enable_changed)
3230 sctx->last_tcs = NULL; /* invalidate derived tess state */
3231
3232 si_set_active_descriptors_for_shader(sctx, sel);
3233 }
3234
3235 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3236 {
3237 struct si_context *sctx = (struct si_context *)ctx;
3238 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3239 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3240 struct si_shader_selector *sel = state;
3241 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3242
3243 if (sctx->tes_shader.cso == sel)
3244 return;
3245
3246 sctx->tes_shader.cso = sel;
3247 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3248 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3249 si_update_tess_uses_prim_id(sctx);
3250
3251 si_update_common_shader_state(sctx);
3252 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3253
3254 bool ngg_changed = si_update_ngg(sctx);
3255 if (ngg_changed || enable_changed)
3256 si_shader_change_notify(sctx);
3257 if (enable_changed)
3258 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3259 si_update_vs_viewport_state(sctx);
3260 si_set_active_descriptors_for_shader(sctx, sel);
3261 si_update_streamout_state(sctx);
3262 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3263 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3264 }
3265
3266 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3267 {
3268 struct si_context *sctx = (struct si_context *)ctx;
3269 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3270 struct si_shader_selector *sel = state;
3271
3272 /* skip if supplied shader is one already in use */
3273 if (old_sel == sel)
3274 return;
3275
3276 sctx->ps_shader.cso = sel;
3277 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3278
3279 si_update_common_shader_state(sctx);
3280 if (sel) {
3281 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3282 si_update_tess_uses_prim_id(sctx);
3283
3284 if (!old_sel ||
3285 old_sel->info.colors_written != sel->info.colors_written)
3286 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3287
3288 if (sctx->screen->has_out_of_order_rast &&
3289 (!old_sel ||
3290 old_sel->info.writes_memory != sel->info.writes_memory ||
3291 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3292 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3293 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3294 }
3295 si_set_active_descriptors_for_shader(sctx, sel);
3296 si_update_ps_colorbuf0_slot(sctx);
3297 }
3298
3299 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3300 {
3301 if (shader->is_optimized) {
3302 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3303 &shader->ready);
3304 }
3305
3306 util_queue_fence_destroy(&shader->ready);
3307
3308 if (shader->pm4) {
3309 /* If destroyed shaders were not unbound, the next compiled
3310 * shader variant could get the same pointer address and so
3311 * binding it to the same shader stage would be considered
3312 * a no-op, causing random behavior.
3313 */
3314 switch (shader->selector->type) {
3315 case PIPE_SHADER_VERTEX:
3316 if (shader->key.as_ls) {
3317 assert(sctx->chip_class <= GFX8);
3318 si_pm4_delete_state(sctx, ls, shader->pm4);
3319 } else if (shader->key.as_es) {
3320 assert(sctx->chip_class <= GFX8);
3321 si_pm4_delete_state(sctx, es, shader->pm4);
3322 } else if (shader->key.as_ngg) {
3323 si_pm4_delete_state(sctx, gs, shader->pm4);
3324 } else {
3325 si_pm4_delete_state(sctx, vs, shader->pm4);
3326 }
3327 break;
3328 case PIPE_SHADER_TESS_CTRL:
3329 si_pm4_delete_state(sctx, hs, shader->pm4);
3330 break;
3331 case PIPE_SHADER_TESS_EVAL:
3332 if (shader->key.as_es) {
3333 assert(sctx->chip_class <= GFX8);
3334 si_pm4_delete_state(sctx, es, shader->pm4);
3335 } else if (shader->key.as_ngg) {
3336 si_pm4_delete_state(sctx, gs, shader->pm4);
3337 } else {
3338 si_pm4_delete_state(sctx, vs, shader->pm4);
3339 }
3340 break;
3341 case PIPE_SHADER_GEOMETRY:
3342 if (shader->is_gs_copy_shader)
3343 si_pm4_delete_state(sctx, vs, shader->pm4);
3344 else
3345 si_pm4_delete_state(sctx, gs, shader->pm4);
3346 break;
3347 case PIPE_SHADER_FRAGMENT:
3348 si_pm4_delete_state(sctx, ps, shader->pm4);
3349 break;
3350 default:;
3351 }
3352 }
3353
3354 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3355 si_shader_destroy(shader);
3356 free(shader);
3357 }
3358
3359 static void si_destroy_shader_selector(struct pipe_context *ctx, void *cso)
3360 {
3361 struct si_context *sctx = (struct si_context*)ctx;
3362 struct si_shader_selector *sel = (struct si_shader_selector *)cso;
3363 struct si_shader *p = sel->first_variant, *c;
3364 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3365 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3366 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3367 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3368 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3369 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3370 };
3371
3372 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3373
3374 if (current_shader[sel->type]->cso == sel) {
3375 current_shader[sel->type]->cso = NULL;
3376 current_shader[sel->type]->current = NULL;
3377 }
3378
3379 while (p) {
3380 c = p->next_variant;
3381 si_delete_shader(sctx, p);
3382 p = c;
3383 }
3384
3385 if (sel->main_shader_part)
3386 si_delete_shader(sctx, sel->main_shader_part);
3387 if (sel->main_shader_part_ls)
3388 si_delete_shader(sctx, sel->main_shader_part_ls);
3389 if (sel->main_shader_part_es)
3390 si_delete_shader(sctx, sel->main_shader_part_es);
3391 if (sel->main_shader_part_ngg)
3392 si_delete_shader(sctx, sel->main_shader_part_ngg);
3393 if (sel->gs_copy_shader)
3394 si_delete_shader(sctx, sel->gs_copy_shader);
3395
3396 util_queue_fence_destroy(&sel->ready);
3397 simple_mtx_destroy(&sel->mutex);
3398 ralloc_free(sel->nir);
3399 free(sel->nir_binary);
3400 free(sel);
3401 }
3402
3403 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3404 {
3405 struct si_context *sctx = (struct si_context *)ctx;
3406 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3407
3408 si_shader_selector_reference(sctx, &sel, NULL);
3409 }
3410
3411 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3412 struct si_shader *vs, unsigned name,
3413 unsigned index, unsigned interpolate)
3414 {
3415 struct si_shader_info *vsinfo = &vs->selector->info;
3416 unsigned j, offset, ps_input_cntl = 0;
3417
3418 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3419 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3420 name == TGSI_SEMANTIC_PRIMID)
3421 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3422
3423 if (name == TGSI_SEMANTIC_PCOORD ||
3424 (name == TGSI_SEMANTIC_TEXCOORD &&
3425 sctx->sprite_coord_enable & (1 << index))) {
3426 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3427 }
3428
3429 for (j = 0; j < vsinfo->num_outputs; j++) {
3430 if (name == vsinfo->output_semantic_name[j] &&
3431 index == vsinfo->output_semantic_index[j]) {
3432 offset = vs->info.vs_output_param_offset[j];
3433
3434 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3435 /* The input is loaded from parameter memory. */
3436 ps_input_cntl |= S_028644_OFFSET(offset);
3437 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3438 if (offset == AC_EXP_PARAM_UNDEFINED) {
3439 /* This can happen with depth-only rendering. */
3440 offset = 0;
3441 } else {
3442 /* The input is a DEFAULT_VAL constant. */
3443 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3444 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3445 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3446 }
3447
3448 ps_input_cntl = S_028644_OFFSET(0x20) |
3449 S_028644_DEFAULT_VAL(offset);
3450 }
3451 break;
3452 }
3453 }
3454
3455 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3456 /* PrimID is written after the last output when HW VS is used. */
3457 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3458 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3459 /* No corresponding output found, load defaults into input.
3460 * Don't set any other bits.
3461 * (FLAT_SHADE=1 completely changes behavior) */
3462 ps_input_cntl = S_028644_OFFSET(0x20);
3463 /* D3D 9 behaviour. GL is undefined */
3464 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3465 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3466 }
3467 return ps_input_cntl;
3468 }
3469
3470 static void si_emit_spi_map(struct si_context *sctx)
3471 {
3472 struct si_shader *ps = sctx->ps_shader.current;
3473 struct si_shader *vs = si_get_vs_state(sctx);
3474 struct si_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3475 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3476 unsigned spi_ps_input_cntl[32];
3477
3478 if (!ps || !ps->selector->info.num_inputs)
3479 return;
3480
3481 num_interp = si_get_ps_num_interp(ps);
3482 assert(num_interp > 0);
3483
3484 for (i = 0; i < psinfo->num_inputs; i++) {
3485 unsigned name = psinfo->input_semantic_name[i];
3486 unsigned index = psinfo->input_semantic_index[i];
3487 unsigned interpolate = psinfo->input_interpolate[i];
3488
3489 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3490 index, interpolate);
3491
3492 if (name == TGSI_SEMANTIC_COLOR) {
3493 assert(index < ARRAY_SIZE(bcol_interp));
3494 bcol_interp[index] = interpolate;
3495 }
3496 }
3497
3498 if (ps->key.part.ps.prolog.color_two_side) {
3499 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3500
3501 for (i = 0; i < 2; i++) {
3502 if (!(psinfo->colors_read & (0xf << (i * 4))))
3503 continue;
3504
3505 spi_ps_input_cntl[num_written++] =
3506 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3507
3508 }
3509 }
3510 assert(num_interp == num_written);
3511
3512 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3513 /* Dota 2: Only ~16% of SPI map updates set different values. */
3514 /* Talos: Only ~9% of SPI map updates set different values. */
3515 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3516 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3517 spi_ps_input_cntl,
3518 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3519
3520 if (initial_cdw != sctx->gfx_cs->current.cdw)
3521 sctx->context_roll = true;
3522 }
3523
3524 /**
3525 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3526 */
3527 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3528 {
3529 if (sctx->init_config_has_vgt_flush)
3530 return;
3531
3532 /* Done by Vulkan before VGT_FLUSH. */
3533 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3534 si_pm4_cmd_add(sctx->init_config,
3535 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3536 si_pm4_cmd_end(sctx->init_config, false);
3537
3538 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3539 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3540 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3541 si_pm4_cmd_end(sctx->init_config, false);
3542 sctx->init_config_has_vgt_flush = true;
3543 }
3544
3545 /* Initialize state related to ESGS / GSVS ring buffers */
3546 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3547 {
3548 struct si_shader_selector *es =
3549 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3550 struct si_shader_selector *gs = sctx->gs_shader.cso;
3551 struct si_pm4_state *pm4;
3552
3553 /* Chip constants. */
3554 unsigned num_se = sctx->screen->info.max_se;
3555 unsigned wave_size = 64;
3556 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3557 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3558 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3559 */
3560 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3561 unsigned alignment = 256 * num_se;
3562 /* The maximum size is 63.999 MB per SE. */
3563 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3564
3565 /* Calculate the minimum size. */
3566 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3567 wave_size, alignment);
3568
3569 /* These are recommended sizes, not minimum sizes. */
3570 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3571 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3572 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3573 gs->max_gsvs_emit_size;
3574
3575 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3576 esgs_ring_size = align(esgs_ring_size, alignment);
3577 gsvs_ring_size = align(gsvs_ring_size, alignment);
3578
3579 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3580 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3581
3582 /* Some rings don't have to be allocated if shaders don't use them.
3583 * (e.g. no varyings between ES and GS or GS and VS)
3584 *
3585 * GFX9 doesn't have the ESGS ring.
3586 */
3587 bool update_esgs = sctx->chip_class <= GFX8 &&
3588 esgs_ring_size &&
3589 (!sctx->esgs_ring ||
3590 sctx->esgs_ring->width0 < esgs_ring_size);
3591 bool update_gsvs = gsvs_ring_size &&
3592 (!sctx->gsvs_ring ||
3593 sctx->gsvs_ring->width0 < gsvs_ring_size);
3594
3595 if (!update_esgs && !update_gsvs)
3596 return true;
3597
3598 if (update_esgs) {
3599 pipe_resource_reference(&sctx->esgs_ring, NULL);
3600 sctx->esgs_ring =
3601 pipe_aligned_buffer_create(sctx->b.screen,
3602 SI_RESOURCE_FLAG_UNMAPPABLE,
3603 PIPE_USAGE_DEFAULT,
3604 esgs_ring_size,
3605 sctx->screen->info.pte_fragment_size);
3606 if (!sctx->esgs_ring)
3607 return false;
3608 }
3609
3610 if (update_gsvs) {
3611 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3612 sctx->gsvs_ring =
3613 pipe_aligned_buffer_create(sctx->b.screen,
3614 SI_RESOURCE_FLAG_UNMAPPABLE,
3615 PIPE_USAGE_DEFAULT,
3616 gsvs_ring_size,
3617 sctx->screen->info.pte_fragment_size);
3618 if (!sctx->gsvs_ring)
3619 return false;
3620 }
3621
3622 /* Create the "init_config_gs_rings" state. */
3623 pm4 = CALLOC_STRUCT(si_pm4_state);
3624 if (!pm4)
3625 return false;
3626
3627 if (sctx->chip_class >= GFX7) {
3628 if (sctx->esgs_ring) {
3629 assert(sctx->chip_class <= GFX8);
3630 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3631 sctx->esgs_ring->width0 / 256);
3632 }
3633 if (sctx->gsvs_ring)
3634 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3635 sctx->gsvs_ring->width0 / 256);
3636 } else {
3637 if (sctx->esgs_ring)
3638 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3639 sctx->esgs_ring->width0 / 256);
3640 if (sctx->gsvs_ring)
3641 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3642 sctx->gsvs_ring->width0 / 256);
3643 }
3644
3645 /* Set the state. */
3646 if (sctx->init_config_gs_rings)
3647 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3648 sctx->init_config_gs_rings = pm4;
3649
3650 if (!sctx->init_config_has_vgt_flush) {
3651 si_init_config_add_vgt_flush(sctx);
3652 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3653 }
3654
3655 /* Flush the context to re-emit both init_config states. */
3656 sctx->initial_gfx_cs_size = 0; /* force flush */
3657 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3658
3659 /* Set ring bindings. */
3660 if (sctx->esgs_ring) {
3661 assert(sctx->chip_class <= GFX8);
3662 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3663 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3664 true, true, 4, 64, 0);
3665 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3666 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3667 false, false, 0, 0, 0);
3668 }
3669 if (sctx->gsvs_ring) {
3670 si_set_ring_buffer(sctx, SI_RING_GSVS,
3671 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3672 false, false, 0, 0, 0);
3673 }
3674
3675 return true;
3676 }
3677
3678 static void si_shader_lock(struct si_shader *shader)
3679 {
3680 simple_mtx_lock(&shader->selector->mutex);
3681 if (shader->previous_stage_sel) {
3682 assert(shader->previous_stage_sel != shader->selector);
3683 simple_mtx_lock(&shader->previous_stage_sel->mutex);
3684 }
3685 }
3686
3687 static void si_shader_unlock(struct si_shader *shader)
3688 {
3689 if (shader->previous_stage_sel)
3690 simple_mtx_unlock(&shader->previous_stage_sel->mutex);
3691 simple_mtx_unlock(&shader->selector->mutex);
3692 }
3693
3694 /**
3695 * @returns 1 if \p sel has been updated to use a new scratch buffer
3696 * 0 if not
3697 * < 0 if there was a failure
3698 */
3699 static int si_update_scratch_buffer(struct si_context *sctx,
3700 struct si_shader *shader)
3701 {
3702 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3703
3704 if (!shader)
3705 return 0;
3706
3707 /* This shader doesn't need a scratch buffer */
3708 if (shader->config.scratch_bytes_per_wave == 0)
3709 return 0;
3710
3711 /* Prevent race conditions when updating:
3712 * - si_shader::scratch_bo
3713 * - si_shader::binary::code
3714 * - si_shader::previous_stage::binary::code.
3715 */
3716 si_shader_lock(shader);
3717
3718 /* This shader is already configured to use the current
3719 * scratch buffer. */
3720 if (shader->scratch_bo == sctx->scratch_buffer) {
3721 si_shader_unlock(shader);
3722 return 0;
3723 }
3724
3725 assert(sctx->scratch_buffer);
3726
3727 /* Replace the shader bo with a new bo that has the relocs applied. */
3728 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3729 si_shader_unlock(shader);
3730 return -1;
3731 }
3732
3733 /* Update the shader state to use the new shader bo. */
3734 si_shader_init_pm4_state(sctx->screen, shader);
3735
3736 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3737
3738 si_shader_unlock(shader);
3739 return 1;
3740 }
3741
3742 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3743 {
3744 return shader ? shader->config.scratch_bytes_per_wave : 0;
3745 }
3746
3747 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3748 {
3749 if (!sctx->tes_shader.cso)
3750 return NULL; /* tessellation disabled */
3751
3752 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3753 sctx->fixed_func_tcs_shader.current;
3754 }
3755
3756 static bool si_update_scratch_relocs(struct si_context *sctx)
3757 {
3758 struct si_shader *tcs = si_get_tcs_current(sctx);
3759 int r;
3760
3761 /* Update the shaders, so that they are using the latest scratch.
3762 * The scratch buffer may have been changed since these shaders were
3763 * last used, so we still need to try to update them, even if they
3764 * require scratch buffers smaller than the current size.
3765 */
3766 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3767 if (r < 0)
3768 return false;
3769 if (r == 1)
3770 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3771
3772 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3773 if (r < 0)
3774 return false;
3775 if (r == 1)
3776 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3777
3778 r = si_update_scratch_buffer(sctx, tcs);
3779 if (r < 0)
3780 return false;
3781 if (r == 1)
3782 si_pm4_bind_state(sctx, hs, tcs->pm4);
3783
3784 /* VS can be bound as LS, ES, or VS. */
3785 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3786 if (r < 0)
3787 return false;
3788 if (r == 1) {
3789 if (sctx->vs_shader.current->key.as_ls)
3790 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3791 else if (sctx->vs_shader.current->key.as_es)
3792 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3793 else if (sctx->vs_shader.current->key.as_ngg)
3794 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3795 else
3796 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3797 }
3798
3799 /* TES can be bound as ES or VS. */
3800 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3801 if (r < 0)
3802 return false;
3803 if (r == 1) {
3804 if (sctx->tes_shader.current->key.as_es)
3805 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3806 else if (sctx->tes_shader.current->key.as_ngg)
3807 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3808 else
3809 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3810 }
3811
3812 return true;
3813 }
3814
3815 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3816 {
3817 /* SPI_TMPRING_SIZE.WAVESIZE must be constant for each scratch buffer.
3818 * There are 2 cases to handle:
3819 *
3820 * - If the current needed size is less than the maximum seen size,
3821 * use the maximum seen size, so that WAVESIZE remains the same.
3822 *
3823 * - If the current needed size is greater than the maximum seen size,
3824 * the scratch buffer is reallocated, so we can increase WAVESIZE.
3825 *
3826 * Shaders that set SCRATCH_EN=0 don't allocate scratch space.
3827 * Otherwise, the number of waves that can use scratch is
3828 * SPI_TMPRING_SIZE.WAVES.
3829 */
3830 unsigned bytes = 0;
3831
3832 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3833 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3834 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3835
3836 if (sctx->tes_shader.cso) {
3837 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3838 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(si_get_tcs_current(sctx)));
3839 }
3840
3841 sctx->max_seen_scratch_bytes_per_wave =
3842 MAX2(sctx->max_seen_scratch_bytes_per_wave, bytes);
3843
3844 unsigned scratch_needed_size =
3845 sctx->max_seen_scratch_bytes_per_wave * sctx->scratch_waves;
3846 unsigned spi_tmpring_size;
3847
3848 if (scratch_needed_size > 0) {
3849 if (!sctx->scratch_buffer ||
3850 scratch_needed_size > sctx->scratch_buffer->b.b.width0) {
3851 /* Create a bigger scratch buffer */
3852 si_resource_reference(&sctx->scratch_buffer, NULL);
3853
3854 sctx->scratch_buffer =
3855 si_aligned_buffer_create(&sctx->screen->b,
3856 SI_RESOURCE_FLAG_UNMAPPABLE,
3857 PIPE_USAGE_DEFAULT,
3858 scratch_needed_size,
3859 sctx->screen->info.pte_fragment_size);
3860 if (!sctx->scratch_buffer)
3861 return false;
3862
3863 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3864 si_context_add_resource_size(sctx,
3865 &sctx->scratch_buffer->b.b);
3866 }
3867
3868 if (!si_update_scratch_relocs(sctx))
3869 return false;
3870 }
3871
3872 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3873 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3874 "scratch size should already be aligned correctly.");
3875
3876 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3877 S_0286E8_WAVESIZE(sctx->max_seen_scratch_bytes_per_wave >> 10);
3878 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3879 sctx->spi_tmpring_size = spi_tmpring_size;
3880 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3881 }
3882 return true;
3883 }
3884
3885 static void si_init_tess_factor_ring(struct si_context *sctx)
3886 {
3887 assert(!sctx->tess_rings);
3888 assert(((sctx->screen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
3889
3890 /* The address must be aligned to 2^19, because the shader only
3891 * receives the high 13 bits.
3892 */
3893 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3894 SI_RESOURCE_FLAG_32BIT,
3895 PIPE_USAGE_DEFAULT,
3896 sctx->screen->tess_offchip_ring_size +
3897 sctx->screen->tess_factor_ring_size,
3898 1 << 19);
3899 if (!sctx->tess_rings)
3900 return;
3901
3902 si_init_config_add_vgt_flush(sctx);
3903
3904 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3905 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3906
3907 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3908 sctx->screen->tess_offchip_ring_size;
3909
3910 /* Append these registers to the init config state. */
3911 if (sctx->chip_class >= GFX7) {
3912 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3913 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3914 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3915 factor_va >> 8);
3916 if (sctx->chip_class >= GFX10)
3917 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3918 S_030984_BASE_HI(factor_va >> 40));
3919 else if (sctx->chip_class == GFX9)
3920 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3921 S_030944_BASE_HI(factor_va >> 40));
3922 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3923 sctx->screen->vgt_hs_offchip_param);
3924 } else {
3925 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3926 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3927 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3928 factor_va >> 8);
3929 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3930 sctx->screen->vgt_hs_offchip_param);
3931 }
3932
3933 /* Flush the context to re-emit the init_config state.
3934 * This is done only once in a lifetime of a context.
3935 */
3936 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3937 sctx->initial_gfx_cs_size = 0; /* force flush */
3938 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3939 }
3940
3941 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3942 union si_vgt_stages_key key)
3943 {
3944 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3945 uint32_t stages = 0;
3946
3947 if (key.u.tess) {
3948 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3949 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3950
3951 if (key.u.gs)
3952 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3953 S_028B54_GS_EN(1);
3954 else if (key.u.ngg)
3955 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3956 else
3957 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3958 } else if (key.u.gs) {
3959 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3960 S_028B54_GS_EN(1);
3961 } else if (key.u.ngg) {
3962 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3963 }
3964
3965 if (key.u.ngg) {
3966 stages |= S_028B54_PRIMGEN_EN(1) |
3967 S_028B54_GS_FAST_LAUNCH(key.u.ngg_gs_fast_launch) |
3968 S_028B54_NGG_WAVE_ID_EN(key.u.streamout) |
3969 S_028B54_PRIMGEN_PASSTHRU_EN(key.u.ngg_passthrough);
3970 } else if (key.u.gs)
3971 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3972
3973 if (screen->info.chip_class >= GFX9)
3974 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3975
3976 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
3977 stages |= S_028B54_HS_W32_EN(1) |
3978 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3979 S_028B54_VS_W32_EN(1);
3980 }
3981
3982 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3983 return pm4;
3984 }
3985
3986 static void si_update_vgt_shader_config(struct si_context *sctx,
3987 union si_vgt_stages_key key)
3988 {
3989 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3990
3991 if (unlikely(!*pm4))
3992 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3993 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3994 }
3995
3996 bool si_update_shaders(struct si_context *sctx)
3997 {
3998 struct pipe_context *ctx = (struct pipe_context*)sctx;
3999 struct si_compiler_ctx_state compiler_state;
4000 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
4001 struct si_shader *old_vs = si_get_vs_state(sctx);
4002 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
4003 struct si_shader *old_ps = sctx->ps_shader.current;
4004 union si_vgt_stages_key key;
4005 unsigned old_spi_shader_col_format =
4006 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
4007 int r;
4008
4009 if (!sctx->compiler.passes)
4010 si_init_compiler(sctx->screen, &sctx->compiler);
4011
4012 compiler_state.compiler = &sctx->compiler;
4013 compiler_state.debug = sctx->debug;
4014 compiler_state.is_debug_context = sctx->is_debug;
4015
4016 key.index = 0;
4017
4018 if (sctx->tes_shader.cso)
4019 key.u.tess = 1;
4020 if (sctx->gs_shader.cso)
4021 key.u.gs = 1;
4022
4023 if (sctx->ngg) {
4024 key.u.ngg = 1;
4025 key.u.streamout = !!si_get_vs(sctx)->cso->so.num_outputs;
4026 }
4027
4028 /* Update TCS and TES. */
4029 if (sctx->tes_shader.cso) {
4030 if (!sctx->tess_rings) {
4031 si_init_tess_factor_ring(sctx);
4032 if (!sctx->tess_rings)
4033 return false;
4034 }
4035
4036 if (sctx->tcs_shader.cso) {
4037 r = si_shader_select(ctx, &sctx->tcs_shader, key,
4038 &compiler_state);
4039 if (r)
4040 return false;
4041 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
4042 } else {
4043 if (!sctx->fixed_func_tcs_shader.cso) {
4044 sctx->fixed_func_tcs_shader.cso =
4045 si_create_fixed_func_tcs(sctx);
4046 if (!sctx->fixed_func_tcs_shader.cso)
4047 return false;
4048 }
4049
4050 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
4051 key, &compiler_state);
4052 if (r)
4053 return false;
4054 si_pm4_bind_state(sctx, hs,
4055 sctx->fixed_func_tcs_shader.current->pm4);
4056 }
4057
4058 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
4059 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
4060 if (r)
4061 return false;
4062
4063 if (sctx->gs_shader.cso) {
4064 /* TES as ES */
4065 assert(sctx->chip_class <= GFX8);
4066 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
4067 } else if (key.u.ngg) {
4068 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
4069 } else {
4070 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
4071 }
4072 }
4073 } else {
4074 if (sctx->chip_class <= GFX8)
4075 si_pm4_bind_state(sctx, ls, NULL);
4076 si_pm4_bind_state(sctx, hs, NULL);
4077 }
4078
4079 /* Update GS. */
4080 if (sctx->gs_shader.cso) {
4081 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
4082 if (r)
4083 return false;
4084 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
4085 if (!key.u.ngg) {
4086 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
4087
4088 if (!si_update_gs_ring_buffers(sctx))
4089 return false;
4090 } else {
4091 si_pm4_bind_state(sctx, vs, NULL);
4092 }
4093 } else {
4094 if (!key.u.ngg) {
4095 si_pm4_bind_state(sctx, gs, NULL);
4096 if (sctx->chip_class <= GFX8)
4097 si_pm4_bind_state(sctx, es, NULL);
4098 }
4099 }
4100
4101 /* Update VS. */
4102 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
4103 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
4104 if (r)
4105 return false;
4106
4107 if (!key.u.tess && !key.u.gs) {
4108 if (key.u.ngg) {
4109 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
4110 si_pm4_bind_state(sctx, vs, NULL);
4111 } else {
4112 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
4113 }
4114 } else if (sctx->tes_shader.cso) {
4115 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
4116 } else {
4117 assert(sctx->gs_shader.cso);
4118 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
4119 }
4120 }
4121
4122 /* This must be done after the shader variant is selected. */
4123 if (sctx->ngg) {
4124 struct si_shader *vs = si_get_vs(sctx)->current;
4125
4126 key.u.ngg_passthrough = gfx10_is_ngg_passthrough(vs);
4127 key.u.ngg_gs_fast_launch = !!(vs->key.opt.ngg_culling &
4128 SI_NGG_CULL_GS_FAST_LAUNCH_ALL);
4129 }
4130
4131 si_update_vgt_shader_config(sctx, key);
4132
4133 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
4134 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
4135
4136 if (sctx->ps_shader.cso) {
4137 unsigned db_shader_control;
4138
4139 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
4140 if (r)
4141 return false;
4142 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
4143
4144 db_shader_control =
4145 sctx->ps_shader.cso->db_shader_control |
4146 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
4147
4148 if (si_pm4_state_changed(sctx, ps) ||
4149 si_pm4_state_changed(sctx, vs) ||
4150 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
4151 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
4152 sctx->flatshade != rs->flatshade) {
4153 sctx->sprite_coord_enable = rs->sprite_coord_enable;
4154 sctx->flatshade = rs->flatshade;
4155 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
4156 }
4157
4158 if (sctx->screen->info.rbplus_allowed &&
4159 si_pm4_state_changed(sctx, ps) &&
4160 (!old_ps ||
4161 old_spi_shader_col_format !=
4162 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
4163 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
4164
4165 if (sctx->ps_db_shader_control != db_shader_control) {
4166 sctx->ps_db_shader_control = db_shader_control;
4167 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4168 if (sctx->screen->dpbb_allowed)
4169 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
4170 }
4171
4172 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
4173 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
4174 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
4175
4176 if (sctx->chip_class == GFX6)
4177 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4178
4179 if (sctx->framebuffer.nr_samples <= 1)
4180 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
4181 }
4182 }
4183
4184 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
4185 si_pm4_state_enabled_and_changed(sctx, hs) ||
4186 si_pm4_state_enabled_and_changed(sctx, es) ||
4187 si_pm4_state_enabled_and_changed(sctx, gs) ||
4188 si_pm4_state_enabled_and_changed(sctx, vs) ||
4189 si_pm4_state_enabled_and_changed(sctx, ps)) {
4190 if (!si_update_spi_tmpring_size(sctx))
4191 return false;
4192 }
4193
4194 if (sctx->chip_class >= GFX7) {
4195 if (si_pm4_state_enabled_and_changed(sctx, ls))
4196 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
4197 else if (!sctx->queued.named.ls)
4198 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
4199
4200 if (si_pm4_state_enabled_and_changed(sctx, hs))
4201 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
4202 else if (!sctx->queued.named.hs)
4203 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
4204
4205 if (si_pm4_state_enabled_and_changed(sctx, es))
4206 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4207 else if (!sctx->queued.named.es)
4208 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4209
4210 if (si_pm4_state_enabled_and_changed(sctx, gs))
4211 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4212 else if (!sctx->queued.named.gs)
4213 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4214
4215 if (si_pm4_state_enabled_and_changed(sctx, vs))
4216 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4217 else if (!sctx->queued.named.vs)
4218 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4219
4220 if (si_pm4_state_enabled_and_changed(sctx, ps))
4221 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4222 else if (!sctx->queued.named.ps)
4223 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4224 }
4225
4226 sctx->do_update_shaders = false;
4227 return true;
4228 }
4229
4230 static void si_emit_scratch_state(struct si_context *sctx)
4231 {
4232 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4233
4234 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4235 sctx->spi_tmpring_size);
4236
4237 if (sctx->scratch_buffer) {
4238 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4239 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4240 RADEON_PRIO_SCRATCH_BUFFER);
4241 }
4242 }
4243
4244 void si_init_screen_live_shader_cache(struct si_screen *sscreen)
4245 {
4246 util_live_shader_cache_init(&sscreen->live_shader_cache,
4247 si_create_shader_selector,
4248 si_destroy_shader_selector);
4249 }
4250
4251 void si_init_shader_functions(struct si_context *sctx)
4252 {
4253 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4254 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4255
4256 sctx->b.create_vs_state = si_create_shader;
4257 sctx->b.create_tcs_state = si_create_shader;
4258 sctx->b.create_tes_state = si_create_shader;
4259 sctx->b.create_gs_state = si_create_shader;
4260 sctx->b.create_fs_state = si_create_shader;
4261
4262 sctx->b.bind_vs_state = si_bind_vs_shader;
4263 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4264 sctx->b.bind_tes_state = si_bind_tes_shader;
4265 sctx->b.bind_gs_state = si_bind_gs_shader;
4266 sctx->b.bind_fs_state = si_bind_ps_shader;
4267
4268 sctx->b.delete_vs_state = si_delete_shader_selector;
4269 sctx->b.delete_tcs_state = si_delete_shader_selector;
4270 sctx->b.delete_tes_state = si_delete_shader_selector;
4271 sctx->b.delete_gs_state = si_delete_shader_selector;
4272 sctx->b.delete_fs_state = si_delete_shader_selector;
4273 }