projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi/gfx10: generate geometry shaders for NGG
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
45 * size as integer.
46 */
47 void *si_get_ir_binary(struct si_shader_selector *sel)
48 {
49 struct blob blob;
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->tokens) {
54 ir_binary = sel->tokens;
55 ir_size = tgsi_num_tokens(sel->tokens) *
56 sizeof(struct tgsi_token);
57 } else {
58 assert(sel->nir);
59
60 blob_init(&blob);
61 nir_serialize(&blob, sel->nir);
62 ir_binary = blob.data;
63 ir_size = blob.size;
64 }
65
66 unsigned size = 4 + ir_size + sizeof(sel->so);
67 char *result = (char*)MALLOC(size);
68 if (!result)
69 return NULL;
70
71 *((uint32_t*)result) = size;
72 memcpy(result + 4, ir_binary, ir_size);
73 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
74
75 if (sel->nir)
76 blob_finish(&blob);
77
78 return result;
79 }
80
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
83 {
84 /* data may be NULL if size == 0 */
85 if (size)
86 memcpy(ptr, data, size);
87 ptr += DIV_ROUND_UP(size, 4);
88 return ptr;
89 }
90
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
93 {
94 memcpy(data, ptr, size);
95 ptr += DIV_ROUND_UP(size, 4);
96 return ptr;
97 }
98
99 /**
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
102 */
103 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
104 {
105 *ptr++ = size;
106 return write_data(ptr, data, size);
107 }
108
109 /**
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
112 */
113 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
114 {
115 *size = *ptr++;
116 assert(*data == NULL);
117 if (!*size)
118 return ptr;
119 *data = malloc(*size);
120 return read_data(ptr, *data, *size);
121 }
122
123 /**
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
125 * as integer.
126 */
127 static void *si_get_shader_binary(struct si_shader *shader)
128 {
129 /* There is always a size of data followed by the data itself. */
130 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
131 strlen(shader->binary.llvm_ir_string) + 1 : 0;
132
133 /* Refuse to allocate overly large buffers and guard against integer
134 * overflow. */
135 if (shader->binary.elf_size > UINT_MAX / 4 ||
136 llvm_ir_size > UINT_MAX / 4)
137 return NULL;
138
139 unsigned size =
140 4 + /* total size */
141 4 + /* CRC32 of the data below */
142 align(sizeof(shader->config), 4) +
143 align(sizeof(shader->info), 4) +
144 4 + align(shader->binary.elf_size, 4) +
145 4 + align(llvm_ir_size, 4);
146 void *buffer = CALLOC(1, size);
147 uint32_t *ptr = (uint32_t*)buffer;
148
149 if (!buffer)
150 return NULL;
151
152 *ptr++ = size;
153 ptr++; /* CRC32 is calculated at the end. */
154
155 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
156 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
157 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
158 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
159 assert((char *)ptr - (char *)buffer == size);
160
161 /* Compute CRC32. */
162 ptr = (uint32_t*)buffer;
163 ptr++;
164 *ptr = util_hash_crc32(ptr + 1, size - 8);
165
166 return buffer;
167 }
168
169 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
170 {
171 uint32_t *ptr = (uint32_t*)binary;
172 uint32_t size = *ptr++;
173 uint32_t crc32 = *ptr++;
174 unsigned chunk_size;
175 unsigned elf_size;
176
177 if (util_hash_crc32(ptr, size - 8) != crc32) {
178 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
179 return false;
180 }
181
182 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
183 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
184 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
185 &elf_size);
186 shader->binary.elf_size = elf_size;
187 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
188
189 return true;
190 }
191
192 /**
193 * Insert a shader into the cache. It's assumed the shader is not in the cache.
194 * Use si_shader_cache_load_shader before calling this.
195 *
196 * Returns false on failure, in which case the ir_binary should be freed.
197 */
198 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
199 struct si_shader *shader,
200 bool insert_into_disk_cache)
201 {
202 void *hw_binary;
203 struct hash_entry *entry;
204 uint8_t key[CACHE_KEY_SIZE];
205
206 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
207 if (entry)
208 return false; /* already added */
209
210 hw_binary = si_get_shader_binary(shader);
211 if (!hw_binary)
212 return false;
213
214 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
215 hw_binary) == NULL) {
216 FREE(hw_binary);
217 return false;
218 }
219
220 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
221 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
222 *((uint32_t *)ir_binary), key);
223 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
224 *((uint32_t *) hw_binary), NULL);
225 }
226
227 return true;
228 }
229
230 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
231 struct si_shader *shader)
232 {
233 struct hash_entry *entry =
234 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
235 if (!entry) {
236 if (sscreen->disk_shader_cache) {
237 unsigned char sha1[CACHE_KEY_SIZE];
238 size_t tg_size = *((uint32_t *) ir_binary);
239
240 disk_cache_compute_key(sscreen->disk_shader_cache,
241 ir_binary, tg_size, sha1);
242
243 size_t binary_size;
244 uint8_t *buffer =
245 disk_cache_get(sscreen->disk_shader_cache,
246 sha1, &binary_size);
247 if (!buffer)
248 return false;
249
250 if (binary_size < sizeof(uint32_t) ||
251 *((uint32_t*)buffer) != binary_size) {
252 /* Something has gone wrong discard the item
253 * from the cache and rebuild/link from
254 * source.
255 */
256 assert(!"Invalid radeonsi shader disk cache "
257 "item!");
258
259 disk_cache_remove(sscreen->disk_shader_cache,
260 sha1);
261 free(buffer);
262
263 return false;
264 }
265
266 if (!si_load_shader_binary(shader, buffer)) {
267 free(buffer);
268 return false;
269 }
270 free(buffer);
271
272 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
273 shader, false))
274 FREE(ir_binary);
275 } else {
276 return false;
277 }
278 } else {
279 if (si_load_shader_binary(shader, entry->data))
280 FREE(ir_binary);
281 else
282 return false;
283 }
284 p_atomic_inc(&sscreen->num_shader_cache_hits);
285 return true;
286 }
287
288 static uint32_t si_shader_cache_key_hash(const void *key)
289 {
290 /* The first dword is the key size. */
291 return util_hash_crc32(key, *(uint32_t*)key);
292 }
293
294 static bool si_shader_cache_key_equals(const void *a, const void *b)
295 {
296 uint32_t *keya = (uint32_t*)a;
297 uint32_t *keyb = (uint32_t*)b;
298
299 /* The first dword is the key size. */
300 if (*keya != *keyb)
301 return false;
302
303 return memcmp(keya, keyb, *keya) == 0;
304 }
305
306 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
307 {
308 FREE((void*)entry->key);
309 FREE(entry->data);
310 }
311
312 bool si_init_shader_cache(struct si_screen *sscreen)
313 {
314 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
315 sscreen->shader_cache =
316 _mesa_hash_table_create(NULL,
317 si_shader_cache_key_hash,
318 si_shader_cache_key_equals);
319
320 return sscreen->shader_cache != NULL;
321 }
322
323 void si_destroy_shader_cache(struct si_screen *sscreen)
324 {
325 if (sscreen->shader_cache)
326 _mesa_hash_table_destroy(sscreen->shader_cache,
327 si_destroy_shader_cache_entry);
328 mtx_destroy(&sscreen->shader_cache_mutex);
329 }
330
331 /* SHADER STATES */
332
333 static void si_set_tesseval_regs(struct si_screen *sscreen,
334 const struct si_shader_selector *tes,
335 struct si_pm4_state *pm4)
336 {
337 const struct tgsi_shader_info *info = &tes->info;
338 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
339 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
340 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
341 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
342 unsigned type, partitioning, topology, distribution_mode;
343
344 switch (tes_prim_mode) {
345 case PIPE_PRIM_LINES:
346 type = V_028B6C_TESS_ISOLINE;
347 break;
348 case PIPE_PRIM_TRIANGLES:
349 type = V_028B6C_TESS_TRIANGLE;
350 break;
351 case PIPE_PRIM_QUADS:
352 type = V_028B6C_TESS_QUAD;
353 break;
354 default:
355 assert(0);
356 return;
357 }
358
359 switch (tes_spacing) {
360 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
361 partitioning = V_028B6C_PART_FRAC_ODD;
362 break;
363 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
364 partitioning = V_028B6C_PART_FRAC_EVEN;
365 break;
366 case PIPE_TESS_SPACING_EQUAL:
367 partitioning = V_028B6C_PART_INTEGER;
368 break;
369 default:
370 assert(0);
371 return;
372 }
373
374 if (tes_point_mode)
375 topology = V_028B6C_OUTPUT_POINT;
376 else if (tes_prim_mode == PIPE_PRIM_LINES)
377 topology = V_028B6C_OUTPUT_LINE;
378 else if (tes_vertex_order_cw)
379 /* for some reason, this must be the other way around */
380 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
381 else
382 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
383
384 if (sscreen->has_distributed_tess) {
385 if (sscreen->info.family == CHIP_FIJI ||
386 sscreen->info.family >= CHIP_POLARIS10)
387 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
388 else
389 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
390 } else
391 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
392
393 assert(pm4->shader);
394 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
395 S_028B6C_PARTITIONING(partitioning) |
396 S_028B6C_TOPOLOGY(topology) |
397 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
398 }
399
400 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
401 * whether the "fractional odd" tessellation spacing is used.
402 *
403 * Possible VGT configurations and which state should set the register:
404 *
405 * Reg set in | VGT shader configuration | Value
406 * ------------------------------------------------------
407 * VS as VS | VS | 30
408 * VS as ES | ES -> GS -> VS | 30
409 * TES as VS | LS -> HS -> VS | 14 or 30
410 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
411 *
412 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
413 */
414 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
415 struct si_shader_selector *sel,
416 struct si_shader *shader,
417 struct si_pm4_state *pm4)
418 {
419 unsigned type = sel->type;
420
421 if (sscreen->info.family < CHIP_POLARIS10)
422 return;
423
424 /* VS as VS, or VS as ES: */
425 if ((type == PIPE_SHADER_VERTEX &&
426 (!shader ||
427 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
428 /* TES as VS, or TES as ES: */
429 type == PIPE_SHADER_TESS_EVAL) {
430 unsigned vtx_reuse_depth = 30;
431
432 if (type == PIPE_SHADER_TESS_EVAL &&
433 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
434 PIPE_TESS_SPACING_FRACTIONAL_ODD)
435 vtx_reuse_depth = 14;
436
437 assert(pm4->shader);
438 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
439 }
440 }
441
442 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
443 {
444 if (shader->pm4)
445 si_pm4_clear_state(shader->pm4);
446 else
447 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
448
449 if (shader->pm4) {
450 shader->pm4->shader = shader;
451 return shader->pm4;
452 } else {
453 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
454 return NULL;
455 }
456 }
457
458 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
459 {
460 /* Add the pointer to VBO descriptors. */
461 return num_always_on_user_sgprs + 1;
462 }
463
464 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
465 {
466 struct si_pm4_state *pm4;
467 unsigned vgpr_comp_cnt;
468 uint64_t va;
469
470 assert(sscreen->info.chip_class <= GFX8);
471
472 pm4 = si_get_shader_pm4_state(shader);
473 if (!pm4)
474 return;
475
476 va = shader->bo->gpu_address;
477 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
478
479 /* We need at least 2 components for LS.
480 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
481 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
482 */
483 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
484
485 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
486 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
487
488 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
489 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
490 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
491 S_00B528_DX10_CLAMP(1) |
492 S_00B528_FLOAT_MODE(shader->config.float_mode);
493 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
494 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
495 }
496
497 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
498 {
499 struct si_pm4_state *pm4;
500 uint64_t va;
501 unsigned ls_vgpr_comp_cnt = 0;
502
503 pm4 = si_get_shader_pm4_state(shader);
504 if (!pm4)
505 return;
506
507 va = shader->bo->gpu_address;
508 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
509
510 if (sscreen->info.chip_class >= GFX9) {
511 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
512 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
513
514 /* We need at least 2 components for LS.
515 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
516 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
517 */
518 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
519
520 unsigned num_user_sgprs =
521 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
522
523 shader->config.rsrc2 =
524 S_00B42C_USER_SGPR(num_user_sgprs) |
525 S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5) |
526 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
527 } else {
528 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
529 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
530
531 shader->config.rsrc2 =
532 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
533 S_00B42C_OC_LDS_EN(1) |
534 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
535 }
536
537 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
538 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
539 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
540 S_00B428_DX10_CLAMP(1) |
541 S_00B428_FLOAT_MODE(shader->config.float_mode) |
542 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
543
544 if (sscreen->info.chip_class <= GFX8) {
545 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
546 shader->config.rsrc2);
547 }
548 }
549
550 static void si_emit_shader_es(struct si_context *sctx)
551 {
552 struct si_shader *shader = sctx->queued.named.es->shader;
553 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
554
555 if (!shader)
556 return;
557
558 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
559 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
560 shader->selector->esgs_itemsize / 4);
561
562 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
563 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
564 SI_TRACKED_VGT_TF_PARAM,
565 shader->vgt_tf_param);
566
567 if (shader->vgt_vertex_reuse_block_cntl)
568 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
569 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
570 shader->vgt_vertex_reuse_block_cntl);
571
572 if (initial_cdw != sctx->gfx_cs->current.cdw)
573 sctx->context_roll = true;
574 }
575
576 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
577 {
578 struct si_pm4_state *pm4;
579 unsigned num_user_sgprs;
580 unsigned vgpr_comp_cnt;
581 uint64_t va;
582 unsigned oc_lds_en;
583
584 assert(sscreen->info.chip_class <= GFX8);
585
586 pm4 = si_get_shader_pm4_state(shader);
587 if (!pm4)
588 return;
589
590 pm4->atom.emit = si_emit_shader_es;
591 va = shader->bo->gpu_address;
592 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
593
594 if (shader->selector->type == PIPE_SHADER_VERTEX) {
595 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
596 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
597 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
598 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
599 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
600 num_user_sgprs = SI_TES_NUM_USER_SGPR;
601 } else
602 unreachable("invalid shader selector type");
603
604 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
605
606 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
607 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
608 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
609 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
610 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
611 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
612 S_00B328_DX10_CLAMP(1) |
613 S_00B328_FLOAT_MODE(shader->config.float_mode));
614 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
615 S_00B32C_USER_SGPR(num_user_sgprs) |
616 S_00B32C_OC_LDS_EN(oc_lds_en) |
617 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
618
619 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
620 si_set_tesseval_regs(sscreen, shader->selector, pm4);
621
622 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
623 }
624
625 static unsigned si_conv_prim_to_gs_out(unsigned mode)
626 {
627 static const int prim_conv[] = {
628 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
629 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
630 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
631 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
632 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
633 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
634 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
635 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
636 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
637 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
638 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
639 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
640 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
641 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
642 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
643 };
644 assert(mode < ARRAY_SIZE(prim_conv));
645
646 return prim_conv[mode];
647 }
648
649 void gfx9_get_gs_info(struct si_shader_selector *es,
650 struct si_shader_selector *gs,
651 struct gfx9_gs_info *out)
652 {
653 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
654 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
655 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
656 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
657
658 /* All these are in dwords: */
659 /* We can't allow using the whole LDS, because GS waves compete with
660 * other shader stages for LDS space. */
661 const unsigned max_lds_size = 8 * 1024;
662 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
663 unsigned esgs_lds_size;
664
665 /* All these are per subgroup: */
666 const unsigned max_out_prims = 32 * 1024;
667 const unsigned max_es_verts = 255;
668 const unsigned ideal_gs_prims = 64;
669 unsigned max_gs_prims, gs_prims;
670 unsigned min_es_verts, es_verts, worst_case_es_verts;
671
672 if (uses_adjacency || gs_num_invocations > 1)
673 max_gs_prims = 127 / gs_num_invocations;
674 else
675 max_gs_prims = 255;
676
677 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
678 * Make sure we don't go over the maximum value.
679 */
680 if (gs->gs_max_out_vertices > 0) {
681 max_gs_prims = MIN2(max_gs_prims,
682 max_out_prims /
683 (gs->gs_max_out_vertices * gs_num_invocations));
684 }
685 assert(max_gs_prims > 0);
686
687 /* If the primitive has adjacency, halve the number of vertices
688 * that will be reused in multiple primitives.
689 */
690 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
691
692 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
693 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
694
695 /* Compute ESGS LDS size based on the worst case number of ES vertices
696 * needed to create the target number of GS prims per subgroup.
697 */
698 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
699
700 /* If total LDS usage is too big, refactor partitions based on ratio
701 * of ESGS item sizes.
702 */
703 if (esgs_lds_size > max_lds_size) {
704 /* Our target GS Prims Per Subgroup was too large. Calculate
705 * the maximum number of GS Prims Per Subgroup that will fit
706 * into LDS, capped by the maximum that the hardware can support.
707 */
708 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
709 max_gs_prims);
710 assert(gs_prims > 0);
711 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
712 max_es_verts);
713
714 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
715 assert(esgs_lds_size <= max_lds_size);
716 }
717
718 /* Now calculate remaining ESGS information. */
719 if (esgs_lds_size)
720 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
721 else
722 es_verts = max_es_verts;
723
724 /* Vertices for adjacency primitives are not always reused, so restore
725 * it for ES_VERTS_PER_SUBGRP.
726 */
727 min_es_verts = gs->gs_input_verts_per_prim;
728
729 /* For normal primitives, the VGT only checks if they are past the ES
730 * verts per subgroup after allocating a full GS primitive and if they
731 * are, kick off a new subgroup. But if those additional ES verts are
732 * unique (e.g. not reused) we need to make sure there is enough LDS
733 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
734 */
735 es_verts -= min_es_verts - 1;
736
737 out->es_verts_per_subgroup = es_verts;
738 out->gs_prims_per_subgroup = gs_prims;
739 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
740 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
741 gs->gs_max_out_vertices;
742 out->esgs_ring_size = 4 * esgs_lds_size;
743
744 assert(out->max_prims_per_subgroup <= max_out_prims);
745 }
746
747 static void si_emit_shader_gs(struct si_context *sctx)
748 {
749 struct si_shader *shader = sctx->queued.named.gs->shader;
750 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
751
752 if (!shader)
753 return;
754
755 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
756 * R_028A68_VGT_GSVS_RING_OFFSET_3, R_028A6C_VGT_GS_OUT_PRIM_TYPE */
757 radeon_opt_set_context_reg4(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
758 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
759 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
760 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
761 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3,
762 shader->ctx_reg.gs.vgt_gs_out_prim_type);
763
764
765 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
766 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
767 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
768 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
769
770 /* R_028B38_VGT_GS_MAX_VERT_OUT */
771 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
772 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
773 shader->ctx_reg.gs.vgt_gs_max_vert_out);
774
775 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
776 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
777 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
778 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
779 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
780 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
781 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
782 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
783
784 /* R_028B90_VGT_GS_INSTANCE_CNT */
785 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
786 SI_TRACKED_VGT_GS_INSTANCE_CNT,
787 shader->ctx_reg.gs.vgt_gs_instance_cnt);
788
789 if (sctx->chip_class >= GFX9) {
790 /* R_028A44_VGT_GS_ONCHIP_CNTL */
791 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
792 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
793 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
794 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
795 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
796 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
797 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
798 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
799 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
800 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
801 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
802
803 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
804 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
805 SI_TRACKED_VGT_TF_PARAM,
806 shader->vgt_tf_param);
807 if (shader->vgt_vertex_reuse_block_cntl)
808 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
809 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
810 shader->vgt_vertex_reuse_block_cntl);
811 }
812
813 if (initial_cdw != sctx->gfx_cs->current.cdw)
814 sctx->context_roll = true;
815 }
816
817 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
818 {
819 struct si_shader_selector *sel = shader->selector;
820 const ubyte *num_components = sel->info.num_stream_output_components;
821 unsigned gs_num_invocations = sel->gs_num_invocations;
822 struct si_pm4_state *pm4;
823 uint64_t va;
824 unsigned max_stream = sel->max_gs_stream;
825 unsigned offset;
826
827 pm4 = si_get_shader_pm4_state(shader);
828 if (!pm4)
829 return;
830
831 pm4->atom.emit = si_emit_shader_gs;
832
833 offset = num_components[0] * sel->gs_max_out_vertices;
834 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
835
836 if (max_stream >= 1)
837 offset += num_components[1] * sel->gs_max_out_vertices;
838 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
839
840 if (max_stream >= 2)
841 offset += num_components[2] * sel->gs_max_out_vertices;
842 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
843
844 shader->ctx_reg.gs.vgt_gs_out_prim_type =
845 si_conv_prim_to_gs_out(sel->gs_output_prim);
846
847 if (max_stream >= 3)
848 offset += num_components[3] * sel->gs_max_out_vertices;
849 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
850
851 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
852 assert(offset < (1 << 15));
853
854 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
855
856 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
857 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
858 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
859 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
860
861 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
862 S_028B90_ENABLE(gs_num_invocations > 0);
863
864 va = shader->bo->gpu_address;
865 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
866
867 if (sscreen->info.chip_class >= GFX9) {
868 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
869 unsigned es_type = shader->key.part.gs.es->type;
870 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
871
872 if (es_type == PIPE_SHADER_VERTEX)
873 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
874 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
875 else if (es_type == PIPE_SHADER_TESS_EVAL)
876 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
877 else
878 unreachable("invalid shader selector type");
879
880 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
881 * VGPR[0:4] are always loaded.
882 */
883 if (sel->info.uses_invocationid)
884 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
885 else if (sel->info.uses_primid)
886 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
887 else if (input_prim >= PIPE_PRIM_TRIANGLES)
888 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
889 else
890 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
891
892 unsigned num_user_sgprs;
893 if (es_type == PIPE_SHADER_VERTEX)
894 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
895 else
896 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
897
898 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
899 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
900
901 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
902 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
903 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
904 S_00B228_DX10_CLAMP(1) |
905 S_00B228_FLOAT_MODE(shader->config.float_mode) |
906 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
907 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
908 S_00B22C_USER_SGPR(num_user_sgprs) |
909 S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5) |
910 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
911 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
912 S_00B22C_LDS_SIZE(shader->config.lds_size) |
913 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
914
915 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
916 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
917 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
918 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
919 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
920 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
921 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
922 shader->key.part.gs.es->esgs_itemsize / 4;
923
924 if (es_type == PIPE_SHADER_TESS_EVAL)
925 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
926
927 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
928 NULL, pm4);
929 } else {
930 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
931 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
932
933 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
934 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
935 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
936 S_00B228_DX10_CLAMP(1) |
937 S_00B228_FLOAT_MODE(shader->config.float_mode));
938 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
939 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
940 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
941 }
942 }
943
944 /* Common tail code for NGG primitive shaders. */
945 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
946 struct si_shader *shader,
947 unsigned initial_cdw)
948 {
949 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
950 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
951 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
952 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
953 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
954 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
955 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
956 SI_TRACKED_VGT_PRIMITIVEID_EN,
957 shader->ctx_reg.ngg.vgt_primitiveid_en);
958 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
959 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
960 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
961 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
962 SI_TRACKED_VGT_GS_INSTANCE_CNT,
963 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
964 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
965 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
966 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
967 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
968 SI_TRACKED_VGT_REUSE_OFF,
969 shader->ctx_reg.ngg.vgt_reuse_off);
970 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
971 SI_TRACKED_SPI_VS_OUT_CONFIG,
972 shader->ctx_reg.ngg.spi_vs_out_config);
973 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
974 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
975 shader->ctx_reg.ngg.spi_shader_idx_format,
976 shader->ctx_reg.ngg.spi_shader_pos_format);
977 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
978 SI_TRACKED_PA_CL_VTE_CNTL,
979 shader->ctx_reg.ngg.pa_cl_vte_cntl);
980
981 if (initial_cdw != sctx->gfx_cs->current.cdw)
982 sctx->context_roll = true;
983
984 if (shader->ge_cntl != sctx->last_multi_vgt_param) {
985 radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, shader->ge_cntl);
986 sctx->last_multi_vgt_param = shader->ge_cntl;
987 }
988 }
989
990 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
991 {
992 struct si_shader *shader = sctx->queued.named.gs->shader;
993 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
994
995 if (!shader)
996 return;
997
998 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
999 }
1000
1001 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1002 {
1003 struct si_shader *shader = sctx->queued.named.gs->shader;
1004 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1005
1006 if (!shader)
1007 return;
1008
1009 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1010 SI_TRACKED_VGT_TF_PARAM,
1011 shader->vgt_tf_param);
1012
1013 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1014 }
1015
1016 /**
1017 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1018 * in NGG mode.
1019 */
1020 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1021 {
1022 const struct tgsi_shader_info *info = &shader->selector->info;
1023 enum pipe_shader_type es_type = shader->selector->type;
1024 unsigned num_user_sgprs;
1025 unsigned nparams, es_vgpr_comp_cnt;
1026 uint64_t va;
1027 unsigned window_space =
1028 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1029 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1030 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1031 if (!pm4)
1032 return;
1033
1034 pm4->atom.emit = es_type == PIPE_SHADER_TESS_EVAL ? gfx10_emit_shader_ngg_tess_nogs
1035 : gfx10_emit_shader_ngg_notess_nogs;
1036
1037 va = shader->bo->gpu_address;
1038 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1039
1040 if (es_type == PIPE_SHADER_VERTEX) {
1041 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1042 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
1043
1044 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1045 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1046 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1047 } else {
1048 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1049 }
1050 } else {
1051 assert(es_type == PIPE_SHADER_TESS_EVAL);
1052 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1053 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1054 }
1055
1056 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1057 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1058 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1059 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
1060 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1061 S_00B228_DX10_CLAMP(1) |
1062 S_00B228_GS_VGPR_COMP_CNT(3));
1063 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1064 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1065 S_00B22C_USER_SGPR(num_user_sgprs) |
1066 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1067 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5));
1068
1069 /* TODO: Use NO_PC_EXPORT when applicable. */
1070 nparams = MAX2(shader->info.nr_param_exports, 1);
1071 shader->ctx_reg.ngg.spi_vs_out_config =
1072 S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1073
1074 shader->ctx_reg.ngg.spi_shader_idx_format =
1075 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1076 shader->ctx_reg.ngg.spi_shader_pos_format =
1077 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1078 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1079 V_02870C_SPI_SHADER_4COMP :
1080 V_02870C_SPI_SHADER_NONE) |
1081 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1082 V_02870C_SPI_SHADER_4COMP :
1083 V_02870C_SPI_SHADER_NONE) |
1084 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1085 V_02870C_SPI_SHADER_4COMP :
1086 V_02870C_SPI_SHADER_NONE);
1087
1088 shader->ctx_reg.ngg.vgt_primitiveid_en =
1089 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1090 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id);
1091
1092 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1093
1094 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1095 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1096
1097 uint32_t es_verts_per_subgrp = 252;
1098 uint32_t gs_prims_per_subgrp = 255;
1099 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1100 S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgrp) |
1101 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgrp) |
1102 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_prims_per_subgrp);
1103 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1104 S_0287FC_MAX_VERTS_PER_SUBGROUP(es_verts_per_subgrp);
1105 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1106 S_028B4C_PRIM_AMP_FACTOR(1) |
1107 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1108 shader->ge_cntl =
1109 S_03096C_PRIM_GRP_SIZE(gs_prims_per_subgrp) |
1110 S_03096C_VERT_GRP_SIZE(es_verts_per_subgrp);
1111
1112 if (window_space) {
1113 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1114 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1115 } else {
1116 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1117 S_028818_VTX_W0_FMT(1) |
1118 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1119 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1120 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1121 }
1122
1123 shader->ctx_reg.ngg.vgt_reuse_off =
1124 S_028AB4_REUSE_OFF(sscreen->info.family == CHIP_NAVI10 &&
1125 sscreen->info.chip_external_rev == 0x1 &&
1126 es_type == PIPE_SHADER_TESS_EVAL);
1127 }
1128
1129 static void si_emit_shader_vs(struct si_context *sctx)
1130 {
1131 struct si_shader *shader = sctx->queued.named.vs->shader;
1132 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1133
1134 if (!shader)
1135 return;
1136
1137 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1138 SI_TRACKED_VGT_GS_MODE,
1139 shader->ctx_reg.vs.vgt_gs_mode);
1140 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1141 SI_TRACKED_VGT_PRIMITIVEID_EN,
1142 shader->ctx_reg.vs.vgt_primitiveid_en);
1143
1144 if (sctx->chip_class <= GFX8) {
1145 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1146 SI_TRACKED_VGT_REUSE_OFF,
1147 shader->ctx_reg.vs.vgt_reuse_off);
1148 }
1149
1150 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1151 SI_TRACKED_SPI_VS_OUT_CONFIG,
1152 shader->ctx_reg.vs.spi_vs_out_config);
1153
1154 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1155 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1156 shader->ctx_reg.vs.spi_shader_pos_format);
1157
1158 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1159 SI_TRACKED_PA_CL_VTE_CNTL,
1160 shader->ctx_reg.vs.pa_cl_vte_cntl);
1161
1162 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1163 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1164 SI_TRACKED_VGT_TF_PARAM,
1165 shader->vgt_tf_param);
1166
1167 if (shader->vgt_vertex_reuse_block_cntl)
1168 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1169 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1170 shader->vgt_vertex_reuse_block_cntl);
1171
1172 if (initial_cdw != sctx->gfx_cs->current.cdw)
1173 sctx->context_roll = true;
1174 }
1175
1176 /**
1177 * Compute the state for \p shader, which will run as a vertex shader on the
1178 * hardware.
1179 *
1180 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1181 * is the copy shader.
1182 */
1183 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1184 struct si_shader_selector *gs)
1185 {
1186 const struct tgsi_shader_info *info = &shader->selector->info;
1187 struct si_pm4_state *pm4;
1188 unsigned num_user_sgprs, vgpr_comp_cnt;
1189 uint64_t va;
1190 unsigned nparams, oc_lds_en;
1191 unsigned window_space =
1192 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1193 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1194
1195 pm4 = si_get_shader_pm4_state(shader);
1196 if (!pm4)
1197 return;
1198
1199 pm4->atom.emit = si_emit_shader_vs;
1200
1201 /* We always write VGT_GS_MODE in the VS state, because every switch
1202 * between different shader pipelines involving a different GS or no
1203 * GS at all involves a switch of the VS (different GS use different
1204 * copy shaders). On the other hand, when the API switches from a GS to
1205 * no GS and then back to the same GS used originally, the GS state is
1206 * not sent again.
1207 */
1208 if (!gs) {
1209 unsigned mode = V_028A40_GS_OFF;
1210
1211 /* PrimID needs GS scenario A. */
1212 if (enable_prim_id)
1213 mode = V_028A40_GS_SCENARIO_A;
1214
1215 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1216 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1217 } else {
1218 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1219 sscreen->info.chip_class);
1220 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1221 }
1222
1223 if (sscreen->info.chip_class <= GFX8) {
1224 /* Reuse needs to be set off if we write oViewport. */
1225 shader->ctx_reg.vs.vgt_reuse_off =
1226 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1227 }
1228
1229 va = shader->bo->gpu_address;
1230 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1231
1232 if (gs) {
1233 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1234 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1235 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1236 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1237 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1238 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1239 */
1240 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1241
1242 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1243 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1244 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1245 } else {
1246 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1247 }
1248 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1249 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1250 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1251 } else
1252 unreachable("invalid shader selector type");
1253
1254 /* VS is required to export at least one param. */
1255 nparams = MAX2(shader->info.nr_param_exports, 1);
1256 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1257
1258 shader->ctx_reg.vs.spi_shader_pos_format =
1259 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1260 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1261 V_02870C_SPI_SHADER_4COMP :
1262 V_02870C_SPI_SHADER_NONE) |
1263 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1264 V_02870C_SPI_SHADER_4COMP :
1265 V_02870C_SPI_SHADER_NONE) |
1266 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1267 V_02870C_SPI_SHADER_4COMP :
1268 V_02870C_SPI_SHADER_NONE);
1269
1270 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1271
1272 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1273 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1274 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
1275 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
1276 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
1277 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1278 S_00B128_DX10_CLAMP(1) |
1279 S_00B128_FLOAT_MODE(shader->config.float_mode));
1280 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
1281 S_00B12C_USER_SGPR(num_user_sgprs) |
1282 S_00B12C_OC_LDS_EN(oc_lds_en) |
1283 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1284 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1285 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1286 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1287 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
1288 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1289
1290 if (window_space)
1291 shader->ctx_reg.vs.pa_cl_vte_cntl =
1292 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1293 else
1294 shader->ctx_reg.vs.pa_cl_vte_cntl =
1295 S_028818_VTX_W0_FMT(1) |
1296 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1297 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1298 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1299
1300 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1301 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1302
1303 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1304 }
1305
1306 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1307 {
1308 struct tgsi_shader_info *info = &ps->selector->info;
1309 unsigned num_colors = !!(info->colors_read & 0x0f) +
1310 !!(info->colors_read & 0xf0);
1311 unsigned num_interp = ps->selector->info.num_inputs +
1312 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1313
1314 assert(num_interp <= 32);
1315 return MIN2(num_interp, 32);
1316 }
1317
1318 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1319 {
1320 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1321 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1322
1323 /* If the i-th target format is set, all previous target formats must
1324 * be non-zero to avoid hangs.
1325 */
1326 for (i = 0; i < num_targets; i++)
1327 if (!(value & (0xf << (i * 4))))
1328 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1329
1330 return value;
1331 }
1332
1333 static void si_emit_shader_ps(struct si_context *sctx)
1334 {
1335 struct si_shader *shader = sctx->queued.named.ps->shader;
1336 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1337
1338 if (!shader)
1339 return;
1340
1341 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1342 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1343 SI_TRACKED_SPI_PS_INPUT_ENA,
1344 shader->ctx_reg.ps.spi_ps_input_ena,
1345 shader->ctx_reg.ps.spi_ps_input_addr);
1346
1347 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1348 SI_TRACKED_SPI_BARYC_CNTL,
1349 shader->ctx_reg.ps.spi_baryc_cntl);
1350 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1351 SI_TRACKED_SPI_PS_IN_CONTROL,
1352 shader->ctx_reg.ps.spi_ps_in_control);
1353
1354 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1355 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1356 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1357 shader->ctx_reg.ps.spi_shader_z_format,
1358 shader->ctx_reg.ps.spi_shader_col_format);
1359
1360 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1361 SI_TRACKED_CB_SHADER_MASK,
1362 shader->ctx_reg.ps.cb_shader_mask);
1363
1364 if (initial_cdw != sctx->gfx_cs->current.cdw)
1365 sctx->context_roll = true;
1366 }
1367
1368 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1369 {
1370 struct tgsi_shader_info *info = &shader->selector->info;
1371 struct si_pm4_state *pm4;
1372 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1373 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1374 uint64_t va;
1375 unsigned input_ena = shader->config.spi_ps_input_ena;
1376
1377 /* we need to enable at least one of them, otherwise we hang the GPU */
1378 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1379 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1380 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1381 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1382 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1383 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1384 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1385 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1386 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1387 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1388 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1389 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1390 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1391 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1392
1393 /* Validate interpolation optimization flags (read as implications). */
1394 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1395 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1396 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1397 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1398 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1399 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1400 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1401 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1402 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1403 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1404 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1405 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1406 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1407 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1408 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1409 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1410 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1411 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1412
1413 /* Validate cases when the optimizations are off (read as implications). */
1414 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1415 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1416 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1417 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1418 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1419 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1420
1421 pm4 = si_get_shader_pm4_state(shader);
1422 if (!pm4)
1423 return;
1424
1425 pm4->atom.emit = si_emit_shader_ps;
1426
1427 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1428 * Possible vaules:
1429 * 0 -> Position = pixel center
1430 * 1 -> Position = pixel centroid
1431 * 2 -> Position = at sample position
1432 *
1433 * From GLSL 4.5 specification, section 7.1:
1434 * "The variable gl_FragCoord is available as an input variable from
1435 * within fragment shaders and it holds the window relative coordinates
1436 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1437 * value can be for any location within the pixel, or one of the
1438 * fragment samples. The use of centroid does not further restrict
1439 * this value to be inside the current primitive."
1440 *
1441 * Meaning that centroid has no effect and we can return anything within
1442 * the pixel. Thus, return the value at sample position, because that's
1443 * the most accurate one shaders can get.
1444 */
1445 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1446
1447 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1448 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1449 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1450
1451 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1452 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1453
1454 /* Ensure that some export memory is always allocated, for two reasons:
1455 *
1456 * 1) Correctness: The hardware ignores the EXEC mask if no export
1457 * memory is allocated, so KILL and alpha test do not work correctly
1458 * without this.
1459 * 2) Performance: Every shader needs at least a NULL export, even when
1460 * it writes no color/depth output. The NULL export instruction
1461 * stalls without this setting.
1462 *
1463 * Don't add this to CB_SHADER_MASK.
1464 */
1465 if (!spi_shader_col_format &&
1466 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1467 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1468
1469 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1470 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1471
1472 /* Set interpolation controls. */
1473 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1474
1475 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1476 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1477 shader->ctx_reg.ps.spi_shader_z_format =
1478 ac_get_spi_shader_z_format(info->writes_z,
1479 info->writes_stencil,
1480 info->writes_samplemask);
1481 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1482 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1483
1484 va = shader->bo->gpu_address;
1485 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1486 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1487 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1488
1489 uint32_t rsrc1 =
1490 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1491 S_00B028_DX10_CLAMP(1) |
1492 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1493 S_00B028_FLOAT_MODE(shader->config.float_mode);
1494
1495 if (sscreen->info.chip_class < GFX10) {
1496 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1497 }
1498
1499 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1500 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1501 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1502 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1503 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1504 }
1505
1506 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1507 struct si_shader *shader)
1508 {
1509 switch (shader->selector->type) {
1510 case PIPE_SHADER_VERTEX:
1511 if (shader->key.as_ls)
1512 si_shader_ls(sscreen, shader);
1513 else if (shader->key.as_es)
1514 si_shader_es(sscreen, shader);
1515 else if (shader->key.as_ngg)
1516 gfx10_shader_ngg(sscreen, shader);
1517 else
1518 si_shader_vs(sscreen, shader, NULL);
1519 break;
1520 case PIPE_SHADER_TESS_CTRL:
1521 si_shader_hs(sscreen, shader);
1522 break;
1523 case PIPE_SHADER_TESS_EVAL:
1524 if (shader->key.as_es)
1525 si_shader_es(sscreen, shader);
1526 else if (shader->key.as_ngg)
1527 gfx10_shader_ngg(sscreen, shader);
1528 else
1529 si_shader_vs(sscreen, shader, NULL);
1530 break;
1531 case PIPE_SHADER_GEOMETRY:
1532 si_shader_gs(sscreen, shader);
1533 break;
1534 case PIPE_SHADER_FRAGMENT:
1535 si_shader_ps(sscreen, shader);
1536 break;
1537 default:
1538 assert(0);
1539 }
1540 }
1541
1542 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1543 {
1544 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1545 if (sctx->queued.named.dsa)
1546 return sctx->queued.named.dsa->alpha_func;
1547
1548 return PIPE_FUNC_ALWAYS;
1549 }
1550
1551 void si_shader_selector_key_vs(struct si_context *sctx,
1552 struct si_shader_selector *vs,
1553 struct si_shader_key *key,
1554 struct si_vs_prolog_bits *prolog_key)
1555 {
1556 if (!sctx->vertex_elements ||
1557 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS])
1558 return;
1559
1560 struct si_vertex_elements *elts = sctx->vertex_elements;
1561
1562 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1563 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1564 prolog_key->unpack_instance_id_from_vertex_id =
1565 sctx->prim_discard_cs_instancing;
1566
1567 /* Prefer a monolithic shader to allow scheduling divisions around
1568 * VBO loads. */
1569 if (prolog_key->instance_divisor_is_fetched)
1570 key->opt.prefer_mono = 1;
1571
1572 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1573 unsigned count_mask = (1 << count) - 1;
1574 unsigned fix = elts->fix_fetch_always & count_mask;
1575 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1576
1577 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1578 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1579 while (mask) {
1580 unsigned i = u_bit_scan(&mask);
1581 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1582 unsigned vbidx = elts->vertex_buffer_index[i];
1583 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1584 unsigned align_mask = (1 << log_hw_load_size) - 1;
1585 if (vb->buffer_offset & align_mask ||
1586 vb->stride & align_mask) {
1587 fix |= 1 << i;
1588 opencode |= 1 << i;
1589 }
1590 }
1591 }
1592
1593 while (fix) {
1594 unsigned i = u_bit_scan(&fix);
1595 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1596 }
1597 key->mono.vs_fetch_opencode = opencode;
1598 }
1599
1600 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1601 struct si_shader_selector *vs,
1602 struct si_shader_key *key)
1603 {
1604 struct si_shader_selector *ps = sctx->ps_shader.cso;
1605
1606 key->opt.clip_disable =
1607 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1608 (vs->info.clipdist_writemask ||
1609 vs->info.writes_clipvertex) &&
1610 !vs->info.culldist_writemask;
1611
1612 /* Find out if PS is disabled. */
1613 bool ps_disabled = true;
1614 if (ps) {
1615 const struct si_state_blend *blend = sctx->queued.named.blend;
1616 bool alpha_to_coverage = blend && blend->alpha_to_coverage;
1617 bool ps_modifies_zs = ps->info.uses_kill ||
1618 ps->info.writes_z ||
1619 ps->info.writes_stencil ||
1620 ps->info.writes_samplemask ||
1621 alpha_to_coverage ||
1622 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1623 unsigned ps_colormask = si_get_total_colormask(sctx);
1624
1625 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1626 (!ps_colormask &&
1627 !ps_modifies_zs &&
1628 !ps->info.writes_memory);
1629 }
1630
1631 /* Find out which VS outputs aren't used by the PS. */
1632 uint64_t outputs_written = vs->outputs_written_before_ps;
1633 uint64_t inputs_read = 0;
1634
1635 /* Ignore outputs that are not passed from VS to PS. */
1636 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1637 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1638 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1639
1640 if (!ps_disabled) {
1641 inputs_read = ps->inputs_read;
1642 }
1643
1644 uint64_t linked = outputs_written & inputs_read;
1645
1646 key->opt.kill_outputs = ~linked & outputs_written;
1647 }
1648
1649 /* Compute the key for the hw shader variant */
1650 static inline void si_shader_selector_key(struct pipe_context *ctx,
1651 struct si_shader_selector *sel,
1652 union si_vgt_stages_key stages_key,
1653 struct si_shader_key *key)
1654 {
1655 struct si_context *sctx = (struct si_context *)ctx;
1656
1657 memset(key, 0, sizeof(*key));
1658
1659 switch (sel->type) {
1660 case PIPE_SHADER_VERTEX:
1661 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1662
1663 if (sctx->tes_shader.cso)
1664 key->as_ls = 1;
1665 else if (sctx->gs_shader.cso)
1666 key->as_es = 1;
1667 else {
1668 key->as_ngg = stages_key.u.ngg;
1669 si_shader_selector_key_hw_vs(sctx, sel, key);
1670
1671 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1672 key->mono.u.vs_export_prim_id = 1;
1673 }
1674 break;
1675 case PIPE_SHADER_TESS_CTRL:
1676 if (sctx->chip_class >= GFX9) {
1677 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1678 key, &key->part.tcs.ls_prolog);
1679 key->part.tcs.ls = sctx->vs_shader.cso;
1680
1681 /* When the LS VGPR fix is needed, monolithic shaders
1682 * can:
1683 * - avoid initializing EXEC in both the LS prolog
1684 * and the LS main part when !vs_needs_prolog
1685 * - remove the fixup for unused input VGPRs
1686 */
1687 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1688
1689 /* The LS output / HS input layout can be communicated
1690 * directly instead of via user SGPRs for merged LS-HS.
1691 * The LS VGPR fix prefers this too.
1692 */
1693 key->opt.prefer_mono = 1;
1694 }
1695
1696 key->part.tcs.epilog.prim_mode =
1697 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1698 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1699 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1700 key->part.tcs.epilog.tes_reads_tess_factors =
1701 sctx->tes_shader.cso->info.reads_tess_factors;
1702
1703 if (sel == sctx->fixed_func_tcs_shader.cso)
1704 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1705 break;
1706 case PIPE_SHADER_TESS_EVAL:
1707 if (sctx->gs_shader.cso)
1708 key->as_es = 1;
1709 else {
1710 key->as_ngg = stages_key.u.ngg;
1711 si_shader_selector_key_hw_vs(sctx, sel, key);
1712
1713 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1714 key->mono.u.vs_export_prim_id = 1;
1715 }
1716 break;
1717 case PIPE_SHADER_GEOMETRY:
1718 if (sctx->chip_class >= GFX9) {
1719 if (sctx->tes_shader.cso) {
1720 key->part.gs.es = sctx->tes_shader.cso;
1721 } else {
1722 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1723 key, &key->part.gs.vs_prolog);
1724 key->part.gs.es = sctx->vs_shader.cso;
1725 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1726 }
1727
1728 key->as_ngg = stages_key.u.ngg;
1729
1730 /* Merged ES-GS can have unbalanced wave usage.
1731 *
1732 * ES threads are per-vertex, while GS threads are
1733 * per-primitive. So without any amplification, there
1734 * are fewer GS threads than ES threads, which can result
1735 * in empty (no-op) GS waves. With too much amplification,
1736 * there are more GS threads than ES threads, which
1737 * can result in empty (no-op) ES waves.
1738 *
1739 * Non-monolithic shaders are implemented by setting EXEC
1740 * at the beginning of shader parts, and don't jump to
1741 * the end if EXEC is 0.
1742 *
1743 * Monolithic shaders use conditional blocks, so they can
1744 * jump and skip empty waves of ES or GS. So set this to
1745 * always use optimized variants, which are monolithic.
1746 */
1747 key->opt.prefer_mono = 1;
1748 }
1749 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1750 break;
1751 case PIPE_SHADER_FRAGMENT: {
1752 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1753 struct si_state_blend *blend = sctx->queued.named.blend;
1754
1755 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1756 sel->info.colors_written == 0x1)
1757 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1758
1759 if (blend) {
1760 /* Select the shader color format based on whether
1761 * blending or alpha are needed.
1762 */
1763 key->part.ps.epilog.spi_shader_col_format =
1764 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1765 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1766 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1767 sctx->framebuffer.spi_shader_col_format_blend) |
1768 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1769 sctx->framebuffer.spi_shader_col_format_alpha) |
1770 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1771 sctx->framebuffer.spi_shader_col_format);
1772 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1773
1774 /* The output for dual source blending should have
1775 * the same format as the first output.
1776 */
1777 if (blend->dual_src_blend)
1778 key->part.ps.epilog.spi_shader_col_format |=
1779 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1780 } else
1781 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1782
1783 /* If alpha-to-coverage is enabled, we have to export alpha
1784 * even if there is no color buffer.
1785 */
1786 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1787 blend && blend->alpha_to_coverage)
1788 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1789
1790 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1791 * to the range supported by the type if a channel has less
1792 * than 16 bits and the export format is 16_ABGR.
1793 */
1794 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1795 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1796 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1797 }
1798
1799 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1800 if (!key->part.ps.epilog.last_cbuf) {
1801 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1802 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1803 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1804 }
1805
1806 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1807 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1808
1809 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1810 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1811
1812 if (sctx->queued.named.blend) {
1813 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1814 rs->multisample_enable;
1815 }
1816
1817 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1818 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1819 (is_line && rs->line_smooth)) &&
1820 sctx->framebuffer.nr_samples <= 1;
1821 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1822
1823 if (sctx->ps_iter_samples > 1 &&
1824 sel->info.reads_samplemask) {
1825 key->part.ps.prolog.samplemask_log_ps_iter =
1826 util_logbase2(sctx->ps_iter_samples);
1827 }
1828
1829 if (rs->force_persample_interp &&
1830 rs->multisample_enable &&
1831 sctx->framebuffer.nr_samples > 1 &&
1832 sctx->ps_iter_samples > 1) {
1833 key->part.ps.prolog.force_persp_sample_interp =
1834 sel->info.uses_persp_center ||
1835 sel->info.uses_persp_centroid;
1836
1837 key->part.ps.prolog.force_linear_sample_interp =
1838 sel->info.uses_linear_center ||
1839 sel->info.uses_linear_centroid;
1840 } else if (rs->multisample_enable &&
1841 sctx->framebuffer.nr_samples > 1) {
1842 key->part.ps.prolog.bc_optimize_for_persp =
1843 sel->info.uses_persp_center &&
1844 sel->info.uses_persp_centroid;
1845 key->part.ps.prolog.bc_optimize_for_linear =
1846 sel->info.uses_linear_center &&
1847 sel->info.uses_linear_centroid;
1848 } else {
1849 /* Make sure SPI doesn't compute more than 1 pair
1850 * of (i,j), which is the optimization here. */
1851 key->part.ps.prolog.force_persp_center_interp =
1852 sel->info.uses_persp_center +
1853 sel->info.uses_persp_centroid +
1854 sel->info.uses_persp_sample > 1;
1855
1856 key->part.ps.prolog.force_linear_center_interp =
1857 sel->info.uses_linear_center +
1858 sel->info.uses_linear_centroid +
1859 sel->info.uses_linear_sample > 1;
1860
1861 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
1862 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1863 }
1864
1865 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1866
1867 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1868 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
1869 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
1870 struct pipe_resource *tex = cb0->texture;
1871
1872 /* 1D textures are allocated and used as 2D on GFX9. */
1873 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
1874 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
1875 (tex->target == PIPE_TEXTURE_1D ||
1876 tex->target == PIPE_TEXTURE_1D_ARRAY);
1877 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
1878 tex->target == PIPE_TEXTURE_2D_ARRAY ||
1879 tex->target == PIPE_TEXTURE_CUBE ||
1880 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
1881 tex->target == PIPE_TEXTURE_3D;
1882 }
1883 break;
1884 }
1885 default:
1886 assert(0);
1887 }
1888
1889 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
1890 memset(&key->opt, 0, sizeof(key->opt));
1891 }
1892
1893 static void si_build_shader_variant(struct si_shader *shader,
1894 int thread_index,
1895 bool low_priority)
1896 {
1897 struct si_shader_selector *sel = shader->selector;
1898 struct si_screen *sscreen = sel->screen;
1899 struct ac_llvm_compiler *compiler;
1900 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1901
1902 if (thread_index >= 0) {
1903 if (low_priority) {
1904 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
1905 compiler = &sscreen->compiler_lowp[thread_index];
1906 } else {
1907 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
1908 compiler = &sscreen->compiler[thread_index];
1909 }
1910 if (!debug->async)
1911 debug = NULL;
1912 } else {
1913 assert(!low_priority);
1914 compiler = shader->compiler_ctx_state.compiler;
1915 }
1916
1917 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
1918 PRINT_ERR("Failed to build shader variant (type=%u)\n",
1919 sel->type);
1920 shader->compilation_failed = true;
1921 return;
1922 }
1923
1924 if (shader->compiler_ctx_state.is_debug_context) {
1925 FILE *f = open_memstream(&shader->shader_log,
1926 &shader->shader_log_size);
1927 if (f) {
1928 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1929 fclose(f);
1930 }
1931 }
1932
1933 si_shader_init_pm4_state(sscreen, shader);
1934 }
1935
1936 static void si_build_shader_variant_low_priority(void *job, int thread_index)
1937 {
1938 struct si_shader *shader = (struct si_shader *)job;
1939
1940 assert(thread_index >= 0);
1941
1942 si_build_shader_variant(shader, thread_index, true);
1943 }
1944
1945 static const struct si_shader_key zeroed;
1946
1947 static bool si_check_missing_main_part(struct si_screen *sscreen,
1948 struct si_shader_selector *sel,
1949 struct si_compiler_ctx_state *compiler_state,
1950 struct si_shader_key *key)
1951 {
1952 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1953
1954 if (!*mainp) {
1955 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1956
1957 if (!main_part)
1958 return false;
1959
1960 /* We can leave the fence as permanently signaled because the
1961 * main part becomes visible globally only after it has been
1962 * compiled. */
1963 util_queue_fence_init(&main_part->ready);
1964
1965 main_part->selector = sel;
1966 main_part->key.as_es = key->as_es;
1967 main_part->key.as_ls = key->as_ls;
1968 main_part->key.as_ngg = key->as_ngg;
1969 main_part->is_monolithic = false;
1970
1971 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
1972 main_part, &compiler_state->debug) != 0) {
1973 FREE(main_part);
1974 return false;
1975 }
1976 *mainp = main_part;
1977 }
1978 return true;
1979 }
1980
1981 /**
1982 * Select a shader variant according to the shader key.
1983 *
1984 * \param optimized_or_none If the key describes an optimized shader variant and
1985 * the compilation isn't finished, don't select any
1986 * shader and return an error.
1987 */
1988 int si_shader_select_with_key(struct si_screen *sscreen,
1989 struct si_shader_ctx_state *state,
1990 struct si_compiler_ctx_state *compiler_state,
1991 struct si_shader_key *key,
1992 int thread_index,
1993 bool optimized_or_none)
1994 {
1995 struct si_shader_selector *sel = state->cso;
1996 struct si_shader_selector *previous_stage_sel = NULL;
1997 struct si_shader *current = state->current;
1998 struct si_shader *iter, *shader = NULL;
1999
2000 again:
2001 /* Check if we don't need to change anything.
2002 * This path is also used for most shaders that don't need multiple
2003 * variants, it will cost just a computation of the key and this
2004 * test. */
2005 if (likely(current &&
2006 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2007 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2008 if (current->is_optimized) {
2009 if (optimized_or_none)
2010 return -1;
2011
2012 memset(&key->opt, 0, sizeof(key->opt));
2013 goto current_not_ready;
2014 }
2015
2016 util_queue_fence_wait(&current->ready);
2017 }
2018
2019 return current->compilation_failed ? -1 : 0;
2020 }
2021 current_not_ready:
2022
2023 /* This must be done before the mutex is locked, because async GS
2024 * compilation calls this function too, and therefore must enter
2025 * the mutex first.
2026 *
2027 * Only wait if we are in a draw call. Don't wait if we are
2028 * in a compiler thread.
2029 */
2030 if (thread_index < 0)
2031 util_queue_fence_wait(&sel->ready);
2032
2033 mtx_lock(&sel->mutex);
2034
2035 /* Find the shader variant. */
2036 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2037 /* Don't check the "current" shader. We checked it above. */
2038 if (current != iter &&
2039 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2040 mtx_unlock(&sel->mutex);
2041
2042 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2043 /* If it's an optimized shader and its compilation has
2044 * been started but isn't done, use the unoptimized
2045 * shader so as not to cause a stall due to compilation.
2046 */
2047 if (iter->is_optimized) {
2048 if (optimized_or_none)
2049 return -1;
2050 memset(&key->opt, 0, sizeof(key->opt));
2051 goto again;
2052 }
2053
2054 util_queue_fence_wait(&iter->ready);
2055 }
2056
2057 if (iter->compilation_failed) {
2058 return -1; /* skip the draw call */
2059 }
2060
2061 state->current = iter;
2062 return 0;
2063 }
2064 }
2065
2066 /* Build a new shader. */
2067 shader = CALLOC_STRUCT(si_shader);
2068 if (!shader) {
2069 mtx_unlock(&sel->mutex);
2070 return -ENOMEM;
2071 }
2072
2073 util_queue_fence_init(&shader->ready);
2074
2075 shader->selector = sel;
2076 shader->key = *key;
2077 shader->compiler_ctx_state = *compiler_state;
2078
2079 /* If this is a merged shader, get the first shader's selector. */
2080 if (sscreen->info.chip_class >= GFX9) {
2081 if (sel->type == PIPE_SHADER_TESS_CTRL)
2082 previous_stage_sel = key->part.tcs.ls;
2083 else if (sel->type == PIPE_SHADER_GEOMETRY)
2084 previous_stage_sel = key->part.gs.es;
2085
2086 /* We need to wait for the previous shader. */
2087 if (previous_stage_sel && thread_index < 0)
2088 util_queue_fence_wait(&previous_stage_sel->ready);
2089 }
2090
2091 bool is_pure_monolithic =
2092 sscreen->use_monolithic_shaders ||
2093 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2094
2095 /* Compile the main shader part if it doesn't exist. This can happen
2096 * if the initial guess was wrong.
2097 *
2098 * The prim discard CS doesn't need the main shader part.
2099 */
2100 if (!is_pure_monolithic &&
2101 !key->opt.vs_as_prim_discard_cs) {
2102 bool ok = true;
2103
2104 /* Make sure the main shader part is present. This is needed
2105 * for shaders that can be compiled as VS, LS, or ES, and only
2106 * one of them is compiled at creation.
2107 *
2108 * It is also needed for GS, which can be compiled as non-NGG
2109 * and NGG.
2110 *
2111 * For merged shaders, check that the starting shader's main
2112 * part is present.
2113 */
2114 if (previous_stage_sel) {
2115 struct si_shader_key shader1_key = zeroed;
2116
2117 if (sel->type == PIPE_SHADER_TESS_CTRL)
2118 shader1_key.as_ls = 1;
2119 else if (sel->type == PIPE_SHADER_GEOMETRY)
2120 shader1_key.as_es = 1;
2121 else
2122 assert(0);
2123
2124 mtx_lock(&previous_stage_sel->mutex);
2125 ok = si_check_missing_main_part(sscreen,
2126 previous_stage_sel,
2127 compiler_state, &shader1_key);
2128 mtx_unlock(&previous_stage_sel->mutex);
2129 }
2130
2131 if (ok) {
2132 ok = si_check_missing_main_part(sscreen, sel,
2133 compiler_state, key);
2134 }
2135
2136 if (!ok) {
2137 FREE(shader);
2138 mtx_unlock(&sel->mutex);
2139 return -ENOMEM; /* skip the draw call */
2140 }
2141 }
2142
2143 /* Keep the reference to the 1st shader of merged shaders, so that
2144 * Gallium can't destroy it before we destroy the 2nd shader.
2145 *
2146 * Set sctx = NULL, because it's unused if we're not releasing
2147 * the shader, and we don't have any sctx here.
2148 */
2149 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2150 previous_stage_sel);
2151
2152 /* Monolithic-only shaders don't make a distinction between optimized
2153 * and unoptimized. */
2154 shader->is_monolithic =
2155 is_pure_monolithic ||
2156 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2157
2158 /* The prim discard CS is always optimized. */
2159 shader->is_optimized =
2160 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2161 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2162
2163 /* If it's an optimized shader, compile it asynchronously. */
2164 if (shader->is_optimized && thread_index < 0) {
2165 /* Compile it asynchronously. */
2166 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2167 shader, &shader->ready,
2168 si_build_shader_variant_low_priority, NULL);
2169
2170 /* Add only after the ready fence was reset, to guard against a
2171 * race with si_bind_XX_shader. */
2172 if (!sel->last_variant) {
2173 sel->first_variant = shader;
2174 sel->last_variant = shader;
2175 } else {
2176 sel->last_variant->next_variant = shader;
2177 sel->last_variant = shader;
2178 }
2179
2180 /* Use the default (unoptimized) shader for now. */
2181 memset(&key->opt, 0, sizeof(key->opt));
2182 mtx_unlock(&sel->mutex);
2183
2184 if (sscreen->options.sync_compile)
2185 util_queue_fence_wait(&shader->ready);
2186
2187 if (optimized_or_none)
2188 return -1;
2189 goto again;
2190 }
2191
2192 /* Reset the fence before adding to the variant list. */
2193 util_queue_fence_reset(&shader->ready);
2194
2195 if (!sel->last_variant) {
2196 sel->first_variant = shader;
2197 sel->last_variant = shader;
2198 } else {
2199 sel->last_variant->next_variant = shader;
2200 sel->last_variant = shader;
2201 }
2202
2203 mtx_unlock(&sel->mutex);
2204
2205 assert(!shader->is_optimized);
2206 si_build_shader_variant(shader, thread_index, false);
2207
2208 util_queue_fence_signal(&shader->ready);
2209
2210 if (!shader->compilation_failed)
2211 state->current = shader;
2212
2213 return shader->compilation_failed ? -1 : 0;
2214 }
2215
2216 static int si_shader_select(struct pipe_context *ctx,
2217 struct si_shader_ctx_state *state,
2218 union si_vgt_stages_key stages_key,
2219 struct si_compiler_ctx_state *compiler_state)
2220 {
2221 struct si_context *sctx = (struct si_context *)ctx;
2222 struct si_shader_key key;
2223
2224 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2225 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2226 &key, -1, false);
2227 }
2228
2229 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2230 bool streamout,
2231 struct si_shader_key *key)
2232 {
2233 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2234
2235 switch (info->processor) {
2236 case PIPE_SHADER_VERTEX:
2237 switch (next_shader) {
2238 case PIPE_SHADER_GEOMETRY:
2239 key->as_es = 1;
2240 break;
2241 case PIPE_SHADER_TESS_CTRL:
2242 case PIPE_SHADER_TESS_EVAL:
2243 key->as_ls = 1;
2244 break;
2245 default:
2246 /* If POSITION isn't written, it can only be a HW VS
2247 * if streamout is used. If streamout isn't used,
2248 * assume that it's a HW LS. (the next shader is TCS)
2249 * This heuristic is needed for separate shader objects.
2250 */
2251 if (!info->writes_position && !streamout)
2252 key->as_ls = 1;
2253 }
2254 break;
2255
2256 case PIPE_SHADER_TESS_EVAL:
2257 if (next_shader == PIPE_SHADER_GEOMETRY ||
2258 !info->writes_position)
2259 key->as_es = 1;
2260 break;
2261 }
2262 }
2263
2264 /**
2265 * Compile the main shader part or the monolithic shader as part of
2266 * si_shader_selector initialization. Since it can be done asynchronously,
2267 * there is no way to report compile failures to applications.
2268 */
2269 static void si_init_shader_selector_async(void *job, int thread_index)
2270 {
2271 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2272 struct si_screen *sscreen = sel->screen;
2273 struct ac_llvm_compiler *compiler;
2274 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2275
2276 assert(!debug->debug_message || debug->async);
2277 assert(thread_index >= 0);
2278 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2279 compiler = &sscreen->compiler[thread_index];
2280
2281 if (sel->nir)
2282 si_lower_nir(sel);
2283
2284 /* Compile the main shader part for use with a prolog and/or epilog.
2285 * If this fails, the driver will try to compile a monolithic shader
2286 * on demand.
2287 */
2288 if (!sscreen->use_monolithic_shaders) {
2289 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2290 void *ir_binary = NULL;
2291
2292 if (!shader) {
2293 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2294 return;
2295 }
2296
2297 /* We can leave the fence signaled because use of the default
2298 * main part is guarded by the selector's ready fence. */
2299 util_queue_fence_init(&shader->ready);
2300
2301 shader->selector = sel;
2302 shader->is_monolithic = false;
2303 si_parse_next_shader_property(&sel->info,
2304 sel->so.num_outputs != 0,
2305 &shader->key);
2306 if (sscreen->info.chip_class >= GFX10 &&
2307 !sscreen->options.disable_ngg &&
2308 (((sel->type == PIPE_SHADER_VERTEX ||
2309 sel->type == PIPE_SHADER_TESS_EVAL) &&
2310 !shader->key.as_ls && !shader->key.as_es) ||
2311 sel->type == PIPE_SHADER_GEOMETRY))
2312 shader->key.as_ngg = 1;
2313
2314 if (sel->tokens || sel->nir)
2315 ir_binary = si_get_ir_binary(sel);
2316
2317 /* Try to load the shader from the shader cache. */
2318 mtx_lock(&sscreen->shader_cache_mutex);
2319
2320 if (ir_binary &&
2321 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2322 mtx_unlock(&sscreen->shader_cache_mutex);
2323 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2324 } else {
2325 mtx_unlock(&sscreen->shader_cache_mutex);
2326
2327 /* Compile the shader if it hasn't been loaded from the cache. */
2328 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2329 debug) != 0) {
2330 FREE(shader);
2331 FREE(ir_binary);
2332 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2333 return;
2334 }
2335
2336 if (ir_binary) {
2337 mtx_lock(&sscreen->shader_cache_mutex);
2338 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2339 FREE(ir_binary);
2340 mtx_unlock(&sscreen->shader_cache_mutex);
2341 }
2342 }
2343
2344 *si_get_main_shader_part(sel, &shader->key) = shader;
2345
2346 /* Unset "outputs_written" flags for outputs converted to
2347 * DEFAULT_VAL, so that later inter-shader optimizations don't
2348 * try to eliminate outputs that don't exist in the final
2349 * shader.
2350 *
2351 * This is only done if non-monolithic shaders are enabled.
2352 */
2353 if ((sel->type == PIPE_SHADER_VERTEX ||
2354 sel->type == PIPE_SHADER_TESS_EVAL) &&
2355 !shader->key.as_ls &&
2356 !shader->key.as_es) {
2357 unsigned i;
2358
2359 for (i = 0; i < sel->info.num_outputs; i++) {
2360 unsigned offset = shader->info.vs_output_param_offset[i];
2361
2362 if (offset <= AC_EXP_PARAM_OFFSET_31)
2363 continue;
2364
2365 unsigned name = sel->info.output_semantic_name[i];
2366 unsigned index = sel->info.output_semantic_index[i];
2367 unsigned id;
2368
2369 switch (name) {
2370 case TGSI_SEMANTIC_GENERIC:
2371 /* don't process indices the function can't handle */
2372 if (index >= SI_MAX_IO_GENERIC)
2373 break;
2374 /* fall through */
2375 default:
2376 id = si_shader_io_get_unique_index(name, index, true);
2377 sel->outputs_written_before_ps &= ~(1ull << id);
2378 break;
2379 case TGSI_SEMANTIC_POSITION: /* ignore these */
2380 case TGSI_SEMANTIC_PSIZE:
2381 case TGSI_SEMANTIC_CLIPVERTEX:
2382 case TGSI_SEMANTIC_EDGEFLAG:
2383 break;
2384 }
2385 }
2386 }
2387 }
2388
2389 /* The GS copy shader is always pre-compiled.
2390 *
2391 * TODO-GFX10: We could compile the GS copy shader on demand, since it
2392 * is only used in the (rare) non-NGG case.
2393 */
2394 if (sel->type == PIPE_SHADER_GEOMETRY) {
2395 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2396 if (!sel->gs_copy_shader) {
2397 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2398 return;
2399 }
2400
2401 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2402 }
2403 }
2404
2405 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2406 struct util_queue_fence *ready_fence,
2407 struct si_compiler_ctx_state *compiler_ctx_state,
2408 void *job, util_queue_execute_func execute)
2409 {
2410 util_queue_fence_init(ready_fence);
2411
2412 struct util_async_debug_callback async_debug;
2413 bool debug =
2414 (sctx->debug.debug_message && !sctx->debug.async) ||
2415 sctx->is_debug ||
2416 si_can_dump_shader(sctx->screen, processor);
2417
2418 if (debug) {
2419 u_async_debug_init(&async_debug);
2420 compiler_ctx_state->debug = async_debug.base;
2421 }
2422
2423 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2424 ready_fence, execute, NULL);
2425
2426 if (debug) {
2427 util_queue_fence_wait(ready_fence);
2428 u_async_debug_drain(&async_debug, &sctx->debug);
2429 u_async_debug_cleanup(&async_debug);
2430 }
2431
2432 if (sctx->screen->options.sync_compile)
2433 util_queue_fence_wait(ready_fence);
2434 }
2435
2436 /* Return descriptor slot usage masks from the given shader info. */
2437 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2438 uint32_t *const_and_shader_buffers,
2439 uint64_t *samplers_and_images)
2440 {
2441 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2442
2443 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2444 num_constbufs = util_last_bit(info->const_buffers_declared);
2445 /* two 8-byte images share one 16-byte slot */
2446 num_images = align(util_last_bit(info->images_declared), 2);
2447 num_samplers = util_last_bit(info->samplers_declared);
2448
2449 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2450 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2451 *const_and_shader_buffers =
2452 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2453
2454 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2455 start = si_get_image_slot(num_images - 1) / 2;
2456 *samplers_and_images =
2457 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2458 }
2459
2460 static void *si_create_shader_selector(struct pipe_context *ctx,
2461 const struct pipe_shader_state *state)
2462 {
2463 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2464 struct si_context *sctx = (struct si_context*)ctx;
2465 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2466 int i;
2467
2468 if (!sel)
2469 return NULL;
2470
2471 pipe_reference_init(&sel->reference, 1);
2472 sel->screen = sscreen;
2473 sel->compiler_ctx_state.debug = sctx->debug;
2474 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2475
2476 sel->so = state->stream_output;
2477
2478 if (state->type == PIPE_SHADER_IR_TGSI) {
2479 sel->tokens = tgsi_dup_tokens(state->tokens);
2480 if (!sel->tokens) {
2481 FREE(sel);
2482 return NULL;
2483 }
2484
2485 tgsi_scan_shader(state->tokens, &sel->info);
2486 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2487 } else {
2488 assert(state->type == PIPE_SHADER_IR_NIR);
2489
2490 sel->nir = state->ir.nir;
2491
2492 si_nir_opts(sel->nir);
2493 si_nir_scan_shader(sel->nir, &sel->info);
2494 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2495 }
2496
2497 sel->type = sel->info.processor;
2498 p_atomic_inc(&sscreen->num_shaders_created);
2499 si_get_active_slot_masks(&sel->info,
2500 &sel->active_const_and_shader_buffers,
2501 &sel->active_samplers_and_images);
2502
2503 /* Record which streamout buffers are enabled. */
2504 for (i = 0; i < sel->so.num_outputs; i++) {
2505 sel->enabled_streamout_buffer_mask |=
2506 (1 << sel->so.output[i].output_buffer) <<
2507 (sel->so.output[i].stream * 4);
2508 }
2509
2510 /* The prolog is a no-op if there are no inputs. */
2511 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2512 sel->info.num_inputs &&
2513 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2514
2515 sel->force_correct_derivs_after_kill =
2516 sel->type == PIPE_SHADER_FRAGMENT &&
2517 sel->info.uses_derivatives &&
2518 sel->info.uses_kill &&
2519 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2520
2521 sel->prim_discard_cs_allowed =
2522 sel->type == PIPE_SHADER_VERTEX &&
2523 !sel->info.uses_bindless_images &&
2524 !sel->info.uses_bindless_samplers &&
2525 !sel->info.writes_memory &&
2526 !sel->info.writes_viewport_index &&
2527 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2528 !sel->so.num_outputs;
2529
2530 /* Set which opcode uses which (i,j) pair. */
2531 if (sel->info.uses_persp_opcode_interp_centroid)
2532 sel->info.uses_persp_centroid = true;
2533
2534 if (sel->info.uses_linear_opcode_interp_centroid)
2535 sel->info.uses_linear_centroid = true;
2536
2537 if (sel->info.uses_persp_opcode_interp_offset ||
2538 sel->info.uses_persp_opcode_interp_sample)
2539 sel->info.uses_persp_center = true;
2540
2541 if (sel->info.uses_linear_opcode_interp_offset ||
2542 sel->info.uses_linear_opcode_interp_sample)
2543 sel->info.uses_linear_center = true;
2544
2545 switch (sel->type) {
2546 case PIPE_SHADER_GEOMETRY:
2547 sel->gs_output_prim =
2548 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2549 sel->gs_max_out_vertices =
2550 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2551 sel->gs_num_invocations =
2552 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2553 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2554 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2555 sel->gs_max_out_vertices;
2556
2557 sel->max_gs_stream = 0;
2558 for (i = 0; i < sel->so.num_outputs; i++)
2559 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2560 sel->so.output[i].stream);
2561
2562 sel->gs_input_verts_per_prim =
2563 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2564 break;
2565
2566 case PIPE_SHADER_TESS_CTRL:
2567 /* Always reserve space for these. */
2568 sel->patch_outputs_written |=
2569 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2570 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2571 /* fall through */
2572 case PIPE_SHADER_VERTEX:
2573 case PIPE_SHADER_TESS_EVAL:
2574 for (i = 0; i < sel->info.num_outputs; i++) {
2575 unsigned name = sel->info.output_semantic_name[i];
2576 unsigned index = sel->info.output_semantic_index[i];
2577
2578 switch (name) {
2579 case TGSI_SEMANTIC_TESSINNER:
2580 case TGSI_SEMANTIC_TESSOUTER:
2581 case TGSI_SEMANTIC_PATCH:
2582 sel->patch_outputs_written |=
2583 1ull << si_shader_io_get_unique_index_patch(name, index);
2584 break;
2585
2586 case TGSI_SEMANTIC_GENERIC:
2587 /* don't process indices the function can't handle */
2588 if (index >= SI_MAX_IO_GENERIC)
2589 break;
2590 /* fall through */
2591 default:
2592 sel->outputs_written |=
2593 1ull << si_shader_io_get_unique_index(name, index, false);
2594 sel->outputs_written_before_ps |=
2595 1ull << si_shader_io_get_unique_index(name, index, true);
2596 break;
2597 case TGSI_SEMANTIC_EDGEFLAG:
2598 break;
2599 }
2600 }
2601 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2602 sel->lshs_vertex_stride = sel->esgs_itemsize;
2603
2604 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2605 * will start on a different bank. (except for the maximum 32*16).
2606 */
2607 if (sel->lshs_vertex_stride < 32*16)
2608 sel->lshs_vertex_stride += 4;
2609
2610 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2611 * conflicts, i.e. each vertex will start at a different bank.
2612 */
2613 if (sctx->chip_class >= GFX9)
2614 sel->esgs_itemsize += 4;
2615
2616 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2617 break;
2618
2619 case PIPE_SHADER_FRAGMENT:
2620 for (i = 0; i < sel->info.num_inputs; i++) {
2621 unsigned name = sel->info.input_semantic_name[i];
2622 unsigned index = sel->info.input_semantic_index[i];
2623
2624 switch (name) {
2625 case TGSI_SEMANTIC_GENERIC:
2626 /* don't process indices the function can't handle */
2627 if (index >= SI_MAX_IO_GENERIC)
2628 break;
2629 /* fall through */
2630 default:
2631 sel->inputs_read |=
2632 1ull << si_shader_io_get_unique_index(name, index, true);
2633 break;
2634 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2635 break;
2636 }
2637 }
2638
2639 for (i = 0; i < 8; i++)
2640 if (sel->info.colors_written & (1 << i))
2641 sel->colors_written_4bit |= 0xf << (4 * i);
2642
2643 for (i = 0; i < sel->info.num_inputs; i++) {
2644 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2645 int index = sel->info.input_semantic_index[i];
2646 sel->color_attr_index[index] = i;
2647 }
2648 }
2649 break;
2650 }
2651
2652 /* PA_CL_VS_OUT_CNTL */
2653 bool misc_vec_ena =
2654 sel->info.writes_psize || sel->info.writes_edgeflag ||
2655 sel->info.writes_layer || sel->info.writes_viewport_index;
2656 sel->pa_cl_vs_out_cntl =
2657 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2658 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2659 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2660 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2661 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2662 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2663 sel->clipdist_mask = sel->info.writes_clipvertex ?
2664 SIX_BITS : sel->info.clipdist_writemask;
2665 sel->culldist_mask = sel->info.culldist_writemask <<
2666 sel->info.num_written_clipdistance;
2667
2668 /* DB_SHADER_CONTROL */
2669 sel->db_shader_control =
2670 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2671 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2672 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2673 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2674
2675 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2676 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2677 sel->db_shader_control |=
2678 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2679 break;
2680 case TGSI_FS_DEPTH_LAYOUT_LESS:
2681 sel->db_shader_control |=
2682 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2683 break;
2684 }
2685
2686 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2687 *
2688 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2689 * --|-----------|------------|------------|--------------------|-------------------|-------------
2690 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2691 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2692 * 2 | false | true | n/a | LateZ | 1 | 0
2693 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2694 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2695 *
2696 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2697 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2698 *
2699 * Don't use ReZ without profiling !!!
2700 *
2701 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2702 * shaders.
2703 */
2704 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2705 /* Cases 3, 4. */
2706 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2707 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2708 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2709 } else if (sel->info.writes_memory) {
2710 /* Case 2. */
2711 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2712 S_02880C_EXEC_ON_HIER_FAIL(1);
2713 } else {
2714 /* Case 1. */
2715 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2716 }
2717
2718 (void) mtx_init(&sel->mutex, mtx_plain);
2719
2720 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2721 &sel->compiler_ctx_state, sel,
2722 si_init_shader_selector_async);
2723 return sel;
2724 }
2725
2726 static void si_update_streamout_state(struct si_context *sctx)
2727 {
2728 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2729
2730 if (!shader_with_so)
2731 return;
2732
2733 sctx->streamout.enabled_stream_buffers_mask =
2734 shader_with_so->enabled_streamout_buffer_mask;
2735 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2736 }
2737
2738 static void si_update_clip_regs(struct si_context *sctx,
2739 struct si_shader_selector *old_hw_vs,
2740 struct si_shader *old_hw_vs_variant,
2741 struct si_shader_selector *next_hw_vs,
2742 struct si_shader *next_hw_vs_variant)
2743 {
2744 if (next_hw_vs &&
2745 (!old_hw_vs ||
2746 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2747 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2748 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2749 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2750 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2751 !old_hw_vs_variant ||
2752 !next_hw_vs_variant ||
2753 old_hw_vs_variant->key.opt.clip_disable !=
2754 next_hw_vs_variant->key.opt.clip_disable))
2755 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2756 }
2757
2758 static void si_update_common_shader_state(struct si_context *sctx)
2759 {
2760 sctx->uses_bindless_samplers =
2761 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2762 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2763 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2764 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2765 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2766 sctx->uses_bindless_images =
2767 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2768 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2769 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2770 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2771 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2772 sctx->do_update_shaders = true;
2773 }
2774
2775 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2776 {
2777 struct si_context *sctx = (struct si_context *)ctx;
2778 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2779 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2780 struct si_shader_selector *sel = state;
2781
2782 if (sctx->vs_shader.cso == sel)
2783 return;
2784
2785 sctx->vs_shader.cso = sel;
2786 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2787 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2788
2789 si_update_common_shader_state(sctx);
2790 si_update_vs_viewport_state(sctx);
2791 si_set_active_descriptors_for_shader(sctx, sel);
2792 si_update_streamout_state(sctx);
2793 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2794 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2795 }
2796
2797 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2798 {
2799 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2800 (sctx->tes_shader.cso &&
2801 sctx->tes_shader.cso->info.uses_primid) ||
2802 (sctx->tcs_shader.cso &&
2803 sctx->tcs_shader.cso->info.uses_primid) ||
2804 (sctx->gs_shader.cso &&
2805 sctx->gs_shader.cso->info.uses_primid) ||
2806 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2807 sctx->ps_shader.cso->info.uses_primid);
2808 }
2809
2810 static bool si_update_ngg(struct si_context *sctx)
2811 {
2812 if (sctx->chip_class <= GFX9 ||
2813 sctx->screen->options.disable_ngg)
2814 return false;
2815
2816 bool new_ngg = true;
2817
2818 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2819 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
2820 sctx->gs_shader.cso->gs_num_invocations * sctx->gs_shader.cso->gs_max_out_vertices > 256)
2821 new_ngg = false;
2822
2823 if (new_ngg != sctx->ngg) {
2824 sctx->ngg = new_ngg;
2825 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2826 return true;
2827 }
2828 return false;
2829 }
2830
2831 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2832 {
2833 struct si_context *sctx = (struct si_context *)ctx;
2834 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2835 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2836 struct si_shader_selector *sel = state;
2837 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2838 bool ngg_changed;
2839
2840 if (sctx->gs_shader.cso == sel)
2841 return;
2842
2843 sctx->gs_shader.cso = sel;
2844 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2845 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2846
2847 si_update_common_shader_state(sctx);
2848 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2849
2850 ngg_changed = si_update_ngg(sctx);
2851 if (ngg_changed || enable_changed)
2852 si_shader_change_notify(sctx);
2853 if (enable_changed) {
2854 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2855 si_update_tess_uses_prim_id(sctx);
2856 }
2857 si_update_vs_viewport_state(sctx);
2858 si_set_active_descriptors_for_shader(sctx, sel);
2859 si_update_streamout_state(sctx);
2860 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2861 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2862 }
2863
2864 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2865 {
2866 struct si_context *sctx = (struct si_context *)ctx;
2867 struct si_shader_selector *sel = state;
2868 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2869
2870 if (sctx->tcs_shader.cso == sel)
2871 return;
2872
2873 sctx->tcs_shader.cso = sel;
2874 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2875 si_update_tess_uses_prim_id(sctx);
2876
2877 si_update_common_shader_state(sctx);
2878
2879 if (enable_changed)
2880 sctx->last_tcs = NULL; /* invalidate derived tess state */
2881
2882 si_set_active_descriptors_for_shader(sctx, sel);
2883 }
2884
2885 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2886 {
2887 struct si_context *sctx = (struct si_context *)ctx;
2888 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2889 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2890 struct si_shader_selector *sel = state;
2891 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2892
2893 if (sctx->tes_shader.cso == sel)
2894 return;
2895
2896 sctx->tes_shader.cso = sel;
2897 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2898 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2899 si_update_tess_uses_prim_id(sctx);
2900
2901 si_update_common_shader_state(sctx);
2902 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2903
2904 if (enable_changed) {
2905 si_update_ngg(sctx);
2906 si_shader_change_notify(sctx);
2907 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2908 }
2909 si_update_vs_viewport_state(sctx);
2910 si_set_active_descriptors_for_shader(sctx, sel);
2911 si_update_streamout_state(sctx);
2912 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2913 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2914 }
2915
2916 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2917 {
2918 struct si_context *sctx = (struct si_context *)ctx;
2919 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
2920 struct si_shader_selector *sel = state;
2921
2922 /* skip if supplied shader is one already in use */
2923 if (old_sel == sel)
2924 return;
2925
2926 sctx->ps_shader.cso = sel;
2927 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2928
2929 si_update_common_shader_state(sctx);
2930 if (sel) {
2931 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2932 si_update_tess_uses_prim_id(sctx);
2933
2934 if (!old_sel ||
2935 old_sel->info.colors_written != sel->info.colors_written)
2936 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2937
2938 if (sctx->screen->has_out_of_order_rast &&
2939 (!old_sel ||
2940 old_sel->info.writes_memory != sel->info.writes_memory ||
2941 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
2942 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
2943 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2944 }
2945 si_set_active_descriptors_for_shader(sctx, sel);
2946 si_update_ps_colorbuf0_slot(sctx);
2947 }
2948
2949 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2950 {
2951 if (shader->is_optimized) {
2952 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
2953 &shader->ready);
2954 }
2955
2956 util_queue_fence_destroy(&shader->ready);
2957
2958 if (shader->pm4) {
2959 switch (shader->selector->type) {
2960 case PIPE_SHADER_VERTEX:
2961 if (shader->key.as_ls) {
2962 assert(sctx->chip_class <= GFX8);
2963 si_pm4_delete_state(sctx, ls, shader->pm4);
2964 } else if (shader->key.as_es) {
2965 assert(sctx->chip_class <= GFX8);
2966 si_pm4_delete_state(sctx, es, shader->pm4);
2967 } else {
2968 si_pm4_delete_state(sctx, vs, shader->pm4);
2969 }
2970 break;
2971 case PIPE_SHADER_TESS_CTRL:
2972 si_pm4_delete_state(sctx, hs, shader->pm4);
2973 break;
2974 case PIPE_SHADER_TESS_EVAL:
2975 if (shader->key.as_es) {
2976 assert(sctx->chip_class <= GFX8);
2977 si_pm4_delete_state(sctx, es, shader->pm4);
2978 } else {
2979 si_pm4_delete_state(sctx, vs, shader->pm4);
2980 }
2981 break;
2982 case PIPE_SHADER_GEOMETRY:
2983 if (shader->is_gs_copy_shader)
2984 si_pm4_delete_state(sctx, vs, shader->pm4);
2985 else
2986 si_pm4_delete_state(sctx, gs, shader->pm4);
2987 break;
2988 case PIPE_SHADER_FRAGMENT:
2989 si_pm4_delete_state(sctx, ps, shader->pm4);
2990 break;
2991 }
2992 }
2993
2994 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2995 si_shader_destroy(shader);
2996 free(shader);
2997 }
2998
2999 void si_destroy_shader_selector(struct si_context *sctx,
3000 struct si_shader_selector *sel)
3001 {
3002 struct si_shader *p = sel->first_variant, *c;
3003 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3004 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3005 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3006 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3007 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3008 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3009 };
3010
3011 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3012
3013 if (current_shader[sel->type]->cso == sel) {
3014 current_shader[sel->type]->cso = NULL;
3015 current_shader[sel->type]->current = NULL;
3016 }
3017
3018 while (p) {
3019 c = p->next_variant;
3020 si_delete_shader(sctx, p);
3021 p = c;
3022 }
3023
3024 if (sel->main_shader_part)
3025 si_delete_shader(sctx, sel->main_shader_part);
3026 if (sel->main_shader_part_ls)
3027 si_delete_shader(sctx, sel->main_shader_part_ls);
3028 if (sel->main_shader_part_es)
3029 si_delete_shader(sctx, sel->main_shader_part_es);
3030 if (sel->main_shader_part_ngg)
3031 si_delete_shader(sctx, sel->main_shader_part_ngg);
3032 if (sel->gs_copy_shader)
3033 si_delete_shader(sctx, sel->gs_copy_shader);
3034
3035 util_queue_fence_destroy(&sel->ready);
3036 mtx_destroy(&sel->mutex);
3037 free(sel->tokens);
3038 ralloc_free(sel->nir);
3039 free(sel);
3040 }
3041
3042 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3043 {
3044 struct si_context *sctx = (struct si_context *)ctx;
3045 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3046
3047 si_shader_selector_reference(sctx, &sel, NULL);
3048 }
3049
3050 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3051 struct si_shader *vs, unsigned name,
3052 unsigned index, unsigned interpolate)
3053 {
3054 struct tgsi_shader_info *vsinfo = &vs->selector->info;
3055 unsigned j, offset, ps_input_cntl = 0;
3056
3057 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3058 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3059 name == TGSI_SEMANTIC_PRIMID)
3060 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3061
3062 if (name == TGSI_SEMANTIC_PCOORD ||
3063 (name == TGSI_SEMANTIC_TEXCOORD &&
3064 sctx->sprite_coord_enable & (1 << index))) {
3065 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3066 }
3067
3068 for (j = 0; j < vsinfo->num_outputs; j++) {
3069 if (name == vsinfo->output_semantic_name[j] &&
3070 index == vsinfo->output_semantic_index[j]) {
3071 offset = vs->info.vs_output_param_offset[j];
3072
3073 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3074 /* The input is loaded from parameter memory. */
3075 ps_input_cntl |= S_028644_OFFSET(offset);
3076 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3077 if (offset == AC_EXP_PARAM_UNDEFINED) {
3078 /* This can happen with depth-only rendering. */
3079 offset = 0;
3080 } else {
3081 /* The input is a DEFAULT_VAL constant. */
3082 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3083 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3084 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3085 }
3086
3087 ps_input_cntl = S_028644_OFFSET(0x20) |
3088 S_028644_DEFAULT_VAL(offset);
3089 }
3090 break;
3091 }
3092 }
3093
3094 if (name == TGSI_SEMANTIC_PRIMID)
3095 /* PrimID is written after the last output. */
3096 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3097 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3098 /* No corresponding output found, load defaults into input.
3099 * Don't set any other bits.
3100 * (FLAT_SHADE=1 completely changes behavior) */
3101 ps_input_cntl = S_028644_OFFSET(0x20);
3102 /* D3D 9 behaviour. GL is undefined */
3103 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3104 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3105 }
3106 return ps_input_cntl;
3107 }
3108
3109 static void si_emit_spi_map(struct si_context *sctx)
3110 {
3111 struct si_shader *ps = sctx->ps_shader.current;
3112 struct si_shader *vs = si_get_vs_state(sctx);
3113 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3114 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3115 unsigned spi_ps_input_cntl[32];
3116
3117 if (!ps || !ps->selector->info.num_inputs)
3118 return;
3119
3120 num_interp = si_get_ps_num_interp(ps);
3121 assert(num_interp > 0);
3122
3123 for (i = 0; i < psinfo->num_inputs; i++) {
3124 unsigned name = psinfo->input_semantic_name[i];
3125 unsigned index = psinfo->input_semantic_index[i];
3126 unsigned interpolate = psinfo->input_interpolate[i];
3127
3128 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3129 index, interpolate);
3130
3131 if (name == TGSI_SEMANTIC_COLOR) {
3132 assert(index < ARRAY_SIZE(bcol_interp));
3133 bcol_interp[index] = interpolate;
3134 }
3135 }
3136
3137 if (ps->key.part.ps.prolog.color_two_side) {
3138 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3139
3140 for (i = 0; i < 2; i++) {
3141 if (!(psinfo->colors_read & (0xf << (i * 4))))
3142 continue;
3143
3144 spi_ps_input_cntl[num_written++] =
3145 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3146
3147 }
3148 }
3149 assert(num_interp == num_written);
3150
3151 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3152 /* Dota 2: Only ~16% of SPI map updates set different values. */
3153 /* Talos: Only ~9% of SPI map updates set different values. */
3154 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3155 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3156 spi_ps_input_cntl,
3157 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3158
3159 if (initial_cdw != sctx->gfx_cs->current.cdw)
3160 sctx->context_roll = true;
3161 }
3162
3163 /**
3164 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3165 */
3166 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3167 {
3168 if (sctx->init_config_has_vgt_flush)
3169 return;
3170
3171 /* Done by Vulkan before VGT_FLUSH. */
3172 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3173 si_pm4_cmd_add(sctx->init_config,
3174 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3175 si_pm4_cmd_end(sctx->init_config, false);
3176
3177 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3178 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3179 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3180 si_pm4_cmd_end(sctx->init_config, false);
3181 sctx->init_config_has_vgt_flush = true;
3182 }
3183
3184 /* Initialize state related to ESGS / GSVS ring buffers */
3185 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3186 {
3187 struct si_shader_selector *es =
3188 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3189 struct si_shader_selector *gs = sctx->gs_shader.cso;
3190 struct si_pm4_state *pm4;
3191
3192 /* Chip constants. */
3193 unsigned num_se = sctx->screen->info.max_se;
3194 unsigned wave_size = 64;
3195 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3196 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3197 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3198 */
3199 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3200 unsigned alignment = 256 * num_se;
3201 /* The maximum size is 63.999 MB per SE. */
3202 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3203
3204 /* Calculate the minimum size. */
3205 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3206 wave_size, alignment);
3207
3208 /* These are recommended sizes, not minimum sizes. */
3209 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3210 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3211 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3212 gs->max_gsvs_emit_size;
3213
3214 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3215 esgs_ring_size = align(esgs_ring_size, alignment);
3216 gsvs_ring_size = align(gsvs_ring_size, alignment);
3217
3218 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3219 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3220
3221 /* Some rings don't have to be allocated if shaders don't use them.
3222 * (e.g. no varyings between ES and GS or GS and VS)
3223 *
3224 * GFX9 doesn't have the ESGS ring.
3225 */
3226 bool update_esgs = sctx->chip_class <= GFX8 &&
3227 esgs_ring_size &&
3228 (!sctx->esgs_ring ||
3229 sctx->esgs_ring->width0 < esgs_ring_size);
3230 bool update_gsvs = gsvs_ring_size &&
3231 (!sctx->gsvs_ring ||
3232 sctx->gsvs_ring->width0 < gsvs_ring_size);
3233
3234 if (!update_esgs && !update_gsvs)
3235 return true;
3236
3237 if (update_esgs) {
3238 pipe_resource_reference(&sctx->esgs_ring, NULL);
3239 sctx->esgs_ring =
3240 pipe_aligned_buffer_create(sctx->b.screen,
3241 SI_RESOURCE_FLAG_UNMAPPABLE,
3242 PIPE_USAGE_DEFAULT,
3243 esgs_ring_size, alignment);
3244 if (!sctx->esgs_ring)
3245 return false;
3246 }
3247
3248 if (update_gsvs) {
3249 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3250 sctx->gsvs_ring =
3251 pipe_aligned_buffer_create(sctx->b.screen,
3252 SI_RESOURCE_FLAG_UNMAPPABLE,
3253 PIPE_USAGE_DEFAULT,
3254 gsvs_ring_size, alignment);
3255 if (!sctx->gsvs_ring)
3256 return false;
3257 }
3258
3259 /* Create the "init_config_gs_rings" state. */
3260 pm4 = CALLOC_STRUCT(si_pm4_state);
3261 if (!pm4)
3262 return false;
3263
3264 if (sctx->chip_class >= GFX7) {
3265 if (sctx->esgs_ring) {
3266 assert(sctx->chip_class <= GFX8);
3267 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3268 sctx->esgs_ring->width0 / 256);
3269 }
3270 if (sctx->gsvs_ring)
3271 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3272 sctx->gsvs_ring->width0 / 256);
3273 } else {
3274 if (sctx->esgs_ring)
3275 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3276 sctx->esgs_ring->width0 / 256);
3277 if (sctx->gsvs_ring)
3278 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3279 sctx->gsvs_ring->width0 / 256);
3280 }
3281
3282 /* Set the state. */
3283 if (sctx->init_config_gs_rings)
3284 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3285 sctx->init_config_gs_rings = pm4;
3286
3287 if (!sctx->init_config_has_vgt_flush) {
3288 si_init_config_add_vgt_flush(sctx);
3289 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3290 }
3291
3292 /* Flush the context to re-emit both init_config states. */
3293 sctx->initial_gfx_cs_size = 0; /* force flush */
3294 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3295
3296 /* Set ring bindings. */
3297 if (sctx->esgs_ring) {
3298 assert(sctx->chip_class <= GFX8);
3299 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3300 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3301 true, true, 4, 64, 0);
3302 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3303 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3304 false, false, 0, 0, 0);
3305 }
3306 if (sctx->gsvs_ring) {
3307 si_set_ring_buffer(sctx, SI_RING_GSVS,
3308 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3309 false, false, 0, 0, 0);
3310 }
3311
3312 return true;
3313 }
3314
3315 static void si_shader_lock(struct si_shader *shader)
3316 {
3317 mtx_lock(&shader->selector->mutex);
3318 if (shader->previous_stage_sel) {
3319 assert(shader->previous_stage_sel != shader->selector);
3320 mtx_lock(&shader->previous_stage_sel->mutex);
3321 }
3322 }
3323
3324 static void si_shader_unlock(struct si_shader *shader)
3325 {
3326 if (shader->previous_stage_sel)
3327 mtx_unlock(&shader->previous_stage_sel->mutex);
3328 mtx_unlock(&shader->selector->mutex);
3329 }
3330
3331 /**
3332 * @returns 1 if \p sel has been updated to use a new scratch buffer
3333 * 0 if not
3334 * < 0 if there was a failure
3335 */
3336 static int si_update_scratch_buffer(struct si_context *sctx,
3337 struct si_shader *shader)
3338 {
3339 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3340
3341 if (!shader)
3342 return 0;
3343
3344 /* This shader doesn't need a scratch buffer */
3345 if (shader->config.scratch_bytes_per_wave == 0)
3346 return 0;
3347
3348 /* Prevent race conditions when updating:
3349 * - si_shader::scratch_bo
3350 * - si_shader::binary::code
3351 * - si_shader::previous_stage::binary::code.
3352 */
3353 si_shader_lock(shader);
3354
3355 /* This shader is already configured to use the current
3356 * scratch buffer. */
3357 if (shader->scratch_bo == sctx->scratch_buffer) {
3358 si_shader_unlock(shader);
3359 return 0;
3360 }
3361
3362 assert(sctx->scratch_buffer);
3363
3364 /* Replace the shader bo with a new bo that has the relocs applied. */
3365 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3366 si_shader_unlock(shader);
3367 return -1;
3368 }
3369
3370 /* Update the shader state to use the new shader bo. */
3371 si_shader_init_pm4_state(sctx->screen, shader);
3372
3373 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3374
3375 si_shader_unlock(shader);
3376 return 1;
3377 }
3378
3379 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3380 {
3381 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3382 }
3383
3384 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3385 {
3386 return shader ? shader->config.scratch_bytes_per_wave : 0;
3387 }
3388
3389 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3390 {
3391 if (!sctx->tes_shader.cso)
3392 return NULL; /* tessellation disabled */
3393
3394 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3395 sctx->fixed_func_tcs_shader.current;
3396 }
3397
3398 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3399 {
3400 unsigned bytes = 0;
3401
3402 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3403 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3404 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3405 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3406
3407 if (sctx->tes_shader.cso) {
3408 struct si_shader *tcs = si_get_tcs_current(sctx);
3409
3410 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3411 }
3412 return bytes;
3413 }
3414
3415 static bool si_update_scratch_relocs(struct si_context *sctx)
3416 {
3417 struct si_shader *tcs = si_get_tcs_current(sctx);
3418 int r;
3419
3420 /* Update the shaders, so that they are using the latest scratch.
3421 * The scratch buffer may have been changed since these shaders were
3422 * last used, so we still need to try to update them, even if they
3423 * require scratch buffers smaller than the current size.
3424 */
3425 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3426 if (r < 0)
3427 return false;
3428 if (r == 1)
3429 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3430
3431 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3432 if (r < 0)
3433 return false;
3434 if (r == 1)
3435 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3436
3437 r = si_update_scratch_buffer(sctx, tcs);
3438 if (r < 0)
3439 return false;
3440 if (r == 1)
3441 si_pm4_bind_state(sctx, hs, tcs->pm4);
3442
3443 /* VS can be bound as LS, ES, or VS. */
3444 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3445 if (r < 0)
3446 return false;
3447 if (r == 1) {
3448 if (sctx->tes_shader.current)
3449 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3450 else if (sctx->gs_shader.current)
3451 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3452 else
3453 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3454 }
3455
3456 /* TES can be bound as ES or VS. */
3457 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3458 if (r < 0)
3459 return false;
3460 if (r == 1) {
3461 if (sctx->gs_shader.current)
3462 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3463 else
3464 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3465 }
3466
3467 return true;
3468 }
3469
3470 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3471 {
3472 unsigned current_scratch_buffer_size =
3473 si_get_current_scratch_buffer_size(sctx);
3474 unsigned scratch_bytes_per_wave =
3475 si_get_max_scratch_bytes_per_wave(sctx);
3476 unsigned scratch_needed_size = scratch_bytes_per_wave *
3477 sctx->scratch_waves;
3478 unsigned spi_tmpring_size;
3479
3480 if (scratch_needed_size > 0) {
3481 if (scratch_needed_size > current_scratch_buffer_size) {
3482 /* Create a bigger scratch buffer */
3483 si_resource_reference(&sctx->scratch_buffer, NULL);
3484
3485 sctx->scratch_buffer =
3486 si_aligned_buffer_create(&sctx->screen->b,
3487 SI_RESOURCE_FLAG_UNMAPPABLE,
3488 PIPE_USAGE_DEFAULT,
3489 scratch_needed_size, 256);
3490 if (!sctx->scratch_buffer)
3491 return false;
3492
3493 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3494 si_context_add_resource_size(sctx,
3495 &sctx->scratch_buffer->b.b);
3496 }
3497
3498 if (!si_update_scratch_relocs(sctx))
3499 return false;
3500 }
3501
3502 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3503 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3504 "scratch size should already be aligned correctly.");
3505
3506 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3507 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3508 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3509 sctx->spi_tmpring_size = spi_tmpring_size;
3510 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3511 }
3512 return true;
3513 }
3514
3515 static void si_init_tess_factor_ring(struct si_context *sctx)
3516 {
3517 assert(!sctx->tess_rings);
3518
3519 /* The address must be aligned to 2^19, because the shader only
3520 * receives the high 13 bits.
3521 */
3522 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3523 SI_RESOURCE_FLAG_32BIT,
3524 PIPE_USAGE_DEFAULT,
3525 sctx->screen->tess_offchip_ring_size +
3526 sctx->screen->tess_factor_ring_size,
3527 1 << 19);
3528 if (!sctx->tess_rings)
3529 return;
3530
3531 si_init_config_add_vgt_flush(sctx);
3532
3533 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3534 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3535
3536 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3537 sctx->screen->tess_offchip_ring_size;
3538
3539 /* Append these registers to the init config state. */
3540 if (sctx->chip_class >= GFX7) {
3541 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3542 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3543 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3544 factor_va >> 8);
3545 if (sctx->chip_class >= GFX9)
3546 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3547 S_030944_BASE_HI(factor_va >> 40));
3548 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3549 sctx->screen->vgt_hs_offchip_param);
3550 } else {
3551 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3552 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3553 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3554 factor_va >> 8);
3555 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3556 sctx->screen->vgt_hs_offchip_param);
3557 }
3558
3559 /* Flush the context to re-emit the init_config state.
3560 * This is done only once in a lifetime of a context.
3561 */
3562 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3563 sctx->initial_gfx_cs_size = 0; /* force flush */
3564 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3565 }
3566
3567 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3568 union si_vgt_stages_key key)
3569 {
3570 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3571 uint32_t stages = 0;
3572
3573 if (key.u.tess) {
3574 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3575 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3576
3577 if (key.u.gs)
3578 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3579 S_028B54_GS_EN(1);
3580 else if (key.u.ngg)
3581 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3582 else
3583 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3584 } else if (key.u.gs) {
3585 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3586 S_028B54_GS_EN(1);
3587 } else if (key.u.ngg) {
3588 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3589 }
3590
3591 if (key.u.ngg) {
3592 stages |= S_028B54_PRIMGEN_EN(1);
3593 if (key.u.streamout)
3594 stages |= S_028B54_NGG_WAVE_ID_EN(1);
3595 } else if (key.u.gs)
3596 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3597
3598 if (screen->info.chip_class >= GFX9)
3599 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3600
3601 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3602 return pm4;
3603 }
3604
3605 static void si_update_vgt_shader_config(struct si_context *sctx,
3606 union si_vgt_stages_key key)
3607 {
3608 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3609
3610 if (unlikely(!*pm4))
3611 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3612 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3613 }
3614
3615 bool si_update_shaders(struct si_context *sctx)
3616 {
3617 struct pipe_context *ctx = (struct pipe_context*)sctx;
3618 struct si_compiler_ctx_state compiler_state;
3619 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3620 struct si_shader *old_vs = si_get_vs_state(sctx);
3621 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3622 struct si_shader *old_ps = sctx->ps_shader.current;
3623 union si_vgt_stages_key key;
3624 unsigned old_spi_shader_col_format =
3625 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3626 int r;
3627
3628 compiler_state.compiler = &sctx->compiler;
3629 compiler_state.debug = sctx->debug;
3630 compiler_state.is_debug_context = sctx->is_debug;
3631
3632 key.index = 0;
3633
3634 if (sctx->tes_shader.cso)
3635 key.u.tess = 1;
3636 if (sctx->gs_shader.cso)
3637 key.u.gs = 1;
3638
3639 if (sctx->chip_class >= GFX10) {
3640 key.u.ngg = sctx->ngg;
3641
3642 if (sctx->gs_shader.cso)
3643 key.u.streamout = !!sctx->gs_shader.cso->so.num_outputs;
3644 else if (sctx->tes_shader.cso)
3645 key.u.streamout = !!sctx->tes_shader.cso->so.num_outputs;
3646 else
3647 key.u.streamout = !!sctx->vs_shader.cso->so.num_outputs;
3648 }
3649
3650 /* Update TCS and TES. */
3651 if (sctx->tes_shader.cso) {
3652 if (!sctx->tess_rings) {
3653 si_init_tess_factor_ring(sctx);
3654 if (!sctx->tess_rings)
3655 return false;
3656 }
3657
3658 if (sctx->tcs_shader.cso) {
3659 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3660 &compiler_state);
3661 if (r)
3662 return false;
3663 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3664 } else {
3665 if (!sctx->fixed_func_tcs_shader.cso) {
3666 sctx->fixed_func_tcs_shader.cso =
3667 si_create_fixed_func_tcs(sctx);
3668 if (!sctx->fixed_func_tcs_shader.cso)
3669 return false;
3670 }
3671
3672 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3673 key, &compiler_state);
3674 if (r)
3675 return false;
3676 si_pm4_bind_state(sctx, hs,
3677 sctx->fixed_func_tcs_shader.current->pm4);
3678 }
3679
3680 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3681 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3682 if (r)
3683 return false;
3684
3685 if (sctx->gs_shader.cso) {
3686 /* TES as ES */
3687 assert(sctx->chip_class <= GFX8);
3688 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3689 } else if (key.u.ngg) {
3690 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3691 } else {
3692 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3693 }
3694 }
3695 } else {
3696 if (sctx->chip_class <= GFX8)
3697 si_pm4_bind_state(sctx, ls, NULL);
3698 si_pm4_bind_state(sctx, hs, NULL);
3699 }
3700
3701 /* Update GS. */
3702 if (sctx->gs_shader.cso) {
3703 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3704 if (r)
3705 return false;
3706 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3707 if (!key.u.ngg) {
3708 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3709
3710 if (!si_update_gs_ring_buffers(sctx))
3711 return false;
3712 } else {
3713 si_pm4_bind_state(sctx, vs, NULL);
3714 }
3715 } else {
3716 if (!key.u.ngg) {
3717 si_pm4_bind_state(sctx, gs, NULL);
3718 if (sctx->chip_class <= GFX8)
3719 si_pm4_bind_state(sctx, es, NULL);
3720 }
3721 }
3722
3723 /* Update VS. */
3724 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
3725 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
3726 if (r)
3727 return false;
3728
3729 if (!key.u.tess && !key.u.gs) {
3730 if (key.u.ngg) {
3731 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3732 si_pm4_bind_state(sctx, vs, NULL);
3733 } else {
3734 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3735 }
3736 } else if (sctx->tes_shader.cso) {
3737 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3738 } else {
3739 assert(sctx->gs_shader.cso);
3740 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3741 }
3742 }
3743
3744 si_update_vgt_shader_config(sctx, key);
3745
3746 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3747 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3748
3749 if (sctx->ps_shader.cso) {
3750 unsigned db_shader_control;
3751
3752 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
3753 if (r)
3754 return false;
3755 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3756
3757 db_shader_control =
3758 sctx->ps_shader.cso->db_shader_control |
3759 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3760
3761 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3762 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3763 sctx->flatshade != rs->flatshade) {
3764 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3765 sctx->flatshade = rs->flatshade;
3766 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3767 }
3768
3769 if (sctx->screen->rbplus_allowed &&
3770 si_pm4_state_changed(sctx, ps) &&
3771 (!old_ps ||
3772 old_spi_shader_col_format !=
3773 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3774 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3775
3776 if (sctx->ps_db_shader_control != db_shader_control) {
3777 sctx->ps_db_shader_control = db_shader_control;
3778 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3779 if (sctx->screen->dpbb_allowed)
3780 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3781 }
3782
3783 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3784 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3785 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3786
3787 if (sctx->chip_class == GFX6)
3788 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3789
3790 if (sctx->framebuffer.nr_samples <= 1)
3791 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3792 }
3793 }
3794
3795 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3796 si_pm4_state_enabled_and_changed(sctx, hs) ||
3797 si_pm4_state_enabled_and_changed(sctx, es) ||
3798 si_pm4_state_enabled_and_changed(sctx, gs) ||
3799 si_pm4_state_enabled_and_changed(sctx, vs) ||
3800 si_pm4_state_enabled_and_changed(sctx, ps)) {
3801 if (!si_update_spi_tmpring_size(sctx))
3802 return false;
3803 }
3804
3805 if (sctx->chip_class >= GFX7) {
3806 if (si_pm4_state_enabled_and_changed(sctx, ls))
3807 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3808 else if (!sctx->queued.named.ls)
3809 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3810
3811 if (si_pm4_state_enabled_and_changed(sctx, hs))
3812 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3813 else if (!sctx->queued.named.hs)
3814 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3815
3816 if (si_pm4_state_enabled_and_changed(sctx, es))
3817 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3818 else if (!sctx->queued.named.es)
3819 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3820
3821 if (si_pm4_state_enabled_and_changed(sctx, gs))
3822 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3823 else if (!sctx->queued.named.gs)
3824 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3825
3826 if (si_pm4_state_enabled_and_changed(sctx, vs))
3827 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3828 else if (!sctx->queued.named.vs)
3829 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3830
3831 if (si_pm4_state_enabled_and_changed(sctx, ps))
3832 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3833 else if (!sctx->queued.named.ps)
3834 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3835 }
3836
3837 sctx->do_update_shaders = false;
3838 return true;
3839 }
3840
3841 static void si_emit_scratch_state(struct si_context *sctx)
3842 {
3843 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3844
3845 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3846 sctx->spi_tmpring_size);
3847
3848 if (sctx->scratch_buffer) {
3849 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3850 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3851 RADEON_PRIO_SCRATCH_BUFFER);
3852 }
3853 }
3854
3855 void si_init_shader_functions(struct si_context *sctx)
3856 {
3857 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
3858 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
3859
3860 sctx->b.create_vs_state = si_create_shader_selector;
3861 sctx->b.create_tcs_state = si_create_shader_selector;
3862 sctx->b.create_tes_state = si_create_shader_selector;
3863 sctx->b.create_gs_state = si_create_shader_selector;
3864 sctx->b.create_fs_state = si_create_shader_selector;
3865
3866 sctx->b.bind_vs_state = si_bind_vs_shader;
3867 sctx->b.bind_tcs_state = si_bind_tcs_shader;
3868 sctx->b.bind_tes_state = si_bind_tes_shader;
3869 sctx->b.bind_gs_state = si_bind_gs_shader;
3870 sctx->b.bind_fs_state = si_bind_ps_shader;
3871
3872 sctx->b.delete_vs_state = si_delete_shader_selector;
3873 sctx->b.delete_tcs_state = si_delete_shader_selector;
3874 sctx->b.delete_tes_state = si_delete_shader_selector;
3875 sctx->b.delete_gs_state = si_delete_shader_selector;
3876 sctx->b.delete_fs_state = si_delete_shader_selector;
3877 }