2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
29 #include "si_shader.h"
31 #include "radeon/r600_cs.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/u_memory.h"
36 #include "util/u_simple_shaders.h"
38 static void si_set_tesseval_regs(struct si_shader
*shader
,
39 struct si_pm4_state
*pm4
)
41 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
42 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
43 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
44 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
45 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
46 unsigned type
, partitioning
, topology
;
48 switch (tes_prim_mode
) {
50 type
= V_028B6C_TESS_ISOLINE
;
52 case PIPE_PRIM_TRIANGLES
:
53 type
= V_028B6C_TESS_TRIANGLE
;
56 type
= V_028B6C_TESS_QUAD
;
63 switch (tes_spacing
) {
64 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
65 partitioning
= V_028B6C_PART_FRAC_ODD
;
67 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
68 partitioning
= V_028B6C_PART_FRAC_EVEN
;
70 case PIPE_TESS_SPACING_EQUAL
:
71 partitioning
= V_028B6C_PART_INTEGER
;
79 topology
= V_028B6C_OUTPUT_POINT
;
80 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
81 topology
= V_028B6C_OUTPUT_LINE
;
82 else if (tes_vertex_order_cw
)
83 /* for some reason, this must be the other way around */
84 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
86 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
88 si_pm4_set_reg(pm4
, R_028B6C_VGT_TF_PARAM
,
90 S_028B6C_PARTITIONING(partitioning
) |
91 S_028B6C_TOPOLOGY(topology
));
94 static void si_shader_ls(struct si_shader
*shader
)
96 struct si_pm4_state
*pm4
;
97 unsigned num_sgprs
, num_user_sgprs
;
98 unsigned vgpr_comp_cnt
;
101 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
105 va
= shader
->bo
->gpu_address
;
106 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_USER_SHADER
);
108 /* We need at least 2 components for LS.
109 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
110 vgpr_comp_cnt
= shader
->uses_instanceid
? 3 : 1;
112 num_user_sgprs
= SI_LS_NUM_USER_SGPR
;
113 num_sgprs
= shader
->num_sgprs
;
114 if (num_user_sgprs
> num_sgprs
) {
115 /* Last 2 reserved SGPRs are used for VCC */
116 num_sgprs
= num_user_sgprs
+ 2;
118 assert(num_sgprs
<= 104);
120 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
121 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, va
>> 40);
123 shader
->ls_rsrc1
= S_00B528_VGPRS((shader
->num_vgprs
- 1) / 4) |
124 S_00B528_SGPRS((num_sgprs
- 1) / 8) |
125 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
126 S_00B528_DX10_CLAMP(shader
->dx10_clamp_mode
);
127 shader
->ls_rsrc2
= S_00B52C_USER_SGPR(num_user_sgprs
) |
128 S_00B52C_SCRATCH_EN(shader
->scratch_bytes_per_wave
> 0);
131 static void si_shader_hs(struct si_shader
*shader
)
133 struct si_pm4_state
*pm4
;
134 unsigned num_sgprs
, num_user_sgprs
;
137 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
141 va
= shader
->bo
->gpu_address
;
142 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_USER_SHADER
);
144 num_user_sgprs
= SI_TCS_NUM_USER_SGPR
;
145 num_sgprs
= shader
->num_sgprs
;
146 /* One SGPR after user SGPRs is pre-loaded with tessellation factor
148 if ((num_user_sgprs
+ 1) > num_sgprs
) {
149 /* Last 2 reserved SGPRs are used for VCC */
150 num_sgprs
= num_user_sgprs
+ 1 + 2;
152 assert(num_sgprs
<= 104);
154 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
155 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, va
>> 40);
156 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
157 S_00B428_VGPRS((shader
->num_vgprs
- 1) / 4) |
158 S_00B428_SGPRS((num_sgprs
- 1) / 8) |
159 S_00B428_DX10_CLAMP(shader
->dx10_clamp_mode
));
160 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
161 S_00B42C_USER_SGPR(num_user_sgprs
) |
162 S_00B42C_SCRATCH_EN(shader
->scratch_bytes_per_wave
> 0));
165 static void si_shader_es(struct si_shader
*shader
)
167 struct si_pm4_state
*pm4
;
168 unsigned num_sgprs
, num_user_sgprs
;
169 unsigned vgpr_comp_cnt
;
172 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
177 va
= shader
->bo
->gpu_address
;
178 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_USER_SHADER
);
180 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
181 vgpr_comp_cnt
= shader
->uses_instanceid
? 3 : 0;
182 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
183 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
184 vgpr_comp_cnt
= 3; /* all components are needed for TES */
185 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
187 unreachable("invalid shader selector type");
189 num_sgprs
= shader
->num_sgprs
;
190 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
191 if ((num_user_sgprs
+ 1) > num_sgprs
) {
192 /* Last 2 reserved SGPRs are used for VCC */
193 num_sgprs
= num_user_sgprs
+ 1 + 2;
195 assert(num_sgprs
<= 104);
197 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
198 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
199 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
200 S_00B328_VGPRS((shader
->num_vgprs
- 1) / 4) |
201 S_00B328_SGPRS((num_sgprs
- 1) / 8) |
202 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
203 S_00B328_DX10_CLAMP(shader
->dx10_clamp_mode
));
204 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
205 S_00B32C_USER_SGPR(num_user_sgprs
) |
206 S_00B32C_SCRATCH_EN(shader
->scratch_bytes_per_wave
> 0));
208 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
209 si_set_tesseval_regs(shader
, pm4
);
212 static unsigned si_gs_get_max_stream(struct si_shader
*shader
)
214 struct pipe_stream_output_info
*so
= &shader
->selector
->so
;
215 unsigned max_stream
= 0, i
;
217 if (so
->num_outputs
== 0)
220 for (i
= 0; i
< so
->num_outputs
; i
++) {
221 if (so
->output
[i
].stream
> max_stream
)
222 max_stream
= so
->output
[i
].stream
;
227 static void si_shader_gs(struct si_shader
*shader
)
229 unsigned gs_vert_itemsize
= shader
->selector
->info
.num_outputs
* 16;
230 unsigned gs_max_vert_out
= shader
->selector
->gs_max_out_vertices
;
231 unsigned gsvs_itemsize
= (gs_vert_itemsize
* gs_max_vert_out
) >> 2;
232 unsigned gs_num_invocations
= shader
->selector
->gs_num_invocations
;
234 struct si_pm4_state
*pm4
;
235 unsigned num_sgprs
, num_user_sgprs
;
237 unsigned max_stream
= si_gs_get_max_stream(shader
);
239 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
240 assert(gsvs_itemsize
< (1 << 15));
242 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
247 if (gs_max_vert_out
<= 128) {
248 cut_mode
= V_028A40_GS_CUT_128
;
249 } else if (gs_max_vert_out
<= 256) {
250 cut_mode
= V_028A40_GS_CUT_256
;
251 } else if (gs_max_vert_out
<= 512) {
252 cut_mode
= V_028A40_GS_CUT_512
;
254 assert(gs_max_vert_out
<= 1024);
255 cut_mode
= V_028A40_GS_CUT_1024
;
258 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
,
259 S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
260 S_028A40_CUT_MODE(cut_mode
)|
261 S_028A40_ES_WRITE_OPTIMIZE(1) |
262 S_028A40_GS_WRITE_OPTIMIZE(1));
264 si_pm4_set_reg(pm4
, R_028A60_VGT_GSVS_RING_OFFSET_1
, gsvs_itemsize
);
265 si_pm4_set_reg(pm4
, R_028A64_VGT_GSVS_RING_OFFSET_2
, gsvs_itemsize
* ((max_stream
>= 2) ? 2 : 1));
266 si_pm4_set_reg(pm4
, R_028A68_VGT_GSVS_RING_OFFSET_3
, gsvs_itemsize
* ((max_stream
>= 3) ? 3 : 1));
268 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
269 util_bitcount64(shader
->selector
->inputs_read
) * (16 >> 2));
270 si_pm4_set_reg(pm4
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, gsvs_itemsize
* (max_stream
+ 1));
272 si_pm4_set_reg(pm4
, R_028B38_VGT_GS_MAX_VERT_OUT
, gs_max_vert_out
);
274 si_pm4_set_reg(pm4
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, gs_vert_itemsize
>> 2);
275 si_pm4_set_reg(pm4
, R_028B60_VGT_GS_VERT_ITEMSIZE_1
, (max_stream
>= 1) ? gs_vert_itemsize
>> 2 : 0);
276 si_pm4_set_reg(pm4
, R_028B64_VGT_GS_VERT_ITEMSIZE_2
, (max_stream
>= 2) ? gs_vert_itemsize
>> 2 : 0);
277 si_pm4_set_reg(pm4
, R_028B68_VGT_GS_VERT_ITEMSIZE_3
, (max_stream
>= 3) ? gs_vert_itemsize
>> 2 : 0);
279 si_pm4_set_reg(pm4
, R_028B90_VGT_GS_INSTANCE_CNT
,
280 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
281 S_028B90_ENABLE(gs_num_invocations
> 0));
283 va
= shader
->bo
->gpu_address
;
284 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_USER_SHADER
);
285 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
286 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, va
>> 40);
288 num_user_sgprs
= SI_GS_NUM_USER_SGPR
;
289 num_sgprs
= shader
->num_sgprs
;
290 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
291 if ((num_user_sgprs
+ 2) > num_sgprs
) {
292 /* Last 2 reserved SGPRs are used for VCC */
293 num_sgprs
= num_user_sgprs
+ 2 + 2;
295 assert(num_sgprs
<= 104);
297 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
298 S_00B228_VGPRS((shader
->num_vgprs
- 1) / 4) |
299 S_00B228_SGPRS((num_sgprs
- 1) / 8) |
300 S_00B228_DX10_CLAMP(shader
->dx10_clamp_mode
));
301 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
302 S_00B22C_USER_SGPR(num_user_sgprs
) |
303 S_00B22C_SCRATCH_EN(shader
->scratch_bytes_per_wave
> 0));
306 static void si_shader_vs(struct si_shader
*shader
)
308 struct si_pm4_state
*pm4
;
309 unsigned num_sgprs
, num_user_sgprs
;
310 unsigned nparams
, vgpr_comp_cnt
;
312 unsigned window_space
=
313 shader
->selector
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
314 bool enable_prim_id
= si_vs_exports_prim_id(shader
);
316 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
321 /* If this is the GS copy shader, the GS state writes this register.
322 * Otherwise, the VS state writes it.
324 if (!shader
->is_gs_copy_shader
) {
325 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
,
326 S_028A40_MODE(enable_prim_id
? V_028A40_GS_SCENARIO_A
: 0));
327 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, enable_prim_id
);
329 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
331 va
= shader
->bo
->gpu_address
;
332 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_USER_SHADER
);
334 if (shader
->is_gs_copy_shader
) {
335 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
336 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
337 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
338 vgpr_comp_cnt
= shader
->uses_instanceid
? 3 : (enable_prim_id
? 2 : 0);
339 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
340 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
341 vgpr_comp_cnt
= 3; /* all components are needed for TES */
342 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
344 unreachable("invalid shader selector type");
346 num_sgprs
= shader
->num_sgprs
;
347 if (num_user_sgprs
> num_sgprs
) {
348 /* Last 2 reserved SGPRs are used for VCC */
349 num_sgprs
= num_user_sgprs
+ 2;
351 assert(num_sgprs
<= 104);
353 /* VS is required to export at least one param. */
354 nparams
= MAX2(shader
->nr_param_exports
, 1);
355 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
356 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
358 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
359 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
360 S_02870C_POS1_EXPORT_FORMAT(shader
->nr_pos_exports
> 1 ?
361 V_02870C_SPI_SHADER_4COMP
:
362 V_02870C_SPI_SHADER_NONE
) |
363 S_02870C_POS2_EXPORT_FORMAT(shader
->nr_pos_exports
> 2 ?
364 V_02870C_SPI_SHADER_4COMP
:
365 V_02870C_SPI_SHADER_NONE
) |
366 S_02870C_POS3_EXPORT_FORMAT(shader
->nr_pos_exports
> 3 ?
367 V_02870C_SPI_SHADER_4COMP
:
368 V_02870C_SPI_SHADER_NONE
));
370 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
371 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, va
>> 40);
372 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
373 S_00B128_VGPRS((shader
->num_vgprs
- 1) / 4) |
374 S_00B128_SGPRS((num_sgprs
- 1) / 8) |
375 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
376 S_00B128_DX10_CLAMP(shader
->dx10_clamp_mode
));
377 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
378 S_00B12C_USER_SGPR(num_user_sgprs
) |
379 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
380 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
381 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
382 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
383 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
) |
384 S_00B12C_SCRATCH_EN(shader
->scratch_bytes_per_wave
> 0));
386 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
387 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
389 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
390 S_028818_VTX_W0_FMT(1) |
391 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
392 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
393 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
395 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
396 si_set_tesseval_regs(shader
, pm4
);
399 static void si_shader_ps(struct si_shader
*shader
)
401 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
402 struct si_pm4_state
*pm4
;
403 unsigned i
, spi_ps_in_control
;
404 unsigned num_sgprs
, num_user_sgprs
;
405 unsigned spi_baryc_cntl
= 0;
408 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
413 for (i
= 0; i
< info
->num_inputs
; i
++) {
414 switch (info
->input_semantic_name
[i
]) {
415 case TGSI_SEMANTIC_POSITION
:
416 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
418 * 0 -> Position = pixel center (default)
419 * 1 -> Position = pixel centroid
420 * 2 -> Position = at sample position
422 switch (info
->input_interpolate_loc
[i
]) {
423 case TGSI_INTERPOLATE_LOC_CENTROID
:
424 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(1);
426 case TGSI_INTERPOLATE_LOC_SAMPLE
:
427 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
431 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
432 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
433 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
438 spi_ps_in_control
= S_0286D8_NUM_INTERP(shader
->nparam
) |
439 S_0286D8_BC_OPTIMIZE_DISABLE(1);
441 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
442 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
444 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
, shader
->spi_shader_z_format
);
445 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
,
446 shader
->spi_shader_col_format
);
447 si_pm4_set_reg(pm4
, R_02823C_CB_SHADER_MASK
, shader
->cb_shader_mask
);
449 va
= shader
->bo
->gpu_address
;
450 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_USER_SHADER
);
451 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
452 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, va
>> 40);
454 num_user_sgprs
= SI_PS_NUM_USER_SGPR
;
455 num_sgprs
= shader
->num_sgprs
;
456 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
457 if ((num_user_sgprs
+ 1) > num_sgprs
) {
458 /* Last 2 reserved SGPRs are used for VCC */
459 num_sgprs
= num_user_sgprs
+ 1 + 2;
461 assert(num_sgprs
<= 104);
463 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
464 S_00B028_VGPRS((shader
->num_vgprs
- 1) / 4) |
465 S_00B028_SGPRS((num_sgprs
- 1) / 8) |
466 S_00B028_DX10_CLAMP(shader
->dx10_clamp_mode
));
467 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
468 S_00B02C_EXTRA_LDS_SIZE(shader
->lds_size
) |
469 S_00B02C_USER_SGPR(num_user_sgprs
) |
470 S_00B32C_SCRATCH_EN(shader
->scratch_bytes_per_wave
> 0));
473 static void si_shader_init_pm4_state(struct si_shader
*shader
)
477 si_pm4_free_state_simple(shader
->pm4
);
479 switch (shader
->selector
->type
) {
480 case PIPE_SHADER_VERTEX
:
481 if (shader
->key
.vs
.as_ls
)
482 si_shader_ls(shader
);
483 else if (shader
->key
.vs
.as_es
)
484 si_shader_es(shader
);
486 si_shader_vs(shader
);
488 case PIPE_SHADER_TESS_CTRL
:
489 si_shader_hs(shader
);
491 case PIPE_SHADER_TESS_EVAL
:
492 if (shader
->key
.tes
.as_es
)
493 si_shader_es(shader
);
495 si_shader_vs(shader
);
497 case PIPE_SHADER_GEOMETRY
:
498 si_shader_gs(shader
);
499 si_shader_vs(shader
->gs_copy_shader
);
501 case PIPE_SHADER_FRAGMENT
:
502 si_shader_ps(shader
);
509 /* Compute the key for the hw shader variant */
510 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
511 struct si_shader_selector
*sel
,
512 union si_shader_key
*key
)
514 struct si_context
*sctx
= (struct si_context
*)ctx
;
517 memset(key
, 0, sizeof(*key
));
520 case PIPE_SHADER_VERTEX
:
521 if (sctx
->vertex_elements
)
522 for (i
= 0; i
< sctx
->vertex_elements
->count
; ++i
)
523 key
->vs
.instance_divisors
[i
] =
524 sctx
->vertex_elements
->elements
[i
].instance_divisor
;
526 if (sctx
->tes_shader
)
528 else if (sctx
->gs_shader
) {
530 key
->vs
.es_enabled_outputs
= sctx
->gs_shader
->inputs_read
;
533 if (!sctx
->gs_shader
&& sctx
->ps_shader
&&
534 sctx
->ps_shader
->info
.uses_primid
)
535 key
->vs
.export_prim_id
= 1;
537 case PIPE_SHADER_TESS_CTRL
:
539 sctx
->tes_shader
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
541 case PIPE_SHADER_TESS_EVAL
:
542 if (sctx
->gs_shader
) {
544 key
->tes
.es_enabled_outputs
= sctx
->gs_shader
->inputs_read
;
545 } else if (sctx
->ps_shader
&& sctx
->ps_shader
->info
.uses_primid
)
546 key
->tes
.export_prim_id
= 1;
548 case PIPE_SHADER_GEOMETRY
:
550 case PIPE_SHADER_FRAGMENT
: {
551 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
553 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
554 key
->ps
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
555 key
->ps
.export_16bpc
= sctx
->framebuffer
.export_16bpc
;
558 bool is_poly
= (sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES
&&
559 sctx
->current_rast_prim
<= PIPE_PRIM_POLYGON
) ||
560 sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES_ADJACENCY
;
561 bool is_line
= !is_poly
&& sctx
->current_rast_prim
!= PIPE_PRIM_POINTS
;
563 key
->ps
.color_two_side
= rs
->two_side
;
565 if (sctx
->queued
.named
.blend
) {
566 key
->ps
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
567 rs
->multisample_enable
&&
568 !sctx
->framebuffer
.cb0_is_integer
;
571 key
->ps
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
572 key
->ps
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
573 (is_line
&& rs
->line_smooth
)) &&
574 sctx
->framebuffer
.nr_samples
<= 1;
577 key
->ps
.alpha_func
= PIPE_FUNC_ALWAYS
;
578 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
579 if (sctx
->queued
.named
.dsa
&&
580 !sctx
->framebuffer
.cb0_is_integer
)
581 key
->ps
.alpha_func
= sctx
->queued
.named
.dsa
->alpha_func
;
589 /* Select the hw shader variant depending on the current state. */
590 static int si_shader_select(struct pipe_context
*ctx
,
591 struct si_shader_selector
*sel
)
593 struct si_context
*sctx
= (struct si_context
*)ctx
;
594 union si_shader_key key
;
595 struct si_shader
* shader
= NULL
;
598 si_shader_selector_key(ctx
, sel
, &key
);
600 /* Check if we don't need to change anything.
601 * This path is also used for most shaders that don't need multiple
602 * variants, it will cost just a computation of the key and this
604 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
608 /* lookup if we have other variants in the list */
609 if (sel
->num_shaders
> 1) {
610 struct si_shader
*p
= sel
->current
, *c
= p
->next_variant
;
612 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
618 p
->next_variant
= c
->next_variant
;
624 shader
->next_variant
= sel
->current
;
625 sel
->current
= shader
;
627 shader
= CALLOC(1, sizeof(struct si_shader
));
628 shader
->selector
= sel
;
631 shader
->next_variant
= sel
->current
;
632 sel
->current
= shader
;
633 r
= si_shader_create((struct si_screen
*)ctx
->screen
, sctx
->tm
,
636 R600_ERR("Failed to build shader variant (type=%u) %d\n",
642 si_shader_init_pm4_state(shader
);
644 p_atomic_inc(&sctx
->screen
->b
.num_compilations
);
650 static void *si_create_shader_selector(struct pipe_context
*ctx
,
651 const struct pipe_shader_state
*state
)
653 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
654 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
660 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
666 sel
->so
= state
->stream_output
;
667 tgsi_scan_shader(state
->tokens
, &sel
->info
);
668 sel
->type
= util_pipe_shader_from_tgsi_processor(sel
->info
.processor
);
669 p_atomic_inc(&sscreen
->b
.num_shaders_created
);
671 /* First set which opcode uses which (i,j) pair. */
672 if (sel
->info
.uses_persp_opcode_interp_centroid
)
673 sel
->info
.uses_persp_centroid
= true;
675 if (sel
->info
.uses_linear_opcode_interp_centroid
)
676 sel
->info
.uses_linear_centroid
= true;
678 if (sel
->info
.uses_persp_opcode_interp_offset
||
679 sel
->info
.uses_persp_opcode_interp_sample
)
680 sel
->info
.uses_persp_center
= true;
682 if (sel
->info
.uses_linear_opcode_interp_offset
||
683 sel
->info
.uses_linear_opcode_interp_sample
)
684 sel
->info
.uses_linear_center
= true;
686 /* Determine if the shader has to use a conditional assignment when
687 * emulating force_persample_interp.
689 sel
->forces_persample_interp_for_persp
=
690 sel
->info
.uses_persp_center
+
691 sel
->info
.uses_persp_centroid
+
692 sel
->info
.uses_persp_sample
>= 2;
694 sel
->forces_persample_interp_for_linear
=
695 sel
->info
.uses_linear_center
+
696 sel
->info
.uses_linear_centroid
+
697 sel
->info
.uses_linear_sample
>= 2;
700 case PIPE_SHADER_GEOMETRY
:
701 sel
->gs_output_prim
=
702 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
703 sel
->gs_max_out_vertices
=
704 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
705 sel
->gs_num_invocations
=
706 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
707 sel
->gsvs_itemsize
= sel
->info
.num_outputs
* 16 *
708 sel
->gs_max_out_vertices
;
710 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
711 unsigned name
= sel
->info
.input_semantic_name
[i
];
712 unsigned index
= sel
->info
.input_semantic_index
[i
];
715 case TGSI_SEMANTIC_PRIMID
:
719 1llu << si_shader_io_get_unique_index(name
, index
);
724 case PIPE_SHADER_VERTEX
:
725 case PIPE_SHADER_TESS_CTRL
:
726 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
727 unsigned name
= sel
->info
.output_semantic_name
[i
];
728 unsigned index
= sel
->info
.output_semantic_index
[i
];
731 case TGSI_SEMANTIC_TESSINNER
:
732 case TGSI_SEMANTIC_TESSOUTER
:
733 case TGSI_SEMANTIC_PATCH
:
734 sel
->patch_outputs_written
|=
735 1llu << si_shader_io_get_unique_index(name
, index
);
738 sel
->outputs_written
|=
739 1llu << si_shader_io_get_unique_index(name
, index
);
743 case PIPE_SHADER_FRAGMENT
:
744 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
745 unsigned name
= sel
->info
.output_semantic_name
[i
];
746 unsigned index
= sel
->info
.output_semantic_index
[i
];
748 if (name
== TGSI_SEMANTIC_COLOR
)
749 sel
->ps_colors_written
|= 1 << index
;
754 if (sscreen
->b
.debug_flags
& DBG_PRECOMPILE
)
755 if (si_shader_select(ctx
, sel
)) {
756 fprintf(stderr
, "radeonsi: can't create a shader\n");
757 tgsi_free_tokens(sel
->tokens
);
766 * Normally, we only emit 1 viewport and 1 scissor if no shader is using
767 * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
768 * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
769 * called to emit the rest.
771 static void si_update_viewports_and_scissors(struct si_context
*sctx
)
773 struct tgsi_shader_info
*info
= si_get_vs_info(sctx
);
775 if (!info
|| !info
->writes_viewport_index
)
778 if (sctx
->scissors
.dirty_mask
)
779 si_mark_atom_dirty(sctx
, &sctx
->scissors
.atom
);
780 if (sctx
->viewports
.dirty_mask
)
781 si_mark_atom_dirty(sctx
, &sctx
->viewports
.atom
);
784 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
786 struct si_context
*sctx
= (struct si_context
*)ctx
;
787 struct si_shader_selector
*sel
= state
;
789 if (sctx
->vs_shader
== sel
|| !sel
)
792 sctx
->vs_shader
= sel
;
793 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
794 si_update_viewports_and_scissors(sctx
);
797 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
799 struct si_context
*sctx
= (struct si_context
*)ctx
;
800 struct si_shader_selector
*sel
= state
;
801 bool enable_changed
= !!sctx
->gs_shader
!= !!sel
;
803 if (sctx
->gs_shader
== sel
)
806 sctx
->gs_shader
= sel
;
807 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
808 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
811 si_shader_change_notify(sctx
);
812 si_update_viewports_and_scissors(sctx
);
815 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
817 struct si_context
*sctx
= (struct si_context
*)ctx
;
818 struct si_shader_selector
*sel
= state
;
819 bool enable_changed
= !!sctx
->tcs_shader
!= !!sel
;
821 if (sctx
->tcs_shader
== sel
)
824 sctx
->tcs_shader
= sel
;
827 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
830 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
832 struct si_context
*sctx
= (struct si_context
*)ctx
;
833 struct si_shader_selector
*sel
= state
;
834 bool enable_changed
= !!sctx
->tes_shader
!= !!sel
;
836 if (sctx
->tes_shader
== sel
)
839 sctx
->tes_shader
= sel
;
840 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
841 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
843 if (enable_changed
) {
844 si_shader_change_notify(sctx
);
845 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
847 si_update_viewports_and_scissors(sctx
);
850 static void si_make_dummy_ps(struct si_context
*sctx
)
852 if (!sctx
->dummy_pixel_shader
) {
853 sctx
->dummy_pixel_shader
=
854 util_make_fragment_cloneinput_shader(&sctx
->b
.b
, 0,
855 TGSI_SEMANTIC_GENERIC
,
856 TGSI_INTERPOLATE_CONSTANT
);
860 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
862 struct si_context
*sctx
= (struct si_context
*)ctx
;
863 struct si_shader_selector
*sel
= state
;
865 /* skip if supplied shader is one already in use */
866 if (sctx
->ps_shader
== sel
)
869 /* use a dummy shader if binding a NULL shader */
871 si_make_dummy_ps(sctx
);
872 sel
= sctx
->dummy_pixel_shader
;
875 sctx
->ps_shader
= sel
;
876 si_mark_atom_dirty(sctx
, &sctx
->cb_target_mask
);
879 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
881 struct si_context
*sctx
= (struct si_context
*)ctx
;
882 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
883 struct si_shader
*p
= sel
->current
, *c
;
884 struct si_shader_selector
**current_shader
[SI_NUM_SHADERS
] = {
885 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
886 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
887 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
888 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
889 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
892 if (*current_shader
[sel
->type
] == sel
)
893 *current_shader
[sel
->type
] = NULL
;
898 case PIPE_SHADER_VERTEX
:
900 si_pm4_delete_state(sctx
, ls
, p
->pm4
);
901 else if (p
->key
.vs
.as_es
)
902 si_pm4_delete_state(sctx
, es
, p
->pm4
);
904 si_pm4_delete_state(sctx
, vs
, p
->pm4
);
906 case PIPE_SHADER_TESS_CTRL
:
907 si_pm4_delete_state(sctx
, hs
, p
->pm4
);
909 case PIPE_SHADER_TESS_EVAL
:
910 if (p
->key
.tes
.as_es
)
911 si_pm4_delete_state(sctx
, es
, p
->pm4
);
913 si_pm4_delete_state(sctx
, vs
, p
->pm4
);
915 case PIPE_SHADER_GEOMETRY
:
916 si_pm4_delete_state(sctx
, gs
, p
->pm4
);
917 si_pm4_delete_state(sctx
, vs
, p
->gs_copy_shader
->pm4
);
919 case PIPE_SHADER_FRAGMENT
:
920 si_pm4_delete_state(sctx
, ps
, p
->pm4
);
924 si_shader_destroy(p
);
933 static void si_emit_spi_map(struct si_context
*sctx
, struct r600_atom
*atom
)
935 struct radeon_winsys_cs
*cs
= sctx
->b
.rings
.gfx
.cs
;
936 struct si_shader
*ps
= sctx
->ps_shader
->current
;
937 struct si_shader
*vs
= si_get_vs_state(sctx
);
938 struct tgsi_shader_info
*psinfo
= &ps
->selector
->info
;
939 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
940 unsigned i
, j
, tmp
, num_written
= 0;
945 radeon_set_context_reg_seq(cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps
->nparam
);
947 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
948 unsigned name
= psinfo
->input_semantic_name
[i
];
949 unsigned index
= psinfo
->input_semantic_index
[i
];
950 unsigned interpolate
= psinfo
->input_interpolate
[i
];
951 unsigned param_offset
= ps
->ps_input_param_offset
[i
];
953 if (name
== TGSI_SEMANTIC_POSITION
||
954 name
== TGSI_SEMANTIC_FACE
)
955 /* Read from preloaded VGPRs, not parameters */
961 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
962 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
))
963 tmp
|= S_028644_FLAT_SHADE(1);
965 if (name
== TGSI_SEMANTIC_PCOORD
||
966 (name
== TGSI_SEMANTIC_TEXCOORD
&&
967 sctx
->sprite_coord_enable
& (1 << index
))) {
968 tmp
|= S_028644_PT_SPRITE_TEX(1);
971 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
972 if (name
== vsinfo
->output_semantic_name
[j
] &&
973 index
== vsinfo
->output_semantic_index
[j
]) {
974 tmp
|= S_028644_OFFSET(vs
->vs_output_param_offset
[j
]);
979 if (name
== TGSI_SEMANTIC_PRIMID
)
980 /* PrimID is written after the last output. */
981 tmp
|= S_028644_OFFSET(vs
->vs_output_param_offset
[vsinfo
->num_outputs
]);
982 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(tmp
)) {
983 /* No corresponding output found, load defaults into input.
984 * Don't set any other bits.
985 * (FLAT_SHADE=1 completely changes behavior) */
986 tmp
= S_028644_OFFSET(0x20);
989 assert(param_offset
== num_written
);
990 radeon_emit(cs
, tmp
);
993 if (name
== TGSI_SEMANTIC_COLOR
&&
994 ps
->key
.ps
.color_two_side
) {
995 name
= TGSI_SEMANTIC_BCOLOR
;
1000 assert(ps
->nparam
== num_written
);
1003 static void si_emit_spi_ps_input(struct si_context
*sctx
, struct r600_atom
*atom
)
1005 struct radeon_winsys_cs
*cs
= sctx
->b
.rings
.gfx
.cs
;
1006 struct si_shader
*ps
= sctx
->ps_shader
->current
;
1007 unsigned input_ena
= ps
->spi_ps_input_ena
;
1009 /* we need to enable at least one of them, otherwise we hang the GPU */
1010 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1011 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1012 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1013 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1014 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1015 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1016 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1017 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1019 if (sctx
->force_persample_interp
) {
1020 unsigned num_persp
= G_0286CC_PERSP_SAMPLE_ENA(input_ena
) +
1021 G_0286CC_PERSP_CENTER_ENA(input_ena
) +
1022 G_0286CC_PERSP_CENTROID_ENA(input_ena
);
1023 unsigned num_linear
= G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) +
1024 G_0286CC_LINEAR_CENTER_ENA(input_ena
) +
1025 G_0286CC_LINEAR_CENTROID_ENA(input_ena
);
1027 /* If only one set of (i,j) coordinates is used, we can disable
1028 * CENTER/CENTROID, enable SAMPLE and it will load SAMPLE coordinates
1029 * where CENTER/CENTROID are expected, effectively forcing per-sample
1032 if (num_persp
== 1) {
1033 input_ena
&= C_0286CC_PERSP_CENTER_ENA
;
1034 input_ena
&= C_0286CC_PERSP_CENTROID_ENA
;
1035 input_ena
|= G_0286CC_PERSP_SAMPLE_ENA(1);
1037 if (num_linear
== 1) {
1038 input_ena
&= C_0286CC_LINEAR_CENTER_ENA
;
1039 input_ena
&= C_0286CC_LINEAR_CENTROID_ENA
;
1040 input_ena
|= G_0286CC_LINEAR_SAMPLE_ENA(1);
1043 /* If at least 2 sets of coordinates are used, we can't use this
1044 * trick and have to select SAMPLE using a conditional assignment
1045 * in the shader with "force_persample_interp" being a shader constant.
1049 radeon_set_context_reg_seq(cs
, R_0286CC_SPI_PS_INPUT_ENA
, 2);
1050 radeon_emit(cs
, input_ena
);
1051 radeon_emit(cs
, input_ena
);
1053 if (ps
->selector
->forces_persample_interp_for_persp
||
1054 ps
->selector
->forces_persample_interp_for_linear
)
1055 radeon_set_sh_reg(cs
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
1056 SI_SGPR_PS_STATE_BITS
* 4,
1057 sctx
->force_persample_interp
);
1061 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1063 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
1065 if (sctx
->init_config_has_vgt_flush
)
1068 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
1069 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1070 si_pm4_cmd_end(sctx
->init_config
, false);
1071 sctx
->init_config_has_vgt_flush
= true;
1074 /* Initialize state related to ESGS / GSVS ring buffers */
1075 static void si_init_gs_rings(struct si_context
*sctx
)
1077 unsigned esgs_ring_size
= 128 * 1024;
1078 unsigned gsvs_ring_size
= 60 * 1024 * 1024;
1080 assert(!sctx
->esgs_ring
&& !sctx
->gsvs_ring
);
1082 sctx
->esgs_ring
= pipe_buffer_create(sctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1083 PIPE_USAGE_DEFAULT
, esgs_ring_size
);
1084 if (!sctx
->esgs_ring
)
1087 sctx
->gsvs_ring
= pipe_buffer_create(sctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1088 PIPE_USAGE_DEFAULT
, gsvs_ring_size
);
1089 if (!sctx
->gsvs_ring
) {
1090 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
1094 si_init_config_add_vgt_flush(sctx
);
1096 /* Append these registers to the init config state. */
1097 if (sctx
->b
.chip_class
>= CIK
) {
1098 if (sctx
->b
.chip_class
>= VI
) {
1099 /* The maximum sizes are 63.999 MB on VI, because
1100 * the register fields only have 18 bits. */
1101 assert(esgs_ring_size
/ 256 < (1 << 18));
1102 assert(gsvs_ring_size
/ 256 < (1 << 18));
1104 si_pm4_set_reg(sctx
->init_config
, R_030900_VGT_ESGS_RING_SIZE
,
1105 esgs_ring_size
/ 256);
1106 si_pm4_set_reg(sctx
->init_config
, R_030904_VGT_GSVS_RING_SIZE
,
1107 gsvs_ring_size
/ 256);
1109 si_pm4_set_reg(sctx
->init_config
, R_0088C8_VGT_ESGS_RING_SIZE
,
1110 esgs_ring_size
/ 256);
1111 si_pm4_set_reg(sctx
->init_config
, R_0088CC_VGT_GSVS_RING_SIZE
,
1112 gsvs_ring_size
/ 256);
1115 /* Flush the context to re-emit the init_config state.
1116 * This is done only once in a lifetime of a context.
1118 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
1119 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
1120 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
1122 si_set_ring_buffer(&sctx
->b
.b
, PIPE_SHADER_VERTEX
, SI_RING_ESGS
,
1123 sctx
->esgs_ring
, 0, esgs_ring_size
,
1124 true, true, 4, 64, 0);
1125 si_set_ring_buffer(&sctx
->b
.b
, PIPE_SHADER_GEOMETRY
, SI_RING_ESGS
,
1126 sctx
->esgs_ring
, 0, esgs_ring_size
,
1127 false, false, 0, 0, 0);
1128 si_set_ring_buffer(&sctx
->b
.b
, PIPE_SHADER_VERTEX
, SI_RING_GSVS
,
1129 sctx
->gsvs_ring
, 0, gsvs_ring_size
,
1130 false, false, 0, 0, 0);
1133 static void si_update_gs_rings(struct si_context
*sctx
)
1135 unsigned gsvs_itemsize
= sctx
->gs_shader
->gsvs_itemsize
;
1138 if (gsvs_itemsize
== sctx
->last_gsvs_itemsize
)
1141 sctx
->last_gsvs_itemsize
= gsvs_itemsize
;
1143 si_set_ring_buffer(&sctx
->b
.b
, PIPE_SHADER_GEOMETRY
, SI_RING_GSVS
,
1144 sctx
->gsvs_ring
, gsvs_itemsize
,
1145 64, true, true, 4, 16, 0);
1147 offset
= gsvs_itemsize
* 64;
1148 si_set_ring_buffer(&sctx
->b
.b
, PIPE_SHADER_GEOMETRY
, SI_RING_GSVS_1
,
1149 sctx
->gsvs_ring
, gsvs_itemsize
,
1150 64, true, true, 4, 16, offset
);
1152 offset
= (gsvs_itemsize
* 2) * 64;
1153 si_set_ring_buffer(&sctx
->b
.b
, PIPE_SHADER_GEOMETRY
, SI_RING_GSVS_2
,
1154 sctx
->gsvs_ring
, gsvs_itemsize
,
1155 64, true, true, 4, 16, offset
);
1157 offset
= (gsvs_itemsize
* 3) * 64;
1158 si_set_ring_buffer(&sctx
->b
.b
, PIPE_SHADER_GEOMETRY
, SI_RING_GSVS_3
,
1159 sctx
->gsvs_ring
, gsvs_itemsize
,
1160 64, true, true, 4, 16, offset
);
1164 * @returns 1 if \p sel has been updated to use a new scratch buffer
1166 * < 0 if there was a failure
1168 static int si_update_scratch_buffer(struct si_context
*sctx
,
1169 struct si_shader_selector
*sel
)
1171 struct si_shader
*shader
;
1172 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
1178 shader
= sel
->current
;
1180 /* This shader doesn't need a scratch buffer */
1181 if (shader
->scratch_bytes_per_wave
== 0)
1184 /* This shader is already configured to use the current
1185 * scratch buffer. */
1186 if (shader
->scratch_bo
== sctx
->scratch_buffer
)
1189 assert(sctx
->scratch_buffer
);
1191 si_shader_apply_scratch_relocs(sctx
, shader
, scratch_va
);
1193 /* Replace the shader bo with a new bo that has the relocs applied. */
1194 r
= si_shader_binary_upload(sctx
->screen
, shader
);
1198 /* Update the shader state to use the new shader bo. */
1199 si_shader_init_pm4_state(shader
);
1201 r600_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
1206 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
1208 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
1211 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader_selector
*sel
)
1213 return sel
? sel
->current
->scratch_bytes_per_wave
: 0;
1216 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
1220 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
));
1221 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
));
1222 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
));
1223 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tcs_shader
));
1224 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
));
1228 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
1230 unsigned current_scratch_buffer_size
=
1231 si_get_current_scratch_buffer_size(sctx
);
1232 unsigned scratch_bytes_per_wave
=
1233 si_get_max_scratch_bytes_per_wave(sctx
);
1234 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
1235 sctx
->scratch_waves
;
1238 if (scratch_needed_size
> 0) {
1239 if (scratch_needed_size
> current_scratch_buffer_size
) {
1240 /* Create a bigger scratch buffer */
1241 pipe_resource_reference(
1242 (struct pipe_resource
**)&sctx
->scratch_buffer
,
1245 sctx
->scratch_buffer
=
1246 si_resource_create_custom(&sctx
->screen
->b
.b
,
1247 PIPE_USAGE_DEFAULT
, scratch_needed_size
);
1248 if (!sctx
->scratch_buffer
)
1250 sctx
->emit_scratch_reloc
= true;
1253 /* Update the shaders, so they are using the latest scratch. The
1254 * scratch buffer may have been changed since these shaders were
1255 * last used, so we still need to try to update them, even if
1256 * they require scratch buffers smaller than the current size.
1258 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
);
1262 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
->current
->pm4
);
1264 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
);
1268 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
->current
->pm4
);
1270 r
= si_update_scratch_buffer(sctx
, sctx
->tcs_shader
);
1274 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
->current
->pm4
);
1276 /* VS can be bound as LS, ES, or VS. */
1277 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
);
1281 if (sctx
->tes_shader
)
1282 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
->current
->pm4
);
1283 else if (sctx
->gs_shader
)
1284 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
->current
->pm4
);
1286 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
->current
->pm4
);
1289 /* TES can be bound as ES or VS. */
1290 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
);
1294 if (sctx
->gs_shader
)
1295 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
->current
->pm4
);
1297 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
->current
->pm4
);
1301 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1302 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
1303 "scratch size should already be aligned correctly.");
1305 sctx
->spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
1306 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
1310 static void si_init_tess_factor_ring(struct si_context
*sctx
)
1312 assert(!sctx
->tf_ring
);
1314 sctx
->tf_ring
= pipe_buffer_create(sctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1316 32768 * sctx
->screen
->b
.info
.max_se
);
1320 assert(((sctx
->tf_ring
->width0
/ 4) & C_030938_SIZE
) == 0);
1322 si_init_config_add_vgt_flush(sctx
);
1324 /* Append these registers to the init config state. */
1325 if (sctx
->b
.chip_class
>= CIK
) {
1326 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
1327 S_030938_SIZE(sctx
->tf_ring
->width0
/ 4));
1328 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
1329 r600_resource(sctx
->tf_ring
)->gpu_address
>> 8);
1331 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
1332 S_008988_SIZE(sctx
->tf_ring
->width0
/ 4));
1333 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
1334 r600_resource(sctx
->tf_ring
)->gpu_address
>> 8);
1337 /* Flush the context to re-emit the init_config state.
1338 * This is done only once in a lifetime of a context.
1340 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
1341 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
1342 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
1344 si_set_ring_buffer(&sctx
->b
.b
, PIPE_SHADER_TESS_CTRL
,
1345 SI_RING_TESS_FACTOR
, sctx
->tf_ring
, 0,
1346 sctx
->tf_ring
->width0
, false, false, 0, 0, 0);
1350 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
1351 * VS passes its outputs to TES directly, so the fixed-function shader only
1352 * has to write TESSOUTER and TESSINNER.
1354 static void si_generate_fixed_func_tcs(struct si_context
*sctx
)
1356 struct ureg_src const0
, const1
;
1357 struct ureg_dst tessouter
, tessinner
;
1358 struct ureg_program
*ureg
= ureg_create(TGSI_PROCESSOR_TESS_CTRL
);
1361 return; /* if we get here, we're screwed */
1363 assert(!sctx
->fixed_func_tcs_shader
);
1365 ureg_DECL_constant2D(ureg
, 0, 1, SI_DRIVER_STATE_CONST_BUF
);
1366 const0
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 0),
1367 SI_DRIVER_STATE_CONST_BUF
);
1368 const1
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 1),
1369 SI_DRIVER_STATE_CONST_BUF
);
1371 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
1372 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
1374 ureg_MOV(ureg
, tessouter
, const0
);
1375 ureg_MOV(ureg
, tessinner
, const1
);
1378 sctx
->fixed_func_tcs_shader
=
1379 ureg_create_shader_and_destroy(ureg
, &sctx
->b
.b
);
1382 static void si_update_vgt_shader_config(struct si_context
*sctx
)
1384 /* Calculate the index of the config.
1385 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
1386 unsigned index
= 2*!!sctx
->tes_shader
+ !!sctx
->gs_shader
;
1387 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[index
];
1390 uint32_t stages
= 0;
1392 *pm4
= CALLOC_STRUCT(si_pm4_state
);
1394 if (sctx
->tes_shader
) {
1395 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
1398 if (sctx
->gs_shader
)
1399 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
1401 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
1403 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
1404 } else if (sctx
->gs_shader
) {
1405 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
1407 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
1410 si_pm4_set_reg(*pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
1412 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
1415 static void si_update_so(struct si_context
*sctx
, struct si_shader_selector
*shader
)
1417 struct pipe_stream_output_info
*so
= &shader
->so
;
1418 uint32_t enabled_stream_buffers_mask
= 0;
1421 for (i
= 0; i
< so
->num_outputs
; i
++)
1422 enabled_stream_buffers_mask
|= (1 << so
->output
[i
].output_buffer
) << (so
->output
[i
].stream
* 4);
1423 sctx
->b
.streamout
.enabled_stream_buffers_mask
= enabled_stream_buffers_mask
;
1424 sctx
->b
.streamout
.stride_in_dw
= shader
->so
.stride
;
1427 bool si_update_shaders(struct si_context
*sctx
)
1429 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
1430 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1433 /* Update stages before GS. */
1434 if (sctx
->tes_shader
) {
1435 if (!sctx
->tf_ring
) {
1436 si_init_tess_factor_ring(sctx
);
1442 r
= si_shader_select(ctx
, sctx
->vs_shader
);
1445 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
->current
->pm4
);
1447 if (sctx
->tcs_shader
) {
1448 r
= si_shader_select(ctx
, sctx
->tcs_shader
);
1451 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
->current
->pm4
);
1453 if (!sctx
->fixed_func_tcs_shader
) {
1454 si_generate_fixed_func_tcs(sctx
);
1455 if (!sctx
->fixed_func_tcs_shader
)
1459 r
= si_shader_select(ctx
, sctx
->fixed_func_tcs_shader
);
1462 si_pm4_bind_state(sctx
, hs
,
1463 sctx
->fixed_func_tcs_shader
->current
->pm4
);
1466 r
= si_shader_select(ctx
, sctx
->tes_shader
);
1470 if (sctx
->gs_shader
) {
1472 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
->current
->pm4
);
1475 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
->current
->pm4
);
1476 si_update_so(sctx
, sctx
->tes_shader
);
1478 } else if (sctx
->gs_shader
) {
1480 r
= si_shader_select(ctx
, sctx
->vs_shader
);
1483 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
->current
->pm4
);
1486 r
= si_shader_select(ctx
, sctx
->vs_shader
);
1489 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
->current
->pm4
);
1490 si_update_so(sctx
, sctx
->vs_shader
);
1494 if (sctx
->gs_shader
) {
1495 r
= si_shader_select(ctx
, sctx
->gs_shader
);
1498 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
->current
->pm4
);
1499 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
->current
->gs_copy_shader
->pm4
);
1500 si_update_so(sctx
, sctx
->gs_shader
);
1502 if (!sctx
->gsvs_ring
) {
1503 si_init_gs_rings(sctx
);
1504 if (!sctx
->gsvs_ring
)
1508 si_update_gs_rings(sctx
);
1510 si_pm4_bind_state(sctx
, gs
, NULL
);
1511 si_pm4_bind_state(sctx
, es
, NULL
);
1514 si_update_vgt_shader_config(sctx
);
1516 r
= si_shader_select(ctx
, sctx
->ps_shader
);
1519 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
->current
->pm4
);
1521 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
1522 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
1523 sctx
->flatshade
!= rs
->flatshade
) {
1524 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
1525 sctx
->flatshade
= rs
->flatshade
;
1526 si_mark_atom_dirty(sctx
, &sctx
->spi_map
);
1529 if (si_pm4_state_changed(sctx
, ps
) ||
1530 sctx
->force_persample_interp
!= rs
->force_persample_interp
) {
1531 sctx
->force_persample_interp
= rs
->force_persample_interp
;
1532 si_mark_atom_dirty(sctx
, &sctx
->spi_ps_input
);
1535 if (si_pm4_state_changed(sctx
, ls
) ||
1536 si_pm4_state_changed(sctx
, hs
) ||
1537 si_pm4_state_changed(sctx
, es
) ||
1538 si_pm4_state_changed(sctx
, gs
) ||
1539 si_pm4_state_changed(sctx
, vs
) ||
1540 si_pm4_state_changed(sctx
, ps
)) {
1541 if (!si_update_spi_tmpring_size(sctx
))
1545 if (sctx
->ps_db_shader_control
!= sctx
->ps_shader
->current
->db_shader_control
) {
1546 sctx
->ps_db_shader_control
= sctx
->ps_shader
->current
->db_shader_control
;
1547 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1550 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
->current
->key
.ps
.poly_line_smoothing
) {
1551 sctx
->smoothing_enabled
= sctx
->ps_shader
->current
->key
.ps
.poly_line_smoothing
;
1552 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
1554 if (sctx
->b
.chip_class
== SI
)
1555 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1560 void si_init_shader_functions(struct si_context
*sctx
)
1562 si_init_atom(sctx
, &sctx
->spi_map
, &sctx
->atoms
.s
.spi_map
, si_emit_spi_map
);
1563 si_init_atom(sctx
, &sctx
->spi_ps_input
, &sctx
->atoms
.s
.spi_ps_input
, si_emit_spi_ps_input
);
1565 sctx
->b
.b
.create_vs_state
= si_create_shader_selector
;
1566 sctx
->b
.b
.create_tcs_state
= si_create_shader_selector
;
1567 sctx
->b
.b
.create_tes_state
= si_create_shader_selector
;
1568 sctx
->b
.b
.create_gs_state
= si_create_shader_selector
;
1569 sctx
->b
.b
.create_fs_state
= si_create_shader_selector
;
1571 sctx
->b
.b
.bind_vs_state
= si_bind_vs_shader
;
1572 sctx
->b
.b
.bind_tcs_state
= si_bind_tcs_shader
;
1573 sctx
->b
.b
.bind_tes_state
= si_bind_tes_shader
;
1574 sctx
->b
.b
.bind_gs_state
= si_bind_gs_shader
;
1575 sctx
->b
.b
.bind_fs_state
= si_bind_ps_shader
;
1577 sctx
->b
.b
.delete_vs_state
= si_delete_shader_selector
;
1578 sctx
->b
.b
.delete_tcs_state
= si_delete_shader_selector
;
1579 sctx
->b
.b
.delete_tes_state
= si_delete_shader_selector
;
1580 sctx
->b
.b
.delete_gs_state
= si_delete_shader_selector
;
1581 sctx
->b
.b
.delete_fs_state
= si_delete_shader_selector
;