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radeonsi: don't count special outputs for the VS export count
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31
32 #include "tgsi/tgsi_parse.h"
33 #include "util/u_memory.h"
34 #include "util/u_simple_shaders.h"
35
36 static void si_shader_es(struct si_shader *shader)
37 {
38 struct si_pm4_state *pm4;
39 unsigned num_sgprs, num_user_sgprs;
40 unsigned vgpr_comp_cnt;
41 uint64_t va;
42
43 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
44
45 if (pm4 == NULL)
46 return;
47
48 va = shader->bo->gpu_address;
49 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
50
51 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
52
53 num_user_sgprs = SI_VS_NUM_USER_SGPR;
54 num_sgprs = shader->num_sgprs;
55 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
56 if ((num_user_sgprs + 1) > num_sgprs) {
57 /* Last 2 reserved SGPRs are used for VCC */
58 num_sgprs = num_user_sgprs + 1 + 2;
59 }
60 assert(num_sgprs <= 104);
61
62 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
63 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
64 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
65 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
66 S_00B328_SGPRS((num_sgprs - 1) / 8) |
67 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
68 S_00B328_DX10_CLAMP(shader->dx10_clamp_mode));
69 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
70 S_00B32C_USER_SGPR(num_user_sgprs) |
71 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
72 }
73
74 static void si_shader_gs(struct si_shader *shader)
75 {
76 unsigned gs_vert_itemsize = shader->selector->info.num_outputs * (16 >> 2);
77 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
78 unsigned gsvs_itemsize = gs_vert_itemsize * gs_max_vert_out;
79 unsigned cut_mode;
80 struct si_pm4_state *pm4;
81 unsigned num_sgprs, num_user_sgprs;
82 uint64_t va;
83
84 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
85 assert(gsvs_itemsize < (1 << 15));
86
87 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
88
89 if (pm4 == NULL)
90 return;
91
92 if (gs_max_vert_out <= 128) {
93 cut_mode = V_028A40_GS_CUT_128;
94 } else if (gs_max_vert_out <= 256) {
95 cut_mode = V_028A40_GS_CUT_256;
96 } else if (gs_max_vert_out <= 512) {
97 cut_mode = V_028A40_GS_CUT_512;
98 } else {
99 assert(gs_max_vert_out <= 1024);
100 cut_mode = V_028A40_GS_CUT_1024;
101 }
102
103 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
104 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
105 S_028A40_CUT_MODE(cut_mode)|
106 S_028A40_ES_WRITE_OPTIMIZE(1) |
107 S_028A40_GS_WRITE_OPTIMIZE(1));
108
109 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
110 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize);
111 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize);
112
113 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
114 util_bitcount64(shader->selector->gs_used_inputs) * (16 >> 2));
115 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
116
117 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
118
119 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize);
120
121 va = shader->bo->gpu_address;
122 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
123 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
124 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
125
126 num_user_sgprs = SI_GS_NUM_USER_SGPR;
127 num_sgprs = shader->num_sgprs;
128 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
129 if ((num_user_sgprs + 2) > num_sgprs) {
130 /* Last 2 reserved SGPRs are used for VCC */
131 num_sgprs = num_user_sgprs + 2 + 2;
132 }
133 assert(num_sgprs <= 104);
134
135 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
136 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
137 S_00B228_SGPRS((num_sgprs - 1) / 8) |
138 S_00B228_DX10_CLAMP(shader->dx10_clamp_mode));
139 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
140 S_00B22C_USER_SGPR(num_user_sgprs) |
141 S_00B22C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
142 }
143
144 static void si_shader_vs(struct si_shader *shader)
145 {
146 struct tgsi_shader_info *info = &shader->selector->info;
147 struct si_pm4_state *pm4;
148 unsigned num_sgprs, num_user_sgprs;
149 unsigned nparams, i, vgpr_comp_cnt;
150 uint64_t va;
151 unsigned window_space =
152 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
153
154 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
155
156 if (pm4 == NULL)
157 return;
158
159 va = shader->bo->gpu_address;
160 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
161
162 if (shader->is_gs_copy_shader) {
163 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
164 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
165 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
166 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
167 num_user_sgprs = SI_VS_NUM_USER_SGPR;
168 } else
169 assert(0);
170
171 num_sgprs = shader->num_sgprs;
172 if (num_user_sgprs > num_sgprs) {
173 /* Last 2 reserved SGPRs are used for VCC */
174 num_sgprs = num_user_sgprs + 2;
175 }
176 assert(num_sgprs <= 104);
177
178 /* Certain attributes (position, psize, etc.) don't count as params.
179 * VS is required to export at least one param and r600_shader_from_tgsi()
180 * takes care of adding a dummy export.
181 */
182 for (nparams = 0, i = 0 ; i < info->num_outputs; i++) {
183 switch (info->output_semantic_name[i]) {
184 case TGSI_SEMANTIC_CLIPVERTEX:
185 case TGSI_SEMANTIC_CLIPDIST:
186 case TGSI_SEMANTIC_CULLDIST:
187 case TGSI_SEMANTIC_POSITION:
188 case TGSI_SEMANTIC_PSIZE:
189 case TGSI_SEMANTIC_EDGEFLAG:
190 case TGSI_SEMANTIC_VIEWPORT_INDEX:
191 case TGSI_SEMANTIC_LAYER:
192 break;
193 default:
194 nparams++;
195 }
196 }
197 if (nparams < 1)
198 nparams = 1;
199
200 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
201 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
202
203 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
204 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
205 S_02870C_POS1_EXPORT_FORMAT(shader->nr_pos_exports > 1 ?
206 V_02870C_SPI_SHADER_4COMP :
207 V_02870C_SPI_SHADER_NONE) |
208 S_02870C_POS2_EXPORT_FORMAT(shader->nr_pos_exports > 2 ?
209 V_02870C_SPI_SHADER_4COMP :
210 V_02870C_SPI_SHADER_NONE) |
211 S_02870C_POS3_EXPORT_FORMAT(shader->nr_pos_exports > 3 ?
212 V_02870C_SPI_SHADER_4COMP :
213 V_02870C_SPI_SHADER_NONE));
214
215 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
216 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
217 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
218 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
219 S_00B128_SGPRS((num_sgprs - 1) / 8) |
220 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
221 S_00B128_DX10_CLAMP(shader->dx10_clamp_mode));
222 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
223 S_00B12C_USER_SGPR(num_user_sgprs) |
224 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
225 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
226 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
227 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
228 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
229 S_00B12C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
230 if (window_space)
231 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
232 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
233 else
234 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
235 S_028818_VTX_W0_FMT(1) |
236 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
237 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
238 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
239 }
240
241 static void si_shader_ps(struct si_shader *shader)
242 {
243 struct tgsi_shader_info *info = &shader->selector->info;
244 struct si_pm4_state *pm4;
245 unsigned i, spi_ps_in_control;
246 unsigned num_sgprs, num_user_sgprs;
247 unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
248 uint64_t va;
249
250 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
251
252 if (pm4 == NULL)
253 return;
254
255 for (i = 0; i < info->num_inputs; i++) {
256 switch (info->input_semantic_name[i]) {
257 case TGSI_SEMANTIC_POSITION:
258 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
259 * Possible vaules:
260 * 0 -> Position = pixel center (default)
261 * 1 -> Position = pixel centroid
262 * 2 -> Position = at sample position
263 */
264 switch (info->input_interpolate_loc[i]) {
265 case TGSI_INTERPOLATE_LOC_CENTROID:
266 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
267 break;
268 case TGSI_INTERPOLATE_LOC_SAMPLE:
269 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
270 break;
271 }
272
273 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
274 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
275 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
276 break;
277 }
278 }
279
280 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->nparam) |
281 S_0286D8_BC_OPTIMIZE_DISABLE(1);
282
283 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
284 spi_ps_input_ena = shader->spi_ps_input_ena;
285 /* we need to enable at least one of them, otherwise we hang the GPU */
286 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
287 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
288 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
289 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
290 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
291 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
292 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
293 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
294
295 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
296 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
297 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
298
299 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
300 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
301 shader->spi_shader_col_format);
302 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
303
304 va = shader->bo->gpu_address;
305 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
306 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
307 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
308
309 num_user_sgprs = SI_PS_NUM_USER_SGPR;
310 num_sgprs = shader->num_sgprs;
311 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
312 if ((num_user_sgprs + 1) > num_sgprs) {
313 /* Last 2 reserved SGPRs are used for VCC */
314 num_sgprs = num_user_sgprs + 1 + 2;
315 }
316 assert(num_sgprs <= 104);
317
318 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
319 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
320 S_00B028_SGPRS((num_sgprs - 1) / 8) |
321 S_00B028_DX10_CLAMP(shader->dx10_clamp_mode));
322 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
323 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
324 S_00B02C_USER_SGPR(num_user_sgprs) |
325 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
326 }
327
328 static void si_shader_init_pm4_state(struct si_shader *shader)
329 {
330
331 if (shader->pm4)
332 si_pm4_free_state_simple(shader->pm4);
333
334 switch (shader->selector->type) {
335 case PIPE_SHADER_VERTEX:
336 if (shader->key.vs.as_es)
337 si_shader_es(shader);
338 else
339 si_shader_vs(shader);
340 break;
341 case PIPE_SHADER_GEOMETRY:
342 si_shader_gs(shader);
343 si_shader_vs(shader->gs_copy_shader);
344 break;
345 case PIPE_SHADER_FRAGMENT:
346 si_shader_ps(shader);
347 break;
348 default:
349 assert(0);
350 }
351 }
352
353 /* Compute the key for the hw shader variant */
354 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
355 struct si_shader_selector *sel,
356 union si_shader_key *key)
357 {
358 struct si_context *sctx = (struct si_context *)ctx;
359 memset(key, 0, sizeof(*key));
360
361 if (sel->type == PIPE_SHADER_VERTEX) {
362 unsigned i;
363 if (!sctx->vertex_elements)
364 return;
365
366 for (i = 0; i < sctx->vertex_elements->count; ++i)
367 key->vs.instance_divisors[i] = sctx->vertex_elements->elements[i].instance_divisor;
368
369 if (sctx->gs_shader) {
370 key->vs.as_es = 1;
371 key->vs.gs_used_inputs = sctx->gs_shader->gs_used_inputs;
372 }
373 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
374 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
375
376 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
377 key->ps.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
378 key->ps.export_16bpc = sctx->framebuffer.export_16bpc;
379
380 if (rs) {
381 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
382 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
383 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
384 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
385
386 key->ps.color_two_side = rs->two_side;
387
388 if (sctx->queued.named.blend) {
389 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
390 rs->multisample_enable &&
391 !sctx->framebuffer.cb0_is_integer;
392 }
393
394 key->ps.poly_stipple = rs->poly_stipple_enable && is_poly;
395 key->ps.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
396 (is_line && rs->line_smooth)) &&
397 sctx->framebuffer.nr_samples <= 1;
398 }
399
400 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
401
402 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
403 if (sctx->queued.named.dsa &&
404 !sctx->framebuffer.cb0_is_integer)
405 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
406 }
407 }
408
409 /* Select the hw shader variant depending on the current state. */
410 static int si_shader_select(struct pipe_context *ctx,
411 struct si_shader_selector *sel)
412 {
413 struct si_context *sctx = (struct si_context *)ctx;
414 union si_shader_key key;
415 struct si_shader * shader = NULL;
416 int r;
417
418 si_shader_selector_key(ctx, sel, &key);
419
420 /* Check if we don't need to change anything.
421 * This path is also used for most shaders that don't need multiple
422 * variants, it will cost just a computation of the key and this
423 * test. */
424 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
425 return 0;
426 }
427
428 /* lookup if we have other variants in the list */
429 if (sel->num_shaders > 1) {
430 struct si_shader *p = sel->current, *c = p->next_variant;
431
432 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
433 p = c;
434 c = c->next_variant;
435 }
436
437 if (c) {
438 p->next_variant = c->next_variant;
439 shader = c;
440 }
441 }
442
443 if (shader) {
444 shader->next_variant = sel->current;
445 sel->current = shader;
446 } else {
447 shader = CALLOC(1, sizeof(struct si_shader));
448 shader->selector = sel;
449 shader->key = key;
450
451 shader->next_variant = sel->current;
452 sel->current = shader;
453 r = si_shader_create((struct si_screen*)ctx->screen, sctx->tm,
454 shader);
455 if (unlikely(r)) {
456 R600_ERR("Failed to build shader variant (type=%u) %d\n",
457 sel->type, r);
458 sel->current = NULL;
459 FREE(shader);
460 return r;
461 }
462 si_shader_init_pm4_state(shader);
463 sel->num_shaders++;
464 }
465
466 return 0;
467 }
468
469 static void *si_create_shader_state(struct pipe_context *ctx,
470 const struct pipe_shader_state *state,
471 unsigned pipe_shader_type)
472 {
473 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
474 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
475 int i;
476
477 sel->type = pipe_shader_type;
478 sel->tokens = tgsi_dup_tokens(state->tokens);
479 sel->so = state->stream_output;
480 tgsi_scan_shader(state->tokens, &sel->info);
481
482 switch (pipe_shader_type) {
483 case PIPE_SHADER_GEOMETRY:
484 sel->gs_output_prim =
485 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
486 sel->gs_max_out_vertices =
487 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
488
489 for (i = 0; i < sel->info.num_inputs; i++) {
490 unsigned name = sel->info.input_semantic_name[i];
491 unsigned index = sel->info.input_semantic_index[i];
492
493 switch (name) {
494 case TGSI_SEMANTIC_PRIMID:
495 break;
496 default:
497 sel->gs_used_inputs |=
498 1llu << si_shader_io_get_unique_index(name, index);
499 }
500 }
501 }
502
503 if (sscreen->b.debug_flags & DBG_PRECOMPILE)
504 si_shader_select(ctx, sel);
505
506 return sel;
507 }
508
509 static void *si_create_fs_state(struct pipe_context *ctx,
510 const struct pipe_shader_state *state)
511 {
512 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
513 }
514
515 static void *si_create_gs_state(struct pipe_context *ctx,
516 const struct pipe_shader_state *state)
517 {
518 return si_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
519 }
520
521 static void *si_create_vs_state(struct pipe_context *ctx,
522 const struct pipe_shader_state *state)
523 {
524 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
525 }
526
527 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
528 {
529 struct si_context *sctx = (struct si_context *)ctx;
530 struct si_shader_selector *sel = state;
531
532 if (sctx->vs_shader == sel || !sel)
533 return;
534
535 sctx->vs_shader = sel;
536 sctx->clip_regs.dirty = true;
537 }
538
539 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
540 {
541 struct si_context *sctx = (struct si_context *)ctx;
542 struct si_shader_selector *sel = state;
543
544 if (sctx->gs_shader == sel)
545 return;
546
547 sctx->gs_shader = sel;
548 sctx->clip_regs.dirty = true;
549 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
550 }
551
552 static void si_make_dummy_ps(struct si_context *sctx)
553 {
554 if (!sctx->dummy_pixel_shader) {
555 sctx->dummy_pixel_shader =
556 util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
557 TGSI_SEMANTIC_GENERIC,
558 TGSI_INTERPOLATE_CONSTANT);
559 }
560 }
561
562 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
563 {
564 struct si_context *sctx = (struct si_context *)ctx;
565 struct si_shader_selector *sel = state;
566
567 /* skip if supplied shader is one already in use */
568 if (sctx->ps_shader == sel)
569 return;
570
571 /* use a dummy shader if binding a NULL shader */
572 if (!sel) {
573 si_make_dummy_ps(sctx);
574 sel = sctx->dummy_pixel_shader;
575 }
576
577 sctx->ps_shader = sel;
578 }
579
580 static void si_delete_shader_selector(struct pipe_context *ctx,
581 struct si_shader_selector *sel)
582 {
583 struct si_context *sctx = (struct si_context *)ctx;
584 struct si_shader *p = sel->current, *c;
585
586 while (p) {
587 c = p->next_variant;
588 if (sel->type == PIPE_SHADER_GEOMETRY) {
589 si_pm4_delete_state(sctx, gs, p->pm4);
590 si_pm4_delete_state(sctx, vs, p->gs_copy_shader->pm4);
591 } else if (sel->type == PIPE_SHADER_FRAGMENT)
592 si_pm4_delete_state(sctx, ps, p->pm4);
593 else if (p->key.vs.as_es)
594 si_pm4_delete_state(sctx, es, p->pm4);
595 else
596 si_pm4_delete_state(sctx, vs, p->pm4);
597 si_shader_destroy(ctx, p);
598 free(p);
599 p = c;
600 }
601
602 free(sel->tokens);
603 free(sel);
604 }
605
606 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
607 {
608 struct si_context *sctx = (struct si_context *)ctx;
609 struct si_shader_selector *sel = (struct si_shader_selector *)state;
610
611 if (sctx->vs_shader == sel) {
612 sctx->vs_shader = NULL;
613 }
614
615 si_delete_shader_selector(ctx, sel);
616 }
617
618 static void si_delete_gs_shader(struct pipe_context *ctx, void *state)
619 {
620 struct si_context *sctx = (struct si_context *)ctx;
621 struct si_shader_selector *sel = (struct si_shader_selector *)state;
622
623 if (sctx->gs_shader == sel) {
624 sctx->gs_shader = NULL;
625 }
626
627 si_delete_shader_selector(ctx, sel);
628 }
629
630 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
631 {
632 struct si_context *sctx = (struct si_context *)ctx;
633 struct si_shader_selector *sel = (struct si_shader_selector *)state;
634
635 if (sctx->ps_shader == sel) {
636 sctx->ps_shader = NULL;
637 }
638
639 si_delete_shader_selector(ctx, sel);
640 }
641
642 static void si_update_spi_map(struct si_context *sctx)
643 {
644 struct si_shader *ps = sctx->ps_shader->current;
645 struct si_shader *vs = si_get_vs_state(sctx);
646 struct tgsi_shader_info *psinfo = &ps->selector->info;
647 struct tgsi_shader_info *vsinfo = &vs->selector->info;
648 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
649 unsigned i, j, tmp;
650
651 for (i = 0; i < psinfo->num_inputs; i++) {
652 unsigned name = psinfo->input_semantic_name[i];
653 unsigned index = psinfo->input_semantic_index[i];
654 unsigned interpolate = psinfo->input_interpolate[i];
655 unsigned param_offset = ps->ps_input_param_offset[i];
656
657 if (name == TGSI_SEMANTIC_POSITION ||
658 name == TGSI_SEMANTIC_FACE)
659 /* Read from preloaded VGPRs, not parameters */
660 continue;
661
662 bcolor:
663 tmp = 0;
664
665 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
666 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
667 tmp |= S_028644_FLAT_SHADE(1);
668
669 if (name == TGSI_SEMANTIC_PCOORD ||
670 (name == TGSI_SEMANTIC_TEXCOORD &&
671 sctx->sprite_coord_enable & (1 << index))) {
672 tmp |= S_028644_PT_SPRITE_TEX(1);
673 }
674
675 for (j = 0; j < vsinfo->num_outputs; j++) {
676 if (name == vsinfo->output_semantic_name[j] &&
677 index == vsinfo->output_semantic_index[j]) {
678 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[j]);
679 break;
680 }
681 }
682
683 if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(tmp)) {
684 /* No corresponding output found, load defaults into input.
685 * Don't set any other bits.
686 * (FLAT_SHADE=1 completely changes behavior) */
687 tmp = S_028644_OFFSET(0x20);
688 }
689
690 si_pm4_set_reg(pm4,
691 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
692 tmp);
693
694 if (name == TGSI_SEMANTIC_COLOR &&
695 ps->key.ps.color_two_side) {
696 name = TGSI_SEMANTIC_BCOLOR;
697 param_offset++;
698 goto bcolor;
699 }
700 }
701
702 si_pm4_set_state(sctx, spi, pm4);
703 }
704
705 /* Initialize state related to ESGS / GSVS ring buffers */
706 static void si_init_gs_rings(struct si_context *sctx)
707 {
708 unsigned esgs_ring_size = 128 * 1024;
709 unsigned gsvs_ring_size = 64 * 1024 * 1024;
710
711 assert(!sctx->gs_rings);
712 sctx->gs_rings = CALLOC_STRUCT(si_pm4_state);
713
714 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
715 PIPE_USAGE_DEFAULT, esgs_ring_size);
716
717 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
718 PIPE_USAGE_DEFAULT, gsvs_ring_size);
719
720 if (sctx->b.chip_class >= CIK) {
721 si_pm4_set_reg(sctx->gs_rings, R_030900_VGT_ESGS_RING_SIZE,
722 esgs_ring_size / 256);
723 si_pm4_set_reg(sctx->gs_rings, R_030904_VGT_GSVS_RING_SIZE,
724 gsvs_ring_size / 256);
725 } else {
726 si_pm4_set_reg(sctx->gs_rings, R_0088C8_VGT_ESGS_RING_SIZE,
727 esgs_ring_size / 256);
728 si_pm4_set_reg(sctx->gs_rings, R_0088CC_VGT_GSVS_RING_SIZE,
729 gsvs_ring_size / 256);
730 }
731
732 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
733 sctx->esgs_ring, 0, esgs_ring_size,
734 true, true, 4, 64);
735 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
736 sctx->esgs_ring, 0, esgs_ring_size,
737 false, false, 0, 0);
738 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
739 sctx->gsvs_ring, 0, gsvs_ring_size,
740 false, false, 0, 0);
741 }
742
743 /**
744 * @returns 1 if \p sel has been updated to use a new scratch buffer and 0
745 * otherwise.
746 */
747 static unsigned si_update_scratch_buffer(struct si_context *sctx,
748 struct si_shader_selector *sel)
749 {
750 struct si_shader *shader;
751 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
752 unsigned char *ptr;
753
754 if (!sel)
755 return 0;
756
757 shader = sel->current;
758
759 /* This shader doesn't need a scratch buffer */
760 if (shader->scratch_bytes_per_wave == 0)
761 return 0;
762
763 /* This shader is already configured to use the current
764 * scratch buffer. */
765 if (shader->scratch_bo == sctx->scratch_buffer)
766 return 0;
767
768 assert(sctx->scratch_buffer);
769
770 si_shader_apply_scratch_relocs(sctx, shader, scratch_va);
771
772 /* Replace the shader bo with a new bo that has the relocs applied. */
773 r600_resource_reference(&shader->bo, NULL);
774 shader->bo = si_resource_create_custom(&sctx->screen->b.b, PIPE_USAGE_IMMUTABLE,
775 shader->binary.code_size);
776 ptr = sctx->screen->b.ws->buffer_map(shader->bo->cs_buf, NULL, PIPE_TRANSFER_WRITE);
777 util_memcpy_cpu_to_le32(ptr, shader->binary.code, shader->binary.code_size);
778 sctx->screen->b.ws->buffer_unmap(shader->bo->cs_buf);
779
780 /* Update the shader state to use the new shader bo. */
781 si_shader_init_pm4_state(shader);
782
783 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
784
785 return 1;
786 }
787
788 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
789 {
790 if (!sctx->scratch_buffer)
791 return 0;
792
793 return sctx->scratch_buffer->b.b.width0;
794 }
795
796 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_context *sctx,
797 struct si_shader_selector *sel)
798 {
799 if (!sel)
800 return 0;
801
802 return sel->current->scratch_bytes_per_wave;
803 }
804
805 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
806 {
807
808 return MAX3(si_get_scratch_buffer_bytes_per_wave(sctx, sctx->ps_shader),
809 si_get_scratch_buffer_bytes_per_wave(sctx, sctx->gs_shader),
810 si_get_scratch_buffer_bytes_per_wave(sctx, sctx->vs_shader));
811 }
812
813 static void si_update_spi_tmpring_size(struct si_context *sctx)
814 {
815 unsigned current_scratch_buffer_size =
816 si_get_current_scratch_buffer_size(sctx);
817 unsigned scratch_bytes_per_wave =
818 si_get_max_scratch_bytes_per_wave(sctx);
819 unsigned scratch_needed_size = scratch_bytes_per_wave *
820 sctx->scratch_waves;
821
822 if (scratch_needed_size > 0) {
823
824 if (scratch_needed_size > current_scratch_buffer_size) {
825 /* Create a bigger scratch buffer */
826 pipe_resource_reference(
827 (struct pipe_resource**)&sctx->scratch_buffer,
828 NULL);
829
830 sctx->scratch_buffer =
831 si_resource_create_custom(&sctx->screen->b.b,
832 PIPE_USAGE_DEFAULT, scratch_needed_size);
833 }
834
835 /* Update the shaders, so they are using the latest scratch. The
836 * scratch buffer may have been changed since these shaders were
837 * last used, so we still need to try to update them, even if
838 * they require scratch buffers smaller than the current size.
839 */
840 if (si_update_scratch_buffer(sctx, sctx->ps_shader))
841 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
842 if (si_update_scratch_buffer(sctx, sctx->gs_shader))
843 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
844 if (si_update_scratch_buffer(sctx, sctx->vs_shader))
845 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
846 }
847
848 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
849 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
850 "scratch size should already be aligned correctly.");
851
852 sctx->spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
853 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
854 }
855
856 void si_update_shaders(struct si_context *sctx)
857 {
858 struct pipe_context *ctx = (struct pipe_context*)sctx;
859 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
860
861 if (sctx->gs_shader) {
862 si_shader_select(ctx, sctx->gs_shader);
863 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
864 si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
865
866 sctx->b.streamout.stride_in_dw = sctx->gs_shader->so.stride;
867
868 si_shader_select(ctx, sctx->vs_shader);
869 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
870
871 if (!sctx->gs_rings)
872 si_init_gs_rings(sctx);
873 if (sctx->emitted.named.gs_rings != sctx->gs_rings)
874 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
875 si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
876
877 si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
878 sctx->gsvs_ring,
879 sctx->gs_shader->gs_max_out_vertices *
880 sctx->gs_shader->info.num_outputs * 16,
881 64, true, true, 4, 16);
882
883 if (!sctx->gs_on) {
884 sctx->gs_on = CALLOC_STRUCT(si_pm4_state);
885
886 si_pm4_set_reg(sctx->gs_on, R_028B54_VGT_SHADER_STAGES_EN,
887 S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
888 S_028B54_GS_EN(1) |
889 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER));
890 }
891 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_on);
892 } else {
893 si_shader_select(ctx, sctx->vs_shader);
894 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
895
896 sctx->b.streamout.stride_in_dw = sctx->vs_shader->so.stride;
897
898 if (!sctx->gs_off) {
899 sctx->gs_off = CALLOC_STRUCT(si_pm4_state);
900
901 si_pm4_set_reg(sctx->gs_off, R_028A40_VGT_GS_MODE, 0);
902 si_pm4_set_reg(sctx->gs_off, R_028B54_VGT_SHADER_STAGES_EN, 0);
903 }
904 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_off);
905 si_pm4_bind_state(sctx, gs_rings, NULL);
906 si_pm4_bind_state(sctx, gs, NULL);
907 si_pm4_bind_state(sctx, es, NULL);
908 }
909
910 si_shader_select(ctx, sctx->ps_shader);
911
912 if (!sctx->ps_shader->current) {
913 struct si_shader_selector *sel;
914
915 /* use a dummy shader if compiling the shader (variant) failed */
916 si_make_dummy_ps(sctx);
917 sel = sctx->dummy_pixel_shader;
918 si_shader_select(ctx, sel);
919 sctx->ps_shader->current = sel->current;
920 }
921
922 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
923
924 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
925 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
926 sctx->flatshade != rs->flatshade) {
927 sctx->sprite_coord_enable = rs->sprite_coord_enable;
928 sctx->flatshade = rs->flatshade;
929 si_update_spi_map(sctx);
930 }
931
932 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
933 si_pm4_state_changed(sctx, gs)) {
934 si_update_spi_tmpring_size(sctx);
935 }
936
937 if (sctx->ps_db_shader_control != sctx->ps_shader->current->db_shader_control) {
938 sctx->ps_db_shader_control = sctx->ps_shader->current->db_shader_control;
939 sctx->db_render_state.dirty = true;
940 }
941
942 if (sctx->smoothing_enabled != sctx->ps_shader->current->key.ps.poly_line_smoothing) {
943 sctx->smoothing_enabled = sctx->ps_shader->current->key.ps.poly_line_smoothing;
944 sctx->msaa_config.dirty = true;
945
946 if (sctx->b.chip_class == SI)
947 sctx->db_render_state.dirty = true;
948 }
949 }
950
951 void si_init_shader_functions(struct si_context *sctx)
952 {
953 sctx->b.b.create_vs_state = si_create_vs_state;
954 sctx->b.b.create_gs_state = si_create_gs_state;
955 sctx->b.b.create_fs_state = si_create_fs_state;
956
957 sctx->b.b.bind_vs_state = si_bind_vs_shader;
958 sctx->b.b.bind_gs_state = si_bind_gs_shader;
959 sctx->b.b.bind_fs_state = si_bind_ps_shader;
960
961 sctx->b.b.delete_vs_state = si_delete_vs_shader;
962 sctx->b.b.delete_gs_state = si_delete_gs_shader;
963 sctx->b.b.delete_fs_state = si_delete_ps_shader;
964 }