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radeonsi/gfx9: wait for main part compilation of 1st shaders of merged shaders
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "sid.h"
30 #include "gfx9d.h"
31 #include "radeon/r600_cs.h"
32
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/hash_table.h"
36 #include "util/crc32.h"
37 #include "util/u_memory.h"
38 #include "util/u_prim.h"
39
40 #include "util/disk_cache.h"
41 #include "util/mesa-sha1.h"
42 #include "ac_exp_param.h"
43
44 /* SHADER_CACHE */
45
46 /**
47 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
48 * integer.
49 */
50 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
51 {
52 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
53 sizeof(struct tgsi_token);
54 unsigned size = 4 + tgsi_size + sizeof(sel->so);
55 char *result = (char*)MALLOC(size);
56
57 if (!result)
58 return NULL;
59
60 *((uint32_t*)result) = size;
61 memcpy(result + 4, sel->tokens, tgsi_size);
62 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
63 return result;
64 }
65
66 /** Copy "data" to "ptr" and return the next dword following copied data. */
67 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
68 {
69 /* data may be NULL if size == 0 */
70 if (size)
71 memcpy(ptr, data, size);
72 ptr += DIV_ROUND_UP(size, 4);
73 return ptr;
74 }
75
76 /** Read data from "ptr". Return the next dword following the data. */
77 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
78 {
79 memcpy(data, ptr, size);
80 ptr += DIV_ROUND_UP(size, 4);
81 return ptr;
82 }
83
84 /**
85 * Write the size as uint followed by the data. Return the next dword
86 * following the copied data.
87 */
88 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
89 {
90 *ptr++ = size;
91 return write_data(ptr, data, size);
92 }
93
94 /**
95 * Read the size as uint followed by the data. Return both via parameters.
96 * Return the next dword following the data.
97 */
98 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
99 {
100 *size = *ptr++;
101 assert(*data == NULL);
102 if (!*size)
103 return ptr;
104 *data = malloc(*size);
105 return read_data(ptr, *data, *size);
106 }
107
108 /**
109 * Return the shader binary in a buffer. The first 4 bytes contain its size
110 * as integer.
111 */
112 static void *si_get_shader_binary(struct si_shader *shader)
113 {
114 /* There is always a size of data followed by the data itself. */
115 unsigned relocs_size = shader->binary.reloc_count *
116 sizeof(shader->binary.relocs[0]);
117 unsigned disasm_size = shader->binary.disasm_string ?
118 strlen(shader->binary.disasm_string) + 1 : 0;
119 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
120 strlen(shader->binary.llvm_ir_string) + 1 : 0;
121 unsigned size =
122 4 + /* total size */
123 4 + /* CRC32 of the data below */
124 align(sizeof(shader->config), 4) +
125 align(sizeof(shader->info), 4) +
126 4 + align(shader->binary.code_size, 4) +
127 4 + align(shader->binary.rodata_size, 4) +
128 4 + align(relocs_size, 4) +
129 4 + align(disasm_size, 4) +
130 4 + align(llvm_ir_size, 4);
131 void *buffer = CALLOC(1, size);
132 uint32_t *ptr = (uint32_t*)buffer;
133
134 if (!buffer)
135 return NULL;
136
137 *ptr++ = size;
138 ptr++; /* CRC32 is calculated at the end. */
139
140 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
141 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
142 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
143 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
144 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
145 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
146 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
147 assert((char *)ptr - (char *)buffer == size);
148
149 /* Compute CRC32. */
150 ptr = (uint32_t*)buffer;
151 ptr++;
152 *ptr = util_hash_crc32(ptr + 1, size - 8);
153
154 return buffer;
155 }
156
157 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
158 {
159 uint32_t *ptr = (uint32_t*)binary;
160 uint32_t size = *ptr++;
161 uint32_t crc32 = *ptr++;
162 unsigned chunk_size;
163
164 if (util_hash_crc32(ptr, size - 8) != crc32) {
165 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
166 return false;
167 }
168
169 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
170 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
171 ptr = read_chunk(ptr, (void**)&shader->binary.code,
172 &shader->binary.code_size);
173 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
174 &shader->binary.rodata_size);
175 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
176 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
177 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
178 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
179
180 return true;
181 }
182
183 /**
184 * Insert a shader into the cache. It's assumed the shader is not in the cache.
185 * Use si_shader_cache_load_shader before calling this.
186 *
187 * Returns false on failure, in which case the tgsi_binary should be freed.
188 */
189 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
190 void *tgsi_binary,
191 struct si_shader *shader,
192 bool insert_into_disk_cache)
193 {
194 void *hw_binary;
195 struct hash_entry *entry;
196 uint8_t key[CACHE_KEY_SIZE];
197
198 entry = _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
199 if (entry)
200 return false; /* already added */
201
202 hw_binary = si_get_shader_binary(shader);
203 if (!hw_binary)
204 return false;
205
206 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
207 hw_binary) == NULL) {
208 FREE(hw_binary);
209 return false;
210 }
211
212 if (sscreen->b.disk_shader_cache && insert_into_disk_cache) {
213 disk_cache_compute_key(sscreen->b.disk_shader_cache, tgsi_binary,
214 *((uint32_t *)tgsi_binary), key);
215 disk_cache_put(sscreen->b.disk_shader_cache, key, hw_binary,
216 *((uint32_t *) hw_binary));
217 }
218
219 return true;
220 }
221
222 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
223 void *tgsi_binary,
224 struct si_shader *shader)
225 {
226 struct hash_entry *entry =
227 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
228 if (!entry) {
229 if (sscreen->b.disk_shader_cache) {
230 unsigned char sha1[CACHE_KEY_SIZE];
231 size_t tg_size = *((uint32_t *) tgsi_binary);
232
233 disk_cache_compute_key(sscreen->b.disk_shader_cache,
234 tgsi_binary, tg_size, sha1);
235
236 size_t binary_size;
237 uint8_t *buffer =
238 disk_cache_get(sscreen->b.disk_shader_cache,
239 sha1, &binary_size);
240 if (!buffer)
241 return false;
242
243 if (binary_size < sizeof(uint32_t) ||
244 *((uint32_t*)buffer) != binary_size) {
245 /* Something has gone wrong discard the item
246 * from the cache and rebuild/link from
247 * source.
248 */
249 assert(!"Invalid radeonsi shader disk cache "
250 "item!");
251
252 disk_cache_remove(sscreen->b.disk_shader_cache,
253 sha1);
254 free(buffer);
255
256 return false;
257 }
258
259 if (!si_load_shader_binary(shader, buffer)) {
260 free(buffer);
261 return false;
262 }
263 free(buffer);
264
265 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary,
266 shader, false))
267 FREE(tgsi_binary);
268 } else {
269 return false;
270 }
271 } else {
272 if (si_load_shader_binary(shader, entry->data))
273 FREE(tgsi_binary);
274 else
275 return false;
276 }
277 p_atomic_inc(&sscreen->b.num_shader_cache_hits);
278 return true;
279 }
280
281 static uint32_t si_shader_cache_key_hash(const void *key)
282 {
283 /* The first dword is the key size. */
284 return util_hash_crc32(key, *(uint32_t*)key);
285 }
286
287 static bool si_shader_cache_key_equals(const void *a, const void *b)
288 {
289 uint32_t *keya = (uint32_t*)a;
290 uint32_t *keyb = (uint32_t*)b;
291
292 /* The first dword is the key size. */
293 if (*keya != *keyb)
294 return false;
295
296 return memcmp(keya, keyb, *keya) == 0;
297 }
298
299 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
300 {
301 FREE((void*)entry->key);
302 FREE(entry->data);
303 }
304
305 bool si_init_shader_cache(struct si_screen *sscreen)
306 {
307 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
308 sscreen->shader_cache =
309 _mesa_hash_table_create(NULL,
310 si_shader_cache_key_hash,
311 si_shader_cache_key_equals);
312
313 return sscreen->shader_cache != NULL;
314 }
315
316 void si_destroy_shader_cache(struct si_screen *sscreen)
317 {
318 if (sscreen->shader_cache)
319 _mesa_hash_table_destroy(sscreen->shader_cache,
320 si_destroy_shader_cache_entry);
321 mtx_destroy(&sscreen->shader_cache_mutex);
322 }
323
324 /* SHADER STATES */
325
326 static void si_set_tesseval_regs(struct si_screen *sscreen,
327 struct si_shader_selector *tes,
328 struct si_pm4_state *pm4)
329 {
330 struct tgsi_shader_info *info = &tes->info;
331 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
332 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
333 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
334 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
335 unsigned type, partitioning, topology, distribution_mode;
336
337 switch (tes_prim_mode) {
338 case PIPE_PRIM_LINES:
339 type = V_028B6C_TESS_ISOLINE;
340 break;
341 case PIPE_PRIM_TRIANGLES:
342 type = V_028B6C_TESS_TRIANGLE;
343 break;
344 case PIPE_PRIM_QUADS:
345 type = V_028B6C_TESS_QUAD;
346 break;
347 default:
348 assert(0);
349 return;
350 }
351
352 switch (tes_spacing) {
353 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
354 partitioning = V_028B6C_PART_FRAC_ODD;
355 break;
356 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
357 partitioning = V_028B6C_PART_FRAC_EVEN;
358 break;
359 case PIPE_TESS_SPACING_EQUAL:
360 partitioning = V_028B6C_PART_INTEGER;
361 break;
362 default:
363 assert(0);
364 return;
365 }
366
367 if (tes_point_mode)
368 topology = V_028B6C_OUTPUT_POINT;
369 else if (tes_prim_mode == PIPE_PRIM_LINES)
370 topology = V_028B6C_OUTPUT_LINE;
371 else if (tes_vertex_order_cw)
372 /* for some reason, this must be the other way around */
373 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
374 else
375 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
376
377 if (sscreen->has_distributed_tess) {
378 if (sscreen->b.family == CHIP_FIJI ||
379 sscreen->b.family >= CHIP_POLARIS10)
380 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
381 else
382 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
383 } else
384 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
385
386 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
387 S_028B6C_TYPE(type) |
388 S_028B6C_PARTITIONING(partitioning) |
389 S_028B6C_TOPOLOGY(topology) |
390 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
391 }
392
393 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
394 * whether the "fractional odd" tessellation spacing is used.
395 *
396 * Possible VGT configurations and which state should set the register:
397 *
398 * Reg set in | VGT shader configuration | Value
399 * ------------------------------------------------------
400 * VS as VS | VS | 30
401 * VS as ES | ES -> GS -> VS | 30
402 * TES as VS | LS -> HS -> VS | 14 or 30
403 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
404 *
405 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
406 */
407 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
408 struct si_shader_selector *sel,
409 struct si_shader *shader,
410 struct si_pm4_state *pm4)
411 {
412 unsigned type = sel->type;
413
414 if (sscreen->b.family < CHIP_POLARIS10)
415 return;
416
417 /* VS as VS, or VS as ES: */
418 if ((type == PIPE_SHADER_VERTEX &&
419 (!shader ||
420 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
421 /* TES as VS, or TES as ES: */
422 type == PIPE_SHADER_TESS_EVAL) {
423 unsigned vtx_reuse_depth = 30;
424
425 if (type == PIPE_SHADER_TESS_EVAL &&
426 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
427 PIPE_TESS_SPACING_FRACTIONAL_ODD)
428 vtx_reuse_depth = 14;
429
430 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
431 vtx_reuse_depth);
432 }
433 }
434
435 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
436 {
437 if (shader->pm4)
438 si_pm4_clear_state(shader->pm4);
439 else
440 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
441
442 return shader->pm4;
443 }
444
445 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
446 {
447 struct si_pm4_state *pm4;
448 unsigned vgpr_comp_cnt;
449 uint64_t va;
450
451 assert(sscreen->b.chip_class <= VI);
452
453 pm4 = si_get_shader_pm4_state(shader);
454 if (!pm4)
455 return;
456
457 va = shader->bo->gpu_address;
458 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
459
460 /* We need at least 2 components for LS.
461 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
462 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
463 */
464 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
465
466 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
467 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
468
469 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
470 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
471 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
472 S_00B528_DX10_CLAMP(1) |
473 S_00B528_FLOAT_MODE(shader->config.float_mode);
474 shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR) |
475 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
476 }
477
478 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
479 {
480 struct si_pm4_state *pm4;
481 uint64_t va;
482 unsigned ls_vgpr_comp_cnt = 0;
483
484 pm4 = si_get_shader_pm4_state(shader);
485 if (!pm4)
486 return;
487
488 va = shader->bo->gpu_address;
489 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
490
491 if (sscreen->b.chip_class >= GFX9) {
492 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
493 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, va >> 40);
494
495 /* We need at least 2 components for LS.
496 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
497 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
498 */
499 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
500
501 shader->config.rsrc2 =
502 S_00B42C_USER_SGPR(GFX9_TCS_NUM_USER_SGPR) |
503 S_00B42C_USER_SGPR_MSB(GFX9_TCS_NUM_USER_SGPR >> 5) |
504 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
505 } else {
506 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
507 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
508
509 shader->config.rsrc2 =
510 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
511 S_00B42C_OC_LDS_EN(1) |
512 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
513 }
514
515 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
516 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
517 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
518 S_00B428_DX10_CLAMP(1) |
519 S_00B428_FLOAT_MODE(shader->config.float_mode) |
520 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
521
522 if (sscreen->b.chip_class <= VI) {
523 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
524 shader->config.rsrc2);
525 }
526 }
527
528 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
529 {
530 struct si_pm4_state *pm4;
531 unsigned num_user_sgprs;
532 unsigned vgpr_comp_cnt;
533 uint64_t va;
534 unsigned oc_lds_en;
535
536 assert(sscreen->b.chip_class <= VI);
537
538 pm4 = si_get_shader_pm4_state(shader);
539 if (!pm4)
540 return;
541
542 va = shader->bo->gpu_address;
543 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
544
545 if (shader->selector->type == PIPE_SHADER_VERTEX) {
546 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
547 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
548 num_user_sgprs = SI_VS_NUM_USER_SGPR;
549 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
550 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
551 num_user_sgprs = SI_TES_NUM_USER_SGPR;
552 } else
553 unreachable("invalid shader selector type");
554
555 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
556
557 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
558 shader->selector->esgs_itemsize / 4);
559 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
560 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
561 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
562 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
563 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
564 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
565 S_00B328_DX10_CLAMP(1) |
566 S_00B328_FLOAT_MODE(shader->config.float_mode));
567 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
568 S_00B32C_USER_SGPR(num_user_sgprs) |
569 S_00B32C_OC_LDS_EN(oc_lds_en) |
570 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
571
572 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
573 si_set_tesseval_regs(sscreen, shader->selector, pm4);
574
575 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
576 }
577
578 /**
579 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
580 * geometry shader.
581 */
582 static uint32_t si_vgt_gs_mode(struct si_shader_selector *sel)
583 {
584 enum chip_class chip_class = sel->screen->b.chip_class;
585 unsigned gs_max_vert_out = sel->gs_max_out_vertices;
586 unsigned cut_mode;
587
588 if (gs_max_vert_out <= 128) {
589 cut_mode = V_028A40_GS_CUT_128;
590 } else if (gs_max_vert_out <= 256) {
591 cut_mode = V_028A40_GS_CUT_256;
592 } else if (gs_max_vert_out <= 512) {
593 cut_mode = V_028A40_GS_CUT_512;
594 } else {
595 assert(gs_max_vert_out <= 1024);
596 cut_mode = V_028A40_GS_CUT_1024;
597 }
598
599 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
600 S_028A40_CUT_MODE(cut_mode)|
601 S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) |
602 S_028A40_GS_WRITE_OPTIMIZE(1) |
603 S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
604 }
605
606 struct gfx9_gs_info {
607 unsigned es_verts_per_subgroup;
608 unsigned gs_prims_per_subgroup;
609 unsigned gs_inst_prims_in_subgroup;
610 unsigned max_prims_per_subgroup;
611 unsigned lds_size;
612 };
613
614 static void gfx9_get_gs_info(struct si_shader_selector *es,
615 struct si_shader_selector *gs,
616 struct gfx9_gs_info *out)
617 {
618 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
619 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
620 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
621 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
622
623 /* All these are in dwords: */
624 /* We can't allow using the whole LDS, because GS waves compete with
625 * other shader stages for LDS space. */
626 const unsigned max_lds_size = 8 * 1024;
627 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
628 unsigned esgs_lds_size;
629
630 /* All these are per subgroup: */
631 const unsigned max_out_prims = 32 * 1024;
632 const unsigned max_es_verts = 255;
633 const unsigned ideal_gs_prims = 64;
634 unsigned max_gs_prims, gs_prims;
635 unsigned min_es_verts, es_verts, worst_case_es_verts;
636
637 assert(gs_num_invocations <= 32); /* GL maximum */
638
639 if (uses_adjacency || gs_num_invocations > 1)
640 max_gs_prims = 127 / gs_num_invocations;
641 else
642 max_gs_prims = 255;
643
644 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
645 * Make sure we don't go over the maximum value.
646 */
647 max_gs_prims = MIN2(max_gs_prims,
648 max_out_prims /
649 (gs->gs_max_out_vertices * gs_num_invocations));
650 assert(max_gs_prims > 0);
651
652 /* If the primitive has adjacency, halve the number of vertices
653 * that will be reused in multiple primitives.
654 */
655 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
656
657 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
658 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
659
660 /* Compute ESGS LDS size based on the worst case number of ES vertices
661 * needed to create the target number of GS prims per subgroup.
662 */
663 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
664
665 /* If total LDS usage is too big, refactor partitions based on ratio
666 * of ESGS item sizes.
667 */
668 if (esgs_lds_size > max_lds_size) {
669 /* Our target GS Prims Per Subgroup was too large. Calculate
670 * the maximum number of GS Prims Per Subgroup that will fit
671 * into LDS, capped by the maximum that the hardware can support.
672 */
673 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
674 max_gs_prims);
675 assert(gs_prims > 0);
676 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
677 max_es_verts);
678
679 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
680 assert(esgs_lds_size <= max_lds_size);
681 }
682
683 /* Now calculate remaining ESGS information. */
684 if (esgs_lds_size)
685 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
686 else
687 es_verts = max_es_verts;
688
689 /* Vertices for adjacency primitives are not always reused, so restore
690 * it for ES_VERTS_PER_SUBGRP.
691 */
692 min_es_verts = gs->gs_input_verts_per_prim;
693
694 /* For normal primitives, the VGT only checks if they are past the ES
695 * verts per subgroup after allocating a full GS primitive and if they
696 * are, kick off a new subgroup. But if those additional ES verts are
697 * unique (e.g. not reused) we need to make sure there is enough LDS
698 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
699 */
700 es_verts -= min_es_verts - 1;
701
702 out->es_verts_per_subgroup = es_verts;
703 out->gs_prims_per_subgroup = gs_prims;
704 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
705 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
706 gs->gs_max_out_vertices;
707 out->lds_size = align(esgs_lds_size, 128) / 128;
708
709 assert(out->max_prims_per_subgroup <= max_out_prims);
710 }
711
712 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
713 {
714 struct si_shader_selector *sel = shader->selector;
715 const ubyte *num_components = sel->info.num_stream_output_components;
716 unsigned gs_num_invocations = sel->gs_num_invocations;
717 struct si_pm4_state *pm4;
718 uint64_t va;
719 unsigned max_stream = sel->max_gs_stream;
720 unsigned offset;
721
722 pm4 = si_get_shader_pm4_state(shader);
723 if (!pm4)
724 return;
725
726 offset = num_components[0] * sel->gs_max_out_vertices;
727 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
728 if (max_stream >= 1)
729 offset += num_components[1] * sel->gs_max_out_vertices;
730 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
731 if (max_stream >= 2)
732 offset += num_components[2] * sel->gs_max_out_vertices;
733 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
734 if (max_stream >= 3)
735 offset += num_components[3] * sel->gs_max_out_vertices;
736 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
737
738 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
739 assert(offset < (1 << 15));
740
741 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, sel->gs_max_out_vertices);
742
743 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
744 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
745 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
746 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
747
748 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
749 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
750 S_028B90_ENABLE(gs_num_invocations > 0));
751
752 va = shader->bo->gpu_address;
753 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
754
755 if (sscreen->b.chip_class >= GFX9) {
756 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
757 unsigned es_type = shader->key.part.gs.es->type;
758 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
759 struct gfx9_gs_info gs_info;
760
761 if (es_type == PIPE_SHADER_VERTEX)
762 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
763 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
764 else if (es_type == PIPE_SHADER_TESS_EVAL)
765 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
766 else
767 unreachable("invalid shader selector type");
768
769 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
770 * VGPR[0:4] are always loaded.
771 */
772 if (sel->info.uses_invocationid)
773 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
774 else if (sel->info.uses_primid)
775 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
776 else if (input_prim >= PIPE_PRIM_TRIANGLES)
777 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
778 else
779 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
780
781 gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
782
783 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
784 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, va >> 40);
785
786 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
787 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
788 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
789 S_00B228_DX10_CLAMP(1) |
790 S_00B228_FLOAT_MODE(shader->config.float_mode) |
791 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
792 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
793 S_00B22C_USER_SGPR(GFX9_GS_NUM_USER_SGPR) |
794 S_00B22C_USER_SGPR_MSB(GFX9_GS_NUM_USER_SGPR >> 5) |
795 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
796 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
797 S_00B22C_LDS_SIZE(gs_info.lds_size) |
798 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
799
800 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
801 S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) |
802 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) |
803 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup));
804 si_pm4_set_reg(pm4, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
805 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup));
806 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
807 shader->key.part.gs.es->esgs_itemsize / 4);
808
809 if (es_type == PIPE_SHADER_TESS_EVAL)
810 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
811
812 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
813 NULL, pm4);
814 } else {
815 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
816 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
817
818 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
819 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
820 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
821 S_00B228_DX10_CLAMP(1) |
822 S_00B228_FLOAT_MODE(shader->config.float_mode));
823 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
824 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
825 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
826 }
827 }
828
829 /**
830 * Compute the state for \p shader, which will run as a vertex shader on the
831 * hardware.
832 *
833 * If \p gs is non-NULL, it points to the geometry shader for which this shader
834 * is the copy shader.
835 */
836 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
837 struct si_shader_selector *gs)
838 {
839 struct si_pm4_state *pm4;
840 unsigned num_user_sgprs;
841 unsigned nparams, vgpr_comp_cnt;
842 uint64_t va;
843 unsigned oc_lds_en;
844 unsigned window_space =
845 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
846 bool enable_prim_id = shader->key.mono.vs_export_prim_id || shader->selector->info.uses_primid;
847
848 pm4 = si_get_shader_pm4_state(shader);
849 if (!pm4)
850 return;
851
852 /* We always write VGT_GS_MODE in the VS state, because every switch
853 * between different shader pipelines involving a different GS or no
854 * GS at all involves a switch of the VS (different GS use different
855 * copy shaders). On the other hand, when the API switches from a GS to
856 * no GS and then back to the same GS used originally, the GS state is
857 * not sent again.
858 */
859 if (!gs) {
860 unsigned mode = 0;
861
862 /* PrimID needs GS scenario A.
863 * GFX9 also needs it when ViewportIndex is enabled.
864 */
865 if (enable_prim_id ||
866 (sscreen->b.chip_class >= GFX9 &&
867 shader->selector->info.writes_viewport_index))
868 mode = V_028A40_GS_SCENARIO_A;
869
870 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, S_028A40_MODE(mode));
871 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
872 } else {
873 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
874 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
875 }
876
877 va = shader->bo->gpu_address;
878 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
879
880 if (gs) {
881 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
882 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
883 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
884 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
885 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
886 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
887 */
888 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
889 num_user_sgprs = SI_VS_NUM_USER_SGPR;
890 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
891 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
892 num_user_sgprs = SI_TES_NUM_USER_SGPR;
893 } else
894 unreachable("invalid shader selector type");
895
896 /* VS is required to export at least one param. */
897 nparams = MAX2(shader->info.nr_param_exports, 1);
898 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
899 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
900
901 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
902 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
903 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
904 V_02870C_SPI_SHADER_4COMP :
905 V_02870C_SPI_SHADER_NONE) |
906 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
907 V_02870C_SPI_SHADER_4COMP :
908 V_02870C_SPI_SHADER_NONE) |
909 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
910 V_02870C_SPI_SHADER_4COMP :
911 V_02870C_SPI_SHADER_NONE));
912
913 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
914
915 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
916 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
917 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
918 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
919 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
920 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
921 S_00B128_DX10_CLAMP(1) |
922 S_00B128_FLOAT_MODE(shader->config.float_mode));
923 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
924 S_00B12C_USER_SGPR(num_user_sgprs) |
925 S_00B12C_OC_LDS_EN(oc_lds_en) |
926 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
927 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
928 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
929 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
930 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
931 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
932 if (window_space)
933 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
934 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
935 else
936 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
937 S_028818_VTX_W0_FMT(1) |
938 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
939 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
940 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
941
942 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
943 si_set_tesseval_regs(sscreen, shader->selector, pm4);
944
945 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
946 }
947
948 static unsigned si_get_ps_num_interp(struct si_shader *ps)
949 {
950 struct tgsi_shader_info *info = &ps->selector->info;
951 unsigned num_colors = !!(info->colors_read & 0x0f) +
952 !!(info->colors_read & 0xf0);
953 unsigned num_interp = ps->selector->info.num_inputs +
954 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
955
956 assert(num_interp <= 32);
957 return MIN2(num_interp, 32);
958 }
959
960 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
961 {
962 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
963 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
964
965 /* If the i-th target format is set, all previous target formats must
966 * be non-zero to avoid hangs.
967 */
968 for (i = 0; i < num_targets; i++)
969 if (!(value & (0xf << (i * 4))))
970 value |= V_028714_SPI_SHADER_32_R << (i * 4);
971
972 return value;
973 }
974
975 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
976 {
977 unsigned i, cb_shader_mask = 0;
978
979 for (i = 0; i < 8; i++) {
980 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
981 case V_028714_SPI_SHADER_ZERO:
982 break;
983 case V_028714_SPI_SHADER_32_R:
984 cb_shader_mask |= 0x1 << (i * 4);
985 break;
986 case V_028714_SPI_SHADER_32_GR:
987 cb_shader_mask |= 0x3 << (i * 4);
988 break;
989 case V_028714_SPI_SHADER_32_AR:
990 cb_shader_mask |= 0x9 << (i * 4);
991 break;
992 case V_028714_SPI_SHADER_FP16_ABGR:
993 case V_028714_SPI_SHADER_UNORM16_ABGR:
994 case V_028714_SPI_SHADER_SNORM16_ABGR:
995 case V_028714_SPI_SHADER_UINT16_ABGR:
996 case V_028714_SPI_SHADER_SINT16_ABGR:
997 case V_028714_SPI_SHADER_32_ABGR:
998 cb_shader_mask |= 0xf << (i * 4);
999 break;
1000 default:
1001 assert(0);
1002 }
1003 }
1004 return cb_shader_mask;
1005 }
1006
1007 static void si_shader_ps(struct si_shader *shader)
1008 {
1009 struct tgsi_shader_info *info = &shader->selector->info;
1010 struct si_pm4_state *pm4;
1011 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1012 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1013 uint64_t va;
1014 unsigned input_ena = shader->config.spi_ps_input_ena;
1015
1016 /* we need to enable at least one of them, otherwise we hang the GPU */
1017 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1018 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1019 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1020 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1021 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1022 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1023 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1024 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1025 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1026 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1027 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1028 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1029 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1030 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1031
1032 /* Validate interpolation optimization flags (read as implications). */
1033 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1034 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1035 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1036 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1037 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1038 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1039 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1040 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1041 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1042 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1043 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1044 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1045 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1046 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1047 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1048 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1049 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1050 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1051
1052 /* Validate cases when the optimizations are off (read as implications). */
1053 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1054 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1055 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1056 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1057 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1058 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1059
1060 pm4 = si_get_shader_pm4_state(shader);
1061 if (!pm4)
1062 return;
1063
1064 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1065 * Possible vaules:
1066 * 0 -> Position = pixel center
1067 * 1 -> Position = pixel centroid
1068 * 2 -> Position = at sample position
1069 *
1070 * From GLSL 4.5 specification, section 7.1:
1071 * "The variable gl_FragCoord is available as an input variable from
1072 * within fragment shaders and it holds the window relative coordinates
1073 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1074 * value can be for any location within the pixel, or one of the
1075 * fragment samples. The use of centroid does not further restrict
1076 * this value to be inside the current primitive."
1077 *
1078 * Meaning that centroid has no effect and we can return anything within
1079 * the pixel. Thus, return the value at sample position, because that's
1080 * the most accurate one shaders can get.
1081 */
1082 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1083
1084 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1085 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1086 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1087
1088 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1089 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
1090
1091 /* Ensure that some export memory is always allocated, for two reasons:
1092 *
1093 * 1) Correctness: The hardware ignores the EXEC mask if no export
1094 * memory is allocated, so KILL and alpha test do not work correctly
1095 * without this.
1096 * 2) Performance: Every shader needs at least a NULL export, even when
1097 * it writes no color/depth output. The NULL export instruction
1098 * stalls without this setting.
1099 *
1100 * Don't add this to CB_SHADER_MASK.
1101 */
1102 if (!spi_shader_col_format &&
1103 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1104 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1105
1106 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
1107 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
1108 shader->config.spi_ps_input_addr);
1109
1110 /* Set interpolation controls. */
1111 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1112
1113 /* Set registers. */
1114 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1115 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
1116
1117 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
1118 si_get_spi_shader_z_format(info->writes_z,
1119 info->writes_stencil,
1120 info->writes_samplemask));
1121
1122 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
1123 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
1124
1125 va = shader->bo->gpu_address;
1126 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1127 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1128 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
1129
1130 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1131 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1132 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
1133 S_00B028_DX10_CLAMP(1) |
1134 S_00B028_FLOAT_MODE(shader->config.float_mode));
1135 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1136 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1137 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1138 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1139 }
1140
1141 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1142 struct si_shader *shader)
1143 {
1144 switch (shader->selector->type) {
1145 case PIPE_SHADER_VERTEX:
1146 if (shader->key.as_ls)
1147 si_shader_ls(sscreen, shader);
1148 else if (shader->key.as_es)
1149 si_shader_es(sscreen, shader);
1150 else
1151 si_shader_vs(sscreen, shader, NULL);
1152 break;
1153 case PIPE_SHADER_TESS_CTRL:
1154 si_shader_hs(sscreen, shader);
1155 break;
1156 case PIPE_SHADER_TESS_EVAL:
1157 if (shader->key.as_es)
1158 si_shader_es(sscreen, shader);
1159 else
1160 si_shader_vs(sscreen, shader, NULL);
1161 break;
1162 case PIPE_SHADER_GEOMETRY:
1163 si_shader_gs(sscreen, shader);
1164 break;
1165 case PIPE_SHADER_FRAGMENT:
1166 si_shader_ps(shader);
1167 break;
1168 default:
1169 assert(0);
1170 }
1171 }
1172
1173 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1174 {
1175 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1176 if (sctx->queued.named.dsa)
1177 return sctx->queued.named.dsa->alpha_func;
1178
1179 return PIPE_FUNC_ALWAYS;
1180 }
1181
1182 static void si_shader_selector_key_vs(struct si_context *sctx,
1183 struct si_shader_selector *vs,
1184 struct si_shader_key *key,
1185 struct si_vs_prolog_bits *prolog_key)
1186 {
1187 if (!sctx->vertex_elements)
1188 return;
1189
1190 unsigned count = MIN2(vs->info.num_inputs,
1191 sctx->vertex_elements->count);
1192 for (unsigned i = 0; i < count; ++i) {
1193 prolog_key->instance_divisors[i] =
1194 sctx->vertex_elements->elements[i].instance_divisor;
1195 }
1196
1197 memcpy(key->mono.vs_fix_fetch, sctx->vertex_elements->fix_fetch, count);
1198 }
1199
1200 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1201 struct si_shader_selector *vs,
1202 struct si_shader_key *key)
1203 {
1204 struct si_shader_selector *ps = sctx->ps_shader.cso;
1205
1206 key->opt.hw_vs.clip_disable =
1207 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1208 (vs->info.clipdist_writemask ||
1209 vs->info.writes_clipvertex) &&
1210 !vs->info.culldist_writemask;
1211
1212 /* Find out if PS is disabled. */
1213 bool ps_disabled = true;
1214 if (ps) {
1215 bool ps_modifies_zs = ps->info.uses_kill ||
1216 ps->info.writes_z ||
1217 ps->info.writes_stencil ||
1218 ps->info.writes_samplemask ||
1219 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1220
1221 unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1222 sctx->queued.named.blend->cb_target_mask;
1223 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1224 ps_colormask &= ps->colors_written_4bit;
1225
1226 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1227 (!ps_colormask &&
1228 !ps_modifies_zs &&
1229 !ps->info.writes_memory);
1230 }
1231
1232 /* Find out which VS outputs aren't used by the PS. */
1233 uint64_t outputs_written = vs->outputs_written;
1234 uint64_t inputs_read = 0;
1235
1236 outputs_written &= ~0x3; /* ignore POSITION, PSIZE */
1237
1238 if (!ps_disabled) {
1239 inputs_read = ps->inputs_read;
1240 }
1241
1242 uint64_t linked = outputs_written & inputs_read;
1243
1244 key->opt.hw_vs.kill_outputs = ~linked & outputs_written;
1245 }
1246
1247 /* Compute the key for the hw shader variant */
1248 static inline void si_shader_selector_key(struct pipe_context *ctx,
1249 struct si_shader_selector *sel,
1250 struct si_shader_key *key)
1251 {
1252 struct si_context *sctx = (struct si_context *)ctx;
1253
1254 memset(key, 0, sizeof(*key));
1255
1256 switch (sel->type) {
1257 case PIPE_SHADER_VERTEX:
1258 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1259
1260 if (sctx->tes_shader.cso)
1261 key->as_ls = 1;
1262 else if (sctx->gs_shader.cso)
1263 key->as_es = 1;
1264 else {
1265 si_shader_selector_key_hw_vs(sctx, sel, key);
1266
1267 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1268 key->mono.vs_export_prim_id = 1;
1269 }
1270 break;
1271 case PIPE_SHADER_TESS_CTRL:
1272 if (sctx->b.chip_class >= GFX9) {
1273 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1274 key, &key->part.tcs.ls_prolog);
1275 key->part.tcs.ls = sctx->vs_shader.cso;
1276 }
1277
1278 key->part.tcs.epilog.prim_mode =
1279 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1280 key->part.tcs.epilog.tes_reads_tess_factors =
1281 sctx->tes_shader.cso->info.reads_tess_factors;
1282
1283 if (sel == sctx->fixed_func_tcs_shader.cso)
1284 key->mono.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1285 break;
1286 case PIPE_SHADER_TESS_EVAL:
1287 if (sctx->gs_shader.cso)
1288 key->as_es = 1;
1289 else {
1290 si_shader_selector_key_hw_vs(sctx, sel, key);
1291
1292 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1293 key->mono.vs_export_prim_id = 1;
1294 }
1295 break;
1296 case PIPE_SHADER_GEOMETRY:
1297 if (sctx->b.chip_class >= GFX9) {
1298 if (sctx->tes_shader.cso) {
1299 key->part.gs.es = sctx->tes_shader.cso;
1300 } else {
1301 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1302 key, &key->part.gs.vs_prolog);
1303 key->part.gs.es = sctx->vs_shader.cso;
1304 }
1305
1306 /* Merged ES-GS can have unbalanced wave usage.
1307 *
1308 * ES threads are per-vertex, while GS threads are
1309 * per-primitive. So without any amplification, there
1310 * are fewer GS threads than ES threads, which can result
1311 * in empty (no-op) GS waves. With too much amplification,
1312 * there are more GS threads than ES threads, which
1313 * can result in empty (no-op) ES waves.
1314 *
1315 * Non-monolithic shaders are implemented by setting EXEC
1316 * at the beginning of shader parts, and don't jump to
1317 * the end if EXEC is 0.
1318 *
1319 * Monolithic shaders use conditional blocks, so they can
1320 * jump and skip empty waves of ES or GS. So set this to
1321 * always use optimized variants, which are monolithic.
1322 */
1323 key->opt.prefer_mono = 1;
1324 }
1325 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1326 break;
1327 case PIPE_SHADER_FRAGMENT: {
1328 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1329 struct si_state_blend *blend = sctx->queued.named.blend;
1330
1331 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1332 sel->info.colors_written == 0x1)
1333 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1334
1335 if (blend) {
1336 /* Select the shader color format based on whether
1337 * blending or alpha are needed.
1338 */
1339 key->part.ps.epilog.spi_shader_col_format =
1340 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1341 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1342 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1343 sctx->framebuffer.spi_shader_col_format_blend) |
1344 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1345 sctx->framebuffer.spi_shader_col_format_alpha) |
1346 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1347 sctx->framebuffer.spi_shader_col_format);
1348
1349 /* The output for dual source blending should have
1350 * the same format as the first output.
1351 */
1352 if (blend->dual_src_blend)
1353 key->part.ps.epilog.spi_shader_col_format |=
1354 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1355 } else
1356 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1357
1358 /* If alpha-to-coverage is enabled, we have to export alpha
1359 * even if there is no color buffer.
1360 */
1361 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1362 blend && blend->alpha_to_coverage)
1363 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1364
1365 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1366 * to the range supported by the type if a channel has less
1367 * than 16 bits and the export format is 16_ABGR.
1368 */
1369 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII) {
1370 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1371 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1372 }
1373
1374 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1375 if (!key->part.ps.epilog.last_cbuf) {
1376 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1377 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1378 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1379 }
1380
1381 if (rs) {
1382 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
1383 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
1384 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
1385 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
1386
1387 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1388 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1389
1390 if (sctx->queued.named.blend) {
1391 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1392 rs->multisample_enable;
1393 }
1394
1395 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1396 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1397 (is_line && rs->line_smooth)) &&
1398 sctx->framebuffer.nr_samples <= 1;
1399 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1400
1401 if (rs->force_persample_interp &&
1402 rs->multisample_enable &&
1403 sctx->framebuffer.nr_samples > 1 &&
1404 sctx->ps_iter_samples > 1) {
1405 key->part.ps.prolog.force_persp_sample_interp =
1406 sel->info.uses_persp_center ||
1407 sel->info.uses_persp_centroid;
1408
1409 key->part.ps.prolog.force_linear_sample_interp =
1410 sel->info.uses_linear_center ||
1411 sel->info.uses_linear_centroid;
1412 } else if (rs->multisample_enable &&
1413 sctx->framebuffer.nr_samples > 1) {
1414 key->part.ps.prolog.bc_optimize_for_persp =
1415 sel->info.uses_persp_center &&
1416 sel->info.uses_persp_centroid;
1417 key->part.ps.prolog.bc_optimize_for_linear =
1418 sel->info.uses_linear_center &&
1419 sel->info.uses_linear_centroid;
1420 } else {
1421 /* Make sure SPI doesn't compute more than 1 pair
1422 * of (i,j), which is the optimization here. */
1423 key->part.ps.prolog.force_persp_center_interp =
1424 sel->info.uses_persp_center +
1425 sel->info.uses_persp_centroid +
1426 sel->info.uses_persp_sample > 1;
1427
1428 key->part.ps.prolog.force_linear_center_interp =
1429 sel->info.uses_linear_center +
1430 sel->info.uses_linear_centroid +
1431 sel->info.uses_linear_sample > 1;
1432 }
1433 }
1434
1435 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1436 break;
1437 }
1438 default:
1439 assert(0);
1440 }
1441
1442 if (unlikely(sctx->screen->b.debug_flags & DBG_NO_OPT_VARIANT))
1443 memset(&key->opt, 0, sizeof(key->opt));
1444 }
1445
1446 static void si_build_shader_variant(void *job, int thread_index)
1447 {
1448 struct si_shader *shader = (struct si_shader *)job;
1449 struct si_shader_selector *sel = shader->selector;
1450 struct si_screen *sscreen = sel->screen;
1451 LLVMTargetMachineRef tm;
1452 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1453 int r;
1454
1455 if (thread_index >= 0) {
1456 assert(thread_index < ARRAY_SIZE(sscreen->tm_low_priority));
1457 tm = sscreen->tm_low_priority[thread_index];
1458 if (!debug->async)
1459 debug = NULL;
1460 } else {
1461 tm = shader->compiler_ctx_state.tm;
1462 }
1463
1464 r = si_shader_create(sscreen, tm, shader, debug);
1465 if (unlikely(r)) {
1466 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1467 sel->type, r);
1468 shader->compilation_failed = true;
1469 return;
1470 }
1471
1472 if (shader->compiler_ctx_state.is_debug_context) {
1473 FILE *f = open_memstream(&shader->shader_log,
1474 &shader->shader_log_size);
1475 if (f) {
1476 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1477 fclose(f);
1478 }
1479 }
1480
1481 si_shader_init_pm4_state(sscreen, shader);
1482 }
1483
1484 static const struct si_shader_key zeroed;
1485
1486 static bool si_check_missing_main_part(struct si_screen *sscreen,
1487 struct si_shader_selector *sel,
1488 struct si_compiler_ctx_state *compiler_state,
1489 struct si_shader_key *key)
1490 {
1491 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1492
1493 if (!*mainp) {
1494 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1495
1496 if (!main_part)
1497 return false;
1498
1499 main_part->selector = sel;
1500 main_part->key.as_es = key->as_es;
1501 main_part->key.as_ls = key->as_ls;
1502
1503 if (si_compile_tgsi_shader(sscreen, compiler_state->tm,
1504 main_part, false,
1505 &compiler_state->debug) != 0) {
1506 FREE(main_part);
1507 return false;
1508 }
1509 *mainp = main_part;
1510 }
1511 return true;
1512 }
1513
1514 static void si_destroy_shader_selector(struct si_context *sctx,
1515 struct si_shader_selector *sel);
1516
1517 static void si_shader_selector_reference(struct si_context *sctx,
1518 struct si_shader_selector **dst,
1519 struct si_shader_selector *src)
1520 {
1521 if (pipe_reference(&(*dst)->reference, &src->reference))
1522 si_destroy_shader_selector(sctx, *dst);
1523
1524 *dst = src;
1525 }
1526
1527 /* Select the hw shader variant depending on the current state. */
1528 static int si_shader_select_with_key(struct si_screen *sscreen,
1529 struct si_shader_ctx_state *state,
1530 struct si_compiler_ctx_state *compiler_state,
1531 struct si_shader_key *key,
1532 int thread_index)
1533 {
1534 struct si_shader_selector *sel = state->cso;
1535 struct si_shader_selector *previous_stage_sel = NULL;
1536 struct si_shader *current = state->current;
1537 struct si_shader *iter, *shader = NULL;
1538
1539 again:
1540 /* Check if we don't need to change anything.
1541 * This path is also used for most shaders that don't need multiple
1542 * variants, it will cost just a computation of the key and this
1543 * test. */
1544 if (likely(current &&
1545 memcmp(&current->key, key, sizeof(*key)) == 0 &&
1546 (!current->is_optimized ||
1547 util_queue_fence_is_signalled(&current->optimized_ready))))
1548 return current->compilation_failed ? -1 : 0;
1549
1550 /* This must be done before the mutex is locked, because async GS
1551 * compilation calls this function too, and therefore must enter
1552 * the mutex first.
1553 *
1554 * Only wait if we are in a draw call. Don't wait if we are
1555 * in a compiler thread.
1556 */
1557 if (thread_index < 0)
1558 util_queue_fence_wait(&sel->ready);
1559
1560 mtx_lock(&sel->mutex);
1561
1562 /* Find the shader variant. */
1563 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1564 /* Don't check the "current" shader. We checked it above. */
1565 if (current != iter &&
1566 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1567 /* If it's an optimized shader and its compilation has
1568 * been started but isn't done, use the unoptimized
1569 * shader so as not to cause a stall due to compilation.
1570 */
1571 if (iter->is_optimized &&
1572 !util_queue_fence_is_signalled(&iter->optimized_ready)) {
1573 memset(&key->opt, 0, sizeof(key->opt));
1574 mtx_unlock(&sel->mutex);
1575 goto again;
1576 }
1577
1578 if (iter->compilation_failed) {
1579 mtx_unlock(&sel->mutex);
1580 return -1; /* skip the draw call */
1581 }
1582
1583 state->current = iter;
1584 mtx_unlock(&sel->mutex);
1585 return 0;
1586 }
1587 }
1588
1589 /* Build a new shader. */
1590 shader = CALLOC_STRUCT(si_shader);
1591 if (!shader) {
1592 mtx_unlock(&sel->mutex);
1593 return -ENOMEM;
1594 }
1595 shader->selector = sel;
1596 shader->key = *key;
1597 shader->compiler_ctx_state = *compiler_state;
1598
1599 /* If this is a merged shader, get the first shader's selector. */
1600 if (sscreen->b.chip_class >= GFX9) {
1601 if (sel->type == PIPE_SHADER_TESS_CTRL)
1602 previous_stage_sel = key->part.tcs.ls;
1603 else if (sel->type == PIPE_SHADER_GEOMETRY)
1604 previous_stage_sel = key->part.gs.es;
1605
1606 /* We need to wait for the previous shader. */
1607 if (previous_stage_sel && thread_index < 0)
1608 util_queue_fence_wait(&previous_stage_sel->ready);
1609 }
1610
1611 /* Compile the main shader part if it doesn't exist. This can happen
1612 * if the initial guess was wrong. */
1613 bool is_pure_monolithic =
1614 sscreen->use_monolithic_shaders ||
1615 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1616
1617 if (!is_pure_monolithic) {
1618 bool ok;
1619
1620 /* Make sure the main shader part is present. This is needed
1621 * for shaders that can be compiled as VS, LS, or ES, and only
1622 * one of them is compiled at creation.
1623 *
1624 * For merged shaders, check that the starting shader's main
1625 * part is present.
1626 */
1627 if (previous_stage_sel) {
1628 struct si_shader_key shader1_key = zeroed;
1629
1630 if (sel->type == PIPE_SHADER_TESS_CTRL)
1631 shader1_key.as_ls = 1;
1632 else if (sel->type == PIPE_SHADER_GEOMETRY)
1633 shader1_key.as_es = 1;
1634 else
1635 assert(0);
1636
1637 ok = si_check_missing_main_part(sscreen,
1638 previous_stage_sel,
1639 compiler_state, &shader1_key);
1640 } else {
1641 ok = si_check_missing_main_part(sscreen, sel,
1642 compiler_state, key);
1643 }
1644 if (!ok) {
1645 FREE(shader);
1646 mtx_unlock(&sel->mutex);
1647 return -ENOMEM; /* skip the draw call */
1648 }
1649 }
1650
1651 /* Keep the reference to the 1st shader of merged shaders, so that
1652 * Gallium can't destroy it before we destroy the 2nd shader.
1653 *
1654 * Set sctx = NULL, because it's unused if we're not releasing
1655 * the shader, and we don't have any sctx here.
1656 */
1657 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
1658 previous_stage_sel);
1659
1660 /* Monolithic-only shaders don't make a distinction between optimized
1661 * and unoptimized. */
1662 shader->is_monolithic =
1663 is_pure_monolithic ||
1664 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1665
1666 shader->is_optimized =
1667 !is_pure_monolithic &&
1668 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1669 if (shader->is_optimized)
1670 util_queue_fence_init(&shader->optimized_ready);
1671
1672 if (!sel->last_variant) {
1673 sel->first_variant = shader;
1674 sel->last_variant = shader;
1675 } else {
1676 sel->last_variant->next_variant = shader;
1677 sel->last_variant = shader;
1678 }
1679
1680 /* If it's an optimized shader, compile it asynchronously. */
1681 if (shader->is_optimized &&
1682 !is_pure_monolithic &&
1683 thread_index < 0) {
1684 /* Compile it asynchronously. */
1685 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
1686 shader, &shader->optimized_ready,
1687 si_build_shader_variant, NULL);
1688
1689 /* Use the default (unoptimized) shader for now. */
1690 memset(&key->opt, 0, sizeof(key->opt));
1691 mtx_unlock(&sel->mutex);
1692 goto again;
1693 }
1694
1695 assert(!shader->is_optimized);
1696 si_build_shader_variant(shader, thread_index);
1697
1698 if (!shader->compilation_failed)
1699 state->current = shader;
1700
1701 mtx_unlock(&sel->mutex);
1702 return shader->compilation_failed ? -1 : 0;
1703 }
1704
1705 static int si_shader_select(struct pipe_context *ctx,
1706 struct si_shader_ctx_state *state,
1707 struct si_compiler_ctx_state *compiler_state)
1708 {
1709 struct si_context *sctx = (struct si_context *)ctx;
1710 struct si_shader_key key;
1711
1712 si_shader_selector_key(ctx, state->cso, &key);
1713 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1714 &key, -1);
1715 }
1716
1717 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1718 struct si_shader_key *key)
1719 {
1720 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1721
1722 switch (info->processor) {
1723 case PIPE_SHADER_VERTEX:
1724 switch (next_shader) {
1725 case PIPE_SHADER_GEOMETRY:
1726 key->as_es = 1;
1727 break;
1728 case PIPE_SHADER_TESS_CTRL:
1729 case PIPE_SHADER_TESS_EVAL:
1730 key->as_ls = 1;
1731 break;
1732 default:
1733 /* If POSITION isn't written, it can't be a HW VS.
1734 * Assume that it's a HW LS. (the next shader is TCS)
1735 * This heuristic is needed for separate shader objects.
1736 */
1737 if (!info->writes_position)
1738 key->as_ls = 1;
1739 }
1740 break;
1741
1742 case PIPE_SHADER_TESS_EVAL:
1743 if (next_shader == PIPE_SHADER_GEOMETRY ||
1744 !info->writes_position)
1745 key->as_es = 1;
1746 break;
1747 }
1748 }
1749
1750 /**
1751 * Compile the main shader part or the monolithic shader as part of
1752 * si_shader_selector initialization. Since it can be done asynchronously,
1753 * there is no way to report compile failures to applications.
1754 */
1755 void si_init_shader_selector_async(void *job, int thread_index)
1756 {
1757 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1758 struct si_screen *sscreen = sel->screen;
1759 LLVMTargetMachineRef tm;
1760 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
1761 unsigned i;
1762
1763 if (thread_index >= 0) {
1764 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1765 tm = sscreen->tm[thread_index];
1766 if (!debug->async)
1767 debug = NULL;
1768 } else {
1769 tm = sel->compiler_ctx_state.tm;
1770 }
1771
1772 /* Compile the main shader part for use with a prolog and/or epilog.
1773 * If this fails, the driver will try to compile a monolithic shader
1774 * on demand.
1775 */
1776 if (!sscreen->use_monolithic_shaders) {
1777 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1778 void *tgsi_binary;
1779
1780 if (!shader) {
1781 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1782 return;
1783 }
1784
1785 shader->selector = sel;
1786 si_parse_next_shader_property(&sel->info, &shader->key);
1787
1788 tgsi_binary = si_get_tgsi_binary(sel);
1789
1790 /* Try to load the shader from the shader cache. */
1791 mtx_lock(&sscreen->shader_cache_mutex);
1792
1793 if (tgsi_binary &&
1794 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1795 mtx_unlock(&sscreen->shader_cache_mutex);
1796 } else {
1797 mtx_unlock(&sscreen->shader_cache_mutex);
1798
1799 /* Compile the shader if it hasn't been loaded from the cache. */
1800 if (si_compile_tgsi_shader(sscreen, tm, shader, false,
1801 debug) != 0) {
1802 FREE(shader);
1803 FREE(tgsi_binary);
1804 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1805 return;
1806 }
1807
1808 if (tgsi_binary) {
1809 mtx_lock(&sscreen->shader_cache_mutex);
1810 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary, shader, true))
1811 FREE(tgsi_binary);
1812 mtx_unlock(&sscreen->shader_cache_mutex);
1813 }
1814 }
1815
1816 *si_get_main_shader_part(sel, &shader->key) = shader;
1817
1818 /* Unset "outputs_written" flags for outputs converted to
1819 * DEFAULT_VAL, so that later inter-shader optimizations don't
1820 * try to eliminate outputs that don't exist in the final
1821 * shader.
1822 *
1823 * This is only done if non-monolithic shaders are enabled.
1824 */
1825 if ((sel->type == PIPE_SHADER_VERTEX ||
1826 sel->type == PIPE_SHADER_TESS_EVAL) &&
1827 !shader->key.as_ls &&
1828 !shader->key.as_es) {
1829 unsigned i;
1830
1831 for (i = 0; i < sel->info.num_outputs; i++) {
1832 unsigned offset = shader->info.vs_output_param_offset[i];
1833
1834 if (offset <= AC_EXP_PARAM_OFFSET_31)
1835 continue;
1836
1837 unsigned name = sel->info.output_semantic_name[i];
1838 unsigned index = sel->info.output_semantic_index[i];
1839 unsigned id;
1840
1841 switch (name) {
1842 case TGSI_SEMANTIC_GENERIC:
1843 /* don't process indices the function can't handle */
1844 if (index >= SI_MAX_IO_GENERIC)
1845 break;
1846 /* fall through */
1847 default:
1848 id = si_shader_io_get_unique_index(name, index);
1849 sel->outputs_written &= ~(1ull << id);
1850 break;
1851 case TGSI_SEMANTIC_POSITION: /* ignore these */
1852 case TGSI_SEMANTIC_PSIZE:
1853 case TGSI_SEMANTIC_CLIPVERTEX:
1854 case TGSI_SEMANTIC_EDGEFLAG:
1855 break;
1856 }
1857 }
1858 }
1859 }
1860
1861 /* Pre-compilation. */
1862 if (sscreen->b.debug_flags & DBG_PRECOMPILE) {
1863 struct si_shader_ctx_state state = {sel};
1864 struct si_shader_key key;
1865
1866 memset(&key, 0, sizeof(key));
1867 si_parse_next_shader_property(&sel->info, &key);
1868
1869 /* Set reasonable defaults, so that the shader key doesn't
1870 * cause any code to be eliminated.
1871 */
1872 switch (sel->type) {
1873 case PIPE_SHADER_TESS_CTRL:
1874 key.part.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1875 break;
1876 case PIPE_SHADER_FRAGMENT:
1877 key.part.ps.prolog.bc_optimize_for_persp =
1878 sel->info.uses_persp_center &&
1879 sel->info.uses_persp_centroid;
1880 key.part.ps.prolog.bc_optimize_for_linear =
1881 sel->info.uses_linear_center &&
1882 sel->info.uses_linear_centroid;
1883 key.part.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1884 for (i = 0; i < 8; i++)
1885 if (sel->info.colors_written & (1 << i))
1886 key.part.ps.epilog.spi_shader_col_format |=
1887 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1888 break;
1889 }
1890
1891 if (si_shader_select_with_key(sscreen, &state,
1892 &sel->compiler_ctx_state, &key,
1893 thread_index))
1894 fprintf(stderr, "radeonsi: can't create a monolithic shader\n");
1895 }
1896
1897 /* The GS copy shader is always pre-compiled. */
1898 if (sel->type == PIPE_SHADER_GEOMETRY) {
1899 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
1900 if (!sel->gs_copy_shader) {
1901 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
1902 return;
1903 }
1904
1905 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
1906 }
1907 }
1908
1909 /* Return descriptor slot usage masks from the given shader info. */
1910 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
1911 uint32_t *const_and_shader_buffers,
1912 uint64_t *samplers_and_images)
1913 {
1914 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
1915
1916 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
1917 num_constbufs = util_last_bit(info->const_buffers_declared);
1918 /* two 8-byte images share one 16-byte slot */
1919 num_images = align(util_last_bit(info->images_declared), 2);
1920 num_samplers = util_last_bit(info->samplers_declared);
1921
1922 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
1923 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
1924 *const_and_shader_buffers =
1925 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
1926
1927 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
1928 start = si_get_image_slot(num_images - 1) / 2;
1929 *samplers_and_images =
1930 u_bit_consecutive64(start, num_images / 2 + num_samplers);
1931 }
1932
1933 static void *si_create_shader_selector(struct pipe_context *ctx,
1934 const struct pipe_shader_state *state)
1935 {
1936 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1937 struct si_context *sctx = (struct si_context*)ctx;
1938 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
1939 int i;
1940
1941 if (!sel)
1942 return NULL;
1943
1944 pipe_reference_init(&sel->reference, 1);
1945 sel->screen = sscreen;
1946 sel->compiler_ctx_state.tm = sctx->tm;
1947 sel->compiler_ctx_state.debug = sctx->b.debug;
1948 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
1949 sel->tokens = tgsi_dup_tokens(state->tokens);
1950 if (!sel->tokens) {
1951 FREE(sel);
1952 return NULL;
1953 }
1954
1955 sel->so = state->stream_output;
1956 tgsi_scan_shader(state->tokens, &sel->info);
1957 sel->type = sel->info.processor;
1958 p_atomic_inc(&sscreen->b.num_shaders_created);
1959 si_get_active_slot_masks(&sel->info,
1960 &sel->active_const_and_shader_buffers,
1961 &sel->active_samplers_and_images);
1962
1963 /* Record which streamout buffers are enabled. */
1964 for (i = 0; i < sel->so.num_outputs; i++) {
1965 sel->enabled_streamout_buffer_mask |=
1966 (1 << sel->so.output[i].output_buffer) <<
1967 (sel->so.output[i].stream * 4);
1968 }
1969
1970 /* The prolog is a no-op if there are no inputs. */
1971 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
1972 sel->info.num_inputs;
1973
1974 /* Set which opcode uses which (i,j) pair. */
1975 if (sel->info.uses_persp_opcode_interp_centroid)
1976 sel->info.uses_persp_centroid = true;
1977
1978 if (sel->info.uses_linear_opcode_interp_centroid)
1979 sel->info.uses_linear_centroid = true;
1980
1981 if (sel->info.uses_persp_opcode_interp_offset ||
1982 sel->info.uses_persp_opcode_interp_sample)
1983 sel->info.uses_persp_center = true;
1984
1985 if (sel->info.uses_linear_opcode_interp_offset ||
1986 sel->info.uses_linear_opcode_interp_sample)
1987 sel->info.uses_linear_center = true;
1988
1989 switch (sel->type) {
1990 case PIPE_SHADER_GEOMETRY:
1991 sel->gs_output_prim =
1992 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
1993 sel->gs_max_out_vertices =
1994 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
1995 sel->gs_num_invocations =
1996 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
1997 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
1998 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
1999 sel->gs_max_out_vertices;
2000
2001 sel->max_gs_stream = 0;
2002 for (i = 0; i < sel->so.num_outputs; i++)
2003 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2004 sel->so.output[i].stream);
2005
2006 sel->gs_input_verts_per_prim =
2007 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2008 break;
2009
2010 case PIPE_SHADER_TESS_CTRL:
2011 /* Always reserve space for these. */
2012 sel->patch_outputs_written |=
2013 (1llu << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2014 (1llu << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2015 /* fall through */
2016 case PIPE_SHADER_VERTEX:
2017 case PIPE_SHADER_TESS_EVAL:
2018 for (i = 0; i < sel->info.num_outputs; i++) {
2019 unsigned name = sel->info.output_semantic_name[i];
2020 unsigned index = sel->info.output_semantic_index[i];
2021
2022 switch (name) {
2023 case TGSI_SEMANTIC_TESSINNER:
2024 case TGSI_SEMANTIC_TESSOUTER:
2025 case TGSI_SEMANTIC_PATCH:
2026 sel->patch_outputs_written |=
2027 1llu << si_shader_io_get_unique_index_patch(name, index);
2028 break;
2029
2030 case TGSI_SEMANTIC_GENERIC:
2031 /* don't process indices the function can't handle */
2032 if (index >= SI_MAX_IO_GENERIC)
2033 break;
2034 /* fall through */
2035 default:
2036 sel->outputs_written |=
2037 1llu << si_shader_io_get_unique_index(name, index);
2038 break;
2039 case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
2040 case TGSI_SEMANTIC_EDGEFLAG:
2041 break;
2042 }
2043 }
2044 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2045
2046 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2047 * conflicts, i.e. each vertex will start at a different bank.
2048 */
2049 if (sctx->b.chip_class >= GFX9)
2050 sel->esgs_itemsize += 4;
2051 break;
2052
2053 case PIPE_SHADER_FRAGMENT:
2054 for (i = 0; i < sel->info.num_inputs; i++) {
2055 unsigned name = sel->info.input_semantic_name[i];
2056 unsigned index = sel->info.input_semantic_index[i];
2057
2058 switch (name) {
2059 case TGSI_SEMANTIC_GENERIC:
2060 /* don't process indices the function can't handle */
2061 if (index >= SI_MAX_IO_GENERIC)
2062 break;
2063 /* fall through */
2064 default:
2065 sel->inputs_read |=
2066 1llu << si_shader_io_get_unique_index(name, index);
2067 break;
2068 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2069 break;
2070 }
2071 }
2072
2073 for (i = 0; i < 8; i++)
2074 if (sel->info.colors_written & (1 << i))
2075 sel->colors_written_4bit |= 0xf << (4 * i);
2076
2077 for (i = 0; i < sel->info.num_inputs; i++) {
2078 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2079 int index = sel->info.input_semantic_index[i];
2080 sel->color_attr_index[index] = i;
2081 }
2082 }
2083 break;
2084 }
2085
2086 /* DB_SHADER_CONTROL */
2087 sel->db_shader_control =
2088 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2089 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2090 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2091 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2092
2093 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2094 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2095 sel->db_shader_control |=
2096 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2097 break;
2098 case TGSI_FS_DEPTH_LAYOUT_LESS:
2099 sel->db_shader_control |=
2100 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2101 break;
2102 }
2103
2104 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2105 *
2106 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2107 * --|-----------|------------|------------|--------------------|-------------------|-------------
2108 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2109 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2110 * 2 | false | true | n/a | LateZ | 1 | 0
2111 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2112 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2113 *
2114 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2115 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2116 *
2117 * Don't use ReZ without profiling !!!
2118 *
2119 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2120 * shaders.
2121 */
2122 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2123 /* Cases 3, 4. */
2124 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2125 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2126 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2127 } else if (sel->info.writes_memory) {
2128 /* Case 2. */
2129 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2130 S_02880C_EXEC_ON_HIER_FAIL(1);
2131 } else {
2132 /* Case 1. */
2133 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2134 }
2135
2136 (void) mtx_init(&sel->mutex, mtx_plain);
2137 util_queue_fence_init(&sel->ready);
2138
2139 if ((sctx->b.debug.debug_message && !sctx->b.debug.async) ||
2140 sctx->is_debug ||
2141 r600_can_dump_shader(&sscreen->b, sel->info.processor))
2142 si_init_shader_selector_async(sel, -1);
2143 else
2144 util_queue_add_job(&sscreen->shader_compiler_queue, sel,
2145 &sel->ready, si_init_shader_selector_async,
2146 NULL);
2147
2148 return sel;
2149 }
2150
2151 static void si_update_streamout_state(struct si_context *sctx)
2152 {
2153 struct si_shader_selector *shader_with_so =
2154 sctx->gs_shader.cso ? sctx->gs_shader.cso :
2155 sctx->tes_shader.cso ? sctx->tes_shader.cso :
2156 sctx->vs_shader.cso;
2157 if (!shader_with_so)
2158 return;
2159
2160 sctx->b.streamout.enabled_stream_buffers_mask =
2161 shader_with_so->enabled_streamout_buffer_mask;
2162 sctx->b.streamout.stride_in_dw = shader_with_so->so.stride;
2163 }
2164
2165 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2166 {
2167 struct si_context *sctx = (struct si_context *)ctx;
2168 struct si_shader_selector *sel = state;
2169
2170 if (sctx->vs_shader.cso == sel)
2171 return;
2172
2173 sctx->vs_shader.cso = sel;
2174 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2175 sctx->do_update_shaders = true;
2176 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2177 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
2178 si_set_active_descriptors_for_shader(sctx, sel);
2179 si_update_streamout_state(sctx);
2180 }
2181
2182 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2183 {
2184 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2185 (sctx->tes_shader.cso &&
2186 sctx->tes_shader.cso->info.uses_primid) ||
2187 (sctx->tcs_shader.cso &&
2188 sctx->tcs_shader.cso->info.uses_primid) ||
2189 (sctx->gs_shader.cso &&
2190 sctx->gs_shader.cso->info.uses_primid) ||
2191 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2192 sctx->ps_shader.cso->info.uses_primid);
2193 }
2194
2195 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2196 {
2197 struct si_context *sctx = (struct si_context *)ctx;
2198 struct si_shader_selector *sel = state;
2199 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2200
2201 if (sctx->gs_shader.cso == sel)
2202 return;
2203
2204 sctx->gs_shader.cso = sel;
2205 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2206 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2207 sctx->do_update_shaders = true;
2208 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2209 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2210
2211 if (enable_changed) {
2212 si_shader_change_notify(sctx);
2213 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2214 si_update_tess_uses_prim_id(sctx);
2215 }
2216 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
2217 si_set_active_descriptors_for_shader(sctx, sel);
2218 si_update_streamout_state(sctx);
2219 }
2220
2221 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2222 {
2223 struct si_context *sctx = (struct si_context *)ctx;
2224 struct si_shader_selector *sel = state;
2225 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2226
2227 if (sctx->tcs_shader.cso == sel)
2228 return;
2229
2230 sctx->tcs_shader.cso = sel;
2231 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2232 si_update_tess_uses_prim_id(sctx);
2233 sctx->do_update_shaders = true;
2234
2235 if (enable_changed)
2236 sctx->last_tcs = NULL; /* invalidate derived tess state */
2237
2238 si_set_active_descriptors_for_shader(sctx, sel);
2239 }
2240
2241 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2242 {
2243 struct si_context *sctx = (struct si_context *)ctx;
2244 struct si_shader_selector *sel = state;
2245 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2246
2247 if (sctx->tes_shader.cso == sel)
2248 return;
2249
2250 sctx->tes_shader.cso = sel;
2251 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2252 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2253 si_update_tess_uses_prim_id(sctx);
2254 sctx->do_update_shaders = true;
2255 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2256 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2257
2258 if (enable_changed) {
2259 si_shader_change_notify(sctx);
2260 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2261 }
2262 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
2263 si_set_active_descriptors_for_shader(sctx, sel);
2264 si_update_streamout_state(sctx);
2265 }
2266
2267 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2268 {
2269 struct si_context *sctx = (struct si_context *)ctx;
2270 struct si_shader_selector *sel = state;
2271
2272 /* skip if supplied shader is one already in use */
2273 if (sctx->ps_shader.cso == sel)
2274 return;
2275
2276 sctx->ps_shader.cso = sel;
2277 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2278 sctx->do_update_shaders = true;
2279 if (sel && sctx->ia_multi_vgt_param_key.u.uses_tess)
2280 si_update_tess_uses_prim_id(sctx);
2281 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2282 si_set_active_descriptors_for_shader(sctx, sel);
2283 }
2284
2285 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2286 {
2287 if (shader->is_optimized) {
2288 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
2289 &shader->optimized_ready);
2290 util_queue_fence_destroy(&shader->optimized_ready);
2291 }
2292
2293 if (shader->pm4) {
2294 switch (shader->selector->type) {
2295 case PIPE_SHADER_VERTEX:
2296 if (shader->key.as_ls) {
2297 assert(sctx->b.chip_class <= VI);
2298 si_pm4_delete_state(sctx, ls, shader->pm4);
2299 } else if (shader->key.as_es) {
2300 assert(sctx->b.chip_class <= VI);
2301 si_pm4_delete_state(sctx, es, shader->pm4);
2302 } else {
2303 si_pm4_delete_state(sctx, vs, shader->pm4);
2304 }
2305 break;
2306 case PIPE_SHADER_TESS_CTRL:
2307 si_pm4_delete_state(sctx, hs, shader->pm4);
2308 break;
2309 case PIPE_SHADER_TESS_EVAL:
2310 if (shader->key.as_es) {
2311 assert(sctx->b.chip_class <= VI);
2312 si_pm4_delete_state(sctx, es, shader->pm4);
2313 } else {
2314 si_pm4_delete_state(sctx, vs, shader->pm4);
2315 }
2316 break;
2317 case PIPE_SHADER_GEOMETRY:
2318 if (shader->is_gs_copy_shader)
2319 si_pm4_delete_state(sctx, vs, shader->pm4);
2320 else
2321 si_pm4_delete_state(sctx, gs, shader->pm4);
2322 break;
2323 case PIPE_SHADER_FRAGMENT:
2324 si_pm4_delete_state(sctx, ps, shader->pm4);
2325 break;
2326 }
2327 }
2328
2329 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2330 si_shader_destroy(shader);
2331 free(shader);
2332 }
2333
2334 static void si_destroy_shader_selector(struct si_context *sctx,
2335 struct si_shader_selector *sel)
2336 {
2337 struct si_shader *p = sel->first_variant, *c;
2338 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2339 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2340 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2341 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2342 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2343 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2344 };
2345
2346 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
2347
2348 if (current_shader[sel->type]->cso == sel) {
2349 current_shader[sel->type]->cso = NULL;
2350 current_shader[sel->type]->current = NULL;
2351 }
2352
2353 while (p) {
2354 c = p->next_variant;
2355 si_delete_shader(sctx, p);
2356 p = c;
2357 }
2358
2359 if (sel->main_shader_part)
2360 si_delete_shader(sctx, sel->main_shader_part);
2361 if (sel->main_shader_part_ls)
2362 si_delete_shader(sctx, sel->main_shader_part_ls);
2363 if (sel->main_shader_part_es)
2364 si_delete_shader(sctx, sel->main_shader_part_es);
2365 if (sel->gs_copy_shader)
2366 si_delete_shader(sctx, sel->gs_copy_shader);
2367
2368 util_queue_fence_destroy(&sel->ready);
2369 mtx_destroy(&sel->mutex);
2370 free(sel->tokens);
2371 free(sel);
2372 }
2373
2374 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
2375 {
2376 struct si_context *sctx = (struct si_context *)ctx;
2377 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2378
2379 si_shader_selector_reference(sctx, &sel, NULL);
2380 }
2381
2382 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2383 struct si_shader *vs, unsigned name,
2384 unsigned index, unsigned interpolate)
2385 {
2386 struct tgsi_shader_info *vsinfo = &vs->selector->info;
2387 unsigned j, offset, ps_input_cntl = 0;
2388
2389 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2390 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
2391 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2392
2393 if (name == TGSI_SEMANTIC_PCOORD ||
2394 (name == TGSI_SEMANTIC_TEXCOORD &&
2395 sctx->sprite_coord_enable & (1 << index))) {
2396 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2397 }
2398
2399 for (j = 0; j < vsinfo->num_outputs; j++) {
2400 if (name == vsinfo->output_semantic_name[j] &&
2401 index == vsinfo->output_semantic_index[j]) {
2402 offset = vs->info.vs_output_param_offset[j];
2403
2404 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2405 /* The input is loaded from parameter memory. */
2406 ps_input_cntl |= S_028644_OFFSET(offset);
2407 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2408 if (offset == AC_EXP_PARAM_UNDEFINED) {
2409 /* This can happen with depth-only rendering. */
2410 offset = 0;
2411 } else {
2412 /* The input is a DEFAULT_VAL constant. */
2413 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2414 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2415 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2416 }
2417
2418 ps_input_cntl = S_028644_OFFSET(0x20) |
2419 S_028644_DEFAULT_VAL(offset);
2420 }
2421 break;
2422 }
2423 }
2424
2425 if (name == TGSI_SEMANTIC_PRIMID)
2426 /* PrimID is written after the last output. */
2427 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2428 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2429 /* No corresponding output found, load defaults into input.
2430 * Don't set any other bits.
2431 * (FLAT_SHADE=1 completely changes behavior) */
2432 ps_input_cntl = S_028644_OFFSET(0x20);
2433 /* D3D 9 behaviour. GL is undefined */
2434 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2435 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2436 }
2437 return ps_input_cntl;
2438 }
2439
2440 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
2441 {
2442 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2443 struct si_shader *ps = sctx->ps_shader.current;
2444 struct si_shader *vs = si_get_vs_state(sctx);
2445 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2446 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2447
2448 if (!ps || !ps->selector->info.num_inputs)
2449 return;
2450
2451 num_interp = si_get_ps_num_interp(ps);
2452 assert(num_interp > 0);
2453 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
2454
2455 for (i = 0; i < psinfo->num_inputs; i++) {
2456 unsigned name = psinfo->input_semantic_name[i];
2457 unsigned index = psinfo->input_semantic_index[i];
2458 unsigned interpolate = psinfo->input_interpolate[i];
2459
2460 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
2461 interpolate));
2462 num_written++;
2463
2464 if (name == TGSI_SEMANTIC_COLOR) {
2465 assert(index < ARRAY_SIZE(bcol_interp));
2466 bcol_interp[index] = interpolate;
2467 }
2468 }
2469
2470 if (ps->key.part.ps.prolog.color_two_side) {
2471 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2472
2473 for (i = 0; i < 2; i++) {
2474 if (!(psinfo->colors_read & (0xf << (i * 4))))
2475 continue;
2476
2477 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
2478 i, bcol_interp[i]));
2479 num_written++;
2480 }
2481 }
2482 assert(num_interp == num_written);
2483 }
2484
2485 /**
2486 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2487 */
2488 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2489 {
2490 if (sctx->init_config_has_vgt_flush)
2491 return;
2492
2493 /* Done by Vulkan before VGT_FLUSH. */
2494 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2495 si_pm4_cmd_add(sctx->init_config,
2496 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2497 si_pm4_cmd_end(sctx->init_config, false);
2498
2499 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2500 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2501 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2502 si_pm4_cmd_end(sctx->init_config, false);
2503 sctx->init_config_has_vgt_flush = true;
2504 }
2505
2506 /* Initialize state related to ESGS / GSVS ring buffers */
2507 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2508 {
2509 struct si_shader_selector *es =
2510 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2511 struct si_shader_selector *gs = sctx->gs_shader.cso;
2512 struct si_pm4_state *pm4;
2513
2514 /* Chip constants. */
2515 unsigned num_se = sctx->screen->b.info.max_se;
2516 unsigned wave_size = 64;
2517 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2518 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2519 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2520 */
2521 unsigned gs_vertex_reuse = (sctx->b.chip_class >= VI ? 32 : 16) * num_se;
2522 unsigned alignment = 256 * num_se;
2523 /* The maximum size is 63.999 MB per SE. */
2524 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2525
2526 /* Calculate the minimum size. */
2527 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2528 wave_size, alignment);
2529
2530 /* These are recommended sizes, not minimum sizes. */
2531 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2532 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2533 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2534 gs->max_gsvs_emit_size;
2535
2536 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2537 esgs_ring_size = align(esgs_ring_size, alignment);
2538 gsvs_ring_size = align(gsvs_ring_size, alignment);
2539
2540 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2541 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2542
2543 /* Some rings don't have to be allocated if shaders don't use them.
2544 * (e.g. no varyings between ES and GS or GS and VS)
2545 *
2546 * GFX9 doesn't have the ESGS ring.
2547 */
2548 bool update_esgs = sctx->b.chip_class <= VI &&
2549 esgs_ring_size &&
2550 (!sctx->esgs_ring ||
2551 sctx->esgs_ring->width0 < esgs_ring_size);
2552 bool update_gsvs = gsvs_ring_size &&
2553 (!sctx->gsvs_ring ||
2554 sctx->gsvs_ring->width0 < gsvs_ring_size);
2555
2556 if (!update_esgs && !update_gsvs)
2557 return true;
2558
2559 if (update_esgs) {
2560 pipe_resource_reference(&sctx->esgs_ring, NULL);
2561 sctx->esgs_ring =
2562 r600_aligned_buffer_create(sctx->b.b.screen,
2563 R600_RESOURCE_FLAG_UNMAPPABLE,
2564 PIPE_USAGE_DEFAULT,
2565 esgs_ring_size, alignment);
2566 if (!sctx->esgs_ring)
2567 return false;
2568 }
2569
2570 if (update_gsvs) {
2571 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2572 sctx->gsvs_ring =
2573 r600_aligned_buffer_create(sctx->b.b.screen,
2574 R600_RESOURCE_FLAG_UNMAPPABLE,
2575 PIPE_USAGE_DEFAULT,
2576 gsvs_ring_size, alignment);
2577 if (!sctx->gsvs_ring)
2578 return false;
2579 }
2580
2581 /* Create the "init_config_gs_rings" state. */
2582 pm4 = CALLOC_STRUCT(si_pm4_state);
2583 if (!pm4)
2584 return false;
2585
2586 if (sctx->b.chip_class >= CIK) {
2587 if (sctx->esgs_ring) {
2588 assert(sctx->b.chip_class <= VI);
2589 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2590 sctx->esgs_ring->width0 / 256);
2591 }
2592 if (sctx->gsvs_ring)
2593 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2594 sctx->gsvs_ring->width0 / 256);
2595 } else {
2596 if (sctx->esgs_ring)
2597 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2598 sctx->esgs_ring->width0 / 256);
2599 if (sctx->gsvs_ring)
2600 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2601 sctx->gsvs_ring->width0 / 256);
2602 }
2603
2604 /* Set the state. */
2605 if (sctx->init_config_gs_rings)
2606 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2607 sctx->init_config_gs_rings = pm4;
2608
2609 if (!sctx->init_config_has_vgt_flush) {
2610 si_init_config_add_vgt_flush(sctx);
2611 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2612 }
2613
2614 /* Flush the context to re-emit both init_config states. */
2615 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2616 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2617
2618 /* Set ring bindings. */
2619 if (sctx->esgs_ring) {
2620 assert(sctx->b.chip_class <= VI);
2621 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
2622 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2623 true, true, 4, 64, 0);
2624 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
2625 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2626 false, false, 0, 0, 0);
2627 }
2628 if (sctx->gsvs_ring) {
2629 si_set_ring_buffer(&sctx->b.b, SI_RING_GSVS,
2630 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2631 false, false, 0, 0, 0);
2632 }
2633
2634 return true;
2635 }
2636
2637 static void si_shader_lock(struct si_shader *shader)
2638 {
2639 mtx_lock(&shader->selector->mutex);
2640 if (shader->previous_stage_sel) {
2641 assert(shader->previous_stage_sel != shader->selector);
2642 mtx_lock(&shader->previous_stage_sel->mutex);
2643 }
2644 }
2645
2646 static void si_shader_unlock(struct si_shader *shader)
2647 {
2648 if (shader->previous_stage_sel)
2649 mtx_unlock(&shader->previous_stage_sel->mutex);
2650 mtx_unlock(&shader->selector->mutex);
2651 }
2652
2653 /**
2654 * @returns 1 if \p sel has been updated to use a new scratch buffer
2655 * 0 if not
2656 * < 0 if there was a failure
2657 */
2658 static int si_update_scratch_buffer(struct si_context *sctx,
2659 struct si_shader *shader)
2660 {
2661 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2662 int r;
2663
2664 if (!shader)
2665 return 0;
2666
2667 /* This shader doesn't need a scratch buffer */
2668 if (shader->config.scratch_bytes_per_wave == 0)
2669 return 0;
2670
2671 /* Prevent race conditions when updating:
2672 * - si_shader::scratch_bo
2673 * - si_shader::binary::code
2674 * - si_shader::previous_stage::binary::code.
2675 */
2676 si_shader_lock(shader);
2677
2678 /* This shader is already configured to use the current
2679 * scratch buffer. */
2680 if (shader->scratch_bo == sctx->scratch_buffer) {
2681 si_shader_unlock(shader);
2682 return 0;
2683 }
2684
2685 assert(sctx->scratch_buffer);
2686
2687 if (shader->previous_stage)
2688 si_shader_apply_scratch_relocs(shader->previous_stage, scratch_va);
2689
2690 si_shader_apply_scratch_relocs(shader, scratch_va);
2691
2692 /* Replace the shader bo with a new bo that has the relocs applied. */
2693 r = si_shader_binary_upload(sctx->screen, shader);
2694 if (r) {
2695 si_shader_unlock(shader);
2696 return r;
2697 }
2698
2699 /* Update the shader state to use the new shader bo. */
2700 si_shader_init_pm4_state(sctx->screen, shader);
2701
2702 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2703
2704 si_shader_unlock(shader);
2705 return 1;
2706 }
2707
2708 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2709 {
2710 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2711 }
2712
2713 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2714 {
2715 return shader ? shader->config.scratch_bytes_per_wave : 0;
2716 }
2717
2718 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
2719 {
2720 if (!sctx->tes_shader.cso)
2721 return NULL; /* tessellation disabled */
2722
2723 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
2724 sctx->fixed_func_tcs_shader.current;
2725 }
2726
2727 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2728 {
2729 unsigned bytes = 0;
2730
2731 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2732 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2733 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2734 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2735
2736 if (sctx->tes_shader.cso) {
2737 struct si_shader *tcs = si_get_tcs_current(sctx);
2738
2739 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
2740 }
2741 return bytes;
2742 }
2743
2744 static bool si_update_scratch_relocs(struct si_context *sctx)
2745 {
2746 struct si_shader *tcs = si_get_tcs_current(sctx);
2747 int r;
2748
2749 /* Update the shaders, so that they are using the latest scratch.
2750 * The scratch buffer may have been changed since these shaders were
2751 * last used, so we still need to try to update them, even if they
2752 * require scratch buffers smaller than the current size.
2753 */
2754 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2755 if (r < 0)
2756 return false;
2757 if (r == 1)
2758 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2759
2760 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2761 if (r < 0)
2762 return false;
2763 if (r == 1)
2764 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2765
2766 r = si_update_scratch_buffer(sctx, tcs);
2767 if (r < 0)
2768 return false;
2769 if (r == 1)
2770 si_pm4_bind_state(sctx, hs, tcs->pm4);
2771
2772 /* VS can be bound as LS, ES, or VS. */
2773 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2774 if (r < 0)
2775 return false;
2776 if (r == 1) {
2777 if (sctx->tes_shader.current)
2778 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2779 else if (sctx->gs_shader.current)
2780 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2781 else
2782 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2783 }
2784
2785 /* TES can be bound as ES or VS. */
2786 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2787 if (r < 0)
2788 return false;
2789 if (r == 1) {
2790 if (sctx->gs_shader.current)
2791 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2792 else
2793 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2794 }
2795
2796 return true;
2797 }
2798
2799 static bool si_update_spi_tmpring_size(struct si_context *sctx)
2800 {
2801 unsigned current_scratch_buffer_size =
2802 si_get_current_scratch_buffer_size(sctx);
2803 unsigned scratch_bytes_per_wave =
2804 si_get_max_scratch_bytes_per_wave(sctx);
2805 unsigned scratch_needed_size = scratch_bytes_per_wave *
2806 sctx->scratch_waves;
2807 unsigned spi_tmpring_size;
2808
2809 if (scratch_needed_size > 0) {
2810 if (scratch_needed_size > current_scratch_buffer_size) {
2811 /* Create a bigger scratch buffer */
2812 r600_resource_reference(&sctx->scratch_buffer, NULL);
2813
2814 sctx->scratch_buffer = (struct r600_resource*)
2815 r600_aligned_buffer_create(&sctx->screen->b.b,
2816 R600_RESOURCE_FLAG_UNMAPPABLE,
2817 PIPE_USAGE_DEFAULT,
2818 scratch_needed_size, 256);
2819 if (!sctx->scratch_buffer)
2820 return false;
2821
2822 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2823 r600_context_add_resource_size(&sctx->b.b,
2824 &sctx->scratch_buffer->b.b);
2825 }
2826
2827 if (!si_update_scratch_relocs(sctx))
2828 return false;
2829 }
2830
2831 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2832 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
2833 "scratch size should already be aligned correctly.");
2834
2835 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
2836 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
2837 if (spi_tmpring_size != sctx->spi_tmpring_size) {
2838 sctx->spi_tmpring_size = spi_tmpring_size;
2839 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2840 }
2841 return true;
2842 }
2843
2844 static void si_init_tess_factor_ring(struct si_context *sctx)
2845 {
2846 bool double_offchip_buffers = sctx->b.chip_class >= CIK &&
2847 sctx->b.family != CHIP_CARRIZO &&
2848 sctx->b.family != CHIP_STONEY;
2849 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2850 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
2851 sctx->screen->b.info.max_se;
2852 unsigned offchip_granularity;
2853
2854 switch (sctx->screen->tess_offchip_block_dw_size) {
2855 default:
2856 assert(0);
2857 /* fall through */
2858 case 8192:
2859 offchip_granularity = V_03093C_X_8K_DWORDS;
2860 break;
2861 case 4096:
2862 offchip_granularity = V_03093C_X_4K_DWORDS;
2863 break;
2864 }
2865
2866 switch (sctx->b.chip_class) {
2867 case SI:
2868 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2869 break;
2870 case CIK:
2871 case VI:
2872 case GFX9:
2873 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2874 break;
2875 default:
2876 assert(0);
2877 return;
2878 }
2879
2880 assert(!sctx->tf_ring);
2881 /* Use 64K alignment for both rings, so that we can pass the address
2882 * to shaders as one SGPR containing bits [16:47].
2883 */
2884 sctx->tf_ring = r600_aligned_buffer_create(sctx->b.b.screen,
2885 R600_RESOURCE_FLAG_UNMAPPABLE,
2886 PIPE_USAGE_DEFAULT,
2887 32768 * sctx->screen->b.info.max_se,
2888 64 * 1024);
2889 if (!sctx->tf_ring)
2890 return;
2891
2892 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
2893
2894 sctx->tess_offchip_ring =
2895 r600_aligned_buffer_create(sctx->b.b.screen,
2896 R600_RESOURCE_FLAG_UNMAPPABLE,
2897 PIPE_USAGE_DEFAULT,
2898 max_offchip_buffers *
2899 sctx->screen->tess_offchip_block_dw_size * 4,
2900 64 * 1024);
2901 if (!sctx->tess_offchip_ring)
2902 return;
2903
2904 si_init_config_add_vgt_flush(sctx);
2905
2906 uint64_t offchip_va = r600_resource(sctx->tess_offchip_ring)->gpu_address;
2907 uint64_t factor_va = r600_resource(sctx->tf_ring)->gpu_address;
2908 assert((offchip_va & 0xffff) == 0);
2909 assert((factor_va & 0xffff) == 0);
2910
2911 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_offchip_ring),
2912 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
2913 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tf_ring),
2914 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
2915
2916 /* Append these registers to the init config state. */
2917 if (sctx->b.chip_class >= CIK) {
2918 if (sctx->b.chip_class >= VI)
2919 --max_offchip_buffers;
2920
2921 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
2922 S_030938_SIZE(sctx->tf_ring->width0 / 4));
2923 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
2924 factor_va >> 8);
2925 if (sctx->b.chip_class >= GFX9)
2926 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
2927 factor_va >> 40);
2928 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
2929 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2930 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
2931 } else {
2932 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
2933 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
2934 S_008988_SIZE(sctx->tf_ring->width0 / 4));
2935 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
2936 factor_va >> 8);
2937 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2938 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
2939 }
2940
2941 if (sctx->b.chip_class >= GFX9) {
2942 si_pm4_set_reg(sctx->init_config,
2943 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
2944 GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
2945 offchip_va >> 16);
2946 si_pm4_set_reg(sctx->init_config,
2947 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
2948 GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
2949 factor_va >> 16);
2950 } else {
2951 si_pm4_set_reg(sctx->init_config,
2952 R_00B430_SPI_SHADER_USER_DATA_HS_0 +
2953 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
2954 offchip_va >> 16);
2955 si_pm4_set_reg(sctx->init_config,
2956 R_00B430_SPI_SHADER_USER_DATA_HS_0 +
2957 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
2958 factor_va >> 16);
2959 }
2960
2961 /* Flush the context to re-emit the init_config state.
2962 * This is done only once in a lifetime of a context.
2963 */
2964 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2965 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2966 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2967 }
2968
2969 /**
2970 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
2971 * VS passes its outputs to TES directly, so the fixed-function shader only
2972 * has to write TESSOUTER and TESSINNER.
2973 */
2974 static void si_generate_fixed_func_tcs(struct si_context *sctx)
2975 {
2976 struct ureg_src outer, inner;
2977 struct ureg_dst tessouter, tessinner;
2978 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
2979
2980 if (!ureg)
2981 return; /* if we get here, we're screwed */
2982
2983 assert(!sctx->fixed_func_tcs_shader.cso);
2984
2985 outer = ureg_DECL_system_value(ureg,
2986 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
2987 inner = ureg_DECL_system_value(ureg,
2988 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
2989
2990 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
2991 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
2992
2993 ureg_MOV(ureg, tessouter, outer);
2994 ureg_MOV(ureg, tessinner, inner);
2995 ureg_END(ureg);
2996
2997 sctx->fixed_func_tcs_shader.cso =
2998 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
2999 }
3000
3001 static void si_update_vgt_shader_config(struct si_context *sctx)
3002 {
3003 /* Calculate the index of the config.
3004 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3005 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
3006 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
3007
3008 if (!*pm4) {
3009 uint32_t stages = 0;
3010
3011 *pm4 = CALLOC_STRUCT(si_pm4_state);
3012
3013 if (sctx->tes_shader.cso) {
3014 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3015 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3016
3017 if (sctx->gs_shader.cso)
3018 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3019 S_028B54_GS_EN(1) |
3020 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3021 else
3022 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3023 } else if (sctx->gs_shader.cso) {
3024 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3025 S_028B54_GS_EN(1) |
3026 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3027 }
3028
3029 if (sctx->b.chip_class >= GFX9)
3030 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3031
3032 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3033 }
3034 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3035 }
3036
3037 bool si_update_shaders(struct si_context *sctx)
3038 {
3039 struct pipe_context *ctx = (struct pipe_context*)sctx;
3040 struct si_compiler_ctx_state compiler_state;
3041 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3042 struct si_shader *old_vs = si_get_vs_state(sctx);
3043 bool old_clip_disable = old_vs ? old_vs->key.opt.hw_vs.clip_disable : false;
3044 int r;
3045
3046 compiler_state.tm = sctx->tm;
3047 compiler_state.debug = sctx->b.debug;
3048 compiler_state.is_debug_context = sctx->is_debug;
3049
3050 /* Update stages before GS. */
3051 if (sctx->tes_shader.cso) {
3052 if (!sctx->tf_ring) {
3053 si_init_tess_factor_ring(sctx);
3054 if (!sctx->tf_ring)
3055 return false;
3056 }
3057
3058 /* VS as LS */
3059 if (sctx->b.chip_class <= VI) {
3060 r = si_shader_select(ctx, &sctx->vs_shader,
3061 &compiler_state);
3062 if (r)
3063 return false;
3064 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3065 }
3066
3067 if (sctx->tcs_shader.cso) {
3068 r = si_shader_select(ctx, &sctx->tcs_shader,
3069 &compiler_state);
3070 if (r)
3071 return false;
3072 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3073 } else {
3074 if (!sctx->fixed_func_tcs_shader.cso) {
3075 si_generate_fixed_func_tcs(sctx);
3076 if (!sctx->fixed_func_tcs_shader.cso)
3077 return false;
3078 }
3079
3080 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3081 &compiler_state);
3082 if (r)
3083 return false;
3084 si_pm4_bind_state(sctx, hs,
3085 sctx->fixed_func_tcs_shader.current->pm4);
3086 }
3087
3088 if (sctx->gs_shader.cso) {
3089 /* TES as ES */
3090 if (sctx->b.chip_class <= VI) {
3091 r = si_shader_select(ctx, &sctx->tes_shader,
3092 &compiler_state);
3093 if (r)
3094 return false;
3095 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3096 }
3097 } else {
3098 /* TES as VS */
3099 r = si_shader_select(ctx, &sctx->tes_shader,
3100 &compiler_state);
3101 if (r)
3102 return false;
3103 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3104 }
3105 } else if (sctx->gs_shader.cso) {
3106 if (sctx->b.chip_class <= VI) {
3107 /* VS as ES */
3108 r = si_shader_select(ctx, &sctx->vs_shader,
3109 &compiler_state);
3110 if (r)
3111 return false;
3112 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3113
3114 si_pm4_bind_state(sctx, ls, NULL);
3115 si_pm4_bind_state(sctx, hs, NULL);
3116 }
3117 } else {
3118 /* VS as VS */
3119 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
3120 if (r)
3121 return false;
3122 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3123 si_pm4_bind_state(sctx, ls, NULL);
3124 si_pm4_bind_state(sctx, hs, NULL);
3125 }
3126
3127 /* Update GS. */
3128 if (sctx->gs_shader.cso) {
3129 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
3130 if (r)
3131 return false;
3132 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3133 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3134
3135 if (!si_update_gs_ring_buffers(sctx))
3136 return false;
3137 } else {
3138 si_pm4_bind_state(sctx, gs, NULL);
3139 if (sctx->b.chip_class <= VI)
3140 si_pm4_bind_state(sctx, es, NULL);
3141 }
3142
3143 si_update_vgt_shader_config(sctx);
3144
3145 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.hw_vs.clip_disable)
3146 si_mark_atom_dirty(sctx, &sctx->clip_regs);
3147
3148 if (sctx->ps_shader.cso) {
3149 unsigned db_shader_control;
3150
3151 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
3152 if (r)
3153 return false;
3154 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3155
3156 db_shader_control =
3157 sctx->ps_shader.cso->db_shader_control |
3158 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3159
3160 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3161 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3162 sctx->flatshade != rs->flatshade) {
3163 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3164 sctx->flatshade = rs->flatshade;
3165 si_mark_atom_dirty(sctx, &sctx->spi_map);
3166 }
3167
3168 if (sctx->screen->b.rbplus_allowed && si_pm4_state_changed(sctx, ps))
3169 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
3170
3171 if (sctx->ps_db_shader_control != db_shader_control) {
3172 sctx->ps_db_shader_control = db_shader_control;
3173 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3174 }
3175
3176 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3177 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3178 si_mark_atom_dirty(sctx, &sctx->msaa_config);
3179
3180 if (sctx->b.chip_class == SI)
3181 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3182
3183 if (sctx->framebuffer.nr_samples <= 1)
3184 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
3185 }
3186 }
3187
3188 if (si_pm4_state_changed(sctx, ls) ||
3189 si_pm4_state_changed(sctx, hs) ||
3190 si_pm4_state_changed(sctx, es) ||
3191 si_pm4_state_changed(sctx, gs) ||
3192 si_pm4_state_changed(sctx, vs) ||
3193 si_pm4_state_changed(sctx, ps)) {
3194 if (!si_update_spi_tmpring_size(sctx))
3195 return false;
3196 }
3197
3198 if (sctx->b.chip_class >= CIK)
3199 si_mark_atom_dirty(sctx, &sctx->prefetch_L2);
3200
3201 sctx->do_update_shaders = false;
3202 return true;
3203 }
3204
3205 static void si_emit_scratch_state(struct si_context *sctx,
3206 struct r600_atom *atom)
3207 {
3208 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3209
3210 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3211 sctx->spi_tmpring_size);
3212
3213 if (sctx->scratch_buffer) {
3214 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
3215 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3216 RADEON_PRIO_SCRATCH_BUFFER);
3217 }
3218 }
3219
3220 void si_init_shader_functions(struct si_context *sctx)
3221 {
3222 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
3223 si_init_atom(sctx, &sctx->scratch_state, &sctx->atoms.s.scratch_state,
3224 si_emit_scratch_state);
3225
3226 sctx->b.b.create_vs_state = si_create_shader_selector;
3227 sctx->b.b.create_tcs_state = si_create_shader_selector;
3228 sctx->b.b.create_tes_state = si_create_shader_selector;
3229 sctx->b.b.create_gs_state = si_create_shader_selector;
3230 sctx->b.b.create_fs_state = si_create_shader_selector;
3231
3232 sctx->b.b.bind_vs_state = si_bind_vs_shader;
3233 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
3234 sctx->b.b.bind_tes_state = si_bind_tes_shader;
3235 sctx->b.b.bind_gs_state = si_bind_gs_shader;
3236 sctx->b.b.bind_fs_state = si_bind_ps_shader;
3237
3238 sctx->b.b.delete_vs_state = si_delete_shader_selector;
3239 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
3240 sctx->b.b.delete_tes_state = si_delete_shader_selector;
3241 sctx->b.b.delete_gs_state = si_delete_shader_selector;
3242 sctx->b.b.delete_fs_state = si_delete_shader_selector;
3243 }