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radeonsi: print shader cache stats with AMD_DEBUG=cache_stats
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR key for the shader cache.
45 */
46 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
47 unsigned char ir_sha1_cache_key[20])
48 {
49 struct blob blob = {};
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->nir_binary) {
54 ir_binary = sel->nir_binary;
55 ir_size = sel->nir_size;
56 } else {
57 assert(sel->nir);
58
59 blob_init(&blob);
60 nir_serialize(&blob, sel->nir, true);
61 ir_binary = blob.data;
62 ir_size = blob.size;
63 }
64
65 /* These settings affect the compilation, but they are not derived
66 * from the input shader IR.
67 */
68 unsigned shader_variant_flags = 0;
69
70 if (ngg)
71 shader_variant_flags |= 1 << 0;
72 if (sel->nir)
73 shader_variant_flags |= 1 << 1;
74 if (si_get_wave_size(sel->screen, sel->type, ngg, es) == 32)
75 shader_variant_flags |= 1 << 2;
76 if (sel->force_correct_derivs_after_kill)
77 shader_variant_flags |= 1 << 3;
78
79 struct mesa_sha1 ctx;
80 _mesa_sha1_init(&ctx);
81 _mesa_sha1_update(&ctx, &shader_variant_flags, 4);
82 _mesa_sha1_update(&ctx, ir_binary, ir_size);
83 if (sel->type == PIPE_SHADER_VERTEX ||
84 sel->type == PIPE_SHADER_TESS_EVAL ||
85 sel->type == PIPE_SHADER_GEOMETRY)
86 _mesa_sha1_update(&ctx, &sel->so, sizeof(sel->so));
87 _mesa_sha1_final(&ctx, ir_sha1_cache_key);
88
89 if (ir_binary == blob.data)
90 blob_finish(&blob);
91 }
92
93 /** Copy "data" to "ptr" and return the next dword following copied data. */
94 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
95 {
96 /* data may be NULL if size == 0 */
97 if (size)
98 memcpy(ptr, data, size);
99 ptr += DIV_ROUND_UP(size, 4);
100 return ptr;
101 }
102
103 /** Read data from "ptr". Return the next dword following the data. */
104 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
105 {
106 memcpy(data, ptr, size);
107 ptr += DIV_ROUND_UP(size, 4);
108 return ptr;
109 }
110
111 /**
112 * Write the size as uint followed by the data. Return the next dword
113 * following the copied data.
114 */
115 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
116 {
117 *ptr++ = size;
118 return write_data(ptr, data, size);
119 }
120
121 /**
122 * Read the size as uint followed by the data. Return both via parameters.
123 * Return the next dword following the data.
124 */
125 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
126 {
127 *size = *ptr++;
128 assert(*data == NULL);
129 if (!*size)
130 return ptr;
131 *data = malloc(*size);
132 return read_data(ptr, *data, *size);
133 }
134
135 /**
136 * Return the shader binary in a buffer. The first 4 bytes contain its size
137 * as integer.
138 */
139 static void *si_get_shader_binary(struct si_shader *shader)
140 {
141 /* There is always a size of data followed by the data itself. */
142 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
143 strlen(shader->binary.llvm_ir_string) + 1 : 0;
144
145 /* Refuse to allocate overly large buffers and guard against integer
146 * overflow. */
147 if (shader->binary.elf_size > UINT_MAX / 4 ||
148 llvm_ir_size > UINT_MAX / 4)
149 return NULL;
150
151 unsigned size =
152 4 + /* total size */
153 4 + /* CRC32 of the data below */
154 align(sizeof(shader->config), 4) +
155 align(sizeof(shader->info), 4) +
156 4 + align(shader->binary.elf_size, 4) +
157 4 + align(llvm_ir_size, 4);
158 void *buffer = CALLOC(1, size);
159 uint32_t *ptr = (uint32_t*)buffer;
160
161 if (!buffer)
162 return NULL;
163
164 *ptr++ = size;
165 ptr++; /* CRC32 is calculated at the end. */
166
167 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
168 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
169 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
170 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
171 assert((char *)ptr - (char *)buffer == size);
172
173 /* Compute CRC32. */
174 ptr = (uint32_t*)buffer;
175 ptr++;
176 *ptr = util_hash_crc32(ptr + 1, size - 8);
177
178 return buffer;
179 }
180
181 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
182 {
183 uint32_t *ptr = (uint32_t*)binary;
184 uint32_t size = *ptr++;
185 uint32_t crc32 = *ptr++;
186 unsigned chunk_size;
187 unsigned elf_size;
188
189 if (util_hash_crc32(ptr, size - 8) != crc32) {
190 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
191 return false;
192 }
193
194 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
195 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
196 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
197 &elf_size);
198 shader->binary.elf_size = elf_size;
199 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
200
201 return true;
202 }
203
204 /**
205 * Insert a shader into the cache. It's assumed the shader is not in the cache.
206 * Use si_shader_cache_load_shader before calling this.
207 */
208 void si_shader_cache_insert_shader(struct si_screen *sscreen,
209 unsigned char ir_sha1_cache_key[20],
210 struct si_shader *shader,
211 bool insert_into_disk_cache)
212 {
213 void *hw_binary;
214 struct hash_entry *entry;
215 uint8_t key[CACHE_KEY_SIZE];
216
217 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
218 if (entry)
219 return; /* already added */
220
221 hw_binary = si_get_shader_binary(shader);
222 if (!hw_binary)
223 return;
224
225 if (_mesa_hash_table_insert(sscreen->shader_cache,
226 mem_dup(ir_sha1_cache_key, 20),
227 hw_binary) == NULL) {
228 FREE(hw_binary);
229 return;
230 }
231
232 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
233 disk_cache_compute_key(sscreen->disk_shader_cache,
234 ir_sha1_cache_key, 20, key);
235 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
236 *((uint32_t *) hw_binary), NULL);
237 }
238 }
239
240 bool si_shader_cache_load_shader(struct si_screen *sscreen,
241 unsigned char ir_sha1_cache_key[20],
242 struct si_shader *shader)
243 {
244 struct hash_entry *entry =
245 _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
246
247 if (entry) {
248 if (si_load_shader_binary(shader, entry->data)) {
249 p_atomic_inc(&sscreen->num_memory_shader_cache_hits);
250 return true;
251 }
252 }
253 p_atomic_inc(&sscreen->num_memory_shader_cache_misses);
254
255 if (!sscreen->disk_shader_cache)
256 return false;
257
258 unsigned char sha1[CACHE_KEY_SIZE];
259 disk_cache_compute_key(sscreen->disk_shader_cache, ir_sha1_cache_key,
260 20, sha1);
261
262 size_t binary_size;
263 uint8_t *buffer = disk_cache_get(sscreen->disk_shader_cache, sha1,
264 &binary_size);
265 if (buffer) {
266 if (binary_size >= sizeof(uint32_t) &&
267 *((uint32_t*)buffer) == binary_size) {
268 if (si_load_shader_binary(shader, buffer)) {
269 free(buffer);
270 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
271 shader, false);
272 p_atomic_inc(&sscreen->num_disk_shader_cache_hits);
273 return true;
274 }
275 } else {
276 /* Something has gone wrong discard the item from the cache and
277 * rebuild/link from source.
278 */
279 assert(!"Invalid radeonsi shader disk cache item!");
280 disk_cache_remove(sscreen->disk_shader_cache, sha1);
281 }
282 }
283
284 free(buffer);
285 p_atomic_inc(&sscreen->num_disk_shader_cache_misses);
286 return false;
287 }
288
289 static uint32_t si_shader_cache_key_hash(const void *key)
290 {
291 /* Take the first dword of SHA1. */
292 return *(uint32_t*)key;
293 }
294
295 static bool si_shader_cache_key_equals(const void *a, const void *b)
296 {
297 /* Compare SHA1s. */
298 return memcmp(a, b, 20) == 0;
299 }
300
301 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
302 {
303 FREE((void*)entry->key);
304 FREE(entry->data);
305 }
306
307 bool si_init_shader_cache(struct si_screen *sscreen)
308 {
309 (void) simple_mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
310 sscreen->shader_cache =
311 _mesa_hash_table_create(NULL,
312 si_shader_cache_key_hash,
313 si_shader_cache_key_equals);
314
315 return sscreen->shader_cache != NULL;
316 }
317
318 void si_destroy_shader_cache(struct si_screen *sscreen)
319 {
320 if (sscreen->shader_cache)
321 _mesa_hash_table_destroy(sscreen->shader_cache,
322 si_destroy_shader_cache_entry);
323 simple_mtx_destroy(&sscreen->shader_cache_mutex);
324 }
325
326 /* SHADER STATES */
327
328 static void si_set_tesseval_regs(struct si_screen *sscreen,
329 const struct si_shader_selector *tes,
330 struct si_pm4_state *pm4)
331 {
332 const struct si_shader_info *info = &tes->info;
333 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
334 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
335 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
336 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
337 unsigned type, partitioning, topology, distribution_mode;
338
339 switch (tes_prim_mode) {
340 case PIPE_PRIM_LINES:
341 type = V_028B6C_TESS_ISOLINE;
342 break;
343 case PIPE_PRIM_TRIANGLES:
344 type = V_028B6C_TESS_TRIANGLE;
345 break;
346 case PIPE_PRIM_QUADS:
347 type = V_028B6C_TESS_QUAD;
348 break;
349 default:
350 assert(0);
351 return;
352 }
353
354 switch (tes_spacing) {
355 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
356 partitioning = V_028B6C_PART_FRAC_ODD;
357 break;
358 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
359 partitioning = V_028B6C_PART_FRAC_EVEN;
360 break;
361 case PIPE_TESS_SPACING_EQUAL:
362 partitioning = V_028B6C_PART_INTEGER;
363 break;
364 default:
365 assert(0);
366 return;
367 }
368
369 if (tes_point_mode)
370 topology = V_028B6C_OUTPUT_POINT;
371 else if (tes_prim_mode == PIPE_PRIM_LINES)
372 topology = V_028B6C_OUTPUT_LINE;
373 else if (tes_vertex_order_cw)
374 /* for some reason, this must be the other way around */
375 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
376 else
377 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
378
379 if (sscreen->info.has_distributed_tess) {
380 if (sscreen->info.family == CHIP_FIJI ||
381 sscreen->info.family >= CHIP_POLARIS10)
382 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
383 else
384 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
385 } else
386 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
387
388 assert(pm4->shader);
389 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
390 S_028B6C_PARTITIONING(partitioning) |
391 S_028B6C_TOPOLOGY(topology) |
392 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
393 }
394
395 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
396 * whether the "fractional odd" tessellation spacing is used.
397 *
398 * Possible VGT configurations and which state should set the register:
399 *
400 * Reg set in | VGT shader configuration | Value
401 * ------------------------------------------------------
402 * VS as VS | VS | 30
403 * VS as ES | ES -> GS -> VS | 30
404 * TES as VS | LS -> HS -> VS | 14 or 30
405 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
406 *
407 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
408 */
409 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
410 struct si_shader_selector *sel,
411 struct si_shader *shader,
412 struct si_pm4_state *pm4)
413 {
414 unsigned type = sel->type;
415
416 if (sscreen->info.family < CHIP_POLARIS10 ||
417 sscreen->info.chip_class >= GFX10)
418 return;
419
420 /* VS as VS, or VS as ES: */
421 if ((type == PIPE_SHADER_VERTEX &&
422 (!shader ||
423 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
424 /* TES as VS, or TES as ES: */
425 type == PIPE_SHADER_TESS_EVAL) {
426 unsigned vtx_reuse_depth = 30;
427
428 if (type == PIPE_SHADER_TESS_EVAL &&
429 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
430 PIPE_TESS_SPACING_FRACTIONAL_ODD)
431 vtx_reuse_depth = 14;
432
433 assert(pm4->shader);
434 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
435 }
436 }
437
438 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
439 {
440 if (shader->pm4)
441 si_pm4_clear_state(shader->pm4);
442 else
443 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
444
445 if (shader->pm4) {
446 shader->pm4->shader = shader;
447 return shader->pm4;
448 } else {
449 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
450 return NULL;
451 }
452 }
453
454 static unsigned si_get_num_vs_user_sgprs(struct si_shader *shader,
455 unsigned num_always_on_user_sgprs)
456 {
457 struct si_shader_selector *vs = shader->previous_stage_sel ?
458 shader->previous_stage_sel : shader->selector;
459 unsigned num_vbos_in_user_sgprs = vs->num_vbos_in_user_sgprs;
460
461 /* 1 SGPR is reserved for the vertex buffer pointer. */
462 assert(num_always_on_user_sgprs <= SI_SGPR_VS_VB_DESCRIPTOR_FIRST - 1);
463
464 if (num_vbos_in_user_sgprs)
465 return SI_SGPR_VS_VB_DESCRIPTOR_FIRST + num_vbos_in_user_sgprs * 4;
466
467 /* Add the pointer to VBO descriptors. */
468 return num_always_on_user_sgprs + 1;
469 }
470
471 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
472 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen,
473 struct si_shader *shader, bool legacy_vs_prim_id)
474 {
475 assert(shader->selector->type == PIPE_SHADER_VERTEX ||
476 (shader->previous_stage_sel &&
477 shader->previous_stage_sel->type == PIPE_SHADER_VERTEX));
478
479 /* GFX6-9 LS (VertexID, RelAutoindex, InstanceID / StepRate0(==1), ...).
480 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID, ...)
481 * GFX10 LS (VertexID, RelAutoindex, UserVGPR1, InstanceID).
482 * GFX10 ES,VS (VertexID, UserVGPR0, UserVGPR1 or VSPrimID, UserVGPR2 or InstanceID)
483 */
484 bool is_ls = shader->selector->type == PIPE_SHADER_TESS_CTRL || shader->key.as_ls;
485
486 if (sscreen->info.chip_class >= GFX10 && shader->info.uses_instanceid)
487 return 3;
488 else if ((is_ls && shader->info.uses_instanceid) || legacy_vs_prim_id)
489 return 2;
490 else if (is_ls || shader->info.uses_instanceid)
491 return 1;
492 else
493 return 0;
494 }
495
496 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
497 {
498 struct si_pm4_state *pm4;
499 uint64_t va;
500
501 assert(sscreen->info.chip_class <= GFX8);
502
503 pm4 = si_get_shader_pm4_state(shader);
504 if (!pm4)
505 return;
506
507 va = shader->bo->gpu_address;
508 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
509
510 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
511 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
512
513 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
514 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
515 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen, shader, false)) |
516 S_00B528_DX10_CLAMP(1) |
517 S_00B528_FLOAT_MODE(shader->config.float_mode);
518 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR)) |
519 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
520 }
521
522 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
523 {
524 struct si_pm4_state *pm4;
525 uint64_t va;
526
527 pm4 = si_get_shader_pm4_state(shader);
528 if (!pm4)
529 return;
530
531 va = shader->bo->gpu_address;
532 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
533
534 if (sscreen->info.chip_class >= GFX9) {
535 if (sscreen->info.chip_class >= GFX10) {
536 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
537 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
538 } else {
539 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
540 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
541 }
542
543 unsigned num_user_sgprs =
544 si_get_num_vs_user_sgprs(shader, GFX9_TCS_NUM_USER_SGPR);
545
546 shader->config.rsrc2 =
547 S_00B42C_USER_SGPR(num_user_sgprs) |
548 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
549
550 if (sscreen->info.chip_class >= GFX10)
551 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
552 else
553 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
554 } else {
555 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
556 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
557
558 shader->config.rsrc2 =
559 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
560 S_00B42C_OC_LDS_EN(1) |
561 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
562 }
563
564 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
565 S_00B428_VGPRS((shader->config.num_vgprs - 1) /
566 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
567 (sscreen->info.chip_class <= GFX9 ?
568 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
569 S_00B428_DX10_CLAMP(1) |
570 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
571 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
572 S_00B428_FLOAT_MODE(shader->config.float_mode) |
573 S_00B428_LS_VGPR_COMP_CNT(sscreen->info.chip_class >= GFX9 ?
574 si_get_vs_vgpr_comp_cnt(sscreen, shader, false) : 0));
575
576 if (sscreen->info.chip_class <= GFX8) {
577 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
578 shader->config.rsrc2);
579 }
580 }
581
582 static void si_emit_shader_es(struct si_context *sctx)
583 {
584 struct si_shader *shader = sctx->queued.named.es->shader;
585 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
586
587 if (!shader)
588 return;
589
590 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
591 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
592 shader->selector->esgs_itemsize / 4);
593
594 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
595 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
596 SI_TRACKED_VGT_TF_PARAM,
597 shader->vgt_tf_param);
598
599 if (shader->vgt_vertex_reuse_block_cntl)
600 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
601 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
602 shader->vgt_vertex_reuse_block_cntl);
603
604 if (initial_cdw != sctx->gfx_cs->current.cdw)
605 sctx->context_roll = true;
606 }
607
608 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
609 {
610 struct si_pm4_state *pm4;
611 unsigned num_user_sgprs;
612 unsigned vgpr_comp_cnt;
613 uint64_t va;
614 unsigned oc_lds_en;
615
616 assert(sscreen->info.chip_class <= GFX8);
617
618 pm4 = si_get_shader_pm4_state(shader);
619 if (!pm4)
620 return;
621
622 pm4->atom.emit = si_emit_shader_es;
623 va = shader->bo->gpu_address;
624 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
625
626 if (shader->selector->type == PIPE_SHADER_VERTEX) {
627 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
628 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
629 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
630 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
631 num_user_sgprs = SI_TES_NUM_USER_SGPR;
632 } else
633 unreachable("invalid shader selector type");
634
635 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
636
637 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
638 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
639 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
640 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
641 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
642 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
643 S_00B328_DX10_CLAMP(1) |
644 S_00B328_FLOAT_MODE(shader->config.float_mode));
645 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
646 S_00B32C_USER_SGPR(num_user_sgprs) |
647 S_00B32C_OC_LDS_EN(oc_lds_en) |
648 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
649
650 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
651 si_set_tesseval_regs(sscreen, shader->selector, pm4);
652
653 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
654 }
655
656 void gfx9_get_gs_info(struct si_shader_selector *es,
657 struct si_shader_selector *gs,
658 struct gfx9_gs_info *out)
659 {
660 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
661 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
662 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
663 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
664
665 /* All these are in dwords: */
666 /* We can't allow using the whole LDS, because GS waves compete with
667 * other shader stages for LDS space. */
668 const unsigned max_lds_size = 8 * 1024;
669 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
670 unsigned esgs_lds_size;
671
672 /* All these are per subgroup: */
673 const unsigned max_out_prims = 32 * 1024;
674 const unsigned max_es_verts = 255;
675 const unsigned ideal_gs_prims = 64;
676 unsigned max_gs_prims, gs_prims;
677 unsigned min_es_verts, es_verts, worst_case_es_verts;
678
679 if (uses_adjacency || gs_num_invocations > 1)
680 max_gs_prims = 127 / gs_num_invocations;
681 else
682 max_gs_prims = 255;
683
684 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
685 * Make sure we don't go over the maximum value.
686 */
687 if (gs->gs_max_out_vertices > 0) {
688 max_gs_prims = MIN2(max_gs_prims,
689 max_out_prims /
690 (gs->gs_max_out_vertices * gs_num_invocations));
691 }
692 assert(max_gs_prims > 0);
693
694 /* If the primitive has adjacency, halve the number of vertices
695 * that will be reused in multiple primitives.
696 */
697 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
698
699 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
700 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
701
702 /* Compute ESGS LDS size based on the worst case number of ES vertices
703 * needed to create the target number of GS prims per subgroup.
704 */
705 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
706
707 /* If total LDS usage is too big, refactor partitions based on ratio
708 * of ESGS item sizes.
709 */
710 if (esgs_lds_size > max_lds_size) {
711 /* Our target GS Prims Per Subgroup was too large. Calculate
712 * the maximum number of GS Prims Per Subgroup that will fit
713 * into LDS, capped by the maximum that the hardware can support.
714 */
715 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
716 max_gs_prims);
717 assert(gs_prims > 0);
718 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
719 max_es_verts);
720
721 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
722 assert(esgs_lds_size <= max_lds_size);
723 }
724
725 /* Now calculate remaining ESGS information. */
726 if (esgs_lds_size)
727 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
728 else
729 es_verts = max_es_verts;
730
731 /* Vertices for adjacency primitives are not always reused, so restore
732 * it for ES_VERTS_PER_SUBGRP.
733 */
734 min_es_verts = gs->gs_input_verts_per_prim;
735
736 /* For normal primitives, the VGT only checks if they are past the ES
737 * verts per subgroup after allocating a full GS primitive and if they
738 * are, kick off a new subgroup. But if those additional ES verts are
739 * unique (e.g. not reused) we need to make sure there is enough LDS
740 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
741 */
742 es_verts -= min_es_verts - 1;
743
744 out->es_verts_per_subgroup = es_verts;
745 out->gs_prims_per_subgroup = gs_prims;
746 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
747 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
748 gs->gs_max_out_vertices;
749 out->esgs_ring_size = 4 * esgs_lds_size;
750
751 assert(out->max_prims_per_subgroup <= max_out_prims);
752 }
753
754 static void si_emit_shader_gs(struct si_context *sctx)
755 {
756 struct si_shader *shader = sctx->queued.named.gs->shader;
757 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
758
759 if (!shader)
760 return;
761
762 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
763 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
764 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
765 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
766 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
767 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
768 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
769
770 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
771 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
772 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
773 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
774
775 /* R_028B38_VGT_GS_MAX_VERT_OUT */
776 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
777 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
778 shader->ctx_reg.gs.vgt_gs_max_vert_out);
779
780 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
781 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
782 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
783 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
784 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
785 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
786 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
787 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
788
789 /* R_028B90_VGT_GS_INSTANCE_CNT */
790 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
791 SI_TRACKED_VGT_GS_INSTANCE_CNT,
792 shader->ctx_reg.gs.vgt_gs_instance_cnt);
793
794 if (sctx->chip_class >= GFX9) {
795 /* R_028A44_VGT_GS_ONCHIP_CNTL */
796 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
797 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
798 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
799 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
800 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
801 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
802 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
803 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
804 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
805 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
806 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
807
808 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
809 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
810 SI_TRACKED_VGT_TF_PARAM,
811 shader->vgt_tf_param);
812 if (shader->vgt_vertex_reuse_block_cntl)
813 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
814 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
815 shader->vgt_vertex_reuse_block_cntl);
816 }
817
818 if (initial_cdw != sctx->gfx_cs->current.cdw)
819 sctx->context_roll = true;
820 }
821
822 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
823 {
824 struct si_shader_selector *sel = shader->selector;
825 const ubyte *num_components = sel->info.num_stream_output_components;
826 unsigned gs_num_invocations = sel->gs_num_invocations;
827 struct si_pm4_state *pm4;
828 uint64_t va;
829 unsigned max_stream = sel->max_gs_stream;
830 unsigned offset;
831
832 pm4 = si_get_shader_pm4_state(shader);
833 if (!pm4)
834 return;
835
836 pm4->atom.emit = si_emit_shader_gs;
837
838 offset = num_components[0] * sel->gs_max_out_vertices;
839 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
840
841 if (max_stream >= 1)
842 offset += num_components[1] * sel->gs_max_out_vertices;
843 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
844
845 if (max_stream >= 2)
846 offset += num_components[2] * sel->gs_max_out_vertices;
847 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
848
849 if (max_stream >= 3)
850 offset += num_components[3] * sel->gs_max_out_vertices;
851 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
852
853 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
854 assert(offset < (1 << 15));
855
856 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
857
858 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
859 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
860 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
861 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
862
863 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
864 S_028B90_ENABLE(gs_num_invocations > 0);
865
866 va = shader->bo->gpu_address;
867 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
868
869 if (sscreen->info.chip_class >= GFX9) {
870 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
871 unsigned es_type = shader->key.part.gs.es->type;
872 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
873
874 if (es_type == PIPE_SHADER_VERTEX) {
875 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
876 } else if (es_type == PIPE_SHADER_TESS_EVAL)
877 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
878 else
879 unreachable("invalid shader selector type");
880
881 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
882 * VGPR[0:4] are always loaded.
883 */
884 if (sel->info.uses_invocationid)
885 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
886 else if (sel->info.uses_primid)
887 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
888 else if (input_prim >= PIPE_PRIM_TRIANGLES)
889 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
890 else
891 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
892
893 unsigned num_user_sgprs;
894 if (es_type == PIPE_SHADER_VERTEX)
895 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
896 else
897 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
898
899 if (sscreen->info.chip_class >= GFX10) {
900 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
901 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
902 } else {
903 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
904 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
905 }
906
907 uint32_t rsrc1 =
908 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
909 S_00B228_DX10_CLAMP(1) |
910 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
911 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
912 S_00B228_FLOAT_MODE(shader->config.float_mode) |
913 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
914 uint32_t rsrc2 =
915 S_00B22C_USER_SGPR(num_user_sgprs) |
916 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
917 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
918 S_00B22C_LDS_SIZE(shader->config.lds_size) |
919 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
920
921 if (sscreen->info.chip_class >= GFX10) {
922 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
923 } else {
924 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
925 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
926 }
927
928 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
929 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
930
931 if (sscreen->info.chip_class >= GFX10) {
932 si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
933 S_00B204_CU_EN(0xffff) |
934 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0));
935 }
936
937 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
938 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
939 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
940 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
941 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
942 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
943 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
944 shader->key.part.gs.es->esgs_itemsize / 4;
945
946 if (es_type == PIPE_SHADER_TESS_EVAL)
947 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
948
949 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
950 NULL, pm4);
951 } else {
952 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
953 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
954
955 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
956 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
957 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
958 S_00B228_DX10_CLAMP(1) |
959 S_00B228_FLOAT_MODE(shader->config.float_mode));
960 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
961 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
962 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
963 }
964 }
965
966 static void gfx10_emit_ge_pc_alloc(struct si_context *sctx, unsigned value)
967 {
968 enum si_tracked_reg reg = SI_TRACKED_GE_PC_ALLOC;
969
970 if (((sctx->tracked_regs.reg_saved >> reg) & 0x1) != 0x1 ||
971 sctx->tracked_regs.reg_value[reg] != value) {
972 struct radeon_cmdbuf *cs = sctx->gfx_cs;
973
974 if (sctx->family == CHIP_NAVI10 ||
975 sctx->family == CHIP_NAVI12 ||
976 sctx->family == CHIP_NAVI14) {
977 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
978 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
979 radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
980 }
981
982 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC, value);
983
984 sctx->tracked_regs.reg_saved |= 0x1ull << reg;
985 sctx->tracked_regs.reg_value[reg] = value;
986 }
987 }
988
989 /* Common tail code for NGG primitive shaders. */
990 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
991 struct si_shader *shader,
992 unsigned initial_cdw)
993 {
994 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
995 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
996 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
997 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
998 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
999 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
1000 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1001 SI_TRACKED_VGT_PRIMITIVEID_EN,
1002 shader->ctx_reg.ngg.vgt_primitiveid_en);
1003 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1004 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1005 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
1006 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
1007 SI_TRACKED_VGT_GS_INSTANCE_CNT,
1008 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
1009 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
1010 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
1011 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
1012 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1013 SI_TRACKED_SPI_VS_OUT_CONFIG,
1014 shader->ctx_reg.ngg.spi_vs_out_config);
1015 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
1016 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
1017 shader->ctx_reg.ngg.spi_shader_idx_format,
1018 shader->ctx_reg.ngg.spi_shader_pos_format);
1019 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1020 SI_TRACKED_PA_CL_VTE_CNTL,
1021 shader->ctx_reg.ngg.pa_cl_vte_cntl);
1022 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
1023 SI_TRACKED_PA_CL_NGG_CNTL,
1024 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
1025
1026 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1027 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
1028 shader->pa_cl_vs_out_cntl,
1029 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1030
1031 if (initial_cdw != sctx->gfx_cs->current.cdw)
1032 sctx->context_roll = true;
1033
1034 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1035 gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.ngg.ge_pc_alloc);
1036 }
1037
1038 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
1039 {
1040 struct si_shader *shader = sctx->queued.named.gs->shader;
1041 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1042
1043 if (!shader)
1044 return;
1045
1046 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1047 }
1048
1049 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1050 {
1051 struct si_shader *shader = sctx->queued.named.gs->shader;
1052 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1053
1054 if (!shader)
1055 return;
1056
1057 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1058 SI_TRACKED_VGT_TF_PARAM,
1059 shader->vgt_tf_param);
1060
1061 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1062 }
1063
1064 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1065 {
1066 struct si_shader *shader = sctx->queued.named.gs->shader;
1067 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1068
1069 if (!shader)
1070 return;
1071
1072 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1073 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1074 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1075
1076 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1077 }
1078
1079 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1080 {
1081 struct si_shader *shader = sctx->queued.named.gs->shader;
1082 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1083
1084 if (!shader)
1085 return;
1086
1087 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1088 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1089 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1090 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1091 SI_TRACKED_VGT_TF_PARAM,
1092 shader->vgt_tf_param);
1093
1094 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1095 }
1096
1097 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1098 {
1099 if (gs->type == PIPE_SHADER_GEOMETRY)
1100 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1101
1102 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1103 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1104 return PIPE_PRIM_POINTS;
1105 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1106 return PIPE_PRIM_LINES;
1107 return PIPE_PRIM_TRIANGLES;
1108 }
1109
1110 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1111 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1112 }
1113
1114 static unsigned si_get_vs_out_cntl(const struct si_shader_selector *sel, bool ngg)
1115 {
1116 bool misc_vec_ena =
1117 sel->info.writes_psize || (sel->info.writes_edgeflag && !ngg) ||
1118 sel->info.writes_layer || sel->info.writes_viewport_index;
1119 return S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
1120 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag && !ngg) |
1121 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
1122 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
1123 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1124 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
1125 }
1126
1127 /**
1128 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1129 * in NGG mode.
1130 */
1131 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1132 {
1133 const struct si_shader_selector *gs_sel = shader->selector;
1134 const struct si_shader_info *gs_info = &gs_sel->info;
1135 enum pipe_shader_type gs_type = shader->selector->type;
1136 const struct si_shader_selector *es_sel =
1137 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1138 const struct si_shader_info *es_info = &es_sel->info;
1139 enum pipe_shader_type es_type = es_sel->type;
1140 unsigned num_user_sgprs;
1141 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1142 uint64_t va;
1143 unsigned window_space =
1144 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1145 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1146 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1147 unsigned input_prim = si_get_input_prim(gs_sel);
1148 bool break_wave_at_eoi = false;
1149 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1150 if (!pm4)
1151 return;
1152
1153 if (es_type == PIPE_SHADER_TESS_EVAL) {
1154 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1155 : gfx10_emit_shader_ngg_tess_nogs;
1156 } else {
1157 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1158 : gfx10_emit_shader_ngg_notess_nogs;
1159 }
1160
1161 va = shader->bo->gpu_address;
1162 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1163
1164 if (es_type == PIPE_SHADER_VERTEX) {
1165 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
1166
1167 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1168 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1169 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1170 } else {
1171 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
1172 }
1173 } else {
1174 assert(es_type == PIPE_SHADER_TESS_EVAL);
1175 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1176 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1177
1178 if (es_enable_prim_id || gs_info->uses_primid)
1179 break_wave_at_eoi = true;
1180 }
1181
1182 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1183 * VGPR[0:4] are always loaded.
1184 *
1185 * Vertex shaders always need to load VGPR3, because they need to
1186 * pass edge flags for decomposed primitives (such as quads) to the PA
1187 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1188 */
1189 if (gs_info->uses_invocationid ||
1190 (gs_type == PIPE_SHADER_VERTEX && !gfx10_is_ngg_passthrough(shader)))
1191 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1192 else if ((gs_type == PIPE_SHADER_GEOMETRY && gs_info->uses_primid) ||
1193 (gs_type == PIPE_SHADER_VERTEX && shader->key.mono.u.vs_export_prim_id))
1194 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1195 else if (input_prim >= PIPE_PRIM_TRIANGLES && !gfx10_is_ngg_passthrough(shader))
1196 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1197 else
1198 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1199
1200 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1201 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1202 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1203 S_00B228_VGPRS((shader->config.num_vgprs - 1) /
1204 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1205 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1206 S_00B228_DX10_CLAMP(1) |
1207 S_00B228_MEM_ORDERED(1) |
1208 S_00B228_WGP_MODE(1) |
1209 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1210 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1211 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1212 S_00B22C_USER_SGPR(num_user_sgprs) |
1213 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1214 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1215 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1216 S_00B22C_LDS_SIZE(shader->config.lds_size));
1217
1218 /* Determine LATE_ALLOC_GS. */
1219 unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
1220 unsigned late_alloc_wave64; /* The limit is per SH. */
1221
1222 /* For Wave32, the hw will launch twice the number of late
1223 * alloc waves, so 1 == 2x wave32.
1224 *
1225 * Don't use late alloc for NGG on Navi14 due to a hw bug.
1226 */
1227 if (sscreen->info.family == CHIP_NAVI14)
1228 late_alloc_wave64 = 0;
1229 else if (num_cu_per_sh <= 6)
1230 late_alloc_wave64 = num_cu_per_sh - 2; /* All CUs enabled */
1231 else if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL)
1232 late_alloc_wave64 = (num_cu_per_sh - 2) * 6;
1233 else
1234 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
1235
1236 si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1237 S_00B204_CU_EN(0xffff) |
1238 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64));
1239
1240 nparams = MAX2(shader->info.nr_param_exports, 1);
1241 shader->ctx_reg.ngg.spi_vs_out_config =
1242 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1243 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1244
1245 shader->ctx_reg.ngg.spi_shader_idx_format =
1246 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1247 shader->ctx_reg.ngg.spi_shader_pos_format =
1248 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1249 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1250 V_02870C_SPI_SHADER_4COMP :
1251 V_02870C_SPI_SHADER_NONE) |
1252 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1253 V_02870C_SPI_SHADER_4COMP :
1254 V_02870C_SPI_SHADER_NONE) |
1255 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1256 V_02870C_SPI_SHADER_4COMP :
1257 V_02870C_SPI_SHADER_NONE);
1258
1259 shader->ctx_reg.ngg.vgt_primitiveid_en =
1260 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1261 S_028A84_NGG_DISABLE_PROVOK_REUSE(shader->key.mono.u.vs_export_prim_id ||
1262 gs_sel->info.writes_primid);
1263
1264 if (gs_type == PIPE_SHADER_GEOMETRY) {
1265 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1266 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1267 } else {
1268 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1269 }
1270
1271 if (es_type == PIPE_SHADER_TESS_EVAL)
1272 si_set_tesseval_regs(sscreen, es_sel, pm4);
1273
1274 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1275 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1276 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1277 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1278 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1279 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1280 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1281 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1282 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1283 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1284 S_028B90_CNT(gs_num_invocations) |
1285 S_028B90_ENABLE(gs_num_invocations > 1) |
1286 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1287 shader->ngg.max_vert_out_per_gs_instance);
1288
1289 /* Always output hw-generated edge flags and pass them via the prim
1290 * export to prevent drawing lines on internal edges of decomposed
1291 * primitives (such as quads) with polygon mode = lines. Only VS needs
1292 * this.
1293 */
1294 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1295 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
1296 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(gs_sel, true);
1297
1298 /* Oversubscribe PC. This improves performance when there are too many varyings. */
1299 float oversub_pc_factor = 0.25;
1300
1301 if (shader->key.opt.ngg_culling) {
1302 /* Be more aggressive with NGG culling. */
1303 if (shader->info.nr_param_exports > 4)
1304 oversub_pc_factor = 1;
1305 else if (shader->info.nr_param_exports > 2)
1306 oversub_pc_factor = 0.75;
1307 else
1308 oversub_pc_factor = 0.5;
1309 }
1310
1311 unsigned oversub_pc_lines = sscreen->info.pc_lines * oversub_pc_factor;
1312 shader->ctx_reg.ngg.ge_pc_alloc = S_030980_OVERSUB_EN(1) |
1313 S_030980_NUM_PC_LINES(oversub_pc_lines - 1);
1314
1315 if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_TRI_LIST) {
1316 shader->ge_cntl =
1317 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1318 S_03096C_VERT_GRP_SIZE(shader->ngg.max_gsprims * 3);
1319 } else if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_TRI_STRIP) {
1320 shader->ge_cntl =
1321 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1322 S_03096C_VERT_GRP_SIZE(shader->ngg.max_gsprims + 2);
1323 } else {
1324 shader->ge_cntl =
1325 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1326 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
1327 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1328
1329 /* Bug workaround for a possible hang with non-tessellation cases.
1330 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1331 *
1332 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1333 */
1334 if ((sscreen->info.family == CHIP_NAVI10 ||
1335 sscreen->info.family == CHIP_NAVI12 ||
1336 sscreen->info.family == CHIP_NAVI14) &&
1337 (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
1338 shader->ngg.hw_max_esverts != 256) {
1339 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1340
1341 if (shader->ngg.hw_max_esverts > 5) {
1342 shader->ge_cntl |=
1343 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1344 }
1345 }
1346 }
1347
1348 if (window_space) {
1349 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1350 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1351 } else {
1352 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1353 S_028818_VTX_W0_FMT(1) |
1354 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1355 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1356 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1357 }
1358 }
1359
1360 static void si_emit_shader_vs(struct si_context *sctx)
1361 {
1362 struct si_shader *shader = sctx->queued.named.vs->shader;
1363 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1364
1365 if (!shader)
1366 return;
1367
1368 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1369 SI_TRACKED_VGT_GS_MODE,
1370 shader->ctx_reg.vs.vgt_gs_mode);
1371 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1372 SI_TRACKED_VGT_PRIMITIVEID_EN,
1373 shader->ctx_reg.vs.vgt_primitiveid_en);
1374
1375 if (sctx->chip_class <= GFX8) {
1376 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1377 SI_TRACKED_VGT_REUSE_OFF,
1378 shader->ctx_reg.vs.vgt_reuse_off);
1379 }
1380
1381 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1382 SI_TRACKED_SPI_VS_OUT_CONFIG,
1383 shader->ctx_reg.vs.spi_vs_out_config);
1384
1385 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1386 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1387 shader->ctx_reg.vs.spi_shader_pos_format);
1388
1389 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1390 SI_TRACKED_PA_CL_VTE_CNTL,
1391 shader->ctx_reg.vs.pa_cl_vte_cntl);
1392
1393 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1394 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1395 SI_TRACKED_VGT_TF_PARAM,
1396 shader->vgt_tf_param);
1397
1398 if (shader->vgt_vertex_reuse_block_cntl)
1399 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1400 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1401 shader->vgt_vertex_reuse_block_cntl);
1402
1403 /* Required programming for tessellation. (legacy pipeline only) */
1404 if (sctx->chip_class == GFX10 &&
1405 shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1406 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1407 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1408 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1409 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1410 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1411 }
1412
1413 if (sctx->chip_class >= GFX10) {
1414 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1415 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
1416 shader->pa_cl_vs_out_cntl,
1417 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1418 }
1419
1420 if (initial_cdw != sctx->gfx_cs->current.cdw)
1421 sctx->context_roll = true;
1422
1423 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1424 if (sctx->chip_class >= GFX10)
1425 gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.vs.ge_pc_alloc);
1426 }
1427
1428 /**
1429 * Compute the state for \p shader, which will run as a vertex shader on the
1430 * hardware.
1431 *
1432 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1433 * is the copy shader.
1434 */
1435 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1436 struct si_shader_selector *gs)
1437 {
1438 const struct si_shader_info *info = &shader->selector->info;
1439 struct si_pm4_state *pm4;
1440 unsigned num_user_sgprs, vgpr_comp_cnt;
1441 uint64_t va;
1442 unsigned nparams, oc_lds_en;
1443 unsigned window_space =
1444 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1445 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1446
1447 pm4 = si_get_shader_pm4_state(shader);
1448 if (!pm4)
1449 return;
1450
1451 pm4->atom.emit = si_emit_shader_vs;
1452
1453 /* We always write VGT_GS_MODE in the VS state, because every switch
1454 * between different shader pipelines involving a different GS or no
1455 * GS at all involves a switch of the VS (different GS use different
1456 * copy shaders). On the other hand, when the API switches from a GS to
1457 * no GS and then back to the same GS used originally, the GS state is
1458 * not sent again.
1459 */
1460 if (!gs) {
1461 unsigned mode = V_028A40_GS_OFF;
1462
1463 /* PrimID needs GS scenario A. */
1464 if (enable_prim_id)
1465 mode = V_028A40_GS_SCENARIO_A;
1466
1467 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1468 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1469 } else {
1470 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1471 sscreen->info.chip_class);
1472 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1473 }
1474
1475 if (sscreen->info.chip_class <= GFX8) {
1476 /* Reuse needs to be set off if we write oViewport. */
1477 shader->ctx_reg.vs.vgt_reuse_off =
1478 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1479 }
1480
1481 va = shader->bo->gpu_address;
1482 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1483
1484 if (gs) {
1485 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1486 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1487 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1488 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
1489
1490 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1491 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1492 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1493 } else {
1494 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
1495 }
1496 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1497 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1498 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1499 } else
1500 unreachable("invalid shader selector type");
1501
1502 /* VS is required to export at least one param. */
1503 nparams = MAX2(shader->info.nr_param_exports, 1);
1504 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1505
1506 if (sscreen->info.chip_class >= GFX10) {
1507 shader->ctx_reg.vs.spi_vs_out_config |=
1508 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1509 }
1510
1511 shader->ctx_reg.vs.spi_shader_pos_format =
1512 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1513 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1514 V_02870C_SPI_SHADER_4COMP :
1515 V_02870C_SPI_SHADER_NONE) |
1516 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1517 V_02870C_SPI_SHADER_4COMP :
1518 V_02870C_SPI_SHADER_NONE) |
1519 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1520 V_02870C_SPI_SHADER_4COMP :
1521 V_02870C_SPI_SHADER_NONE);
1522 shader->ctx_reg.vs.ge_pc_alloc = S_030980_OVERSUB_EN(1) |
1523 S_030980_NUM_PC_LINES(sscreen->info.pc_lines / 4 - 1);
1524 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, false);
1525
1526 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1527
1528 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1529 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1530
1531 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
1532 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1533 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1534 S_00B128_DX10_CLAMP(1) |
1535 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1536 S_00B128_FLOAT_MODE(shader->config.float_mode);
1537 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1538 S_00B12C_OC_LDS_EN(oc_lds_en) |
1539 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1540
1541 if (sscreen->info.chip_class >= GFX10)
1542 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
1543 else if (sscreen->info.chip_class == GFX9)
1544 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
1545
1546 if (sscreen->info.chip_class <= GFX9)
1547 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1548
1549 if (!sscreen->use_ngg_streamout) {
1550 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1551 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1552 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1553 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1554 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1555 }
1556
1557 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1558 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1559
1560 if (window_space)
1561 shader->ctx_reg.vs.pa_cl_vte_cntl =
1562 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1563 else
1564 shader->ctx_reg.vs.pa_cl_vte_cntl =
1565 S_028818_VTX_W0_FMT(1) |
1566 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1567 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1568 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1569
1570 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1571 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1572
1573 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1574 }
1575
1576 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1577 {
1578 struct si_shader_info *info = &ps->selector->info;
1579 unsigned num_colors = !!(info->colors_read & 0x0f) +
1580 !!(info->colors_read & 0xf0);
1581 unsigned num_interp = ps->selector->info.num_inputs +
1582 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1583
1584 assert(num_interp <= 32);
1585 return MIN2(num_interp, 32);
1586 }
1587
1588 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1589 {
1590 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1591 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1592
1593 /* If the i-th target format is set, all previous target formats must
1594 * be non-zero to avoid hangs.
1595 */
1596 for (i = 0; i < num_targets; i++)
1597 if (!(value & (0xf << (i * 4))))
1598 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1599
1600 return value;
1601 }
1602
1603 static void si_emit_shader_ps(struct si_context *sctx)
1604 {
1605 struct si_shader *shader = sctx->queued.named.ps->shader;
1606 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1607
1608 if (!shader)
1609 return;
1610
1611 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1612 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1613 SI_TRACKED_SPI_PS_INPUT_ENA,
1614 shader->ctx_reg.ps.spi_ps_input_ena,
1615 shader->ctx_reg.ps.spi_ps_input_addr);
1616
1617 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1618 SI_TRACKED_SPI_BARYC_CNTL,
1619 shader->ctx_reg.ps.spi_baryc_cntl);
1620 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1621 SI_TRACKED_SPI_PS_IN_CONTROL,
1622 shader->ctx_reg.ps.spi_ps_in_control);
1623
1624 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1625 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1626 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1627 shader->ctx_reg.ps.spi_shader_z_format,
1628 shader->ctx_reg.ps.spi_shader_col_format);
1629
1630 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1631 SI_TRACKED_CB_SHADER_MASK,
1632 shader->ctx_reg.ps.cb_shader_mask);
1633
1634 if (initial_cdw != sctx->gfx_cs->current.cdw)
1635 sctx->context_roll = true;
1636 }
1637
1638 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1639 {
1640 struct si_shader_info *info = &shader->selector->info;
1641 struct si_pm4_state *pm4;
1642 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1643 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1644 uint64_t va;
1645 unsigned input_ena = shader->config.spi_ps_input_ena;
1646
1647 /* we need to enable at least one of them, otherwise we hang the GPU */
1648 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1649 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1650 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1651 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1652 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1653 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1654 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1655 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1656 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1657 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1658 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1659 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1660 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1661 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1662
1663 /* Validate interpolation optimization flags (read as implications). */
1664 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1665 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1666 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1667 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1668 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1669 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1670 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1671 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1672 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1673 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1674 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1675 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1676 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1677 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1678 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1679 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1680 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1681 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1682
1683 /* Validate cases when the optimizations are off (read as implications). */
1684 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1685 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1686 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1687 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1688 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1689 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1690
1691 pm4 = si_get_shader_pm4_state(shader);
1692 if (!pm4)
1693 return;
1694
1695 pm4->atom.emit = si_emit_shader_ps;
1696
1697 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1698 * Possible vaules:
1699 * 0 -> Position = pixel center
1700 * 1 -> Position = pixel centroid
1701 * 2 -> Position = at sample position
1702 *
1703 * From GLSL 4.5 specification, section 7.1:
1704 * "The variable gl_FragCoord is available as an input variable from
1705 * within fragment shaders and it holds the window relative coordinates
1706 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1707 * value can be for any location within the pixel, or one of the
1708 * fragment samples. The use of centroid does not further restrict
1709 * this value to be inside the current primitive."
1710 *
1711 * Meaning that centroid has no effect and we can return anything within
1712 * the pixel. Thus, return the value at sample position, because that's
1713 * the most accurate one shaders can get.
1714 */
1715 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1716
1717 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1718 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1719 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1720
1721 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1722 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1723
1724 /* Ensure that some export memory is always allocated, for two reasons:
1725 *
1726 * 1) Correctness: The hardware ignores the EXEC mask if no export
1727 * memory is allocated, so KILL and alpha test do not work correctly
1728 * without this.
1729 * 2) Performance: Every shader needs at least a NULL export, even when
1730 * it writes no color/depth output. The NULL export instruction
1731 * stalls without this setting.
1732 *
1733 * Don't add this to CB_SHADER_MASK.
1734 *
1735 * GFX10 supports pixel shaders without exports by setting both
1736 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1737 * instructions if any are present.
1738 */
1739 if ((sscreen->info.chip_class <= GFX9 ||
1740 info->uses_kill ||
1741 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1742 !spi_shader_col_format &&
1743 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1744 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1745
1746 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1747 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1748
1749 /* Set interpolation controls. */
1750 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1751 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1752
1753 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1754 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1755 shader->ctx_reg.ps.spi_shader_z_format =
1756 ac_get_spi_shader_z_format(info->writes_z,
1757 info->writes_stencil,
1758 info->writes_samplemask);
1759 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1760 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1761
1762 va = shader->bo->gpu_address;
1763 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1764 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1765 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1766
1767 uint32_t rsrc1 =
1768 S_00B028_VGPRS((shader->config.num_vgprs - 1) /
1769 (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1770 S_00B028_DX10_CLAMP(1) |
1771 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1772 S_00B028_FLOAT_MODE(shader->config.float_mode);
1773
1774 if (sscreen->info.chip_class < GFX10) {
1775 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1776 }
1777
1778 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1779 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1780 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1781 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1782 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1783 }
1784
1785 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1786 struct si_shader *shader)
1787 {
1788 switch (shader->selector->type) {
1789 case PIPE_SHADER_VERTEX:
1790 if (shader->key.as_ls)
1791 si_shader_ls(sscreen, shader);
1792 else if (shader->key.as_es)
1793 si_shader_es(sscreen, shader);
1794 else if (shader->key.as_ngg)
1795 gfx10_shader_ngg(sscreen, shader);
1796 else
1797 si_shader_vs(sscreen, shader, NULL);
1798 break;
1799 case PIPE_SHADER_TESS_CTRL:
1800 si_shader_hs(sscreen, shader);
1801 break;
1802 case PIPE_SHADER_TESS_EVAL:
1803 if (shader->key.as_es)
1804 si_shader_es(sscreen, shader);
1805 else if (shader->key.as_ngg)
1806 gfx10_shader_ngg(sscreen, shader);
1807 else
1808 si_shader_vs(sscreen, shader, NULL);
1809 break;
1810 case PIPE_SHADER_GEOMETRY:
1811 if (shader->key.as_ngg)
1812 gfx10_shader_ngg(sscreen, shader);
1813 else
1814 si_shader_gs(sscreen, shader);
1815 break;
1816 case PIPE_SHADER_FRAGMENT:
1817 si_shader_ps(sscreen, shader);
1818 break;
1819 default:
1820 assert(0);
1821 }
1822 }
1823
1824 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1825 {
1826 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1827 return sctx->queued.named.dsa->alpha_func;
1828 }
1829
1830 void si_shader_selector_key_vs(struct si_context *sctx,
1831 struct si_shader_selector *vs,
1832 struct si_shader_key *key,
1833 struct si_vs_prolog_bits *prolog_key)
1834 {
1835 if (!sctx->vertex_elements ||
1836 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
1837 return;
1838
1839 struct si_vertex_elements *elts = sctx->vertex_elements;
1840
1841 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1842 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1843 prolog_key->unpack_instance_id_from_vertex_id =
1844 sctx->prim_discard_cs_instancing;
1845
1846 /* Prefer a monolithic shader to allow scheduling divisions around
1847 * VBO loads. */
1848 if (prolog_key->instance_divisor_is_fetched)
1849 key->opt.prefer_mono = 1;
1850
1851 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1852 unsigned count_mask = (1 << count) - 1;
1853 unsigned fix = elts->fix_fetch_always & count_mask;
1854 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1855
1856 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1857 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1858 while (mask) {
1859 unsigned i = u_bit_scan(&mask);
1860 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1861 unsigned vbidx = elts->vertex_buffer_index[i];
1862 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1863 unsigned align_mask = (1 << log_hw_load_size) - 1;
1864 if (vb->buffer_offset & align_mask ||
1865 vb->stride & align_mask) {
1866 fix |= 1 << i;
1867 opencode |= 1 << i;
1868 }
1869 }
1870 }
1871
1872 while (fix) {
1873 unsigned i = u_bit_scan(&fix);
1874 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1875 }
1876 key->mono.vs_fetch_opencode = opencode;
1877 }
1878
1879 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1880 struct si_shader_selector *vs,
1881 struct si_shader_key *key)
1882 {
1883 struct si_shader_selector *ps = sctx->ps_shader.cso;
1884
1885 key->opt.clip_disable =
1886 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1887 (vs->info.clipdist_writemask ||
1888 vs->info.writes_clipvertex) &&
1889 !vs->info.culldist_writemask;
1890
1891 /* Find out if PS is disabled. */
1892 bool ps_disabled = true;
1893 if (ps) {
1894 bool ps_modifies_zs = ps->info.uses_kill ||
1895 ps->info.writes_z ||
1896 ps->info.writes_stencil ||
1897 ps->info.writes_samplemask ||
1898 sctx->queued.named.blend->alpha_to_coverage ||
1899 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1900 unsigned ps_colormask = si_get_total_colormask(sctx);
1901
1902 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1903 (!ps_colormask &&
1904 !ps_modifies_zs &&
1905 !ps->info.writes_memory);
1906 }
1907
1908 /* Find out which VS outputs aren't used by the PS. */
1909 uint64_t outputs_written = vs->outputs_written_before_ps;
1910 uint64_t inputs_read = 0;
1911
1912 /* Ignore outputs that are not passed from VS to PS. */
1913 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1914 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1915 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1916
1917 if (!ps_disabled) {
1918 inputs_read = ps->inputs_read;
1919 }
1920
1921 uint64_t linked = outputs_written & inputs_read;
1922
1923 key->opt.kill_outputs = ~linked & outputs_written;
1924 key->opt.ngg_culling = sctx->ngg_culling;
1925 }
1926
1927 /* Compute the key for the hw shader variant */
1928 static inline void si_shader_selector_key(struct pipe_context *ctx,
1929 struct si_shader_selector *sel,
1930 union si_vgt_stages_key stages_key,
1931 struct si_shader_key *key)
1932 {
1933 struct si_context *sctx = (struct si_context *)ctx;
1934
1935 memset(key, 0, sizeof(*key));
1936
1937 switch (sel->type) {
1938 case PIPE_SHADER_VERTEX:
1939 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1940
1941 if (sctx->tes_shader.cso)
1942 key->as_ls = 1;
1943 else if (sctx->gs_shader.cso) {
1944 key->as_es = 1;
1945 key->as_ngg = stages_key.u.ngg;
1946 } else {
1947 key->as_ngg = stages_key.u.ngg;
1948 si_shader_selector_key_hw_vs(sctx, sel, key);
1949
1950 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1951 key->mono.u.vs_export_prim_id = 1;
1952 }
1953 break;
1954 case PIPE_SHADER_TESS_CTRL:
1955 if (sctx->chip_class >= GFX9) {
1956 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1957 key, &key->part.tcs.ls_prolog);
1958 key->part.tcs.ls = sctx->vs_shader.cso;
1959
1960 /* When the LS VGPR fix is needed, monolithic shaders
1961 * can:
1962 * - avoid initializing EXEC in both the LS prolog
1963 * and the LS main part when !vs_needs_prolog
1964 * - remove the fixup for unused input VGPRs
1965 */
1966 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1967
1968 /* The LS output / HS input layout can be communicated
1969 * directly instead of via user SGPRs for merged LS-HS.
1970 * The LS VGPR fix prefers this too.
1971 */
1972 key->opt.prefer_mono = 1;
1973 }
1974
1975 key->part.tcs.epilog.prim_mode =
1976 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1977 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1978 sel->info.tessfactors_are_def_in_all_invocs;
1979 key->part.tcs.epilog.tes_reads_tess_factors =
1980 sctx->tes_shader.cso->info.reads_tess_factors;
1981
1982 if (sel == sctx->fixed_func_tcs_shader.cso)
1983 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1984 break;
1985 case PIPE_SHADER_TESS_EVAL:
1986 key->as_ngg = stages_key.u.ngg;
1987
1988 if (sctx->gs_shader.cso)
1989 key->as_es = 1;
1990 else {
1991 si_shader_selector_key_hw_vs(sctx, sel, key);
1992
1993 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1994 key->mono.u.vs_export_prim_id = 1;
1995 }
1996 break;
1997 case PIPE_SHADER_GEOMETRY:
1998 if (sctx->chip_class >= GFX9) {
1999 if (sctx->tes_shader.cso) {
2000 key->part.gs.es = sctx->tes_shader.cso;
2001 } else {
2002 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
2003 key, &key->part.gs.vs_prolog);
2004 key->part.gs.es = sctx->vs_shader.cso;
2005 key->part.gs.prolog.gfx9_prev_is_vs = 1;
2006 }
2007
2008 key->as_ngg = stages_key.u.ngg;
2009
2010 /* Merged ES-GS can have unbalanced wave usage.
2011 *
2012 * ES threads are per-vertex, while GS threads are
2013 * per-primitive. So without any amplification, there
2014 * are fewer GS threads than ES threads, which can result
2015 * in empty (no-op) GS waves. With too much amplification,
2016 * there are more GS threads than ES threads, which
2017 * can result in empty (no-op) ES waves.
2018 *
2019 * Non-monolithic shaders are implemented by setting EXEC
2020 * at the beginning of shader parts, and don't jump to
2021 * the end if EXEC is 0.
2022 *
2023 * Monolithic shaders use conditional blocks, so they can
2024 * jump and skip empty waves of ES or GS. So set this to
2025 * always use optimized variants, which are monolithic.
2026 */
2027 key->opt.prefer_mono = 1;
2028 }
2029 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
2030 break;
2031 case PIPE_SHADER_FRAGMENT: {
2032 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2033 struct si_state_blend *blend = sctx->queued.named.blend;
2034
2035 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
2036 sel->info.colors_written == 0x1)
2037 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
2038
2039 /* Select the shader color format based on whether
2040 * blending or alpha are needed.
2041 */
2042 key->part.ps.epilog.spi_shader_col_format =
2043 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
2044 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
2045 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
2046 sctx->framebuffer.spi_shader_col_format_blend) |
2047 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
2048 sctx->framebuffer.spi_shader_col_format_alpha) |
2049 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
2050 sctx->framebuffer.spi_shader_col_format);
2051 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
2052
2053 /* The output for dual source blending should have
2054 * the same format as the first output.
2055 */
2056 if (blend->dual_src_blend) {
2057 key->part.ps.epilog.spi_shader_col_format |=
2058 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
2059 }
2060
2061 /* If alpha-to-coverage is enabled, we have to export alpha
2062 * even if there is no color buffer.
2063 */
2064 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
2065 blend->alpha_to_coverage)
2066 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
2067
2068 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
2069 * to the range supported by the type if a channel has less
2070 * than 16 bits and the export format is 16_ABGR.
2071 */
2072 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
2073 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
2074 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
2075 }
2076
2077 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
2078 if (!key->part.ps.epilog.last_cbuf) {
2079 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
2080 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
2081 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
2082 }
2083
2084 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
2085 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
2086
2087 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
2088 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
2089
2090 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one &&
2091 rs->multisample_enable;
2092
2093 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
2094 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
2095 (is_line && rs->line_smooth)) &&
2096 sctx->framebuffer.nr_samples <= 1;
2097 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
2098
2099 if (sctx->ps_iter_samples > 1 &&
2100 sel->info.reads_samplemask) {
2101 key->part.ps.prolog.samplemask_log_ps_iter =
2102 util_logbase2(sctx->ps_iter_samples);
2103 }
2104
2105 if (rs->force_persample_interp &&
2106 rs->multisample_enable &&
2107 sctx->framebuffer.nr_samples > 1 &&
2108 sctx->ps_iter_samples > 1) {
2109 key->part.ps.prolog.force_persp_sample_interp =
2110 sel->info.uses_persp_center ||
2111 sel->info.uses_persp_centroid;
2112
2113 key->part.ps.prolog.force_linear_sample_interp =
2114 sel->info.uses_linear_center ||
2115 sel->info.uses_linear_centroid;
2116 } else if (rs->multisample_enable &&
2117 sctx->framebuffer.nr_samples > 1) {
2118 key->part.ps.prolog.bc_optimize_for_persp =
2119 sel->info.uses_persp_center &&
2120 sel->info.uses_persp_centroid;
2121 key->part.ps.prolog.bc_optimize_for_linear =
2122 sel->info.uses_linear_center &&
2123 sel->info.uses_linear_centroid;
2124 } else {
2125 /* Make sure SPI doesn't compute more than 1 pair
2126 * of (i,j), which is the optimization here. */
2127 key->part.ps.prolog.force_persp_center_interp =
2128 sel->info.uses_persp_center +
2129 sel->info.uses_persp_centroid +
2130 sel->info.uses_persp_sample > 1;
2131
2132 key->part.ps.prolog.force_linear_center_interp =
2133 sel->info.uses_linear_center +
2134 sel->info.uses_linear_centroid +
2135 sel->info.uses_linear_sample > 1;
2136
2137 if (sel->info.uses_persp_opcode_interp_sample ||
2138 sel->info.uses_linear_opcode_interp_sample)
2139 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2140 }
2141
2142 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2143
2144 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2145 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2146 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2147 struct pipe_resource *tex = cb0->texture;
2148
2149 /* 1D textures are allocated and used as 2D on GFX9. */
2150 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2151 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2152 (tex->target == PIPE_TEXTURE_1D ||
2153 tex->target == PIPE_TEXTURE_1D_ARRAY);
2154 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2155 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2156 tex->target == PIPE_TEXTURE_CUBE ||
2157 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2158 tex->target == PIPE_TEXTURE_3D;
2159 }
2160 break;
2161 }
2162 default:
2163 assert(0);
2164 }
2165
2166 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2167 memset(&key->opt, 0, sizeof(key->opt));
2168 }
2169
2170 static void si_build_shader_variant(struct si_shader *shader,
2171 int thread_index,
2172 bool low_priority)
2173 {
2174 struct si_shader_selector *sel = shader->selector;
2175 struct si_screen *sscreen = sel->screen;
2176 struct ac_llvm_compiler *compiler;
2177 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2178
2179 if (thread_index >= 0) {
2180 if (low_priority) {
2181 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2182 compiler = &sscreen->compiler_lowp[thread_index];
2183 } else {
2184 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2185 compiler = &sscreen->compiler[thread_index];
2186 }
2187 if (!debug->async)
2188 debug = NULL;
2189 } else {
2190 assert(!low_priority);
2191 compiler = shader->compiler_ctx_state.compiler;
2192 }
2193
2194 if (!compiler->passes)
2195 si_init_compiler(sscreen, compiler);
2196
2197 if (unlikely(!si_create_shader_variant(sscreen, compiler, shader, debug))) {
2198 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2199 sel->type);
2200 shader->compilation_failed = true;
2201 return;
2202 }
2203
2204 if (shader->compiler_ctx_state.is_debug_context) {
2205 FILE *f = open_memstream(&shader->shader_log,
2206 &shader->shader_log_size);
2207 if (f) {
2208 si_shader_dump(sscreen, shader, NULL, f, false);
2209 fclose(f);
2210 }
2211 }
2212
2213 si_shader_init_pm4_state(sscreen, shader);
2214 }
2215
2216 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2217 {
2218 struct si_shader *shader = (struct si_shader *)job;
2219
2220 assert(thread_index >= 0);
2221
2222 si_build_shader_variant(shader, thread_index, true);
2223 }
2224
2225 static const struct si_shader_key zeroed;
2226
2227 static bool si_check_missing_main_part(struct si_screen *sscreen,
2228 struct si_shader_selector *sel,
2229 struct si_compiler_ctx_state *compiler_state,
2230 struct si_shader_key *key)
2231 {
2232 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2233
2234 if (!*mainp) {
2235 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2236
2237 if (!main_part)
2238 return false;
2239
2240 /* We can leave the fence as permanently signaled because the
2241 * main part becomes visible globally only after it has been
2242 * compiled. */
2243 util_queue_fence_init(&main_part->ready);
2244
2245 main_part->selector = sel;
2246 main_part->key.as_es = key->as_es;
2247 main_part->key.as_ls = key->as_ls;
2248 main_part->key.as_ngg = key->as_ngg;
2249 main_part->is_monolithic = false;
2250
2251 if (!si_compile_shader(sscreen, compiler_state->compiler,
2252 main_part, &compiler_state->debug)) {
2253 FREE(main_part);
2254 return false;
2255 }
2256 *mainp = main_part;
2257 }
2258 return true;
2259 }
2260
2261 /**
2262 * Select a shader variant according to the shader key.
2263 *
2264 * \param optimized_or_none If the key describes an optimized shader variant and
2265 * the compilation isn't finished, don't select any
2266 * shader and return an error.
2267 */
2268 int si_shader_select_with_key(struct si_screen *sscreen,
2269 struct si_shader_ctx_state *state,
2270 struct si_compiler_ctx_state *compiler_state,
2271 struct si_shader_key *key,
2272 int thread_index,
2273 bool optimized_or_none)
2274 {
2275 struct si_shader_selector *sel = state->cso;
2276 struct si_shader_selector *previous_stage_sel = NULL;
2277 struct si_shader *current = state->current;
2278 struct si_shader *iter, *shader = NULL;
2279
2280 again:
2281 /* Check if we don't need to change anything.
2282 * This path is also used for most shaders that don't need multiple
2283 * variants, it will cost just a computation of the key and this
2284 * test. */
2285 if (likely(current &&
2286 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2287 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2288 if (current->is_optimized) {
2289 if (optimized_or_none)
2290 return -1;
2291
2292 memset(&key->opt, 0, sizeof(key->opt));
2293 goto current_not_ready;
2294 }
2295
2296 util_queue_fence_wait(&current->ready);
2297 }
2298
2299 return current->compilation_failed ? -1 : 0;
2300 }
2301 current_not_ready:
2302
2303 /* This must be done before the mutex is locked, because async GS
2304 * compilation calls this function too, and therefore must enter
2305 * the mutex first.
2306 *
2307 * Only wait if we are in a draw call. Don't wait if we are
2308 * in a compiler thread.
2309 */
2310 if (thread_index < 0)
2311 util_queue_fence_wait(&sel->ready);
2312
2313 simple_mtx_lock(&sel->mutex);
2314
2315 /* Find the shader variant. */
2316 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2317 /* Don't check the "current" shader. We checked it above. */
2318 if (current != iter &&
2319 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2320 simple_mtx_unlock(&sel->mutex);
2321
2322 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2323 /* If it's an optimized shader and its compilation has
2324 * been started but isn't done, use the unoptimized
2325 * shader so as not to cause a stall due to compilation.
2326 */
2327 if (iter->is_optimized) {
2328 if (optimized_or_none)
2329 return -1;
2330 memset(&key->opt, 0, sizeof(key->opt));
2331 goto again;
2332 }
2333
2334 util_queue_fence_wait(&iter->ready);
2335 }
2336
2337 if (iter->compilation_failed) {
2338 return -1; /* skip the draw call */
2339 }
2340
2341 state->current = iter;
2342 return 0;
2343 }
2344 }
2345
2346 /* Build a new shader. */
2347 shader = CALLOC_STRUCT(si_shader);
2348 if (!shader) {
2349 simple_mtx_unlock(&sel->mutex);
2350 return -ENOMEM;
2351 }
2352
2353 util_queue_fence_init(&shader->ready);
2354
2355 shader->selector = sel;
2356 shader->key = *key;
2357 shader->compiler_ctx_state = *compiler_state;
2358
2359 /* If this is a merged shader, get the first shader's selector. */
2360 if (sscreen->info.chip_class >= GFX9) {
2361 if (sel->type == PIPE_SHADER_TESS_CTRL)
2362 previous_stage_sel = key->part.tcs.ls;
2363 else if (sel->type == PIPE_SHADER_GEOMETRY)
2364 previous_stage_sel = key->part.gs.es;
2365
2366 /* We need to wait for the previous shader. */
2367 if (previous_stage_sel && thread_index < 0)
2368 util_queue_fence_wait(&previous_stage_sel->ready);
2369 }
2370
2371 bool is_pure_monolithic =
2372 sscreen->use_monolithic_shaders ||
2373 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2374
2375 /* Compile the main shader part if it doesn't exist. This can happen
2376 * if the initial guess was wrong.
2377 *
2378 * The prim discard CS doesn't need the main shader part.
2379 */
2380 if (!is_pure_monolithic &&
2381 !key->opt.vs_as_prim_discard_cs) {
2382 bool ok = true;
2383
2384 /* Make sure the main shader part is present. This is needed
2385 * for shaders that can be compiled as VS, LS, or ES, and only
2386 * one of them is compiled at creation.
2387 *
2388 * It is also needed for GS, which can be compiled as non-NGG
2389 * and NGG.
2390 *
2391 * For merged shaders, check that the starting shader's main
2392 * part is present.
2393 */
2394 if (previous_stage_sel) {
2395 struct si_shader_key shader1_key = zeroed;
2396
2397 if (sel->type == PIPE_SHADER_TESS_CTRL) {
2398 shader1_key.as_ls = 1;
2399 } else if (sel->type == PIPE_SHADER_GEOMETRY) {
2400 shader1_key.as_es = 1;
2401 shader1_key.as_ngg = key->as_ngg; /* for Wave32 vs Wave64 */
2402 } else {
2403 assert(0);
2404 }
2405
2406 simple_mtx_lock(&previous_stage_sel->mutex);
2407 ok = si_check_missing_main_part(sscreen,
2408 previous_stage_sel,
2409 compiler_state, &shader1_key);
2410 simple_mtx_unlock(&previous_stage_sel->mutex);
2411 }
2412
2413 if (ok) {
2414 ok = si_check_missing_main_part(sscreen, sel,
2415 compiler_state, key);
2416 }
2417
2418 if (!ok) {
2419 FREE(shader);
2420 simple_mtx_unlock(&sel->mutex);
2421 return -ENOMEM; /* skip the draw call */
2422 }
2423 }
2424
2425 /* Keep the reference to the 1st shader of merged shaders, so that
2426 * Gallium can't destroy it before we destroy the 2nd shader.
2427 *
2428 * Set sctx = NULL, because it's unused if we're not releasing
2429 * the shader, and we don't have any sctx here.
2430 */
2431 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2432 previous_stage_sel);
2433
2434 /* Monolithic-only shaders don't make a distinction between optimized
2435 * and unoptimized. */
2436 shader->is_monolithic =
2437 is_pure_monolithic ||
2438 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2439
2440 /* The prim discard CS is always optimized. */
2441 shader->is_optimized =
2442 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2443 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2444
2445 /* If it's an optimized shader, compile it asynchronously. */
2446 if (shader->is_optimized && thread_index < 0) {
2447 /* Compile it asynchronously. */
2448 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2449 shader, &shader->ready,
2450 si_build_shader_variant_low_priority, NULL,
2451 0);
2452
2453 /* Add only after the ready fence was reset, to guard against a
2454 * race with si_bind_XX_shader. */
2455 if (!sel->last_variant) {
2456 sel->first_variant = shader;
2457 sel->last_variant = shader;
2458 } else {
2459 sel->last_variant->next_variant = shader;
2460 sel->last_variant = shader;
2461 }
2462
2463 /* Use the default (unoptimized) shader for now. */
2464 memset(&key->opt, 0, sizeof(key->opt));
2465 simple_mtx_unlock(&sel->mutex);
2466
2467 if (sscreen->options.sync_compile)
2468 util_queue_fence_wait(&shader->ready);
2469
2470 if (optimized_or_none)
2471 return -1;
2472 goto again;
2473 }
2474
2475 /* Reset the fence before adding to the variant list. */
2476 util_queue_fence_reset(&shader->ready);
2477
2478 if (!sel->last_variant) {
2479 sel->first_variant = shader;
2480 sel->last_variant = shader;
2481 } else {
2482 sel->last_variant->next_variant = shader;
2483 sel->last_variant = shader;
2484 }
2485
2486 simple_mtx_unlock(&sel->mutex);
2487
2488 assert(!shader->is_optimized);
2489 si_build_shader_variant(shader, thread_index, false);
2490
2491 util_queue_fence_signal(&shader->ready);
2492
2493 if (!shader->compilation_failed)
2494 state->current = shader;
2495
2496 return shader->compilation_failed ? -1 : 0;
2497 }
2498
2499 static int si_shader_select(struct pipe_context *ctx,
2500 struct si_shader_ctx_state *state,
2501 union si_vgt_stages_key stages_key,
2502 struct si_compiler_ctx_state *compiler_state)
2503 {
2504 struct si_context *sctx = (struct si_context *)ctx;
2505 struct si_shader_key key;
2506
2507 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2508 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2509 &key, -1, false);
2510 }
2511
2512 static void si_parse_next_shader_property(const struct si_shader_info *info,
2513 bool streamout,
2514 struct si_shader_key *key)
2515 {
2516 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2517
2518 switch (info->processor) {
2519 case PIPE_SHADER_VERTEX:
2520 switch (next_shader) {
2521 case PIPE_SHADER_GEOMETRY:
2522 key->as_es = 1;
2523 break;
2524 case PIPE_SHADER_TESS_CTRL:
2525 case PIPE_SHADER_TESS_EVAL:
2526 key->as_ls = 1;
2527 break;
2528 default:
2529 /* If POSITION isn't written, it can only be a HW VS
2530 * if streamout is used. If streamout isn't used,
2531 * assume that it's a HW LS. (the next shader is TCS)
2532 * This heuristic is needed for separate shader objects.
2533 */
2534 if (!info->writes_position && !streamout)
2535 key->as_ls = 1;
2536 }
2537 break;
2538
2539 case PIPE_SHADER_TESS_EVAL:
2540 if (next_shader == PIPE_SHADER_GEOMETRY ||
2541 !info->writes_position)
2542 key->as_es = 1;
2543 break;
2544 }
2545 }
2546
2547 /**
2548 * Compile the main shader part or the monolithic shader as part of
2549 * si_shader_selector initialization. Since it can be done asynchronously,
2550 * there is no way to report compile failures to applications.
2551 */
2552 static void si_init_shader_selector_async(void *job, int thread_index)
2553 {
2554 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2555 struct si_screen *sscreen = sel->screen;
2556 struct ac_llvm_compiler *compiler;
2557 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2558
2559 assert(!debug->debug_message || debug->async);
2560 assert(thread_index >= 0);
2561 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2562 compiler = &sscreen->compiler[thread_index];
2563
2564 if (!compiler->passes)
2565 si_init_compiler(sscreen, compiler);
2566
2567 /* Serialize NIR to save memory. Monolithic shader variants
2568 * have to deserialize NIR before compilation.
2569 */
2570 if (sel->nir) {
2571 struct blob blob;
2572 size_t size;
2573
2574 blob_init(&blob);
2575 /* true = remove optional debugging data to increase
2576 * the likehood of getting more shader cache hits.
2577 * It also drops variable names, so we'll save more memory.
2578 */
2579 nir_serialize(&blob, sel->nir, true);
2580 blob_finish_get_buffer(&blob, &sel->nir_binary, &size);
2581 sel->nir_size = size;
2582 }
2583
2584 /* Compile the main shader part for use with a prolog and/or epilog.
2585 * If this fails, the driver will try to compile a monolithic shader
2586 * on demand.
2587 */
2588 if (!sscreen->use_monolithic_shaders) {
2589 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2590 unsigned char ir_sha1_cache_key[20];
2591
2592 if (!shader) {
2593 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2594 return;
2595 }
2596
2597 /* We can leave the fence signaled because use of the default
2598 * main part is guarded by the selector's ready fence. */
2599 util_queue_fence_init(&shader->ready);
2600
2601 shader->selector = sel;
2602 shader->is_monolithic = false;
2603 si_parse_next_shader_property(&sel->info,
2604 sel->so.num_outputs != 0,
2605 &shader->key);
2606
2607 if (sscreen->use_ngg &&
2608 (!sel->so.num_outputs || sscreen->use_ngg_streamout) &&
2609 ((sel->type == PIPE_SHADER_VERTEX && !shader->key.as_ls) ||
2610 sel->type == PIPE_SHADER_TESS_EVAL ||
2611 sel->type == PIPE_SHADER_GEOMETRY))
2612 shader->key.as_ngg = 1;
2613
2614 if (sel->nir) {
2615 si_get_ir_cache_key(sel, shader->key.as_ngg,
2616 shader->key.as_es, ir_sha1_cache_key);
2617 }
2618
2619 /* Try to load the shader from the shader cache. */
2620 simple_mtx_lock(&sscreen->shader_cache_mutex);
2621
2622 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
2623 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2624 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2625 } else {
2626 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2627
2628 /* Compile the shader if it hasn't been loaded from the cache. */
2629 if (!si_compile_shader(sscreen, compiler, shader, debug)) {
2630 FREE(shader);
2631 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2632 return;
2633 }
2634
2635 simple_mtx_lock(&sscreen->shader_cache_mutex);
2636 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
2637 shader, true);
2638 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2639 }
2640
2641 *si_get_main_shader_part(sel, &shader->key) = shader;
2642
2643 /* Unset "outputs_written" flags for outputs converted to
2644 * DEFAULT_VAL, so that later inter-shader optimizations don't
2645 * try to eliminate outputs that don't exist in the final
2646 * shader.
2647 *
2648 * This is only done if non-monolithic shaders are enabled.
2649 */
2650 if ((sel->type == PIPE_SHADER_VERTEX ||
2651 sel->type == PIPE_SHADER_TESS_EVAL) &&
2652 !shader->key.as_ls &&
2653 !shader->key.as_es) {
2654 unsigned i;
2655
2656 for (i = 0; i < sel->info.num_outputs; i++) {
2657 unsigned offset = shader->info.vs_output_param_offset[i];
2658
2659 if (offset <= AC_EXP_PARAM_OFFSET_31)
2660 continue;
2661
2662 unsigned name = sel->info.output_semantic_name[i];
2663 unsigned index = sel->info.output_semantic_index[i];
2664 unsigned id;
2665
2666 switch (name) {
2667 case TGSI_SEMANTIC_GENERIC:
2668 /* don't process indices the function can't handle */
2669 if (index >= SI_MAX_IO_GENERIC)
2670 break;
2671 /* fall through */
2672 default:
2673 id = si_shader_io_get_unique_index(name, index, true);
2674 sel->outputs_written_before_ps &= ~(1ull << id);
2675 break;
2676 case TGSI_SEMANTIC_POSITION: /* ignore these */
2677 case TGSI_SEMANTIC_PSIZE:
2678 case TGSI_SEMANTIC_CLIPVERTEX:
2679 case TGSI_SEMANTIC_EDGEFLAG:
2680 break;
2681 }
2682 }
2683 }
2684 }
2685
2686 /* The GS copy shader is always pre-compiled. */
2687 if (sel->type == PIPE_SHADER_GEOMETRY &&
2688 (!sscreen->use_ngg ||
2689 !sscreen->use_ngg_streamout || /* also for PRIMITIVES_GENERATED */
2690 sel->tess_turns_off_ngg)) {
2691 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2692 if (!sel->gs_copy_shader) {
2693 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2694 return;
2695 }
2696
2697 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2698 }
2699
2700 /* Free NIR. We only keep serialized NIR after this point. */
2701 if (sel->nir) {
2702 ralloc_free(sel->nir);
2703 sel->nir = NULL;
2704 }
2705 }
2706
2707 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2708 struct util_queue_fence *ready_fence,
2709 struct si_compiler_ctx_state *compiler_ctx_state,
2710 void *job, util_queue_execute_func execute)
2711 {
2712 util_queue_fence_init(ready_fence);
2713
2714 struct util_async_debug_callback async_debug;
2715 bool debug =
2716 (sctx->debug.debug_message && !sctx->debug.async) ||
2717 sctx->is_debug ||
2718 si_can_dump_shader(sctx->screen, processor);
2719
2720 if (debug) {
2721 u_async_debug_init(&async_debug);
2722 compiler_ctx_state->debug = async_debug.base;
2723 }
2724
2725 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2726 ready_fence, execute, NULL, 0);
2727
2728 if (debug) {
2729 util_queue_fence_wait(ready_fence);
2730 u_async_debug_drain(&async_debug, &sctx->debug);
2731 u_async_debug_cleanup(&async_debug);
2732 }
2733
2734 if (sctx->screen->options.sync_compile)
2735 util_queue_fence_wait(ready_fence);
2736 }
2737
2738 /* Return descriptor slot usage masks from the given shader info. */
2739 void si_get_active_slot_masks(const struct si_shader_info *info,
2740 uint32_t *const_and_shader_buffers,
2741 uint64_t *samplers_and_images)
2742 {
2743 unsigned start, num_shaderbufs, num_constbufs, num_images, num_msaa_images, num_samplers;
2744
2745 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2746 num_constbufs = util_last_bit(info->const_buffers_declared);
2747 /* two 8-byte images share one 16-byte slot */
2748 num_images = align(util_last_bit(info->images_declared), 2);
2749 num_msaa_images = align(util_last_bit(info->msaa_images_declared), 2);
2750 num_samplers = util_last_bit(info->samplers_declared);
2751
2752 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2753 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2754 *const_and_shader_buffers =
2755 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2756
2757 /* The layout is:
2758 * - fmask[last] ... fmask[0] go to [15-last .. 15]
2759 * - image[last] ... image[0] go to [31-last .. 31]
2760 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
2761 *
2762 * FMASKs for images are placed separately, because MSAA images are rare,
2763 * and so we can benefit from a better cache hit rate if we keep image
2764 * descriptors together.
2765 */
2766 if (num_msaa_images)
2767 num_images = SI_NUM_IMAGES + num_msaa_images; /* add FMASK descriptors */
2768
2769 start = si_get_image_slot(num_images - 1) / 2;
2770 *samplers_and_images =
2771 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2772 }
2773
2774 static void *si_create_shader_selector(struct pipe_context *ctx,
2775 const struct pipe_shader_state *state)
2776 {
2777 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2778 struct si_context *sctx = (struct si_context*)ctx;
2779 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2780 int i;
2781
2782 if (!sel)
2783 return NULL;
2784
2785 sel->screen = sscreen;
2786 sel->compiler_ctx_state.debug = sctx->debug;
2787 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2788
2789 sel->so = state->stream_output;
2790
2791 if (state->type == PIPE_SHADER_IR_TGSI) {
2792 sel->nir = tgsi_to_nir(state->tokens, ctx->screen);
2793 } else {
2794 assert(state->type == PIPE_SHADER_IR_NIR);
2795 sel->nir = state->ir.nir;
2796 }
2797
2798 si_nir_scan_shader(sel->nir, &sel->info);
2799 si_nir_adjust_driver_locations(sel->nir);
2800
2801 sel->type = sel->info.processor;
2802 p_atomic_inc(&sscreen->num_shaders_created);
2803 si_get_active_slot_masks(&sel->info,
2804 &sel->active_const_and_shader_buffers,
2805 &sel->active_samplers_and_images);
2806
2807 /* Record which streamout buffers are enabled. */
2808 for (i = 0; i < sel->so.num_outputs; i++) {
2809 sel->enabled_streamout_buffer_mask |=
2810 (1 << sel->so.output[i].output_buffer) <<
2811 (sel->so.output[i].stream * 4);
2812 }
2813
2814 sel->num_vs_inputs = sel->type == PIPE_SHADER_VERTEX &&
2815 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] ?
2816 sel->info.num_inputs : 0;
2817 sel->num_vbos_in_user_sgprs =
2818 MIN2(sel->num_vs_inputs, sscreen->num_vbos_in_user_sgprs);
2819
2820 /* The prolog is a no-op if there are no inputs. */
2821 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2822 sel->info.num_inputs &&
2823 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
2824
2825 sel->force_correct_derivs_after_kill =
2826 sel->type == PIPE_SHADER_FRAGMENT &&
2827 sel->info.uses_derivatives &&
2828 sel->info.uses_kill &&
2829 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2830
2831 sel->prim_discard_cs_allowed =
2832 sel->type == PIPE_SHADER_VERTEX &&
2833 !sel->info.uses_bindless_images &&
2834 !sel->info.uses_bindless_samplers &&
2835 !sel->info.writes_memory &&
2836 !sel->info.writes_viewport_index &&
2837 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2838 !sel->so.num_outputs;
2839
2840 switch (sel->type) {
2841 case PIPE_SHADER_GEOMETRY:
2842 sel->gs_output_prim =
2843 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2844
2845 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2846 sel->rast_prim = sel->gs_output_prim;
2847 if (util_rast_prim_is_triangles(sel->rast_prim))
2848 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2849
2850 sel->gs_max_out_vertices =
2851 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2852 sel->gs_num_invocations =
2853 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2854 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2855 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2856 sel->gs_max_out_vertices;
2857
2858 sel->max_gs_stream = 0;
2859 for (i = 0; i < sel->so.num_outputs; i++)
2860 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2861 sel->so.output[i].stream);
2862
2863 sel->gs_input_verts_per_prim =
2864 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2865
2866 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2867 sel->tess_turns_off_ngg =
2868 sscreen->info.chip_class == GFX10 &&
2869 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2870 break;
2871
2872 case PIPE_SHADER_TESS_CTRL:
2873 /* Always reserve space for these. */
2874 sel->patch_outputs_written |=
2875 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2876 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2877 /* fall through */
2878 case PIPE_SHADER_VERTEX:
2879 case PIPE_SHADER_TESS_EVAL:
2880 for (i = 0; i < sel->info.num_outputs; i++) {
2881 unsigned name = sel->info.output_semantic_name[i];
2882 unsigned index = sel->info.output_semantic_index[i];
2883
2884 switch (name) {
2885 case TGSI_SEMANTIC_TESSINNER:
2886 case TGSI_SEMANTIC_TESSOUTER:
2887 case TGSI_SEMANTIC_PATCH:
2888 sel->patch_outputs_written |=
2889 1ull << si_shader_io_get_unique_index_patch(name, index);
2890 break;
2891
2892 case TGSI_SEMANTIC_GENERIC:
2893 /* don't process indices the function can't handle */
2894 if (index >= SI_MAX_IO_GENERIC)
2895 break;
2896 /* fall through */
2897 default:
2898 sel->outputs_written |=
2899 1ull << si_shader_io_get_unique_index(name, index, false);
2900 sel->outputs_written_before_ps |=
2901 1ull << si_shader_io_get_unique_index(name, index, true);
2902 break;
2903 case TGSI_SEMANTIC_EDGEFLAG:
2904 break;
2905 }
2906 }
2907 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2908 sel->lshs_vertex_stride = sel->esgs_itemsize;
2909
2910 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2911 * will start on a different bank. (except for the maximum 32*16).
2912 */
2913 if (sel->lshs_vertex_stride < 32*16)
2914 sel->lshs_vertex_stride += 4;
2915
2916 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2917 * conflicts, i.e. each vertex will start at a different bank.
2918 */
2919 if (sctx->chip_class >= GFX9)
2920 sel->esgs_itemsize += 4;
2921
2922 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2923
2924 /* Only for TES: */
2925 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2926 sel->rast_prim = PIPE_PRIM_POINTS;
2927 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2928 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2929 else
2930 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2931 break;
2932
2933 case PIPE_SHADER_FRAGMENT:
2934 for (i = 0; i < sel->info.num_inputs; i++) {
2935 unsigned name = sel->info.input_semantic_name[i];
2936 unsigned index = sel->info.input_semantic_index[i];
2937
2938 switch (name) {
2939 case TGSI_SEMANTIC_GENERIC:
2940 /* don't process indices the function can't handle */
2941 if (index >= SI_MAX_IO_GENERIC)
2942 break;
2943 /* fall through */
2944 default:
2945 sel->inputs_read |=
2946 1ull << si_shader_io_get_unique_index(name, index, true);
2947 break;
2948 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2949 break;
2950 }
2951 }
2952
2953 for (i = 0; i < 8; i++)
2954 if (sel->info.colors_written & (1 << i))
2955 sel->colors_written_4bit |= 0xf << (4 * i);
2956
2957 for (i = 0; i < sel->info.num_inputs; i++) {
2958 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2959 int index = sel->info.input_semantic_index[i];
2960 sel->color_attr_index[index] = i;
2961 }
2962 }
2963 break;
2964 default:;
2965 }
2966
2967 sel->ngg_culling_allowed =
2968 sscreen->info.chip_class == GFX10 &&
2969 sscreen->info.has_dedicated_vram &&
2970 sscreen->use_ngg_culling &&
2971 /* Disallow TES by default, because TessMark results are mixed. */
2972 (sel->type == PIPE_SHADER_VERTEX ||
2973 (sscreen->always_use_ngg_culling && sel->type == PIPE_SHADER_TESS_EVAL)) &&
2974 sel->info.writes_position &&
2975 !sel->info.writes_viewport_index && /* cull only against viewport 0 */
2976 !sel->info.writes_memory &&
2977 !sel->so.num_outputs &&
2978 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] &&
2979 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
2980
2981 /* PA_CL_VS_OUT_CNTL */
2982 if (sctx->chip_class <= GFX9)
2983 sel->pa_cl_vs_out_cntl = si_get_vs_out_cntl(sel, false);
2984
2985 sel->clipdist_mask = sel->info.writes_clipvertex ?
2986 SIX_BITS : sel->info.clipdist_writemask;
2987 sel->culldist_mask = sel->info.culldist_writemask <<
2988 sel->info.num_written_clipdistance;
2989
2990 /* DB_SHADER_CONTROL */
2991 sel->db_shader_control =
2992 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2993 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2994 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2995 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2996
2997 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2998 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2999 sel->db_shader_control |=
3000 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3001 break;
3002 case TGSI_FS_DEPTH_LAYOUT_LESS:
3003 sel->db_shader_control |=
3004 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3005 break;
3006 }
3007
3008 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
3009 *
3010 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
3011 * --|-----------|------------|------------|--------------------|-------------------|-------------
3012 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
3013 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
3014 * 2 | false | true | n/a | LateZ | 1 | 0
3015 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
3016 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
3017 *
3018 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
3019 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
3020 *
3021 * Don't use ReZ without profiling !!!
3022 *
3023 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
3024 * shaders.
3025 */
3026 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
3027 /* Cases 3, 4. */
3028 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
3029 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
3030 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
3031 } else if (sel->info.writes_memory) {
3032 /* Case 2. */
3033 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
3034 S_02880C_EXEC_ON_HIER_FAIL(1);
3035 } else {
3036 /* Case 1. */
3037 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3038 }
3039
3040 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
3041 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
3042
3043 (void) simple_mtx_init(&sel->mutex, mtx_plain);
3044
3045 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
3046 &sel->compiler_ctx_state, sel,
3047 si_init_shader_selector_async);
3048 return sel;
3049 }
3050
3051 static void *si_create_shader(struct pipe_context *ctx,
3052 const struct pipe_shader_state *state)
3053 {
3054 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
3055
3056 return util_live_shader_cache_get(ctx, &sscreen->live_shader_cache, state);
3057 }
3058
3059 static void si_update_streamout_state(struct si_context *sctx)
3060 {
3061 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
3062
3063 if (!shader_with_so)
3064 return;
3065
3066 sctx->streamout.enabled_stream_buffers_mask =
3067 shader_with_so->enabled_streamout_buffer_mask;
3068 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
3069 }
3070
3071 static void si_update_clip_regs(struct si_context *sctx,
3072 struct si_shader_selector *old_hw_vs,
3073 struct si_shader *old_hw_vs_variant,
3074 struct si_shader_selector *next_hw_vs,
3075 struct si_shader *next_hw_vs_variant)
3076 {
3077 if (next_hw_vs &&
3078 (!old_hw_vs ||
3079 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
3080 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
3081 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
3082 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
3083 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
3084 !old_hw_vs_variant ||
3085 !next_hw_vs_variant ||
3086 old_hw_vs_variant->key.opt.clip_disable !=
3087 next_hw_vs_variant->key.opt.clip_disable))
3088 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3089 }
3090
3091 static void si_update_common_shader_state(struct si_context *sctx)
3092 {
3093 sctx->uses_bindless_samplers =
3094 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
3095 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
3096 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
3097 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
3098 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
3099 sctx->uses_bindless_images =
3100 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
3101 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
3102 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
3103 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
3104 si_shader_uses_bindless_images(sctx->tes_shader.cso);
3105 sctx->do_update_shaders = true;
3106 }
3107
3108 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
3109 {
3110 struct si_context *sctx = (struct si_context *)ctx;
3111 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3112 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3113 struct si_shader_selector *sel = state;
3114
3115 if (sctx->vs_shader.cso == sel)
3116 return;
3117
3118 sctx->vs_shader.cso = sel;
3119 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
3120 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] : 0;
3121
3122 if (si_update_ngg(sctx))
3123 si_shader_change_notify(sctx);
3124
3125 si_update_common_shader_state(sctx);
3126 si_update_vs_viewport_state(sctx);
3127 si_set_active_descriptors_for_shader(sctx, sel);
3128 si_update_streamout_state(sctx);
3129 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3130 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3131 }
3132
3133 static void si_update_tess_uses_prim_id(struct si_context *sctx)
3134 {
3135 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
3136 (sctx->tes_shader.cso &&
3137 sctx->tes_shader.cso->info.uses_primid) ||
3138 (sctx->tcs_shader.cso &&
3139 sctx->tcs_shader.cso->info.uses_primid) ||
3140 (sctx->gs_shader.cso &&
3141 sctx->gs_shader.cso->info.uses_primid) ||
3142 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
3143 sctx->ps_shader.cso->info.uses_primid);
3144 }
3145
3146 bool si_update_ngg(struct si_context *sctx)
3147 {
3148 if (!sctx->screen->use_ngg) {
3149 assert(!sctx->ngg);
3150 return false;
3151 }
3152
3153 bool new_ngg = true;
3154
3155 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
3156 sctx->gs_shader.cso->tess_turns_off_ngg) {
3157 new_ngg = false;
3158 } else if (!sctx->screen->use_ngg_streamout) {
3159 struct si_shader_selector *last = si_get_vs(sctx)->cso;
3160
3161 if ((last && last->so.num_outputs) ||
3162 sctx->streamout.prims_gen_query_enabled)
3163 new_ngg = false;
3164 }
3165
3166 if (new_ngg != sctx->ngg) {
3167 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3168 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3169 * pointers are set.
3170 */
3171 if ((sctx->family == CHIP_NAVI10 ||
3172 sctx->family == CHIP_NAVI12 ||
3173 sctx->family == CHIP_NAVI14) &&
3174 !new_ngg)
3175 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
3176
3177 sctx->ngg = new_ngg;
3178 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3179 return true;
3180 }
3181 return false;
3182 }
3183
3184 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3185 {
3186 struct si_context *sctx = (struct si_context *)ctx;
3187 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3188 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3189 struct si_shader_selector *sel = state;
3190 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3191 bool ngg_changed;
3192
3193 if (sctx->gs_shader.cso == sel)
3194 return;
3195
3196 sctx->gs_shader.cso = sel;
3197 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3198 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3199
3200 si_update_common_shader_state(sctx);
3201 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3202
3203 ngg_changed = si_update_ngg(sctx);
3204 if (ngg_changed || enable_changed)
3205 si_shader_change_notify(sctx);
3206 if (enable_changed) {
3207 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3208 si_update_tess_uses_prim_id(sctx);
3209 }
3210 si_update_vs_viewport_state(sctx);
3211 si_set_active_descriptors_for_shader(sctx, sel);
3212 si_update_streamout_state(sctx);
3213 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3214 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3215 }
3216
3217 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3218 {
3219 struct si_context *sctx = (struct si_context *)ctx;
3220 struct si_shader_selector *sel = state;
3221 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3222
3223 if (sctx->tcs_shader.cso == sel)
3224 return;
3225
3226 sctx->tcs_shader.cso = sel;
3227 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3228 si_update_tess_uses_prim_id(sctx);
3229
3230 si_update_common_shader_state(sctx);
3231
3232 if (enable_changed)
3233 sctx->last_tcs = NULL; /* invalidate derived tess state */
3234
3235 si_set_active_descriptors_for_shader(sctx, sel);
3236 }
3237
3238 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3239 {
3240 struct si_context *sctx = (struct si_context *)ctx;
3241 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3242 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3243 struct si_shader_selector *sel = state;
3244 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3245
3246 if (sctx->tes_shader.cso == sel)
3247 return;
3248
3249 sctx->tes_shader.cso = sel;
3250 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3251 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3252 si_update_tess_uses_prim_id(sctx);
3253
3254 si_update_common_shader_state(sctx);
3255 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3256
3257 bool ngg_changed = si_update_ngg(sctx);
3258 if (ngg_changed || enable_changed)
3259 si_shader_change_notify(sctx);
3260 if (enable_changed)
3261 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3262 si_update_vs_viewport_state(sctx);
3263 si_set_active_descriptors_for_shader(sctx, sel);
3264 si_update_streamout_state(sctx);
3265 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3266 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3267 }
3268
3269 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3270 {
3271 struct si_context *sctx = (struct si_context *)ctx;
3272 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3273 struct si_shader_selector *sel = state;
3274
3275 /* skip if supplied shader is one already in use */
3276 if (old_sel == sel)
3277 return;
3278
3279 sctx->ps_shader.cso = sel;
3280 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3281
3282 si_update_common_shader_state(sctx);
3283 if (sel) {
3284 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3285 si_update_tess_uses_prim_id(sctx);
3286
3287 if (!old_sel ||
3288 old_sel->info.colors_written != sel->info.colors_written)
3289 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3290
3291 if (sctx->screen->has_out_of_order_rast &&
3292 (!old_sel ||
3293 old_sel->info.writes_memory != sel->info.writes_memory ||
3294 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3295 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3296 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3297 }
3298 si_set_active_descriptors_for_shader(sctx, sel);
3299 si_update_ps_colorbuf0_slot(sctx);
3300 }
3301
3302 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3303 {
3304 if (shader->is_optimized) {
3305 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3306 &shader->ready);
3307 }
3308
3309 util_queue_fence_destroy(&shader->ready);
3310
3311 if (shader->pm4) {
3312 /* If destroyed shaders were not unbound, the next compiled
3313 * shader variant could get the same pointer address and so
3314 * binding it to the same shader stage would be considered
3315 * a no-op, causing random behavior.
3316 */
3317 switch (shader->selector->type) {
3318 case PIPE_SHADER_VERTEX:
3319 if (shader->key.as_ls) {
3320 assert(sctx->chip_class <= GFX8);
3321 si_pm4_delete_state(sctx, ls, shader->pm4);
3322 } else if (shader->key.as_es) {
3323 assert(sctx->chip_class <= GFX8);
3324 si_pm4_delete_state(sctx, es, shader->pm4);
3325 } else if (shader->key.as_ngg) {
3326 si_pm4_delete_state(sctx, gs, shader->pm4);
3327 } else {
3328 si_pm4_delete_state(sctx, vs, shader->pm4);
3329 }
3330 break;
3331 case PIPE_SHADER_TESS_CTRL:
3332 si_pm4_delete_state(sctx, hs, shader->pm4);
3333 break;
3334 case PIPE_SHADER_TESS_EVAL:
3335 if (shader->key.as_es) {
3336 assert(sctx->chip_class <= GFX8);
3337 si_pm4_delete_state(sctx, es, shader->pm4);
3338 } else if (shader->key.as_ngg) {
3339 si_pm4_delete_state(sctx, gs, shader->pm4);
3340 } else {
3341 si_pm4_delete_state(sctx, vs, shader->pm4);
3342 }
3343 break;
3344 case PIPE_SHADER_GEOMETRY:
3345 if (shader->is_gs_copy_shader)
3346 si_pm4_delete_state(sctx, vs, shader->pm4);
3347 else
3348 si_pm4_delete_state(sctx, gs, shader->pm4);
3349 break;
3350 case PIPE_SHADER_FRAGMENT:
3351 si_pm4_delete_state(sctx, ps, shader->pm4);
3352 break;
3353 default:;
3354 }
3355 }
3356
3357 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3358 si_shader_destroy(shader);
3359 free(shader);
3360 }
3361
3362 static void si_destroy_shader_selector(struct pipe_context *ctx, void *cso)
3363 {
3364 struct si_context *sctx = (struct si_context*)ctx;
3365 struct si_shader_selector *sel = (struct si_shader_selector *)cso;
3366 struct si_shader *p = sel->first_variant, *c;
3367 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3368 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3369 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3370 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3371 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3372 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3373 };
3374
3375 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3376
3377 if (current_shader[sel->type]->cso == sel) {
3378 current_shader[sel->type]->cso = NULL;
3379 current_shader[sel->type]->current = NULL;
3380 }
3381
3382 while (p) {
3383 c = p->next_variant;
3384 si_delete_shader(sctx, p);
3385 p = c;
3386 }
3387
3388 if (sel->main_shader_part)
3389 si_delete_shader(sctx, sel->main_shader_part);
3390 if (sel->main_shader_part_ls)
3391 si_delete_shader(sctx, sel->main_shader_part_ls);
3392 if (sel->main_shader_part_es)
3393 si_delete_shader(sctx, sel->main_shader_part_es);
3394 if (sel->main_shader_part_ngg)
3395 si_delete_shader(sctx, sel->main_shader_part_ngg);
3396 if (sel->gs_copy_shader)
3397 si_delete_shader(sctx, sel->gs_copy_shader);
3398
3399 util_queue_fence_destroy(&sel->ready);
3400 simple_mtx_destroy(&sel->mutex);
3401 ralloc_free(sel->nir);
3402 free(sel->nir_binary);
3403 free(sel);
3404 }
3405
3406 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3407 {
3408 struct si_context *sctx = (struct si_context *)ctx;
3409 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3410
3411 si_shader_selector_reference(sctx, &sel, NULL);
3412 }
3413
3414 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3415 struct si_shader *vs, unsigned name,
3416 unsigned index, unsigned interpolate)
3417 {
3418 struct si_shader_info *vsinfo = &vs->selector->info;
3419 unsigned j, offset, ps_input_cntl = 0;
3420
3421 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3422 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3423 name == TGSI_SEMANTIC_PRIMID)
3424 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3425
3426 if (name == TGSI_SEMANTIC_PCOORD ||
3427 (name == TGSI_SEMANTIC_TEXCOORD &&
3428 sctx->sprite_coord_enable & (1 << index))) {
3429 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3430 }
3431
3432 for (j = 0; j < vsinfo->num_outputs; j++) {
3433 if (name == vsinfo->output_semantic_name[j] &&
3434 index == vsinfo->output_semantic_index[j]) {
3435 offset = vs->info.vs_output_param_offset[j];
3436
3437 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3438 /* The input is loaded from parameter memory. */
3439 ps_input_cntl |= S_028644_OFFSET(offset);
3440 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3441 if (offset == AC_EXP_PARAM_UNDEFINED) {
3442 /* This can happen with depth-only rendering. */
3443 offset = 0;
3444 } else {
3445 /* The input is a DEFAULT_VAL constant. */
3446 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3447 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3448 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3449 }
3450
3451 ps_input_cntl = S_028644_OFFSET(0x20) |
3452 S_028644_DEFAULT_VAL(offset);
3453 }
3454 break;
3455 }
3456 }
3457
3458 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3459 /* PrimID is written after the last output when HW VS is used. */
3460 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3461 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3462 /* No corresponding output found, load defaults into input.
3463 * Don't set any other bits.
3464 * (FLAT_SHADE=1 completely changes behavior) */
3465 ps_input_cntl = S_028644_OFFSET(0x20);
3466 /* D3D 9 behaviour. GL is undefined */
3467 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3468 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3469 }
3470 return ps_input_cntl;
3471 }
3472
3473 static void si_emit_spi_map(struct si_context *sctx)
3474 {
3475 struct si_shader *ps = sctx->ps_shader.current;
3476 struct si_shader *vs = si_get_vs_state(sctx);
3477 struct si_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3478 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3479 unsigned spi_ps_input_cntl[32];
3480
3481 if (!ps || !ps->selector->info.num_inputs)
3482 return;
3483
3484 num_interp = si_get_ps_num_interp(ps);
3485 assert(num_interp > 0);
3486
3487 for (i = 0; i < psinfo->num_inputs; i++) {
3488 unsigned name = psinfo->input_semantic_name[i];
3489 unsigned index = psinfo->input_semantic_index[i];
3490 unsigned interpolate = psinfo->input_interpolate[i];
3491
3492 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3493 index, interpolate);
3494
3495 if (name == TGSI_SEMANTIC_COLOR) {
3496 assert(index < ARRAY_SIZE(bcol_interp));
3497 bcol_interp[index] = interpolate;
3498 }
3499 }
3500
3501 if (ps->key.part.ps.prolog.color_two_side) {
3502 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3503
3504 for (i = 0; i < 2; i++) {
3505 if (!(psinfo->colors_read & (0xf << (i * 4))))
3506 continue;
3507
3508 spi_ps_input_cntl[num_written++] =
3509 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3510
3511 }
3512 }
3513 assert(num_interp == num_written);
3514
3515 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3516 /* Dota 2: Only ~16% of SPI map updates set different values. */
3517 /* Talos: Only ~9% of SPI map updates set different values. */
3518 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3519 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3520 spi_ps_input_cntl,
3521 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3522
3523 if (initial_cdw != sctx->gfx_cs->current.cdw)
3524 sctx->context_roll = true;
3525 }
3526
3527 /**
3528 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3529 */
3530 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3531 {
3532 if (sctx->init_config_has_vgt_flush)
3533 return;
3534
3535 /* Done by Vulkan before VGT_FLUSH. */
3536 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3537 si_pm4_cmd_add(sctx->init_config,
3538 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3539 si_pm4_cmd_end(sctx->init_config, false);
3540
3541 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3542 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3543 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3544 si_pm4_cmd_end(sctx->init_config, false);
3545 sctx->init_config_has_vgt_flush = true;
3546 }
3547
3548 /* Initialize state related to ESGS / GSVS ring buffers */
3549 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3550 {
3551 struct si_shader_selector *es =
3552 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3553 struct si_shader_selector *gs = sctx->gs_shader.cso;
3554 struct si_pm4_state *pm4;
3555
3556 /* Chip constants. */
3557 unsigned num_se = sctx->screen->info.max_se;
3558 unsigned wave_size = 64;
3559 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3560 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3561 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3562 */
3563 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3564 unsigned alignment = 256 * num_se;
3565 /* The maximum size is 63.999 MB per SE. */
3566 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3567
3568 /* Calculate the minimum size. */
3569 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3570 wave_size, alignment);
3571
3572 /* These are recommended sizes, not minimum sizes. */
3573 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3574 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3575 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3576 gs->max_gsvs_emit_size;
3577
3578 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3579 esgs_ring_size = align(esgs_ring_size, alignment);
3580 gsvs_ring_size = align(gsvs_ring_size, alignment);
3581
3582 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3583 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3584
3585 /* Some rings don't have to be allocated if shaders don't use them.
3586 * (e.g. no varyings between ES and GS or GS and VS)
3587 *
3588 * GFX9 doesn't have the ESGS ring.
3589 */
3590 bool update_esgs = sctx->chip_class <= GFX8 &&
3591 esgs_ring_size &&
3592 (!sctx->esgs_ring ||
3593 sctx->esgs_ring->width0 < esgs_ring_size);
3594 bool update_gsvs = gsvs_ring_size &&
3595 (!sctx->gsvs_ring ||
3596 sctx->gsvs_ring->width0 < gsvs_ring_size);
3597
3598 if (!update_esgs && !update_gsvs)
3599 return true;
3600
3601 if (update_esgs) {
3602 pipe_resource_reference(&sctx->esgs_ring, NULL);
3603 sctx->esgs_ring =
3604 pipe_aligned_buffer_create(sctx->b.screen,
3605 SI_RESOURCE_FLAG_UNMAPPABLE,
3606 PIPE_USAGE_DEFAULT,
3607 esgs_ring_size,
3608 sctx->screen->info.pte_fragment_size);
3609 if (!sctx->esgs_ring)
3610 return false;
3611 }
3612
3613 if (update_gsvs) {
3614 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3615 sctx->gsvs_ring =
3616 pipe_aligned_buffer_create(sctx->b.screen,
3617 SI_RESOURCE_FLAG_UNMAPPABLE,
3618 PIPE_USAGE_DEFAULT,
3619 gsvs_ring_size,
3620 sctx->screen->info.pte_fragment_size);
3621 if (!sctx->gsvs_ring)
3622 return false;
3623 }
3624
3625 /* Create the "init_config_gs_rings" state. */
3626 pm4 = CALLOC_STRUCT(si_pm4_state);
3627 if (!pm4)
3628 return false;
3629
3630 if (sctx->chip_class >= GFX7) {
3631 if (sctx->esgs_ring) {
3632 assert(sctx->chip_class <= GFX8);
3633 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3634 sctx->esgs_ring->width0 / 256);
3635 }
3636 if (sctx->gsvs_ring)
3637 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3638 sctx->gsvs_ring->width0 / 256);
3639 } else {
3640 if (sctx->esgs_ring)
3641 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3642 sctx->esgs_ring->width0 / 256);
3643 if (sctx->gsvs_ring)
3644 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3645 sctx->gsvs_ring->width0 / 256);
3646 }
3647
3648 /* Set the state. */
3649 if (sctx->init_config_gs_rings)
3650 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3651 sctx->init_config_gs_rings = pm4;
3652
3653 if (!sctx->init_config_has_vgt_flush) {
3654 si_init_config_add_vgt_flush(sctx);
3655 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3656 }
3657
3658 /* Flush the context to re-emit both init_config states. */
3659 sctx->initial_gfx_cs_size = 0; /* force flush */
3660 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3661
3662 /* Set ring bindings. */
3663 if (sctx->esgs_ring) {
3664 assert(sctx->chip_class <= GFX8);
3665 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3666 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3667 true, true, 4, 64, 0);
3668 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3669 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3670 false, false, 0, 0, 0);
3671 }
3672 if (sctx->gsvs_ring) {
3673 si_set_ring_buffer(sctx, SI_RING_GSVS,
3674 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3675 false, false, 0, 0, 0);
3676 }
3677
3678 return true;
3679 }
3680
3681 static void si_shader_lock(struct si_shader *shader)
3682 {
3683 simple_mtx_lock(&shader->selector->mutex);
3684 if (shader->previous_stage_sel) {
3685 assert(shader->previous_stage_sel != shader->selector);
3686 simple_mtx_lock(&shader->previous_stage_sel->mutex);
3687 }
3688 }
3689
3690 static void si_shader_unlock(struct si_shader *shader)
3691 {
3692 if (shader->previous_stage_sel)
3693 simple_mtx_unlock(&shader->previous_stage_sel->mutex);
3694 simple_mtx_unlock(&shader->selector->mutex);
3695 }
3696
3697 /**
3698 * @returns 1 if \p sel has been updated to use a new scratch buffer
3699 * 0 if not
3700 * < 0 if there was a failure
3701 */
3702 static int si_update_scratch_buffer(struct si_context *sctx,
3703 struct si_shader *shader)
3704 {
3705 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3706
3707 if (!shader)
3708 return 0;
3709
3710 /* This shader doesn't need a scratch buffer */
3711 if (shader->config.scratch_bytes_per_wave == 0)
3712 return 0;
3713
3714 /* Prevent race conditions when updating:
3715 * - si_shader::scratch_bo
3716 * - si_shader::binary::code
3717 * - si_shader::previous_stage::binary::code.
3718 */
3719 si_shader_lock(shader);
3720
3721 /* This shader is already configured to use the current
3722 * scratch buffer. */
3723 if (shader->scratch_bo == sctx->scratch_buffer) {
3724 si_shader_unlock(shader);
3725 return 0;
3726 }
3727
3728 assert(sctx->scratch_buffer);
3729
3730 /* Replace the shader bo with a new bo that has the relocs applied. */
3731 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3732 si_shader_unlock(shader);
3733 return -1;
3734 }
3735
3736 /* Update the shader state to use the new shader bo. */
3737 si_shader_init_pm4_state(sctx->screen, shader);
3738
3739 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3740
3741 si_shader_unlock(shader);
3742 return 1;
3743 }
3744
3745 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3746 {
3747 return shader ? shader->config.scratch_bytes_per_wave : 0;
3748 }
3749
3750 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3751 {
3752 if (!sctx->tes_shader.cso)
3753 return NULL; /* tessellation disabled */
3754
3755 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3756 sctx->fixed_func_tcs_shader.current;
3757 }
3758
3759 static bool si_update_scratch_relocs(struct si_context *sctx)
3760 {
3761 struct si_shader *tcs = si_get_tcs_current(sctx);
3762 int r;
3763
3764 /* Update the shaders, so that they are using the latest scratch.
3765 * The scratch buffer may have been changed since these shaders were
3766 * last used, so we still need to try to update them, even if they
3767 * require scratch buffers smaller than the current size.
3768 */
3769 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3770 if (r < 0)
3771 return false;
3772 if (r == 1)
3773 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3774
3775 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3776 if (r < 0)
3777 return false;
3778 if (r == 1)
3779 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3780
3781 r = si_update_scratch_buffer(sctx, tcs);
3782 if (r < 0)
3783 return false;
3784 if (r == 1)
3785 si_pm4_bind_state(sctx, hs, tcs->pm4);
3786
3787 /* VS can be bound as LS, ES, or VS. */
3788 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3789 if (r < 0)
3790 return false;
3791 if (r == 1) {
3792 if (sctx->vs_shader.current->key.as_ls)
3793 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3794 else if (sctx->vs_shader.current->key.as_es)
3795 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3796 else if (sctx->vs_shader.current->key.as_ngg)
3797 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3798 else
3799 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3800 }
3801
3802 /* TES can be bound as ES or VS. */
3803 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3804 if (r < 0)
3805 return false;
3806 if (r == 1) {
3807 if (sctx->tes_shader.current->key.as_es)
3808 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3809 else if (sctx->tes_shader.current->key.as_ngg)
3810 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3811 else
3812 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3813 }
3814
3815 return true;
3816 }
3817
3818 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3819 {
3820 /* SPI_TMPRING_SIZE.WAVESIZE must be constant for each scratch buffer.
3821 * There are 2 cases to handle:
3822 *
3823 * - If the current needed size is less than the maximum seen size,
3824 * use the maximum seen size, so that WAVESIZE remains the same.
3825 *
3826 * - If the current needed size is greater than the maximum seen size,
3827 * the scratch buffer is reallocated, so we can increase WAVESIZE.
3828 *
3829 * Shaders that set SCRATCH_EN=0 don't allocate scratch space.
3830 * Otherwise, the number of waves that can use scratch is
3831 * SPI_TMPRING_SIZE.WAVES.
3832 */
3833 unsigned bytes = 0;
3834
3835 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3836 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3837 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3838
3839 if (sctx->tes_shader.cso) {
3840 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3841 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(si_get_tcs_current(sctx)));
3842 }
3843
3844 sctx->max_seen_scratch_bytes_per_wave =
3845 MAX2(sctx->max_seen_scratch_bytes_per_wave, bytes);
3846
3847 unsigned scratch_needed_size =
3848 sctx->max_seen_scratch_bytes_per_wave * sctx->scratch_waves;
3849 unsigned spi_tmpring_size;
3850
3851 if (scratch_needed_size > 0) {
3852 if (!sctx->scratch_buffer ||
3853 scratch_needed_size > sctx->scratch_buffer->b.b.width0) {
3854 /* Create a bigger scratch buffer */
3855 si_resource_reference(&sctx->scratch_buffer, NULL);
3856
3857 sctx->scratch_buffer =
3858 si_aligned_buffer_create(&sctx->screen->b,
3859 SI_RESOURCE_FLAG_UNMAPPABLE,
3860 PIPE_USAGE_DEFAULT,
3861 scratch_needed_size,
3862 sctx->screen->info.pte_fragment_size);
3863 if (!sctx->scratch_buffer)
3864 return false;
3865
3866 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3867 si_context_add_resource_size(sctx,
3868 &sctx->scratch_buffer->b.b);
3869 }
3870
3871 if (!si_update_scratch_relocs(sctx))
3872 return false;
3873 }
3874
3875 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3876 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3877 "scratch size should already be aligned correctly.");
3878
3879 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3880 S_0286E8_WAVESIZE(sctx->max_seen_scratch_bytes_per_wave >> 10);
3881 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3882 sctx->spi_tmpring_size = spi_tmpring_size;
3883 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3884 }
3885 return true;
3886 }
3887
3888 static void si_init_tess_factor_ring(struct si_context *sctx)
3889 {
3890 assert(!sctx->tess_rings);
3891 assert(((sctx->screen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
3892
3893 /* The address must be aligned to 2^19, because the shader only
3894 * receives the high 13 bits.
3895 */
3896 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3897 SI_RESOURCE_FLAG_32BIT,
3898 PIPE_USAGE_DEFAULT,
3899 sctx->screen->tess_offchip_ring_size +
3900 sctx->screen->tess_factor_ring_size,
3901 1 << 19);
3902 if (!sctx->tess_rings)
3903 return;
3904
3905 si_init_config_add_vgt_flush(sctx);
3906
3907 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3908 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3909
3910 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3911 sctx->screen->tess_offchip_ring_size;
3912
3913 /* Append these registers to the init config state. */
3914 if (sctx->chip_class >= GFX7) {
3915 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3916 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3917 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3918 factor_va >> 8);
3919 if (sctx->chip_class >= GFX10)
3920 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3921 S_030984_BASE_HI(factor_va >> 40));
3922 else if (sctx->chip_class == GFX9)
3923 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3924 S_030944_BASE_HI(factor_va >> 40));
3925 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3926 sctx->screen->vgt_hs_offchip_param);
3927 } else {
3928 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3929 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3930 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3931 factor_va >> 8);
3932 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3933 sctx->screen->vgt_hs_offchip_param);
3934 }
3935
3936 /* Flush the context to re-emit the init_config state.
3937 * This is done only once in a lifetime of a context.
3938 */
3939 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3940 sctx->initial_gfx_cs_size = 0; /* force flush */
3941 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3942 }
3943
3944 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3945 union si_vgt_stages_key key)
3946 {
3947 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3948 uint32_t stages = 0;
3949
3950 if (key.u.tess) {
3951 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3952 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3953
3954 if (key.u.gs)
3955 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3956 S_028B54_GS_EN(1);
3957 else if (key.u.ngg)
3958 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3959 else
3960 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3961 } else if (key.u.gs) {
3962 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3963 S_028B54_GS_EN(1);
3964 } else if (key.u.ngg) {
3965 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3966 }
3967
3968 if (key.u.ngg) {
3969 stages |= S_028B54_PRIMGEN_EN(1) |
3970 S_028B54_GS_FAST_LAUNCH(key.u.ngg_gs_fast_launch) |
3971 S_028B54_NGG_WAVE_ID_EN(key.u.streamout) |
3972 S_028B54_PRIMGEN_PASSTHRU_EN(key.u.ngg_passthrough);
3973 } else if (key.u.gs)
3974 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3975
3976 if (screen->info.chip_class >= GFX9)
3977 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3978
3979 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
3980 stages |= S_028B54_HS_W32_EN(1) |
3981 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3982 S_028B54_VS_W32_EN(1);
3983 }
3984
3985 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3986 return pm4;
3987 }
3988
3989 static void si_update_vgt_shader_config(struct si_context *sctx,
3990 union si_vgt_stages_key key)
3991 {
3992 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3993
3994 if (unlikely(!*pm4))
3995 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3996 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3997 }
3998
3999 bool si_update_shaders(struct si_context *sctx)
4000 {
4001 struct pipe_context *ctx = (struct pipe_context*)sctx;
4002 struct si_compiler_ctx_state compiler_state;
4003 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
4004 struct si_shader *old_vs = si_get_vs_state(sctx);
4005 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
4006 struct si_shader *old_ps = sctx->ps_shader.current;
4007 union si_vgt_stages_key key;
4008 unsigned old_spi_shader_col_format =
4009 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
4010 int r;
4011
4012 if (!sctx->compiler.passes)
4013 si_init_compiler(sctx->screen, &sctx->compiler);
4014
4015 compiler_state.compiler = &sctx->compiler;
4016 compiler_state.debug = sctx->debug;
4017 compiler_state.is_debug_context = sctx->is_debug;
4018
4019 key.index = 0;
4020
4021 if (sctx->tes_shader.cso)
4022 key.u.tess = 1;
4023 if (sctx->gs_shader.cso)
4024 key.u.gs = 1;
4025
4026 if (sctx->ngg) {
4027 key.u.ngg = 1;
4028 key.u.streamout = !!si_get_vs(sctx)->cso->so.num_outputs;
4029 }
4030
4031 /* Update TCS and TES. */
4032 if (sctx->tes_shader.cso) {
4033 if (!sctx->tess_rings) {
4034 si_init_tess_factor_ring(sctx);
4035 if (!sctx->tess_rings)
4036 return false;
4037 }
4038
4039 if (sctx->tcs_shader.cso) {
4040 r = si_shader_select(ctx, &sctx->tcs_shader, key,
4041 &compiler_state);
4042 if (r)
4043 return false;
4044 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
4045 } else {
4046 if (!sctx->fixed_func_tcs_shader.cso) {
4047 sctx->fixed_func_tcs_shader.cso =
4048 si_create_fixed_func_tcs(sctx);
4049 if (!sctx->fixed_func_tcs_shader.cso)
4050 return false;
4051 }
4052
4053 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
4054 key, &compiler_state);
4055 if (r)
4056 return false;
4057 si_pm4_bind_state(sctx, hs,
4058 sctx->fixed_func_tcs_shader.current->pm4);
4059 }
4060
4061 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
4062 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
4063 if (r)
4064 return false;
4065
4066 if (sctx->gs_shader.cso) {
4067 /* TES as ES */
4068 assert(sctx->chip_class <= GFX8);
4069 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
4070 } else if (key.u.ngg) {
4071 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
4072 } else {
4073 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
4074 }
4075 }
4076 } else {
4077 if (sctx->chip_class <= GFX8)
4078 si_pm4_bind_state(sctx, ls, NULL);
4079 si_pm4_bind_state(sctx, hs, NULL);
4080 }
4081
4082 /* Update GS. */
4083 if (sctx->gs_shader.cso) {
4084 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
4085 if (r)
4086 return false;
4087 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
4088 if (!key.u.ngg) {
4089 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
4090
4091 if (!si_update_gs_ring_buffers(sctx))
4092 return false;
4093 } else {
4094 si_pm4_bind_state(sctx, vs, NULL);
4095 }
4096 } else {
4097 if (!key.u.ngg) {
4098 si_pm4_bind_state(sctx, gs, NULL);
4099 if (sctx->chip_class <= GFX8)
4100 si_pm4_bind_state(sctx, es, NULL);
4101 }
4102 }
4103
4104 /* Update VS. */
4105 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
4106 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
4107 if (r)
4108 return false;
4109
4110 if (!key.u.tess && !key.u.gs) {
4111 if (key.u.ngg) {
4112 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
4113 si_pm4_bind_state(sctx, vs, NULL);
4114 } else {
4115 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
4116 }
4117 } else if (sctx->tes_shader.cso) {
4118 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
4119 } else {
4120 assert(sctx->gs_shader.cso);
4121 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
4122 }
4123 }
4124
4125 /* This must be done after the shader variant is selected. */
4126 if (sctx->ngg) {
4127 struct si_shader *vs = si_get_vs(sctx)->current;
4128
4129 key.u.ngg_passthrough = gfx10_is_ngg_passthrough(vs);
4130 key.u.ngg_gs_fast_launch = !!(vs->key.opt.ngg_culling &
4131 SI_NGG_CULL_GS_FAST_LAUNCH_ALL);
4132 }
4133
4134 si_update_vgt_shader_config(sctx, key);
4135
4136 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
4137 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
4138
4139 if (sctx->ps_shader.cso) {
4140 unsigned db_shader_control;
4141
4142 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
4143 if (r)
4144 return false;
4145 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
4146
4147 db_shader_control =
4148 sctx->ps_shader.cso->db_shader_control |
4149 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
4150
4151 if (si_pm4_state_changed(sctx, ps) ||
4152 si_pm4_state_changed(sctx, vs) ||
4153 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
4154 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
4155 sctx->flatshade != rs->flatshade) {
4156 sctx->sprite_coord_enable = rs->sprite_coord_enable;
4157 sctx->flatshade = rs->flatshade;
4158 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
4159 }
4160
4161 if (sctx->screen->info.rbplus_allowed &&
4162 si_pm4_state_changed(sctx, ps) &&
4163 (!old_ps ||
4164 old_spi_shader_col_format !=
4165 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
4166 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
4167
4168 if (sctx->ps_db_shader_control != db_shader_control) {
4169 sctx->ps_db_shader_control = db_shader_control;
4170 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4171 if (sctx->screen->dpbb_allowed)
4172 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
4173 }
4174
4175 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
4176 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
4177 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
4178
4179 if (sctx->chip_class == GFX6)
4180 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4181
4182 if (sctx->framebuffer.nr_samples <= 1)
4183 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
4184 }
4185 }
4186
4187 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
4188 si_pm4_state_enabled_and_changed(sctx, hs) ||
4189 si_pm4_state_enabled_and_changed(sctx, es) ||
4190 si_pm4_state_enabled_and_changed(sctx, gs) ||
4191 si_pm4_state_enabled_and_changed(sctx, vs) ||
4192 si_pm4_state_enabled_and_changed(sctx, ps)) {
4193 if (!si_update_spi_tmpring_size(sctx))
4194 return false;
4195 }
4196
4197 if (sctx->chip_class >= GFX7) {
4198 if (si_pm4_state_enabled_and_changed(sctx, ls))
4199 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
4200 else if (!sctx->queued.named.ls)
4201 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
4202
4203 if (si_pm4_state_enabled_and_changed(sctx, hs))
4204 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
4205 else if (!sctx->queued.named.hs)
4206 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
4207
4208 if (si_pm4_state_enabled_and_changed(sctx, es))
4209 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4210 else if (!sctx->queued.named.es)
4211 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4212
4213 if (si_pm4_state_enabled_and_changed(sctx, gs))
4214 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4215 else if (!sctx->queued.named.gs)
4216 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4217
4218 if (si_pm4_state_enabled_and_changed(sctx, vs))
4219 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4220 else if (!sctx->queued.named.vs)
4221 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4222
4223 if (si_pm4_state_enabled_and_changed(sctx, ps))
4224 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4225 else if (!sctx->queued.named.ps)
4226 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4227 }
4228
4229 sctx->do_update_shaders = false;
4230 return true;
4231 }
4232
4233 static void si_emit_scratch_state(struct si_context *sctx)
4234 {
4235 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4236
4237 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4238 sctx->spi_tmpring_size);
4239
4240 if (sctx->scratch_buffer) {
4241 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4242 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4243 RADEON_PRIO_SCRATCH_BUFFER);
4244 }
4245 }
4246
4247 void si_init_screen_live_shader_cache(struct si_screen *sscreen)
4248 {
4249 util_live_shader_cache_init(&sscreen->live_shader_cache,
4250 si_create_shader_selector,
4251 si_destroy_shader_selector);
4252 }
4253
4254 void si_init_shader_functions(struct si_context *sctx)
4255 {
4256 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4257 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4258
4259 sctx->b.create_vs_state = si_create_shader;
4260 sctx->b.create_tcs_state = si_create_shader;
4261 sctx->b.create_tes_state = si_create_shader;
4262 sctx->b.create_gs_state = si_create_shader;
4263 sctx->b.create_fs_state = si_create_shader;
4264
4265 sctx->b.bind_vs_state = si_bind_vs_shader;
4266 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4267 sctx->b.bind_tes_state = si_bind_tes_shader;
4268 sctx->b.bind_gs_state = si_bind_gs_shader;
4269 sctx->b.bind_fs_state = si_bind_ps_shader;
4270
4271 sctx->b.delete_vs_state = si_delete_shader_selector;
4272 sctx->b.delete_tcs_state = si_delete_shader_selector;
4273 sctx->b.delete_tes_state = si_delete_shader_selector;
4274 sctx->b.delete_gs_state = si_delete_shader_selector;
4275 sctx->b.delete_fs_state = si_delete_shader_selector;
4276 }