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radeonsi/gfx10: implement a bug workaround for GE_PC_ALLOC
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
36
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41
42 /* SHADER_CACHE */
43
44 /**
45 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
46 * size as integer.
47 */
48 void *si_get_ir_binary(struct si_shader_selector *sel)
49 {
50 struct blob blob;
51 unsigned ir_size;
52 void *ir_binary;
53
54 if (sel->tokens) {
55 ir_binary = sel->tokens;
56 ir_size = tgsi_num_tokens(sel->tokens) *
57 sizeof(struct tgsi_token);
58 } else {
59 assert(sel->nir);
60
61 blob_init(&blob);
62 nir_serialize(&blob, sel->nir);
63 ir_binary = blob.data;
64 ir_size = blob.size;
65 }
66
67 unsigned size = 4 + ir_size + sizeof(sel->so);
68 char *result = (char*)MALLOC(size);
69 if (!result)
70 return NULL;
71
72 *((uint32_t*)result) = size;
73 memcpy(result + 4, ir_binary, ir_size);
74 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
75
76 if (sel->nir)
77 blob_finish(&blob);
78
79 return result;
80 }
81
82 /** Copy "data" to "ptr" and return the next dword following copied data. */
83 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
84 {
85 /* data may be NULL if size == 0 */
86 if (size)
87 memcpy(ptr, data, size);
88 ptr += DIV_ROUND_UP(size, 4);
89 return ptr;
90 }
91
92 /** Read data from "ptr". Return the next dword following the data. */
93 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
94 {
95 memcpy(data, ptr, size);
96 ptr += DIV_ROUND_UP(size, 4);
97 return ptr;
98 }
99
100 /**
101 * Write the size as uint followed by the data. Return the next dword
102 * following the copied data.
103 */
104 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
105 {
106 *ptr++ = size;
107 return write_data(ptr, data, size);
108 }
109
110 /**
111 * Read the size as uint followed by the data. Return both via parameters.
112 * Return the next dword following the data.
113 */
114 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
115 {
116 *size = *ptr++;
117 assert(*data == NULL);
118 if (!*size)
119 return ptr;
120 *data = malloc(*size);
121 return read_data(ptr, *data, *size);
122 }
123
124 /**
125 * Return the shader binary in a buffer. The first 4 bytes contain its size
126 * as integer.
127 */
128 static void *si_get_shader_binary(struct si_shader *shader)
129 {
130 /* There is always a size of data followed by the data itself. */
131 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
132 strlen(shader->binary.llvm_ir_string) + 1 : 0;
133
134 /* Refuse to allocate overly large buffers and guard against integer
135 * overflow. */
136 if (shader->binary.elf_size > UINT_MAX / 4 ||
137 llvm_ir_size > UINT_MAX / 4)
138 return NULL;
139
140 unsigned size =
141 4 + /* total size */
142 4 + /* CRC32 of the data below */
143 align(sizeof(shader->config), 4) +
144 align(sizeof(shader->info), 4) +
145 4 + align(shader->binary.elf_size, 4) +
146 4 + align(llvm_ir_size, 4);
147 void *buffer = CALLOC(1, size);
148 uint32_t *ptr = (uint32_t*)buffer;
149
150 if (!buffer)
151 return NULL;
152
153 *ptr++ = size;
154 ptr++; /* CRC32 is calculated at the end. */
155
156 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
157 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
158 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
159 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
160 assert((char *)ptr - (char *)buffer == size);
161
162 /* Compute CRC32. */
163 ptr = (uint32_t*)buffer;
164 ptr++;
165 *ptr = util_hash_crc32(ptr + 1, size - 8);
166
167 return buffer;
168 }
169
170 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
171 {
172 uint32_t *ptr = (uint32_t*)binary;
173 uint32_t size = *ptr++;
174 uint32_t crc32 = *ptr++;
175 unsigned chunk_size;
176 unsigned elf_size;
177
178 if (util_hash_crc32(ptr, size - 8) != crc32) {
179 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
180 return false;
181 }
182
183 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
184 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
185 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
186 &elf_size);
187 shader->binary.elf_size = elf_size;
188 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
189
190 return true;
191 }
192
193 /**
194 * Insert a shader into the cache. It's assumed the shader is not in the cache.
195 * Use si_shader_cache_load_shader before calling this.
196 *
197 * Returns false on failure, in which case the ir_binary should be freed.
198 */
199 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
200 struct si_shader *shader,
201 bool insert_into_disk_cache)
202 {
203 void *hw_binary;
204 struct hash_entry *entry;
205 uint8_t key[CACHE_KEY_SIZE];
206
207 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
208 if (entry)
209 return false; /* already added */
210
211 hw_binary = si_get_shader_binary(shader);
212 if (!hw_binary)
213 return false;
214
215 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
216 hw_binary) == NULL) {
217 FREE(hw_binary);
218 return false;
219 }
220
221 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
222 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
223 *((uint32_t *)ir_binary), key);
224 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
225 *((uint32_t *) hw_binary), NULL);
226 }
227
228 return true;
229 }
230
231 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
232 struct si_shader *shader)
233 {
234 struct hash_entry *entry =
235 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
236 if (!entry) {
237 if (sscreen->disk_shader_cache) {
238 unsigned char sha1[CACHE_KEY_SIZE];
239 size_t tg_size = *((uint32_t *) ir_binary);
240
241 disk_cache_compute_key(sscreen->disk_shader_cache,
242 ir_binary, tg_size, sha1);
243
244 size_t binary_size;
245 uint8_t *buffer =
246 disk_cache_get(sscreen->disk_shader_cache,
247 sha1, &binary_size);
248 if (!buffer)
249 return false;
250
251 if (binary_size < sizeof(uint32_t) ||
252 *((uint32_t*)buffer) != binary_size) {
253 /* Something has gone wrong discard the item
254 * from the cache and rebuild/link from
255 * source.
256 */
257 assert(!"Invalid radeonsi shader disk cache "
258 "item!");
259
260 disk_cache_remove(sscreen->disk_shader_cache,
261 sha1);
262 free(buffer);
263
264 return false;
265 }
266
267 if (!si_load_shader_binary(shader, buffer)) {
268 free(buffer);
269 return false;
270 }
271 free(buffer);
272
273 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
274 shader, false))
275 FREE(ir_binary);
276 } else {
277 return false;
278 }
279 } else {
280 if (si_load_shader_binary(shader, entry->data))
281 FREE(ir_binary);
282 else
283 return false;
284 }
285 p_atomic_inc(&sscreen->num_shader_cache_hits);
286 return true;
287 }
288
289 static uint32_t si_shader_cache_key_hash(const void *key)
290 {
291 /* The first dword is the key size. */
292 return util_hash_crc32(key, *(uint32_t*)key);
293 }
294
295 static bool si_shader_cache_key_equals(const void *a, const void *b)
296 {
297 uint32_t *keya = (uint32_t*)a;
298 uint32_t *keyb = (uint32_t*)b;
299
300 /* The first dword is the key size. */
301 if (*keya != *keyb)
302 return false;
303
304 return memcmp(keya, keyb, *keya) == 0;
305 }
306
307 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
308 {
309 FREE((void*)entry->key);
310 FREE(entry->data);
311 }
312
313 bool si_init_shader_cache(struct si_screen *sscreen)
314 {
315 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
316 sscreen->shader_cache =
317 _mesa_hash_table_create(NULL,
318 si_shader_cache_key_hash,
319 si_shader_cache_key_equals);
320
321 return sscreen->shader_cache != NULL;
322 }
323
324 void si_destroy_shader_cache(struct si_screen *sscreen)
325 {
326 if (sscreen->shader_cache)
327 _mesa_hash_table_destroy(sscreen->shader_cache,
328 si_destroy_shader_cache_entry);
329 mtx_destroy(&sscreen->shader_cache_mutex);
330 }
331
332 /* SHADER STATES */
333
334 static void si_set_tesseval_regs(struct si_screen *sscreen,
335 const struct si_shader_selector *tes,
336 struct si_pm4_state *pm4)
337 {
338 const struct tgsi_shader_info *info = &tes->info;
339 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
340 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
341 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
342 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
343 unsigned type, partitioning, topology, distribution_mode;
344
345 switch (tes_prim_mode) {
346 case PIPE_PRIM_LINES:
347 type = V_028B6C_TESS_ISOLINE;
348 break;
349 case PIPE_PRIM_TRIANGLES:
350 type = V_028B6C_TESS_TRIANGLE;
351 break;
352 case PIPE_PRIM_QUADS:
353 type = V_028B6C_TESS_QUAD;
354 break;
355 default:
356 assert(0);
357 return;
358 }
359
360 switch (tes_spacing) {
361 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
362 partitioning = V_028B6C_PART_FRAC_ODD;
363 break;
364 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
365 partitioning = V_028B6C_PART_FRAC_EVEN;
366 break;
367 case PIPE_TESS_SPACING_EQUAL:
368 partitioning = V_028B6C_PART_INTEGER;
369 break;
370 default:
371 assert(0);
372 return;
373 }
374
375 if (tes_point_mode)
376 topology = V_028B6C_OUTPUT_POINT;
377 else if (tes_prim_mode == PIPE_PRIM_LINES)
378 topology = V_028B6C_OUTPUT_LINE;
379 else if (tes_vertex_order_cw)
380 /* for some reason, this must be the other way around */
381 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
382 else
383 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
384
385 if (sscreen->has_distributed_tess) {
386 if (sscreen->info.family == CHIP_FIJI ||
387 sscreen->info.family >= CHIP_POLARIS10)
388 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
389 else
390 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
391 } else
392 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
393
394 assert(pm4->shader);
395 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
396 S_028B6C_PARTITIONING(partitioning) |
397 S_028B6C_TOPOLOGY(topology) |
398 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
399 }
400
401 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
402 * whether the "fractional odd" tessellation spacing is used.
403 *
404 * Possible VGT configurations and which state should set the register:
405 *
406 * Reg set in | VGT shader configuration | Value
407 * ------------------------------------------------------
408 * VS as VS | VS | 30
409 * VS as ES | ES -> GS -> VS | 30
410 * TES as VS | LS -> HS -> VS | 14 or 30
411 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
412 *
413 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
414 */
415 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
416 struct si_shader_selector *sel,
417 struct si_shader *shader,
418 struct si_pm4_state *pm4)
419 {
420 unsigned type = sel->type;
421
422 if (sscreen->info.family < CHIP_POLARIS10 ||
423 sscreen->info.chip_class >= GFX10)
424 return;
425
426 /* VS as VS, or VS as ES: */
427 if ((type == PIPE_SHADER_VERTEX &&
428 (!shader ||
429 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
430 /* TES as VS, or TES as ES: */
431 type == PIPE_SHADER_TESS_EVAL) {
432 unsigned vtx_reuse_depth = 30;
433
434 if (type == PIPE_SHADER_TESS_EVAL &&
435 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
436 PIPE_TESS_SPACING_FRACTIONAL_ODD)
437 vtx_reuse_depth = 14;
438
439 assert(pm4->shader);
440 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
441 }
442 }
443
444 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
445 {
446 if (shader->pm4)
447 si_pm4_clear_state(shader->pm4);
448 else
449 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
450
451 if (shader->pm4) {
452 shader->pm4->shader = shader;
453 return shader->pm4;
454 } else {
455 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
456 return NULL;
457 }
458 }
459
460 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
461 {
462 /* Add the pointer to VBO descriptors. */
463 return num_always_on_user_sgprs + 1;
464 }
465
466 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
467 {
468 struct si_pm4_state *pm4;
469 unsigned vgpr_comp_cnt;
470 uint64_t va;
471
472 assert(sscreen->info.chip_class <= GFX8);
473
474 pm4 = si_get_shader_pm4_state(shader);
475 if (!pm4)
476 return;
477
478 va = shader->bo->gpu_address;
479 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
480
481 /* We need at least 2 components for LS.
482 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
483 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
484 */
485 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
486
487 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
488 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
489
490 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
491 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
492 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
493 S_00B528_DX10_CLAMP(1) |
494 S_00B528_FLOAT_MODE(shader->config.float_mode);
495 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
496 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
497 }
498
499 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
500 {
501 struct si_pm4_state *pm4;
502 uint64_t va;
503 unsigned ls_vgpr_comp_cnt = 0;
504
505 pm4 = si_get_shader_pm4_state(shader);
506 if (!pm4)
507 return;
508
509 va = shader->bo->gpu_address;
510 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
511
512 if (sscreen->info.chip_class >= GFX9) {
513 if (sscreen->info.chip_class >= GFX10) {
514 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
515 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
516 } else {
517 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
518 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
519 }
520
521 /* We need at least 2 components for LS.
522 * GFX9 VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
523 * GFX10 VGPR0-3: (VertexID, RelAutoindex, UserVGPR1, InstanceID).
524 * On gfx9, StepRate0 is set to 1 so that VGPR3 doesn't have to
525 * be loaded.
526 */
527 ls_vgpr_comp_cnt = 1;
528 if (shader->info.uses_instanceid) {
529 if (sscreen->info.chip_class >= GFX10)
530 ls_vgpr_comp_cnt = 3;
531 else
532 ls_vgpr_comp_cnt = 2;
533 }
534
535 unsigned num_user_sgprs =
536 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
537
538 shader->config.rsrc2 =
539 S_00B42C_USER_SGPR(num_user_sgprs) |
540 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
541
542 if (sscreen->info.chip_class >= GFX10)
543 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
544 else
545 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
546 } else {
547 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
548 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
549
550 shader->config.rsrc2 =
551 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
552 S_00B42C_OC_LDS_EN(1) |
553 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
554 }
555
556 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
557 S_00B428_VGPRS((shader->config.num_vgprs - 1) /
558 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
559 (sscreen->info.chip_class <= GFX9 ?
560 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
561 S_00B428_DX10_CLAMP(1) |
562 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
563 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
564 S_00B428_FLOAT_MODE(shader->config.float_mode) |
565 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
566
567 if (sscreen->info.chip_class <= GFX8) {
568 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
569 shader->config.rsrc2);
570 }
571 }
572
573 static void si_emit_shader_es(struct si_context *sctx)
574 {
575 struct si_shader *shader = sctx->queued.named.es->shader;
576 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
577
578 if (!shader)
579 return;
580
581 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
582 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
583 shader->selector->esgs_itemsize / 4);
584
585 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
586 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
587 SI_TRACKED_VGT_TF_PARAM,
588 shader->vgt_tf_param);
589
590 if (shader->vgt_vertex_reuse_block_cntl)
591 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
592 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
593 shader->vgt_vertex_reuse_block_cntl);
594
595 if (initial_cdw != sctx->gfx_cs->current.cdw)
596 sctx->context_roll = true;
597 }
598
599 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
600 {
601 struct si_pm4_state *pm4;
602 unsigned num_user_sgprs;
603 unsigned vgpr_comp_cnt;
604 uint64_t va;
605 unsigned oc_lds_en;
606
607 assert(sscreen->info.chip_class <= GFX8);
608
609 pm4 = si_get_shader_pm4_state(shader);
610 if (!pm4)
611 return;
612
613 pm4->atom.emit = si_emit_shader_es;
614 va = shader->bo->gpu_address;
615 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
616
617 if (shader->selector->type == PIPE_SHADER_VERTEX) {
618 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
619 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
620 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
621 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
622 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
623 num_user_sgprs = SI_TES_NUM_USER_SGPR;
624 } else
625 unreachable("invalid shader selector type");
626
627 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
628
629 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
630 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
631 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
632 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
633 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
634 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
635 S_00B328_DX10_CLAMP(1) |
636 S_00B328_FLOAT_MODE(shader->config.float_mode));
637 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
638 S_00B32C_USER_SGPR(num_user_sgprs) |
639 S_00B32C_OC_LDS_EN(oc_lds_en) |
640 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
641
642 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
643 si_set_tesseval_regs(sscreen, shader->selector, pm4);
644
645 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
646 }
647
648 void gfx9_get_gs_info(struct si_shader_selector *es,
649 struct si_shader_selector *gs,
650 struct gfx9_gs_info *out)
651 {
652 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
653 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
654 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
655 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
656
657 /* All these are in dwords: */
658 /* We can't allow using the whole LDS, because GS waves compete with
659 * other shader stages for LDS space. */
660 const unsigned max_lds_size = 8 * 1024;
661 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
662 unsigned esgs_lds_size;
663
664 /* All these are per subgroup: */
665 const unsigned max_out_prims = 32 * 1024;
666 const unsigned max_es_verts = 255;
667 const unsigned ideal_gs_prims = 64;
668 unsigned max_gs_prims, gs_prims;
669 unsigned min_es_verts, es_verts, worst_case_es_verts;
670
671 if (uses_adjacency || gs_num_invocations > 1)
672 max_gs_prims = 127 / gs_num_invocations;
673 else
674 max_gs_prims = 255;
675
676 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
677 * Make sure we don't go over the maximum value.
678 */
679 if (gs->gs_max_out_vertices > 0) {
680 max_gs_prims = MIN2(max_gs_prims,
681 max_out_prims /
682 (gs->gs_max_out_vertices * gs_num_invocations));
683 }
684 assert(max_gs_prims > 0);
685
686 /* If the primitive has adjacency, halve the number of vertices
687 * that will be reused in multiple primitives.
688 */
689 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
690
691 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
692 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
693
694 /* Compute ESGS LDS size based on the worst case number of ES vertices
695 * needed to create the target number of GS prims per subgroup.
696 */
697 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
698
699 /* If total LDS usage is too big, refactor partitions based on ratio
700 * of ESGS item sizes.
701 */
702 if (esgs_lds_size > max_lds_size) {
703 /* Our target GS Prims Per Subgroup was too large. Calculate
704 * the maximum number of GS Prims Per Subgroup that will fit
705 * into LDS, capped by the maximum that the hardware can support.
706 */
707 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
708 max_gs_prims);
709 assert(gs_prims > 0);
710 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
711 max_es_verts);
712
713 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
714 assert(esgs_lds_size <= max_lds_size);
715 }
716
717 /* Now calculate remaining ESGS information. */
718 if (esgs_lds_size)
719 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
720 else
721 es_verts = max_es_verts;
722
723 /* Vertices for adjacency primitives are not always reused, so restore
724 * it for ES_VERTS_PER_SUBGRP.
725 */
726 min_es_verts = gs->gs_input_verts_per_prim;
727
728 /* For normal primitives, the VGT only checks if they are past the ES
729 * verts per subgroup after allocating a full GS primitive and if they
730 * are, kick off a new subgroup. But if those additional ES verts are
731 * unique (e.g. not reused) we need to make sure there is enough LDS
732 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
733 */
734 es_verts -= min_es_verts - 1;
735
736 out->es_verts_per_subgroup = es_verts;
737 out->gs_prims_per_subgroup = gs_prims;
738 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
739 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
740 gs->gs_max_out_vertices;
741 out->esgs_ring_size = 4 * esgs_lds_size;
742
743 assert(out->max_prims_per_subgroup <= max_out_prims);
744 }
745
746 static void si_emit_shader_gs(struct si_context *sctx)
747 {
748 struct si_shader *shader = sctx->queued.named.gs->shader;
749 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
750
751 if (!shader)
752 return;
753
754 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
755 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
756 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
757 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
758 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
759 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
760 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
761
762 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
763 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
764 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
765 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
766
767 /* R_028B38_VGT_GS_MAX_VERT_OUT */
768 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
769 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
770 shader->ctx_reg.gs.vgt_gs_max_vert_out);
771
772 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
773 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
774 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
775 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
776 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
777 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
778 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
779 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
780
781 /* R_028B90_VGT_GS_INSTANCE_CNT */
782 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
783 SI_TRACKED_VGT_GS_INSTANCE_CNT,
784 shader->ctx_reg.gs.vgt_gs_instance_cnt);
785
786 if (sctx->chip_class >= GFX9) {
787 /* R_028A44_VGT_GS_ONCHIP_CNTL */
788 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
789 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
790 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
791 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
792 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
793 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
794 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
795 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
796 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
797 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
798 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
799
800 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
801 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
802 SI_TRACKED_VGT_TF_PARAM,
803 shader->vgt_tf_param);
804 if (shader->vgt_vertex_reuse_block_cntl)
805 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
806 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
807 shader->vgt_vertex_reuse_block_cntl);
808 }
809
810 if (initial_cdw != sctx->gfx_cs->current.cdw)
811 sctx->context_roll = true;
812 }
813
814 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
815 {
816 struct si_shader_selector *sel = shader->selector;
817 const ubyte *num_components = sel->info.num_stream_output_components;
818 unsigned gs_num_invocations = sel->gs_num_invocations;
819 struct si_pm4_state *pm4;
820 uint64_t va;
821 unsigned max_stream = sel->max_gs_stream;
822 unsigned offset;
823
824 pm4 = si_get_shader_pm4_state(shader);
825 if (!pm4)
826 return;
827
828 pm4->atom.emit = si_emit_shader_gs;
829
830 offset = num_components[0] * sel->gs_max_out_vertices;
831 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
832
833 if (max_stream >= 1)
834 offset += num_components[1] * sel->gs_max_out_vertices;
835 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
836
837 if (max_stream >= 2)
838 offset += num_components[2] * sel->gs_max_out_vertices;
839 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
840
841 if (max_stream >= 3)
842 offset += num_components[3] * sel->gs_max_out_vertices;
843 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
844
845 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
846 assert(offset < (1 << 15));
847
848 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
849
850 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
851 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
852 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
853 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
854
855 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
856 S_028B90_ENABLE(gs_num_invocations > 0);
857
858 va = shader->bo->gpu_address;
859 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
860
861 if (sscreen->info.chip_class >= GFX9) {
862 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
863 unsigned es_type = shader->key.part.gs.es->type;
864 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
865
866 if (es_type == PIPE_SHADER_VERTEX)
867 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
868 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
869 else if (es_type == PIPE_SHADER_TESS_EVAL)
870 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
871 else
872 unreachable("invalid shader selector type");
873
874 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
875 * VGPR[0:4] are always loaded.
876 */
877 if (sel->info.uses_invocationid)
878 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
879 else if (sel->info.uses_primid)
880 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
881 else if (input_prim >= PIPE_PRIM_TRIANGLES)
882 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
883 else
884 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
885
886 unsigned num_user_sgprs;
887 if (es_type == PIPE_SHADER_VERTEX)
888 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
889 else
890 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
891
892 if (sscreen->info.chip_class >= GFX10) {
893 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
894 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
895 } else {
896 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
897 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
898 }
899
900 uint32_t rsrc1 =
901 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
902 S_00B228_DX10_CLAMP(1) |
903 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
904 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
905 S_00B228_FLOAT_MODE(shader->config.float_mode) |
906 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
907 uint32_t rsrc2 =
908 S_00B22C_USER_SGPR(num_user_sgprs) |
909 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
910 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
911 S_00B22C_LDS_SIZE(shader->config.lds_size) |
912 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
913
914 if (sscreen->info.chip_class >= GFX10) {
915 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
916 } else {
917 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
918 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
919 }
920
921 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
922 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
923
924 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
925 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
926 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
927 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
928 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
929 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
930 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
931 shader->key.part.gs.es->esgs_itemsize / 4;
932
933 if (es_type == PIPE_SHADER_TESS_EVAL)
934 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
935
936 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
937 NULL, pm4);
938 } else {
939 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
940 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
941
942 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
943 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
944 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
945 S_00B228_DX10_CLAMP(1) |
946 S_00B228_FLOAT_MODE(shader->config.float_mode));
947 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
948 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
949 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
950 }
951 }
952
953 /* Common tail code for NGG primitive shaders. */
954 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
955 struct si_shader *shader,
956 unsigned initial_cdw)
957 {
958 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
959 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
960 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
961 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
962 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
963 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
964 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
965 SI_TRACKED_VGT_PRIMITIVEID_EN,
966 shader->ctx_reg.ngg.vgt_primitiveid_en);
967 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
968 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
969 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
970 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
971 SI_TRACKED_VGT_GS_INSTANCE_CNT,
972 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
973 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
974 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
975 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
976 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
977 SI_TRACKED_VGT_REUSE_OFF,
978 shader->ctx_reg.ngg.vgt_reuse_off);
979 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
980 SI_TRACKED_SPI_VS_OUT_CONFIG,
981 shader->ctx_reg.ngg.spi_vs_out_config);
982 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
983 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
984 shader->ctx_reg.ngg.spi_shader_idx_format,
985 shader->ctx_reg.ngg.spi_shader_pos_format);
986 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
987 SI_TRACKED_PA_CL_VTE_CNTL,
988 shader->ctx_reg.ngg.pa_cl_vte_cntl);
989 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
990 SI_TRACKED_PA_CL_NGG_CNTL,
991 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
992
993 if (initial_cdw != sctx->gfx_cs->current.cdw)
994 sctx->context_roll = true;
995 }
996
997 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
998 {
999 struct si_shader *shader = sctx->queued.named.gs->shader;
1000 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1001
1002 if (!shader)
1003 return;
1004
1005 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1006 }
1007
1008 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1009 {
1010 struct si_shader *shader = sctx->queued.named.gs->shader;
1011 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1012
1013 if (!shader)
1014 return;
1015
1016 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1017 SI_TRACKED_VGT_TF_PARAM,
1018 shader->vgt_tf_param);
1019
1020 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1021 }
1022
1023 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1024 {
1025 struct si_shader *shader = sctx->queued.named.gs->shader;
1026 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1027
1028 if (!shader)
1029 return;
1030
1031 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1032 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1033 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1034
1035 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1036 }
1037
1038 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1039 {
1040 struct si_shader *shader = sctx->queued.named.gs->shader;
1041 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1042
1043 if (!shader)
1044 return;
1045
1046 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1047 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1048 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1049 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1050 SI_TRACKED_VGT_TF_PARAM,
1051 shader->vgt_tf_param);
1052
1053 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1054 }
1055
1056 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1057 {
1058 if (gs->type == PIPE_SHADER_GEOMETRY)
1059 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1060
1061 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1062 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1063 return PIPE_PRIM_POINTS;
1064 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1065 return PIPE_PRIM_LINES;
1066 return PIPE_PRIM_TRIANGLES;
1067 }
1068
1069 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1070 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1071 }
1072
1073 /**
1074 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1075 * in NGG mode.
1076 */
1077 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1078 {
1079 const struct si_shader_selector *gs_sel = shader->selector;
1080 const struct tgsi_shader_info *gs_info = &gs_sel->info;
1081 enum pipe_shader_type gs_type = shader->selector->type;
1082 const struct si_shader_selector *es_sel =
1083 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1084 const struct tgsi_shader_info *es_info = &es_sel->info;
1085 enum pipe_shader_type es_type = es_sel->type;
1086 unsigned num_user_sgprs;
1087 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1088 uint64_t va;
1089 unsigned window_space =
1090 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1091 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1092 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1093 unsigned input_prim = si_get_input_prim(gs_sel);
1094 bool break_wave_at_eoi = false;
1095 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1096 if (!pm4)
1097 return;
1098
1099 if (es_type == PIPE_SHADER_TESS_EVAL) {
1100 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1101 : gfx10_emit_shader_ngg_tess_nogs;
1102 } else {
1103 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1104 : gfx10_emit_shader_ngg_notess_nogs;
1105 }
1106
1107 va = shader->bo->gpu_address;
1108 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1109
1110 if (es_type == PIPE_SHADER_VERTEX) {
1111 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1112 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
1113
1114 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1115 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1116 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1117 } else {
1118 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
1119 }
1120 } else {
1121 assert(es_type == PIPE_SHADER_TESS_EVAL);
1122 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1123 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1124
1125 if (es_enable_prim_id || gs_info->uses_primid)
1126 break_wave_at_eoi = true;
1127 }
1128
1129 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1130 * VGPR[0:4] are always loaded.
1131 *
1132 * Vertex shaders always need to load VGPR3, because they need to
1133 * pass edge flags for decomposed primitives (such as quads) to the PA
1134 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1135 */
1136 if (gs_info->uses_invocationid || gs_type == PIPE_SHADER_VERTEX)
1137 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1138 else if (gs_info->uses_primid)
1139 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1140 else if (input_prim >= PIPE_PRIM_TRIANGLES)
1141 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1142 else
1143 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1144
1145 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1146 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1147 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1148 S_00B228_VGPRS((shader->config.num_vgprs - 1) /
1149 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1150 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1151 S_00B228_DX10_CLAMP(1) |
1152 S_00B228_MEM_ORDERED(1) |
1153 S_00B228_WGP_MODE(1) |
1154 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1155 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1156 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1157 S_00B22C_USER_SGPR(num_user_sgprs) |
1158 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1159 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1160 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1161 S_00B22C_LDS_SIZE(shader->config.lds_size));
1162
1163 nparams = MAX2(shader->info.nr_param_exports, 1);
1164 shader->ctx_reg.ngg.spi_vs_out_config =
1165 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1166 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1167
1168 shader->ctx_reg.ngg.spi_shader_idx_format =
1169 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1170 shader->ctx_reg.ngg.spi_shader_pos_format =
1171 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1172 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1173 V_02870C_SPI_SHADER_4COMP :
1174 V_02870C_SPI_SHADER_NONE) |
1175 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1176 V_02870C_SPI_SHADER_4COMP :
1177 V_02870C_SPI_SHADER_NONE) |
1178 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1179 V_02870C_SPI_SHADER_4COMP :
1180 V_02870C_SPI_SHADER_NONE);
1181
1182 shader->ctx_reg.ngg.vgt_primitiveid_en =
1183 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1184 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id);
1185
1186 if (gs_type == PIPE_SHADER_GEOMETRY) {
1187 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1188 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1189 } else {
1190 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1191 }
1192
1193 if (es_type == PIPE_SHADER_TESS_EVAL)
1194 si_set_tesseval_regs(sscreen, es_sel, pm4);
1195
1196 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1197 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1198 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1199 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1200 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1201 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1202 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1203 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1204 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1205 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1206 S_028B90_CNT(gs_num_invocations) |
1207 S_028B90_ENABLE(gs_num_invocations > 1) |
1208 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1209 shader->ngg.max_vert_out_per_gs_instance);
1210
1211 /* Always output hw-generated edge flags and pass them via the prim
1212 * export to prevent drawing lines on internal edges of decomposed
1213 * primitives (such as quads) with polygon mode = lines. Only VS needs
1214 * this.
1215 */
1216 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1217 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
1218
1219 shader->ge_cntl =
1220 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1221 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) |
1222 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1223
1224 /* Bug workaround for a possible hang with non-tessellation cases.
1225 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1226 *
1227 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1228 */
1229 if ((sscreen->info.family == CHIP_NAVI10 ||
1230 sscreen->info.family == CHIP_NAVI12 ||
1231 sscreen->info.family == CHIP_NAVI14) &&
1232 (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
1233 shader->ngg.hw_max_esverts != 256) {
1234 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1235
1236 if (shader->ngg.hw_max_esverts > 5) {
1237 shader->ge_cntl |=
1238 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1239 }
1240 }
1241
1242 if (window_space) {
1243 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1244 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1245 } else {
1246 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1247 S_028818_VTX_W0_FMT(1) |
1248 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1249 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1250 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1251 }
1252
1253 shader->ctx_reg.ngg.vgt_reuse_off =
1254 S_028AB4_REUSE_OFF(sscreen->info.family == CHIP_NAVI10 &&
1255 sscreen->info.chip_external_rev == 0x1 &&
1256 es_type == PIPE_SHADER_TESS_EVAL);
1257 }
1258
1259 static void si_emit_shader_vs(struct si_context *sctx)
1260 {
1261 struct si_shader *shader = sctx->queued.named.vs->shader;
1262 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1263
1264 if (!shader)
1265 return;
1266
1267 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1268 SI_TRACKED_VGT_GS_MODE,
1269 shader->ctx_reg.vs.vgt_gs_mode);
1270 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1271 SI_TRACKED_VGT_PRIMITIVEID_EN,
1272 shader->ctx_reg.vs.vgt_primitiveid_en);
1273
1274 if (sctx->chip_class <= GFX8) {
1275 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1276 SI_TRACKED_VGT_REUSE_OFF,
1277 shader->ctx_reg.vs.vgt_reuse_off);
1278 }
1279
1280 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1281 SI_TRACKED_SPI_VS_OUT_CONFIG,
1282 shader->ctx_reg.vs.spi_vs_out_config);
1283
1284 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1285 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1286 shader->ctx_reg.vs.spi_shader_pos_format);
1287
1288 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1289 SI_TRACKED_PA_CL_VTE_CNTL,
1290 shader->ctx_reg.vs.pa_cl_vte_cntl);
1291
1292 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1293 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1294 SI_TRACKED_VGT_TF_PARAM,
1295 shader->vgt_tf_param);
1296
1297 if (shader->vgt_vertex_reuse_block_cntl)
1298 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1299 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1300 shader->vgt_vertex_reuse_block_cntl);
1301
1302 if (initial_cdw != sctx->gfx_cs->current.cdw)
1303 sctx->context_roll = true;
1304 }
1305
1306 /**
1307 * Compute the state for \p shader, which will run as a vertex shader on the
1308 * hardware.
1309 *
1310 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1311 * is the copy shader.
1312 */
1313 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1314 struct si_shader_selector *gs)
1315 {
1316 const struct tgsi_shader_info *info = &shader->selector->info;
1317 struct si_pm4_state *pm4;
1318 unsigned num_user_sgprs, vgpr_comp_cnt;
1319 uint64_t va;
1320 unsigned nparams, oc_lds_en;
1321 unsigned window_space =
1322 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1323 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1324
1325 pm4 = si_get_shader_pm4_state(shader);
1326 if (!pm4)
1327 return;
1328
1329 pm4->atom.emit = si_emit_shader_vs;
1330
1331 /* We always write VGT_GS_MODE in the VS state, because every switch
1332 * between different shader pipelines involving a different GS or no
1333 * GS at all involves a switch of the VS (different GS use different
1334 * copy shaders). On the other hand, when the API switches from a GS to
1335 * no GS and then back to the same GS used originally, the GS state is
1336 * not sent again.
1337 */
1338 if (!gs) {
1339 unsigned mode = V_028A40_GS_OFF;
1340
1341 /* PrimID needs GS scenario A. */
1342 if (enable_prim_id)
1343 mode = V_028A40_GS_SCENARIO_A;
1344
1345 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1346 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1347 } else {
1348 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1349 sscreen->info.chip_class);
1350 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1351 }
1352
1353 if (sscreen->info.chip_class <= GFX8) {
1354 /* Reuse needs to be set off if we write oViewport. */
1355 shader->ctx_reg.vs.vgt_reuse_off =
1356 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1357 }
1358
1359 va = shader->bo->gpu_address;
1360 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1361
1362 if (gs) {
1363 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1364 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1365 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1366 if (sscreen->info.chip_class >= GFX10) {
1367 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
1368 } else {
1369 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1370 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1371 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1372 */
1373 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1374 }
1375
1376 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1377 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1378 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1379 } else {
1380 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1381 }
1382 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1383 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1384 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1385 } else
1386 unreachable("invalid shader selector type");
1387
1388 /* VS is required to export at least one param. */
1389 nparams = MAX2(shader->info.nr_param_exports, 1);
1390 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1391
1392 if (sscreen->info.chip_class >= GFX10) {
1393 shader->ctx_reg.vs.spi_vs_out_config |=
1394 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1395 }
1396
1397 shader->ctx_reg.vs.spi_shader_pos_format =
1398 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1399 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1400 V_02870C_SPI_SHADER_4COMP :
1401 V_02870C_SPI_SHADER_NONE) |
1402 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1403 V_02870C_SPI_SHADER_4COMP :
1404 V_02870C_SPI_SHADER_NONE) |
1405 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1406 V_02870C_SPI_SHADER_4COMP :
1407 V_02870C_SPI_SHADER_NONE);
1408
1409 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1410
1411 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1412 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1413
1414 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
1415 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1416 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1417 S_00B128_DX10_CLAMP(1) |
1418 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1419 S_00B128_FLOAT_MODE(shader->config.float_mode);
1420 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1421 S_00B12C_OC_LDS_EN(oc_lds_en) |
1422 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1423
1424 if (sscreen->info.chip_class <= GFX9) {
1425 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1426 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1427 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1428 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1429 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1430 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1431 }
1432
1433 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1434 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1435
1436 if (window_space)
1437 shader->ctx_reg.vs.pa_cl_vte_cntl =
1438 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1439 else
1440 shader->ctx_reg.vs.pa_cl_vte_cntl =
1441 S_028818_VTX_W0_FMT(1) |
1442 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1443 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1444 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1445
1446 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1447 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1448
1449 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1450 }
1451
1452 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1453 {
1454 struct tgsi_shader_info *info = &ps->selector->info;
1455 unsigned num_colors = !!(info->colors_read & 0x0f) +
1456 !!(info->colors_read & 0xf0);
1457 unsigned num_interp = ps->selector->info.num_inputs +
1458 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1459
1460 assert(num_interp <= 32);
1461 return MIN2(num_interp, 32);
1462 }
1463
1464 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1465 {
1466 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1467 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1468
1469 /* If the i-th target format is set, all previous target formats must
1470 * be non-zero to avoid hangs.
1471 */
1472 for (i = 0; i < num_targets; i++)
1473 if (!(value & (0xf << (i * 4))))
1474 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1475
1476 return value;
1477 }
1478
1479 static void si_emit_shader_ps(struct si_context *sctx)
1480 {
1481 struct si_shader *shader = sctx->queued.named.ps->shader;
1482 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1483
1484 if (!shader)
1485 return;
1486
1487 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1488 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1489 SI_TRACKED_SPI_PS_INPUT_ENA,
1490 shader->ctx_reg.ps.spi_ps_input_ena,
1491 shader->ctx_reg.ps.spi_ps_input_addr);
1492
1493 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1494 SI_TRACKED_SPI_BARYC_CNTL,
1495 shader->ctx_reg.ps.spi_baryc_cntl);
1496 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1497 SI_TRACKED_SPI_PS_IN_CONTROL,
1498 shader->ctx_reg.ps.spi_ps_in_control);
1499
1500 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1501 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1502 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1503 shader->ctx_reg.ps.spi_shader_z_format,
1504 shader->ctx_reg.ps.spi_shader_col_format);
1505
1506 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1507 SI_TRACKED_CB_SHADER_MASK,
1508 shader->ctx_reg.ps.cb_shader_mask);
1509
1510 if (initial_cdw != sctx->gfx_cs->current.cdw)
1511 sctx->context_roll = true;
1512 }
1513
1514 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1515 {
1516 struct tgsi_shader_info *info = &shader->selector->info;
1517 struct si_pm4_state *pm4;
1518 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1519 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1520 uint64_t va;
1521 unsigned input_ena = shader->config.spi_ps_input_ena;
1522
1523 /* we need to enable at least one of them, otherwise we hang the GPU */
1524 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1525 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1526 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1527 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1528 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1529 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1530 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1531 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1532 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1533 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1534 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1535 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1536 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1537 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1538
1539 /* Validate interpolation optimization flags (read as implications). */
1540 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1541 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1542 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1543 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1544 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1545 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1546 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1547 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1548 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1549 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1550 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1551 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1552 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1553 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1554 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1555 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1556 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1557 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1558
1559 /* Validate cases when the optimizations are off (read as implications). */
1560 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1561 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1562 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1563 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1564 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1565 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1566
1567 pm4 = si_get_shader_pm4_state(shader);
1568 if (!pm4)
1569 return;
1570
1571 pm4->atom.emit = si_emit_shader_ps;
1572
1573 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1574 * Possible vaules:
1575 * 0 -> Position = pixel center
1576 * 1 -> Position = pixel centroid
1577 * 2 -> Position = at sample position
1578 *
1579 * From GLSL 4.5 specification, section 7.1:
1580 * "The variable gl_FragCoord is available as an input variable from
1581 * within fragment shaders and it holds the window relative coordinates
1582 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1583 * value can be for any location within the pixel, or one of the
1584 * fragment samples. The use of centroid does not further restrict
1585 * this value to be inside the current primitive."
1586 *
1587 * Meaning that centroid has no effect and we can return anything within
1588 * the pixel. Thus, return the value at sample position, because that's
1589 * the most accurate one shaders can get.
1590 */
1591 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1592
1593 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1594 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1595 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1596
1597 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1598 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1599
1600 /* Ensure that some export memory is always allocated, for two reasons:
1601 *
1602 * 1) Correctness: The hardware ignores the EXEC mask if no export
1603 * memory is allocated, so KILL and alpha test do not work correctly
1604 * without this.
1605 * 2) Performance: Every shader needs at least a NULL export, even when
1606 * it writes no color/depth output. The NULL export instruction
1607 * stalls without this setting.
1608 *
1609 * Don't add this to CB_SHADER_MASK.
1610 *
1611 * GFX10 supports pixel shaders without exports by setting both
1612 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1613 * instructions if any are present.
1614 */
1615 if ((sscreen->info.chip_class <= GFX9 ||
1616 info->uses_kill ||
1617 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1618 !spi_shader_col_format &&
1619 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1620 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1621
1622 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1623 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1624
1625 /* Set interpolation controls. */
1626 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1627 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1628
1629 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1630 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1631 shader->ctx_reg.ps.spi_shader_z_format =
1632 ac_get_spi_shader_z_format(info->writes_z,
1633 info->writes_stencil,
1634 info->writes_samplemask);
1635 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1636 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1637
1638 va = shader->bo->gpu_address;
1639 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1640 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1641 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1642
1643 uint32_t rsrc1 =
1644 S_00B028_VGPRS((shader->config.num_vgprs - 1) /
1645 (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1646 S_00B028_DX10_CLAMP(1) |
1647 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1648 S_00B028_FLOAT_MODE(shader->config.float_mode);
1649
1650 if (sscreen->info.chip_class < GFX10) {
1651 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1652 }
1653
1654 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1655 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1656 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1657 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1658 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1659 }
1660
1661 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1662 struct si_shader *shader)
1663 {
1664 switch (shader->selector->type) {
1665 case PIPE_SHADER_VERTEX:
1666 if (shader->key.as_ls)
1667 si_shader_ls(sscreen, shader);
1668 else if (shader->key.as_es)
1669 si_shader_es(sscreen, shader);
1670 else if (shader->key.as_ngg)
1671 gfx10_shader_ngg(sscreen, shader);
1672 else
1673 si_shader_vs(sscreen, shader, NULL);
1674 break;
1675 case PIPE_SHADER_TESS_CTRL:
1676 si_shader_hs(sscreen, shader);
1677 break;
1678 case PIPE_SHADER_TESS_EVAL:
1679 if (shader->key.as_es)
1680 si_shader_es(sscreen, shader);
1681 else if (shader->key.as_ngg)
1682 gfx10_shader_ngg(sscreen, shader);
1683 else
1684 si_shader_vs(sscreen, shader, NULL);
1685 break;
1686 case PIPE_SHADER_GEOMETRY:
1687 if (shader->key.as_ngg)
1688 gfx10_shader_ngg(sscreen, shader);
1689 else
1690 si_shader_gs(sscreen, shader);
1691 break;
1692 case PIPE_SHADER_FRAGMENT:
1693 si_shader_ps(sscreen, shader);
1694 break;
1695 default:
1696 assert(0);
1697 }
1698 }
1699
1700 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1701 {
1702 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1703 return sctx->queued.named.dsa->alpha_func;
1704 }
1705
1706 void si_shader_selector_key_vs(struct si_context *sctx,
1707 struct si_shader_selector *vs,
1708 struct si_shader_key *key,
1709 struct si_vs_prolog_bits *prolog_key)
1710 {
1711 if (!sctx->vertex_elements ||
1712 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS])
1713 return;
1714
1715 struct si_vertex_elements *elts = sctx->vertex_elements;
1716
1717 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1718 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1719 prolog_key->unpack_instance_id_from_vertex_id =
1720 sctx->prim_discard_cs_instancing;
1721
1722 /* Prefer a monolithic shader to allow scheduling divisions around
1723 * VBO loads. */
1724 if (prolog_key->instance_divisor_is_fetched)
1725 key->opt.prefer_mono = 1;
1726
1727 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1728 unsigned count_mask = (1 << count) - 1;
1729 unsigned fix = elts->fix_fetch_always & count_mask;
1730 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1731
1732 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1733 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1734 while (mask) {
1735 unsigned i = u_bit_scan(&mask);
1736 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1737 unsigned vbidx = elts->vertex_buffer_index[i];
1738 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1739 unsigned align_mask = (1 << log_hw_load_size) - 1;
1740 if (vb->buffer_offset & align_mask ||
1741 vb->stride & align_mask) {
1742 fix |= 1 << i;
1743 opencode |= 1 << i;
1744 }
1745 }
1746 }
1747
1748 while (fix) {
1749 unsigned i = u_bit_scan(&fix);
1750 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1751 }
1752 key->mono.vs_fetch_opencode = opencode;
1753 }
1754
1755 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1756 struct si_shader_selector *vs,
1757 struct si_shader_key *key)
1758 {
1759 struct si_shader_selector *ps = sctx->ps_shader.cso;
1760
1761 key->opt.clip_disable =
1762 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1763 (vs->info.clipdist_writemask ||
1764 vs->info.writes_clipvertex) &&
1765 !vs->info.culldist_writemask;
1766
1767 /* Find out if PS is disabled. */
1768 bool ps_disabled = true;
1769 if (ps) {
1770 bool ps_modifies_zs = ps->info.uses_kill ||
1771 ps->info.writes_z ||
1772 ps->info.writes_stencil ||
1773 ps->info.writes_samplemask ||
1774 sctx->queued.named.blend->alpha_to_coverage ||
1775 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1776 unsigned ps_colormask = si_get_total_colormask(sctx);
1777
1778 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1779 (!ps_colormask &&
1780 !ps_modifies_zs &&
1781 !ps->info.writes_memory);
1782 }
1783
1784 /* Find out which VS outputs aren't used by the PS. */
1785 uint64_t outputs_written = vs->outputs_written_before_ps;
1786 uint64_t inputs_read = 0;
1787
1788 /* Ignore outputs that are not passed from VS to PS. */
1789 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1790 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1791 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1792
1793 if (!ps_disabled) {
1794 inputs_read = ps->inputs_read;
1795 }
1796
1797 uint64_t linked = outputs_written & inputs_read;
1798
1799 key->opt.kill_outputs = ~linked & outputs_written;
1800 }
1801
1802 /* Compute the key for the hw shader variant */
1803 static inline void si_shader_selector_key(struct pipe_context *ctx,
1804 struct si_shader_selector *sel,
1805 union si_vgt_stages_key stages_key,
1806 struct si_shader_key *key)
1807 {
1808 struct si_context *sctx = (struct si_context *)ctx;
1809
1810 memset(key, 0, sizeof(*key));
1811
1812 switch (sel->type) {
1813 case PIPE_SHADER_VERTEX:
1814 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1815
1816 if (sctx->tes_shader.cso)
1817 key->as_ls = 1;
1818 else if (sctx->gs_shader.cso)
1819 key->as_es = 1;
1820 else {
1821 key->as_ngg = stages_key.u.ngg;
1822 si_shader_selector_key_hw_vs(sctx, sel, key);
1823
1824 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1825 key->mono.u.vs_export_prim_id = 1;
1826 }
1827 break;
1828 case PIPE_SHADER_TESS_CTRL:
1829 if (sctx->chip_class >= GFX9) {
1830 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1831 key, &key->part.tcs.ls_prolog);
1832 key->part.tcs.ls = sctx->vs_shader.cso;
1833
1834 /* When the LS VGPR fix is needed, monolithic shaders
1835 * can:
1836 * - avoid initializing EXEC in both the LS prolog
1837 * and the LS main part when !vs_needs_prolog
1838 * - remove the fixup for unused input VGPRs
1839 */
1840 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1841
1842 /* The LS output / HS input layout can be communicated
1843 * directly instead of via user SGPRs for merged LS-HS.
1844 * The LS VGPR fix prefers this too.
1845 */
1846 key->opt.prefer_mono = 1;
1847 }
1848
1849 key->part.tcs.epilog.prim_mode =
1850 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1851 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1852 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1853 key->part.tcs.epilog.tes_reads_tess_factors =
1854 sctx->tes_shader.cso->info.reads_tess_factors;
1855
1856 if (sel == sctx->fixed_func_tcs_shader.cso)
1857 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1858 break;
1859 case PIPE_SHADER_TESS_EVAL:
1860 key->as_ngg = stages_key.u.ngg;
1861
1862 if (sctx->gs_shader.cso)
1863 key->as_es = 1;
1864 else {
1865 si_shader_selector_key_hw_vs(sctx, sel, key);
1866
1867 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1868 key->mono.u.vs_export_prim_id = 1;
1869 }
1870 break;
1871 case PIPE_SHADER_GEOMETRY:
1872 if (sctx->chip_class >= GFX9) {
1873 if (sctx->tes_shader.cso) {
1874 key->part.gs.es = sctx->tes_shader.cso;
1875 } else {
1876 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1877 key, &key->part.gs.vs_prolog);
1878 key->part.gs.es = sctx->vs_shader.cso;
1879 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1880 }
1881
1882 key->as_ngg = stages_key.u.ngg;
1883
1884 /* Merged ES-GS can have unbalanced wave usage.
1885 *
1886 * ES threads are per-vertex, while GS threads are
1887 * per-primitive. So without any amplification, there
1888 * are fewer GS threads than ES threads, which can result
1889 * in empty (no-op) GS waves. With too much amplification,
1890 * there are more GS threads than ES threads, which
1891 * can result in empty (no-op) ES waves.
1892 *
1893 * Non-monolithic shaders are implemented by setting EXEC
1894 * at the beginning of shader parts, and don't jump to
1895 * the end if EXEC is 0.
1896 *
1897 * Monolithic shaders use conditional blocks, so they can
1898 * jump and skip empty waves of ES or GS. So set this to
1899 * always use optimized variants, which are monolithic.
1900 */
1901 key->opt.prefer_mono = 1;
1902 }
1903 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1904 break;
1905 case PIPE_SHADER_FRAGMENT: {
1906 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1907 struct si_state_blend *blend = sctx->queued.named.blend;
1908
1909 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1910 sel->info.colors_written == 0x1)
1911 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1912
1913 /* Select the shader color format based on whether
1914 * blending or alpha are needed.
1915 */
1916 key->part.ps.epilog.spi_shader_col_format =
1917 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1918 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1919 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1920 sctx->framebuffer.spi_shader_col_format_blend) |
1921 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1922 sctx->framebuffer.spi_shader_col_format_alpha) |
1923 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1924 sctx->framebuffer.spi_shader_col_format);
1925 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1926
1927 /* The output for dual source blending should have
1928 * the same format as the first output.
1929 */
1930 if (blend->dual_src_blend) {
1931 key->part.ps.epilog.spi_shader_col_format |=
1932 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1933 }
1934
1935 /* If alpha-to-coverage is enabled, we have to export alpha
1936 * even if there is no color buffer.
1937 */
1938 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1939 blend->alpha_to_coverage)
1940 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1941
1942 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1943 * to the range supported by the type if a channel has less
1944 * than 16 bits and the export format is 16_ABGR.
1945 */
1946 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1947 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1948 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1949 }
1950
1951 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1952 if (!key->part.ps.epilog.last_cbuf) {
1953 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1954 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1955 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1956 }
1957
1958 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1959 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1960
1961 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1962 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1963
1964 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one &&
1965 rs->multisample_enable;
1966
1967 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1968 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1969 (is_line && rs->line_smooth)) &&
1970 sctx->framebuffer.nr_samples <= 1;
1971 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1972
1973 if (sctx->ps_iter_samples > 1 &&
1974 sel->info.reads_samplemask) {
1975 key->part.ps.prolog.samplemask_log_ps_iter =
1976 util_logbase2(sctx->ps_iter_samples);
1977 }
1978
1979 if (rs->force_persample_interp &&
1980 rs->multisample_enable &&
1981 sctx->framebuffer.nr_samples > 1 &&
1982 sctx->ps_iter_samples > 1) {
1983 key->part.ps.prolog.force_persp_sample_interp =
1984 sel->info.uses_persp_center ||
1985 sel->info.uses_persp_centroid;
1986
1987 key->part.ps.prolog.force_linear_sample_interp =
1988 sel->info.uses_linear_center ||
1989 sel->info.uses_linear_centroid;
1990 } else if (rs->multisample_enable &&
1991 sctx->framebuffer.nr_samples > 1) {
1992 key->part.ps.prolog.bc_optimize_for_persp =
1993 sel->info.uses_persp_center &&
1994 sel->info.uses_persp_centroid;
1995 key->part.ps.prolog.bc_optimize_for_linear =
1996 sel->info.uses_linear_center &&
1997 sel->info.uses_linear_centroid;
1998 } else {
1999 /* Make sure SPI doesn't compute more than 1 pair
2000 * of (i,j), which is the optimization here. */
2001 key->part.ps.prolog.force_persp_center_interp =
2002 sel->info.uses_persp_center +
2003 sel->info.uses_persp_centroid +
2004 sel->info.uses_persp_sample > 1;
2005
2006 key->part.ps.prolog.force_linear_center_interp =
2007 sel->info.uses_linear_center +
2008 sel->info.uses_linear_centroid +
2009 sel->info.uses_linear_sample > 1;
2010
2011 if (sel->info.uses_persp_opcode_interp_sample ||
2012 sel->info.uses_linear_opcode_interp_sample)
2013 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2014 }
2015
2016 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2017
2018 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2019 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2020 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2021 struct pipe_resource *tex = cb0->texture;
2022
2023 /* 1D textures are allocated and used as 2D on GFX9. */
2024 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2025 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2026 (tex->target == PIPE_TEXTURE_1D ||
2027 tex->target == PIPE_TEXTURE_1D_ARRAY);
2028 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2029 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2030 tex->target == PIPE_TEXTURE_CUBE ||
2031 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2032 tex->target == PIPE_TEXTURE_3D;
2033 }
2034 break;
2035 }
2036 default:
2037 assert(0);
2038 }
2039
2040 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2041 memset(&key->opt, 0, sizeof(key->opt));
2042 }
2043
2044 static void si_build_shader_variant(struct si_shader *shader,
2045 int thread_index,
2046 bool low_priority)
2047 {
2048 struct si_shader_selector *sel = shader->selector;
2049 struct si_screen *sscreen = sel->screen;
2050 struct ac_llvm_compiler *compiler;
2051 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2052
2053 if (thread_index >= 0) {
2054 if (low_priority) {
2055 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2056 compiler = &sscreen->compiler_lowp[thread_index];
2057 } else {
2058 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2059 compiler = &sscreen->compiler[thread_index];
2060 }
2061 if (!debug->async)
2062 debug = NULL;
2063 } else {
2064 assert(!low_priority);
2065 compiler = shader->compiler_ctx_state.compiler;
2066 }
2067
2068 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
2069 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2070 sel->type);
2071 shader->compilation_failed = true;
2072 return;
2073 }
2074
2075 if (shader->compiler_ctx_state.is_debug_context) {
2076 FILE *f = open_memstream(&shader->shader_log,
2077 &shader->shader_log_size);
2078 if (f) {
2079 si_shader_dump(sscreen, shader, NULL, f, false);
2080 fclose(f);
2081 }
2082 }
2083
2084 si_shader_init_pm4_state(sscreen, shader);
2085 }
2086
2087 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2088 {
2089 struct si_shader *shader = (struct si_shader *)job;
2090
2091 assert(thread_index >= 0);
2092
2093 si_build_shader_variant(shader, thread_index, true);
2094 }
2095
2096 static const struct si_shader_key zeroed;
2097
2098 static bool si_check_missing_main_part(struct si_screen *sscreen,
2099 struct si_shader_selector *sel,
2100 struct si_compiler_ctx_state *compiler_state,
2101 struct si_shader_key *key)
2102 {
2103 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2104
2105 if (!*mainp) {
2106 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2107
2108 if (!main_part)
2109 return false;
2110
2111 /* We can leave the fence as permanently signaled because the
2112 * main part becomes visible globally only after it has been
2113 * compiled. */
2114 util_queue_fence_init(&main_part->ready);
2115
2116 main_part->selector = sel;
2117 main_part->key.as_es = key->as_es;
2118 main_part->key.as_ls = key->as_ls;
2119 main_part->key.as_ngg = key->as_ngg;
2120 main_part->is_monolithic = false;
2121
2122 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
2123 main_part, &compiler_state->debug) != 0) {
2124 FREE(main_part);
2125 return false;
2126 }
2127 *mainp = main_part;
2128 }
2129 return true;
2130 }
2131
2132 /**
2133 * Select a shader variant according to the shader key.
2134 *
2135 * \param optimized_or_none If the key describes an optimized shader variant and
2136 * the compilation isn't finished, don't select any
2137 * shader and return an error.
2138 */
2139 int si_shader_select_with_key(struct si_screen *sscreen,
2140 struct si_shader_ctx_state *state,
2141 struct si_compiler_ctx_state *compiler_state,
2142 struct si_shader_key *key,
2143 int thread_index,
2144 bool optimized_or_none)
2145 {
2146 struct si_shader_selector *sel = state->cso;
2147 struct si_shader_selector *previous_stage_sel = NULL;
2148 struct si_shader *current = state->current;
2149 struct si_shader *iter, *shader = NULL;
2150
2151 again:
2152 /* Check if we don't need to change anything.
2153 * This path is also used for most shaders that don't need multiple
2154 * variants, it will cost just a computation of the key and this
2155 * test. */
2156 if (likely(current &&
2157 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2158 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2159 if (current->is_optimized) {
2160 if (optimized_or_none)
2161 return -1;
2162
2163 memset(&key->opt, 0, sizeof(key->opt));
2164 goto current_not_ready;
2165 }
2166
2167 util_queue_fence_wait(&current->ready);
2168 }
2169
2170 return current->compilation_failed ? -1 : 0;
2171 }
2172 current_not_ready:
2173
2174 /* This must be done before the mutex is locked, because async GS
2175 * compilation calls this function too, and therefore must enter
2176 * the mutex first.
2177 *
2178 * Only wait if we are in a draw call. Don't wait if we are
2179 * in a compiler thread.
2180 */
2181 if (thread_index < 0)
2182 util_queue_fence_wait(&sel->ready);
2183
2184 mtx_lock(&sel->mutex);
2185
2186 /* Find the shader variant. */
2187 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2188 /* Don't check the "current" shader. We checked it above. */
2189 if (current != iter &&
2190 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2191 mtx_unlock(&sel->mutex);
2192
2193 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2194 /* If it's an optimized shader and its compilation has
2195 * been started but isn't done, use the unoptimized
2196 * shader so as not to cause a stall due to compilation.
2197 */
2198 if (iter->is_optimized) {
2199 if (optimized_or_none)
2200 return -1;
2201 memset(&key->opt, 0, sizeof(key->opt));
2202 goto again;
2203 }
2204
2205 util_queue_fence_wait(&iter->ready);
2206 }
2207
2208 if (iter->compilation_failed) {
2209 return -1; /* skip the draw call */
2210 }
2211
2212 state->current = iter;
2213 return 0;
2214 }
2215 }
2216
2217 /* Build a new shader. */
2218 shader = CALLOC_STRUCT(si_shader);
2219 if (!shader) {
2220 mtx_unlock(&sel->mutex);
2221 return -ENOMEM;
2222 }
2223
2224 util_queue_fence_init(&shader->ready);
2225
2226 shader->selector = sel;
2227 shader->key = *key;
2228 shader->compiler_ctx_state = *compiler_state;
2229
2230 /* If this is a merged shader, get the first shader's selector. */
2231 if (sscreen->info.chip_class >= GFX9) {
2232 if (sel->type == PIPE_SHADER_TESS_CTRL)
2233 previous_stage_sel = key->part.tcs.ls;
2234 else if (sel->type == PIPE_SHADER_GEOMETRY)
2235 previous_stage_sel = key->part.gs.es;
2236
2237 /* We need to wait for the previous shader. */
2238 if (previous_stage_sel && thread_index < 0)
2239 util_queue_fence_wait(&previous_stage_sel->ready);
2240 }
2241
2242 bool is_pure_monolithic =
2243 sscreen->use_monolithic_shaders ||
2244 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2245
2246 /* Compile the main shader part if it doesn't exist. This can happen
2247 * if the initial guess was wrong.
2248 *
2249 * The prim discard CS doesn't need the main shader part.
2250 */
2251 if (!is_pure_monolithic &&
2252 !key->opt.vs_as_prim_discard_cs) {
2253 bool ok = true;
2254
2255 /* Make sure the main shader part is present. This is needed
2256 * for shaders that can be compiled as VS, LS, or ES, and only
2257 * one of them is compiled at creation.
2258 *
2259 * It is also needed for GS, which can be compiled as non-NGG
2260 * and NGG.
2261 *
2262 * For merged shaders, check that the starting shader's main
2263 * part is present.
2264 */
2265 if (previous_stage_sel) {
2266 struct si_shader_key shader1_key = zeroed;
2267
2268 if (sel->type == PIPE_SHADER_TESS_CTRL)
2269 shader1_key.as_ls = 1;
2270 else if (sel->type == PIPE_SHADER_GEOMETRY)
2271 shader1_key.as_es = 1;
2272 else
2273 assert(0);
2274
2275 if (sel->type == PIPE_SHADER_GEOMETRY &&
2276 previous_stage_sel->type == PIPE_SHADER_TESS_EVAL)
2277 shader1_key.as_ngg = key->as_ngg;
2278
2279 mtx_lock(&previous_stage_sel->mutex);
2280 ok = si_check_missing_main_part(sscreen,
2281 previous_stage_sel,
2282 compiler_state, &shader1_key);
2283 mtx_unlock(&previous_stage_sel->mutex);
2284 }
2285
2286 if (ok) {
2287 ok = si_check_missing_main_part(sscreen, sel,
2288 compiler_state, key);
2289 }
2290
2291 if (!ok) {
2292 FREE(shader);
2293 mtx_unlock(&sel->mutex);
2294 return -ENOMEM; /* skip the draw call */
2295 }
2296 }
2297
2298 /* Keep the reference to the 1st shader of merged shaders, so that
2299 * Gallium can't destroy it before we destroy the 2nd shader.
2300 *
2301 * Set sctx = NULL, because it's unused if we're not releasing
2302 * the shader, and we don't have any sctx here.
2303 */
2304 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2305 previous_stage_sel);
2306
2307 /* Monolithic-only shaders don't make a distinction between optimized
2308 * and unoptimized. */
2309 shader->is_monolithic =
2310 is_pure_monolithic ||
2311 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2312
2313 /* The prim discard CS is always optimized. */
2314 shader->is_optimized =
2315 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2316 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2317
2318 /* If it's an optimized shader, compile it asynchronously. */
2319 if (shader->is_optimized && thread_index < 0) {
2320 /* Compile it asynchronously. */
2321 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2322 shader, &shader->ready,
2323 si_build_shader_variant_low_priority, NULL);
2324
2325 /* Add only after the ready fence was reset, to guard against a
2326 * race with si_bind_XX_shader. */
2327 if (!sel->last_variant) {
2328 sel->first_variant = shader;
2329 sel->last_variant = shader;
2330 } else {
2331 sel->last_variant->next_variant = shader;
2332 sel->last_variant = shader;
2333 }
2334
2335 /* Use the default (unoptimized) shader for now. */
2336 memset(&key->opt, 0, sizeof(key->opt));
2337 mtx_unlock(&sel->mutex);
2338
2339 if (sscreen->options.sync_compile)
2340 util_queue_fence_wait(&shader->ready);
2341
2342 if (optimized_or_none)
2343 return -1;
2344 goto again;
2345 }
2346
2347 /* Reset the fence before adding to the variant list. */
2348 util_queue_fence_reset(&shader->ready);
2349
2350 if (!sel->last_variant) {
2351 sel->first_variant = shader;
2352 sel->last_variant = shader;
2353 } else {
2354 sel->last_variant->next_variant = shader;
2355 sel->last_variant = shader;
2356 }
2357
2358 mtx_unlock(&sel->mutex);
2359
2360 assert(!shader->is_optimized);
2361 si_build_shader_variant(shader, thread_index, false);
2362
2363 util_queue_fence_signal(&shader->ready);
2364
2365 if (!shader->compilation_failed)
2366 state->current = shader;
2367
2368 return shader->compilation_failed ? -1 : 0;
2369 }
2370
2371 static int si_shader_select(struct pipe_context *ctx,
2372 struct si_shader_ctx_state *state,
2373 union si_vgt_stages_key stages_key,
2374 struct si_compiler_ctx_state *compiler_state)
2375 {
2376 struct si_context *sctx = (struct si_context *)ctx;
2377 struct si_shader_key key;
2378
2379 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2380 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2381 &key, -1, false);
2382 }
2383
2384 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2385 bool streamout,
2386 struct si_shader_key *key)
2387 {
2388 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2389
2390 switch (info->processor) {
2391 case PIPE_SHADER_VERTEX:
2392 switch (next_shader) {
2393 case PIPE_SHADER_GEOMETRY:
2394 key->as_es = 1;
2395 break;
2396 case PIPE_SHADER_TESS_CTRL:
2397 case PIPE_SHADER_TESS_EVAL:
2398 key->as_ls = 1;
2399 break;
2400 default:
2401 /* If POSITION isn't written, it can only be a HW VS
2402 * if streamout is used. If streamout isn't used,
2403 * assume that it's a HW LS. (the next shader is TCS)
2404 * This heuristic is needed for separate shader objects.
2405 */
2406 if (!info->writes_position && !streamout)
2407 key->as_ls = 1;
2408 }
2409 break;
2410
2411 case PIPE_SHADER_TESS_EVAL:
2412 if (next_shader == PIPE_SHADER_GEOMETRY ||
2413 !info->writes_position)
2414 key->as_es = 1;
2415 break;
2416 }
2417 }
2418
2419 /**
2420 * Compile the main shader part or the monolithic shader as part of
2421 * si_shader_selector initialization. Since it can be done asynchronously,
2422 * there is no way to report compile failures to applications.
2423 */
2424 static void si_init_shader_selector_async(void *job, int thread_index)
2425 {
2426 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2427 struct si_screen *sscreen = sel->screen;
2428 struct ac_llvm_compiler *compiler;
2429 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2430
2431 assert(!debug->debug_message || debug->async);
2432 assert(thread_index >= 0);
2433 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2434 compiler = &sscreen->compiler[thread_index];
2435
2436 if (sel->nir) {
2437 /* TODO: GS always sets wave size = default. Legacy GS will have
2438 * incorrect subgroup_size and ballot_bit_size. */
2439 si_lower_nir(sel, si_get_wave_size(sscreen, sel->type, true, false));
2440 }
2441
2442 /* Compile the main shader part for use with a prolog and/or epilog.
2443 * If this fails, the driver will try to compile a monolithic shader
2444 * on demand.
2445 */
2446 if (!sscreen->use_monolithic_shaders) {
2447 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2448 void *ir_binary = NULL;
2449
2450 if (!shader) {
2451 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2452 return;
2453 }
2454
2455 /* We can leave the fence signaled because use of the default
2456 * main part is guarded by the selector's ready fence. */
2457 util_queue_fence_init(&shader->ready);
2458
2459 shader->selector = sel;
2460 shader->is_monolithic = false;
2461 si_parse_next_shader_property(&sel->info,
2462 sel->so.num_outputs != 0,
2463 &shader->key);
2464 if (sscreen->info.chip_class >= GFX10 &&
2465 ((sel->type == PIPE_SHADER_VERTEX &&
2466 !shader->key.as_ls && !shader->key.as_es) ||
2467 sel->type == PIPE_SHADER_TESS_EVAL ||
2468 sel->type == PIPE_SHADER_GEOMETRY))
2469 shader->key.as_ngg = 1;
2470
2471 if (sel->tokens || sel->nir)
2472 ir_binary = si_get_ir_binary(sel);
2473
2474 /* Try to load the shader from the shader cache. */
2475 mtx_lock(&sscreen->shader_cache_mutex);
2476
2477 if (ir_binary &&
2478 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2479 mtx_unlock(&sscreen->shader_cache_mutex);
2480 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2481 } else {
2482 mtx_unlock(&sscreen->shader_cache_mutex);
2483
2484 /* Compile the shader if it hasn't been loaded from the cache. */
2485 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2486 debug) != 0) {
2487 FREE(shader);
2488 FREE(ir_binary);
2489 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2490 return;
2491 }
2492
2493 if (ir_binary) {
2494 mtx_lock(&sscreen->shader_cache_mutex);
2495 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2496 FREE(ir_binary);
2497 mtx_unlock(&sscreen->shader_cache_mutex);
2498 }
2499 }
2500
2501 *si_get_main_shader_part(sel, &shader->key) = shader;
2502
2503 /* Unset "outputs_written" flags for outputs converted to
2504 * DEFAULT_VAL, so that later inter-shader optimizations don't
2505 * try to eliminate outputs that don't exist in the final
2506 * shader.
2507 *
2508 * This is only done if non-monolithic shaders are enabled.
2509 */
2510 if ((sel->type == PIPE_SHADER_VERTEX ||
2511 sel->type == PIPE_SHADER_TESS_EVAL) &&
2512 !shader->key.as_ls &&
2513 !shader->key.as_es) {
2514 unsigned i;
2515
2516 for (i = 0; i < sel->info.num_outputs; i++) {
2517 unsigned offset = shader->info.vs_output_param_offset[i];
2518
2519 if (offset <= AC_EXP_PARAM_OFFSET_31)
2520 continue;
2521
2522 unsigned name = sel->info.output_semantic_name[i];
2523 unsigned index = sel->info.output_semantic_index[i];
2524 unsigned id;
2525
2526 switch (name) {
2527 case TGSI_SEMANTIC_GENERIC:
2528 /* don't process indices the function can't handle */
2529 if (index >= SI_MAX_IO_GENERIC)
2530 break;
2531 /* fall through */
2532 default:
2533 id = si_shader_io_get_unique_index(name, index, true);
2534 sel->outputs_written_before_ps &= ~(1ull << id);
2535 break;
2536 case TGSI_SEMANTIC_POSITION: /* ignore these */
2537 case TGSI_SEMANTIC_PSIZE:
2538 case TGSI_SEMANTIC_CLIPVERTEX:
2539 case TGSI_SEMANTIC_EDGEFLAG:
2540 break;
2541 }
2542 }
2543 }
2544 }
2545
2546 /* The GS copy shader is always pre-compiled. */
2547 if (sel->type == PIPE_SHADER_GEOMETRY &&
2548 (sscreen->info.chip_class <= GFX9 || sel->tess_turns_off_ngg)) {
2549 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2550 if (!sel->gs_copy_shader) {
2551 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2552 return;
2553 }
2554
2555 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2556 }
2557 }
2558
2559 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2560 struct util_queue_fence *ready_fence,
2561 struct si_compiler_ctx_state *compiler_ctx_state,
2562 void *job, util_queue_execute_func execute)
2563 {
2564 util_queue_fence_init(ready_fence);
2565
2566 struct util_async_debug_callback async_debug;
2567 bool debug =
2568 (sctx->debug.debug_message && !sctx->debug.async) ||
2569 sctx->is_debug ||
2570 si_can_dump_shader(sctx->screen, processor);
2571
2572 if (debug) {
2573 u_async_debug_init(&async_debug);
2574 compiler_ctx_state->debug = async_debug.base;
2575 }
2576
2577 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2578 ready_fence, execute, NULL);
2579
2580 if (debug) {
2581 util_queue_fence_wait(ready_fence);
2582 u_async_debug_drain(&async_debug, &sctx->debug);
2583 u_async_debug_cleanup(&async_debug);
2584 }
2585
2586 if (sctx->screen->options.sync_compile)
2587 util_queue_fence_wait(ready_fence);
2588 }
2589
2590 /* Return descriptor slot usage masks from the given shader info. */
2591 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2592 uint32_t *const_and_shader_buffers,
2593 uint64_t *samplers_and_images)
2594 {
2595 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2596
2597 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2598 num_constbufs = util_last_bit(info->const_buffers_declared);
2599 /* two 8-byte images share one 16-byte slot */
2600 num_images = align(util_last_bit(info->images_declared), 2);
2601 num_samplers = util_last_bit(info->samplers_declared);
2602
2603 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2604 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2605 *const_and_shader_buffers =
2606 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2607
2608 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2609 start = si_get_image_slot(num_images - 1) / 2;
2610 *samplers_and_images =
2611 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2612 }
2613
2614 static void *si_create_shader_selector(struct pipe_context *ctx,
2615 const struct pipe_shader_state *state)
2616 {
2617 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2618 struct si_context *sctx = (struct si_context*)ctx;
2619 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2620 int i;
2621
2622 if (!sel)
2623 return NULL;
2624
2625 pipe_reference_init(&sel->reference, 1);
2626 sel->screen = sscreen;
2627 sel->compiler_ctx_state.debug = sctx->debug;
2628 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2629
2630 sel->so = state->stream_output;
2631
2632 if (state->type == PIPE_SHADER_IR_TGSI &&
2633 !sscreen->options.always_nir) {
2634 sel->tokens = tgsi_dup_tokens(state->tokens);
2635 if (!sel->tokens) {
2636 FREE(sel);
2637 return NULL;
2638 }
2639
2640 tgsi_scan_shader(state->tokens, &sel->info);
2641 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2642
2643 /* Fixup for TGSI: Set which opcode uses which (i,j) pair. */
2644 if (sel->info.uses_persp_opcode_interp_centroid)
2645 sel->info.uses_persp_centroid = true;
2646
2647 if (sel->info.uses_linear_opcode_interp_centroid)
2648 sel->info.uses_linear_centroid = true;
2649
2650 if (sel->info.uses_persp_opcode_interp_offset ||
2651 sel->info.uses_persp_opcode_interp_sample)
2652 sel->info.uses_persp_center = true;
2653
2654 if (sel->info.uses_linear_opcode_interp_offset ||
2655 sel->info.uses_linear_opcode_interp_sample)
2656 sel->info.uses_linear_center = true;
2657 } else {
2658 if (state->type == PIPE_SHADER_IR_TGSI) {
2659 sel->nir = tgsi_to_nir(state->tokens, ctx->screen);
2660 } else {
2661 assert(state->type == PIPE_SHADER_IR_NIR);
2662 sel->nir = state->ir.nir;
2663 }
2664
2665 si_nir_lower_ps_inputs(sel->nir);
2666 si_nir_opts(sel->nir);
2667 si_nir_scan_shader(sel->nir, &sel->info);
2668 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2669 }
2670
2671 sel->type = sel->info.processor;
2672 p_atomic_inc(&sscreen->num_shaders_created);
2673 si_get_active_slot_masks(&sel->info,
2674 &sel->active_const_and_shader_buffers,
2675 &sel->active_samplers_and_images);
2676
2677 /* Record which streamout buffers are enabled. */
2678 for (i = 0; i < sel->so.num_outputs; i++) {
2679 sel->enabled_streamout_buffer_mask |=
2680 (1 << sel->so.output[i].output_buffer) <<
2681 (sel->so.output[i].stream * 4);
2682 }
2683
2684 /* The prolog is a no-op if there are no inputs. */
2685 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2686 sel->info.num_inputs &&
2687 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2688
2689 sel->force_correct_derivs_after_kill =
2690 sel->type == PIPE_SHADER_FRAGMENT &&
2691 sel->info.uses_derivatives &&
2692 sel->info.uses_kill &&
2693 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2694
2695 sel->prim_discard_cs_allowed =
2696 sel->type == PIPE_SHADER_VERTEX &&
2697 !sel->info.uses_bindless_images &&
2698 !sel->info.uses_bindless_samplers &&
2699 !sel->info.writes_memory &&
2700 !sel->info.writes_viewport_index &&
2701 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2702 !sel->so.num_outputs;
2703
2704 if (sel->type == PIPE_SHADER_VERTEX &&
2705 sel->info.writes_edgeflag) {
2706 if (sscreen->info.chip_class >= GFX10)
2707 sel->ngg_writes_edgeflag = true;
2708 else
2709 sel->pos_writes_edgeflag = true;
2710 }
2711
2712 switch (sel->type) {
2713 case PIPE_SHADER_GEOMETRY:
2714 sel->gs_output_prim =
2715 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2716
2717 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2718 sel->rast_prim = sel->gs_output_prim;
2719 if (util_rast_prim_is_triangles(sel->rast_prim))
2720 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2721
2722 sel->gs_max_out_vertices =
2723 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2724 sel->gs_num_invocations =
2725 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2726 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2727 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2728 sel->gs_max_out_vertices;
2729
2730 sel->max_gs_stream = 0;
2731 for (i = 0; i < sel->so.num_outputs; i++)
2732 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2733 sel->so.output[i].stream);
2734
2735 sel->gs_input_verts_per_prim =
2736 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2737
2738 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2739 sel->tess_turns_off_ngg =
2740 (sscreen->info.family == CHIP_NAVI10 ||
2741 sscreen->info.family == CHIP_NAVI12 ||
2742 sscreen->info.family == CHIP_NAVI14) &&
2743 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2744 break;
2745
2746 case PIPE_SHADER_TESS_CTRL:
2747 /* Always reserve space for these. */
2748 sel->patch_outputs_written |=
2749 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2750 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2751 /* fall through */
2752 case PIPE_SHADER_VERTEX:
2753 case PIPE_SHADER_TESS_EVAL:
2754 for (i = 0; i < sel->info.num_outputs; i++) {
2755 unsigned name = sel->info.output_semantic_name[i];
2756 unsigned index = sel->info.output_semantic_index[i];
2757
2758 switch (name) {
2759 case TGSI_SEMANTIC_TESSINNER:
2760 case TGSI_SEMANTIC_TESSOUTER:
2761 case TGSI_SEMANTIC_PATCH:
2762 sel->patch_outputs_written |=
2763 1ull << si_shader_io_get_unique_index_patch(name, index);
2764 break;
2765
2766 case TGSI_SEMANTIC_GENERIC:
2767 /* don't process indices the function can't handle */
2768 if (index >= SI_MAX_IO_GENERIC)
2769 break;
2770 /* fall through */
2771 default:
2772 sel->outputs_written |=
2773 1ull << si_shader_io_get_unique_index(name, index, false);
2774 sel->outputs_written_before_ps |=
2775 1ull << si_shader_io_get_unique_index(name, index, true);
2776 break;
2777 case TGSI_SEMANTIC_EDGEFLAG:
2778 break;
2779 }
2780 }
2781 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2782 sel->lshs_vertex_stride = sel->esgs_itemsize;
2783
2784 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2785 * will start on a different bank. (except for the maximum 32*16).
2786 */
2787 if (sel->lshs_vertex_stride < 32*16)
2788 sel->lshs_vertex_stride += 4;
2789
2790 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2791 * conflicts, i.e. each vertex will start at a different bank.
2792 */
2793 if (sctx->chip_class >= GFX9)
2794 sel->esgs_itemsize += 4;
2795
2796 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2797
2798 /* Only for TES: */
2799 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2800 sel->rast_prim = PIPE_PRIM_POINTS;
2801 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2802 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2803 else
2804 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2805 break;
2806
2807 case PIPE_SHADER_FRAGMENT:
2808 for (i = 0; i < sel->info.num_inputs; i++) {
2809 unsigned name = sel->info.input_semantic_name[i];
2810 unsigned index = sel->info.input_semantic_index[i];
2811
2812 switch (name) {
2813 case TGSI_SEMANTIC_GENERIC:
2814 /* don't process indices the function can't handle */
2815 if (index >= SI_MAX_IO_GENERIC)
2816 break;
2817 /* fall through */
2818 default:
2819 sel->inputs_read |=
2820 1ull << si_shader_io_get_unique_index(name, index, true);
2821 break;
2822 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2823 break;
2824 }
2825 }
2826
2827 for (i = 0; i < 8; i++)
2828 if (sel->info.colors_written & (1 << i))
2829 sel->colors_written_4bit |= 0xf << (4 * i);
2830
2831 for (i = 0; i < sel->info.num_inputs; i++) {
2832 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2833 int index = sel->info.input_semantic_index[i];
2834 sel->color_attr_index[index] = i;
2835 }
2836 }
2837 break;
2838 default:;
2839 }
2840
2841 /* PA_CL_VS_OUT_CNTL */
2842 bool misc_vec_ena =
2843 sel->info.writes_psize || sel->pos_writes_edgeflag ||
2844 sel->info.writes_layer || sel->info.writes_viewport_index;
2845 sel->pa_cl_vs_out_cntl =
2846 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2847 S_02881C_USE_VTX_EDGE_FLAG(sel->pos_writes_edgeflag) |
2848 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2849 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2850 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2851 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2852 sel->clipdist_mask = sel->info.writes_clipvertex ?
2853 SIX_BITS : sel->info.clipdist_writemask;
2854 sel->culldist_mask = sel->info.culldist_writemask <<
2855 sel->info.num_written_clipdistance;
2856
2857 /* DB_SHADER_CONTROL */
2858 sel->db_shader_control =
2859 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2860 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2861 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2862 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2863
2864 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2865 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2866 sel->db_shader_control |=
2867 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2868 break;
2869 case TGSI_FS_DEPTH_LAYOUT_LESS:
2870 sel->db_shader_control |=
2871 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2872 break;
2873 }
2874
2875 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2876 *
2877 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2878 * --|-----------|------------|------------|--------------------|-------------------|-------------
2879 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2880 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2881 * 2 | false | true | n/a | LateZ | 1 | 0
2882 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2883 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2884 *
2885 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2886 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2887 *
2888 * Don't use ReZ without profiling !!!
2889 *
2890 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2891 * shaders.
2892 */
2893 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2894 /* Cases 3, 4. */
2895 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2896 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2897 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2898 } else if (sel->info.writes_memory) {
2899 /* Case 2. */
2900 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2901 S_02880C_EXEC_ON_HIER_FAIL(1);
2902 } else {
2903 /* Case 1. */
2904 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2905 }
2906
2907 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
2908 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2909
2910 (void) mtx_init(&sel->mutex, mtx_plain);
2911
2912 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2913 &sel->compiler_ctx_state, sel,
2914 si_init_shader_selector_async);
2915 return sel;
2916 }
2917
2918 static void si_update_streamout_state(struct si_context *sctx)
2919 {
2920 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2921
2922 if (!shader_with_so)
2923 return;
2924
2925 sctx->streamout.enabled_stream_buffers_mask =
2926 shader_with_so->enabled_streamout_buffer_mask;
2927 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2928 }
2929
2930 static void si_update_clip_regs(struct si_context *sctx,
2931 struct si_shader_selector *old_hw_vs,
2932 struct si_shader *old_hw_vs_variant,
2933 struct si_shader_selector *next_hw_vs,
2934 struct si_shader *next_hw_vs_variant)
2935 {
2936 if (next_hw_vs &&
2937 (!old_hw_vs ||
2938 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2939 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2940 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2941 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2942 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2943 !old_hw_vs_variant ||
2944 !next_hw_vs_variant ||
2945 old_hw_vs_variant->key.opt.clip_disable !=
2946 next_hw_vs_variant->key.opt.clip_disable))
2947 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2948 }
2949
2950 static void si_update_common_shader_state(struct si_context *sctx)
2951 {
2952 sctx->uses_bindless_samplers =
2953 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2954 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2955 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2956 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2957 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2958 sctx->uses_bindless_images =
2959 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2960 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2961 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2962 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2963 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2964 sctx->do_update_shaders = true;
2965 }
2966
2967 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2968 {
2969 struct si_context *sctx = (struct si_context *)ctx;
2970 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2971 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2972 struct si_shader_selector *sel = state;
2973
2974 if (sctx->vs_shader.cso == sel)
2975 return;
2976
2977 sctx->vs_shader.cso = sel;
2978 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2979 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2980
2981 si_update_common_shader_state(sctx);
2982 si_update_vs_viewport_state(sctx);
2983 si_set_active_descriptors_for_shader(sctx, sel);
2984 si_update_streamout_state(sctx);
2985 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2986 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2987 }
2988
2989 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2990 {
2991 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2992 (sctx->tes_shader.cso &&
2993 sctx->tes_shader.cso->info.uses_primid) ||
2994 (sctx->tcs_shader.cso &&
2995 sctx->tcs_shader.cso->info.uses_primid) ||
2996 (sctx->gs_shader.cso &&
2997 sctx->gs_shader.cso->info.uses_primid) ||
2998 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2999 sctx->ps_shader.cso->info.uses_primid);
3000 }
3001
3002 static bool si_update_ngg(struct si_context *sctx)
3003 {
3004 if (sctx->chip_class <= GFX9)
3005 return false;
3006
3007 bool new_ngg = true;
3008
3009 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
3010 sctx->gs_shader.cso->tess_turns_off_ngg)
3011 new_ngg = false;
3012
3013 if (new_ngg != sctx->ngg) {
3014 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3015 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3016 * pointers are set.
3017 */
3018 if ((sctx->family == CHIP_NAVI10 ||
3019 sctx->family == CHIP_NAVI12 ||
3020 sctx->family == CHIP_NAVI14) &&
3021 !new_ngg)
3022 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
3023
3024 sctx->ngg = new_ngg;
3025 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3026 return true;
3027 }
3028 return false;
3029 }
3030
3031 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3032 {
3033 struct si_context *sctx = (struct si_context *)ctx;
3034 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3035 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3036 struct si_shader_selector *sel = state;
3037 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3038 bool ngg_changed;
3039
3040 if (sctx->gs_shader.cso == sel)
3041 return;
3042
3043 sctx->gs_shader.cso = sel;
3044 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3045 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3046
3047 si_update_common_shader_state(sctx);
3048 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3049
3050 ngg_changed = si_update_ngg(sctx);
3051 if (ngg_changed || enable_changed)
3052 si_shader_change_notify(sctx);
3053 if (enable_changed) {
3054 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3055 si_update_tess_uses_prim_id(sctx);
3056 }
3057 si_update_vs_viewport_state(sctx);
3058 si_set_active_descriptors_for_shader(sctx, sel);
3059 si_update_streamout_state(sctx);
3060 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3061 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3062 }
3063
3064 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3065 {
3066 struct si_context *sctx = (struct si_context *)ctx;
3067 struct si_shader_selector *sel = state;
3068 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3069
3070 if (sctx->tcs_shader.cso == sel)
3071 return;
3072
3073 sctx->tcs_shader.cso = sel;
3074 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3075 si_update_tess_uses_prim_id(sctx);
3076
3077 si_update_common_shader_state(sctx);
3078
3079 if (enable_changed)
3080 sctx->last_tcs = NULL; /* invalidate derived tess state */
3081
3082 si_set_active_descriptors_for_shader(sctx, sel);
3083 }
3084
3085 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3086 {
3087 struct si_context *sctx = (struct si_context *)ctx;
3088 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3089 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3090 struct si_shader_selector *sel = state;
3091 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3092
3093 if (sctx->tes_shader.cso == sel)
3094 return;
3095
3096 sctx->tes_shader.cso = sel;
3097 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3098 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3099 si_update_tess_uses_prim_id(sctx);
3100
3101 si_update_common_shader_state(sctx);
3102 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3103
3104 if (enable_changed) {
3105 si_update_ngg(sctx);
3106 si_shader_change_notify(sctx);
3107 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3108 }
3109 si_update_vs_viewport_state(sctx);
3110 si_set_active_descriptors_for_shader(sctx, sel);
3111 si_update_streamout_state(sctx);
3112 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3113 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3114 }
3115
3116 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3117 {
3118 struct si_context *sctx = (struct si_context *)ctx;
3119 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3120 struct si_shader_selector *sel = state;
3121
3122 /* skip if supplied shader is one already in use */
3123 if (old_sel == sel)
3124 return;
3125
3126 sctx->ps_shader.cso = sel;
3127 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3128
3129 si_update_common_shader_state(sctx);
3130 if (sel) {
3131 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3132 si_update_tess_uses_prim_id(sctx);
3133
3134 if (!old_sel ||
3135 old_sel->info.colors_written != sel->info.colors_written)
3136 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3137
3138 if (sctx->screen->has_out_of_order_rast &&
3139 (!old_sel ||
3140 old_sel->info.writes_memory != sel->info.writes_memory ||
3141 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3142 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3143 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3144 }
3145 si_set_active_descriptors_for_shader(sctx, sel);
3146 si_update_ps_colorbuf0_slot(sctx);
3147 }
3148
3149 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3150 {
3151 if (shader->is_optimized) {
3152 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3153 &shader->ready);
3154 }
3155
3156 util_queue_fence_destroy(&shader->ready);
3157
3158 if (shader->pm4) {
3159 /* If destroyed shaders were not unbound, the next compiled
3160 * shader variant could get the same pointer address and so
3161 * binding it to the same shader stage would be considered
3162 * a no-op, causing random behavior.
3163 */
3164 switch (shader->selector->type) {
3165 case PIPE_SHADER_VERTEX:
3166 if (shader->key.as_ls) {
3167 assert(sctx->chip_class <= GFX8);
3168 si_pm4_delete_state(sctx, ls, shader->pm4);
3169 } else if (shader->key.as_es) {
3170 assert(sctx->chip_class <= GFX8);
3171 si_pm4_delete_state(sctx, es, shader->pm4);
3172 } else if (shader->key.as_ngg) {
3173 si_pm4_delete_state(sctx, gs, shader->pm4);
3174 } else {
3175 si_pm4_delete_state(sctx, vs, shader->pm4);
3176 }
3177 break;
3178 case PIPE_SHADER_TESS_CTRL:
3179 si_pm4_delete_state(sctx, hs, shader->pm4);
3180 break;
3181 case PIPE_SHADER_TESS_EVAL:
3182 if (shader->key.as_es) {
3183 assert(sctx->chip_class <= GFX8);
3184 si_pm4_delete_state(sctx, es, shader->pm4);
3185 } else if (shader->key.as_ngg) {
3186 si_pm4_delete_state(sctx, gs, shader->pm4);
3187 } else {
3188 si_pm4_delete_state(sctx, vs, shader->pm4);
3189 }
3190 break;
3191 case PIPE_SHADER_GEOMETRY:
3192 if (shader->is_gs_copy_shader)
3193 si_pm4_delete_state(sctx, vs, shader->pm4);
3194 else
3195 si_pm4_delete_state(sctx, gs, shader->pm4);
3196 break;
3197 case PIPE_SHADER_FRAGMENT:
3198 si_pm4_delete_state(sctx, ps, shader->pm4);
3199 break;
3200 default:;
3201 }
3202 }
3203
3204 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3205 si_shader_destroy(shader);
3206 free(shader);
3207 }
3208
3209 void si_destroy_shader_selector(struct si_context *sctx,
3210 struct si_shader_selector *sel)
3211 {
3212 struct si_shader *p = sel->first_variant, *c;
3213 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3214 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3215 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3216 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3217 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3218 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3219 };
3220
3221 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3222
3223 if (current_shader[sel->type]->cso == sel) {
3224 current_shader[sel->type]->cso = NULL;
3225 current_shader[sel->type]->current = NULL;
3226 }
3227
3228 while (p) {
3229 c = p->next_variant;
3230 si_delete_shader(sctx, p);
3231 p = c;
3232 }
3233
3234 if (sel->main_shader_part)
3235 si_delete_shader(sctx, sel->main_shader_part);
3236 if (sel->main_shader_part_ls)
3237 si_delete_shader(sctx, sel->main_shader_part_ls);
3238 if (sel->main_shader_part_es)
3239 si_delete_shader(sctx, sel->main_shader_part_es);
3240 if (sel->main_shader_part_ngg)
3241 si_delete_shader(sctx, sel->main_shader_part_ngg);
3242 if (sel->gs_copy_shader)
3243 si_delete_shader(sctx, sel->gs_copy_shader);
3244
3245 util_queue_fence_destroy(&sel->ready);
3246 mtx_destroy(&sel->mutex);
3247 free(sel->tokens);
3248 ralloc_free(sel->nir);
3249 free(sel);
3250 }
3251
3252 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3253 {
3254 struct si_context *sctx = (struct si_context *)ctx;
3255 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3256
3257 si_shader_selector_reference(sctx, &sel, NULL);
3258 }
3259
3260 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3261 struct si_shader *vs, unsigned name,
3262 unsigned index, unsigned interpolate)
3263 {
3264 struct tgsi_shader_info *vsinfo = &vs->selector->info;
3265 unsigned j, offset, ps_input_cntl = 0;
3266
3267 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3268 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3269 name == TGSI_SEMANTIC_PRIMID)
3270 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3271
3272 if (name == TGSI_SEMANTIC_PCOORD ||
3273 (name == TGSI_SEMANTIC_TEXCOORD &&
3274 sctx->sprite_coord_enable & (1 << index))) {
3275 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3276 }
3277
3278 for (j = 0; j < vsinfo->num_outputs; j++) {
3279 if (name == vsinfo->output_semantic_name[j] &&
3280 index == vsinfo->output_semantic_index[j]) {
3281 offset = vs->info.vs_output_param_offset[j];
3282
3283 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3284 /* The input is loaded from parameter memory. */
3285 ps_input_cntl |= S_028644_OFFSET(offset);
3286 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3287 if (offset == AC_EXP_PARAM_UNDEFINED) {
3288 /* This can happen with depth-only rendering. */
3289 offset = 0;
3290 } else {
3291 /* The input is a DEFAULT_VAL constant. */
3292 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3293 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3294 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3295 }
3296
3297 ps_input_cntl = S_028644_OFFSET(0x20) |
3298 S_028644_DEFAULT_VAL(offset);
3299 }
3300 break;
3301 }
3302 }
3303
3304 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3305 /* PrimID is written after the last output when HW VS is used. */
3306 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3307 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3308 /* No corresponding output found, load defaults into input.
3309 * Don't set any other bits.
3310 * (FLAT_SHADE=1 completely changes behavior) */
3311 ps_input_cntl = S_028644_OFFSET(0x20);
3312 /* D3D 9 behaviour. GL is undefined */
3313 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3314 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3315 }
3316 return ps_input_cntl;
3317 }
3318
3319 static void si_emit_spi_map(struct si_context *sctx)
3320 {
3321 struct si_shader *ps = sctx->ps_shader.current;
3322 struct si_shader *vs = si_get_vs_state(sctx);
3323 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3324 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3325 unsigned spi_ps_input_cntl[32];
3326
3327 if (!ps || !ps->selector->info.num_inputs)
3328 return;
3329
3330 num_interp = si_get_ps_num_interp(ps);
3331 assert(num_interp > 0);
3332
3333 for (i = 0; i < psinfo->num_inputs; i++) {
3334 unsigned name = psinfo->input_semantic_name[i];
3335 unsigned index = psinfo->input_semantic_index[i];
3336 unsigned interpolate = psinfo->input_interpolate[i];
3337
3338 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3339 index, interpolate);
3340
3341 if (name == TGSI_SEMANTIC_COLOR) {
3342 assert(index < ARRAY_SIZE(bcol_interp));
3343 bcol_interp[index] = interpolate;
3344 }
3345 }
3346
3347 if (ps->key.part.ps.prolog.color_two_side) {
3348 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3349
3350 for (i = 0; i < 2; i++) {
3351 if (!(psinfo->colors_read & (0xf << (i * 4))))
3352 continue;
3353
3354 spi_ps_input_cntl[num_written++] =
3355 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3356
3357 }
3358 }
3359 assert(num_interp == num_written);
3360
3361 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3362 /* Dota 2: Only ~16% of SPI map updates set different values. */
3363 /* Talos: Only ~9% of SPI map updates set different values. */
3364 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3365 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3366 spi_ps_input_cntl,
3367 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3368
3369 if (initial_cdw != sctx->gfx_cs->current.cdw)
3370 sctx->context_roll = true;
3371 }
3372
3373 /**
3374 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3375 */
3376 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3377 {
3378 if (sctx->init_config_has_vgt_flush)
3379 return;
3380
3381 /* Done by Vulkan before VGT_FLUSH. */
3382 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3383 si_pm4_cmd_add(sctx->init_config,
3384 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3385 si_pm4_cmd_end(sctx->init_config, false);
3386
3387 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3388 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3389 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3390 si_pm4_cmd_end(sctx->init_config, false);
3391 sctx->init_config_has_vgt_flush = true;
3392 }
3393
3394 /* Initialize state related to ESGS / GSVS ring buffers */
3395 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3396 {
3397 struct si_shader_selector *es =
3398 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3399 struct si_shader_selector *gs = sctx->gs_shader.cso;
3400 struct si_pm4_state *pm4;
3401
3402 /* Chip constants. */
3403 unsigned num_se = sctx->screen->info.max_se;
3404 unsigned wave_size = 64;
3405 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3406 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3407 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3408 */
3409 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3410 unsigned alignment = 256 * num_se;
3411 /* The maximum size is 63.999 MB per SE. */
3412 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3413
3414 /* Calculate the minimum size. */
3415 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3416 wave_size, alignment);
3417
3418 /* These are recommended sizes, not minimum sizes. */
3419 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3420 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3421 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3422 gs->max_gsvs_emit_size;
3423
3424 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3425 esgs_ring_size = align(esgs_ring_size, alignment);
3426 gsvs_ring_size = align(gsvs_ring_size, alignment);
3427
3428 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3429 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3430
3431 /* Some rings don't have to be allocated if shaders don't use them.
3432 * (e.g. no varyings between ES and GS or GS and VS)
3433 *
3434 * GFX9 doesn't have the ESGS ring.
3435 */
3436 bool update_esgs = sctx->chip_class <= GFX8 &&
3437 esgs_ring_size &&
3438 (!sctx->esgs_ring ||
3439 sctx->esgs_ring->width0 < esgs_ring_size);
3440 bool update_gsvs = gsvs_ring_size &&
3441 (!sctx->gsvs_ring ||
3442 sctx->gsvs_ring->width0 < gsvs_ring_size);
3443
3444 if (!update_esgs && !update_gsvs)
3445 return true;
3446
3447 if (update_esgs) {
3448 pipe_resource_reference(&sctx->esgs_ring, NULL);
3449 sctx->esgs_ring =
3450 pipe_aligned_buffer_create(sctx->b.screen,
3451 SI_RESOURCE_FLAG_UNMAPPABLE,
3452 PIPE_USAGE_DEFAULT,
3453 esgs_ring_size, alignment);
3454 if (!sctx->esgs_ring)
3455 return false;
3456 }
3457
3458 if (update_gsvs) {
3459 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3460 sctx->gsvs_ring =
3461 pipe_aligned_buffer_create(sctx->b.screen,
3462 SI_RESOURCE_FLAG_UNMAPPABLE,
3463 PIPE_USAGE_DEFAULT,
3464 gsvs_ring_size, alignment);
3465 if (!sctx->gsvs_ring)
3466 return false;
3467 }
3468
3469 /* Create the "init_config_gs_rings" state. */
3470 pm4 = CALLOC_STRUCT(si_pm4_state);
3471 if (!pm4)
3472 return false;
3473
3474 if (sctx->chip_class >= GFX7) {
3475 if (sctx->esgs_ring) {
3476 assert(sctx->chip_class <= GFX8);
3477 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3478 sctx->esgs_ring->width0 / 256);
3479 }
3480 if (sctx->gsvs_ring)
3481 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3482 sctx->gsvs_ring->width0 / 256);
3483 } else {
3484 if (sctx->esgs_ring)
3485 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3486 sctx->esgs_ring->width0 / 256);
3487 if (sctx->gsvs_ring)
3488 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3489 sctx->gsvs_ring->width0 / 256);
3490 }
3491
3492 /* Set the state. */
3493 if (sctx->init_config_gs_rings)
3494 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3495 sctx->init_config_gs_rings = pm4;
3496
3497 if (!sctx->init_config_has_vgt_flush) {
3498 si_init_config_add_vgt_flush(sctx);
3499 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3500 }
3501
3502 /* Flush the context to re-emit both init_config states. */
3503 sctx->initial_gfx_cs_size = 0; /* force flush */
3504 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3505
3506 /* Set ring bindings. */
3507 if (sctx->esgs_ring) {
3508 assert(sctx->chip_class <= GFX8);
3509 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3510 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3511 true, true, 4, 64, 0);
3512 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3513 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3514 false, false, 0, 0, 0);
3515 }
3516 if (sctx->gsvs_ring) {
3517 si_set_ring_buffer(sctx, SI_RING_GSVS,
3518 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3519 false, false, 0, 0, 0);
3520 }
3521
3522 return true;
3523 }
3524
3525 static void si_shader_lock(struct si_shader *shader)
3526 {
3527 mtx_lock(&shader->selector->mutex);
3528 if (shader->previous_stage_sel) {
3529 assert(shader->previous_stage_sel != shader->selector);
3530 mtx_lock(&shader->previous_stage_sel->mutex);
3531 }
3532 }
3533
3534 static void si_shader_unlock(struct si_shader *shader)
3535 {
3536 if (shader->previous_stage_sel)
3537 mtx_unlock(&shader->previous_stage_sel->mutex);
3538 mtx_unlock(&shader->selector->mutex);
3539 }
3540
3541 /**
3542 * @returns 1 if \p sel has been updated to use a new scratch buffer
3543 * 0 if not
3544 * < 0 if there was a failure
3545 */
3546 static int si_update_scratch_buffer(struct si_context *sctx,
3547 struct si_shader *shader)
3548 {
3549 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3550
3551 if (!shader)
3552 return 0;
3553
3554 /* This shader doesn't need a scratch buffer */
3555 if (shader->config.scratch_bytes_per_wave == 0)
3556 return 0;
3557
3558 /* Prevent race conditions when updating:
3559 * - si_shader::scratch_bo
3560 * - si_shader::binary::code
3561 * - si_shader::previous_stage::binary::code.
3562 */
3563 si_shader_lock(shader);
3564
3565 /* This shader is already configured to use the current
3566 * scratch buffer. */
3567 if (shader->scratch_bo == sctx->scratch_buffer) {
3568 si_shader_unlock(shader);
3569 return 0;
3570 }
3571
3572 assert(sctx->scratch_buffer);
3573
3574 /* Replace the shader bo with a new bo that has the relocs applied. */
3575 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3576 si_shader_unlock(shader);
3577 return -1;
3578 }
3579
3580 /* Update the shader state to use the new shader bo. */
3581 si_shader_init_pm4_state(sctx->screen, shader);
3582
3583 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3584
3585 si_shader_unlock(shader);
3586 return 1;
3587 }
3588
3589 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3590 {
3591 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3592 }
3593
3594 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3595 {
3596 return shader ? shader->config.scratch_bytes_per_wave : 0;
3597 }
3598
3599 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3600 {
3601 if (!sctx->tes_shader.cso)
3602 return NULL; /* tessellation disabled */
3603
3604 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3605 sctx->fixed_func_tcs_shader.current;
3606 }
3607
3608 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3609 {
3610 unsigned bytes = 0;
3611
3612 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3613 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3614 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3615 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3616
3617 if (sctx->tes_shader.cso) {
3618 struct si_shader *tcs = si_get_tcs_current(sctx);
3619
3620 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3621 }
3622 return bytes;
3623 }
3624
3625 static bool si_update_scratch_relocs(struct si_context *sctx)
3626 {
3627 struct si_shader *tcs = si_get_tcs_current(sctx);
3628 int r;
3629
3630 /* Update the shaders, so that they are using the latest scratch.
3631 * The scratch buffer may have been changed since these shaders were
3632 * last used, so we still need to try to update them, even if they
3633 * require scratch buffers smaller than the current size.
3634 */
3635 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3636 if (r < 0)
3637 return false;
3638 if (r == 1)
3639 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3640
3641 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3642 if (r < 0)
3643 return false;
3644 if (r == 1)
3645 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3646
3647 r = si_update_scratch_buffer(sctx, tcs);
3648 if (r < 0)
3649 return false;
3650 if (r == 1)
3651 si_pm4_bind_state(sctx, hs, tcs->pm4);
3652
3653 /* VS can be bound as LS, ES, or VS. */
3654 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3655 if (r < 0)
3656 return false;
3657 if (r == 1) {
3658 if (sctx->vs_shader.current->key.as_ls)
3659 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3660 else if (sctx->vs_shader.current->key.as_es)
3661 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3662 else if (sctx->vs_shader.current->key.as_ngg)
3663 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3664 else
3665 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3666 }
3667
3668 /* TES can be bound as ES or VS. */
3669 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3670 if (r < 0)
3671 return false;
3672 if (r == 1) {
3673 if (sctx->tes_shader.current->key.as_es)
3674 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3675 else if (sctx->tes_shader.current->key.as_ngg)
3676 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3677 else
3678 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3679 }
3680
3681 return true;
3682 }
3683
3684 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3685 {
3686 unsigned current_scratch_buffer_size =
3687 si_get_current_scratch_buffer_size(sctx);
3688 unsigned scratch_bytes_per_wave =
3689 si_get_max_scratch_bytes_per_wave(sctx);
3690 unsigned scratch_needed_size = scratch_bytes_per_wave *
3691 sctx->scratch_waves;
3692 unsigned spi_tmpring_size;
3693
3694 if (scratch_needed_size > 0) {
3695 if (scratch_needed_size > current_scratch_buffer_size) {
3696 /* Create a bigger scratch buffer */
3697 si_resource_reference(&sctx->scratch_buffer, NULL);
3698
3699 sctx->scratch_buffer =
3700 si_aligned_buffer_create(&sctx->screen->b,
3701 SI_RESOURCE_FLAG_UNMAPPABLE,
3702 PIPE_USAGE_DEFAULT,
3703 scratch_needed_size, 256);
3704 if (!sctx->scratch_buffer)
3705 return false;
3706
3707 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3708 si_context_add_resource_size(sctx,
3709 &sctx->scratch_buffer->b.b);
3710 }
3711
3712 if (!si_update_scratch_relocs(sctx))
3713 return false;
3714 }
3715
3716 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3717 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3718 "scratch size should already be aligned correctly.");
3719
3720 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3721 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3722 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3723 sctx->spi_tmpring_size = spi_tmpring_size;
3724 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3725 }
3726 return true;
3727 }
3728
3729 static void si_init_tess_factor_ring(struct si_context *sctx)
3730 {
3731 assert(!sctx->tess_rings);
3732
3733 /* The address must be aligned to 2^19, because the shader only
3734 * receives the high 13 bits.
3735 */
3736 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3737 SI_RESOURCE_FLAG_32BIT,
3738 PIPE_USAGE_DEFAULT,
3739 sctx->screen->tess_offchip_ring_size +
3740 sctx->screen->tess_factor_ring_size,
3741 1 << 19);
3742 if (!sctx->tess_rings)
3743 return;
3744
3745 si_init_config_add_vgt_flush(sctx);
3746
3747 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3748 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3749
3750 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3751 sctx->screen->tess_offchip_ring_size;
3752
3753 /* Append these registers to the init config state. */
3754 if (sctx->chip_class >= GFX7) {
3755 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3756 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3757 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3758 factor_va >> 8);
3759 if (sctx->chip_class >= GFX10)
3760 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3761 S_030984_BASE_HI(factor_va >> 40));
3762 else if (sctx->chip_class == GFX9)
3763 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3764 S_030944_BASE_HI(factor_va >> 40));
3765 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3766 sctx->screen->vgt_hs_offchip_param);
3767 } else {
3768 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3769 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3770 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3771 factor_va >> 8);
3772 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3773 sctx->screen->vgt_hs_offchip_param);
3774 }
3775
3776 /* Flush the context to re-emit the init_config state.
3777 * This is done only once in a lifetime of a context.
3778 */
3779 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3780 sctx->initial_gfx_cs_size = 0; /* force flush */
3781 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3782 }
3783
3784 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3785 union si_vgt_stages_key key)
3786 {
3787 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3788 uint32_t stages = 0;
3789
3790 if (key.u.tess) {
3791 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3792 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3793
3794 if (key.u.gs)
3795 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3796 S_028B54_GS_EN(1);
3797 else if (key.u.ngg)
3798 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3799 else
3800 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3801 } else if (key.u.gs) {
3802 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3803 S_028B54_GS_EN(1);
3804 } else if (key.u.ngg) {
3805 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3806 }
3807
3808 if (key.u.ngg) {
3809 stages |= S_028B54_PRIMGEN_EN(1);
3810 if (key.u.streamout)
3811 stages |= S_028B54_NGG_WAVE_ID_EN(1);
3812 } else if (key.u.gs)
3813 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3814
3815 if (screen->info.chip_class >= GFX9)
3816 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3817
3818 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
3819 stages |= S_028B54_HS_W32_EN(1) |
3820 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3821 S_028B54_VS_W32_EN(1);
3822 }
3823
3824 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3825 return pm4;
3826 }
3827
3828 static void si_update_vgt_shader_config(struct si_context *sctx,
3829 union si_vgt_stages_key key)
3830 {
3831 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3832
3833 if (unlikely(!*pm4))
3834 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3835 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3836 }
3837
3838 bool si_update_shaders(struct si_context *sctx)
3839 {
3840 struct pipe_context *ctx = (struct pipe_context*)sctx;
3841 struct si_compiler_ctx_state compiler_state;
3842 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3843 struct si_shader *old_vs = si_get_vs_state(sctx);
3844 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3845 struct si_shader *old_ps = sctx->ps_shader.current;
3846 union si_vgt_stages_key key;
3847 unsigned old_spi_shader_col_format =
3848 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3849 int r;
3850
3851 compiler_state.compiler = &sctx->compiler;
3852 compiler_state.debug = sctx->debug;
3853 compiler_state.is_debug_context = sctx->is_debug;
3854
3855 key.index = 0;
3856
3857 if (sctx->tes_shader.cso)
3858 key.u.tess = 1;
3859 if (sctx->gs_shader.cso)
3860 key.u.gs = 1;
3861
3862 if (sctx->ngg) {
3863 key.u.ngg = 1;
3864 key.u.streamout = !!si_get_vs(sctx)->cso->so.num_outputs;
3865 }
3866
3867 /* Update TCS and TES. */
3868 if (sctx->tes_shader.cso) {
3869 if (!sctx->tess_rings) {
3870 si_init_tess_factor_ring(sctx);
3871 if (!sctx->tess_rings)
3872 return false;
3873 }
3874
3875 if (sctx->tcs_shader.cso) {
3876 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3877 &compiler_state);
3878 if (r)
3879 return false;
3880 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3881 } else {
3882 if (!sctx->fixed_func_tcs_shader.cso) {
3883 sctx->fixed_func_tcs_shader.cso =
3884 si_create_fixed_func_tcs(sctx);
3885 if (!sctx->fixed_func_tcs_shader.cso)
3886 return false;
3887 }
3888
3889 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3890 key, &compiler_state);
3891 if (r)
3892 return false;
3893 si_pm4_bind_state(sctx, hs,
3894 sctx->fixed_func_tcs_shader.current->pm4);
3895 }
3896
3897 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3898 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3899 if (r)
3900 return false;
3901
3902 if (sctx->gs_shader.cso) {
3903 /* TES as ES */
3904 assert(sctx->chip_class <= GFX8);
3905 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3906 } else if (key.u.ngg) {
3907 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3908 } else {
3909 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3910 }
3911 }
3912 } else {
3913 if (sctx->chip_class <= GFX8)
3914 si_pm4_bind_state(sctx, ls, NULL);
3915 si_pm4_bind_state(sctx, hs, NULL);
3916 }
3917
3918 /* Update GS. */
3919 if (sctx->gs_shader.cso) {
3920 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3921 if (r)
3922 return false;
3923 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3924 if (!key.u.ngg) {
3925 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3926
3927 if (!si_update_gs_ring_buffers(sctx))
3928 return false;
3929 } else {
3930 si_pm4_bind_state(sctx, vs, NULL);
3931 }
3932 } else {
3933 if (!key.u.ngg) {
3934 si_pm4_bind_state(sctx, gs, NULL);
3935 if (sctx->chip_class <= GFX8)
3936 si_pm4_bind_state(sctx, es, NULL);
3937 }
3938 }
3939
3940 /* Update VS. */
3941 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
3942 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
3943 if (r)
3944 return false;
3945
3946 if (!key.u.tess && !key.u.gs) {
3947 if (key.u.ngg) {
3948 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3949 si_pm4_bind_state(sctx, vs, NULL);
3950 } else {
3951 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3952 }
3953 } else if (sctx->tes_shader.cso) {
3954 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3955 } else {
3956 assert(sctx->gs_shader.cso);
3957 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3958 }
3959 }
3960
3961 si_update_vgt_shader_config(sctx, key);
3962
3963 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3964 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3965
3966 if (sctx->ps_shader.cso) {
3967 unsigned db_shader_control;
3968
3969 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
3970 if (r)
3971 return false;
3972 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3973
3974 db_shader_control =
3975 sctx->ps_shader.cso->db_shader_control |
3976 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3977
3978 if (si_pm4_state_changed(sctx, ps) ||
3979 si_pm4_state_changed(sctx, vs) ||
3980 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
3981 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3982 sctx->flatshade != rs->flatshade) {
3983 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3984 sctx->flatshade = rs->flatshade;
3985 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3986 }
3987
3988 if (sctx->screen->rbplus_allowed &&
3989 si_pm4_state_changed(sctx, ps) &&
3990 (!old_ps ||
3991 old_spi_shader_col_format !=
3992 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3993 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3994
3995 if (sctx->ps_db_shader_control != db_shader_control) {
3996 sctx->ps_db_shader_control = db_shader_control;
3997 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3998 if (sctx->screen->dpbb_allowed)
3999 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
4000 }
4001
4002 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
4003 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
4004 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
4005
4006 if (sctx->chip_class == GFX6)
4007 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4008
4009 if (sctx->framebuffer.nr_samples <= 1)
4010 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
4011 }
4012 }
4013
4014 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
4015 si_pm4_state_enabled_and_changed(sctx, hs) ||
4016 si_pm4_state_enabled_and_changed(sctx, es) ||
4017 si_pm4_state_enabled_and_changed(sctx, gs) ||
4018 si_pm4_state_enabled_and_changed(sctx, vs) ||
4019 si_pm4_state_enabled_and_changed(sctx, ps)) {
4020 if (!si_update_spi_tmpring_size(sctx))
4021 return false;
4022 }
4023
4024 if (sctx->chip_class >= GFX7) {
4025 if (si_pm4_state_enabled_and_changed(sctx, ls))
4026 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
4027 else if (!sctx->queued.named.ls)
4028 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
4029
4030 if (si_pm4_state_enabled_and_changed(sctx, hs))
4031 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
4032 else if (!sctx->queued.named.hs)
4033 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
4034
4035 if (si_pm4_state_enabled_and_changed(sctx, es))
4036 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4037 else if (!sctx->queued.named.es)
4038 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4039
4040 if (si_pm4_state_enabled_and_changed(sctx, gs))
4041 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4042 else if (!sctx->queued.named.gs)
4043 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4044
4045 if (si_pm4_state_enabled_and_changed(sctx, vs))
4046 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4047 else if (!sctx->queued.named.vs)
4048 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4049
4050 if (si_pm4_state_enabled_and_changed(sctx, ps))
4051 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4052 else if (!sctx->queued.named.ps)
4053 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4054 }
4055
4056 sctx->do_update_shaders = false;
4057 return true;
4058 }
4059
4060 static void si_emit_scratch_state(struct si_context *sctx)
4061 {
4062 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4063
4064 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4065 sctx->spi_tmpring_size);
4066
4067 if (sctx->scratch_buffer) {
4068 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4069 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4070 RADEON_PRIO_SCRATCH_BUFFER);
4071 }
4072 }
4073
4074 void si_init_shader_functions(struct si_context *sctx)
4075 {
4076 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4077 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4078
4079 sctx->b.create_vs_state = si_create_shader_selector;
4080 sctx->b.create_tcs_state = si_create_shader_selector;
4081 sctx->b.create_tes_state = si_create_shader_selector;
4082 sctx->b.create_gs_state = si_create_shader_selector;
4083 sctx->b.create_fs_state = si_create_shader_selector;
4084
4085 sctx->b.bind_vs_state = si_bind_vs_shader;
4086 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4087 sctx->b.bind_tes_state = si_bind_tes_shader;
4088 sctx->b.bind_gs_state = si_bind_gs_shader;
4089 sctx->b.bind_fs_state = si_bind_ps_shader;
4090
4091 sctx->b.delete_vs_state = si_delete_shader_selector;
4092 sctx->b.delete_tcs_state = si_delete_shader_selector;
4093 sctx->b.delete_tes_state = si_delete_shader_selector;
4094 sctx->b.delete_gs_state = si_delete_shader_selector;
4095 sctx->b.delete_fs_state = si_delete_shader_selector;
4096 }