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radeonsi: make si_shader_io_get_unique_index stricter
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_ureg.h"
34 #include "util/hash_table.h"
35 #include "util/u_hash.h"
36 #include "util/u_memory.h"
37 #include "util/u_prim.h"
38
39 /* SHADER_CACHE */
40
41 /**
42 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
43 * integer.
44 */
45 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
46 {
47 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
48 sizeof(struct tgsi_token);
49 unsigned size = 4 + tgsi_size + sizeof(sel->so);
50 char *result = (char*)MALLOC(size);
51
52 if (!result)
53 return NULL;
54
55 *((uint32_t*)result) = size;
56 memcpy(result + 4, sel->tokens, tgsi_size);
57 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
58 return result;
59 }
60
61 /** Copy "data" to "ptr" and return the next dword following copied data. */
62 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
63 {
64 /* data may be NULL if size == 0 */
65 if (size)
66 memcpy(ptr, data, size);
67 ptr += DIV_ROUND_UP(size, 4);
68 return ptr;
69 }
70
71 /** Read data from "ptr". Return the next dword following the data. */
72 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
73 {
74 memcpy(data, ptr, size);
75 ptr += DIV_ROUND_UP(size, 4);
76 return ptr;
77 }
78
79 /**
80 * Write the size as uint followed by the data. Return the next dword
81 * following the copied data.
82 */
83 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
84 {
85 *ptr++ = size;
86 return write_data(ptr, data, size);
87 }
88
89 /**
90 * Read the size as uint followed by the data. Return both via parameters.
91 * Return the next dword following the data.
92 */
93 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
94 {
95 *size = *ptr++;
96 assert(*data == NULL);
97 if (!*size)
98 return ptr;
99 *data = malloc(*size);
100 return read_data(ptr, *data, *size);
101 }
102
103 /**
104 * Return the shader binary in a buffer. The first 4 bytes contain its size
105 * as integer.
106 */
107 static void *si_get_shader_binary(struct si_shader *shader)
108 {
109 /* There is always a size of data followed by the data itself. */
110 unsigned relocs_size = shader->binary.reloc_count *
111 sizeof(shader->binary.relocs[0]);
112 unsigned disasm_size = strlen(shader->binary.disasm_string) + 1;
113 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
114 strlen(shader->binary.llvm_ir_string) + 1 : 0;
115 unsigned size =
116 4 + /* total size */
117 4 + /* CRC32 of the data below */
118 align(sizeof(shader->config), 4) +
119 align(sizeof(shader->info), 4) +
120 4 + align(shader->binary.code_size, 4) +
121 4 + align(shader->binary.rodata_size, 4) +
122 4 + align(relocs_size, 4) +
123 4 + align(disasm_size, 4) +
124 4 + align(llvm_ir_size, 4);
125 void *buffer = CALLOC(1, size);
126 uint32_t *ptr = (uint32_t*)buffer;
127
128 if (!buffer)
129 return NULL;
130
131 *ptr++ = size;
132 ptr++; /* CRC32 is calculated at the end. */
133
134 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
135 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
136 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
137 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
138 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
139 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
140 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
141 assert((char *)ptr - (char *)buffer == size);
142
143 /* Compute CRC32. */
144 ptr = (uint32_t*)buffer;
145 ptr++;
146 *ptr = util_hash_crc32(ptr + 1, size - 8);
147
148 return buffer;
149 }
150
151 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
152 {
153 uint32_t *ptr = (uint32_t*)binary;
154 uint32_t size = *ptr++;
155 uint32_t crc32 = *ptr++;
156 unsigned chunk_size;
157
158 if (util_hash_crc32(ptr, size - 8) != crc32) {
159 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
160 return false;
161 }
162
163 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
164 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
165 ptr = read_chunk(ptr, (void**)&shader->binary.code,
166 &shader->binary.code_size);
167 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
168 &shader->binary.rodata_size);
169 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
170 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
171 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
172 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
173
174 return true;
175 }
176
177 /**
178 * Insert a shader into the cache. It's assumed the shader is not in the cache.
179 * Use si_shader_cache_load_shader before calling this.
180 *
181 * Returns false on failure, in which case the tgsi_binary should be freed.
182 */
183 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
184 void *tgsi_binary,
185 struct si_shader *shader)
186 {
187 void *hw_binary;
188 struct hash_entry *entry;
189
190 entry = _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
191 if (entry)
192 return false; /* already added */
193
194 hw_binary = si_get_shader_binary(shader);
195 if (!hw_binary)
196 return false;
197
198 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
199 hw_binary) == NULL) {
200 FREE(hw_binary);
201 return false;
202 }
203
204 return true;
205 }
206
207 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
208 void *tgsi_binary,
209 struct si_shader *shader)
210 {
211 struct hash_entry *entry =
212 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
213 if (!entry)
214 return false;
215
216 if (!si_load_shader_binary(shader, entry->data))
217 return false;
218
219 p_atomic_inc(&sscreen->b.num_shader_cache_hits);
220 return true;
221 }
222
223 static uint32_t si_shader_cache_key_hash(const void *key)
224 {
225 /* The first dword is the key size. */
226 return util_hash_crc32(key, *(uint32_t*)key);
227 }
228
229 static bool si_shader_cache_key_equals(const void *a, const void *b)
230 {
231 uint32_t *keya = (uint32_t*)a;
232 uint32_t *keyb = (uint32_t*)b;
233
234 /* The first dword is the key size. */
235 if (*keya != *keyb)
236 return false;
237
238 return memcmp(keya, keyb, *keya) == 0;
239 }
240
241 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
242 {
243 FREE((void*)entry->key);
244 FREE(entry->data);
245 }
246
247 bool si_init_shader_cache(struct si_screen *sscreen)
248 {
249 pipe_mutex_init(sscreen->shader_cache_mutex);
250 sscreen->shader_cache =
251 _mesa_hash_table_create(NULL,
252 si_shader_cache_key_hash,
253 si_shader_cache_key_equals);
254 return sscreen->shader_cache != NULL;
255 }
256
257 void si_destroy_shader_cache(struct si_screen *sscreen)
258 {
259 if (sscreen->shader_cache)
260 _mesa_hash_table_destroy(sscreen->shader_cache,
261 si_destroy_shader_cache_entry);
262 pipe_mutex_destroy(sscreen->shader_cache_mutex);
263 }
264
265 /* SHADER STATES */
266
267 static void si_set_tesseval_regs(struct si_screen *sscreen,
268 struct si_shader *shader,
269 struct si_pm4_state *pm4)
270 {
271 struct tgsi_shader_info *info = &shader->selector->info;
272 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
273 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
274 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
275 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
276 unsigned type, partitioning, topology, distribution_mode;
277
278 switch (tes_prim_mode) {
279 case PIPE_PRIM_LINES:
280 type = V_028B6C_TESS_ISOLINE;
281 break;
282 case PIPE_PRIM_TRIANGLES:
283 type = V_028B6C_TESS_TRIANGLE;
284 break;
285 case PIPE_PRIM_QUADS:
286 type = V_028B6C_TESS_QUAD;
287 break;
288 default:
289 assert(0);
290 return;
291 }
292
293 switch (tes_spacing) {
294 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
295 partitioning = V_028B6C_PART_FRAC_ODD;
296 break;
297 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
298 partitioning = V_028B6C_PART_FRAC_EVEN;
299 break;
300 case PIPE_TESS_SPACING_EQUAL:
301 partitioning = V_028B6C_PART_INTEGER;
302 break;
303 default:
304 assert(0);
305 return;
306 }
307
308 if (tes_point_mode)
309 topology = V_028B6C_OUTPUT_POINT;
310 else if (tes_prim_mode == PIPE_PRIM_LINES)
311 topology = V_028B6C_OUTPUT_LINE;
312 else if (tes_vertex_order_cw)
313 /* for some reason, this must be the other way around */
314 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
315 else
316 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
317
318 if (sscreen->has_distributed_tess) {
319 if (sscreen->b.family == CHIP_FIJI ||
320 sscreen->b.family >= CHIP_POLARIS10)
321 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
322 else
323 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
324 } else
325 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
326
327 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
328 S_028B6C_TYPE(type) |
329 S_028B6C_PARTITIONING(partitioning) |
330 S_028B6C_TOPOLOGY(topology) |
331 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
332 }
333
334 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
335 {
336 if (shader->pm4)
337 si_pm4_clear_state(shader->pm4);
338 else
339 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
340
341 return shader->pm4;
342 }
343
344 static void si_shader_ls(struct si_shader *shader)
345 {
346 struct si_pm4_state *pm4;
347 unsigned vgpr_comp_cnt;
348 uint64_t va;
349
350 pm4 = si_get_shader_pm4_state(shader);
351 if (!pm4)
352 return;
353
354 va = shader->bo->gpu_address;
355 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
356
357 /* We need at least 2 components for LS.
358 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
359 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 1;
360
361 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
362 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
363
364 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
365 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
366 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
367 S_00B528_DX10_CLAMP(1) |
368 S_00B528_FLOAT_MODE(shader->config.float_mode);
369 shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_LS_NUM_USER_SGPR) |
370 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
371 }
372
373 static void si_shader_hs(struct si_shader *shader)
374 {
375 struct si_pm4_state *pm4;
376 uint64_t va;
377
378 pm4 = si_get_shader_pm4_state(shader);
379 if (!pm4)
380 return;
381
382 va = shader->bo->gpu_address;
383 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
384
385 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
386 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
387 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
388 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
389 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
390 S_00B428_DX10_CLAMP(1) |
391 S_00B428_FLOAT_MODE(shader->config.float_mode));
392 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
393 S_00B42C_USER_SGPR(SI_TCS_NUM_USER_SGPR) |
394 S_00B42C_OC_LDS_EN(1) |
395 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
396 }
397
398 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
399 {
400 struct si_pm4_state *pm4;
401 unsigned num_user_sgprs;
402 unsigned vgpr_comp_cnt;
403 uint64_t va;
404 unsigned oc_lds_en;
405
406 pm4 = si_get_shader_pm4_state(shader);
407 if (!pm4)
408 return;
409
410 va = shader->bo->gpu_address;
411 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
412
413 if (shader->selector->type == PIPE_SHADER_VERTEX) {
414 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
415 num_user_sgprs = SI_ES_NUM_USER_SGPR;
416 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
417 vgpr_comp_cnt = 3; /* all components are needed for TES */
418 num_user_sgprs = SI_TES_NUM_USER_SGPR;
419 } else
420 unreachable("invalid shader selector type");
421
422 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
423
424 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
425 shader->selector->esgs_itemsize / 4);
426 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
427 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
428 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
429 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
430 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
431 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
432 S_00B328_DX10_CLAMP(1) |
433 S_00B328_FLOAT_MODE(shader->config.float_mode));
434 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
435 S_00B32C_USER_SGPR(num_user_sgprs) |
436 S_00B32C_OC_LDS_EN(oc_lds_en) |
437 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
438
439 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
440 si_set_tesseval_regs(sscreen, shader, pm4);
441 }
442
443 /**
444 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
445 * geometry shader.
446 */
447 static uint32_t si_vgt_gs_mode(struct si_shader_selector *sel)
448 {
449 unsigned gs_max_vert_out = sel->gs_max_out_vertices;
450 unsigned cut_mode;
451
452 if (gs_max_vert_out <= 128) {
453 cut_mode = V_028A40_GS_CUT_128;
454 } else if (gs_max_vert_out <= 256) {
455 cut_mode = V_028A40_GS_CUT_256;
456 } else if (gs_max_vert_out <= 512) {
457 cut_mode = V_028A40_GS_CUT_512;
458 } else {
459 assert(gs_max_vert_out <= 1024);
460 cut_mode = V_028A40_GS_CUT_1024;
461 }
462
463 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
464 S_028A40_CUT_MODE(cut_mode)|
465 S_028A40_ES_WRITE_OPTIMIZE(1) |
466 S_028A40_GS_WRITE_OPTIMIZE(1);
467 }
468
469 static void si_shader_gs(struct si_shader *shader)
470 {
471 unsigned gs_vert_itemsize = shader->selector->gsvs_vertex_size;
472 unsigned gsvs_itemsize = shader->selector->max_gsvs_emit_size >> 2;
473 unsigned gs_num_invocations = shader->selector->gs_num_invocations;
474 struct si_pm4_state *pm4;
475 uint64_t va;
476 unsigned max_stream = shader->selector->max_gs_stream;
477
478 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
479 assert(gsvs_itemsize < (1 << 15));
480
481 pm4 = si_get_shader_pm4_state(shader);
482 if (!pm4)
483 return;
484
485 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(shader->selector));
486
487 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
488 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize * ((max_stream >= 2) ? 2 : 1));
489 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize * ((max_stream >= 3) ? 3 : 1));
490
491 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize * (max_stream + 1));
492
493 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, shader->selector->gs_max_out_vertices);
494
495 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize >> 2);
496 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? gs_vert_itemsize >> 2 : 0);
497 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? gs_vert_itemsize >> 2 : 0);
498 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? gs_vert_itemsize >> 2 : 0);
499
500 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
501 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
502 S_028B90_ENABLE(gs_num_invocations > 0));
503
504 va = shader->bo->gpu_address;
505 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
506 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
507 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
508
509 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
510 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
511 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
512 S_00B228_DX10_CLAMP(1) |
513 S_00B228_FLOAT_MODE(shader->config.float_mode));
514 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
515 S_00B22C_USER_SGPR(SI_GS_NUM_USER_SGPR) |
516 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
517 }
518
519 /**
520 * Compute the state for \p shader, which will run as a vertex shader on the
521 * hardware.
522 *
523 * If \p gs is non-NULL, it points to the geometry shader for which this shader
524 * is the copy shader.
525 */
526 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
527 struct si_shader_selector *gs)
528 {
529 struct si_pm4_state *pm4;
530 unsigned num_user_sgprs;
531 unsigned nparams, vgpr_comp_cnt;
532 uint64_t va;
533 unsigned oc_lds_en;
534 unsigned window_space =
535 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
536 bool enable_prim_id = si_vs_exports_prim_id(shader);
537
538 pm4 = si_get_shader_pm4_state(shader);
539 if (!pm4)
540 return;
541
542 /* We always write VGT_GS_MODE in the VS state, because every switch
543 * between different shader pipelines involving a different GS or no
544 * GS at all involves a switch of the VS (different GS use different
545 * copy shaders). On the other hand, when the API switches from a GS to
546 * no GS and then back to the same GS used originally, the GS state is
547 * not sent again.
548 */
549 if (!gs) {
550 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
551 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
552 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
553 } else {
554 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
555 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
556 }
557
558 va = shader->bo->gpu_address;
559 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
560
561 if (gs) {
562 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
563 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
564 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
565 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
566 num_user_sgprs = SI_VS_NUM_USER_SGPR;
567 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
568 vgpr_comp_cnt = 3; /* all components are needed for TES */
569 num_user_sgprs = SI_TES_NUM_USER_SGPR;
570 } else
571 unreachable("invalid shader selector type");
572
573 /* VS is required to export at least one param. */
574 nparams = MAX2(shader->info.nr_param_exports, 1);
575 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
576 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
577
578 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
579 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
580 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
581 V_02870C_SPI_SHADER_4COMP :
582 V_02870C_SPI_SHADER_NONE) |
583 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
584 V_02870C_SPI_SHADER_4COMP :
585 V_02870C_SPI_SHADER_NONE) |
586 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
587 V_02870C_SPI_SHADER_4COMP :
588 V_02870C_SPI_SHADER_NONE));
589
590 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
591
592 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
593 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
594 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
595 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
596 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
597 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
598 S_00B128_DX10_CLAMP(1) |
599 S_00B128_FLOAT_MODE(shader->config.float_mode));
600 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
601 S_00B12C_USER_SGPR(num_user_sgprs) |
602 S_00B12C_OC_LDS_EN(oc_lds_en) |
603 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
604 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
605 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
606 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
607 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
608 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
609 if (window_space)
610 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
611 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
612 else
613 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
614 S_028818_VTX_W0_FMT(1) |
615 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
616 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
617 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
618
619 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
620 si_set_tesseval_regs(sscreen, shader, pm4);
621 }
622
623 static unsigned si_get_ps_num_interp(struct si_shader *ps)
624 {
625 struct tgsi_shader_info *info = &ps->selector->info;
626 unsigned num_colors = !!(info->colors_read & 0x0f) +
627 !!(info->colors_read & 0xf0);
628 unsigned num_interp = ps->selector->info.num_inputs +
629 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
630
631 assert(num_interp <= 32);
632 return MIN2(num_interp, 32);
633 }
634
635 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
636 {
637 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
638 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
639
640 /* If the i-th target format is set, all previous target formats must
641 * be non-zero to avoid hangs.
642 */
643 for (i = 0; i < num_targets; i++)
644 if (!(value & (0xf << (i * 4))))
645 value |= V_028714_SPI_SHADER_32_R << (i * 4);
646
647 return value;
648 }
649
650 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
651 {
652 unsigned i, cb_shader_mask = 0;
653
654 for (i = 0; i < 8; i++) {
655 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
656 case V_028714_SPI_SHADER_ZERO:
657 break;
658 case V_028714_SPI_SHADER_32_R:
659 cb_shader_mask |= 0x1 << (i * 4);
660 break;
661 case V_028714_SPI_SHADER_32_GR:
662 cb_shader_mask |= 0x3 << (i * 4);
663 break;
664 case V_028714_SPI_SHADER_32_AR:
665 cb_shader_mask |= 0x9 << (i * 4);
666 break;
667 case V_028714_SPI_SHADER_FP16_ABGR:
668 case V_028714_SPI_SHADER_UNORM16_ABGR:
669 case V_028714_SPI_SHADER_SNORM16_ABGR:
670 case V_028714_SPI_SHADER_UINT16_ABGR:
671 case V_028714_SPI_SHADER_SINT16_ABGR:
672 case V_028714_SPI_SHADER_32_ABGR:
673 cb_shader_mask |= 0xf << (i * 4);
674 break;
675 default:
676 assert(0);
677 }
678 }
679 return cb_shader_mask;
680 }
681
682 static void si_shader_ps(struct si_shader *shader)
683 {
684 struct tgsi_shader_info *info = &shader->selector->info;
685 struct si_pm4_state *pm4;
686 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
687 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
688 uint64_t va;
689 unsigned input_ena = shader->config.spi_ps_input_ena;
690
691 /* we need to enable at least one of them, otherwise we hang the GPU */
692 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
693 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
694 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
695 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
696 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
697 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
698 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
699 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
700 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
701 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
702 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
703 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
704 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
705 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
706
707 /* Validate interpolation optimization flags (read as implications). */
708 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
709 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
710 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
711 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
712 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
713 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
714 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
715 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
716 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
717 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
718 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
719 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
720 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
721 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
722 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
723 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
724 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
725 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
726
727 /* Validate cases when the optimizations are off (read as implications). */
728 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
729 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
730 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
731 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
732 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
733 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
734
735 pm4 = si_get_shader_pm4_state(shader);
736 if (!pm4)
737 return;
738
739 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
740 * Possible vaules:
741 * 0 -> Position = pixel center
742 * 1 -> Position = pixel centroid
743 * 2 -> Position = at sample position
744 *
745 * From GLSL 4.5 specification, section 7.1:
746 * "The variable gl_FragCoord is available as an input variable from
747 * within fragment shaders and it holds the window relative coordinates
748 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
749 * value can be for any location within the pixel, or one of the
750 * fragment samples. The use of centroid does not further restrict
751 * this value to be inside the current primitive."
752 *
753 * Meaning that centroid has no effect and we can return anything within
754 * the pixel. Thus, return the value at sample position, because that's
755 * the most accurate one shaders can get.
756 */
757 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
758
759 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
760 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
761 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
762
763 spi_shader_col_format = si_get_spi_shader_col_format(shader);
764 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
765
766 /* Ensure that some export memory is always allocated, for two reasons:
767 *
768 * 1) Correctness: The hardware ignores the EXEC mask if no export
769 * memory is allocated, so KILL and alpha test do not work correctly
770 * without this.
771 * 2) Performance: Every shader needs at least a NULL export, even when
772 * it writes no color/depth output. The NULL export instruction
773 * stalls without this setting.
774 *
775 * Don't add this to CB_SHADER_MASK.
776 */
777 if (!spi_shader_col_format &&
778 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
779 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
780
781 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
782 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
783 shader->config.spi_ps_input_addr);
784
785 /* Set interpolation controls. */
786 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
787
788 /* Set registers. */
789 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
790 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
791
792 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
793 si_get_spi_shader_z_format(info->writes_z,
794 info->writes_stencil,
795 info->writes_samplemask));
796
797 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
798 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
799
800 va = shader->bo->gpu_address;
801 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
802 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
803 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
804
805 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
806 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
807 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
808 S_00B028_DX10_CLAMP(1) |
809 S_00B028_FLOAT_MODE(shader->config.float_mode));
810 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
811 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
812 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
813 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
814 }
815
816 static void si_shader_init_pm4_state(struct si_screen *sscreen,
817 struct si_shader *shader)
818 {
819 switch (shader->selector->type) {
820 case PIPE_SHADER_VERTEX:
821 if (shader->key.as_ls)
822 si_shader_ls(shader);
823 else if (shader->key.as_es)
824 si_shader_es(sscreen, shader);
825 else
826 si_shader_vs(sscreen, shader, NULL);
827 break;
828 case PIPE_SHADER_TESS_CTRL:
829 si_shader_hs(shader);
830 break;
831 case PIPE_SHADER_TESS_EVAL:
832 if (shader->key.as_es)
833 si_shader_es(sscreen, shader);
834 else
835 si_shader_vs(sscreen, shader, NULL);
836 break;
837 case PIPE_SHADER_GEOMETRY:
838 si_shader_gs(shader);
839 break;
840 case PIPE_SHADER_FRAGMENT:
841 si_shader_ps(shader);
842 break;
843 default:
844 assert(0);
845 }
846 }
847
848 static unsigned si_get_alpha_test_func(struct si_context *sctx)
849 {
850 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
851 if (sctx->queued.named.dsa)
852 return sctx->queued.named.dsa->alpha_func;
853
854 return PIPE_FUNC_ALWAYS;
855 }
856
857 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
858 struct si_shader_selector *vs,
859 struct si_shader_key *key)
860 {
861 key->opt.hw_vs.clip_disable =
862 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
863 (vs->info.clipdist_writemask ||
864 vs->info.writes_clipvertex) &&
865 !vs->info.culldist_writemask;
866 }
867
868 /* Compute the key for the hw shader variant */
869 static inline void si_shader_selector_key(struct pipe_context *ctx,
870 struct si_shader_selector *sel,
871 struct si_shader_key *key)
872 {
873 struct si_context *sctx = (struct si_context *)ctx;
874 unsigned i;
875
876 memset(key, 0, sizeof(*key));
877
878 switch (sel->type) {
879 case PIPE_SHADER_VERTEX:
880 if (sctx->vertex_elements) {
881 unsigned count = MIN2(sel->info.num_inputs,
882 sctx->vertex_elements->count);
883 for (i = 0; i < count; ++i)
884 key->part.vs.prolog.instance_divisors[i] =
885 sctx->vertex_elements->elements[i].instance_divisor;
886
887 key->mono.vs.fix_fetch =
888 sctx->vertex_elements->fix_fetch &
889 u_bit_consecutive(0, 2 * count);
890 }
891 if (sctx->tes_shader.cso)
892 key->as_ls = 1;
893 else if (sctx->gs_shader.cso)
894 key->as_es = 1;
895 else {
896 si_shader_selector_key_hw_vs(sctx, sel, key);
897
898 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
899 key->part.vs.epilog.export_prim_id = 1;
900 }
901 break;
902 case PIPE_SHADER_TESS_CTRL:
903 key->part.tcs.epilog.prim_mode =
904 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
905
906 if (sel == sctx->fixed_func_tcs_shader.cso)
907 key->mono.tcs.inputs_to_copy = sctx->vs_shader.cso->outputs_written;
908 break;
909 case PIPE_SHADER_TESS_EVAL:
910 if (sctx->gs_shader.cso)
911 key->as_es = 1;
912 else {
913 si_shader_selector_key_hw_vs(sctx, sel, key);
914
915 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
916 key->part.tes.epilog.export_prim_id = 1;
917 }
918 break;
919 case PIPE_SHADER_GEOMETRY:
920 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
921 break;
922 case PIPE_SHADER_FRAGMENT: {
923 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
924 struct si_state_blend *blend = sctx->queued.named.blend;
925
926 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
927 sel->info.colors_written == 0x1)
928 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
929
930 if (blend) {
931 /* Select the shader color format based on whether
932 * blending or alpha are needed.
933 */
934 key->part.ps.epilog.spi_shader_col_format =
935 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
936 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
937 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
938 sctx->framebuffer.spi_shader_col_format_blend) |
939 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
940 sctx->framebuffer.spi_shader_col_format_alpha) |
941 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
942 sctx->framebuffer.spi_shader_col_format);
943
944 /* The output for dual source blending should have
945 * the same format as the first output.
946 */
947 if (blend->dual_src_blend)
948 key->part.ps.epilog.spi_shader_col_format |=
949 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
950 } else
951 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
952
953 /* If alpha-to-coverage is enabled, we have to export alpha
954 * even if there is no color buffer.
955 */
956 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
957 blend && blend->alpha_to_coverage)
958 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
959
960 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
961 * to the range supported by the type if a channel has less
962 * than 16 bits and the export format is 16_ABGR.
963 */
964 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII)
965 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
966
967 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
968 if (!key->part.ps.epilog.last_cbuf) {
969 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
970 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
971 }
972
973 if (rs) {
974 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
975 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
976 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
977 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
978
979 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
980 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
981
982 if (sctx->queued.named.blend) {
983 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
984 rs->multisample_enable;
985 }
986
987 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
988 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
989 (is_line && rs->line_smooth)) &&
990 sctx->framebuffer.nr_samples <= 1;
991 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
992
993 if (rs->force_persample_interp &&
994 rs->multisample_enable &&
995 sctx->framebuffer.nr_samples > 1 &&
996 sctx->ps_iter_samples > 1) {
997 key->part.ps.prolog.force_persp_sample_interp =
998 sel->info.uses_persp_center ||
999 sel->info.uses_persp_centroid;
1000
1001 key->part.ps.prolog.force_linear_sample_interp =
1002 sel->info.uses_linear_center ||
1003 sel->info.uses_linear_centroid;
1004 } else if (rs->multisample_enable &&
1005 sctx->framebuffer.nr_samples > 1) {
1006 key->part.ps.prolog.bc_optimize_for_persp =
1007 sel->info.uses_persp_center &&
1008 sel->info.uses_persp_centroid;
1009 key->part.ps.prolog.bc_optimize_for_linear =
1010 sel->info.uses_linear_center &&
1011 sel->info.uses_linear_centroid;
1012 } else {
1013 /* Make sure SPI doesn't compute more than 1 pair
1014 * of (i,j), which is the optimization here. */
1015 key->part.ps.prolog.force_persp_center_interp =
1016 sel->info.uses_persp_center +
1017 sel->info.uses_persp_centroid +
1018 sel->info.uses_persp_sample > 1;
1019
1020 key->part.ps.prolog.force_linear_center_interp =
1021 sel->info.uses_linear_center +
1022 sel->info.uses_linear_centroid +
1023 sel->info.uses_linear_sample > 1;
1024 }
1025 }
1026
1027 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1028 break;
1029 }
1030 default:
1031 assert(0);
1032 }
1033 }
1034
1035 static void si_build_shader_variant(void *job, int thread_index)
1036 {
1037 struct si_shader *shader = (struct si_shader *)job;
1038 struct si_shader_selector *sel = shader->selector;
1039 struct si_screen *sscreen = sel->screen;
1040 LLVMTargetMachineRef tm;
1041 struct pipe_debug_callback *debug = &sel->debug;
1042 int r;
1043
1044 if (thread_index >= 0) {
1045 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1046 tm = sscreen->tm[thread_index];
1047 if (!debug->async)
1048 debug = NULL;
1049 } else {
1050 tm = sel->tm;
1051 }
1052
1053 r = si_shader_create(sscreen, tm, shader, debug);
1054 if (unlikely(r)) {
1055 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1056 sel->type, r);
1057 shader->compilation_failed = true;
1058 return;
1059 }
1060
1061 if (sel->is_debug_context) {
1062 FILE *f = open_memstream(&shader->shader_log,
1063 &shader->shader_log_size);
1064 if (f) {
1065 si_shader_dump(sscreen, shader, NULL, sel->type, f);
1066 fclose(f);
1067 }
1068 }
1069
1070 si_shader_init_pm4_state(sscreen, shader);
1071 }
1072
1073 /* Select the hw shader variant depending on the current state. */
1074 static int si_shader_select_with_key(struct si_screen *sscreen,
1075 struct si_shader_ctx_state *state,
1076 struct si_shader_key *key,
1077 int thread_index)
1078 {
1079 static const struct si_shader_key zeroed;
1080 struct si_shader_selector *sel = state->cso;
1081 struct si_shader *current = state->current;
1082 struct si_shader *iter, *shader = NULL;
1083 again:
1084 /* Check if we don't need to change anything.
1085 * This path is also used for most shaders that don't need multiple
1086 * variants, it will cost just a computation of the key and this
1087 * test. */
1088 if (likely(current &&
1089 memcmp(&current->key, key, sizeof(*key)) == 0 &&
1090 (!current->is_optimized ||
1091 util_queue_fence_is_signalled(&current->optimized_ready))))
1092 return 0;
1093
1094 /* This must be done before the mutex is locked, because async GS
1095 * compilation calls this function too, and therefore must enter
1096 * the mutex first.
1097 *
1098 * Only wait if we are in a draw call. Don't wait if we are
1099 * in a compiler thread.
1100 */
1101 if (thread_index < 0)
1102 util_queue_job_wait(&sel->ready);
1103
1104 pipe_mutex_lock(sel->mutex);
1105
1106 /* Find the shader variant. */
1107 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1108 /* Don't check the "current" shader. We checked it above. */
1109 if (current != iter &&
1110 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1111 /* If it's an optimized shader and its compilation has
1112 * been started but isn't done, use the unoptimized
1113 * shader so as not to cause a stall due to compilation.
1114 */
1115 if (iter->is_optimized &&
1116 !util_queue_fence_is_signalled(&iter->optimized_ready)) {
1117 memset(&key->opt, 0, sizeof(key->opt));
1118 pipe_mutex_unlock(sel->mutex);
1119 goto again;
1120 }
1121
1122 if (iter->compilation_failed) {
1123 pipe_mutex_unlock(sel->mutex);
1124 return -1; /* skip the draw call */
1125 }
1126
1127 state->current = iter;
1128 pipe_mutex_unlock(sel->mutex);
1129 return 0;
1130 }
1131 }
1132
1133 /* Build a new shader. */
1134 shader = CALLOC_STRUCT(si_shader);
1135 if (!shader) {
1136 pipe_mutex_unlock(sel->mutex);
1137 return -ENOMEM;
1138 }
1139 shader->selector = sel;
1140 shader->key = *key;
1141
1142 /* Monolithic-only shaders don't make a distinction between optimized
1143 * and unoptimized. */
1144 shader->is_monolithic =
1145 !sel->main_shader_part ||
1146 sel->main_shader_part->key.as_ls != key->as_ls ||
1147 sel->main_shader_part->key.as_es != key->as_es ||
1148 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0 ||
1149 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1150
1151 shader->is_optimized =
1152 !sscreen->use_monolithic_shaders &&
1153 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1154 if (shader->is_optimized)
1155 util_queue_fence_init(&shader->optimized_ready);
1156
1157 if (!sel->last_variant) {
1158 sel->first_variant = shader;
1159 sel->last_variant = shader;
1160 } else {
1161 sel->last_variant->next_variant = shader;
1162 sel->last_variant = shader;
1163 }
1164
1165 /* If it's an optimized shader, compile it asynchronously. */
1166 if (shader->is_optimized &&
1167 thread_index < 0) {
1168 /* Compile it asynchronously. */
1169 util_queue_add_job(&sscreen->shader_compiler_queue,
1170 shader, &shader->optimized_ready,
1171 si_build_shader_variant, NULL);
1172
1173 /* Use the default (unoptimized) shader for now. */
1174 memset(&key->opt, 0, sizeof(key->opt));
1175 pipe_mutex_unlock(sel->mutex);
1176 goto again;
1177 }
1178
1179 assert(!shader->is_optimized);
1180 si_build_shader_variant(shader, thread_index);
1181
1182 if (!shader->compilation_failed)
1183 state->current = shader;
1184
1185 pipe_mutex_unlock(sel->mutex);
1186 return shader->compilation_failed ? -1 : 0;
1187 }
1188
1189 static int si_shader_select(struct pipe_context *ctx,
1190 struct si_shader_ctx_state *state)
1191 {
1192 struct si_context *sctx = (struct si_context *)ctx;
1193 struct si_shader_key key;
1194
1195 si_shader_selector_key(ctx, state->cso, &key);
1196 return si_shader_select_with_key(sctx->screen, state, &key, -1);
1197 }
1198
1199 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1200 struct si_shader_key *key)
1201 {
1202 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1203
1204 switch (info->processor) {
1205 case PIPE_SHADER_VERTEX:
1206 switch (next_shader) {
1207 case PIPE_SHADER_GEOMETRY:
1208 key->as_es = 1;
1209 break;
1210 case PIPE_SHADER_TESS_CTRL:
1211 case PIPE_SHADER_TESS_EVAL:
1212 key->as_ls = 1;
1213 break;
1214 default:
1215 /* If POSITION isn't written, it can't be a HW VS.
1216 * Assume that it's a HW LS. (the next shader is TCS)
1217 * This heuristic is needed for separate shader objects.
1218 */
1219 if (!info->writes_position)
1220 key->as_ls = 1;
1221 }
1222 break;
1223
1224 case PIPE_SHADER_TESS_EVAL:
1225 if (next_shader == PIPE_SHADER_GEOMETRY)
1226 key->as_es = 1;
1227 break;
1228 }
1229 }
1230
1231 /**
1232 * Compile the main shader part or the monolithic shader as part of
1233 * si_shader_selector initialization. Since it can be done asynchronously,
1234 * there is no way to report compile failures to applications.
1235 */
1236 void si_init_shader_selector_async(void *job, int thread_index)
1237 {
1238 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1239 struct si_screen *sscreen = sel->screen;
1240 LLVMTargetMachineRef tm;
1241 struct pipe_debug_callback *debug = &sel->debug;
1242 unsigned i;
1243
1244 if (thread_index >= 0) {
1245 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1246 tm = sscreen->tm[thread_index];
1247 if (!debug->async)
1248 debug = NULL;
1249 } else {
1250 tm = sel->tm;
1251 }
1252
1253 /* Compile the main shader part for use with a prolog and/or epilog.
1254 * If this fails, the driver will try to compile a monolithic shader
1255 * on demand.
1256 */
1257 if (!sscreen->use_monolithic_shaders) {
1258 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1259 void *tgsi_binary;
1260
1261 if (!shader) {
1262 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1263 return;
1264 }
1265
1266 shader->selector = sel;
1267 si_parse_next_shader_property(&sel->info, &shader->key);
1268
1269 tgsi_binary = si_get_tgsi_binary(sel);
1270
1271 /* Try to load the shader from the shader cache. */
1272 pipe_mutex_lock(sscreen->shader_cache_mutex);
1273
1274 if (tgsi_binary &&
1275 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1276 FREE(tgsi_binary);
1277 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1278 } else {
1279 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1280
1281 /* Compile the shader if it hasn't been loaded from the cache. */
1282 if (si_compile_tgsi_shader(sscreen, tm, shader, false,
1283 debug) != 0) {
1284 FREE(shader);
1285 FREE(tgsi_binary);
1286 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1287 return;
1288 }
1289
1290 if (tgsi_binary) {
1291 pipe_mutex_lock(sscreen->shader_cache_mutex);
1292 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary, shader))
1293 FREE(tgsi_binary);
1294 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1295 }
1296 }
1297
1298 sel->main_shader_part = shader;
1299 }
1300
1301 /* Pre-compilation. */
1302 if (sscreen->b.debug_flags & DBG_PRECOMPILE) {
1303 struct si_shader_ctx_state state = {sel};
1304 struct si_shader_key key;
1305
1306 memset(&key, 0, sizeof(key));
1307 si_parse_next_shader_property(&sel->info, &key);
1308
1309 /* Set reasonable defaults, so that the shader key doesn't
1310 * cause any code to be eliminated.
1311 */
1312 switch (sel->type) {
1313 case PIPE_SHADER_TESS_CTRL:
1314 key.part.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1315 break;
1316 case PIPE_SHADER_FRAGMENT:
1317 key.part.ps.prolog.bc_optimize_for_persp =
1318 sel->info.uses_persp_center &&
1319 sel->info.uses_persp_centroid;
1320 key.part.ps.prolog.bc_optimize_for_linear =
1321 sel->info.uses_linear_center &&
1322 sel->info.uses_linear_centroid;
1323 key.part.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1324 for (i = 0; i < 8; i++)
1325 if (sel->info.colors_written & (1 << i))
1326 key.part.ps.epilog.spi_shader_col_format |=
1327 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1328 break;
1329 }
1330
1331 if (si_shader_select_with_key(sscreen, &state, &key, thread_index))
1332 fprintf(stderr, "radeonsi: can't create a monolithic shader\n");
1333 }
1334
1335 /* The GS copy shader is always pre-compiled. */
1336 if (sel->type == PIPE_SHADER_GEOMETRY) {
1337 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
1338 if (!sel->gs_copy_shader) {
1339 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
1340 return;
1341 }
1342
1343 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
1344 }
1345 }
1346
1347 static void *si_create_shader_selector(struct pipe_context *ctx,
1348 const struct pipe_shader_state *state)
1349 {
1350 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1351 struct si_context *sctx = (struct si_context*)ctx;
1352 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
1353 int i;
1354
1355 if (!sel)
1356 return NULL;
1357
1358 sel->screen = sscreen;
1359 sel->tm = sctx->tm;
1360 sel->debug = sctx->b.debug;
1361 sel->is_debug_context = sctx->is_debug;
1362 sel->tokens = tgsi_dup_tokens(state->tokens);
1363 if (!sel->tokens) {
1364 FREE(sel);
1365 return NULL;
1366 }
1367
1368 sel->so = state->stream_output;
1369 tgsi_scan_shader(state->tokens, &sel->info);
1370 sel->type = sel->info.processor;
1371 p_atomic_inc(&sscreen->b.num_shaders_created);
1372
1373 /* Set which opcode uses which (i,j) pair. */
1374 if (sel->info.uses_persp_opcode_interp_centroid)
1375 sel->info.uses_persp_centroid = true;
1376
1377 if (sel->info.uses_linear_opcode_interp_centroid)
1378 sel->info.uses_linear_centroid = true;
1379
1380 if (sel->info.uses_persp_opcode_interp_offset ||
1381 sel->info.uses_persp_opcode_interp_sample)
1382 sel->info.uses_persp_center = true;
1383
1384 if (sel->info.uses_linear_opcode_interp_offset ||
1385 sel->info.uses_linear_opcode_interp_sample)
1386 sel->info.uses_linear_center = true;
1387
1388 switch (sel->type) {
1389 case PIPE_SHADER_GEOMETRY:
1390 sel->gs_output_prim =
1391 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
1392 sel->gs_max_out_vertices =
1393 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
1394 sel->gs_num_invocations =
1395 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
1396 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
1397 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
1398 sel->gs_max_out_vertices;
1399
1400 sel->max_gs_stream = 0;
1401 for (i = 0; i < sel->so.num_outputs; i++)
1402 sel->max_gs_stream = MAX2(sel->max_gs_stream,
1403 sel->so.output[i].stream);
1404
1405 sel->gs_input_verts_per_prim =
1406 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
1407 break;
1408
1409 case PIPE_SHADER_TESS_CTRL:
1410 /* Always reserve space for these. */
1411 sel->patch_outputs_written |=
1412 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0)) |
1413 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0));
1414 /* fall through */
1415 case PIPE_SHADER_VERTEX:
1416 case PIPE_SHADER_TESS_EVAL:
1417 for (i = 0; i < sel->info.num_outputs; i++) {
1418 unsigned name = sel->info.output_semantic_name[i];
1419 unsigned index = sel->info.output_semantic_index[i];
1420
1421 switch (name) {
1422 case TGSI_SEMANTIC_TESSINNER:
1423 case TGSI_SEMANTIC_TESSOUTER:
1424 case TGSI_SEMANTIC_PATCH:
1425 sel->patch_outputs_written |=
1426 1llu << si_shader_io_get_unique_index(name, index);
1427 break;
1428
1429 case TGSI_SEMANTIC_GENERIC:
1430 /* don't process indices the function can't handle */
1431 if (index >= 60)
1432 break;
1433 /* fall through */
1434 case TGSI_SEMANTIC_POSITION:
1435 case TGSI_SEMANTIC_PSIZE:
1436 case TGSI_SEMANTIC_CLIPDIST:
1437 sel->outputs_written |=
1438 1llu << si_shader_io_get_unique_index(name, index);
1439 break;
1440 }
1441 }
1442 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
1443 break;
1444
1445 case PIPE_SHADER_FRAGMENT:
1446 for (i = 0; i < 8; i++)
1447 if (sel->info.colors_written & (1 << i))
1448 sel->colors_written_4bit |= 0xf << (4 * i);
1449
1450 for (i = 0; i < sel->info.num_inputs; i++) {
1451 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
1452 int index = sel->info.input_semantic_index[i];
1453 sel->color_attr_index[index] = i;
1454 }
1455 }
1456 break;
1457 }
1458
1459 /* DB_SHADER_CONTROL */
1460 sel->db_shader_control =
1461 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
1462 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
1463 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
1464 S_02880C_KILL_ENABLE(sel->info.uses_kill);
1465
1466 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
1467 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1468 sel->db_shader_control |=
1469 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
1470 break;
1471 case TGSI_FS_DEPTH_LAYOUT_LESS:
1472 sel->db_shader_control |=
1473 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
1474 break;
1475 }
1476
1477 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
1478 *
1479 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
1480 * --|-----------|------------|------------|--------------------|-------------------|-------------
1481 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
1482 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
1483 * 2 | false | true | n/a | LateZ | 1 | 0
1484 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
1485 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
1486 *
1487 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
1488 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
1489 *
1490 * Don't use ReZ without profiling !!!
1491 *
1492 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
1493 * shaders.
1494 */
1495 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
1496 /* Cases 3, 4. */
1497 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
1498 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
1499 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
1500 } else if (sel->info.writes_memory) {
1501 /* Case 2. */
1502 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
1503 S_02880C_EXEC_ON_HIER_FAIL(1);
1504 } else {
1505 /* Case 1. */
1506 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1507 }
1508
1509 pipe_mutex_init(sel->mutex);
1510 util_queue_fence_init(&sel->ready);
1511
1512 if ((sctx->b.debug.debug_message && !sctx->b.debug.async) ||
1513 sctx->is_debug ||
1514 r600_can_dump_shader(&sscreen->b, sel->info.processor) ||
1515 !util_queue_is_initialized(&sscreen->shader_compiler_queue))
1516 si_init_shader_selector_async(sel, -1);
1517 else
1518 util_queue_add_job(&sscreen->shader_compiler_queue, sel,
1519 &sel->ready, si_init_shader_selector_async,
1520 NULL);
1521
1522 return sel;
1523 }
1524
1525 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1526 {
1527 struct si_context *sctx = (struct si_context *)ctx;
1528 struct si_shader_selector *sel = state;
1529
1530 if (sctx->vs_shader.cso == sel)
1531 return;
1532
1533 sctx->vs_shader.cso = sel;
1534 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
1535 sctx->do_update_shaders = true;
1536 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1537 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1538 }
1539
1540 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
1541 {
1542 struct si_context *sctx = (struct si_context *)ctx;
1543 struct si_shader_selector *sel = state;
1544 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
1545
1546 if (sctx->gs_shader.cso == sel)
1547 return;
1548
1549 sctx->gs_shader.cso = sel;
1550 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
1551 sctx->do_update_shaders = true;
1552 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1553 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1554
1555 if (enable_changed)
1556 si_shader_change_notify(sctx);
1557 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1558 }
1559
1560 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
1561 {
1562 struct si_context *sctx = (struct si_context *)ctx;
1563 struct si_shader_selector *sel = state;
1564 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
1565
1566 if (sctx->tcs_shader.cso == sel)
1567 return;
1568
1569 sctx->tcs_shader.cso = sel;
1570 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
1571 sctx->do_update_shaders = true;
1572
1573 if (enable_changed)
1574 sctx->last_tcs = NULL; /* invalidate derived tess state */
1575 }
1576
1577 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
1578 {
1579 struct si_context *sctx = (struct si_context *)ctx;
1580 struct si_shader_selector *sel = state;
1581 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
1582
1583 if (sctx->tes_shader.cso == sel)
1584 return;
1585
1586 sctx->tes_shader.cso = sel;
1587 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
1588 sctx->do_update_shaders = true;
1589 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1590 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1591
1592 if (enable_changed) {
1593 si_shader_change_notify(sctx);
1594 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
1595 }
1596 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1597 }
1598
1599 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1600 {
1601 struct si_context *sctx = (struct si_context *)ctx;
1602 struct si_shader_selector *sel = state;
1603
1604 /* skip if supplied shader is one already in use */
1605 if (sctx->ps_shader.cso == sel)
1606 return;
1607
1608 sctx->ps_shader.cso = sel;
1609 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
1610 sctx->do_update_shaders = true;
1611 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
1612 }
1613
1614 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
1615 {
1616 if (shader->is_optimized) {
1617 util_queue_job_wait(&shader->optimized_ready);
1618 util_queue_fence_destroy(&shader->optimized_ready);
1619 }
1620
1621 if (shader->pm4) {
1622 switch (shader->selector->type) {
1623 case PIPE_SHADER_VERTEX:
1624 if (shader->key.as_ls)
1625 si_pm4_delete_state(sctx, ls, shader->pm4);
1626 else if (shader->key.as_es)
1627 si_pm4_delete_state(sctx, es, shader->pm4);
1628 else
1629 si_pm4_delete_state(sctx, vs, shader->pm4);
1630 break;
1631 case PIPE_SHADER_TESS_CTRL:
1632 si_pm4_delete_state(sctx, hs, shader->pm4);
1633 break;
1634 case PIPE_SHADER_TESS_EVAL:
1635 if (shader->key.as_es)
1636 si_pm4_delete_state(sctx, es, shader->pm4);
1637 else
1638 si_pm4_delete_state(sctx, vs, shader->pm4);
1639 break;
1640 case PIPE_SHADER_GEOMETRY:
1641 if (shader->is_gs_copy_shader)
1642 si_pm4_delete_state(sctx, vs, shader->pm4);
1643 else
1644 si_pm4_delete_state(sctx, gs, shader->pm4);
1645 break;
1646 case PIPE_SHADER_FRAGMENT:
1647 si_pm4_delete_state(sctx, ps, shader->pm4);
1648 break;
1649 }
1650 }
1651
1652 si_shader_destroy(shader);
1653 free(shader);
1654 }
1655
1656 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
1657 {
1658 struct si_context *sctx = (struct si_context *)ctx;
1659 struct si_shader_selector *sel = (struct si_shader_selector *)state;
1660 struct si_shader *p = sel->first_variant, *c;
1661 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
1662 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
1663 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
1664 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
1665 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
1666 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
1667 };
1668
1669 util_queue_job_wait(&sel->ready);
1670
1671 if (current_shader[sel->type]->cso == sel) {
1672 current_shader[sel->type]->cso = NULL;
1673 current_shader[sel->type]->current = NULL;
1674 }
1675
1676 while (p) {
1677 c = p->next_variant;
1678 si_delete_shader(sctx, p);
1679 p = c;
1680 }
1681
1682 if (sel->main_shader_part)
1683 si_delete_shader(sctx, sel->main_shader_part);
1684 if (sel->gs_copy_shader)
1685 si_delete_shader(sctx, sel->gs_copy_shader);
1686
1687 util_queue_fence_destroy(&sel->ready);
1688 pipe_mutex_destroy(sel->mutex);
1689 free(sel->tokens);
1690 free(sel);
1691 }
1692
1693 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
1694 struct si_shader *vs, unsigned name,
1695 unsigned index, unsigned interpolate)
1696 {
1697 struct tgsi_shader_info *vsinfo = &vs->selector->info;
1698 unsigned j, offset, ps_input_cntl = 0;
1699
1700 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
1701 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
1702 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1703
1704 if (name == TGSI_SEMANTIC_PCOORD ||
1705 (name == TGSI_SEMANTIC_TEXCOORD &&
1706 sctx->sprite_coord_enable & (1 << index))) {
1707 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
1708 }
1709
1710 for (j = 0; j < vsinfo->num_outputs; j++) {
1711 if (name == vsinfo->output_semantic_name[j] &&
1712 index == vsinfo->output_semantic_index[j]) {
1713 offset = vs->info.vs_output_param_offset[j];
1714
1715 if (offset <= EXP_PARAM_OFFSET_31) {
1716 /* The input is loaded from parameter memory. */
1717 ps_input_cntl |= S_028644_OFFSET(offset);
1718 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
1719 /* The input is a DEFAULT_VAL constant. */
1720 assert(offset >= EXP_PARAM_DEFAULT_VAL_0000 &&
1721 offset <= EXP_PARAM_DEFAULT_VAL_1111);
1722
1723 offset -= EXP_PARAM_DEFAULT_VAL_0000;
1724 ps_input_cntl = S_028644_OFFSET(0x20) |
1725 S_028644_DEFAULT_VAL(offset);
1726 }
1727 break;
1728 }
1729 }
1730
1731 if (name == TGSI_SEMANTIC_PRIMID)
1732 /* PrimID is written after the last output. */
1733 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
1734 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
1735 /* No corresponding output found, load defaults into input.
1736 * Don't set any other bits.
1737 * (FLAT_SHADE=1 completely changes behavior) */
1738 ps_input_cntl = S_028644_OFFSET(0x20);
1739 /* D3D 9 behaviour. GL is undefined */
1740 if (name == TGSI_SEMANTIC_COLOR && index == 0)
1741 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
1742 }
1743 return ps_input_cntl;
1744 }
1745
1746 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
1747 {
1748 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1749 struct si_shader *ps = sctx->ps_shader.current;
1750 struct si_shader *vs = si_get_vs_state(sctx);
1751 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
1752 unsigned i, num_interp, num_written = 0, bcol_interp[2];
1753
1754 if (!ps || !ps->selector->info.num_inputs)
1755 return;
1756
1757 num_interp = si_get_ps_num_interp(ps);
1758 assert(num_interp > 0);
1759 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
1760
1761 for (i = 0; i < psinfo->num_inputs; i++) {
1762 unsigned name = psinfo->input_semantic_name[i];
1763 unsigned index = psinfo->input_semantic_index[i];
1764 unsigned interpolate = psinfo->input_interpolate[i];
1765
1766 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
1767 interpolate));
1768 num_written++;
1769
1770 if (name == TGSI_SEMANTIC_COLOR) {
1771 assert(index < ARRAY_SIZE(bcol_interp));
1772 bcol_interp[index] = interpolate;
1773 }
1774 }
1775
1776 if (ps->key.part.ps.prolog.color_two_side) {
1777 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
1778
1779 for (i = 0; i < 2; i++) {
1780 if (!(psinfo->colors_read & (0xf << (i * 4))))
1781 continue;
1782
1783 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
1784 i, bcol_interp[i]));
1785 num_written++;
1786 }
1787 }
1788 assert(num_interp == num_written);
1789 }
1790
1791 /**
1792 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1793 */
1794 static void si_init_config_add_vgt_flush(struct si_context *sctx)
1795 {
1796 if (sctx->init_config_has_vgt_flush)
1797 return;
1798
1799 /* Done by Vulkan before VGT_FLUSH. */
1800 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
1801 si_pm4_cmd_add(sctx->init_config,
1802 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1803 si_pm4_cmd_end(sctx->init_config, false);
1804
1805 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
1806 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
1807 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1808 si_pm4_cmd_end(sctx->init_config, false);
1809 sctx->init_config_has_vgt_flush = true;
1810 }
1811
1812 /* Initialize state related to ESGS / GSVS ring buffers */
1813 static bool si_update_gs_ring_buffers(struct si_context *sctx)
1814 {
1815 struct si_shader_selector *es =
1816 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
1817 struct si_shader_selector *gs = sctx->gs_shader.cso;
1818 struct si_pm4_state *pm4;
1819
1820 /* Chip constants. */
1821 unsigned num_se = sctx->screen->b.info.max_se;
1822 unsigned wave_size = 64;
1823 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1824 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1825 unsigned alignment = 256 * num_se;
1826 /* The maximum size is 63.999 MB per SE. */
1827 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1828
1829 /* Calculate the minimum size. */
1830 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
1831 wave_size, alignment);
1832
1833 /* These are recommended sizes, not minimum sizes. */
1834 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1835 es->esgs_itemsize * gs->gs_input_verts_per_prim;
1836 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1837 gs->max_gsvs_emit_size * (gs->max_gs_stream + 1);
1838
1839 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1840 esgs_ring_size = align(esgs_ring_size, alignment);
1841 gsvs_ring_size = align(gsvs_ring_size, alignment);
1842
1843 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1844 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1845
1846 /* Some rings don't have to be allocated if shaders don't use them.
1847 * (e.g. no varyings between ES and GS or GS and VS)
1848 */
1849 bool update_esgs = esgs_ring_size &&
1850 (!sctx->esgs_ring ||
1851 sctx->esgs_ring->width0 < esgs_ring_size);
1852 bool update_gsvs = gsvs_ring_size &&
1853 (!sctx->gsvs_ring ||
1854 sctx->gsvs_ring->width0 < gsvs_ring_size);
1855
1856 if (!update_esgs && !update_gsvs)
1857 return true;
1858
1859 if (update_esgs) {
1860 pipe_resource_reference(&sctx->esgs_ring, NULL);
1861 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, 0,
1862 PIPE_USAGE_DEFAULT,
1863 esgs_ring_size);
1864 if (!sctx->esgs_ring)
1865 return false;
1866 }
1867
1868 if (update_gsvs) {
1869 pipe_resource_reference(&sctx->gsvs_ring, NULL);
1870 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, 0,
1871 PIPE_USAGE_DEFAULT,
1872 gsvs_ring_size);
1873 if (!sctx->gsvs_ring)
1874 return false;
1875 }
1876
1877 /* Create the "init_config_gs_rings" state. */
1878 pm4 = CALLOC_STRUCT(si_pm4_state);
1879 if (!pm4)
1880 return false;
1881
1882 if (sctx->b.chip_class >= CIK) {
1883 if (sctx->esgs_ring)
1884 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
1885 sctx->esgs_ring->width0 / 256);
1886 if (sctx->gsvs_ring)
1887 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
1888 sctx->gsvs_ring->width0 / 256);
1889 } else {
1890 if (sctx->esgs_ring)
1891 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
1892 sctx->esgs_ring->width0 / 256);
1893 if (sctx->gsvs_ring)
1894 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
1895 sctx->gsvs_ring->width0 / 256);
1896 }
1897
1898 /* Set the state. */
1899 if (sctx->init_config_gs_rings)
1900 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
1901 sctx->init_config_gs_rings = pm4;
1902
1903 if (!sctx->init_config_has_vgt_flush) {
1904 si_init_config_add_vgt_flush(sctx);
1905 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1906 }
1907
1908 /* Flush the context to re-emit both init_config states. */
1909 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1910 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1911
1912 /* Set ring bindings. */
1913 if (sctx->esgs_ring) {
1914 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
1915 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1916 true, true, 4, 64, 0);
1917 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
1918 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1919 false, false, 0, 0, 0);
1920 }
1921 if (sctx->gsvs_ring)
1922 si_set_ring_buffer(&sctx->b.b, SI_VS_RING_GSVS,
1923 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
1924 false, false, 0, 0, 0);
1925 return true;
1926 }
1927
1928 static void si_update_gsvs_ring_bindings(struct si_context *sctx)
1929 {
1930 unsigned gsvs_itemsize = sctx->gs_shader.cso->max_gsvs_emit_size;
1931 uint64_t offset;
1932
1933 if (!sctx->gsvs_ring || gsvs_itemsize == sctx->last_gsvs_itemsize)
1934 return;
1935
1936 sctx->last_gsvs_itemsize = gsvs_itemsize;
1937
1938 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS0,
1939 sctx->gsvs_ring, gsvs_itemsize,
1940 64, true, true, 4, 16, 0);
1941
1942 offset = gsvs_itemsize * 64;
1943 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS1,
1944 sctx->gsvs_ring, gsvs_itemsize,
1945 64, true, true, 4, 16, offset);
1946
1947 offset = (gsvs_itemsize * 2) * 64;
1948 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS2,
1949 sctx->gsvs_ring, gsvs_itemsize,
1950 64, true, true, 4, 16, offset);
1951
1952 offset = (gsvs_itemsize * 3) * 64;
1953 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS3,
1954 sctx->gsvs_ring, gsvs_itemsize,
1955 64, true, true, 4, 16, offset);
1956 }
1957
1958 /**
1959 * @returns 1 if \p sel has been updated to use a new scratch buffer
1960 * 0 if not
1961 * < 0 if there was a failure
1962 */
1963 static int si_update_scratch_buffer(struct si_context *sctx,
1964 struct si_shader *shader)
1965 {
1966 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
1967 int r;
1968
1969 if (!shader)
1970 return 0;
1971
1972 /* This shader doesn't need a scratch buffer */
1973 if (shader->config.scratch_bytes_per_wave == 0)
1974 return 0;
1975
1976 /* This shader is already configured to use the current
1977 * scratch buffer. */
1978 if (shader->scratch_bo == sctx->scratch_buffer)
1979 return 0;
1980
1981 assert(sctx->scratch_buffer);
1982
1983 si_shader_apply_scratch_relocs(sctx, shader, &shader->config, scratch_va);
1984
1985 /* Replace the shader bo with a new bo that has the relocs applied. */
1986 r = si_shader_binary_upload(sctx->screen, shader);
1987 if (r)
1988 return r;
1989
1990 /* Update the shader state to use the new shader bo. */
1991 si_shader_init_pm4_state(sctx->screen, shader);
1992
1993 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
1994
1995 return 1;
1996 }
1997
1998 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
1999 {
2000 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2001 }
2002
2003 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2004 {
2005 return shader ? shader->config.scratch_bytes_per_wave : 0;
2006 }
2007
2008 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2009 {
2010 unsigned bytes = 0;
2011
2012 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2013 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2014 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2015 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
2016 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2017 return bytes;
2018 }
2019
2020 static bool si_update_spi_tmpring_size(struct si_context *sctx)
2021 {
2022 unsigned current_scratch_buffer_size =
2023 si_get_current_scratch_buffer_size(sctx);
2024 unsigned scratch_bytes_per_wave =
2025 si_get_max_scratch_bytes_per_wave(sctx);
2026 unsigned scratch_needed_size = scratch_bytes_per_wave *
2027 sctx->scratch_waves;
2028 unsigned spi_tmpring_size;
2029 int r;
2030
2031 if (scratch_needed_size > 0) {
2032 if (scratch_needed_size > current_scratch_buffer_size) {
2033 /* Create a bigger scratch buffer */
2034 r600_resource_reference(&sctx->scratch_buffer, NULL);
2035
2036 sctx->scratch_buffer = (struct r600_resource*)
2037 pipe_buffer_create(&sctx->screen->b.b, 0,
2038 PIPE_USAGE_DEFAULT, scratch_needed_size);
2039 if (!sctx->scratch_buffer)
2040 return false;
2041 sctx->emit_scratch_reloc = true;
2042 }
2043
2044 /* Update the shaders, so they are using the latest scratch. The
2045 * scratch buffer may have been changed since these shaders were
2046 * last used, so we still need to try to update them, even if
2047 * they require scratch buffers smaller than the current size.
2048 */
2049 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2050 if (r < 0)
2051 return false;
2052 if (r == 1)
2053 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2054
2055 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2056 if (r < 0)
2057 return false;
2058 if (r == 1)
2059 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2060
2061 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
2062 if (r < 0)
2063 return false;
2064 if (r == 1)
2065 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2066
2067 /* VS can be bound as LS, ES, or VS. */
2068 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2069 if (r < 0)
2070 return false;
2071 if (r == 1) {
2072 if (sctx->tes_shader.current)
2073 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2074 else if (sctx->gs_shader.current)
2075 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2076 else
2077 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2078 }
2079
2080 /* TES can be bound as ES or VS. */
2081 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2082 if (r < 0)
2083 return false;
2084 if (r == 1) {
2085 if (sctx->gs_shader.current)
2086 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2087 else
2088 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2089 }
2090 }
2091
2092 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2093 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
2094 "scratch size should already be aligned correctly.");
2095
2096 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
2097 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
2098 if (spi_tmpring_size != sctx->spi_tmpring_size) {
2099 sctx->spi_tmpring_size = spi_tmpring_size;
2100 sctx->emit_scratch_reloc = true;
2101 }
2102 return true;
2103 }
2104
2105 static void si_init_tess_factor_ring(struct si_context *sctx)
2106 {
2107 bool double_offchip_buffers = sctx->b.chip_class >= CIK;
2108 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2109 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
2110 sctx->screen->b.info.max_se;
2111 unsigned offchip_granularity;
2112
2113 switch (sctx->screen->tess_offchip_block_dw_size) {
2114 default:
2115 assert(0);
2116 /* fall through */
2117 case 8192:
2118 offchip_granularity = V_03093C_X_8K_DWORDS;
2119 break;
2120 case 4096:
2121 offchip_granularity = V_03093C_X_4K_DWORDS;
2122 break;
2123 }
2124
2125 switch (sctx->b.chip_class) {
2126 case SI:
2127 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2128 break;
2129 case CIK:
2130 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2131 break;
2132 case VI:
2133 default:
2134 max_offchip_buffers = MIN2(max_offchip_buffers, 512);
2135 break;
2136 }
2137
2138 assert(!sctx->tf_ring);
2139 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, 0,
2140 PIPE_USAGE_DEFAULT,
2141 32768 * sctx->screen->b.info.max_se);
2142 if (!sctx->tf_ring)
2143 return;
2144
2145 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
2146
2147 sctx->tess_offchip_ring = pipe_buffer_create(sctx->b.b.screen, 0,
2148 PIPE_USAGE_DEFAULT,
2149 max_offchip_buffers *
2150 sctx->screen->tess_offchip_block_dw_size * 4);
2151 if (!sctx->tess_offchip_ring)
2152 return;
2153
2154 si_init_config_add_vgt_flush(sctx);
2155
2156 /* Append these registers to the init config state. */
2157 if (sctx->b.chip_class >= CIK) {
2158 if (sctx->b.chip_class >= VI)
2159 --max_offchip_buffers;
2160
2161 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
2162 S_030938_SIZE(sctx->tf_ring->width0 / 4));
2163 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
2164 r600_resource(sctx->tf_ring)->gpu_address >> 8);
2165 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
2166 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2167 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
2168 } else {
2169 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
2170 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
2171 S_008988_SIZE(sctx->tf_ring->width0 / 4));
2172 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
2173 r600_resource(sctx->tf_ring)->gpu_address >> 8);
2174 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2175 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
2176 }
2177
2178 /* Flush the context to re-emit the init_config state.
2179 * This is done only once in a lifetime of a context.
2180 */
2181 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2182 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2183 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2184
2185 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_FACTOR, sctx->tf_ring,
2186 0, sctx->tf_ring->width0, false, false, 0, 0, 0);
2187
2188 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_OFFCHIP,
2189 sctx->tess_offchip_ring, 0,
2190 sctx->tess_offchip_ring->width0, false, false, 0, 0, 0);
2191 }
2192
2193 /**
2194 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
2195 * VS passes its outputs to TES directly, so the fixed-function shader only
2196 * has to write TESSOUTER and TESSINNER.
2197 */
2198 static void si_generate_fixed_func_tcs(struct si_context *sctx)
2199 {
2200 struct ureg_src outer, inner;
2201 struct ureg_dst tessouter, tessinner;
2202 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
2203
2204 if (!ureg)
2205 return; /* if we get here, we're screwed */
2206
2207 assert(!sctx->fixed_func_tcs_shader.cso);
2208
2209 outer = ureg_DECL_system_value(ureg,
2210 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
2211 inner = ureg_DECL_system_value(ureg,
2212 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
2213
2214 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
2215 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
2216
2217 ureg_MOV(ureg, tessouter, outer);
2218 ureg_MOV(ureg, tessinner, inner);
2219 ureg_END(ureg);
2220
2221 sctx->fixed_func_tcs_shader.cso =
2222 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
2223 }
2224
2225 static void si_update_vgt_shader_config(struct si_context *sctx)
2226 {
2227 /* Calculate the index of the config.
2228 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
2229 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
2230 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
2231
2232 if (!*pm4) {
2233 uint32_t stages = 0;
2234
2235 *pm4 = CALLOC_STRUCT(si_pm4_state);
2236
2237 if (sctx->tes_shader.cso) {
2238 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2239 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2240
2241 if (sctx->gs_shader.cso)
2242 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2243 S_028B54_GS_EN(1) |
2244 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2245 else
2246 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2247 } else if (sctx->gs_shader.cso) {
2248 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2249 S_028B54_GS_EN(1) |
2250 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2251 }
2252
2253 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
2254 }
2255 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
2256 }
2257
2258 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
2259 {
2260 struct pipe_stream_output_info *so = &shader->so;
2261 uint32_t enabled_stream_buffers_mask = 0;
2262 int i;
2263
2264 for (i = 0; i < so->num_outputs; i++)
2265 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
2266 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
2267 sctx->b.streamout.stride_in_dw = shader->so.stride;
2268 }
2269
2270 bool si_update_shaders(struct si_context *sctx)
2271 {
2272 struct pipe_context *ctx = (struct pipe_context*)sctx;
2273 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2274 int r;
2275
2276 /* Update stages before GS. */
2277 if (sctx->tes_shader.cso) {
2278 if (!sctx->tf_ring) {
2279 si_init_tess_factor_ring(sctx);
2280 if (!sctx->tf_ring)
2281 return false;
2282 }
2283
2284 /* VS as LS */
2285 r = si_shader_select(ctx, &sctx->vs_shader);
2286 if (r)
2287 return false;
2288 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2289
2290 if (sctx->tcs_shader.cso) {
2291 r = si_shader_select(ctx, &sctx->tcs_shader);
2292 if (r)
2293 return false;
2294 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2295 } else {
2296 if (!sctx->fixed_func_tcs_shader.cso) {
2297 si_generate_fixed_func_tcs(sctx);
2298 if (!sctx->fixed_func_tcs_shader.cso)
2299 return false;
2300 }
2301
2302 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader);
2303 if (r)
2304 return false;
2305 si_pm4_bind_state(sctx, hs,
2306 sctx->fixed_func_tcs_shader.current->pm4);
2307 }
2308
2309 r = si_shader_select(ctx, &sctx->tes_shader);
2310 if (r)
2311 return false;
2312
2313 if (sctx->gs_shader.cso) {
2314 /* TES as ES */
2315 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2316 } else {
2317 /* TES as VS */
2318 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2319 si_update_so(sctx, sctx->tes_shader.cso);
2320 }
2321 } else if (sctx->gs_shader.cso) {
2322 /* VS as ES */
2323 r = si_shader_select(ctx, &sctx->vs_shader);
2324 if (r)
2325 return false;
2326 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2327 } else {
2328 /* VS as VS */
2329 r = si_shader_select(ctx, &sctx->vs_shader);
2330 if (r)
2331 return false;
2332 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2333 si_update_so(sctx, sctx->vs_shader.cso);
2334 }
2335
2336 /* Update GS. */
2337 if (sctx->gs_shader.cso) {
2338 r = si_shader_select(ctx, &sctx->gs_shader);
2339 if (r)
2340 return false;
2341 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2342 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
2343 si_update_so(sctx, sctx->gs_shader.cso);
2344
2345 if (!si_update_gs_ring_buffers(sctx))
2346 return false;
2347
2348 si_update_gsvs_ring_bindings(sctx);
2349 } else {
2350 si_pm4_bind_state(sctx, gs, NULL);
2351 si_pm4_bind_state(sctx, es, NULL);
2352 }
2353
2354 si_update_vgt_shader_config(sctx);
2355
2356 if (sctx->ps_shader.cso) {
2357 unsigned db_shader_control;
2358
2359 r = si_shader_select(ctx, &sctx->ps_shader);
2360 if (r)
2361 return false;
2362 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2363
2364 db_shader_control =
2365 sctx->ps_shader.cso->db_shader_control |
2366 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
2367
2368 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
2369 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
2370 sctx->flatshade != rs->flatshade) {
2371 sctx->sprite_coord_enable = rs->sprite_coord_enable;
2372 sctx->flatshade = rs->flatshade;
2373 si_mark_atom_dirty(sctx, &sctx->spi_map);
2374 }
2375
2376 if (sctx->b.family == CHIP_STONEY && si_pm4_state_changed(sctx, ps))
2377 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2378
2379 if (sctx->ps_db_shader_control != db_shader_control) {
2380 sctx->ps_db_shader_control = db_shader_control;
2381 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2382 }
2383
2384 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
2385 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
2386 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2387
2388 if (sctx->b.chip_class == SI)
2389 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2390
2391 if (sctx->framebuffer.nr_samples <= 1)
2392 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2393 }
2394 }
2395
2396 if (si_pm4_state_changed(sctx, ls) ||
2397 si_pm4_state_changed(sctx, hs) ||
2398 si_pm4_state_changed(sctx, es) ||
2399 si_pm4_state_changed(sctx, gs) ||
2400 si_pm4_state_changed(sctx, vs) ||
2401 si_pm4_state_changed(sctx, ps)) {
2402 if (!si_update_spi_tmpring_size(sctx))
2403 return false;
2404 }
2405
2406 sctx->do_update_shaders = false;
2407 return true;
2408 }
2409
2410 void si_init_shader_functions(struct si_context *sctx)
2411 {
2412 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
2413
2414 sctx->b.b.create_vs_state = si_create_shader_selector;
2415 sctx->b.b.create_tcs_state = si_create_shader_selector;
2416 sctx->b.b.create_tes_state = si_create_shader_selector;
2417 sctx->b.b.create_gs_state = si_create_shader_selector;
2418 sctx->b.b.create_fs_state = si_create_shader_selector;
2419
2420 sctx->b.b.bind_vs_state = si_bind_vs_shader;
2421 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
2422 sctx->b.b.bind_tes_state = si_bind_tes_shader;
2423 sctx->b.b.bind_gs_state = si_bind_gs_shader;
2424 sctx->b.b.bind_fs_state = si_bind_ps_shader;
2425
2426 sctx->b.b.delete_vs_state = si_delete_shader_selector;
2427 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
2428 sctx->b.b.delete_tes_state = si_delete_shader_selector;
2429 sctx->b.b.delete_gs_state = si_delete_shader_selector;
2430 sctx->b.b.delete_fs_state = si_delete_shader_selector;
2431 }