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gallium: remove helpers converting to/from TGSI_PROCESSOR_*
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31 #include "radeon/r600_cs.h"
32
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/hash_table.h"
36 #include "util/u_hash.h"
37 #include "util/u_memory.h"
38 #include "util/u_prim.h"
39 #include "util/u_simple_shaders.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
45 * integer.
46 */
47 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
48 {
49 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
50 sizeof(struct tgsi_token);
51 unsigned size = 4 + tgsi_size + sizeof(sel->so);
52 char *result = (char*)MALLOC(size);
53
54 if (!result)
55 return NULL;
56
57 *((uint32_t*)result) = size;
58 memcpy(result + 4, sel->tokens, tgsi_size);
59 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
60 return result;
61 }
62
63 /** Copy "data" to "ptr" and return the next dword following copied data. */
64 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
65 {
66 memcpy(ptr, data, size);
67 ptr += DIV_ROUND_UP(size, 4);
68 return ptr;
69 }
70
71 /** Read data from "ptr". Return the next dword following the data. */
72 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
73 {
74 memcpy(data, ptr, size);
75 ptr += DIV_ROUND_UP(size, 4);
76 return ptr;
77 }
78
79 /**
80 * Write the size as uint followed by the data. Return the next dword
81 * following the copied data.
82 */
83 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
84 {
85 *ptr++ = size;
86 return write_data(ptr, data, size);
87 }
88
89 /**
90 * Read the size as uint followed by the data. Return both via parameters.
91 * Return the next dword following the data.
92 */
93 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
94 {
95 *size = *ptr++;
96 assert(*data == NULL);
97 *data = malloc(*size);
98 return read_data(ptr, *data, *size);
99 }
100
101 /**
102 * Return the shader binary in a buffer. The first 4 bytes contain its size
103 * as integer.
104 */
105 static void *si_get_shader_binary(struct si_shader *shader)
106 {
107 /* There is always a size of data followed by the data itself. */
108 unsigned relocs_size = shader->binary.reloc_count *
109 sizeof(shader->binary.relocs[0]);
110 unsigned disasm_size = strlen(shader->binary.disasm_string) + 1;
111 unsigned size =
112 4 + /* total size */
113 4 + /* CRC32 of the data below */
114 align(sizeof(shader->config), 4) +
115 align(sizeof(shader->info), 4) +
116 4 + align(shader->binary.code_size, 4) +
117 4 + align(shader->binary.rodata_size, 4) +
118 4 + align(relocs_size, 4) +
119 4 + align(disasm_size, 4);
120 void *buffer = CALLOC(1, size);
121 uint32_t *ptr = (uint32_t*)buffer;
122
123 if (!buffer)
124 return NULL;
125
126 *ptr++ = size;
127 ptr++; /* CRC32 is calculated at the end. */
128
129 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
130 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
131 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
132 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
133 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
134 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
135 assert((char *)ptr - (char *)buffer == size);
136
137 /* Compute CRC32. */
138 ptr = (uint32_t*)buffer;
139 ptr++;
140 *ptr = util_hash_crc32(ptr + 1, size - 8);
141
142 return buffer;
143 }
144
145 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
146 {
147 uint32_t *ptr = (uint32_t*)binary;
148 uint32_t size = *ptr++;
149 uint32_t crc32 = *ptr++;
150 unsigned chunk_size;
151
152 if (util_hash_crc32(ptr, size - 8) != crc32) {
153 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
154 return false;
155 }
156
157 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
158 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
159 ptr = read_chunk(ptr, (void**)&shader->binary.code,
160 &shader->binary.code_size);
161 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
162 &shader->binary.rodata_size);
163 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
164 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
165 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
166
167 return true;
168 }
169
170 /**
171 * Insert a shader into the cache. It's assumed the shader is not in the cache.
172 * Use si_shader_cache_load_shader before calling this.
173 *
174 * Returns false on failure, in which case the tgsi_binary should be freed.
175 */
176 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
177 void *tgsi_binary,
178 struct si_shader *shader)
179 {
180 void *hw_binary = si_get_shader_binary(shader);
181
182 if (!hw_binary)
183 return false;
184
185 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
186 hw_binary) == NULL) {
187 FREE(hw_binary);
188 return false;
189 }
190
191 return true;
192 }
193
194 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
195 void *tgsi_binary,
196 struct si_shader *shader)
197 {
198 struct hash_entry *entry =
199 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
200 if (!entry)
201 return false;
202
203 return si_load_shader_binary(shader, entry->data);
204 }
205
206 static uint32_t si_shader_cache_key_hash(const void *key)
207 {
208 /* The first dword is the key size. */
209 return util_hash_crc32(key, *(uint32_t*)key);
210 }
211
212 static bool si_shader_cache_key_equals(const void *a, const void *b)
213 {
214 uint32_t *keya = (uint32_t*)a;
215 uint32_t *keyb = (uint32_t*)b;
216
217 /* The first dword is the key size. */
218 if (*keya != *keyb)
219 return false;
220
221 return memcmp(keya, keyb, *keya) == 0;
222 }
223
224 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
225 {
226 FREE((void*)entry->key);
227 FREE(entry->data);
228 }
229
230 bool si_init_shader_cache(struct si_screen *sscreen)
231 {
232 pipe_mutex_init(sscreen->shader_cache_mutex);
233 sscreen->shader_cache =
234 _mesa_hash_table_create(NULL,
235 si_shader_cache_key_hash,
236 si_shader_cache_key_equals);
237 return sscreen->shader_cache != NULL;
238 }
239
240 void si_destroy_shader_cache(struct si_screen *sscreen)
241 {
242 if (sscreen->shader_cache)
243 _mesa_hash_table_destroy(sscreen->shader_cache,
244 si_destroy_shader_cache_entry);
245 pipe_mutex_destroy(sscreen->shader_cache_mutex);
246 }
247
248 /* SHADER STATES */
249
250 static void si_set_tesseval_regs(struct si_shader *shader,
251 struct si_pm4_state *pm4)
252 {
253 struct tgsi_shader_info *info = &shader->selector->info;
254 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
255 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
256 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
257 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
258 unsigned type, partitioning, topology;
259
260 switch (tes_prim_mode) {
261 case PIPE_PRIM_LINES:
262 type = V_028B6C_TESS_ISOLINE;
263 break;
264 case PIPE_PRIM_TRIANGLES:
265 type = V_028B6C_TESS_TRIANGLE;
266 break;
267 case PIPE_PRIM_QUADS:
268 type = V_028B6C_TESS_QUAD;
269 break;
270 default:
271 assert(0);
272 return;
273 }
274
275 switch (tes_spacing) {
276 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
277 partitioning = V_028B6C_PART_FRAC_ODD;
278 break;
279 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
280 partitioning = V_028B6C_PART_FRAC_EVEN;
281 break;
282 case PIPE_TESS_SPACING_EQUAL:
283 partitioning = V_028B6C_PART_INTEGER;
284 break;
285 default:
286 assert(0);
287 return;
288 }
289
290 if (tes_point_mode)
291 topology = V_028B6C_OUTPUT_POINT;
292 else if (tes_prim_mode == PIPE_PRIM_LINES)
293 topology = V_028B6C_OUTPUT_LINE;
294 else if (tes_vertex_order_cw)
295 /* for some reason, this must be the other way around */
296 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
297 else
298 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
299
300 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
301 S_028B6C_TYPE(type) |
302 S_028B6C_PARTITIONING(partitioning) |
303 S_028B6C_TOPOLOGY(topology));
304 }
305
306 static void si_shader_ls(struct si_shader *shader)
307 {
308 struct si_pm4_state *pm4;
309 unsigned vgpr_comp_cnt;
310 uint64_t va;
311
312 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
313 if (!pm4)
314 return;
315
316 va = shader->bo->gpu_address;
317 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
318
319 /* We need at least 2 components for LS.
320 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
321 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 1;
322
323 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
324 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
325
326 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
327 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
328 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
329 S_00B528_DX10_CLAMP(1) |
330 S_00B528_FLOAT_MODE(shader->config.float_mode);
331 shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_LS_NUM_USER_SGPR) |
332 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
333 }
334
335 static void si_shader_hs(struct si_shader *shader)
336 {
337 struct si_pm4_state *pm4;
338 uint64_t va;
339
340 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
341 if (!pm4)
342 return;
343
344 va = shader->bo->gpu_address;
345 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
346
347 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
348 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
349 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
350 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
351 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
352 S_00B428_DX10_CLAMP(1) |
353 S_00B428_FLOAT_MODE(shader->config.float_mode));
354 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
355 S_00B42C_USER_SGPR(SI_TCS_NUM_USER_SGPR) |
356 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
357 }
358
359 static void si_shader_es(struct si_shader *shader)
360 {
361 struct si_pm4_state *pm4;
362 unsigned num_user_sgprs;
363 unsigned vgpr_comp_cnt;
364 uint64_t va;
365
366 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
367
368 if (!pm4)
369 return;
370
371 va = shader->bo->gpu_address;
372 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
373
374 if (shader->selector->type == PIPE_SHADER_VERTEX) {
375 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
376 num_user_sgprs = SI_ES_NUM_USER_SGPR;
377 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
378 vgpr_comp_cnt = 3; /* all components are needed for TES */
379 num_user_sgprs = SI_TES_NUM_USER_SGPR;
380 } else
381 unreachable("invalid shader selector type");
382
383 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
384 shader->selector->esgs_itemsize / 4);
385 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
386 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
387 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
388 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
389 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
390 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
391 S_00B328_DX10_CLAMP(1) |
392 S_00B328_FLOAT_MODE(shader->config.float_mode));
393 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
394 S_00B32C_USER_SGPR(num_user_sgprs) |
395 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
396
397 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
398 si_set_tesseval_regs(shader, pm4);
399 }
400
401 /**
402 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
403 * geometry shader.
404 */
405 static uint32_t si_vgt_gs_mode(struct si_shader *shader)
406 {
407 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
408 unsigned cut_mode;
409
410 if (gs_max_vert_out <= 128) {
411 cut_mode = V_028A40_GS_CUT_128;
412 } else if (gs_max_vert_out <= 256) {
413 cut_mode = V_028A40_GS_CUT_256;
414 } else if (gs_max_vert_out <= 512) {
415 cut_mode = V_028A40_GS_CUT_512;
416 } else {
417 assert(gs_max_vert_out <= 1024);
418 cut_mode = V_028A40_GS_CUT_1024;
419 }
420
421 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
422 S_028A40_CUT_MODE(cut_mode)|
423 S_028A40_ES_WRITE_OPTIMIZE(1) |
424 S_028A40_GS_WRITE_OPTIMIZE(1);
425 }
426
427 static void si_shader_gs(struct si_shader *shader)
428 {
429 unsigned gs_vert_itemsize = shader->selector->gsvs_vertex_size;
430 unsigned gsvs_itemsize = shader->selector->max_gsvs_emit_size >> 2;
431 unsigned gs_num_invocations = shader->selector->gs_num_invocations;
432 struct si_pm4_state *pm4;
433 uint64_t va;
434 unsigned max_stream = shader->selector->max_gs_stream;
435
436 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
437 assert(gsvs_itemsize < (1 << 15));
438
439 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
440
441 if (!pm4)
442 return;
443
444 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(shader));
445
446 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
447 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize * ((max_stream >= 2) ? 2 : 1));
448 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize * ((max_stream >= 3) ? 3 : 1));
449
450 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize * (max_stream + 1));
451
452 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, shader->selector->gs_max_out_vertices);
453
454 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize >> 2);
455 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? gs_vert_itemsize >> 2 : 0);
456 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? gs_vert_itemsize >> 2 : 0);
457 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? gs_vert_itemsize >> 2 : 0);
458
459 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
460 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
461 S_028B90_ENABLE(gs_num_invocations > 0));
462
463 va = shader->bo->gpu_address;
464 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
465 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
466 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
467
468 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
469 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
470 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
471 S_00B228_DX10_CLAMP(1) |
472 S_00B228_FLOAT_MODE(shader->config.float_mode));
473 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
474 S_00B22C_USER_SGPR(SI_GS_NUM_USER_SGPR) |
475 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
476 }
477
478 /**
479 * Compute the state for \p shader, which will run as a vertex shader on the
480 * hardware.
481 *
482 * If \p gs is non-NULL, it points to the geometry shader for which this shader
483 * is the copy shader.
484 */
485 static void si_shader_vs(struct si_shader *shader, struct si_shader *gs)
486 {
487 struct si_pm4_state *pm4;
488 unsigned num_user_sgprs;
489 unsigned nparams, vgpr_comp_cnt;
490 uint64_t va;
491 unsigned window_space =
492 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
493 bool enable_prim_id = si_vs_exports_prim_id(shader);
494
495 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
496
497 if (!pm4)
498 return;
499
500 /* We always write VGT_GS_MODE in the VS state, because every switch
501 * between different shader pipelines involving a different GS or no
502 * GS at all involves a switch of the VS (different GS use different
503 * copy shaders). On the other hand, when the API switches from a GS to
504 * no GS and then back to the same GS used originally, the GS state is
505 * not sent again.
506 */
507 if (!gs) {
508 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
509 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
510 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
511 } else {
512 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
513 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
514 }
515
516 va = shader->bo->gpu_address;
517 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
518
519 if (gs) {
520 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
521 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
522 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
523 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
524 num_user_sgprs = SI_VS_NUM_USER_SGPR;
525 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
526 vgpr_comp_cnt = 3; /* all components are needed for TES */
527 num_user_sgprs = SI_TES_NUM_USER_SGPR;
528 } else
529 unreachable("invalid shader selector type");
530
531 /* VS is required to export at least one param. */
532 nparams = MAX2(shader->info.nr_param_exports, 1);
533 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
534 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
535
536 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
537 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
538 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
539 V_02870C_SPI_SHADER_4COMP :
540 V_02870C_SPI_SHADER_NONE) |
541 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
542 V_02870C_SPI_SHADER_4COMP :
543 V_02870C_SPI_SHADER_NONE) |
544 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
545 V_02870C_SPI_SHADER_4COMP :
546 V_02870C_SPI_SHADER_NONE));
547
548 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
549 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
550 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
551 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
552 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
553 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
554 S_00B128_DX10_CLAMP(1) |
555 S_00B128_FLOAT_MODE(shader->config.float_mode));
556 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
557 S_00B12C_USER_SGPR(num_user_sgprs) |
558 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
559 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
560 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
561 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
562 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
563 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
564 if (window_space)
565 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
566 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
567 else
568 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
569 S_028818_VTX_W0_FMT(1) |
570 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
571 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
572 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
573
574 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
575 si_set_tesseval_regs(shader, pm4);
576 }
577
578 static unsigned si_get_ps_num_interp(struct si_shader *ps)
579 {
580 struct tgsi_shader_info *info = &ps->selector->info;
581 unsigned num_colors = !!(info->colors_read & 0x0f) +
582 !!(info->colors_read & 0xf0);
583 unsigned num_interp = ps->selector->info.num_inputs +
584 (ps->key.ps.prolog.color_two_side ? num_colors : 0);
585
586 assert(num_interp <= 32);
587 return MIN2(num_interp, 32);
588 }
589
590 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
591 {
592 unsigned value = shader->key.ps.epilog.spi_shader_col_format;
593 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
594
595 /* If the i-th target format is set, all previous target formats must
596 * be non-zero to avoid hangs.
597 */
598 for (i = 0; i < num_targets; i++)
599 if (!(value & (0xf << (i * 4))))
600 value |= V_028714_SPI_SHADER_32_R << (i * 4);
601
602 return value;
603 }
604
605 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
606 {
607 unsigned i, cb_shader_mask = 0;
608
609 for (i = 0; i < 8; i++) {
610 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
611 case V_028714_SPI_SHADER_ZERO:
612 break;
613 case V_028714_SPI_SHADER_32_R:
614 cb_shader_mask |= 0x1 << (i * 4);
615 break;
616 case V_028714_SPI_SHADER_32_GR:
617 cb_shader_mask |= 0x3 << (i * 4);
618 break;
619 case V_028714_SPI_SHADER_32_AR:
620 cb_shader_mask |= 0x9 << (i * 4);
621 break;
622 case V_028714_SPI_SHADER_FP16_ABGR:
623 case V_028714_SPI_SHADER_UNORM16_ABGR:
624 case V_028714_SPI_SHADER_SNORM16_ABGR:
625 case V_028714_SPI_SHADER_UINT16_ABGR:
626 case V_028714_SPI_SHADER_SINT16_ABGR:
627 case V_028714_SPI_SHADER_32_ABGR:
628 cb_shader_mask |= 0xf << (i * 4);
629 break;
630 default:
631 assert(0);
632 }
633 }
634 return cb_shader_mask;
635 }
636
637 static void si_shader_ps(struct si_shader *shader)
638 {
639 struct tgsi_shader_info *info = &shader->selector->info;
640 struct si_pm4_state *pm4;
641 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
642 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
643 uint64_t va;
644 bool has_centroid;
645 unsigned input_ena = shader->config.spi_ps_input_ena;
646
647 /* we need to enable at least one of them, otherwise we hang the GPU */
648 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
649 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
650 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
651 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
652 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
653 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
654 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
655 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
656
657 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
658
659 if (!pm4)
660 return;
661
662 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
663 * Possible vaules:
664 * 0 -> Position = pixel center
665 * 1 -> Position = pixel centroid
666 * 2 -> Position = at sample position
667 *
668 * From GLSL 4.5 specification, section 7.1:
669 * "The variable gl_FragCoord is available as an input variable from
670 * within fragment shaders and it holds the window relative coordinates
671 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
672 * value can be for any location within the pixel, or one of the
673 * fragment samples. The use of centroid does not further restrict
674 * this value to be inside the current primitive."
675 *
676 * Meaning that centroid has no effect and we can return anything within
677 * the pixel. Thus, return the value at sample position, because that's
678 * the most accurate one shaders can get.
679 */
680 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
681
682 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
683 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
684 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
685
686 spi_shader_col_format = si_get_spi_shader_col_format(shader);
687 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
688
689 /* This must be non-zero for alpha-test/kill to work.
690 * The hardware ignores the EXEC mask if no export memory is allocated.
691 * Don't add this to CB_SHADER_MASK.
692 */
693 if (!spi_shader_col_format &&
694 !info->writes_z && !info->writes_stencil && !info->writes_samplemask &&
695 (shader->selector->info.uses_kill ||
696 shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS))
697 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
698
699 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
700 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
701 shader->config.spi_ps_input_addr);
702
703 /* Set interpolation controls. */
704 has_centroid = G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena) ||
705 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena);
706
707 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
708 S_0286D8_BC_OPTIMIZE_DISABLE(has_centroid);
709
710 /* Set registers. */
711 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
712 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
713
714 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
715 info->writes_samplemask ? V_028710_SPI_SHADER_32_ABGR :
716 info->writes_stencil ? V_028710_SPI_SHADER_32_GR :
717 info->writes_z ? V_028710_SPI_SHADER_32_R :
718 V_028710_SPI_SHADER_ZERO);
719
720 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
721 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
722
723 va = shader->bo->gpu_address;
724 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
725 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
726 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
727
728 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
729 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
730 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
731 S_00B028_DX10_CLAMP(1) |
732 S_00B028_FLOAT_MODE(shader->config.float_mode));
733 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
734 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
735 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
736 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
737
738 /* Prefer RE_Z if the shader is complex enough. The requirement is either:
739 * - the shader uses at least 2 VMEM instructions, or
740 * - the code size is at least 50 2-dword instructions or 100 1-dword
741 * instructions.
742 *
743 * Shaders with side effects that must execute independently of the
744 * depth test require LATE_Z.
745 */
746 if (info->writes_memory &&
747 !info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL])
748 shader->z_order = V_02880C_LATE_Z;
749 else if (info->num_memory_instructions >= 2 ||
750 shader->binary.code_size > 100*4)
751 shader->z_order = V_02880C_EARLY_Z_THEN_RE_Z;
752 else
753 shader->z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
754 }
755
756 static void si_shader_init_pm4_state(struct si_shader *shader)
757 {
758
759 if (shader->pm4)
760 si_pm4_free_state_simple(shader->pm4);
761
762 switch (shader->selector->type) {
763 case PIPE_SHADER_VERTEX:
764 if (shader->key.vs.as_ls)
765 si_shader_ls(shader);
766 else if (shader->key.vs.as_es)
767 si_shader_es(shader);
768 else
769 si_shader_vs(shader, NULL);
770 break;
771 case PIPE_SHADER_TESS_CTRL:
772 si_shader_hs(shader);
773 break;
774 case PIPE_SHADER_TESS_EVAL:
775 if (shader->key.tes.as_es)
776 si_shader_es(shader);
777 else
778 si_shader_vs(shader, NULL);
779 break;
780 case PIPE_SHADER_GEOMETRY:
781 si_shader_gs(shader);
782 si_shader_vs(shader->gs_copy_shader, shader);
783 break;
784 case PIPE_SHADER_FRAGMENT:
785 si_shader_ps(shader);
786 break;
787 default:
788 assert(0);
789 }
790 }
791
792 static unsigned si_get_alpha_test_func(struct si_context *sctx)
793 {
794 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
795 if (sctx->queued.named.dsa &&
796 !sctx->framebuffer.cb0_is_integer)
797 return sctx->queued.named.dsa->alpha_func;
798
799 return PIPE_FUNC_ALWAYS;
800 }
801
802 /* Compute the key for the hw shader variant */
803 static inline void si_shader_selector_key(struct pipe_context *ctx,
804 struct si_shader_selector *sel,
805 union si_shader_key *key)
806 {
807 struct si_context *sctx = (struct si_context *)ctx;
808 unsigned i;
809
810 memset(key, 0, sizeof(*key));
811
812 switch (sel->type) {
813 case PIPE_SHADER_VERTEX:
814 if (sctx->vertex_elements) {
815 unsigned count = MIN2(sel->info.num_inputs,
816 sctx->vertex_elements->count);
817 for (i = 0; i < count; ++i)
818 key->vs.prolog.instance_divisors[i] =
819 sctx->vertex_elements->elements[i].instance_divisor;
820 }
821 if (sctx->tes_shader.cso)
822 key->vs.as_ls = 1;
823 else if (sctx->gs_shader.cso)
824 key->vs.as_es = 1;
825
826 if (!sctx->gs_shader.cso && sctx->ps_shader.cso &&
827 sctx->ps_shader.cso->info.uses_primid)
828 key->vs.epilog.export_prim_id = 1;
829 break;
830 case PIPE_SHADER_TESS_CTRL:
831 key->tcs.epilog.prim_mode =
832 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
833 break;
834 case PIPE_SHADER_TESS_EVAL:
835 if (sctx->gs_shader.cso)
836 key->tes.as_es = 1;
837 else if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
838 key->tes.epilog.export_prim_id = 1;
839 break;
840 case PIPE_SHADER_GEOMETRY:
841 break;
842 case PIPE_SHADER_FRAGMENT: {
843 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
844 struct si_state_blend *blend = sctx->queued.named.blend;
845
846 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
847 sel->info.colors_written == 0x1)
848 key->ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
849
850 if (blend) {
851 /* Select the shader color format based on whether
852 * blending or alpha are needed.
853 */
854 key->ps.epilog.spi_shader_col_format =
855 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
856 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
857 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
858 sctx->framebuffer.spi_shader_col_format_blend) |
859 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
860 sctx->framebuffer.spi_shader_col_format_alpha) |
861 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
862 sctx->framebuffer.spi_shader_col_format);
863 } else
864 key->ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
865
866 /* If alpha-to-coverage is enabled, we have to export alpha
867 * even if there is no color buffer.
868 */
869 if (!(key->ps.epilog.spi_shader_col_format & 0xf) &&
870 blend && blend->alpha_to_coverage)
871 key->ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
872
873 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
874 * to the range supported by the type if a channel has less
875 * than 16 bits and the export format is 16_ABGR.
876 */
877 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII)
878 key->ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
879
880 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
881 if (!key->ps.epilog.last_cbuf) {
882 key->ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
883 key->ps.epilog.color_is_int8 &= sel->info.colors_written;
884 }
885
886 if (rs) {
887 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
888 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
889 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
890 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
891
892 key->ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
893
894 if (sctx->queued.named.blend) {
895 key->ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
896 rs->multisample_enable &&
897 !sctx->framebuffer.cb0_is_integer;
898 }
899
900 key->ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
901 key->ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
902 (is_line && rs->line_smooth)) &&
903 sctx->framebuffer.nr_samples <= 1;
904 key->ps.epilog.clamp_color = rs->clamp_fragment_color;
905
906 key->ps.prolog.force_persample_interp =
907 rs->force_persample_interp &&
908 rs->multisample_enable &&
909 sctx->framebuffer.nr_samples > 1 &&
910 sctx->ps_iter_samples > 1 &&
911 (sel->info.uses_persp_center ||
912 sel->info.uses_persp_centroid ||
913 sel->info.uses_linear_center ||
914 sel->info.uses_linear_centroid);
915 }
916
917 key->ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
918 break;
919 }
920 default:
921 assert(0);
922 }
923 }
924
925 /* Select the hw shader variant depending on the current state. */
926 static int si_shader_select_with_key(struct pipe_context *ctx,
927 struct si_shader_ctx_state *state,
928 union si_shader_key *key)
929 {
930 struct si_context *sctx = (struct si_context *)ctx;
931 struct si_shader_selector *sel = state->cso;
932 struct si_shader *current = state->current;
933 struct si_shader *iter, *shader = NULL;
934 int r;
935
936 /* Check if we don't need to change anything.
937 * This path is also used for most shaders that don't need multiple
938 * variants, it will cost just a computation of the key and this
939 * test. */
940 if (likely(current && memcmp(&current->key, key, sizeof(*key)) == 0))
941 return 0;
942
943 pipe_mutex_lock(sel->mutex);
944
945 /* Find the shader variant. */
946 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
947 /* Don't check the "current" shader. We checked it above. */
948 if (current != iter &&
949 memcmp(&iter->key, key, sizeof(*key)) == 0) {
950 state->current = iter;
951 pipe_mutex_unlock(sel->mutex);
952 return 0;
953 }
954 }
955
956 /* Build a new shader. */
957 shader = CALLOC_STRUCT(si_shader);
958 if (!shader) {
959 pipe_mutex_unlock(sel->mutex);
960 return -ENOMEM;
961 }
962 shader->selector = sel;
963 shader->key = *key;
964
965 r = si_shader_create(sctx->screen, sctx->tm, shader, &sctx->b.debug);
966 if (unlikely(r)) {
967 R600_ERR("Failed to build shader variant (type=%u) %d\n",
968 sel->type, r);
969 FREE(shader);
970 pipe_mutex_unlock(sel->mutex);
971 return r;
972 }
973 si_shader_init_pm4_state(shader);
974
975 if (!sel->last_variant) {
976 sel->first_variant = shader;
977 sel->last_variant = shader;
978 } else {
979 sel->last_variant->next_variant = shader;
980 sel->last_variant = shader;
981 }
982 state->current = shader;
983 pipe_mutex_unlock(sel->mutex);
984 return 0;
985 }
986
987 static int si_shader_select(struct pipe_context *ctx,
988 struct si_shader_ctx_state *state)
989 {
990 union si_shader_key key;
991
992 si_shader_selector_key(ctx, state->cso, &key);
993 return si_shader_select_with_key(ctx, state, &key);
994 }
995
996 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
997 union si_shader_key *key)
998 {
999 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1000
1001 switch (info->processor) {
1002 case PIPE_SHADER_VERTEX:
1003 switch (next_shader) {
1004 case PIPE_SHADER_GEOMETRY:
1005 key->vs.as_es = 1;
1006 break;
1007 case PIPE_SHADER_TESS_CTRL:
1008 case PIPE_SHADER_TESS_EVAL:
1009 key->vs.as_ls = 1;
1010 break;
1011 }
1012 break;
1013
1014 case PIPE_SHADER_TESS_EVAL:
1015 if (next_shader == PIPE_SHADER_GEOMETRY)
1016 key->tes.as_es = 1;
1017 break;
1018 }
1019 }
1020
1021 static void *si_create_shader_selector(struct pipe_context *ctx,
1022 const struct pipe_shader_state *state)
1023 {
1024 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1025 struct si_context *sctx = (struct si_context*)ctx;
1026 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
1027 int i;
1028
1029 if (!sel)
1030 return NULL;
1031
1032 sel->tokens = tgsi_dup_tokens(state->tokens);
1033 if (!sel->tokens) {
1034 FREE(sel);
1035 return NULL;
1036 }
1037
1038 sel->so = state->stream_output;
1039 tgsi_scan_shader(state->tokens, &sel->info);
1040 sel->type = sel->info.processor;
1041 p_atomic_inc(&sscreen->b.num_shaders_created);
1042
1043 /* Set which opcode uses which (i,j) pair. */
1044 if (sel->info.uses_persp_opcode_interp_centroid)
1045 sel->info.uses_persp_centroid = true;
1046
1047 if (sel->info.uses_linear_opcode_interp_centroid)
1048 sel->info.uses_linear_centroid = true;
1049
1050 if (sel->info.uses_persp_opcode_interp_offset ||
1051 sel->info.uses_persp_opcode_interp_sample)
1052 sel->info.uses_persp_center = true;
1053
1054 if (sel->info.uses_linear_opcode_interp_offset ||
1055 sel->info.uses_linear_opcode_interp_sample)
1056 sel->info.uses_linear_center = true;
1057
1058 switch (sel->type) {
1059 case PIPE_SHADER_GEOMETRY:
1060 sel->gs_output_prim =
1061 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
1062 sel->gs_max_out_vertices =
1063 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
1064 sel->gs_num_invocations =
1065 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
1066 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
1067 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
1068 sel->gs_max_out_vertices;
1069
1070 sel->max_gs_stream = 0;
1071 for (i = 0; i < sel->so.num_outputs; i++)
1072 sel->max_gs_stream = MAX2(sel->max_gs_stream,
1073 sel->so.output[i].stream);
1074
1075 sel->gs_input_verts_per_prim =
1076 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
1077 break;
1078
1079 case PIPE_SHADER_VERTEX:
1080 case PIPE_SHADER_TESS_CTRL:
1081 case PIPE_SHADER_TESS_EVAL:
1082 for (i = 0; i < sel->info.num_outputs; i++) {
1083 unsigned name = sel->info.output_semantic_name[i];
1084 unsigned index = sel->info.output_semantic_index[i];
1085
1086 switch (name) {
1087 case TGSI_SEMANTIC_TESSINNER:
1088 case TGSI_SEMANTIC_TESSOUTER:
1089 case TGSI_SEMANTIC_PATCH:
1090 sel->patch_outputs_written |=
1091 1llu << si_shader_io_get_unique_index(name, index);
1092 break;
1093 default:
1094 sel->outputs_written |=
1095 1llu << si_shader_io_get_unique_index(name, index);
1096 }
1097 }
1098 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
1099 break;
1100
1101 case PIPE_SHADER_FRAGMENT:
1102 for (i = 0; i < 8; i++)
1103 if (sel->info.colors_written & (1 << i))
1104 sel->colors_written_4bit |= 0xf << (4 * i);
1105
1106 for (i = 0; i < sel->info.num_inputs; i++) {
1107 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
1108 int index = sel->info.input_semantic_index[i];
1109 sel->color_attr_index[index] = i;
1110 }
1111 }
1112 break;
1113 }
1114
1115 /* DB_SHADER_CONTROL */
1116 sel->db_shader_control =
1117 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
1118 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
1119 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
1120 S_02880C_KILL_ENABLE(sel->info.uses_kill);
1121
1122 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
1123 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1124 sel->db_shader_control |=
1125 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
1126 break;
1127 case TGSI_FS_DEPTH_LAYOUT_LESS:
1128 sel->db_shader_control |=
1129 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
1130 break;
1131 }
1132
1133 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL])
1134 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1);
1135
1136 if (sel->info.writes_memory)
1137 sel->db_shader_control |= S_02880C_EXEC_ON_HIER_FAIL(1) |
1138 S_02880C_EXEC_ON_NOOP(1);
1139
1140 /* Compile the main shader part for use with a prolog and/or epilog. */
1141 if (sel->type != PIPE_SHADER_GEOMETRY &&
1142 !sscreen->use_monolithic_shaders) {
1143 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1144 void *tgsi_binary;
1145
1146 if (!shader)
1147 goto error;
1148
1149 shader->selector = sel;
1150 si_parse_next_shader_property(&sel->info, &shader->key);
1151
1152 tgsi_binary = si_get_tgsi_binary(sel);
1153
1154 /* Try to load the shader from the shader cache. */
1155 pipe_mutex_lock(sscreen->shader_cache_mutex);
1156
1157 if (tgsi_binary &&
1158 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1159 FREE(tgsi_binary);
1160 } else {
1161 /* Compile the shader if it hasn't been loaded from the cache. */
1162 if (si_compile_tgsi_shader(sscreen, sctx->tm, shader, false,
1163 &sctx->b.debug) != 0) {
1164 FREE(shader);
1165 FREE(tgsi_binary);
1166 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1167 goto error;
1168 }
1169
1170 if (tgsi_binary &&
1171 !si_shader_cache_insert_shader(sscreen, tgsi_binary, shader))
1172 FREE(tgsi_binary);
1173 }
1174 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1175
1176 sel->main_shader_part = shader;
1177 }
1178
1179 /* Pre-compilation. */
1180 if (sel->type == PIPE_SHADER_GEOMETRY ||
1181 sscreen->b.debug_flags & DBG_PRECOMPILE) {
1182 struct si_shader_ctx_state state = {sel};
1183 union si_shader_key key;
1184
1185 memset(&key, 0, sizeof(key));
1186 si_parse_next_shader_property(&sel->info, &key);
1187
1188 /* Set reasonable defaults, so that the shader key doesn't
1189 * cause any code to be eliminated.
1190 */
1191 switch (sel->type) {
1192 case PIPE_SHADER_TESS_CTRL:
1193 key.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1194 break;
1195 case PIPE_SHADER_FRAGMENT:
1196 key.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1197 for (i = 0; i < 8; i++)
1198 if (sel->info.colors_written & (1 << i))
1199 key.ps.epilog.spi_shader_col_format |=
1200 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1201 break;
1202 }
1203
1204 if (si_shader_select_with_key(ctx, &state, &key))
1205 goto error;
1206 }
1207
1208 pipe_mutex_init(sel->mutex);
1209 return sel;
1210
1211 error:
1212 fprintf(stderr, "radeonsi: can't create a shader\n");
1213 tgsi_free_tokens(sel->tokens);
1214 FREE(sel);
1215 return NULL;
1216 }
1217
1218 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1219 {
1220 struct si_context *sctx = (struct si_context *)ctx;
1221 struct si_shader_selector *sel = state;
1222
1223 if (sctx->vs_shader.cso == sel)
1224 return;
1225
1226 sctx->vs_shader.cso = sel;
1227 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
1228 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1229 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1230 }
1231
1232 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
1233 {
1234 struct si_context *sctx = (struct si_context *)ctx;
1235 struct si_shader_selector *sel = state;
1236 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
1237
1238 if (sctx->gs_shader.cso == sel)
1239 return;
1240
1241 sctx->gs_shader.cso = sel;
1242 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
1243 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1244 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1245
1246 if (enable_changed)
1247 si_shader_change_notify(sctx);
1248 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1249 }
1250
1251 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
1252 {
1253 struct si_context *sctx = (struct si_context *)ctx;
1254 struct si_shader_selector *sel = state;
1255 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
1256
1257 if (sctx->tcs_shader.cso == sel)
1258 return;
1259
1260 sctx->tcs_shader.cso = sel;
1261 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
1262
1263 if (enable_changed)
1264 sctx->last_tcs = NULL; /* invalidate derived tess state */
1265 }
1266
1267 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
1268 {
1269 struct si_context *sctx = (struct si_context *)ctx;
1270 struct si_shader_selector *sel = state;
1271 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
1272
1273 if (sctx->tes_shader.cso == sel)
1274 return;
1275
1276 sctx->tes_shader.cso = sel;
1277 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
1278 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1279 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1280
1281 if (enable_changed) {
1282 si_shader_change_notify(sctx);
1283 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
1284 }
1285 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1286 }
1287
1288 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1289 {
1290 struct si_context *sctx = (struct si_context *)ctx;
1291 struct si_shader_selector *sel = state;
1292
1293 /* skip if supplied shader is one already in use */
1294 if (sctx->ps_shader.cso == sel)
1295 return;
1296
1297 sctx->ps_shader.cso = sel;
1298 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
1299 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
1300 }
1301
1302 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
1303 {
1304 if (shader->pm4) {
1305 switch (shader->selector->type) {
1306 case PIPE_SHADER_VERTEX:
1307 if (shader->key.vs.as_ls)
1308 si_pm4_delete_state(sctx, ls, shader->pm4);
1309 else if (shader->key.vs.as_es)
1310 si_pm4_delete_state(sctx, es, shader->pm4);
1311 else
1312 si_pm4_delete_state(sctx, vs, shader->pm4);
1313 break;
1314 case PIPE_SHADER_TESS_CTRL:
1315 si_pm4_delete_state(sctx, hs, shader->pm4);
1316 break;
1317 case PIPE_SHADER_TESS_EVAL:
1318 if (shader->key.tes.as_es)
1319 si_pm4_delete_state(sctx, es, shader->pm4);
1320 else
1321 si_pm4_delete_state(sctx, vs, shader->pm4);
1322 break;
1323 case PIPE_SHADER_GEOMETRY:
1324 si_pm4_delete_state(sctx, gs, shader->pm4);
1325 si_pm4_delete_state(sctx, vs, shader->gs_copy_shader->pm4);
1326 break;
1327 case PIPE_SHADER_FRAGMENT:
1328 si_pm4_delete_state(sctx, ps, shader->pm4);
1329 break;
1330 }
1331 }
1332
1333 si_shader_destroy(shader);
1334 free(shader);
1335 }
1336
1337 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
1338 {
1339 struct si_context *sctx = (struct si_context *)ctx;
1340 struct si_shader_selector *sel = (struct si_shader_selector *)state;
1341 struct si_shader *p = sel->first_variant, *c;
1342 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
1343 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
1344 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
1345 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
1346 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
1347 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
1348 };
1349
1350 if (current_shader[sel->type]->cso == sel) {
1351 current_shader[sel->type]->cso = NULL;
1352 current_shader[sel->type]->current = NULL;
1353 }
1354
1355 while (p) {
1356 c = p->next_variant;
1357 si_delete_shader(sctx, p);
1358 p = c;
1359 }
1360
1361 if (sel->main_shader_part)
1362 si_delete_shader(sctx, sel->main_shader_part);
1363
1364 pipe_mutex_destroy(sel->mutex);
1365 free(sel->tokens);
1366 free(sel);
1367 }
1368
1369 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
1370 struct si_shader *vs, unsigned name,
1371 unsigned index, unsigned interpolate)
1372 {
1373 struct tgsi_shader_info *vsinfo = &vs->selector->info;
1374 unsigned j, ps_input_cntl = 0;
1375
1376 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
1377 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
1378 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1379
1380 if (name == TGSI_SEMANTIC_PCOORD ||
1381 (name == TGSI_SEMANTIC_TEXCOORD &&
1382 sctx->sprite_coord_enable & (1 << index))) {
1383 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
1384 }
1385
1386 for (j = 0; j < vsinfo->num_outputs; j++) {
1387 if (name == vsinfo->output_semantic_name[j] &&
1388 index == vsinfo->output_semantic_index[j]) {
1389 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[j]);
1390 break;
1391 }
1392 }
1393
1394 if (name == TGSI_SEMANTIC_PRIMID)
1395 /* PrimID is written after the last output. */
1396 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
1397 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
1398 /* No corresponding output found, load defaults into input.
1399 * Don't set any other bits.
1400 * (FLAT_SHADE=1 completely changes behavior) */
1401 ps_input_cntl = S_028644_OFFSET(0x20);
1402 }
1403 return ps_input_cntl;
1404 }
1405
1406 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
1407 {
1408 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1409 struct si_shader *ps = sctx->ps_shader.current;
1410 struct si_shader *vs = si_get_vs_state(sctx);
1411 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
1412 unsigned i, num_interp, num_written = 0, bcol_interp[2];
1413
1414 if (!ps || !ps->selector->info.num_inputs)
1415 return;
1416
1417 num_interp = si_get_ps_num_interp(ps);
1418 assert(num_interp > 0);
1419 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
1420
1421 for (i = 0; i < psinfo->num_inputs; i++) {
1422 unsigned name = psinfo->input_semantic_name[i];
1423 unsigned index = psinfo->input_semantic_index[i];
1424 unsigned interpolate = psinfo->input_interpolate[i];
1425
1426 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
1427 interpolate));
1428 num_written++;
1429
1430 if (name == TGSI_SEMANTIC_COLOR) {
1431 assert(index < ARRAY_SIZE(bcol_interp));
1432 bcol_interp[index] = interpolate;
1433 }
1434 }
1435
1436 if (ps->key.ps.prolog.color_two_side) {
1437 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
1438
1439 for (i = 0; i < 2; i++) {
1440 if (!(psinfo->colors_read & (0xf << (i * 4))))
1441 continue;
1442
1443 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
1444 i, bcol_interp[i]));
1445 num_written++;
1446 }
1447 }
1448 assert(num_interp == num_written);
1449 }
1450
1451 /**
1452 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1453 */
1454 static void si_init_config_add_vgt_flush(struct si_context *sctx)
1455 {
1456 if (sctx->init_config_has_vgt_flush)
1457 return;
1458
1459 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
1460 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
1461 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1462 si_pm4_cmd_end(sctx->init_config, false);
1463 sctx->init_config_has_vgt_flush = true;
1464 }
1465
1466 /* Initialize state related to ESGS / GSVS ring buffers */
1467 static bool si_update_gs_ring_buffers(struct si_context *sctx)
1468 {
1469 struct si_shader_selector *es =
1470 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
1471 struct si_shader_selector *gs = sctx->gs_shader.cso;
1472 struct si_pm4_state *pm4;
1473
1474 /* Chip constants. */
1475 unsigned num_se = sctx->screen->b.info.max_se;
1476 unsigned wave_size = 64;
1477 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1478 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1479 unsigned alignment = 256 * num_se;
1480 /* The maximum size is 63.999 MB per SE. */
1481 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1482
1483 /* Calculate the minimum size. */
1484 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
1485 wave_size, alignment);
1486
1487 /* These are recommended sizes, not minimum sizes. */
1488 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1489 es->esgs_itemsize * gs->gs_input_verts_per_prim;
1490 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1491 gs->max_gsvs_emit_size * (gs->max_gs_stream + 1);
1492
1493 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1494 esgs_ring_size = align(esgs_ring_size, alignment);
1495 gsvs_ring_size = align(gsvs_ring_size, alignment);
1496
1497 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1498 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1499
1500 /* Some rings don't have to be allocated if shaders don't use them.
1501 * (e.g. no varyings between ES and GS or GS and VS)
1502 */
1503 bool update_esgs = esgs_ring_size &&
1504 (!sctx->esgs_ring ||
1505 sctx->esgs_ring->width0 < esgs_ring_size);
1506 bool update_gsvs = gsvs_ring_size &&
1507 (!sctx->gsvs_ring ||
1508 sctx->gsvs_ring->width0 < gsvs_ring_size);
1509
1510 if (!update_esgs && !update_gsvs)
1511 return true;
1512
1513 if (update_esgs) {
1514 pipe_resource_reference(&sctx->esgs_ring, NULL);
1515 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1516 PIPE_USAGE_DEFAULT,
1517 esgs_ring_size);
1518 if (!sctx->esgs_ring)
1519 return false;
1520 }
1521
1522 if (update_gsvs) {
1523 pipe_resource_reference(&sctx->gsvs_ring, NULL);
1524 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1525 PIPE_USAGE_DEFAULT,
1526 gsvs_ring_size);
1527 if (!sctx->gsvs_ring)
1528 return false;
1529 }
1530
1531 /* Create the "init_config_gs_rings" state. */
1532 pm4 = CALLOC_STRUCT(si_pm4_state);
1533 if (!pm4)
1534 return false;
1535
1536 if (sctx->b.chip_class >= CIK) {
1537 if (sctx->esgs_ring)
1538 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
1539 sctx->esgs_ring->width0 / 256);
1540 if (sctx->gsvs_ring)
1541 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
1542 sctx->gsvs_ring->width0 / 256);
1543 } else {
1544 if (sctx->esgs_ring)
1545 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
1546 sctx->esgs_ring->width0 / 256);
1547 if (sctx->gsvs_ring)
1548 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
1549 sctx->gsvs_ring->width0 / 256);
1550 }
1551
1552 /* Set the state. */
1553 if (sctx->init_config_gs_rings)
1554 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
1555 sctx->init_config_gs_rings = pm4;
1556
1557 if (!sctx->init_config_has_vgt_flush) {
1558 si_init_config_add_vgt_flush(sctx);
1559 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1560 }
1561
1562 /* Flush the context to re-emit both init_config states. */
1563 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1564 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1565
1566 /* Set ring bindings. */
1567 if (sctx->esgs_ring) {
1568 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
1569 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1570 true, true, 4, 64, 0);
1571 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
1572 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1573 false, false, 0, 0, 0);
1574 }
1575 if (sctx->gsvs_ring)
1576 si_set_ring_buffer(&sctx->b.b, SI_VS_RING_GSVS,
1577 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
1578 false, false, 0, 0, 0);
1579 return true;
1580 }
1581
1582 static void si_update_gsvs_ring_bindings(struct si_context *sctx)
1583 {
1584 unsigned gsvs_itemsize = sctx->gs_shader.cso->max_gsvs_emit_size;
1585 uint64_t offset;
1586
1587 if (!sctx->gsvs_ring || gsvs_itemsize == sctx->last_gsvs_itemsize)
1588 return;
1589
1590 sctx->last_gsvs_itemsize = gsvs_itemsize;
1591
1592 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS0,
1593 sctx->gsvs_ring, gsvs_itemsize,
1594 64, true, true, 4, 16, 0);
1595
1596 offset = gsvs_itemsize * 64;
1597 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS1,
1598 sctx->gsvs_ring, gsvs_itemsize,
1599 64, true, true, 4, 16, offset);
1600
1601 offset = (gsvs_itemsize * 2) * 64;
1602 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS2,
1603 sctx->gsvs_ring, gsvs_itemsize,
1604 64, true, true, 4, 16, offset);
1605
1606 offset = (gsvs_itemsize * 3) * 64;
1607 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS3,
1608 sctx->gsvs_ring, gsvs_itemsize,
1609 64, true, true, 4, 16, offset);
1610 }
1611
1612 /**
1613 * @returns 1 if \p sel has been updated to use a new scratch buffer
1614 * 0 if not
1615 * < 0 if there was a failure
1616 */
1617 static int si_update_scratch_buffer(struct si_context *sctx,
1618 struct si_shader *shader)
1619 {
1620 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
1621 int r;
1622
1623 if (!shader)
1624 return 0;
1625
1626 /* This shader doesn't need a scratch buffer */
1627 if (shader->config.scratch_bytes_per_wave == 0)
1628 return 0;
1629
1630 /* This shader is already configured to use the current
1631 * scratch buffer. */
1632 if (shader->scratch_bo == sctx->scratch_buffer)
1633 return 0;
1634
1635 assert(sctx->scratch_buffer);
1636
1637 si_shader_apply_scratch_relocs(sctx, shader, &shader->config, scratch_va);
1638
1639 /* Replace the shader bo with a new bo that has the relocs applied. */
1640 r = si_shader_binary_upload(sctx->screen, shader);
1641 if (r)
1642 return r;
1643
1644 /* Update the shader state to use the new shader bo. */
1645 si_shader_init_pm4_state(shader);
1646
1647 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
1648
1649 return 1;
1650 }
1651
1652 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
1653 {
1654 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
1655 }
1656
1657 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
1658 {
1659 return shader ? shader->config.scratch_bytes_per_wave : 0;
1660 }
1661
1662 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
1663 {
1664 unsigned bytes = 0;
1665
1666 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
1667 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
1668 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
1669 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
1670 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
1671 return bytes;
1672 }
1673
1674 static bool si_update_spi_tmpring_size(struct si_context *sctx)
1675 {
1676 unsigned current_scratch_buffer_size =
1677 si_get_current_scratch_buffer_size(sctx);
1678 unsigned scratch_bytes_per_wave =
1679 si_get_max_scratch_bytes_per_wave(sctx);
1680 unsigned scratch_needed_size = scratch_bytes_per_wave *
1681 sctx->scratch_waves;
1682 unsigned spi_tmpring_size;
1683 int r;
1684
1685 if (scratch_needed_size > 0) {
1686 if (scratch_needed_size > current_scratch_buffer_size) {
1687 /* Create a bigger scratch buffer */
1688 pipe_resource_reference(
1689 (struct pipe_resource**)&sctx->scratch_buffer,
1690 NULL);
1691
1692 sctx->scratch_buffer =
1693 si_resource_create_custom(&sctx->screen->b.b,
1694 PIPE_USAGE_DEFAULT, scratch_needed_size);
1695 if (!sctx->scratch_buffer)
1696 return false;
1697 sctx->emit_scratch_reloc = true;
1698 }
1699
1700 /* Update the shaders, so they are using the latest scratch. The
1701 * scratch buffer may have been changed since these shaders were
1702 * last used, so we still need to try to update them, even if
1703 * they require scratch buffers smaller than the current size.
1704 */
1705 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
1706 if (r < 0)
1707 return false;
1708 if (r == 1)
1709 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1710
1711 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
1712 if (r < 0)
1713 return false;
1714 if (r == 1)
1715 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1716
1717 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
1718 if (r < 0)
1719 return false;
1720 if (r == 1)
1721 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1722
1723 /* VS can be bound as LS, ES, or VS. */
1724 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
1725 if (r < 0)
1726 return false;
1727 if (r == 1) {
1728 if (sctx->tes_shader.current)
1729 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1730 else if (sctx->gs_shader.current)
1731 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1732 else
1733 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1734 }
1735
1736 /* TES can be bound as ES or VS. */
1737 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
1738 if (r < 0)
1739 return false;
1740 if (r == 1) {
1741 if (sctx->gs_shader.current)
1742 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1743 else
1744 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1745 }
1746 }
1747
1748 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1749 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
1750 "scratch size should already be aligned correctly.");
1751
1752 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
1753 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
1754 if (spi_tmpring_size != sctx->spi_tmpring_size) {
1755 sctx->spi_tmpring_size = spi_tmpring_size;
1756 sctx->emit_scratch_reloc = true;
1757 }
1758 return true;
1759 }
1760
1761 static void si_init_tess_factor_ring(struct si_context *sctx)
1762 {
1763 assert(!sctx->tf_ring);
1764
1765 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1766 PIPE_USAGE_DEFAULT,
1767 32768 * sctx->screen->b.info.max_se);
1768 if (!sctx->tf_ring)
1769 return;
1770
1771 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
1772
1773 si_init_config_add_vgt_flush(sctx);
1774
1775 /* Append these registers to the init config state. */
1776 if (sctx->b.chip_class >= CIK) {
1777 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
1778 S_030938_SIZE(sctx->tf_ring->width0 / 4));
1779 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
1780 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1781 } else {
1782 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
1783 S_008988_SIZE(sctx->tf_ring->width0 / 4));
1784 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
1785 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1786 }
1787
1788 /* Flush the context to re-emit the init_config state.
1789 * This is done only once in a lifetime of a context.
1790 */
1791 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1792 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1793 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1794
1795 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_FACTOR, sctx->tf_ring,
1796 0, sctx->tf_ring->width0, false, false, 0, 0, 0);
1797 }
1798
1799 /**
1800 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
1801 * VS passes its outputs to TES directly, so the fixed-function shader only
1802 * has to write TESSOUTER and TESSINNER.
1803 */
1804 static void si_generate_fixed_func_tcs(struct si_context *sctx)
1805 {
1806 struct ureg_src outer, inner;
1807 struct ureg_dst tessouter, tessinner;
1808 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
1809
1810 if (!ureg)
1811 return; /* if we get here, we're screwed */
1812
1813 assert(!sctx->fixed_func_tcs_shader.cso);
1814
1815 outer = ureg_DECL_system_value(ureg,
1816 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
1817 inner = ureg_DECL_system_value(ureg,
1818 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
1819
1820 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1821 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1822
1823 ureg_MOV(ureg, tessouter, outer);
1824 ureg_MOV(ureg, tessinner, inner);
1825 ureg_END(ureg);
1826
1827 sctx->fixed_func_tcs_shader.cso =
1828 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
1829 }
1830
1831 static void si_update_vgt_shader_config(struct si_context *sctx)
1832 {
1833 /* Calculate the index of the config.
1834 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
1835 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
1836 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
1837
1838 if (!*pm4) {
1839 uint32_t stages = 0;
1840
1841 *pm4 = CALLOC_STRUCT(si_pm4_state);
1842
1843 if (sctx->tes_shader.cso) {
1844 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1845 S_028B54_HS_EN(1);
1846
1847 if (sctx->gs_shader.cso)
1848 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1849 S_028B54_GS_EN(1) |
1850 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1851 else
1852 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1853 } else if (sctx->gs_shader.cso) {
1854 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1855 S_028B54_GS_EN(1) |
1856 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1857 }
1858
1859 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
1860 }
1861 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
1862 }
1863
1864 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
1865 {
1866 struct pipe_stream_output_info *so = &shader->so;
1867 uint32_t enabled_stream_buffers_mask = 0;
1868 int i;
1869
1870 for (i = 0; i < so->num_outputs; i++)
1871 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
1872 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
1873 sctx->b.streamout.stride_in_dw = shader->so.stride;
1874 }
1875
1876 bool si_update_shaders(struct si_context *sctx)
1877 {
1878 struct pipe_context *ctx = (struct pipe_context*)sctx;
1879 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1880 int r;
1881
1882 /* Update stages before GS. */
1883 if (sctx->tes_shader.cso) {
1884 if (!sctx->tf_ring) {
1885 si_init_tess_factor_ring(sctx);
1886 if (!sctx->tf_ring)
1887 return false;
1888 }
1889
1890 /* VS as LS */
1891 r = si_shader_select(ctx, &sctx->vs_shader);
1892 if (r)
1893 return false;
1894 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1895
1896 if (sctx->tcs_shader.cso) {
1897 r = si_shader_select(ctx, &sctx->tcs_shader);
1898 if (r)
1899 return false;
1900 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1901 } else {
1902 if (!sctx->fixed_func_tcs_shader.cso) {
1903 si_generate_fixed_func_tcs(sctx);
1904 if (!sctx->fixed_func_tcs_shader.cso)
1905 return false;
1906 }
1907
1908 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader);
1909 if (r)
1910 return false;
1911 si_pm4_bind_state(sctx, hs,
1912 sctx->fixed_func_tcs_shader.current->pm4);
1913 }
1914
1915 r = si_shader_select(ctx, &sctx->tes_shader);
1916 if (r)
1917 return false;
1918
1919 if (sctx->gs_shader.cso) {
1920 /* TES as ES */
1921 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1922 } else {
1923 /* TES as VS */
1924 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1925 si_update_so(sctx, sctx->tes_shader.cso);
1926 }
1927 } else if (sctx->gs_shader.cso) {
1928 /* VS as ES */
1929 r = si_shader_select(ctx, &sctx->vs_shader);
1930 if (r)
1931 return false;
1932 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1933 } else {
1934 /* VS as VS */
1935 r = si_shader_select(ctx, &sctx->vs_shader);
1936 if (r)
1937 return false;
1938 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1939 si_update_so(sctx, sctx->vs_shader.cso);
1940 }
1941
1942 /* Update GS. */
1943 if (sctx->gs_shader.cso) {
1944 r = si_shader_select(ctx, &sctx->gs_shader);
1945 if (r)
1946 return false;
1947 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1948 si_pm4_bind_state(sctx, vs, sctx->gs_shader.current->gs_copy_shader->pm4);
1949 si_update_so(sctx, sctx->gs_shader.cso);
1950
1951 if (!si_update_gs_ring_buffers(sctx))
1952 return false;
1953
1954 si_update_gsvs_ring_bindings(sctx);
1955 } else {
1956 si_pm4_bind_state(sctx, gs, NULL);
1957 si_pm4_bind_state(sctx, es, NULL);
1958 }
1959
1960 si_update_vgt_shader_config(sctx);
1961
1962 if (sctx->ps_shader.cso) {
1963 unsigned db_shader_control;
1964
1965 r = si_shader_select(ctx, &sctx->ps_shader);
1966 if (r)
1967 return false;
1968 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1969
1970 db_shader_control =
1971 sctx->ps_shader.cso->db_shader_control |
1972 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS) |
1973 S_02880C_Z_ORDER(sctx->ps_shader.current->z_order);
1974
1975 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
1976 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
1977 sctx->flatshade != rs->flatshade) {
1978 sctx->sprite_coord_enable = rs->sprite_coord_enable;
1979 sctx->flatshade = rs->flatshade;
1980 si_mark_atom_dirty(sctx, &sctx->spi_map);
1981 }
1982
1983 if (sctx->b.family == CHIP_STONEY && si_pm4_state_changed(sctx, ps))
1984 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
1985
1986 if (sctx->ps_db_shader_control != db_shader_control) {
1987 sctx->ps_db_shader_control = db_shader_control;
1988 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1989 }
1990
1991 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.ps.epilog.poly_line_smoothing) {
1992 sctx->smoothing_enabled = sctx->ps_shader.current->key.ps.epilog.poly_line_smoothing;
1993 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1994
1995 if (sctx->b.chip_class == SI)
1996 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1997 }
1998 }
1999
2000 if (si_pm4_state_changed(sctx, ls) ||
2001 si_pm4_state_changed(sctx, hs) ||
2002 si_pm4_state_changed(sctx, es) ||
2003 si_pm4_state_changed(sctx, gs) ||
2004 si_pm4_state_changed(sctx, vs) ||
2005 si_pm4_state_changed(sctx, ps)) {
2006 if (!si_update_spi_tmpring_size(sctx))
2007 return false;
2008 }
2009 return true;
2010 }
2011
2012 void si_init_shader_functions(struct si_context *sctx)
2013 {
2014 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
2015
2016 sctx->b.b.create_vs_state = si_create_shader_selector;
2017 sctx->b.b.create_tcs_state = si_create_shader_selector;
2018 sctx->b.b.create_tes_state = si_create_shader_selector;
2019 sctx->b.b.create_gs_state = si_create_shader_selector;
2020 sctx->b.b.create_fs_state = si_create_shader_selector;
2021
2022 sctx->b.b.bind_vs_state = si_bind_vs_shader;
2023 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
2024 sctx->b.b.bind_tes_state = si_bind_tes_shader;
2025 sctx->b.b.bind_gs_state = si_bind_gs_shader;
2026 sctx->b.b.bind_fs_state = si_bind_ps_shader;
2027
2028 sctx->b.b.delete_vs_state = si_delete_shader_selector;
2029 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
2030 sctx->b.b.delete_tes_state = si_delete_shader_selector;
2031 sctx->b.b.delete_gs_state = si_delete_shader_selector;
2032 sctx->b.b.delete_fs_state = si_delete_shader_selector;
2033 }