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radeonsi:optimizing SET_CONTEXT_REG for shaders Tessellation
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
45 * size as integer.
46 */
47 void *si_get_ir_binary(struct si_shader_selector *sel)
48 {
49 struct blob blob;
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->tokens) {
54 ir_binary = sel->tokens;
55 ir_size = tgsi_num_tokens(sel->tokens) *
56 sizeof(struct tgsi_token);
57 } else {
58 assert(sel->nir);
59
60 blob_init(&blob);
61 nir_serialize(&blob, sel->nir);
62 ir_binary = blob.data;
63 ir_size = blob.size;
64 }
65
66 unsigned size = 4 + ir_size + sizeof(sel->so);
67 char *result = (char*)MALLOC(size);
68 if (!result)
69 return NULL;
70
71 *((uint32_t*)result) = size;
72 memcpy(result + 4, ir_binary, ir_size);
73 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
74
75 if (sel->nir)
76 blob_finish(&blob);
77
78 return result;
79 }
80
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
83 {
84 /* data may be NULL if size == 0 */
85 if (size)
86 memcpy(ptr, data, size);
87 ptr += DIV_ROUND_UP(size, 4);
88 return ptr;
89 }
90
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
93 {
94 memcpy(data, ptr, size);
95 ptr += DIV_ROUND_UP(size, 4);
96 return ptr;
97 }
98
99 /**
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
102 */
103 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
104 {
105 *ptr++ = size;
106 return write_data(ptr, data, size);
107 }
108
109 /**
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
112 */
113 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
114 {
115 *size = *ptr++;
116 assert(*data == NULL);
117 if (!*size)
118 return ptr;
119 *data = malloc(*size);
120 return read_data(ptr, *data, *size);
121 }
122
123 /**
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
125 * as integer.
126 */
127 static void *si_get_shader_binary(struct si_shader *shader)
128 {
129 /* There is always a size of data followed by the data itself. */
130 unsigned relocs_size = shader->binary.reloc_count *
131 sizeof(shader->binary.relocs[0]);
132 unsigned disasm_size = shader->binary.disasm_string ?
133 strlen(shader->binary.disasm_string) + 1 : 0;
134 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
135 strlen(shader->binary.llvm_ir_string) + 1 : 0;
136 unsigned size =
137 4 + /* total size */
138 4 + /* CRC32 of the data below */
139 align(sizeof(shader->config), 4) +
140 align(sizeof(shader->info), 4) +
141 4 + align(shader->binary.code_size, 4) +
142 4 + align(shader->binary.rodata_size, 4) +
143 4 + align(relocs_size, 4) +
144 4 + align(disasm_size, 4) +
145 4 + align(llvm_ir_size, 4);
146 void *buffer = CALLOC(1, size);
147 uint32_t *ptr = (uint32_t*)buffer;
148
149 if (!buffer)
150 return NULL;
151
152 *ptr++ = size;
153 ptr++; /* CRC32 is calculated at the end. */
154
155 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
156 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
157 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
158 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
159 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
160 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
161 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
162 assert((char *)ptr - (char *)buffer == size);
163
164 /* Compute CRC32. */
165 ptr = (uint32_t*)buffer;
166 ptr++;
167 *ptr = util_hash_crc32(ptr + 1, size - 8);
168
169 return buffer;
170 }
171
172 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
173 {
174 uint32_t *ptr = (uint32_t*)binary;
175 uint32_t size = *ptr++;
176 uint32_t crc32 = *ptr++;
177 unsigned chunk_size;
178
179 if (util_hash_crc32(ptr, size - 8) != crc32) {
180 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
181 return false;
182 }
183
184 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
185 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
186 ptr = read_chunk(ptr, (void**)&shader->binary.code,
187 &shader->binary.code_size);
188 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
189 &shader->binary.rodata_size);
190 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
191 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
192 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
193 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
194
195 return true;
196 }
197
198 /**
199 * Insert a shader into the cache. It's assumed the shader is not in the cache.
200 * Use si_shader_cache_load_shader before calling this.
201 *
202 * Returns false on failure, in which case the ir_binary should be freed.
203 */
204 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
205 struct si_shader *shader,
206 bool insert_into_disk_cache)
207 {
208 void *hw_binary;
209 struct hash_entry *entry;
210 uint8_t key[CACHE_KEY_SIZE];
211
212 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
213 if (entry)
214 return false; /* already added */
215
216 hw_binary = si_get_shader_binary(shader);
217 if (!hw_binary)
218 return false;
219
220 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
221 hw_binary) == NULL) {
222 FREE(hw_binary);
223 return false;
224 }
225
226 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
227 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
228 *((uint32_t *)ir_binary), key);
229 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
230 *((uint32_t *) hw_binary), NULL);
231 }
232
233 return true;
234 }
235
236 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
237 struct si_shader *shader)
238 {
239 struct hash_entry *entry =
240 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
241 if (!entry) {
242 if (sscreen->disk_shader_cache) {
243 unsigned char sha1[CACHE_KEY_SIZE];
244 size_t tg_size = *((uint32_t *) ir_binary);
245
246 disk_cache_compute_key(sscreen->disk_shader_cache,
247 ir_binary, tg_size, sha1);
248
249 size_t binary_size;
250 uint8_t *buffer =
251 disk_cache_get(sscreen->disk_shader_cache,
252 sha1, &binary_size);
253 if (!buffer)
254 return false;
255
256 if (binary_size < sizeof(uint32_t) ||
257 *((uint32_t*)buffer) != binary_size) {
258 /* Something has gone wrong discard the item
259 * from the cache and rebuild/link from
260 * source.
261 */
262 assert(!"Invalid radeonsi shader disk cache "
263 "item!");
264
265 disk_cache_remove(sscreen->disk_shader_cache,
266 sha1);
267 free(buffer);
268
269 return false;
270 }
271
272 if (!si_load_shader_binary(shader, buffer)) {
273 free(buffer);
274 return false;
275 }
276 free(buffer);
277
278 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
279 shader, false))
280 FREE(ir_binary);
281 } else {
282 return false;
283 }
284 } else {
285 if (si_load_shader_binary(shader, entry->data))
286 FREE(ir_binary);
287 else
288 return false;
289 }
290 p_atomic_inc(&sscreen->num_shader_cache_hits);
291 return true;
292 }
293
294 static uint32_t si_shader_cache_key_hash(const void *key)
295 {
296 /* The first dword is the key size. */
297 return util_hash_crc32(key, *(uint32_t*)key);
298 }
299
300 static bool si_shader_cache_key_equals(const void *a, const void *b)
301 {
302 uint32_t *keya = (uint32_t*)a;
303 uint32_t *keyb = (uint32_t*)b;
304
305 /* The first dword is the key size. */
306 if (*keya != *keyb)
307 return false;
308
309 return memcmp(keya, keyb, *keya) == 0;
310 }
311
312 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
313 {
314 FREE((void*)entry->key);
315 FREE(entry->data);
316 }
317
318 bool si_init_shader_cache(struct si_screen *sscreen)
319 {
320 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
321 sscreen->shader_cache =
322 _mesa_hash_table_create(NULL,
323 si_shader_cache_key_hash,
324 si_shader_cache_key_equals);
325
326 return sscreen->shader_cache != NULL;
327 }
328
329 void si_destroy_shader_cache(struct si_screen *sscreen)
330 {
331 if (sscreen->shader_cache)
332 _mesa_hash_table_destroy(sscreen->shader_cache,
333 si_destroy_shader_cache_entry);
334 mtx_destroy(&sscreen->shader_cache_mutex);
335 }
336
337 /* SHADER STATES */
338
339 static void si_set_tesseval_regs(struct si_screen *sscreen,
340 struct si_shader_selector *tes,
341 struct si_pm4_state *pm4)
342 {
343 struct tgsi_shader_info *info = &tes->info;
344 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
345 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
346 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
347 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
348 unsigned type, partitioning, topology, distribution_mode;
349
350 switch (tes_prim_mode) {
351 case PIPE_PRIM_LINES:
352 type = V_028B6C_TESS_ISOLINE;
353 break;
354 case PIPE_PRIM_TRIANGLES:
355 type = V_028B6C_TESS_TRIANGLE;
356 break;
357 case PIPE_PRIM_QUADS:
358 type = V_028B6C_TESS_QUAD;
359 break;
360 default:
361 assert(0);
362 return;
363 }
364
365 switch (tes_spacing) {
366 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
367 partitioning = V_028B6C_PART_FRAC_ODD;
368 break;
369 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
370 partitioning = V_028B6C_PART_FRAC_EVEN;
371 break;
372 case PIPE_TESS_SPACING_EQUAL:
373 partitioning = V_028B6C_PART_INTEGER;
374 break;
375 default:
376 assert(0);
377 return;
378 }
379
380 if (tes_point_mode)
381 topology = V_028B6C_OUTPUT_POINT;
382 else if (tes_prim_mode == PIPE_PRIM_LINES)
383 topology = V_028B6C_OUTPUT_LINE;
384 else if (tes_vertex_order_cw)
385 /* for some reason, this must be the other way around */
386 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
387 else
388 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
389
390 if (sscreen->has_distributed_tess) {
391 if (sscreen->info.family == CHIP_FIJI ||
392 sscreen->info.family >= CHIP_POLARIS10)
393 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
394 else
395 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
396 } else
397 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
398
399 assert(pm4->shader);
400 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
401 S_028B6C_PARTITIONING(partitioning) |
402 S_028B6C_TOPOLOGY(topology) |
403 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
404 }
405
406 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
407 * whether the "fractional odd" tessellation spacing is used.
408 *
409 * Possible VGT configurations and which state should set the register:
410 *
411 * Reg set in | VGT shader configuration | Value
412 * ------------------------------------------------------
413 * VS as VS | VS | 30
414 * VS as ES | ES -> GS -> VS | 30
415 * TES as VS | LS -> HS -> VS | 14 or 30
416 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
417 *
418 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
419 */
420 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
421 struct si_shader_selector *sel,
422 struct si_shader *shader,
423 struct si_pm4_state *pm4)
424 {
425 unsigned type = sel->type;
426
427 if (sscreen->info.family < CHIP_POLARIS10)
428 return;
429
430 /* VS as VS, or VS as ES: */
431 if ((type == PIPE_SHADER_VERTEX &&
432 (!shader ||
433 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
434 /* TES as VS, or TES as ES: */
435 type == PIPE_SHADER_TESS_EVAL) {
436 unsigned vtx_reuse_depth = 30;
437
438 if (type == PIPE_SHADER_TESS_EVAL &&
439 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
440 PIPE_TESS_SPACING_FRACTIONAL_ODD)
441 vtx_reuse_depth = 14;
442
443 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
444 vtx_reuse_depth);
445 }
446 }
447
448 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
449 {
450 if (shader->pm4)
451 si_pm4_clear_state(shader->pm4);
452 else
453 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
454
455 if (shader->pm4) {
456 shader->pm4->shader = shader;
457 return shader->pm4;
458 } else {
459 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
460 return NULL;
461 }
462 }
463
464 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
465 {
466 /* Add the pointer to VBO descriptors. */
467 if (HAVE_32BIT_POINTERS) {
468 return num_always_on_user_sgprs + 1;
469 } else {
470 assert(num_always_on_user_sgprs % 2 == 0);
471 return num_always_on_user_sgprs + 2;
472 }
473 }
474
475 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
476 {
477 struct si_pm4_state *pm4;
478 unsigned vgpr_comp_cnt;
479 uint64_t va;
480
481 assert(sscreen->info.chip_class <= VI);
482
483 pm4 = si_get_shader_pm4_state(shader);
484 if (!pm4)
485 return;
486
487 va = shader->bo->gpu_address;
488 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
489
490 /* We need at least 2 components for LS.
491 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
492 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
493 */
494 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
495
496 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
497 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
498
499 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
500 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
501 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
502 S_00B528_DX10_CLAMP(1) |
503 S_00B528_FLOAT_MODE(shader->config.float_mode);
504 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
505 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
506 }
507
508 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
509 {
510 struct si_pm4_state *pm4;
511 uint64_t va;
512 unsigned ls_vgpr_comp_cnt = 0;
513
514 pm4 = si_get_shader_pm4_state(shader);
515 if (!pm4)
516 return;
517
518 va = shader->bo->gpu_address;
519 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
520
521 if (sscreen->info.chip_class >= GFX9) {
522 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
523 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
524
525 /* We need at least 2 components for LS.
526 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
527 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
528 */
529 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
530
531 unsigned num_user_sgprs =
532 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
533
534 shader->config.rsrc2 =
535 S_00B42C_USER_SGPR(num_user_sgprs) |
536 S_00B42C_USER_SGPR_MSB(num_user_sgprs >> 5) |
537 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
538 } else {
539 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
540 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
541
542 shader->config.rsrc2 =
543 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
544 S_00B42C_OC_LDS_EN(1) |
545 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
546 }
547
548 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
549 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
550 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
551 S_00B428_DX10_CLAMP(1) |
552 S_00B428_FLOAT_MODE(shader->config.float_mode) |
553 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
554
555 if (sscreen->info.chip_class <= VI) {
556 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
557 shader->config.rsrc2);
558 }
559 }
560
561 static void si_emit_shader_es(struct si_context *sctx)
562 {
563 struct si_shader *shader = sctx->queued.named.es->shader;
564
565 if (!shader)
566 return;
567
568 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
569 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
570 shader->selector->esgs_itemsize / 4);
571
572 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
573 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
574 SI_TRACKED_VGT_TF_PARAM,
575 shader->vgt_tf_param);
576
577 }
578
579 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
580 {
581 struct si_pm4_state *pm4;
582 unsigned num_user_sgprs;
583 unsigned vgpr_comp_cnt;
584 uint64_t va;
585 unsigned oc_lds_en;
586
587 assert(sscreen->info.chip_class <= VI);
588
589 pm4 = si_get_shader_pm4_state(shader);
590 if (!pm4)
591 return;
592
593 pm4->atom.emit = si_emit_shader_es;
594 va = shader->bo->gpu_address;
595 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
596
597 if (shader->selector->type == PIPE_SHADER_VERTEX) {
598 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
599 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
600 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
601 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
602 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
603 num_user_sgprs = SI_TES_NUM_USER_SGPR;
604 } else
605 unreachable("invalid shader selector type");
606
607 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
608
609 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
610 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
611 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
612 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
613 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
614 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
615 S_00B328_DX10_CLAMP(1) |
616 S_00B328_FLOAT_MODE(shader->config.float_mode));
617 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
618 S_00B32C_USER_SGPR(num_user_sgprs) |
619 S_00B32C_OC_LDS_EN(oc_lds_en) |
620 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
621
622 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
623 si_set_tesseval_regs(sscreen, shader->selector, pm4);
624
625 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
626 }
627
628 static unsigned si_conv_prim_to_gs_out(unsigned mode)
629 {
630 static const int prim_conv[] = {
631 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
632 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
633 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
634 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
635 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
636 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
637 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
638 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
639 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
640 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
641 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
642 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
643 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
644 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
645 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
646 };
647 assert(mode < ARRAY_SIZE(prim_conv));
648
649 return prim_conv[mode];
650 }
651
652 struct gfx9_gs_info {
653 unsigned es_verts_per_subgroup;
654 unsigned gs_prims_per_subgroup;
655 unsigned gs_inst_prims_in_subgroup;
656 unsigned max_prims_per_subgroup;
657 unsigned lds_size;
658 };
659
660 static void gfx9_get_gs_info(struct si_shader_selector *es,
661 struct si_shader_selector *gs,
662 struct gfx9_gs_info *out)
663 {
664 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
665 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
666 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
667 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
668
669 /* All these are in dwords: */
670 /* We can't allow using the whole LDS, because GS waves compete with
671 * other shader stages for LDS space. */
672 const unsigned max_lds_size = 8 * 1024;
673 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
674 unsigned esgs_lds_size;
675
676 /* All these are per subgroup: */
677 const unsigned max_out_prims = 32 * 1024;
678 const unsigned max_es_verts = 255;
679 const unsigned ideal_gs_prims = 64;
680 unsigned max_gs_prims, gs_prims;
681 unsigned min_es_verts, es_verts, worst_case_es_verts;
682
683 if (uses_adjacency || gs_num_invocations > 1)
684 max_gs_prims = 127 / gs_num_invocations;
685 else
686 max_gs_prims = 255;
687
688 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
689 * Make sure we don't go over the maximum value.
690 */
691 if (gs->gs_max_out_vertices > 0) {
692 max_gs_prims = MIN2(max_gs_prims,
693 max_out_prims /
694 (gs->gs_max_out_vertices * gs_num_invocations));
695 }
696 assert(max_gs_prims > 0);
697
698 /* If the primitive has adjacency, halve the number of vertices
699 * that will be reused in multiple primitives.
700 */
701 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
702
703 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
704 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
705
706 /* Compute ESGS LDS size based on the worst case number of ES vertices
707 * needed to create the target number of GS prims per subgroup.
708 */
709 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
710
711 /* If total LDS usage is too big, refactor partitions based on ratio
712 * of ESGS item sizes.
713 */
714 if (esgs_lds_size > max_lds_size) {
715 /* Our target GS Prims Per Subgroup was too large. Calculate
716 * the maximum number of GS Prims Per Subgroup that will fit
717 * into LDS, capped by the maximum that the hardware can support.
718 */
719 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
720 max_gs_prims);
721 assert(gs_prims > 0);
722 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
723 max_es_verts);
724
725 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
726 assert(esgs_lds_size <= max_lds_size);
727 }
728
729 /* Now calculate remaining ESGS information. */
730 if (esgs_lds_size)
731 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
732 else
733 es_verts = max_es_verts;
734
735 /* Vertices for adjacency primitives are not always reused, so restore
736 * it for ES_VERTS_PER_SUBGRP.
737 */
738 min_es_verts = gs->gs_input_verts_per_prim;
739
740 /* For normal primitives, the VGT only checks if they are past the ES
741 * verts per subgroup after allocating a full GS primitive and if they
742 * are, kick off a new subgroup. But if those additional ES verts are
743 * unique (e.g. not reused) we need to make sure there is enough LDS
744 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
745 */
746 es_verts -= min_es_verts - 1;
747
748 out->es_verts_per_subgroup = es_verts;
749 out->gs_prims_per_subgroup = gs_prims;
750 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
751 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
752 gs->gs_max_out_vertices;
753 out->lds_size = align(esgs_lds_size, 128) / 128;
754
755 assert(out->max_prims_per_subgroup <= max_out_prims);
756 }
757
758 static void si_emit_shader_gs(struct si_context *sctx)
759 {
760 struct si_shader *shader = sctx->queued.named.gs->shader;
761 if (!shader)
762 return;
763
764 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
765 * R_028A68_VGT_GSVS_RING_OFFSET_3, R_028A6C_VGT_GS_OUT_PRIM_TYPE */
766 radeon_opt_set_context_reg4(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
767 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
768 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
769 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
770 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3,
771 shader->ctx_reg.gs.vgt_gs_out_prim_type);
772
773
774 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
775 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
776 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
777 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
778
779 /* R_028B38_VGT_GS_MAX_VERT_OUT */
780 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
781 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
782 shader->ctx_reg.gs.vgt_gs_max_vert_out);
783
784 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
785 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
786 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
787 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
788 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
789 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
790 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
791 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
792
793 /* R_028B90_VGT_GS_INSTANCE_CNT */
794 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
795 SI_TRACKED_VGT_GS_INSTANCE_CNT,
796 shader->ctx_reg.gs.vgt_gs_instance_cnt);
797
798 if (sctx->chip_class >= GFX9) {
799 /* R_028A44_VGT_GS_ONCHIP_CNTL */
800 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
801 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
802 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
803 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
804 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
805 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
806 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
807 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
808 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
809 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
810 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
811
812 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
813 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
814 SI_TRACKED_VGT_TF_PARAM,
815 shader->vgt_tf_param);
816 }
817 }
818
819 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
820 {
821 struct si_shader_selector *sel = shader->selector;
822 const ubyte *num_components = sel->info.num_stream_output_components;
823 unsigned gs_num_invocations = sel->gs_num_invocations;
824 struct si_pm4_state *pm4;
825 uint64_t va;
826 unsigned max_stream = sel->max_gs_stream;
827 unsigned offset;
828
829 pm4 = si_get_shader_pm4_state(shader);
830 if (!pm4)
831 return;
832
833 pm4->atom.emit = si_emit_shader_gs;
834
835 offset = num_components[0] * sel->gs_max_out_vertices;
836 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
837
838 if (max_stream >= 1)
839 offset += num_components[1] * sel->gs_max_out_vertices;
840 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
841
842 if (max_stream >= 2)
843 offset += num_components[2] * sel->gs_max_out_vertices;
844 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
845
846 shader->ctx_reg.gs.vgt_gs_out_prim_type =
847 si_conv_prim_to_gs_out(sel->gs_output_prim);
848
849 if (max_stream >= 3)
850 offset += num_components[3] * sel->gs_max_out_vertices;
851 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
852
853 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
854 assert(offset < (1 << 15));
855
856 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
857
858 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
859 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
860 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
861 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
862
863 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
864 S_028B90_ENABLE(gs_num_invocations > 0);
865
866 va = shader->bo->gpu_address;
867 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
868
869 if (sscreen->info.chip_class >= GFX9) {
870 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
871 unsigned es_type = shader->key.part.gs.es->type;
872 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
873 struct gfx9_gs_info gs_info;
874
875 if (es_type == PIPE_SHADER_VERTEX)
876 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
877 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
878 else if (es_type == PIPE_SHADER_TESS_EVAL)
879 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
880 else
881 unreachable("invalid shader selector type");
882
883 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
884 * VGPR[0:4] are always loaded.
885 */
886 if (sel->info.uses_invocationid)
887 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
888 else if (sel->info.uses_primid)
889 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
890 else if (input_prim >= PIPE_PRIM_TRIANGLES)
891 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
892 else
893 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
894
895 unsigned num_user_sgprs;
896 if (es_type == PIPE_SHADER_VERTEX)
897 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
898 else
899 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
900
901 gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
902
903 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
904 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
905
906 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
907 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
908 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
909 S_00B228_DX10_CLAMP(1) |
910 S_00B228_FLOAT_MODE(shader->config.float_mode) |
911 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
912 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
913 S_00B22C_USER_SGPR(num_user_sgprs) |
914 S_00B22C_USER_SGPR_MSB(num_user_sgprs >> 5) |
915 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
916 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
917 S_00B22C_LDS_SIZE(gs_info.lds_size) |
918 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
919
920 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
921 S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) |
922 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) |
923 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup);
924 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
925 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup);
926 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
927 shader->key.part.gs.es->esgs_itemsize / 4;
928
929 if (es_type == PIPE_SHADER_TESS_EVAL)
930 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
931
932 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
933 NULL, pm4);
934 } else {
935 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
936 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
937
938 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
939 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
940 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
941 S_00B228_DX10_CLAMP(1) |
942 S_00B228_FLOAT_MODE(shader->config.float_mode));
943 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
944 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
945 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
946 }
947 }
948
949 static void si_emit_shader_vs(struct si_context *sctx)
950 {
951 struct si_shader *shader = sctx->queued.named.vs->shader;
952 if (!shader)
953 return;
954
955 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
956 SI_TRACKED_VGT_GS_MODE,
957 shader->ctx_reg.vs.vgt_gs_mode);
958 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
959 SI_TRACKED_VGT_PRIMITIVEID_EN,
960 shader->ctx_reg.vs.vgt_primitiveid_en);
961
962 if (sctx->chip_class <= VI) {
963 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
964 SI_TRACKED_VGT_REUSE_OFF,
965 shader->ctx_reg.vs.vgt_reuse_off);
966 }
967
968 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
969 SI_TRACKED_SPI_VS_OUT_CONFIG,
970 shader->ctx_reg.vs.spi_vs_out_config);
971
972 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
973 SI_TRACKED_SPI_SHADER_POS_FORMAT,
974 shader->ctx_reg.vs.spi_shader_pos_format);
975
976 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
977 SI_TRACKED_PA_CL_VTE_CNTL,
978 shader->ctx_reg.vs.pa_cl_vte_cntl);
979
980 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
981 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
982 SI_TRACKED_VGT_TF_PARAM,
983 shader->vgt_tf_param);
984 }
985
986 /**
987 * Compute the state for \p shader, which will run as a vertex shader on the
988 * hardware.
989 *
990 * If \p gs is non-NULL, it points to the geometry shader for which this shader
991 * is the copy shader.
992 */
993 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
994 struct si_shader_selector *gs)
995 {
996 const struct tgsi_shader_info *info = &shader->selector->info;
997 struct si_pm4_state *pm4;
998 unsigned num_user_sgprs, vgpr_comp_cnt;
999 uint64_t va;
1000 unsigned nparams, oc_lds_en;
1001 unsigned window_space =
1002 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1003 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1004
1005 pm4 = si_get_shader_pm4_state(shader);
1006 if (!pm4)
1007 return;
1008
1009 pm4->atom.emit = si_emit_shader_vs;
1010
1011 /* We always write VGT_GS_MODE in the VS state, because every switch
1012 * between different shader pipelines involving a different GS or no
1013 * GS at all involves a switch of the VS (different GS use different
1014 * copy shaders). On the other hand, when the API switches from a GS to
1015 * no GS and then back to the same GS used originally, the GS state is
1016 * not sent again.
1017 */
1018 if (!gs) {
1019 unsigned mode = V_028A40_GS_OFF;
1020
1021 /* PrimID needs GS scenario A. */
1022 if (enable_prim_id)
1023 mode = V_028A40_GS_SCENARIO_A;
1024
1025 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1026 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1027 } else {
1028 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1029 sscreen->info.chip_class);
1030 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1031 }
1032
1033 if (sscreen->info.chip_class <= VI) {
1034 /* Reuse needs to be set off if we write oViewport. */
1035 shader->ctx_reg.vs.vgt_reuse_off =
1036 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1037 }
1038
1039 va = shader->bo->gpu_address;
1040 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1041
1042 if (gs) {
1043 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1044 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1045 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1046 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1047 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1048 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1049 */
1050 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1051
1052 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1053 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1054 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1055 } else {
1056 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1057 }
1058 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1059 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1060 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1061 } else
1062 unreachable("invalid shader selector type");
1063
1064 /* VS is required to export at least one param. */
1065 nparams = MAX2(shader->info.nr_param_exports, 1);
1066 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1067
1068 shader->ctx_reg.vs.spi_shader_pos_format =
1069 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1070 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1071 V_02870C_SPI_SHADER_4COMP :
1072 V_02870C_SPI_SHADER_NONE) |
1073 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1074 V_02870C_SPI_SHADER_4COMP :
1075 V_02870C_SPI_SHADER_NONE) |
1076 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1077 V_02870C_SPI_SHADER_4COMP :
1078 V_02870C_SPI_SHADER_NONE);
1079
1080 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1081
1082 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1083 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1084 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
1085 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
1086 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
1087 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1088 S_00B128_DX10_CLAMP(1) |
1089 S_00B128_FLOAT_MODE(shader->config.float_mode));
1090 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
1091 S_00B12C_USER_SGPR(num_user_sgprs) |
1092 S_00B12C_OC_LDS_EN(oc_lds_en) |
1093 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1094 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1095 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1096 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1097 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
1098 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1099
1100 if (window_space)
1101 shader->ctx_reg.vs.pa_cl_vte_cntl =
1102 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1103 else
1104 shader->ctx_reg.vs.pa_cl_vte_cntl =
1105 S_028818_VTX_W0_FMT(1) |
1106 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1107 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1108 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1109
1110 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1111 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1112
1113 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1114 }
1115
1116 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1117 {
1118 struct tgsi_shader_info *info = &ps->selector->info;
1119 unsigned num_colors = !!(info->colors_read & 0x0f) +
1120 !!(info->colors_read & 0xf0);
1121 unsigned num_interp = ps->selector->info.num_inputs +
1122 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1123
1124 assert(num_interp <= 32);
1125 return MIN2(num_interp, 32);
1126 }
1127
1128 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1129 {
1130 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1131 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1132
1133 /* If the i-th target format is set, all previous target formats must
1134 * be non-zero to avoid hangs.
1135 */
1136 for (i = 0; i < num_targets; i++)
1137 if (!(value & (0xf << (i * 4))))
1138 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1139
1140 return value;
1141 }
1142
1143 static void si_emit_shader_ps(struct si_context *sctx)
1144 {
1145 struct si_shader *shader = sctx->queued.named.ps->shader;
1146 if (!shader)
1147 return;
1148
1149 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1150 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1151 SI_TRACKED_SPI_PS_INPUT_ENA,
1152 shader->ctx_reg.ps.spi_ps_input_ena,
1153 shader->ctx_reg.ps.spi_ps_input_addr);
1154
1155 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1156 SI_TRACKED_SPI_BARYC_CNTL,
1157 shader->ctx_reg.ps.spi_baryc_cntl);
1158 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1159 SI_TRACKED_SPI_PS_IN_CONTROL,
1160 shader->ctx_reg.ps.spi_ps_in_control);
1161
1162 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1163 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1164 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1165 shader->ctx_reg.ps.spi_shader_z_format,
1166 shader->ctx_reg.ps.spi_shader_col_format);
1167
1168 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1169 SI_TRACKED_CB_SHADER_MASK,
1170 shader->ctx_reg.ps.cb_shader_mask);
1171 }
1172
1173 static void si_shader_ps(struct si_shader *shader)
1174 {
1175 struct tgsi_shader_info *info = &shader->selector->info;
1176 struct si_pm4_state *pm4;
1177 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1178 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1179 uint64_t va;
1180 unsigned input_ena = shader->config.spi_ps_input_ena;
1181
1182 /* we need to enable at least one of them, otherwise we hang the GPU */
1183 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1184 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1185 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1186 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1187 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1188 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1189 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1190 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1191 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1192 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1193 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1194 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1195 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1196 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1197
1198 /* Validate interpolation optimization flags (read as implications). */
1199 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1200 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1201 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1202 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1203 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1204 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1205 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1206 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1207 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1208 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1209 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1210 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1211 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1212 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1213 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1214 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1215 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1216 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1217
1218 /* Validate cases when the optimizations are off (read as implications). */
1219 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1220 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1221 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1222 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1223 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1224 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1225
1226 pm4 = si_get_shader_pm4_state(shader);
1227 if (!pm4)
1228 return;
1229
1230 pm4->atom.emit = si_emit_shader_ps;
1231
1232 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1233 * Possible vaules:
1234 * 0 -> Position = pixel center
1235 * 1 -> Position = pixel centroid
1236 * 2 -> Position = at sample position
1237 *
1238 * From GLSL 4.5 specification, section 7.1:
1239 * "The variable gl_FragCoord is available as an input variable from
1240 * within fragment shaders and it holds the window relative coordinates
1241 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1242 * value can be for any location within the pixel, or one of the
1243 * fragment samples. The use of centroid does not further restrict
1244 * this value to be inside the current primitive."
1245 *
1246 * Meaning that centroid has no effect and we can return anything within
1247 * the pixel. Thus, return the value at sample position, because that's
1248 * the most accurate one shaders can get.
1249 */
1250 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1251
1252 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1253 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1254 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1255
1256 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1257 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1258
1259 /* Ensure that some export memory is always allocated, for two reasons:
1260 *
1261 * 1) Correctness: The hardware ignores the EXEC mask if no export
1262 * memory is allocated, so KILL and alpha test do not work correctly
1263 * without this.
1264 * 2) Performance: Every shader needs at least a NULL export, even when
1265 * it writes no color/depth output. The NULL export instruction
1266 * stalls without this setting.
1267 *
1268 * Don't add this to CB_SHADER_MASK.
1269 */
1270 if (!spi_shader_col_format &&
1271 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1272 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1273
1274 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1275 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1276
1277 /* Set interpolation controls. */
1278 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1279
1280 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1281 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1282 shader->ctx_reg.ps.spi_shader_z_format =
1283 ac_get_spi_shader_z_format(info->writes_z,
1284 info->writes_stencil,
1285 info->writes_samplemask);
1286 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1287 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1288
1289 va = shader->bo->gpu_address;
1290 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1291 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1292 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1293
1294 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1295 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1296 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
1297 S_00B028_DX10_CLAMP(1) |
1298 S_00B028_FLOAT_MODE(shader->config.float_mode));
1299 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1300 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1301 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1302 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1303 }
1304
1305 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1306 struct si_shader *shader)
1307 {
1308 switch (shader->selector->type) {
1309 case PIPE_SHADER_VERTEX:
1310 if (shader->key.as_ls)
1311 si_shader_ls(sscreen, shader);
1312 else if (shader->key.as_es)
1313 si_shader_es(sscreen, shader);
1314 else
1315 si_shader_vs(sscreen, shader, NULL);
1316 break;
1317 case PIPE_SHADER_TESS_CTRL:
1318 si_shader_hs(sscreen, shader);
1319 break;
1320 case PIPE_SHADER_TESS_EVAL:
1321 if (shader->key.as_es)
1322 si_shader_es(sscreen, shader);
1323 else
1324 si_shader_vs(sscreen, shader, NULL);
1325 break;
1326 case PIPE_SHADER_GEOMETRY:
1327 si_shader_gs(sscreen, shader);
1328 break;
1329 case PIPE_SHADER_FRAGMENT:
1330 si_shader_ps(shader);
1331 break;
1332 default:
1333 assert(0);
1334 }
1335 }
1336
1337 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1338 {
1339 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1340 if (sctx->queued.named.dsa)
1341 return sctx->queued.named.dsa->alpha_func;
1342
1343 return PIPE_FUNC_ALWAYS;
1344 }
1345
1346 static void si_shader_selector_key_vs(struct si_context *sctx,
1347 struct si_shader_selector *vs,
1348 struct si_shader_key *key,
1349 struct si_vs_prolog_bits *prolog_key)
1350 {
1351 if (!sctx->vertex_elements ||
1352 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS])
1353 return;
1354
1355 prolog_key->instance_divisor_is_one =
1356 sctx->vertex_elements->instance_divisor_is_one;
1357 prolog_key->instance_divisor_is_fetched =
1358 sctx->vertex_elements->instance_divisor_is_fetched;
1359
1360 /* Prefer a monolithic shader to allow scheduling divisions around
1361 * VBO loads. */
1362 if (prolog_key->instance_divisor_is_fetched)
1363 key->opt.prefer_mono = 1;
1364
1365 unsigned count = MIN2(vs->info.num_inputs,
1366 sctx->vertex_elements->count);
1367 memcpy(key->mono.vs_fix_fetch, sctx->vertex_elements->fix_fetch, count);
1368 }
1369
1370 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1371 struct si_shader_selector *vs,
1372 struct si_shader_key *key)
1373 {
1374 struct si_shader_selector *ps = sctx->ps_shader.cso;
1375
1376 key->opt.clip_disable =
1377 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1378 (vs->info.clipdist_writemask ||
1379 vs->info.writes_clipvertex) &&
1380 !vs->info.culldist_writemask;
1381
1382 /* Find out if PS is disabled. */
1383 bool ps_disabled = true;
1384 if (ps) {
1385 const struct si_state_blend *blend = sctx->queued.named.blend;
1386 bool alpha_to_coverage = blend && blend->alpha_to_coverage;
1387 bool ps_modifies_zs = ps->info.uses_kill ||
1388 ps->info.writes_z ||
1389 ps->info.writes_stencil ||
1390 ps->info.writes_samplemask ||
1391 alpha_to_coverage ||
1392 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1393 unsigned ps_colormask = si_get_total_colormask(sctx);
1394
1395 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1396 (!ps_colormask &&
1397 !ps_modifies_zs &&
1398 !ps->info.writes_memory);
1399 }
1400
1401 /* Find out which VS outputs aren't used by the PS. */
1402 uint64_t outputs_written = vs->outputs_written_before_ps;
1403 uint64_t inputs_read = 0;
1404
1405 /* Ignore outputs that are not passed from VS to PS. */
1406 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1407 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1408 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1409
1410 if (!ps_disabled) {
1411 inputs_read = ps->inputs_read;
1412 }
1413
1414 uint64_t linked = outputs_written & inputs_read;
1415
1416 key->opt.kill_outputs = ~linked & outputs_written;
1417 }
1418
1419 /* Compute the key for the hw shader variant */
1420 static inline void si_shader_selector_key(struct pipe_context *ctx,
1421 struct si_shader_selector *sel,
1422 struct si_shader_key *key)
1423 {
1424 struct si_context *sctx = (struct si_context *)ctx;
1425
1426 memset(key, 0, sizeof(*key));
1427
1428 switch (sel->type) {
1429 case PIPE_SHADER_VERTEX:
1430 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1431
1432 if (sctx->tes_shader.cso)
1433 key->as_ls = 1;
1434 else if (sctx->gs_shader.cso)
1435 key->as_es = 1;
1436 else {
1437 si_shader_selector_key_hw_vs(sctx, sel, key);
1438
1439 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1440 key->mono.u.vs_export_prim_id = 1;
1441 }
1442 break;
1443 case PIPE_SHADER_TESS_CTRL:
1444 if (sctx->chip_class >= GFX9) {
1445 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1446 key, &key->part.tcs.ls_prolog);
1447 key->part.tcs.ls = sctx->vs_shader.cso;
1448
1449 /* When the LS VGPR fix is needed, monolithic shaders
1450 * can:
1451 * - avoid initializing EXEC in both the LS prolog
1452 * and the LS main part when !vs_needs_prolog
1453 * - remove the fixup for unused input VGPRs
1454 */
1455 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1456
1457 /* The LS output / HS input layout can be communicated
1458 * directly instead of via user SGPRs for merged LS-HS.
1459 * The LS VGPR fix prefers this too.
1460 */
1461 key->opt.prefer_mono = 1;
1462 }
1463
1464 key->part.tcs.epilog.prim_mode =
1465 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1466 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1467 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1468 key->part.tcs.epilog.tes_reads_tess_factors =
1469 sctx->tes_shader.cso->info.reads_tess_factors;
1470
1471 if (sel == sctx->fixed_func_tcs_shader.cso)
1472 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1473 break;
1474 case PIPE_SHADER_TESS_EVAL:
1475 if (sctx->gs_shader.cso)
1476 key->as_es = 1;
1477 else {
1478 si_shader_selector_key_hw_vs(sctx, sel, key);
1479
1480 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1481 key->mono.u.vs_export_prim_id = 1;
1482 }
1483 break;
1484 case PIPE_SHADER_GEOMETRY:
1485 if (sctx->chip_class >= GFX9) {
1486 if (sctx->tes_shader.cso) {
1487 key->part.gs.es = sctx->tes_shader.cso;
1488 } else {
1489 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1490 key, &key->part.gs.vs_prolog);
1491 key->part.gs.es = sctx->vs_shader.cso;
1492 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1493 }
1494
1495 /* Merged ES-GS can have unbalanced wave usage.
1496 *
1497 * ES threads are per-vertex, while GS threads are
1498 * per-primitive. So without any amplification, there
1499 * are fewer GS threads than ES threads, which can result
1500 * in empty (no-op) GS waves. With too much amplification,
1501 * there are more GS threads than ES threads, which
1502 * can result in empty (no-op) ES waves.
1503 *
1504 * Non-monolithic shaders are implemented by setting EXEC
1505 * at the beginning of shader parts, and don't jump to
1506 * the end if EXEC is 0.
1507 *
1508 * Monolithic shaders use conditional blocks, so they can
1509 * jump and skip empty waves of ES or GS. So set this to
1510 * always use optimized variants, which are monolithic.
1511 */
1512 key->opt.prefer_mono = 1;
1513 }
1514 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1515 break;
1516 case PIPE_SHADER_FRAGMENT: {
1517 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1518 struct si_state_blend *blend = sctx->queued.named.blend;
1519
1520 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1521 sel->info.colors_written == 0x1)
1522 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1523
1524 if (blend) {
1525 /* Select the shader color format based on whether
1526 * blending or alpha are needed.
1527 */
1528 key->part.ps.epilog.spi_shader_col_format =
1529 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1530 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1531 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1532 sctx->framebuffer.spi_shader_col_format_blend) |
1533 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1534 sctx->framebuffer.spi_shader_col_format_alpha) |
1535 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1536 sctx->framebuffer.spi_shader_col_format);
1537 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1538
1539 /* The output for dual source blending should have
1540 * the same format as the first output.
1541 */
1542 if (blend->dual_src_blend)
1543 key->part.ps.epilog.spi_shader_col_format |=
1544 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1545 } else
1546 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1547
1548 /* If alpha-to-coverage is enabled, we have to export alpha
1549 * even if there is no color buffer.
1550 */
1551 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1552 blend && blend->alpha_to_coverage)
1553 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1554
1555 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1556 * to the range supported by the type if a channel has less
1557 * than 16 bits and the export format is 16_ABGR.
1558 */
1559 if (sctx->chip_class <= CIK && sctx->family != CHIP_HAWAII) {
1560 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1561 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1562 }
1563
1564 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1565 if (!key->part.ps.epilog.last_cbuf) {
1566 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1567 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1568 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1569 }
1570
1571 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1572 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1573
1574 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1575 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1576
1577 if (sctx->queued.named.blend) {
1578 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1579 rs->multisample_enable;
1580 }
1581
1582 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1583 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1584 (is_line && rs->line_smooth)) &&
1585 sctx->framebuffer.nr_samples <= 1;
1586 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1587
1588 if (sctx->ps_iter_samples > 1 &&
1589 sel->info.reads_samplemask) {
1590 key->part.ps.prolog.samplemask_log_ps_iter =
1591 util_logbase2(sctx->ps_iter_samples);
1592 }
1593
1594 if (rs->force_persample_interp &&
1595 rs->multisample_enable &&
1596 sctx->framebuffer.nr_samples > 1 &&
1597 sctx->ps_iter_samples > 1) {
1598 key->part.ps.prolog.force_persp_sample_interp =
1599 sel->info.uses_persp_center ||
1600 sel->info.uses_persp_centroid;
1601
1602 key->part.ps.prolog.force_linear_sample_interp =
1603 sel->info.uses_linear_center ||
1604 sel->info.uses_linear_centroid;
1605 } else if (rs->multisample_enable &&
1606 sctx->framebuffer.nr_samples > 1) {
1607 key->part.ps.prolog.bc_optimize_for_persp =
1608 sel->info.uses_persp_center &&
1609 sel->info.uses_persp_centroid;
1610 key->part.ps.prolog.bc_optimize_for_linear =
1611 sel->info.uses_linear_center &&
1612 sel->info.uses_linear_centroid;
1613 } else {
1614 /* Make sure SPI doesn't compute more than 1 pair
1615 * of (i,j), which is the optimization here. */
1616 key->part.ps.prolog.force_persp_center_interp =
1617 sel->info.uses_persp_center +
1618 sel->info.uses_persp_centroid +
1619 sel->info.uses_persp_sample > 1;
1620
1621 key->part.ps.prolog.force_linear_center_interp =
1622 sel->info.uses_linear_center +
1623 sel->info.uses_linear_centroid +
1624 sel->info.uses_linear_sample > 1;
1625
1626 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
1627 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1628 }
1629
1630 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1631
1632 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1633 if (sctx->ps_uses_fbfetch) {
1634 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
1635 struct pipe_resource *tex = cb0->texture;
1636
1637 /* 1D textures are allocated and used as 2D on GFX9. */
1638 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
1639 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
1640 (tex->target == PIPE_TEXTURE_1D ||
1641 tex->target == PIPE_TEXTURE_1D_ARRAY);
1642 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
1643 tex->target == PIPE_TEXTURE_2D_ARRAY ||
1644 tex->target == PIPE_TEXTURE_CUBE ||
1645 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
1646 tex->target == PIPE_TEXTURE_3D;
1647 }
1648 break;
1649 }
1650 default:
1651 assert(0);
1652 }
1653
1654 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
1655 memset(&key->opt, 0, sizeof(key->opt));
1656 }
1657
1658 static void si_build_shader_variant(struct si_shader *shader,
1659 int thread_index,
1660 bool low_priority)
1661 {
1662 struct si_shader_selector *sel = shader->selector;
1663 struct si_screen *sscreen = sel->screen;
1664 struct ac_llvm_compiler *compiler;
1665 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1666 int r;
1667
1668 if (thread_index >= 0) {
1669 if (low_priority) {
1670 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
1671 compiler = &sscreen->compiler_lowp[thread_index];
1672 } else {
1673 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
1674 compiler = &sscreen->compiler[thread_index];
1675 }
1676 if (!debug->async)
1677 debug = NULL;
1678 } else {
1679 assert(!low_priority);
1680 compiler = shader->compiler_ctx_state.compiler;
1681 }
1682
1683 r = si_shader_create(sscreen, compiler, shader, debug);
1684 if (unlikely(r)) {
1685 PRINT_ERR("Failed to build shader variant (type=%u) %d\n",
1686 sel->type, r);
1687 shader->compilation_failed = true;
1688 return;
1689 }
1690
1691 if (shader->compiler_ctx_state.is_debug_context) {
1692 FILE *f = open_memstream(&shader->shader_log,
1693 &shader->shader_log_size);
1694 if (f) {
1695 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1696 fclose(f);
1697 }
1698 }
1699
1700 si_shader_init_pm4_state(sscreen, shader);
1701 }
1702
1703 static void si_build_shader_variant_low_priority(void *job, int thread_index)
1704 {
1705 struct si_shader *shader = (struct si_shader *)job;
1706
1707 assert(thread_index >= 0);
1708
1709 si_build_shader_variant(shader, thread_index, true);
1710 }
1711
1712 static const struct si_shader_key zeroed;
1713
1714 static bool si_check_missing_main_part(struct si_screen *sscreen,
1715 struct si_shader_selector *sel,
1716 struct si_compiler_ctx_state *compiler_state,
1717 struct si_shader_key *key)
1718 {
1719 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1720
1721 if (!*mainp) {
1722 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1723
1724 if (!main_part)
1725 return false;
1726
1727 /* We can leave the fence as permanently signaled because the
1728 * main part becomes visible globally only after it has been
1729 * compiled. */
1730 util_queue_fence_init(&main_part->ready);
1731
1732 main_part->selector = sel;
1733 main_part->key.as_es = key->as_es;
1734 main_part->key.as_ls = key->as_ls;
1735 main_part->is_monolithic = false;
1736
1737 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
1738 main_part, &compiler_state->debug) != 0) {
1739 FREE(main_part);
1740 return false;
1741 }
1742 *mainp = main_part;
1743 }
1744 return true;
1745 }
1746
1747 /* Select the hw shader variant depending on the current state. */
1748 static int si_shader_select_with_key(struct si_screen *sscreen,
1749 struct si_shader_ctx_state *state,
1750 struct si_compiler_ctx_state *compiler_state,
1751 struct si_shader_key *key,
1752 int thread_index)
1753 {
1754 struct si_shader_selector *sel = state->cso;
1755 struct si_shader_selector *previous_stage_sel = NULL;
1756 struct si_shader *current = state->current;
1757 struct si_shader *iter, *shader = NULL;
1758
1759 again:
1760 /* Check if we don't need to change anything.
1761 * This path is also used for most shaders that don't need multiple
1762 * variants, it will cost just a computation of the key and this
1763 * test. */
1764 if (likely(current &&
1765 memcmp(&current->key, key, sizeof(*key)) == 0)) {
1766 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
1767 if (current->is_optimized) {
1768 memset(&key->opt, 0, sizeof(key->opt));
1769 goto current_not_ready;
1770 }
1771
1772 util_queue_fence_wait(&current->ready);
1773 }
1774
1775 return current->compilation_failed ? -1 : 0;
1776 }
1777 current_not_ready:
1778
1779 /* This must be done before the mutex is locked, because async GS
1780 * compilation calls this function too, and therefore must enter
1781 * the mutex first.
1782 *
1783 * Only wait if we are in a draw call. Don't wait if we are
1784 * in a compiler thread.
1785 */
1786 if (thread_index < 0)
1787 util_queue_fence_wait(&sel->ready);
1788
1789 mtx_lock(&sel->mutex);
1790
1791 /* Find the shader variant. */
1792 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1793 /* Don't check the "current" shader. We checked it above. */
1794 if (current != iter &&
1795 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1796 mtx_unlock(&sel->mutex);
1797
1798 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
1799 /* If it's an optimized shader and its compilation has
1800 * been started but isn't done, use the unoptimized
1801 * shader so as not to cause a stall due to compilation.
1802 */
1803 if (iter->is_optimized) {
1804 memset(&key->opt, 0, sizeof(key->opt));
1805 goto again;
1806 }
1807
1808 util_queue_fence_wait(&iter->ready);
1809 }
1810
1811 if (iter->compilation_failed) {
1812 return -1; /* skip the draw call */
1813 }
1814
1815 state->current = iter;
1816 return 0;
1817 }
1818 }
1819
1820 /* Build a new shader. */
1821 shader = CALLOC_STRUCT(si_shader);
1822 if (!shader) {
1823 mtx_unlock(&sel->mutex);
1824 return -ENOMEM;
1825 }
1826
1827 util_queue_fence_init(&shader->ready);
1828
1829 shader->selector = sel;
1830 shader->key = *key;
1831 shader->compiler_ctx_state = *compiler_state;
1832
1833 /* If this is a merged shader, get the first shader's selector. */
1834 if (sscreen->info.chip_class >= GFX9) {
1835 if (sel->type == PIPE_SHADER_TESS_CTRL)
1836 previous_stage_sel = key->part.tcs.ls;
1837 else if (sel->type == PIPE_SHADER_GEOMETRY)
1838 previous_stage_sel = key->part.gs.es;
1839
1840 /* We need to wait for the previous shader. */
1841 if (previous_stage_sel && thread_index < 0)
1842 util_queue_fence_wait(&previous_stage_sel->ready);
1843 }
1844
1845 /* Compile the main shader part if it doesn't exist. This can happen
1846 * if the initial guess was wrong. */
1847 bool is_pure_monolithic =
1848 sscreen->use_monolithic_shaders ||
1849 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1850
1851 if (!is_pure_monolithic) {
1852 bool ok;
1853
1854 /* Make sure the main shader part is present. This is needed
1855 * for shaders that can be compiled as VS, LS, or ES, and only
1856 * one of them is compiled at creation.
1857 *
1858 * For merged shaders, check that the starting shader's main
1859 * part is present.
1860 */
1861 if (previous_stage_sel) {
1862 struct si_shader_key shader1_key = zeroed;
1863
1864 if (sel->type == PIPE_SHADER_TESS_CTRL)
1865 shader1_key.as_ls = 1;
1866 else if (sel->type == PIPE_SHADER_GEOMETRY)
1867 shader1_key.as_es = 1;
1868 else
1869 assert(0);
1870
1871 mtx_lock(&previous_stage_sel->mutex);
1872 ok = si_check_missing_main_part(sscreen,
1873 previous_stage_sel,
1874 compiler_state, &shader1_key);
1875 mtx_unlock(&previous_stage_sel->mutex);
1876 } else {
1877 ok = si_check_missing_main_part(sscreen, sel,
1878 compiler_state, key);
1879 }
1880 if (!ok) {
1881 FREE(shader);
1882 mtx_unlock(&sel->mutex);
1883 return -ENOMEM; /* skip the draw call */
1884 }
1885 }
1886
1887 /* Keep the reference to the 1st shader of merged shaders, so that
1888 * Gallium can't destroy it before we destroy the 2nd shader.
1889 *
1890 * Set sctx = NULL, because it's unused if we're not releasing
1891 * the shader, and we don't have any sctx here.
1892 */
1893 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
1894 previous_stage_sel);
1895
1896 /* Monolithic-only shaders don't make a distinction between optimized
1897 * and unoptimized. */
1898 shader->is_monolithic =
1899 is_pure_monolithic ||
1900 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1901
1902 shader->is_optimized =
1903 !is_pure_monolithic &&
1904 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1905
1906 /* If it's an optimized shader, compile it asynchronously. */
1907 if (shader->is_optimized &&
1908 !is_pure_monolithic &&
1909 thread_index < 0) {
1910 /* Compile it asynchronously. */
1911 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
1912 shader, &shader->ready,
1913 si_build_shader_variant_low_priority, NULL);
1914
1915 /* Add only after the ready fence was reset, to guard against a
1916 * race with si_bind_XX_shader. */
1917 if (!sel->last_variant) {
1918 sel->first_variant = shader;
1919 sel->last_variant = shader;
1920 } else {
1921 sel->last_variant->next_variant = shader;
1922 sel->last_variant = shader;
1923 }
1924
1925 /* Use the default (unoptimized) shader for now. */
1926 memset(&key->opt, 0, sizeof(key->opt));
1927 mtx_unlock(&sel->mutex);
1928 goto again;
1929 }
1930
1931 /* Reset the fence before adding to the variant list. */
1932 util_queue_fence_reset(&shader->ready);
1933
1934 if (!sel->last_variant) {
1935 sel->first_variant = shader;
1936 sel->last_variant = shader;
1937 } else {
1938 sel->last_variant->next_variant = shader;
1939 sel->last_variant = shader;
1940 }
1941
1942 mtx_unlock(&sel->mutex);
1943
1944 assert(!shader->is_optimized);
1945 si_build_shader_variant(shader, thread_index, false);
1946
1947 util_queue_fence_signal(&shader->ready);
1948
1949 if (!shader->compilation_failed)
1950 state->current = shader;
1951
1952 return shader->compilation_failed ? -1 : 0;
1953 }
1954
1955 static int si_shader_select(struct pipe_context *ctx,
1956 struct si_shader_ctx_state *state,
1957 struct si_compiler_ctx_state *compiler_state)
1958 {
1959 struct si_context *sctx = (struct si_context *)ctx;
1960 struct si_shader_key key;
1961
1962 si_shader_selector_key(ctx, state->cso, &key);
1963 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1964 &key, -1);
1965 }
1966
1967 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1968 bool streamout,
1969 struct si_shader_key *key)
1970 {
1971 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1972
1973 switch (info->processor) {
1974 case PIPE_SHADER_VERTEX:
1975 switch (next_shader) {
1976 case PIPE_SHADER_GEOMETRY:
1977 key->as_es = 1;
1978 break;
1979 case PIPE_SHADER_TESS_CTRL:
1980 case PIPE_SHADER_TESS_EVAL:
1981 key->as_ls = 1;
1982 break;
1983 default:
1984 /* If POSITION isn't written, it can only be a HW VS
1985 * if streamout is used. If streamout isn't used,
1986 * assume that it's a HW LS. (the next shader is TCS)
1987 * This heuristic is needed for separate shader objects.
1988 */
1989 if (!info->writes_position && !streamout)
1990 key->as_ls = 1;
1991 }
1992 break;
1993
1994 case PIPE_SHADER_TESS_EVAL:
1995 if (next_shader == PIPE_SHADER_GEOMETRY ||
1996 !info->writes_position)
1997 key->as_es = 1;
1998 break;
1999 }
2000 }
2001
2002 /**
2003 * Compile the main shader part or the monolithic shader as part of
2004 * si_shader_selector initialization. Since it can be done asynchronously,
2005 * there is no way to report compile failures to applications.
2006 */
2007 static void si_init_shader_selector_async(void *job, int thread_index)
2008 {
2009 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2010 struct si_screen *sscreen = sel->screen;
2011 struct ac_llvm_compiler *compiler;
2012 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2013
2014 assert(!debug->debug_message || debug->async);
2015 assert(thread_index >= 0);
2016 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2017 compiler = &sscreen->compiler[thread_index];
2018
2019 /* Compile the main shader part for use with a prolog and/or epilog.
2020 * If this fails, the driver will try to compile a monolithic shader
2021 * on demand.
2022 */
2023 if (!sscreen->use_monolithic_shaders) {
2024 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2025 void *ir_binary = NULL;
2026
2027 if (!shader) {
2028 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2029 return;
2030 }
2031
2032 /* We can leave the fence signaled because use of the default
2033 * main part is guarded by the selector's ready fence. */
2034 util_queue_fence_init(&shader->ready);
2035
2036 shader->selector = sel;
2037 shader->is_monolithic = false;
2038 si_parse_next_shader_property(&sel->info,
2039 sel->so.num_outputs != 0,
2040 &shader->key);
2041
2042 if (sel->tokens || sel->nir)
2043 ir_binary = si_get_ir_binary(sel);
2044
2045 /* Try to load the shader from the shader cache. */
2046 mtx_lock(&sscreen->shader_cache_mutex);
2047
2048 if (ir_binary &&
2049 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2050 mtx_unlock(&sscreen->shader_cache_mutex);
2051 si_shader_dump_stats_for_shader_db(shader, debug);
2052 } else {
2053 mtx_unlock(&sscreen->shader_cache_mutex);
2054
2055 /* Compile the shader if it hasn't been loaded from the cache. */
2056 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2057 debug) != 0) {
2058 FREE(shader);
2059 FREE(ir_binary);
2060 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2061 return;
2062 }
2063
2064 if (ir_binary) {
2065 mtx_lock(&sscreen->shader_cache_mutex);
2066 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2067 FREE(ir_binary);
2068 mtx_unlock(&sscreen->shader_cache_mutex);
2069 }
2070 }
2071
2072 *si_get_main_shader_part(sel, &shader->key) = shader;
2073
2074 /* Unset "outputs_written" flags for outputs converted to
2075 * DEFAULT_VAL, so that later inter-shader optimizations don't
2076 * try to eliminate outputs that don't exist in the final
2077 * shader.
2078 *
2079 * This is only done if non-monolithic shaders are enabled.
2080 */
2081 if ((sel->type == PIPE_SHADER_VERTEX ||
2082 sel->type == PIPE_SHADER_TESS_EVAL) &&
2083 !shader->key.as_ls &&
2084 !shader->key.as_es) {
2085 unsigned i;
2086
2087 for (i = 0; i < sel->info.num_outputs; i++) {
2088 unsigned offset = shader->info.vs_output_param_offset[i];
2089
2090 if (offset <= AC_EXP_PARAM_OFFSET_31)
2091 continue;
2092
2093 unsigned name = sel->info.output_semantic_name[i];
2094 unsigned index = sel->info.output_semantic_index[i];
2095 unsigned id;
2096
2097 switch (name) {
2098 case TGSI_SEMANTIC_GENERIC:
2099 /* don't process indices the function can't handle */
2100 if (index >= SI_MAX_IO_GENERIC)
2101 break;
2102 /* fall through */
2103 default:
2104 id = si_shader_io_get_unique_index(name, index, true);
2105 sel->outputs_written_before_ps &= ~(1ull << id);
2106 break;
2107 case TGSI_SEMANTIC_POSITION: /* ignore these */
2108 case TGSI_SEMANTIC_PSIZE:
2109 case TGSI_SEMANTIC_CLIPVERTEX:
2110 case TGSI_SEMANTIC_EDGEFLAG:
2111 break;
2112 }
2113 }
2114 }
2115 }
2116
2117 /* The GS copy shader is always pre-compiled. */
2118 if (sel->type == PIPE_SHADER_GEOMETRY) {
2119 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2120 if (!sel->gs_copy_shader) {
2121 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2122 return;
2123 }
2124
2125 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2126 }
2127 }
2128
2129 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2130 struct util_queue_fence *ready_fence,
2131 struct si_compiler_ctx_state *compiler_ctx_state,
2132 void *job, util_queue_execute_func execute)
2133 {
2134 util_queue_fence_init(ready_fence);
2135
2136 struct util_async_debug_callback async_debug;
2137 bool wait =
2138 (sctx->debug.debug_message && !sctx->debug.async) ||
2139 sctx->is_debug ||
2140 si_can_dump_shader(sctx->screen, processor);
2141
2142 if (wait) {
2143 u_async_debug_init(&async_debug);
2144 compiler_ctx_state->debug = async_debug.base;
2145 }
2146
2147 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2148 ready_fence, execute, NULL);
2149
2150 if (wait) {
2151 util_queue_fence_wait(ready_fence);
2152 u_async_debug_drain(&async_debug, &sctx->debug);
2153 u_async_debug_cleanup(&async_debug);
2154 }
2155 }
2156
2157 /* Return descriptor slot usage masks from the given shader info. */
2158 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2159 uint32_t *const_and_shader_buffers,
2160 uint64_t *samplers_and_images)
2161 {
2162 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2163
2164 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2165 num_constbufs = util_last_bit(info->const_buffers_declared);
2166 /* two 8-byte images share one 16-byte slot */
2167 num_images = align(util_last_bit(info->images_declared), 2);
2168 num_samplers = util_last_bit(info->samplers_declared);
2169
2170 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2171 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2172 *const_and_shader_buffers =
2173 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2174
2175 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2176 start = si_get_image_slot(num_images - 1) / 2;
2177 *samplers_and_images =
2178 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2179 }
2180
2181 static void *si_create_shader_selector(struct pipe_context *ctx,
2182 const struct pipe_shader_state *state)
2183 {
2184 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2185 struct si_context *sctx = (struct si_context*)ctx;
2186 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2187 int i;
2188
2189 if (!sel)
2190 return NULL;
2191
2192 pipe_reference_init(&sel->reference, 1);
2193 sel->screen = sscreen;
2194 sel->compiler_ctx_state.debug = sctx->debug;
2195 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2196
2197 sel->so = state->stream_output;
2198
2199 if (state->type == PIPE_SHADER_IR_TGSI) {
2200 sel->tokens = tgsi_dup_tokens(state->tokens);
2201 if (!sel->tokens) {
2202 FREE(sel);
2203 return NULL;
2204 }
2205
2206 tgsi_scan_shader(state->tokens, &sel->info);
2207 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2208 } else {
2209 assert(state->type == PIPE_SHADER_IR_NIR);
2210
2211 sel->nir = state->ir.nir;
2212
2213 si_nir_scan_shader(sel->nir, &sel->info);
2214 si_nir_scan_tess_ctrl(sel->nir, &sel->info, &sel->tcs_info);
2215
2216 si_lower_nir(sel);
2217 }
2218
2219 sel->type = sel->info.processor;
2220 p_atomic_inc(&sscreen->num_shaders_created);
2221 si_get_active_slot_masks(&sel->info,
2222 &sel->active_const_and_shader_buffers,
2223 &sel->active_samplers_and_images);
2224
2225 /* Record which streamout buffers are enabled. */
2226 for (i = 0; i < sel->so.num_outputs; i++) {
2227 sel->enabled_streamout_buffer_mask |=
2228 (1 << sel->so.output[i].output_buffer) <<
2229 (sel->so.output[i].stream * 4);
2230 }
2231
2232 /* The prolog is a no-op if there are no inputs. */
2233 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2234 sel->info.num_inputs &&
2235 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2236
2237 sel->force_correct_derivs_after_kill =
2238 sel->type == PIPE_SHADER_FRAGMENT &&
2239 sel->info.uses_derivatives &&
2240 sel->info.uses_kill &&
2241 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2242
2243 /* Set which opcode uses which (i,j) pair. */
2244 if (sel->info.uses_persp_opcode_interp_centroid)
2245 sel->info.uses_persp_centroid = true;
2246
2247 if (sel->info.uses_linear_opcode_interp_centroid)
2248 sel->info.uses_linear_centroid = true;
2249
2250 if (sel->info.uses_persp_opcode_interp_offset ||
2251 sel->info.uses_persp_opcode_interp_sample)
2252 sel->info.uses_persp_center = true;
2253
2254 if (sel->info.uses_linear_opcode_interp_offset ||
2255 sel->info.uses_linear_opcode_interp_sample)
2256 sel->info.uses_linear_center = true;
2257
2258 switch (sel->type) {
2259 case PIPE_SHADER_GEOMETRY:
2260 sel->gs_output_prim =
2261 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2262 sel->gs_max_out_vertices =
2263 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2264 sel->gs_num_invocations =
2265 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2266 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2267 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2268 sel->gs_max_out_vertices;
2269
2270 sel->max_gs_stream = 0;
2271 for (i = 0; i < sel->so.num_outputs; i++)
2272 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2273 sel->so.output[i].stream);
2274
2275 sel->gs_input_verts_per_prim =
2276 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2277 break;
2278
2279 case PIPE_SHADER_TESS_CTRL:
2280 /* Always reserve space for these. */
2281 sel->patch_outputs_written |=
2282 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2283 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2284 /* fall through */
2285 case PIPE_SHADER_VERTEX:
2286 case PIPE_SHADER_TESS_EVAL:
2287 for (i = 0; i < sel->info.num_outputs; i++) {
2288 unsigned name = sel->info.output_semantic_name[i];
2289 unsigned index = sel->info.output_semantic_index[i];
2290
2291 switch (name) {
2292 case TGSI_SEMANTIC_TESSINNER:
2293 case TGSI_SEMANTIC_TESSOUTER:
2294 case TGSI_SEMANTIC_PATCH:
2295 sel->patch_outputs_written |=
2296 1ull << si_shader_io_get_unique_index_patch(name, index);
2297 break;
2298
2299 case TGSI_SEMANTIC_GENERIC:
2300 /* don't process indices the function can't handle */
2301 if (index >= SI_MAX_IO_GENERIC)
2302 break;
2303 /* fall through */
2304 default:
2305 sel->outputs_written |=
2306 1ull << si_shader_io_get_unique_index(name, index, false);
2307 sel->outputs_written_before_ps |=
2308 1ull << si_shader_io_get_unique_index(name, index, true);
2309 break;
2310 case TGSI_SEMANTIC_EDGEFLAG:
2311 break;
2312 }
2313 }
2314 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2315 sel->lshs_vertex_stride = sel->esgs_itemsize;
2316
2317 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2318 * will start on a different bank. (except for the maximum 32*16).
2319 */
2320 if (sel->lshs_vertex_stride < 32*16)
2321 sel->lshs_vertex_stride += 4;
2322
2323 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2324 * conflicts, i.e. each vertex will start at a different bank.
2325 */
2326 if (sctx->chip_class >= GFX9)
2327 sel->esgs_itemsize += 4;
2328
2329 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2330 break;
2331
2332 case PIPE_SHADER_FRAGMENT:
2333 for (i = 0; i < sel->info.num_inputs; i++) {
2334 unsigned name = sel->info.input_semantic_name[i];
2335 unsigned index = sel->info.input_semantic_index[i];
2336
2337 switch (name) {
2338 case TGSI_SEMANTIC_GENERIC:
2339 /* don't process indices the function can't handle */
2340 if (index >= SI_MAX_IO_GENERIC)
2341 break;
2342 /* fall through */
2343 default:
2344 sel->inputs_read |=
2345 1ull << si_shader_io_get_unique_index(name, index, true);
2346 break;
2347 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2348 break;
2349 }
2350 }
2351
2352 for (i = 0; i < 8; i++)
2353 if (sel->info.colors_written & (1 << i))
2354 sel->colors_written_4bit |= 0xf << (4 * i);
2355
2356 for (i = 0; i < sel->info.num_inputs; i++) {
2357 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2358 int index = sel->info.input_semantic_index[i];
2359 sel->color_attr_index[index] = i;
2360 }
2361 }
2362 break;
2363 }
2364
2365 /* PA_CL_VS_OUT_CNTL */
2366 bool misc_vec_ena =
2367 sel->info.writes_psize || sel->info.writes_edgeflag ||
2368 sel->info.writes_layer || sel->info.writes_viewport_index;
2369 sel->pa_cl_vs_out_cntl =
2370 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2371 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2372 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2373 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2374 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2375 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2376 sel->clipdist_mask = sel->info.writes_clipvertex ?
2377 SIX_BITS : sel->info.clipdist_writemask;
2378 sel->culldist_mask = sel->info.culldist_writemask <<
2379 sel->info.num_written_clipdistance;
2380
2381 /* DB_SHADER_CONTROL */
2382 sel->db_shader_control =
2383 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2384 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2385 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2386 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2387
2388 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2389 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2390 sel->db_shader_control |=
2391 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2392 break;
2393 case TGSI_FS_DEPTH_LAYOUT_LESS:
2394 sel->db_shader_control |=
2395 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2396 break;
2397 }
2398
2399 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2400 *
2401 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2402 * --|-----------|------------|------------|--------------------|-------------------|-------------
2403 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2404 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2405 * 2 | false | true | n/a | LateZ | 1 | 0
2406 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2407 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2408 *
2409 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2410 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2411 *
2412 * Don't use ReZ without profiling !!!
2413 *
2414 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2415 * shaders.
2416 */
2417 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2418 /* Cases 3, 4. */
2419 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2420 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2421 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2422 } else if (sel->info.writes_memory) {
2423 /* Case 2. */
2424 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2425 S_02880C_EXEC_ON_HIER_FAIL(1);
2426 } else {
2427 /* Case 1. */
2428 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2429 }
2430
2431 (void) mtx_init(&sel->mutex, mtx_plain);
2432
2433 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2434 &sel->compiler_ctx_state, sel,
2435 si_init_shader_selector_async);
2436 return sel;
2437 }
2438
2439 static void si_update_streamout_state(struct si_context *sctx)
2440 {
2441 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2442
2443 if (!shader_with_so)
2444 return;
2445
2446 sctx->streamout.enabled_stream_buffers_mask =
2447 shader_with_so->enabled_streamout_buffer_mask;
2448 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2449 }
2450
2451 static void si_update_clip_regs(struct si_context *sctx,
2452 struct si_shader_selector *old_hw_vs,
2453 struct si_shader *old_hw_vs_variant,
2454 struct si_shader_selector *next_hw_vs,
2455 struct si_shader *next_hw_vs_variant)
2456 {
2457 if (next_hw_vs &&
2458 (!old_hw_vs ||
2459 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2460 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2461 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2462 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2463 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2464 !old_hw_vs_variant ||
2465 !next_hw_vs_variant ||
2466 old_hw_vs_variant->key.opt.clip_disable !=
2467 next_hw_vs_variant->key.opt.clip_disable))
2468 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2469 }
2470
2471 static void si_update_common_shader_state(struct si_context *sctx)
2472 {
2473 sctx->uses_bindless_samplers =
2474 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2475 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2476 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2477 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2478 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2479 sctx->uses_bindless_images =
2480 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2481 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2482 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2483 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2484 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2485 sctx->do_update_shaders = true;
2486 }
2487
2488 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2489 {
2490 struct si_context *sctx = (struct si_context *)ctx;
2491 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2492 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2493 struct si_shader_selector *sel = state;
2494
2495 if (sctx->vs_shader.cso == sel)
2496 return;
2497
2498 sctx->vs_shader.cso = sel;
2499 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2500 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2501
2502 si_update_common_shader_state(sctx);
2503 si_update_vs_viewport_state(sctx);
2504 si_set_active_descriptors_for_shader(sctx, sel);
2505 si_update_streamout_state(sctx);
2506 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2507 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2508 }
2509
2510 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2511 {
2512 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2513 (sctx->tes_shader.cso &&
2514 sctx->tes_shader.cso->info.uses_primid) ||
2515 (sctx->tcs_shader.cso &&
2516 sctx->tcs_shader.cso->info.uses_primid) ||
2517 (sctx->gs_shader.cso &&
2518 sctx->gs_shader.cso->info.uses_primid) ||
2519 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2520 sctx->ps_shader.cso->info.uses_primid);
2521 }
2522
2523 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2524 {
2525 struct si_context *sctx = (struct si_context *)ctx;
2526 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2527 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2528 struct si_shader_selector *sel = state;
2529 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2530
2531 if (sctx->gs_shader.cso == sel)
2532 return;
2533
2534 sctx->gs_shader.cso = sel;
2535 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2536 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2537
2538 si_update_common_shader_state(sctx);
2539 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2540
2541 if (enable_changed) {
2542 si_shader_change_notify(sctx);
2543 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2544 si_update_tess_uses_prim_id(sctx);
2545 }
2546 si_update_vs_viewport_state(sctx);
2547 si_set_active_descriptors_for_shader(sctx, sel);
2548 si_update_streamout_state(sctx);
2549 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2550 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2551 }
2552
2553 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2554 {
2555 struct si_context *sctx = (struct si_context *)ctx;
2556 struct si_shader_selector *sel = state;
2557 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2558
2559 if (sctx->tcs_shader.cso == sel)
2560 return;
2561
2562 sctx->tcs_shader.cso = sel;
2563 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2564 si_update_tess_uses_prim_id(sctx);
2565
2566 si_update_common_shader_state(sctx);
2567
2568 if (enable_changed)
2569 sctx->last_tcs = NULL; /* invalidate derived tess state */
2570
2571 si_set_active_descriptors_for_shader(sctx, sel);
2572 }
2573
2574 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2575 {
2576 struct si_context *sctx = (struct si_context *)ctx;
2577 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2578 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2579 struct si_shader_selector *sel = state;
2580 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2581
2582 if (sctx->tes_shader.cso == sel)
2583 return;
2584
2585 sctx->tes_shader.cso = sel;
2586 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2587 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2588 si_update_tess_uses_prim_id(sctx);
2589
2590 si_update_common_shader_state(sctx);
2591 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2592
2593 if (enable_changed) {
2594 si_shader_change_notify(sctx);
2595 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2596 }
2597 si_update_vs_viewport_state(sctx);
2598 si_set_active_descriptors_for_shader(sctx, sel);
2599 si_update_streamout_state(sctx);
2600 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2601 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2602 }
2603
2604 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2605 {
2606 struct si_context *sctx = (struct si_context *)ctx;
2607 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
2608 struct si_shader_selector *sel = state;
2609
2610 /* skip if supplied shader is one already in use */
2611 if (old_sel == sel)
2612 return;
2613
2614 sctx->ps_shader.cso = sel;
2615 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2616
2617 si_update_common_shader_state(sctx);
2618 if (sel) {
2619 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2620 si_update_tess_uses_prim_id(sctx);
2621
2622 if (!old_sel ||
2623 old_sel->info.colors_written != sel->info.colors_written)
2624 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2625
2626 if (sctx->screen->has_out_of_order_rast &&
2627 (!old_sel ||
2628 old_sel->info.writes_memory != sel->info.writes_memory ||
2629 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
2630 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
2631 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2632 }
2633 si_set_active_descriptors_for_shader(sctx, sel);
2634 si_update_ps_colorbuf0_slot(sctx);
2635 }
2636
2637 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2638 {
2639 if (shader->is_optimized) {
2640 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
2641 &shader->ready);
2642 }
2643
2644 util_queue_fence_destroy(&shader->ready);
2645
2646 if (shader->pm4) {
2647 switch (shader->selector->type) {
2648 case PIPE_SHADER_VERTEX:
2649 if (shader->key.as_ls) {
2650 assert(sctx->chip_class <= VI);
2651 si_pm4_delete_state(sctx, ls, shader->pm4);
2652 } else if (shader->key.as_es) {
2653 assert(sctx->chip_class <= VI);
2654 si_pm4_delete_state(sctx, es, shader->pm4);
2655 } else {
2656 si_pm4_delete_state(sctx, vs, shader->pm4);
2657 }
2658 break;
2659 case PIPE_SHADER_TESS_CTRL:
2660 si_pm4_delete_state(sctx, hs, shader->pm4);
2661 break;
2662 case PIPE_SHADER_TESS_EVAL:
2663 if (shader->key.as_es) {
2664 assert(sctx->chip_class <= VI);
2665 si_pm4_delete_state(sctx, es, shader->pm4);
2666 } else {
2667 si_pm4_delete_state(sctx, vs, shader->pm4);
2668 }
2669 break;
2670 case PIPE_SHADER_GEOMETRY:
2671 if (shader->is_gs_copy_shader)
2672 si_pm4_delete_state(sctx, vs, shader->pm4);
2673 else
2674 si_pm4_delete_state(sctx, gs, shader->pm4);
2675 break;
2676 case PIPE_SHADER_FRAGMENT:
2677 si_pm4_delete_state(sctx, ps, shader->pm4);
2678 break;
2679 }
2680 }
2681
2682 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2683 si_shader_destroy(shader);
2684 free(shader);
2685 }
2686
2687 void si_destroy_shader_selector(struct si_context *sctx,
2688 struct si_shader_selector *sel)
2689 {
2690 struct si_shader *p = sel->first_variant, *c;
2691 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2692 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2693 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2694 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2695 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2696 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2697 };
2698
2699 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
2700
2701 if (current_shader[sel->type]->cso == sel) {
2702 current_shader[sel->type]->cso = NULL;
2703 current_shader[sel->type]->current = NULL;
2704 }
2705
2706 while (p) {
2707 c = p->next_variant;
2708 si_delete_shader(sctx, p);
2709 p = c;
2710 }
2711
2712 if (sel->main_shader_part)
2713 si_delete_shader(sctx, sel->main_shader_part);
2714 if (sel->main_shader_part_ls)
2715 si_delete_shader(sctx, sel->main_shader_part_ls);
2716 if (sel->main_shader_part_es)
2717 si_delete_shader(sctx, sel->main_shader_part_es);
2718 if (sel->gs_copy_shader)
2719 si_delete_shader(sctx, sel->gs_copy_shader);
2720
2721 util_queue_fence_destroy(&sel->ready);
2722 mtx_destroy(&sel->mutex);
2723 free(sel->tokens);
2724 ralloc_free(sel->nir);
2725 free(sel);
2726 }
2727
2728 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
2729 {
2730 struct si_context *sctx = (struct si_context *)ctx;
2731 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2732
2733 si_shader_selector_reference(sctx, &sel, NULL);
2734 }
2735
2736 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2737 struct si_shader *vs, unsigned name,
2738 unsigned index, unsigned interpolate)
2739 {
2740 struct tgsi_shader_info *vsinfo = &vs->selector->info;
2741 unsigned j, offset, ps_input_cntl = 0;
2742
2743 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2744 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
2745 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2746
2747 if (name == TGSI_SEMANTIC_PCOORD ||
2748 (name == TGSI_SEMANTIC_TEXCOORD &&
2749 sctx->sprite_coord_enable & (1 << index))) {
2750 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2751 }
2752
2753 for (j = 0; j < vsinfo->num_outputs; j++) {
2754 if (name == vsinfo->output_semantic_name[j] &&
2755 index == vsinfo->output_semantic_index[j]) {
2756 offset = vs->info.vs_output_param_offset[j];
2757
2758 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2759 /* The input is loaded from parameter memory. */
2760 ps_input_cntl |= S_028644_OFFSET(offset);
2761 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2762 if (offset == AC_EXP_PARAM_UNDEFINED) {
2763 /* This can happen with depth-only rendering. */
2764 offset = 0;
2765 } else {
2766 /* The input is a DEFAULT_VAL constant. */
2767 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2768 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2769 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2770 }
2771
2772 ps_input_cntl = S_028644_OFFSET(0x20) |
2773 S_028644_DEFAULT_VAL(offset);
2774 }
2775 break;
2776 }
2777 }
2778
2779 if (name == TGSI_SEMANTIC_PRIMID)
2780 /* PrimID is written after the last output. */
2781 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2782 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2783 /* No corresponding output found, load defaults into input.
2784 * Don't set any other bits.
2785 * (FLAT_SHADE=1 completely changes behavior) */
2786 ps_input_cntl = S_028644_OFFSET(0x20);
2787 /* D3D 9 behaviour. GL is undefined */
2788 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2789 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2790 }
2791 return ps_input_cntl;
2792 }
2793
2794 static void si_emit_spi_map(struct si_context *sctx)
2795 {
2796 struct si_shader *ps = sctx->ps_shader.current;
2797 struct si_shader *vs = si_get_vs_state(sctx);
2798 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2799 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2800 unsigned spi_ps_input_cntl[32];
2801
2802 if (!ps || !ps->selector->info.num_inputs)
2803 return;
2804
2805 num_interp = si_get_ps_num_interp(ps);
2806 assert(num_interp > 0);
2807
2808 for (i = 0; i < psinfo->num_inputs; i++) {
2809 unsigned name = psinfo->input_semantic_name[i];
2810 unsigned index = psinfo->input_semantic_index[i];
2811 unsigned interpolate = psinfo->input_interpolate[i];
2812
2813 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
2814 index, interpolate);
2815
2816 if (name == TGSI_SEMANTIC_COLOR) {
2817 assert(index < ARRAY_SIZE(bcol_interp));
2818 bcol_interp[index] = interpolate;
2819 }
2820 }
2821
2822 if (ps->key.part.ps.prolog.color_two_side) {
2823 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2824
2825 for (i = 0; i < 2; i++) {
2826 if (!(psinfo->colors_read & (0xf << (i * 4))))
2827 continue;
2828
2829 spi_ps_input_cntl[num_written++] =
2830 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
2831
2832 }
2833 }
2834 assert(num_interp == num_written);
2835
2836 /* R_028644_SPI_PS_INPUT_CNTL_0 */
2837 /* Dota 2: Only ~16% of SPI map updates set different values. */
2838 /* Talos: Only ~9% of SPI map updates set different values. */
2839 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
2840 spi_ps_input_cntl,
2841 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
2842 }
2843
2844 /**
2845 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2846 */
2847 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2848 {
2849 if (sctx->init_config_has_vgt_flush)
2850 return;
2851
2852 /* Done by Vulkan before VGT_FLUSH. */
2853 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2854 si_pm4_cmd_add(sctx->init_config,
2855 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2856 si_pm4_cmd_end(sctx->init_config, false);
2857
2858 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2859 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2860 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2861 si_pm4_cmd_end(sctx->init_config, false);
2862 sctx->init_config_has_vgt_flush = true;
2863 }
2864
2865 /* Initialize state related to ESGS / GSVS ring buffers */
2866 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2867 {
2868 struct si_shader_selector *es =
2869 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2870 struct si_shader_selector *gs = sctx->gs_shader.cso;
2871 struct si_pm4_state *pm4;
2872
2873 /* Chip constants. */
2874 unsigned num_se = sctx->screen->info.max_se;
2875 unsigned wave_size = 64;
2876 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2877 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2878 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2879 */
2880 unsigned gs_vertex_reuse = (sctx->chip_class >= VI ? 32 : 16) * num_se;
2881 unsigned alignment = 256 * num_se;
2882 /* The maximum size is 63.999 MB per SE. */
2883 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2884
2885 /* Calculate the minimum size. */
2886 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2887 wave_size, alignment);
2888
2889 /* These are recommended sizes, not minimum sizes. */
2890 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2891 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2892 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2893 gs->max_gsvs_emit_size;
2894
2895 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2896 esgs_ring_size = align(esgs_ring_size, alignment);
2897 gsvs_ring_size = align(gsvs_ring_size, alignment);
2898
2899 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2900 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2901
2902 /* Some rings don't have to be allocated if shaders don't use them.
2903 * (e.g. no varyings between ES and GS or GS and VS)
2904 *
2905 * GFX9 doesn't have the ESGS ring.
2906 */
2907 bool update_esgs = sctx->chip_class <= VI &&
2908 esgs_ring_size &&
2909 (!sctx->esgs_ring ||
2910 sctx->esgs_ring->width0 < esgs_ring_size);
2911 bool update_gsvs = gsvs_ring_size &&
2912 (!sctx->gsvs_ring ||
2913 sctx->gsvs_ring->width0 < gsvs_ring_size);
2914
2915 if (!update_esgs && !update_gsvs)
2916 return true;
2917
2918 if (update_esgs) {
2919 pipe_resource_reference(&sctx->esgs_ring, NULL);
2920 sctx->esgs_ring =
2921 pipe_aligned_buffer_create(sctx->b.screen,
2922 SI_RESOURCE_FLAG_UNMAPPABLE,
2923 PIPE_USAGE_DEFAULT,
2924 esgs_ring_size, alignment);
2925 if (!sctx->esgs_ring)
2926 return false;
2927 }
2928
2929 if (update_gsvs) {
2930 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2931 sctx->gsvs_ring =
2932 pipe_aligned_buffer_create(sctx->b.screen,
2933 SI_RESOURCE_FLAG_UNMAPPABLE,
2934 PIPE_USAGE_DEFAULT,
2935 gsvs_ring_size, alignment);
2936 if (!sctx->gsvs_ring)
2937 return false;
2938 }
2939
2940 /* Create the "init_config_gs_rings" state. */
2941 pm4 = CALLOC_STRUCT(si_pm4_state);
2942 if (!pm4)
2943 return false;
2944
2945 if (sctx->chip_class >= CIK) {
2946 if (sctx->esgs_ring) {
2947 assert(sctx->chip_class <= VI);
2948 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2949 sctx->esgs_ring->width0 / 256);
2950 }
2951 if (sctx->gsvs_ring)
2952 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2953 sctx->gsvs_ring->width0 / 256);
2954 } else {
2955 if (sctx->esgs_ring)
2956 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2957 sctx->esgs_ring->width0 / 256);
2958 if (sctx->gsvs_ring)
2959 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2960 sctx->gsvs_ring->width0 / 256);
2961 }
2962
2963 /* Set the state. */
2964 if (sctx->init_config_gs_rings)
2965 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2966 sctx->init_config_gs_rings = pm4;
2967
2968 if (!sctx->init_config_has_vgt_flush) {
2969 si_init_config_add_vgt_flush(sctx);
2970 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2971 }
2972
2973 /* Flush the context to re-emit both init_config states. */
2974 sctx->initial_gfx_cs_size = 0; /* force flush */
2975 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
2976
2977 /* Set ring bindings. */
2978 if (sctx->esgs_ring) {
2979 assert(sctx->chip_class <= VI);
2980 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
2981 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2982 true, true, 4, 64, 0);
2983 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
2984 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2985 false, false, 0, 0, 0);
2986 }
2987 if (sctx->gsvs_ring) {
2988 si_set_ring_buffer(sctx, SI_RING_GSVS,
2989 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2990 false, false, 0, 0, 0);
2991 }
2992
2993 return true;
2994 }
2995
2996 static void si_shader_lock(struct si_shader *shader)
2997 {
2998 mtx_lock(&shader->selector->mutex);
2999 if (shader->previous_stage_sel) {
3000 assert(shader->previous_stage_sel != shader->selector);
3001 mtx_lock(&shader->previous_stage_sel->mutex);
3002 }
3003 }
3004
3005 static void si_shader_unlock(struct si_shader *shader)
3006 {
3007 if (shader->previous_stage_sel)
3008 mtx_unlock(&shader->previous_stage_sel->mutex);
3009 mtx_unlock(&shader->selector->mutex);
3010 }
3011
3012 /**
3013 * @returns 1 if \p sel has been updated to use a new scratch buffer
3014 * 0 if not
3015 * < 0 if there was a failure
3016 */
3017 static int si_update_scratch_buffer(struct si_context *sctx,
3018 struct si_shader *shader)
3019 {
3020 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3021 int r;
3022
3023 if (!shader)
3024 return 0;
3025
3026 /* This shader doesn't need a scratch buffer */
3027 if (shader->config.scratch_bytes_per_wave == 0)
3028 return 0;
3029
3030 /* Prevent race conditions when updating:
3031 * - si_shader::scratch_bo
3032 * - si_shader::binary::code
3033 * - si_shader::previous_stage::binary::code.
3034 */
3035 si_shader_lock(shader);
3036
3037 /* This shader is already configured to use the current
3038 * scratch buffer. */
3039 if (shader->scratch_bo == sctx->scratch_buffer) {
3040 si_shader_unlock(shader);
3041 return 0;
3042 }
3043
3044 assert(sctx->scratch_buffer);
3045
3046 if (shader->previous_stage)
3047 si_shader_apply_scratch_relocs(shader->previous_stage, scratch_va);
3048
3049 si_shader_apply_scratch_relocs(shader, scratch_va);
3050
3051 /* Replace the shader bo with a new bo that has the relocs applied. */
3052 r = si_shader_binary_upload(sctx->screen, shader);
3053 if (r) {
3054 si_shader_unlock(shader);
3055 return r;
3056 }
3057
3058 /* Update the shader state to use the new shader bo. */
3059 si_shader_init_pm4_state(sctx->screen, shader);
3060
3061 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3062
3063 si_shader_unlock(shader);
3064 return 1;
3065 }
3066
3067 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3068 {
3069 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3070 }
3071
3072 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3073 {
3074 return shader ? shader->config.scratch_bytes_per_wave : 0;
3075 }
3076
3077 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3078 {
3079 if (!sctx->tes_shader.cso)
3080 return NULL; /* tessellation disabled */
3081
3082 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3083 sctx->fixed_func_tcs_shader.current;
3084 }
3085
3086 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3087 {
3088 unsigned bytes = 0;
3089
3090 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3091 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3092 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3093 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3094
3095 if (sctx->tes_shader.cso) {
3096 struct si_shader *tcs = si_get_tcs_current(sctx);
3097
3098 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3099 }
3100 return bytes;
3101 }
3102
3103 static bool si_update_scratch_relocs(struct si_context *sctx)
3104 {
3105 struct si_shader *tcs = si_get_tcs_current(sctx);
3106 int r;
3107
3108 /* Update the shaders, so that they are using the latest scratch.
3109 * The scratch buffer may have been changed since these shaders were
3110 * last used, so we still need to try to update them, even if they
3111 * require scratch buffers smaller than the current size.
3112 */
3113 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3114 if (r < 0)
3115 return false;
3116 if (r == 1)
3117 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3118
3119 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3120 if (r < 0)
3121 return false;
3122 if (r == 1)
3123 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3124
3125 r = si_update_scratch_buffer(sctx, tcs);
3126 if (r < 0)
3127 return false;
3128 if (r == 1)
3129 si_pm4_bind_state(sctx, hs, tcs->pm4);
3130
3131 /* VS can be bound as LS, ES, or VS. */
3132 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3133 if (r < 0)
3134 return false;
3135 if (r == 1) {
3136 if (sctx->tes_shader.current)
3137 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3138 else if (sctx->gs_shader.current)
3139 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3140 else
3141 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3142 }
3143
3144 /* TES can be bound as ES or VS. */
3145 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3146 if (r < 0)
3147 return false;
3148 if (r == 1) {
3149 if (sctx->gs_shader.current)
3150 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3151 else
3152 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3153 }
3154
3155 return true;
3156 }
3157
3158 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3159 {
3160 unsigned current_scratch_buffer_size =
3161 si_get_current_scratch_buffer_size(sctx);
3162 unsigned scratch_bytes_per_wave =
3163 si_get_max_scratch_bytes_per_wave(sctx);
3164 unsigned scratch_needed_size = scratch_bytes_per_wave *
3165 sctx->scratch_waves;
3166 unsigned spi_tmpring_size;
3167
3168 if (scratch_needed_size > 0) {
3169 if (scratch_needed_size > current_scratch_buffer_size) {
3170 /* Create a bigger scratch buffer */
3171 r600_resource_reference(&sctx->scratch_buffer, NULL);
3172
3173 sctx->scratch_buffer =
3174 si_aligned_buffer_create(&sctx->screen->b,
3175 SI_RESOURCE_FLAG_UNMAPPABLE,
3176 PIPE_USAGE_DEFAULT,
3177 scratch_needed_size, 256);
3178 if (!sctx->scratch_buffer)
3179 return false;
3180
3181 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3182 si_context_add_resource_size(sctx,
3183 &sctx->scratch_buffer->b.b);
3184 }
3185
3186 if (!si_update_scratch_relocs(sctx))
3187 return false;
3188 }
3189
3190 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3191 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3192 "scratch size should already be aligned correctly.");
3193
3194 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3195 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3196 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3197 sctx->spi_tmpring_size = spi_tmpring_size;
3198 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3199 }
3200 return true;
3201 }
3202
3203 static void si_init_tess_factor_ring(struct si_context *sctx)
3204 {
3205 assert(!sctx->tess_rings);
3206
3207 /* The address must be aligned to 2^19, because the shader only
3208 * receives the high 13 bits.
3209 */
3210 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3211 SI_RESOURCE_FLAG_32BIT,
3212 PIPE_USAGE_DEFAULT,
3213 sctx->screen->tess_offchip_ring_size +
3214 sctx->screen->tess_factor_ring_size,
3215 1 << 19);
3216 if (!sctx->tess_rings)
3217 return;
3218
3219 si_init_config_add_vgt_flush(sctx);
3220
3221 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_rings),
3222 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3223
3224 uint64_t factor_va = r600_resource(sctx->tess_rings)->gpu_address +
3225 sctx->screen->tess_offchip_ring_size;
3226
3227 /* Append these registers to the init config state. */
3228 if (sctx->chip_class >= CIK) {
3229 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3230 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3231 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3232 factor_va >> 8);
3233 if (sctx->chip_class >= GFX9)
3234 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3235 S_030944_BASE_HI(factor_va >> 40));
3236 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3237 sctx->screen->vgt_hs_offchip_param);
3238 } else {
3239 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3240 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3241 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3242 factor_va >> 8);
3243 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3244 sctx->screen->vgt_hs_offchip_param);
3245 }
3246
3247 /* Flush the context to re-emit the init_config state.
3248 * This is done only once in a lifetime of a context.
3249 */
3250 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3251 sctx->initial_gfx_cs_size = 0; /* force flush */
3252 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3253 }
3254
3255 static void si_update_vgt_shader_config(struct si_context *sctx)
3256 {
3257 /* Calculate the index of the config.
3258 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3259 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
3260 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
3261
3262 if (!*pm4) {
3263 uint32_t stages = 0;
3264
3265 *pm4 = CALLOC_STRUCT(si_pm4_state);
3266
3267 if (sctx->tes_shader.cso) {
3268 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3269 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3270
3271 if (sctx->gs_shader.cso)
3272 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3273 S_028B54_GS_EN(1) |
3274 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3275 else
3276 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3277 } else if (sctx->gs_shader.cso) {
3278 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3279 S_028B54_GS_EN(1) |
3280 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3281 }
3282
3283 if (sctx->chip_class >= GFX9)
3284 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3285
3286 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3287 }
3288 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3289 }
3290
3291 bool si_update_shaders(struct si_context *sctx)
3292 {
3293 struct pipe_context *ctx = (struct pipe_context*)sctx;
3294 struct si_compiler_ctx_state compiler_state;
3295 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3296 struct si_shader *old_vs = si_get_vs_state(sctx);
3297 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3298 struct si_shader *old_ps = sctx->ps_shader.current;
3299 unsigned old_spi_shader_col_format =
3300 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3301 int r;
3302
3303 compiler_state.compiler = &sctx->compiler;
3304 compiler_state.debug = sctx->debug;
3305 compiler_state.is_debug_context = sctx->is_debug;
3306
3307 /* Update stages before GS. */
3308 if (sctx->tes_shader.cso) {
3309 if (!sctx->tess_rings) {
3310 si_init_tess_factor_ring(sctx);
3311 if (!sctx->tess_rings)
3312 return false;
3313 }
3314
3315 /* VS as LS */
3316 if (sctx->chip_class <= VI) {
3317 r = si_shader_select(ctx, &sctx->vs_shader,
3318 &compiler_state);
3319 if (r)
3320 return false;
3321 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3322 }
3323
3324 if (sctx->tcs_shader.cso) {
3325 r = si_shader_select(ctx, &sctx->tcs_shader,
3326 &compiler_state);
3327 if (r)
3328 return false;
3329 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3330 } else {
3331 if (!sctx->fixed_func_tcs_shader.cso) {
3332 sctx->fixed_func_tcs_shader.cso =
3333 si_create_fixed_func_tcs(sctx);
3334 if (!sctx->fixed_func_tcs_shader.cso)
3335 return false;
3336 }
3337
3338 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3339 &compiler_state);
3340 if (r)
3341 return false;
3342 si_pm4_bind_state(sctx, hs,
3343 sctx->fixed_func_tcs_shader.current->pm4);
3344 }
3345
3346 if (sctx->gs_shader.cso) {
3347 /* TES as ES */
3348 if (sctx->chip_class <= VI) {
3349 r = si_shader_select(ctx, &sctx->tes_shader,
3350 &compiler_state);
3351 if (r)
3352 return false;
3353 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3354 }
3355 } else {
3356 /* TES as VS */
3357 r = si_shader_select(ctx, &sctx->tes_shader,
3358 &compiler_state);
3359 if (r)
3360 return false;
3361 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3362 }
3363 } else if (sctx->gs_shader.cso) {
3364 if (sctx->chip_class <= VI) {
3365 /* VS as ES */
3366 r = si_shader_select(ctx, &sctx->vs_shader,
3367 &compiler_state);
3368 if (r)
3369 return false;
3370 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3371
3372 si_pm4_bind_state(sctx, ls, NULL);
3373 si_pm4_bind_state(sctx, hs, NULL);
3374 }
3375 } else {
3376 /* VS as VS */
3377 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
3378 if (r)
3379 return false;
3380 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3381 si_pm4_bind_state(sctx, ls, NULL);
3382 si_pm4_bind_state(sctx, hs, NULL);
3383 }
3384
3385 /* Update GS. */
3386 if (sctx->gs_shader.cso) {
3387 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
3388 if (r)
3389 return false;
3390 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3391 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3392
3393 if (!si_update_gs_ring_buffers(sctx))
3394 return false;
3395 } else {
3396 si_pm4_bind_state(sctx, gs, NULL);
3397 if (sctx->chip_class <= VI)
3398 si_pm4_bind_state(sctx, es, NULL);
3399 }
3400
3401 si_update_vgt_shader_config(sctx);
3402
3403 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3404 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3405
3406 if (sctx->ps_shader.cso) {
3407 unsigned db_shader_control;
3408
3409 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
3410 if (r)
3411 return false;
3412 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3413
3414 db_shader_control =
3415 sctx->ps_shader.cso->db_shader_control |
3416 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3417
3418 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3419 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3420 sctx->flatshade != rs->flatshade) {
3421 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3422 sctx->flatshade = rs->flatshade;
3423 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3424 }
3425
3426 if (sctx->screen->rbplus_allowed &&
3427 si_pm4_state_changed(sctx, ps) &&
3428 (!old_ps ||
3429 old_spi_shader_col_format !=
3430 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3431 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3432
3433 if (sctx->ps_db_shader_control != db_shader_control) {
3434 sctx->ps_db_shader_control = db_shader_control;
3435 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3436 if (sctx->screen->dpbb_allowed)
3437 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3438 }
3439
3440 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3441 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3442 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3443
3444 if (sctx->chip_class == SI)
3445 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3446
3447 if (sctx->framebuffer.nr_samples <= 1)
3448 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3449 }
3450 }
3451
3452 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3453 si_pm4_state_enabled_and_changed(sctx, hs) ||
3454 si_pm4_state_enabled_and_changed(sctx, es) ||
3455 si_pm4_state_enabled_and_changed(sctx, gs) ||
3456 si_pm4_state_enabled_and_changed(sctx, vs) ||
3457 si_pm4_state_enabled_and_changed(sctx, ps)) {
3458 if (!si_update_spi_tmpring_size(sctx))
3459 return false;
3460 }
3461
3462 if (sctx->chip_class >= CIK) {
3463 if (si_pm4_state_enabled_and_changed(sctx, ls))
3464 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3465 else if (!sctx->queued.named.ls)
3466 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3467
3468 if (si_pm4_state_enabled_and_changed(sctx, hs))
3469 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3470 else if (!sctx->queued.named.hs)
3471 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3472
3473 if (si_pm4_state_enabled_and_changed(sctx, es))
3474 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3475 else if (!sctx->queued.named.es)
3476 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3477
3478 if (si_pm4_state_enabled_and_changed(sctx, gs))
3479 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3480 else if (!sctx->queued.named.gs)
3481 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3482
3483 if (si_pm4_state_enabled_and_changed(sctx, vs))
3484 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3485 else if (!sctx->queued.named.vs)
3486 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3487
3488 if (si_pm4_state_enabled_and_changed(sctx, ps))
3489 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3490 else if (!sctx->queued.named.ps)
3491 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3492 }
3493
3494 sctx->do_update_shaders = false;
3495 return true;
3496 }
3497
3498 static void si_emit_scratch_state(struct si_context *sctx)
3499 {
3500 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3501
3502 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3503 sctx->spi_tmpring_size);
3504
3505 if (sctx->scratch_buffer) {
3506 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3507 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3508 RADEON_PRIO_SCRATCH_BUFFER);
3509 }
3510 }
3511
3512 void si_init_shader_functions(struct si_context *sctx)
3513 {
3514 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
3515 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
3516
3517 sctx->b.create_vs_state = si_create_shader_selector;
3518 sctx->b.create_tcs_state = si_create_shader_selector;
3519 sctx->b.create_tes_state = si_create_shader_selector;
3520 sctx->b.create_gs_state = si_create_shader_selector;
3521 sctx->b.create_fs_state = si_create_shader_selector;
3522
3523 sctx->b.bind_vs_state = si_bind_vs_shader;
3524 sctx->b.bind_tcs_state = si_bind_tcs_shader;
3525 sctx->b.bind_tes_state = si_bind_tes_shader;
3526 sctx->b.bind_gs_state = si_bind_gs_shader;
3527 sctx->b.bind_fs_state = si_bind_ps_shader;
3528
3529 sctx->b.delete_vs_state = si_delete_shader_selector;
3530 sctx->b.delete_tcs_state = si_delete_shader_selector;
3531 sctx->b.delete_tes_state = si_delete_shader_selector;
3532 sctx->b.delete_gs_state = si_delete_shader_selector;
3533 sctx->b.delete_fs_state = si_delete_shader_selector;
3534 }