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radeonsi: add a driver query for shader cache hits
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_ureg.h"
34 #include "util/hash_table.h"
35 #include "util/u_hash.h"
36 #include "util/u_memory.h"
37 #include "util/u_prim.h"
38
39 /* SHADER_CACHE */
40
41 /**
42 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
43 * integer.
44 */
45 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
46 {
47 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
48 sizeof(struct tgsi_token);
49 unsigned size = 4 + tgsi_size + sizeof(sel->so);
50 char *result = (char*)MALLOC(size);
51
52 if (!result)
53 return NULL;
54
55 *((uint32_t*)result) = size;
56 memcpy(result + 4, sel->tokens, tgsi_size);
57 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
58 return result;
59 }
60
61 /** Copy "data" to "ptr" and return the next dword following copied data. */
62 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
63 {
64 /* data may be NULL if size == 0 */
65 if (size)
66 memcpy(ptr, data, size);
67 ptr += DIV_ROUND_UP(size, 4);
68 return ptr;
69 }
70
71 /** Read data from "ptr". Return the next dword following the data. */
72 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
73 {
74 memcpy(data, ptr, size);
75 ptr += DIV_ROUND_UP(size, 4);
76 return ptr;
77 }
78
79 /**
80 * Write the size as uint followed by the data. Return the next dword
81 * following the copied data.
82 */
83 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
84 {
85 *ptr++ = size;
86 return write_data(ptr, data, size);
87 }
88
89 /**
90 * Read the size as uint followed by the data. Return both via parameters.
91 * Return the next dword following the data.
92 */
93 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
94 {
95 *size = *ptr++;
96 assert(*data == NULL);
97 if (!*size)
98 return ptr;
99 *data = malloc(*size);
100 return read_data(ptr, *data, *size);
101 }
102
103 /**
104 * Return the shader binary in a buffer. The first 4 bytes contain its size
105 * as integer.
106 */
107 static void *si_get_shader_binary(struct si_shader *shader)
108 {
109 /* There is always a size of data followed by the data itself. */
110 unsigned relocs_size = shader->binary.reloc_count *
111 sizeof(shader->binary.relocs[0]);
112 unsigned disasm_size = strlen(shader->binary.disasm_string) + 1;
113 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
114 strlen(shader->binary.llvm_ir_string) + 1 : 0;
115 unsigned size =
116 4 + /* total size */
117 4 + /* CRC32 of the data below */
118 align(sizeof(shader->config), 4) +
119 align(sizeof(shader->info), 4) +
120 4 + align(shader->binary.code_size, 4) +
121 4 + align(shader->binary.rodata_size, 4) +
122 4 + align(relocs_size, 4) +
123 4 + align(disasm_size, 4) +
124 4 + align(llvm_ir_size, 4);
125 void *buffer = CALLOC(1, size);
126 uint32_t *ptr = (uint32_t*)buffer;
127
128 if (!buffer)
129 return NULL;
130
131 *ptr++ = size;
132 ptr++; /* CRC32 is calculated at the end. */
133
134 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
135 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
136 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
137 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
138 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
139 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
140 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
141 assert((char *)ptr - (char *)buffer == size);
142
143 /* Compute CRC32. */
144 ptr = (uint32_t*)buffer;
145 ptr++;
146 *ptr = util_hash_crc32(ptr + 1, size - 8);
147
148 return buffer;
149 }
150
151 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
152 {
153 uint32_t *ptr = (uint32_t*)binary;
154 uint32_t size = *ptr++;
155 uint32_t crc32 = *ptr++;
156 unsigned chunk_size;
157
158 if (util_hash_crc32(ptr, size - 8) != crc32) {
159 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
160 return false;
161 }
162
163 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
164 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
165 ptr = read_chunk(ptr, (void**)&shader->binary.code,
166 &shader->binary.code_size);
167 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
168 &shader->binary.rodata_size);
169 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
170 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
171 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
172 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
173
174 return true;
175 }
176
177 /**
178 * Insert a shader into the cache. It's assumed the shader is not in the cache.
179 * Use si_shader_cache_load_shader before calling this.
180 *
181 * Returns false on failure, in which case the tgsi_binary should be freed.
182 */
183 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
184 void *tgsi_binary,
185 struct si_shader *shader)
186 {
187 void *hw_binary;
188 struct hash_entry *entry;
189
190 entry = _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
191 if (entry)
192 return false; /* already added */
193
194 hw_binary = si_get_shader_binary(shader);
195 if (!hw_binary)
196 return false;
197
198 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
199 hw_binary) == NULL) {
200 FREE(hw_binary);
201 return false;
202 }
203
204 return true;
205 }
206
207 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
208 void *tgsi_binary,
209 struct si_shader *shader)
210 {
211 struct hash_entry *entry =
212 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
213 if (!entry)
214 return false;
215
216 if (!si_load_shader_binary(shader, entry->data))
217 return false;
218
219 p_atomic_inc(&sscreen->b.num_shader_cache_hits);
220 return true;
221 }
222
223 static uint32_t si_shader_cache_key_hash(const void *key)
224 {
225 /* The first dword is the key size. */
226 return util_hash_crc32(key, *(uint32_t*)key);
227 }
228
229 static bool si_shader_cache_key_equals(const void *a, const void *b)
230 {
231 uint32_t *keya = (uint32_t*)a;
232 uint32_t *keyb = (uint32_t*)b;
233
234 /* The first dword is the key size. */
235 if (*keya != *keyb)
236 return false;
237
238 return memcmp(keya, keyb, *keya) == 0;
239 }
240
241 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
242 {
243 FREE((void*)entry->key);
244 FREE(entry->data);
245 }
246
247 bool si_init_shader_cache(struct si_screen *sscreen)
248 {
249 pipe_mutex_init(sscreen->shader_cache_mutex);
250 sscreen->shader_cache =
251 _mesa_hash_table_create(NULL,
252 si_shader_cache_key_hash,
253 si_shader_cache_key_equals);
254 return sscreen->shader_cache != NULL;
255 }
256
257 void si_destroy_shader_cache(struct si_screen *sscreen)
258 {
259 if (sscreen->shader_cache)
260 _mesa_hash_table_destroy(sscreen->shader_cache,
261 si_destroy_shader_cache_entry);
262 pipe_mutex_destroy(sscreen->shader_cache_mutex);
263 }
264
265 /* SHADER STATES */
266
267 static void si_set_tesseval_regs(struct si_screen *sscreen,
268 struct si_shader *shader,
269 struct si_pm4_state *pm4)
270 {
271 struct tgsi_shader_info *info = &shader->selector->info;
272 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
273 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
274 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
275 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
276 unsigned type, partitioning, topology, distribution_mode;
277
278 switch (tes_prim_mode) {
279 case PIPE_PRIM_LINES:
280 type = V_028B6C_TESS_ISOLINE;
281 break;
282 case PIPE_PRIM_TRIANGLES:
283 type = V_028B6C_TESS_TRIANGLE;
284 break;
285 case PIPE_PRIM_QUADS:
286 type = V_028B6C_TESS_QUAD;
287 break;
288 default:
289 assert(0);
290 return;
291 }
292
293 switch (tes_spacing) {
294 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
295 partitioning = V_028B6C_PART_FRAC_ODD;
296 break;
297 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
298 partitioning = V_028B6C_PART_FRAC_EVEN;
299 break;
300 case PIPE_TESS_SPACING_EQUAL:
301 partitioning = V_028B6C_PART_INTEGER;
302 break;
303 default:
304 assert(0);
305 return;
306 }
307
308 if (tes_point_mode)
309 topology = V_028B6C_OUTPUT_POINT;
310 else if (tes_prim_mode == PIPE_PRIM_LINES)
311 topology = V_028B6C_OUTPUT_LINE;
312 else if (tes_vertex_order_cw)
313 /* for some reason, this must be the other way around */
314 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
315 else
316 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
317
318 if (sscreen->has_distributed_tess) {
319 if (sscreen->b.family == CHIP_FIJI ||
320 sscreen->b.family >= CHIP_POLARIS10)
321 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
322 else
323 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
324 } else
325 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
326
327 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
328 S_028B6C_TYPE(type) |
329 S_028B6C_PARTITIONING(partitioning) |
330 S_028B6C_TOPOLOGY(topology) |
331 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
332 }
333
334 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
335 {
336 if (shader->pm4)
337 si_pm4_clear_state(shader->pm4);
338 else
339 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
340
341 return shader->pm4;
342 }
343
344 static void si_shader_ls(struct si_shader *shader)
345 {
346 struct si_pm4_state *pm4;
347 unsigned vgpr_comp_cnt;
348 uint64_t va;
349
350 pm4 = si_get_shader_pm4_state(shader);
351 if (!pm4)
352 return;
353
354 va = shader->bo->gpu_address;
355 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
356
357 /* We need at least 2 components for LS.
358 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
359 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 1;
360
361 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
362 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
363
364 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
365 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
366 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
367 S_00B528_DX10_CLAMP(1) |
368 S_00B528_FLOAT_MODE(shader->config.float_mode);
369 shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_LS_NUM_USER_SGPR) |
370 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
371 }
372
373 static void si_shader_hs(struct si_shader *shader)
374 {
375 struct si_pm4_state *pm4;
376 uint64_t va;
377
378 pm4 = si_get_shader_pm4_state(shader);
379 if (!pm4)
380 return;
381
382 va = shader->bo->gpu_address;
383 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
384
385 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
386 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
387 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
388 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
389 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
390 S_00B428_DX10_CLAMP(1) |
391 S_00B428_FLOAT_MODE(shader->config.float_mode));
392 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
393 S_00B42C_USER_SGPR(SI_TCS_NUM_USER_SGPR) |
394 S_00B42C_OC_LDS_EN(1) |
395 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
396 }
397
398 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
399 {
400 struct si_pm4_state *pm4;
401 unsigned num_user_sgprs;
402 unsigned vgpr_comp_cnt;
403 uint64_t va;
404 unsigned oc_lds_en;
405
406 pm4 = si_get_shader_pm4_state(shader);
407 if (!pm4)
408 return;
409
410 va = shader->bo->gpu_address;
411 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
412
413 if (shader->selector->type == PIPE_SHADER_VERTEX) {
414 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
415 num_user_sgprs = SI_ES_NUM_USER_SGPR;
416 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
417 vgpr_comp_cnt = 3; /* all components are needed for TES */
418 num_user_sgprs = SI_TES_NUM_USER_SGPR;
419 } else
420 unreachable("invalid shader selector type");
421
422 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
423
424 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
425 shader->selector->esgs_itemsize / 4);
426 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
427 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
428 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
429 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
430 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
431 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
432 S_00B328_DX10_CLAMP(1) |
433 S_00B328_FLOAT_MODE(shader->config.float_mode));
434 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
435 S_00B32C_USER_SGPR(num_user_sgprs) |
436 S_00B32C_OC_LDS_EN(oc_lds_en) |
437 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
438
439 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
440 si_set_tesseval_regs(sscreen, shader, pm4);
441 }
442
443 /**
444 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
445 * geometry shader.
446 */
447 static uint32_t si_vgt_gs_mode(struct si_shader *shader)
448 {
449 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
450 unsigned cut_mode;
451
452 if (gs_max_vert_out <= 128) {
453 cut_mode = V_028A40_GS_CUT_128;
454 } else if (gs_max_vert_out <= 256) {
455 cut_mode = V_028A40_GS_CUT_256;
456 } else if (gs_max_vert_out <= 512) {
457 cut_mode = V_028A40_GS_CUT_512;
458 } else {
459 assert(gs_max_vert_out <= 1024);
460 cut_mode = V_028A40_GS_CUT_1024;
461 }
462
463 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
464 S_028A40_CUT_MODE(cut_mode)|
465 S_028A40_ES_WRITE_OPTIMIZE(1) |
466 S_028A40_GS_WRITE_OPTIMIZE(1);
467 }
468
469 static void si_shader_gs(struct si_shader *shader)
470 {
471 unsigned gs_vert_itemsize = shader->selector->gsvs_vertex_size;
472 unsigned gsvs_itemsize = shader->selector->max_gsvs_emit_size >> 2;
473 unsigned gs_num_invocations = shader->selector->gs_num_invocations;
474 struct si_pm4_state *pm4;
475 uint64_t va;
476 unsigned max_stream = shader->selector->max_gs_stream;
477
478 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
479 assert(gsvs_itemsize < (1 << 15));
480
481 pm4 = si_get_shader_pm4_state(shader);
482 if (!pm4)
483 return;
484
485 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(shader));
486
487 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
488 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize * ((max_stream >= 2) ? 2 : 1));
489 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize * ((max_stream >= 3) ? 3 : 1));
490
491 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize * (max_stream + 1));
492
493 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, shader->selector->gs_max_out_vertices);
494
495 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize >> 2);
496 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? gs_vert_itemsize >> 2 : 0);
497 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? gs_vert_itemsize >> 2 : 0);
498 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? gs_vert_itemsize >> 2 : 0);
499
500 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
501 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
502 S_028B90_ENABLE(gs_num_invocations > 0));
503
504 va = shader->bo->gpu_address;
505 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
506 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
507 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
508
509 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
510 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
511 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
512 S_00B228_DX10_CLAMP(1) |
513 S_00B228_FLOAT_MODE(shader->config.float_mode));
514 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
515 S_00B22C_USER_SGPR(SI_GS_NUM_USER_SGPR) |
516 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
517 }
518
519 /**
520 * Compute the state for \p shader, which will run as a vertex shader on the
521 * hardware.
522 *
523 * If \p gs is non-NULL, it points to the geometry shader for which this shader
524 * is the copy shader.
525 */
526 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
527 struct si_shader *gs)
528 {
529 struct si_pm4_state *pm4;
530 unsigned num_user_sgprs;
531 unsigned nparams, vgpr_comp_cnt;
532 uint64_t va;
533 unsigned oc_lds_en;
534 unsigned window_space =
535 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
536 bool enable_prim_id = si_vs_exports_prim_id(shader);
537
538 pm4 = si_get_shader_pm4_state(shader);
539 if (!pm4)
540 return;
541
542 /* We always write VGT_GS_MODE in the VS state, because every switch
543 * between different shader pipelines involving a different GS or no
544 * GS at all involves a switch of the VS (different GS use different
545 * copy shaders). On the other hand, when the API switches from a GS to
546 * no GS and then back to the same GS used originally, the GS state is
547 * not sent again.
548 */
549 if (!gs) {
550 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
551 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
552 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
553 } else {
554 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
555 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
556 }
557
558 va = shader->bo->gpu_address;
559 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
560
561 if (gs) {
562 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
563 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
564 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
565 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
566 num_user_sgprs = SI_VS_NUM_USER_SGPR;
567 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
568 vgpr_comp_cnt = 3; /* all components are needed for TES */
569 num_user_sgprs = SI_TES_NUM_USER_SGPR;
570 } else
571 unreachable("invalid shader selector type");
572
573 /* VS is required to export at least one param. */
574 nparams = MAX2(shader->info.nr_param_exports, 1);
575 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
576 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
577
578 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
579 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
580 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
581 V_02870C_SPI_SHADER_4COMP :
582 V_02870C_SPI_SHADER_NONE) |
583 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
584 V_02870C_SPI_SHADER_4COMP :
585 V_02870C_SPI_SHADER_NONE) |
586 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
587 V_02870C_SPI_SHADER_4COMP :
588 V_02870C_SPI_SHADER_NONE));
589
590 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
591
592 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
593 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
594 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
595 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
596 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
597 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
598 S_00B128_DX10_CLAMP(1) |
599 S_00B128_FLOAT_MODE(shader->config.float_mode));
600 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
601 S_00B12C_USER_SGPR(num_user_sgprs) |
602 S_00B12C_OC_LDS_EN(oc_lds_en) |
603 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
604 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
605 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
606 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
607 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
608 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
609 if (window_space)
610 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
611 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
612 else
613 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
614 S_028818_VTX_W0_FMT(1) |
615 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
616 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
617 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
618
619 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
620 si_set_tesseval_regs(sscreen, shader, pm4);
621 }
622
623 static unsigned si_get_ps_num_interp(struct si_shader *ps)
624 {
625 struct tgsi_shader_info *info = &ps->selector->info;
626 unsigned num_colors = !!(info->colors_read & 0x0f) +
627 !!(info->colors_read & 0xf0);
628 unsigned num_interp = ps->selector->info.num_inputs +
629 (ps->key.ps.prolog.color_two_side ? num_colors : 0);
630
631 assert(num_interp <= 32);
632 return MIN2(num_interp, 32);
633 }
634
635 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
636 {
637 unsigned value = shader->key.ps.epilog.spi_shader_col_format;
638 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
639
640 /* If the i-th target format is set, all previous target formats must
641 * be non-zero to avoid hangs.
642 */
643 for (i = 0; i < num_targets; i++)
644 if (!(value & (0xf << (i * 4))))
645 value |= V_028714_SPI_SHADER_32_R << (i * 4);
646
647 return value;
648 }
649
650 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
651 {
652 unsigned i, cb_shader_mask = 0;
653
654 for (i = 0; i < 8; i++) {
655 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
656 case V_028714_SPI_SHADER_ZERO:
657 break;
658 case V_028714_SPI_SHADER_32_R:
659 cb_shader_mask |= 0x1 << (i * 4);
660 break;
661 case V_028714_SPI_SHADER_32_GR:
662 cb_shader_mask |= 0x3 << (i * 4);
663 break;
664 case V_028714_SPI_SHADER_32_AR:
665 cb_shader_mask |= 0x9 << (i * 4);
666 break;
667 case V_028714_SPI_SHADER_FP16_ABGR:
668 case V_028714_SPI_SHADER_UNORM16_ABGR:
669 case V_028714_SPI_SHADER_SNORM16_ABGR:
670 case V_028714_SPI_SHADER_UINT16_ABGR:
671 case V_028714_SPI_SHADER_SINT16_ABGR:
672 case V_028714_SPI_SHADER_32_ABGR:
673 cb_shader_mask |= 0xf << (i * 4);
674 break;
675 default:
676 assert(0);
677 }
678 }
679 return cb_shader_mask;
680 }
681
682 static void si_shader_ps(struct si_shader *shader)
683 {
684 struct tgsi_shader_info *info = &shader->selector->info;
685 struct si_pm4_state *pm4;
686 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
687 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
688 uint64_t va;
689 unsigned input_ena = shader->config.spi_ps_input_ena;
690
691 /* we need to enable at least one of them, otherwise we hang the GPU */
692 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
693 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
694 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
695 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
696 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
697 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
698 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
699 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
700 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
701 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
702 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
703 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
704 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
705 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
706
707 /* Validate interpolation optimization flags (read as implications). */
708 assert(!shader->key.ps.prolog.bc_optimize_for_persp ||
709 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
710 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
711 assert(!shader->key.ps.prolog.bc_optimize_for_linear ||
712 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
713 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
714 assert(!shader->key.ps.prolog.force_persp_center_interp ||
715 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
716 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
717 assert(!shader->key.ps.prolog.force_linear_center_interp ||
718 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
719 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
720 assert(!shader->key.ps.prolog.force_persp_sample_interp ||
721 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
722 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
723 assert(!shader->key.ps.prolog.force_linear_sample_interp ||
724 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
725 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
726
727 /* Validate cases when the optimizations are off (read as implications). */
728 assert(shader->key.ps.prolog.bc_optimize_for_persp ||
729 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
730 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
731 assert(shader->key.ps.prolog.bc_optimize_for_linear ||
732 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
733 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
734
735 pm4 = si_get_shader_pm4_state(shader);
736 if (!pm4)
737 return;
738
739 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
740 * Possible vaules:
741 * 0 -> Position = pixel center
742 * 1 -> Position = pixel centroid
743 * 2 -> Position = at sample position
744 *
745 * From GLSL 4.5 specification, section 7.1:
746 * "The variable gl_FragCoord is available as an input variable from
747 * within fragment shaders and it holds the window relative coordinates
748 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
749 * value can be for any location within the pixel, or one of the
750 * fragment samples. The use of centroid does not further restrict
751 * this value to be inside the current primitive."
752 *
753 * Meaning that centroid has no effect and we can return anything within
754 * the pixel. Thus, return the value at sample position, because that's
755 * the most accurate one shaders can get.
756 */
757 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
758
759 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
760 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
761 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
762
763 spi_shader_col_format = si_get_spi_shader_col_format(shader);
764 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
765
766 /* Ensure that some export memory is always allocated, for two reasons:
767 *
768 * 1) Correctness: The hardware ignores the EXEC mask if no export
769 * memory is allocated, so KILL and alpha test do not work correctly
770 * without this.
771 * 2) Performance: Every shader needs at least a NULL export, even when
772 * it writes no color/depth output. The NULL export instruction
773 * stalls without this setting.
774 *
775 * Don't add this to CB_SHADER_MASK.
776 */
777 if (!spi_shader_col_format &&
778 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
779 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
780
781 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
782 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
783 shader->config.spi_ps_input_addr);
784
785 /* Set interpolation controls. */
786 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
787
788 /* Set registers. */
789 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
790 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
791
792 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
793 si_get_spi_shader_z_format(info->writes_z,
794 info->writes_stencil,
795 info->writes_samplemask));
796
797 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
798 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
799
800 va = shader->bo->gpu_address;
801 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
802 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
803 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
804
805 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
806 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
807 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
808 S_00B028_DX10_CLAMP(1) |
809 S_00B028_FLOAT_MODE(shader->config.float_mode));
810 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
811 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
812 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
813 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
814 }
815
816 static void si_shader_init_pm4_state(struct si_screen *sscreen,
817 struct si_shader *shader)
818 {
819 switch (shader->selector->type) {
820 case PIPE_SHADER_VERTEX:
821 if (shader->key.vs.as_ls)
822 si_shader_ls(shader);
823 else if (shader->key.vs.as_es)
824 si_shader_es(sscreen, shader);
825 else
826 si_shader_vs(sscreen, shader, NULL);
827 break;
828 case PIPE_SHADER_TESS_CTRL:
829 si_shader_hs(shader);
830 break;
831 case PIPE_SHADER_TESS_EVAL:
832 if (shader->key.tes.as_es)
833 si_shader_es(sscreen, shader);
834 else
835 si_shader_vs(sscreen, shader, NULL);
836 break;
837 case PIPE_SHADER_GEOMETRY:
838 si_shader_gs(shader);
839 si_shader_vs(sscreen, shader->gs_copy_shader, shader);
840 break;
841 case PIPE_SHADER_FRAGMENT:
842 si_shader_ps(shader);
843 break;
844 default:
845 assert(0);
846 }
847 }
848
849 static unsigned si_get_alpha_test_func(struct si_context *sctx)
850 {
851 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
852 if (sctx->queued.named.dsa)
853 return sctx->queued.named.dsa->alpha_func;
854
855 return PIPE_FUNC_ALWAYS;
856 }
857
858 /* Compute the key for the hw shader variant */
859 static inline void si_shader_selector_key(struct pipe_context *ctx,
860 struct si_shader_selector *sel,
861 union si_shader_key *key)
862 {
863 struct si_context *sctx = (struct si_context *)ctx;
864 unsigned i;
865
866 memset(key, 0, sizeof(*key));
867
868 switch (sel->type) {
869 case PIPE_SHADER_VERTEX:
870 if (sctx->vertex_elements) {
871 unsigned count = MIN2(sel->info.num_inputs,
872 sctx->vertex_elements->count);
873 for (i = 0; i < count; ++i)
874 key->vs.prolog.instance_divisors[i] =
875 sctx->vertex_elements->elements[i].instance_divisor;
876 }
877 if (sctx->tes_shader.cso)
878 key->vs.as_ls = 1;
879 else if (sctx->gs_shader.cso)
880 key->vs.as_es = 1;
881
882 if (!sctx->gs_shader.cso && sctx->ps_shader.cso &&
883 sctx->ps_shader.cso->info.uses_primid)
884 key->vs.epilog.export_prim_id = 1;
885 break;
886 case PIPE_SHADER_TESS_CTRL:
887 key->tcs.epilog.prim_mode =
888 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
889
890 if (sel == sctx->fixed_func_tcs_shader.cso)
891 key->tcs.epilog.inputs_to_copy = sctx->vs_shader.cso->outputs_written;
892 break;
893 case PIPE_SHADER_TESS_EVAL:
894 if (sctx->gs_shader.cso)
895 key->tes.as_es = 1;
896 else if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
897 key->tes.epilog.export_prim_id = 1;
898 break;
899 case PIPE_SHADER_GEOMETRY:
900 break;
901 case PIPE_SHADER_FRAGMENT: {
902 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
903 struct si_state_blend *blend = sctx->queued.named.blend;
904
905 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
906 sel->info.colors_written == 0x1)
907 key->ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
908
909 if (blend) {
910 /* Select the shader color format based on whether
911 * blending or alpha are needed.
912 */
913 key->ps.epilog.spi_shader_col_format =
914 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
915 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
916 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
917 sctx->framebuffer.spi_shader_col_format_blend) |
918 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
919 sctx->framebuffer.spi_shader_col_format_alpha) |
920 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
921 sctx->framebuffer.spi_shader_col_format);
922
923 /* The output for dual source blending should have
924 * the same format as the first output.
925 */
926 if (blend->dual_src_blend)
927 key->ps.epilog.spi_shader_col_format |=
928 (key->ps.epilog.spi_shader_col_format & 0xf) << 4;
929 } else
930 key->ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
931
932 /* If alpha-to-coverage is enabled, we have to export alpha
933 * even if there is no color buffer.
934 */
935 if (!(key->ps.epilog.spi_shader_col_format & 0xf) &&
936 blend && blend->alpha_to_coverage)
937 key->ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
938
939 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
940 * to the range supported by the type if a channel has less
941 * than 16 bits and the export format is 16_ABGR.
942 */
943 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII)
944 key->ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
945
946 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
947 if (!key->ps.epilog.last_cbuf) {
948 key->ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
949 key->ps.epilog.color_is_int8 &= sel->info.colors_written;
950 }
951
952 if (rs) {
953 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
954 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
955 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
956 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
957
958 key->ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
959 key->ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
960
961 if (sctx->queued.named.blend) {
962 key->ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
963 rs->multisample_enable;
964 }
965
966 key->ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
967 key->ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
968 (is_line && rs->line_smooth)) &&
969 sctx->framebuffer.nr_samples <= 1;
970 key->ps.epilog.clamp_color = rs->clamp_fragment_color;
971
972 if (rs->force_persample_interp &&
973 rs->multisample_enable &&
974 sctx->framebuffer.nr_samples > 1 &&
975 sctx->ps_iter_samples > 1) {
976 key->ps.prolog.force_persp_sample_interp =
977 sel->info.uses_persp_center ||
978 sel->info.uses_persp_centroid;
979
980 key->ps.prolog.force_linear_sample_interp =
981 sel->info.uses_linear_center ||
982 sel->info.uses_linear_centroid;
983 } else if (rs->multisample_enable &&
984 sctx->framebuffer.nr_samples > 1) {
985 key->ps.prolog.bc_optimize_for_persp =
986 sel->info.uses_persp_center &&
987 sel->info.uses_persp_centroid;
988 key->ps.prolog.bc_optimize_for_linear =
989 sel->info.uses_linear_center &&
990 sel->info.uses_linear_centroid;
991 } else {
992 /* Make sure SPI doesn't compute more than 1 pair
993 * of (i,j), which is the optimization here. */
994 key->ps.prolog.force_persp_center_interp =
995 sel->info.uses_persp_center +
996 sel->info.uses_persp_centroid +
997 sel->info.uses_persp_sample > 1;
998
999 key->ps.prolog.force_linear_center_interp =
1000 sel->info.uses_linear_center +
1001 sel->info.uses_linear_centroid +
1002 sel->info.uses_linear_sample > 1;
1003 }
1004 }
1005
1006 key->ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1007 break;
1008 }
1009 default:
1010 assert(0);
1011 }
1012 }
1013
1014 /* Select the hw shader variant depending on the current state. */
1015 static int si_shader_select_with_key(struct si_screen *sscreen,
1016 struct si_shader_ctx_state *state,
1017 union si_shader_key *key,
1018 LLVMTargetMachineRef tm,
1019 struct pipe_debug_callback *debug,
1020 bool wait,
1021 bool is_debug_context)
1022 {
1023 struct si_shader_selector *sel = state->cso;
1024 struct si_shader *current = state->current;
1025 struct si_shader *iter, *shader = NULL;
1026 int r;
1027
1028 /* Check if we don't need to change anything.
1029 * This path is also used for most shaders that don't need multiple
1030 * variants, it will cost just a computation of the key and this
1031 * test. */
1032 if (likely(current && memcmp(&current->key, key, sizeof(*key)) == 0))
1033 return 0;
1034
1035 /* This must be done before the mutex is locked, because async GS
1036 * compilation calls this function too, and therefore must enter
1037 * the mutex first.
1038 */
1039 if (wait)
1040 util_queue_job_wait(&sel->ready);
1041
1042 pipe_mutex_lock(sel->mutex);
1043
1044 /* Find the shader variant. */
1045 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1046 /* Don't check the "current" shader. We checked it above. */
1047 if (current != iter &&
1048 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1049 state->current = iter;
1050 pipe_mutex_unlock(sel->mutex);
1051 return 0;
1052 }
1053 }
1054
1055 /* Build a new shader. */
1056 shader = CALLOC_STRUCT(si_shader);
1057 if (!shader) {
1058 pipe_mutex_unlock(sel->mutex);
1059 return -ENOMEM;
1060 }
1061 shader->selector = sel;
1062 shader->key = *key;
1063
1064 r = si_shader_create(sscreen, tm, shader, debug);
1065 if (unlikely(r)) {
1066 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1067 sel->type, r);
1068 FREE(shader);
1069 pipe_mutex_unlock(sel->mutex);
1070 return r;
1071 }
1072
1073 if (is_debug_context) {
1074 FILE *f = open_memstream(&shader->shader_log,
1075 &shader->shader_log_size);
1076 if (f) {
1077 si_shader_dump(sscreen, shader, NULL, sel->type, f);
1078 fclose(f);
1079 }
1080 }
1081
1082 si_shader_init_pm4_state(sscreen, shader);
1083
1084 if (!sel->last_variant) {
1085 sel->first_variant = shader;
1086 sel->last_variant = shader;
1087 } else {
1088 sel->last_variant->next_variant = shader;
1089 sel->last_variant = shader;
1090 }
1091 state->current = shader;
1092 pipe_mutex_unlock(sel->mutex);
1093 return 0;
1094 }
1095
1096 static int si_shader_select(struct pipe_context *ctx,
1097 struct si_shader_ctx_state *state)
1098 {
1099 struct si_context *sctx = (struct si_context *)ctx;
1100 union si_shader_key key;
1101
1102 si_shader_selector_key(ctx, state->cso, &key);
1103 return si_shader_select_with_key(sctx->screen, state, &key,
1104 sctx->tm, &sctx->b.debug, true,
1105 sctx->is_debug);
1106 }
1107
1108 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1109 union si_shader_key *key)
1110 {
1111 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1112
1113 switch (info->processor) {
1114 case PIPE_SHADER_VERTEX:
1115 switch (next_shader) {
1116 case PIPE_SHADER_GEOMETRY:
1117 key->vs.as_es = 1;
1118 break;
1119 case PIPE_SHADER_TESS_CTRL:
1120 case PIPE_SHADER_TESS_EVAL:
1121 key->vs.as_ls = 1;
1122 break;
1123 }
1124 break;
1125
1126 case PIPE_SHADER_TESS_EVAL:
1127 if (next_shader == PIPE_SHADER_GEOMETRY)
1128 key->tes.as_es = 1;
1129 break;
1130 }
1131 }
1132
1133 /**
1134 * Compile the main shader part or the monolithic shader as part of
1135 * si_shader_selector initialization. Since it can be done asynchronously,
1136 * there is no way to report compile failures to applications.
1137 */
1138 void si_init_shader_selector_async(void *job, int thread_index)
1139 {
1140 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1141 struct si_screen *sscreen = sel->screen;
1142 LLVMTargetMachineRef tm;
1143 struct pipe_debug_callback *debug = &sel->debug;
1144 unsigned i;
1145
1146 if (thread_index >= 0) {
1147 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1148 tm = sscreen->tm[thread_index];
1149 if (!debug->async)
1150 debug = NULL;
1151 } else {
1152 tm = sel->tm;
1153 }
1154
1155 /* Compile the main shader part for use with a prolog and/or epilog.
1156 * If this fails, the driver will try to compile a monolithic shader
1157 * on demand.
1158 */
1159 if (sel->type != PIPE_SHADER_GEOMETRY &&
1160 !sscreen->use_monolithic_shaders) {
1161 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1162 void *tgsi_binary;
1163
1164 if (!shader) {
1165 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1166 return;
1167 }
1168
1169 shader->selector = sel;
1170 si_parse_next_shader_property(&sel->info, &shader->key);
1171
1172 tgsi_binary = si_get_tgsi_binary(sel);
1173
1174 /* Try to load the shader from the shader cache. */
1175 pipe_mutex_lock(sscreen->shader_cache_mutex);
1176
1177 if (tgsi_binary &&
1178 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1179 FREE(tgsi_binary);
1180 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1181 } else {
1182 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1183
1184 /* Compile the shader if it hasn't been loaded from the cache. */
1185 if (si_compile_tgsi_shader(sscreen, tm, shader, false,
1186 debug) != 0) {
1187 FREE(shader);
1188 FREE(tgsi_binary);
1189 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1190 return;
1191 }
1192
1193 if (tgsi_binary) {
1194 pipe_mutex_lock(sscreen->shader_cache_mutex);
1195 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary, shader))
1196 FREE(tgsi_binary);
1197 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1198 }
1199 }
1200
1201 sel->main_shader_part = shader;
1202 }
1203
1204 /* Pre-compilation. */
1205 if (sel->type == PIPE_SHADER_GEOMETRY ||
1206 sscreen->b.debug_flags & DBG_PRECOMPILE) {
1207 struct si_shader_ctx_state state = {sel};
1208 union si_shader_key key;
1209
1210 memset(&key, 0, sizeof(key));
1211 si_parse_next_shader_property(&sel->info, &key);
1212
1213 /* Set reasonable defaults, so that the shader key doesn't
1214 * cause any code to be eliminated.
1215 */
1216 switch (sel->type) {
1217 case PIPE_SHADER_TESS_CTRL:
1218 key.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1219 break;
1220 case PIPE_SHADER_FRAGMENT:
1221 key.ps.prolog.bc_optimize_for_persp =
1222 sel->info.uses_persp_center &&
1223 sel->info.uses_persp_centroid;
1224 key.ps.prolog.bc_optimize_for_linear =
1225 sel->info.uses_linear_center &&
1226 sel->info.uses_linear_centroid;
1227 key.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1228 for (i = 0; i < 8; i++)
1229 if (sel->info.colors_written & (1 << i))
1230 key.ps.epilog.spi_shader_col_format |=
1231 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1232 break;
1233 }
1234
1235 if (si_shader_select_with_key(sscreen, &state, &key, tm, debug,
1236 false, sel->is_debug_context))
1237 fprintf(stderr, "radeonsi: can't create a monolithic shader\n");
1238 }
1239 }
1240
1241 static void *si_create_shader_selector(struct pipe_context *ctx,
1242 const struct pipe_shader_state *state)
1243 {
1244 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1245 struct si_context *sctx = (struct si_context*)ctx;
1246 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
1247 int i;
1248
1249 if (!sel)
1250 return NULL;
1251
1252 sel->screen = sscreen;
1253 sel->tm = sctx->tm;
1254 sel->debug = sctx->b.debug;
1255 sel->is_debug_context = sctx->is_debug;
1256 sel->tokens = tgsi_dup_tokens(state->tokens);
1257 if (!sel->tokens) {
1258 FREE(sel);
1259 return NULL;
1260 }
1261
1262 sel->so = state->stream_output;
1263 tgsi_scan_shader(state->tokens, &sel->info);
1264 sel->type = sel->info.processor;
1265 p_atomic_inc(&sscreen->b.num_shaders_created);
1266
1267 /* Set which opcode uses which (i,j) pair. */
1268 if (sel->info.uses_persp_opcode_interp_centroid)
1269 sel->info.uses_persp_centroid = true;
1270
1271 if (sel->info.uses_linear_opcode_interp_centroid)
1272 sel->info.uses_linear_centroid = true;
1273
1274 if (sel->info.uses_persp_opcode_interp_offset ||
1275 sel->info.uses_persp_opcode_interp_sample)
1276 sel->info.uses_persp_center = true;
1277
1278 if (sel->info.uses_linear_opcode_interp_offset ||
1279 sel->info.uses_linear_opcode_interp_sample)
1280 sel->info.uses_linear_center = true;
1281
1282 switch (sel->type) {
1283 case PIPE_SHADER_GEOMETRY:
1284 sel->gs_output_prim =
1285 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
1286 sel->gs_max_out_vertices =
1287 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
1288 sel->gs_num_invocations =
1289 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
1290 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
1291 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
1292 sel->gs_max_out_vertices;
1293
1294 sel->max_gs_stream = 0;
1295 for (i = 0; i < sel->so.num_outputs; i++)
1296 sel->max_gs_stream = MAX2(sel->max_gs_stream,
1297 sel->so.output[i].stream);
1298
1299 sel->gs_input_verts_per_prim =
1300 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
1301 break;
1302
1303 case PIPE_SHADER_TESS_CTRL:
1304 /* Always reserve space for these. */
1305 sel->patch_outputs_written |=
1306 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0)) |
1307 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0));
1308 /* fall through */
1309 case PIPE_SHADER_VERTEX:
1310 case PIPE_SHADER_TESS_EVAL:
1311 for (i = 0; i < sel->info.num_outputs; i++) {
1312 unsigned name = sel->info.output_semantic_name[i];
1313 unsigned index = sel->info.output_semantic_index[i];
1314
1315 switch (name) {
1316 case TGSI_SEMANTIC_TESSINNER:
1317 case TGSI_SEMANTIC_TESSOUTER:
1318 case TGSI_SEMANTIC_PATCH:
1319 sel->patch_outputs_written |=
1320 1llu << si_shader_io_get_unique_index(name, index);
1321 break;
1322 default:
1323 sel->outputs_written |=
1324 1llu << si_shader_io_get_unique_index(name, index);
1325 }
1326 }
1327 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
1328 break;
1329
1330 case PIPE_SHADER_FRAGMENT:
1331 for (i = 0; i < 8; i++)
1332 if (sel->info.colors_written & (1 << i))
1333 sel->colors_written_4bit |= 0xf << (4 * i);
1334
1335 for (i = 0; i < sel->info.num_inputs; i++) {
1336 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
1337 int index = sel->info.input_semantic_index[i];
1338 sel->color_attr_index[index] = i;
1339 }
1340 }
1341 break;
1342 }
1343
1344 /* DB_SHADER_CONTROL */
1345 sel->db_shader_control =
1346 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
1347 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
1348 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
1349 S_02880C_KILL_ENABLE(sel->info.uses_kill);
1350
1351 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
1352 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1353 sel->db_shader_control |=
1354 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
1355 break;
1356 case TGSI_FS_DEPTH_LAYOUT_LESS:
1357 sel->db_shader_control |=
1358 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
1359 break;
1360 }
1361
1362 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
1363 *
1364 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
1365 * --|-----------|------------|------------|--------------------|-------------------|-------------
1366 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
1367 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
1368 * 2 | false | true | n/a | LateZ | 1 | 0
1369 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
1370 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
1371 *
1372 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
1373 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
1374 *
1375 * Don't use ReZ without profiling !!!
1376 *
1377 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
1378 * shaders.
1379 */
1380 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
1381 /* Cases 3, 4. */
1382 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
1383 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
1384 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
1385 } else if (sel->info.writes_memory) {
1386 /* Case 2. */
1387 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
1388 S_02880C_EXEC_ON_HIER_FAIL(1);
1389 } else {
1390 /* Case 1. */
1391 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1392 }
1393
1394 pipe_mutex_init(sel->mutex);
1395 util_queue_fence_init(&sel->ready);
1396
1397 if ((sctx->b.debug.debug_message && !sctx->b.debug.async) ||
1398 sctx->is_debug ||
1399 r600_can_dump_shader(&sscreen->b, sel->info.processor) ||
1400 !util_queue_is_initialized(&sscreen->shader_compiler_queue))
1401 si_init_shader_selector_async(sel, -1);
1402 else
1403 util_queue_add_job(&sscreen->shader_compiler_queue, sel,
1404 &sel->ready, si_init_shader_selector_async,
1405 NULL);
1406
1407 return sel;
1408 }
1409
1410 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1411 {
1412 struct si_context *sctx = (struct si_context *)ctx;
1413 struct si_shader_selector *sel = state;
1414
1415 if (sctx->vs_shader.cso == sel)
1416 return;
1417
1418 sctx->vs_shader.cso = sel;
1419 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
1420 sctx->do_update_shaders = true;
1421 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1422 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1423 }
1424
1425 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
1426 {
1427 struct si_context *sctx = (struct si_context *)ctx;
1428 struct si_shader_selector *sel = state;
1429 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
1430
1431 if (sctx->gs_shader.cso == sel)
1432 return;
1433
1434 sctx->gs_shader.cso = sel;
1435 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
1436 sctx->do_update_shaders = true;
1437 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1438 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1439
1440 if (enable_changed)
1441 si_shader_change_notify(sctx);
1442 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1443 }
1444
1445 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
1446 {
1447 struct si_context *sctx = (struct si_context *)ctx;
1448 struct si_shader_selector *sel = state;
1449 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
1450
1451 if (sctx->tcs_shader.cso == sel)
1452 return;
1453
1454 sctx->tcs_shader.cso = sel;
1455 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
1456 sctx->do_update_shaders = true;
1457
1458 if (enable_changed)
1459 sctx->last_tcs = NULL; /* invalidate derived tess state */
1460 }
1461
1462 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
1463 {
1464 struct si_context *sctx = (struct si_context *)ctx;
1465 struct si_shader_selector *sel = state;
1466 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
1467
1468 if (sctx->tes_shader.cso == sel)
1469 return;
1470
1471 sctx->tes_shader.cso = sel;
1472 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
1473 sctx->do_update_shaders = true;
1474 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1475 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1476
1477 if (enable_changed) {
1478 si_shader_change_notify(sctx);
1479 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
1480 }
1481 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1482 }
1483
1484 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1485 {
1486 struct si_context *sctx = (struct si_context *)ctx;
1487 struct si_shader_selector *sel = state;
1488
1489 /* skip if supplied shader is one already in use */
1490 if (sctx->ps_shader.cso == sel)
1491 return;
1492
1493 sctx->ps_shader.cso = sel;
1494 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
1495 sctx->do_update_shaders = true;
1496 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
1497 }
1498
1499 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
1500 {
1501 if (shader->pm4) {
1502 switch (shader->selector->type) {
1503 case PIPE_SHADER_VERTEX:
1504 if (shader->key.vs.as_ls)
1505 si_pm4_delete_state(sctx, ls, shader->pm4);
1506 else if (shader->key.vs.as_es)
1507 si_pm4_delete_state(sctx, es, shader->pm4);
1508 else
1509 si_pm4_delete_state(sctx, vs, shader->pm4);
1510 break;
1511 case PIPE_SHADER_TESS_CTRL:
1512 si_pm4_delete_state(sctx, hs, shader->pm4);
1513 break;
1514 case PIPE_SHADER_TESS_EVAL:
1515 if (shader->key.tes.as_es)
1516 si_pm4_delete_state(sctx, es, shader->pm4);
1517 else
1518 si_pm4_delete_state(sctx, vs, shader->pm4);
1519 break;
1520 case PIPE_SHADER_GEOMETRY:
1521 si_pm4_delete_state(sctx, gs, shader->pm4);
1522 si_pm4_delete_state(sctx, vs, shader->gs_copy_shader->pm4);
1523 break;
1524 case PIPE_SHADER_FRAGMENT:
1525 si_pm4_delete_state(sctx, ps, shader->pm4);
1526 break;
1527 }
1528 }
1529
1530 si_shader_destroy(shader);
1531 free(shader);
1532 }
1533
1534 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
1535 {
1536 struct si_context *sctx = (struct si_context *)ctx;
1537 struct si_shader_selector *sel = (struct si_shader_selector *)state;
1538 struct si_shader *p = sel->first_variant, *c;
1539 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
1540 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
1541 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
1542 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
1543 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
1544 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
1545 };
1546
1547 util_queue_job_wait(&sel->ready);
1548
1549 if (current_shader[sel->type]->cso == sel) {
1550 current_shader[sel->type]->cso = NULL;
1551 current_shader[sel->type]->current = NULL;
1552 }
1553
1554 while (p) {
1555 c = p->next_variant;
1556 si_delete_shader(sctx, p);
1557 p = c;
1558 }
1559
1560 if (sel->main_shader_part)
1561 si_delete_shader(sctx, sel->main_shader_part);
1562
1563 util_queue_fence_destroy(&sel->ready);
1564 pipe_mutex_destroy(sel->mutex);
1565 free(sel->tokens);
1566 free(sel);
1567 }
1568
1569 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
1570 struct si_shader *vs, unsigned name,
1571 unsigned index, unsigned interpolate)
1572 {
1573 struct tgsi_shader_info *vsinfo = &vs->selector->info;
1574 unsigned j, offset, ps_input_cntl = 0;
1575
1576 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
1577 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
1578 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1579
1580 if (name == TGSI_SEMANTIC_PCOORD ||
1581 (name == TGSI_SEMANTIC_TEXCOORD &&
1582 sctx->sprite_coord_enable & (1 << index))) {
1583 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
1584 }
1585
1586 for (j = 0; j < vsinfo->num_outputs; j++) {
1587 if (name == vsinfo->output_semantic_name[j] &&
1588 index == vsinfo->output_semantic_index[j]) {
1589 offset = vs->info.vs_output_param_offset[j];
1590
1591 if (offset <= EXP_PARAM_OFFSET_31) {
1592 /* The input is loaded from parameter memory. */
1593 ps_input_cntl |= S_028644_OFFSET(offset);
1594 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
1595 /* The input is a DEFAULT_VAL constant. */
1596 assert(offset >= EXP_PARAM_DEFAULT_VAL_0000 &&
1597 offset <= EXP_PARAM_DEFAULT_VAL_1111);
1598
1599 offset -= EXP_PARAM_DEFAULT_VAL_0000;
1600 ps_input_cntl = S_028644_OFFSET(0x20) |
1601 S_028644_DEFAULT_VAL(offset);
1602 }
1603 break;
1604 }
1605 }
1606
1607 if (name == TGSI_SEMANTIC_PRIMID)
1608 /* PrimID is written after the last output. */
1609 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
1610 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
1611 /* No corresponding output found, load defaults into input.
1612 * Don't set any other bits.
1613 * (FLAT_SHADE=1 completely changes behavior) */
1614 ps_input_cntl = S_028644_OFFSET(0x20);
1615 /* D3D 9 behaviour. GL is undefined */
1616 if (name == TGSI_SEMANTIC_COLOR && index == 0)
1617 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
1618 }
1619 return ps_input_cntl;
1620 }
1621
1622 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
1623 {
1624 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1625 struct si_shader *ps = sctx->ps_shader.current;
1626 struct si_shader *vs = si_get_vs_state(sctx);
1627 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
1628 unsigned i, num_interp, num_written = 0, bcol_interp[2];
1629
1630 if (!ps || !ps->selector->info.num_inputs)
1631 return;
1632
1633 num_interp = si_get_ps_num_interp(ps);
1634 assert(num_interp > 0);
1635 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
1636
1637 for (i = 0; i < psinfo->num_inputs; i++) {
1638 unsigned name = psinfo->input_semantic_name[i];
1639 unsigned index = psinfo->input_semantic_index[i];
1640 unsigned interpolate = psinfo->input_interpolate[i];
1641
1642 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
1643 interpolate));
1644 num_written++;
1645
1646 if (name == TGSI_SEMANTIC_COLOR) {
1647 assert(index < ARRAY_SIZE(bcol_interp));
1648 bcol_interp[index] = interpolate;
1649 }
1650 }
1651
1652 if (ps->key.ps.prolog.color_two_side) {
1653 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
1654
1655 for (i = 0; i < 2; i++) {
1656 if (!(psinfo->colors_read & (0xf << (i * 4))))
1657 continue;
1658
1659 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
1660 i, bcol_interp[i]));
1661 num_written++;
1662 }
1663 }
1664 assert(num_interp == num_written);
1665 }
1666
1667 /**
1668 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1669 */
1670 static void si_init_config_add_vgt_flush(struct si_context *sctx)
1671 {
1672 if (sctx->init_config_has_vgt_flush)
1673 return;
1674
1675 /* Done by Vulkan before VGT_FLUSH. */
1676 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
1677 si_pm4_cmd_add(sctx->init_config,
1678 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1679 si_pm4_cmd_end(sctx->init_config, false);
1680
1681 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
1682 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
1683 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1684 si_pm4_cmd_end(sctx->init_config, false);
1685 sctx->init_config_has_vgt_flush = true;
1686 }
1687
1688 /* Initialize state related to ESGS / GSVS ring buffers */
1689 static bool si_update_gs_ring_buffers(struct si_context *sctx)
1690 {
1691 struct si_shader_selector *es =
1692 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
1693 struct si_shader_selector *gs = sctx->gs_shader.cso;
1694 struct si_pm4_state *pm4;
1695
1696 /* Chip constants. */
1697 unsigned num_se = sctx->screen->b.info.max_se;
1698 unsigned wave_size = 64;
1699 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1700 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1701 unsigned alignment = 256 * num_se;
1702 /* The maximum size is 63.999 MB per SE. */
1703 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1704
1705 /* Calculate the minimum size. */
1706 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
1707 wave_size, alignment);
1708
1709 /* These are recommended sizes, not minimum sizes. */
1710 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1711 es->esgs_itemsize * gs->gs_input_verts_per_prim;
1712 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1713 gs->max_gsvs_emit_size * (gs->max_gs_stream + 1);
1714
1715 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1716 esgs_ring_size = align(esgs_ring_size, alignment);
1717 gsvs_ring_size = align(gsvs_ring_size, alignment);
1718
1719 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1720 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1721
1722 /* Some rings don't have to be allocated if shaders don't use them.
1723 * (e.g. no varyings between ES and GS or GS and VS)
1724 */
1725 bool update_esgs = esgs_ring_size &&
1726 (!sctx->esgs_ring ||
1727 sctx->esgs_ring->width0 < esgs_ring_size);
1728 bool update_gsvs = gsvs_ring_size &&
1729 (!sctx->gsvs_ring ||
1730 sctx->gsvs_ring->width0 < gsvs_ring_size);
1731
1732 if (!update_esgs && !update_gsvs)
1733 return true;
1734
1735 if (update_esgs) {
1736 pipe_resource_reference(&sctx->esgs_ring, NULL);
1737 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, 0,
1738 PIPE_USAGE_DEFAULT,
1739 esgs_ring_size);
1740 if (!sctx->esgs_ring)
1741 return false;
1742 }
1743
1744 if (update_gsvs) {
1745 pipe_resource_reference(&sctx->gsvs_ring, NULL);
1746 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, 0,
1747 PIPE_USAGE_DEFAULT,
1748 gsvs_ring_size);
1749 if (!sctx->gsvs_ring)
1750 return false;
1751 }
1752
1753 /* Create the "init_config_gs_rings" state. */
1754 pm4 = CALLOC_STRUCT(si_pm4_state);
1755 if (!pm4)
1756 return false;
1757
1758 if (sctx->b.chip_class >= CIK) {
1759 if (sctx->esgs_ring)
1760 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
1761 sctx->esgs_ring->width0 / 256);
1762 if (sctx->gsvs_ring)
1763 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
1764 sctx->gsvs_ring->width0 / 256);
1765 } else {
1766 if (sctx->esgs_ring)
1767 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
1768 sctx->esgs_ring->width0 / 256);
1769 if (sctx->gsvs_ring)
1770 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
1771 sctx->gsvs_ring->width0 / 256);
1772 }
1773
1774 /* Set the state. */
1775 if (sctx->init_config_gs_rings)
1776 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
1777 sctx->init_config_gs_rings = pm4;
1778
1779 if (!sctx->init_config_has_vgt_flush) {
1780 si_init_config_add_vgt_flush(sctx);
1781 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1782 }
1783
1784 /* Flush the context to re-emit both init_config states. */
1785 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1786 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1787
1788 /* Set ring bindings. */
1789 if (sctx->esgs_ring) {
1790 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
1791 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1792 true, true, 4, 64, 0);
1793 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
1794 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1795 false, false, 0, 0, 0);
1796 }
1797 if (sctx->gsvs_ring)
1798 si_set_ring_buffer(&sctx->b.b, SI_VS_RING_GSVS,
1799 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
1800 false, false, 0, 0, 0);
1801 return true;
1802 }
1803
1804 static void si_update_gsvs_ring_bindings(struct si_context *sctx)
1805 {
1806 unsigned gsvs_itemsize = sctx->gs_shader.cso->max_gsvs_emit_size;
1807 uint64_t offset;
1808
1809 if (!sctx->gsvs_ring || gsvs_itemsize == sctx->last_gsvs_itemsize)
1810 return;
1811
1812 sctx->last_gsvs_itemsize = gsvs_itemsize;
1813
1814 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS0,
1815 sctx->gsvs_ring, gsvs_itemsize,
1816 64, true, true, 4, 16, 0);
1817
1818 offset = gsvs_itemsize * 64;
1819 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS1,
1820 sctx->gsvs_ring, gsvs_itemsize,
1821 64, true, true, 4, 16, offset);
1822
1823 offset = (gsvs_itemsize * 2) * 64;
1824 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS2,
1825 sctx->gsvs_ring, gsvs_itemsize,
1826 64, true, true, 4, 16, offset);
1827
1828 offset = (gsvs_itemsize * 3) * 64;
1829 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS3,
1830 sctx->gsvs_ring, gsvs_itemsize,
1831 64, true, true, 4, 16, offset);
1832 }
1833
1834 /**
1835 * @returns 1 if \p sel has been updated to use a new scratch buffer
1836 * 0 if not
1837 * < 0 if there was a failure
1838 */
1839 static int si_update_scratch_buffer(struct si_context *sctx,
1840 struct si_shader *shader)
1841 {
1842 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
1843 int r;
1844
1845 if (!shader)
1846 return 0;
1847
1848 /* This shader doesn't need a scratch buffer */
1849 if (shader->config.scratch_bytes_per_wave == 0)
1850 return 0;
1851
1852 /* This shader is already configured to use the current
1853 * scratch buffer. */
1854 if (shader->scratch_bo == sctx->scratch_buffer)
1855 return 0;
1856
1857 assert(sctx->scratch_buffer);
1858
1859 si_shader_apply_scratch_relocs(sctx, shader, &shader->config, scratch_va);
1860
1861 /* Replace the shader bo with a new bo that has the relocs applied. */
1862 r = si_shader_binary_upload(sctx->screen, shader);
1863 if (r)
1864 return r;
1865
1866 /* Update the shader state to use the new shader bo. */
1867 si_shader_init_pm4_state(sctx->screen, shader);
1868
1869 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
1870
1871 return 1;
1872 }
1873
1874 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
1875 {
1876 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
1877 }
1878
1879 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
1880 {
1881 return shader ? shader->config.scratch_bytes_per_wave : 0;
1882 }
1883
1884 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
1885 {
1886 unsigned bytes = 0;
1887
1888 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
1889 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
1890 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
1891 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
1892 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
1893 return bytes;
1894 }
1895
1896 static bool si_update_spi_tmpring_size(struct si_context *sctx)
1897 {
1898 unsigned current_scratch_buffer_size =
1899 si_get_current_scratch_buffer_size(sctx);
1900 unsigned scratch_bytes_per_wave =
1901 si_get_max_scratch_bytes_per_wave(sctx);
1902 unsigned scratch_needed_size = scratch_bytes_per_wave *
1903 sctx->scratch_waves;
1904 unsigned spi_tmpring_size;
1905 int r;
1906
1907 if (scratch_needed_size > 0) {
1908 if (scratch_needed_size > current_scratch_buffer_size) {
1909 /* Create a bigger scratch buffer */
1910 r600_resource_reference(&sctx->scratch_buffer, NULL);
1911
1912 sctx->scratch_buffer = (struct r600_resource*)
1913 pipe_buffer_create(&sctx->screen->b.b, 0,
1914 PIPE_USAGE_DEFAULT, scratch_needed_size);
1915 if (!sctx->scratch_buffer)
1916 return false;
1917 sctx->emit_scratch_reloc = true;
1918 }
1919
1920 /* Update the shaders, so they are using the latest scratch. The
1921 * scratch buffer may have been changed since these shaders were
1922 * last used, so we still need to try to update them, even if
1923 * they require scratch buffers smaller than the current size.
1924 */
1925 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
1926 if (r < 0)
1927 return false;
1928 if (r == 1)
1929 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1930
1931 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
1932 if (r < 0)
1933 return false;
1934 if (r == 1)
1935 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1936
1937 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
1938 if (r < 0)
1939 return false;
1940 if (r == 1)
1941 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1942
1943 /* VS can be bound as LS, ES, or VS. */
1944 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
1945 if (r < 0)
1946 return false;
1947 if (r == 1) {
1948 if (sctx->tes_shader.current)
1949 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1950 else if (sctx->gs_shader.current)
1951 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1952 else
1953 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1954 }
1955
1956 /* TES can be bound as ES or VS. */
1957 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
1958 if (r < 0)
1959 return false;
1960 if (r == 1) {
1961 if (sctx->gs_shader.current)
1962 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1963 else
1964 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1965 }
1966 }
1967
1968 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1969 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
1970 "scratch size should already be aligned correctly.");
1971
1972 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
1973 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
1974 if (spi_tmpring_size != sctx->spi_tmpring_size) {
1975 sctx->spi_tmpring_size = spi_tmpring_size;
1976 sctx->emit_scratch_reloc = true;
1977 }
1978 return true;
1979 }
1980
1981 static void si_init_tess_factor_ring(struct si_context *sctx)
1982 {
1983 bool double_offchip_buffers = sctx->b.chip_class >= CIK;
1984 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1985 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1986 sctx->screen->b.info.max_se;
1987 unsigned offchip_granularity;
1988
1989 switch (sctx->screen->tess_offchip_block_dw_size) {
1990 default:
1991 assert(0);
1992 /* fall through */
1993 case 8192:
1994 offchip_granularity = V_03093C_X_8K_DWORDS;
1995 break;
1996 case 4096:
1997 offchip_granularity = V_03093C_X_4K_DWORDS;
1998 break;
1999 }
2000
2001 switch (sctx->b.chip_class) {
2002 case SI:
2003 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2004 break;
2005 case CIK:
2006 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2007 break;
2008 case VI:
2009 default:
2010 max_offchip_buffers = MIN2(max_offchip_buffers, 512);
2011 break;
2012 }
2013
2014 assert(!sctx->tf_ring);
2015 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, 0,
2016 PIPE_USAGE_DEFAULT,
2017 32768 * sctx->screen->b.info.max_se);
2018 if (!sctx->tf_ring)
2019 return;
2020
2021 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
2022
2023 sctx->tess_offchip_ring = pipe_buffer_create(sctx->b.b.screen, 0,
2024 PIPE_USAGE_DEFAULT,
2025 max_offchip_buffers *
2026 sctx->screen->tess_offchip_block_dw_size * 4);
2027 if (!sctx->tess_offchip_ring)
2028 return;
2029
2030 si_init_config_add_vgt_flush(sctx);
2031
2032 /* Append these registers to the init config state. */
2033 if (sctx->b.chip_class >= CIK) {
2034 if (sctx->b.chip_class >= VI)
2035 --max_offchip_buffers;
2036
2037 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
2038 S_030938_SIZE(sctx->tf_ring->width0 / 4));
2039 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
2040 r600_resource(sctx->tf_ring)->gpu_address >> 8);
2041 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
2042 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2043 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
2044 } else {
2045 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
2046 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
2047 S_008988_SIZE(sctx->tf_ring->width0 / 4));
2048 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
2049 r600_resource(sctx->tf_ring)->gpu_address >> 8);
2050 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2051 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
2052 }
2053
2054 /* Flush the context to re-emit the init_config state.
2055 * This is done only once in a lifetime of a context.
2056 */
2057 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2058 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2059 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2060
2061 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_FACTOR, sctx->tf_ring,
2062 0, sctx->tf_ring->width0, false, false, 0, 0, 0);
2063
2064 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_OFFCHIP,
2065 sctx->tess_offchip_ring, 0,
2066 sctx->tess_offchip_ring->width0, false, false, 0, 0, 0);
2067 }
2068
2069 /**
2070 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
2071 * VS passes its outputs to TES directly, so the fixed-function shader only
2072 * has to write TESSOUTER and TESSINNER.
2073 */
2074 static void si_generate_fixed_func_tcs(struct si_context *sctx)
2075 {
2076 struct ureg_src outer, inner;
2077 struct ureg_dst tessouter, tessinner;
2078 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
2079
2080 if (!ureg)
2081 return; /* if we get here, we're screwed */
2082
2083 assert(!sctx->fixed_func_tcs_shader.cso);
2084
2085 outer = ureg_DECL_system_value(ureg,
2086 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
2087 inner = ureg_DECL_system_value(ureg,
2088 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
2089
2090 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
2091 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
2092
2093 ureg_MOV(ureg, tessouter, outer);
2094 ureg_MOV(ureg, tessinner, inner);
2095 ureg_END(ureg);
2096
2097 sctx->fixed_func_tcs_shader.cso =
2098 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
2099 }
2100
2101 static void si_update_vgt_shader_config(struct si_context *sctx)
2102 {
2103 /* Calculate the index of the config.
2104 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
2105 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
2106 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
2107
2108 if (!*pm4) {
2109 uint32_t stages = 0;
2110
2111 *pm4 = CALLOC_STRUCT(si_pm4_state);
2112
2113 if (sctx->tes_shader.cso) {
2114 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2115 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2116
2117 if (sctx->gs_shader.cso)
2118 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2119 S_028B54_GS_EN(1) |
2120 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2121 else
2122 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2123 } else if (sctx->gs_shader.cso) {
2124 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2125 S_028B54_GS_EN(1) |
2126 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2127 }
2128
2129 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
2130 }
2131 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
2132 }
2133
2134 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
2135 {
2136 struct pipe_stream_output_info *so = &shader->so;
2137 uint32_t enabled_stream_buffers_mask = 0;
2138 int i;
2139
2140 for (i = 0; i < so->num_outputs; i++)
2141 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
2142 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
2143 sctx->b.streamout.stride_in_dw = shader->so.stride;
2144 }
2145
2146 bool si_update_shaders(struct si_context *sctx)
2147 {
2148 struct pipe_context *ctx = (struct pipe_context*)sctx;
2149 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2150 int r;
2151
2152 /* Update stages before GS. */
2153 if (sctx->tes_shader.cso) {
2154 if (!sctx->tf_ring) {
2155 si_init_tess_factor_ring(sctx);
2156 if (!sctx->tf_ring)
2157 return false;
2158 }
2159
2160 /* VS as LS */
2161 r = si_shader_select(ctx, &sctx->vs_shader);
2162 if (r)
2163 return false;
2164 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2165
2166 if (sctx->tcs_shader.cso) {
2167 r = si_shader_select(ctx, &sctx->tcs_shader);
2168 if (r)
2169 return false;
2170 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2171 } else {
2172 if (!sctx->fixed_func_tcs_shader.cso) {
2173 si_generate_fixed_func_tcs(sctx);
2174 if (!sctx->fixed_func_tcs_shader.cso)
2175 return false;
2176 }
2177
2178 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader);
2179 if (r)
2180 return false;
2181 si_pm4_bind_state(sctx, hs,
2182 sctx->fixed_func_tcs_shader.current->pm4);
2183 }
2184
2185 r = si_shader_select(ctx, &sctx->tes_shader);
2186 if (r)
2187 return false;
2188
2189 if (sctx->gs_shader.cso) {
2190 /* TES as ES */
2191 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2192 } else {
2193 /* TES as VS */
2194 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2195 si_update_so(sctx, sctx->tes_shader.cso);
2196 }
2197 } else if (sctx->gs_shader.cso) {
2198 /* VS as ES */
2199 r = si_shader_select(ctx, &sctx->vs_shader);
2200 if (r)
2201 return false;
2202 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2203 } else {
2204 /* VS as VS */
2205 r = si_shader_select(ctx, &sctx->vs_shader);
2206 if (r)
2207 return false;
2208 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2209 si_update_so(sctx, sctx->vs_shader.cso);
2210 }
2211
2212 /* Update GS. */
2213 if (sctx->gs_shader.cso) {
2214 r = si_shader_select(ctx, &sctx->gs_shader);
2215 if (r)
2216 return false;
2217 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2218 si_pm4_bind_state(sctx, vs, sctx->gs_shader.current->gs_copy_shader->pm4);
2219 si_update_so(sctx, sctx->gs_shader.cso);
2220
2221 if (!si_update_gs_ring_buffers(sctx))
2222 return false;
2223
2224 si_update_gsvs_ring_bindings(sctx);
2225 } else {
2226 si_pm4_bind_state(sctx, gs, NULL);
2227 si_pm4_bind_state(sctx, es, NULL);
2228 }
2229
2230 si_update_vgt_shader_config(sctx);
2231
2232 if (sctx->ps_shader.cso) {
2233 unsigned db_shader_control;
2234
2235 r = si_shader_select(ctx, &sctx->ps_shader);
2236 if (r)
2237 return false;
2238 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2239
2240 db_shader_control =
2241 sctx->ps_shader.cso->db_shader_control |
2242 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
2243
2244 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
2245 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
2246 sctx->flatshade != rs->flatshade) {
2247 sctx->sprite_coord_enable = rs->sprite_coord_enable;
2248 sctx->flatshade = rs->flatshade;
2249 si_mark_atom_dirty(sctx, &sctx->spi_map);
2250 }
2251
2252 if (sctx->b.family == CHIP_STONEY && si_pm4_state_changed(sctx, ps))
2253 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2254
2255 if (sctx->ps_db_shader_control != db_shader_control) {
2256 sctx->ps_db_shader_control = db_shader_control;
2257 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2258 }
2259
2260 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.ps.epilog.poly_line_smoothing) {
2261 sctx->smoothing_enabled = sctx->ps_shader.current->key.ps.epilog.poly_line_smoothing;
2262 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2263
2264 if (sctx->b.chip_class == SI)
2265 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2266
2267 if (sctx->framebuffer.nr_samples <= 1)
2268 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2269 }
2270 }
2271
2272 if (si_pm4_state_changed(sctx, ls) ||
2273 si_pm4_state_changed(sctx, hs) ||
2274 si_pm4_state_changed(sctx, es) ||
2275 si_pm4_state_changed(sctx, gs) ||
2276 si_pm4_state_changed(sctx, vs) ||
2277 si_pm4_state_changed(sctx, ps)) {
2278 if (!si_update_spi_tmpring_size(sctx))
2279 return false;
2280 }
2281
2282 sctx->do_update_shaders = false;
2283 return true;
2284 }
2285
2286 void si_init_shader_functions(struct si_context *sctx)
2287 {
2288 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
2289
2290 sctx->b.b.create_vs_state = si_create_shader_selector;
2291 sctx->b.b.create_tcs_state = si_create_shader_selector;
2292 sctx->b.b.create_tes_state = si_create_shader_selector;
2293 sctx->b.b.create_gs_state = si_create_shader_selector;
2294 sctx->b.b.create_fs_state = si_create_shader_selector;
2295
2296 sctx->b.b.bind_vs_state = si_bind_vs_shader;
2297 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
2298 sctx->b.b.bind_tes_state = si_bind_tes_shader;
2299 sctx->b.b.bind_gs_state = si_bind_gs_shader;
2300 sctx->b.b.bind_fs_state = si_bind_ps_shader;
2301
2302 sctx->b.b.delete_vs_state = si_delete_shader_selector;
2303 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
2304 sctx->b.b.delete_tes_state = si_delete_shader_selector;
2305 sctx->b.b.delete_gs_state = si_delete_shader_selector;
2306 sctx->b.b.delete_fs_state = si_delete_shader_selector;
2307 }