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radeonsi: implement a fixed-function tessellation control shader and its state
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_ureg.h"
34 #include "util/u_memory.h"
35 #include "util/u_simple_shaders.h"
36
37 static void si_set_tesseval_regs(struct si_shader *shader,
38 struct si_pm4_state *pm4)
39 {
40 struct tgsi_shader_info *info = &shader->selector->info;
41 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
42 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
43 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
44 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
45 unsigned type, partitioning, topology;
46
47 switch (tes_prim_mode) {
48 case PIPE_PRIM_LINES:
49 type = V_028B6C_TESS_ISOLINE;
50 break;
51 case PIPE_PRIM_TRIANGLES:
52 type = V_028B6C_TESS_TRIANGLE;
53 break;
54 case PIPE_PRIM_QUADS:
55 type = V_028B6C_TESS_QUAD;
56 break;
57 default:
58 assert(0);
59 return;
60 }
61
62 switch (tes_spacing) {
63 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
64 partitioning = V_028B6C_PART_FRAC_ODD;
65 break;
66 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
67 partitioning = V_028B6C_PART_FRAC_EVEN;
68 break;
69 case PIPE_TESS_SPACING_EQUAL:
70 partitioning = V_028B6C_PART_INTEGER;
71 break;
72 default:
73 assert(0);
74 return;
75 }
76
77 if (tes_point_mode)
78 topology = V_028B6C_OUTPUT_POINT;
79 else if (tes_prim_mode == PIPE_PRIM_LINES)
80 topology = V_028B6C_OUTPUT_LINE;
81 else if (tes_vertex_order_cw)
82 /* for some reason, this must be the other way around */
83 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
84 else
85 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
86
87 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
88 S_028B6C_TYPE(type) |
89 S_028B6C_PARTITIONING(partitioning) |
90 S_028B6C_TOPOLOGY(topology));
91 }
92
93 static void si_shader_ls(struct si_shader *shader)
94 {
95 struct si_pm4_state *pm4;
96 unsigned num_sgprs, num_user_sgprs;
97 unsigned vgpr_comp_cnt;
98 uint64_t va;
99
100 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
101 if (pm4 == NULL)
102 return;
103
104 va = shader->bo->gpu_address;
105 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
106
107 /* We need at least 2 components for LS.
108 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
109 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 1;
110
111 num_user_sgprs = SI_LS_NUM_USER_SGPR;
112 num_sgprs = shader->num_sgprs;
113 if (num_user_sgprs > num_sgprs) {
114 /* Last 2 reserved SGPRs are used for VCC */
115 num_sgprs = num_user_sgprs + 2;
116 }
117 assert(num_sgprs <= 104);
118
119 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
120 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
121
122 shader->ls_rsrc1 = S_00B528_VGPRS((shader->num_vgprs - 1) / 4) |
123 S_00B528_SGPRS((num_sgprs - 1) / 8) |
124 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt);
125 shader->ls_rsrc2 = S_00B52C_USER_SGPR(num_user_sgprs);
126 }
127
128 static void si_shader_hs(struct si_shader *shader)
129 {
130 struct si_pm4_state *pm4;
131 unsigned num_sgprs, num_user_sgprs;
132 uint64_t va;
133
134 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
135 if (pm4 == NULL)
136 return;
137
138 va = shader->bo->gpu_address;
139 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
140
141 num_user_sgprs = SI_TCS_NUM_USER_SGPR;
142 num_sgprs = shader->num_sgprs;
143 /* One SGPR after user SGPRs is pre-loaded with tessellation factor
144 * buffer offset. */
145 if ((num_user_sgprs + 1) > num_sgprs) {
146 /* Last 2 reserved SGPRs are used for VCC */
147 num_sgprs = num_user_sgprs + 1 + 2;
148 }
149 assert(num_sgprs <= 104);
150
151 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
152 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
153 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
154 S_00B428_VGPRS((shader->num_vgprs - 1) / 4) |
155 S_00B428_SGPRS((num_sgprs - 1) / 8));
156 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
157 S_00B42C_USER_SGPR(num_user_sgprs));
158 }
159
160 static void si_shader_es(struct si_shader *shader)
161 {
162 struct si_pm4_state *pm4;
163 unsigned num_sgprs, num_user_sgprs;
164 unsigned vgpr_comp_cnt;
165 uint64_t va;
166
167 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
168
169 if (pm4 == NULL)
170 return;
171
172 va = shader->bo->gpu_address;
173 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
174
175 if (shader->selector->type == PIPE_SHADER_VERTEX) {
176 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
177 num_user_sgprs = SI_VS_NUM_USER_SGPR;
178 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
179 vgpr_comp_cnt = 3; /* all components are needed for TES */
180 num_user_sgprs = SI_TES_NUM_USER_SGPR;
181 } else
182 assert(0);
183
184 num_sgprs = shader->num_sgprs;
185 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
186 if ((num_user_sgprs + 1) > num_sgprs) {
187 /* Last 2 reserved SGPRs are used for VCC */
188 num_sgprs = num_user_sgprs + 1 + 2;
189 }
190 assert(num_sgprs <= 104);
191
192 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
193 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
194 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
195 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
196 S_00B328_SGPRS((num_sgprs - 1) / 8) |
197 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
198 S_00B328_DX10_CLAMP(shader->dx10_clamp_mode));
199 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
200 S_00B32C_USER_SGPR(num_user_sgprs) |
201 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
202
203 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
204 si_set_tesseval_regs(shader, pm4);
205 }
206
207 static void si_shader_gs(struct si_shader *shader)
208 {
209 unsigned gs_vert_itemsize = shader->selector->info.num_outputs * (16 >> 2);
210 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
211 unsigned gsvs_itemsize = gs_vert_itemsize * gs_max_vert_out;
212 unsigned gs_num_invocations = shader->selector->gs_num_invocations;
213 unsigned cut_mode;
214 struct si_pm4_state *pm4;
215 unsigned num_sgprs, num_user_sgprs;
216 uint64_t va;
217
218 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
219 assert(gsvs_itemsize < (1 << 15));
220
221 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
222
223 if (pm4 == NULL)
224 return;
225
226 if (gs_max_vert_out <= 128) {
227 cut_mode = V_028A40_GS_CUT_128;
228 } else if (gs_max_vert_out <= 256) {
229 cut_mode = V_028A40_GS_CUT_256;
230 } else if (gs_max_vert_out <= 512) {
231 cut_mode = V_028A40_GS_CUT_512;
232 } else {
233 assert(gs_max_vert_out <= 1024);
234 cut_mode = V_028A40_GS_CUT_1024;
235 }
236
237 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
238 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
239 S_028A40_CUT_MODE(cut_mode)|
240 S_028A40_ES_WRITE_OPTIMIZE(1) |
241 S_028A40_GS_WRITE_OPTIMIZE(1));
242
243 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
244 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize);
245 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize);
246
247 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
248 util_bitcount64(shader->selector->inputs_read) * (16 >> 2));
249 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
250
251 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
252
253 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize);
254
255 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
256 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
257 S_028B90_ENABLE(gs_num_invocations > 0));
258
259 va = shader->bo->gpu_address;
260 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
261 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
262 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
263
264 num_user_sgprs = SI_GS_NUM_USER_SGPR;
265 num_sgprs = shader->num_sgprs;
266 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
267 if ((num_user_sgprs + 2) > num_sgprs) {
268 /* Last 2 reserved SGPRs are used for VCC */
269 num_sgprs = num_user_sgprs + 2 + 2;
270 }
271 assert(num_sgprs <= 104);
272
273 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
274 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
275 S_00B228_SGPRS((num_sgprs - 1) / 8) |
276 S_00B228_DX10_CLAMP(shader->dx10_clamp_mode));
277 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
278 S_00B22C_USER_SGPR(num_user_sgprs) |
279 S_00B22C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
280 }
281
282 static void si_shader_vs(struct si_shader *shader)
283 {
284 struct si_pm4_state *pm4;
285 unsigned num_sgprs, num_user_sgprs;
286 unsigned nparams, vgpr_comp_cnt;
287 uint64_t va;
288 unsigned window_space =
289 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
290
291 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
292
293 if (pm4 == NULL)
294 return;
295
296 va = shader->bo->gpu_address;
297 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
298
299 if (shader->is_gs_copy_shader) {
300 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
301 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
302 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
303 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
304 num_user_sgprs = SI_VS_NUM_USER_SGPR;
305 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
306 vgpr_comp_cnt = 3; /* all components are needed for TES */
307 num_user_sgprs = SI_TES_NUM_USER_SGPR;
308 } else
309 assert(0);
310
311 num_sgprs = shader->num_sgprs;
312 if (num_user_sgprs > num_sgprs) {
313 /* Last 2 reserved SGPRs are used for VCC */
314 num_sgprs = num_user_sgprs + 2;
315 }
316 assert(num_sgprs <= 104);
317
318 /* VS is required to export at least one param. */
319 nparams = MAX2(shader->nr_param_exports, 1);
320 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
321 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
322
323 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
324 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
325 S_02870C_POS1_EXPORT_FORMAT(shader->nr_pos_exports > 1 ?
326 V_02870C_SPI_SHADER_4COMP :
327 V_02870C_SPI_SHADER_NONE) |
328 S_02870C_POS2_EXPORT_FORMAT(shader->nr_pos_exports > 2 ?
329 V_02870C_SPI_SHADER_4COMP :
330 V_02870C_SPI_SHADER_NONE) |
331 S_02870C_POS3_EXPORT_FORMAT(shader->nr_pos_exports > 3 ?
332 V_02870C_SPI_SHADER_4COMP :
333 V_02870C_SPI_SHADER_NONE));
334
335 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
336 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
337 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
338 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
339 S_00B128_SGPRS((num_sgprs - 1) / 8) |
340 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
341 S_00B128_DX10_CLAMP(shader->dx10_clamp_mode));
342 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
343 S_00B12C_USER_SGPR(num_user_sgprs) |
344 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
345 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
346 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
347 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
348 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
349 S_00B12C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
350 if (window_space)
351 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
352 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
353 else
354 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
355 S_028818_VTX_W0_FMT(1) |
356 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
357 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
358 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
359
360 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
361 si_set_tesseval_regs(shader, pm4);
362 }
363
364 static void si_shader_ps(struct si_shader *shader)
365 {
366 struct tgsi_shader_info *info = &shader->selector->info;
367 struct si_pm4_state *pm4;
368 unsigned i, spi_ps_in_control;
369 unsigned num_sgprs, num_user_sgprs;
370 unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
371 uint64_t va;
372
373 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
374
375 if (pm4 == NULL)
376 return;
377
378 for (i = 0; i < info->num_inputs; i++) {
379 switch (info->input_semantic_name[i]) {
380 case TGSI_SEMANTIC_POSITION:
381 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
382 * Possible vaules:
383 * 0 -> Position = pixel center (default)
384 * 1 -> Position = pixel centroid
385 * 2 -> Position = at sample position
386 */
387 switch (info->input_interpolate_loc[i]) {
388 case TGSI_INTERPOLATE_LOC_CENTROID:
389 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
390 break;
391 case TGSI_INTERPOLATE_LOC_SAMPLE:
392 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
393 break;
394 }
395
396 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
397 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
398 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
399 break;
400 }
401 }
402
403 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->nparam) |
404 S_0286D8_BC_OPTIMIZE_DISABLE(1);
405
406 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
407 spi_ps_input_ena = shader->spi_ps_input_ena;
408 /* we need to enable at least one of them, otherwise we hang the GPU */
409 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
410 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
411 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
412 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
413 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
414 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
415 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
416 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
417
418 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
419 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
420 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
421
422 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
423 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
424 shader->spi_shader_col_format);
425 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
426
427 va = shader->bo->gpu_address;
428 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
429 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
430 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
431
432 num_user_sgprs = SI_PS_NUM_USER_SGPR;
433 num_sgprs = shader->num_sgprs;
434 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
435 if ((num_user_sgprs + 1) > num_sgprs) {
436 /* Last 2 reserved SGPRs are used for VCC */
437 num_sgprs = num_user_sgprs + 1 + 2;
438 }
439 assert(num_sgprs <= 104);
440
441 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
442 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
443 S_00B028_SGPRS((num_sgprs - 1) / 8) |
444 S_00B028_DX10_CLAMP(shader->dx10_clamp_mode));
445 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
446 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
447 S_00B02C_USER_SGPR(num_user_sgprs) |
448 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
449 }
450
451 static void si_shader_init_pm4_state(struct si_shader *shader)
452 {
453
454 if (shader->pm4)
455 si_pm4_free_state_simple(shader->pm4);
456
457 switch (shader->selector->type) {
458 case PIPE_SHADER_VERTEX:
459 if (shader->key.vs.as_ls)
460 si_shader_ls(shader);
461 else if (shader->key.vs.as_es)
462 si_shader_es(shader);
463 else
464 si_shader_vs(shader);
465 break;
466 case PIPE_SHADER_TESS_CTRL:
467 si_shader_hs(shader);
468 break;
469 case PIPE_SHADER_TESS_EVAL:
470 if (shader->key.tes.as_es)
471 si_shader_es(shader);
472 else
473 si_shader_vs(shader);
474 break;
475 case PIPE_SHADER_GEOMETRY:
476 si_shader_gs(shader);
477 si_shader_vs(shader->gs_copy_shader);
478 break;
479 case PIPE_SHADER_FRAGMENT:
480 si_shader_ps(shader);
481 break;
482 default:
483 assert(0);
484 }
485 }
486
487 /* Compute the key for the hw shader variant */
488 static inline void si_shader_selector_key(struct pipe_context *ctx,
489 struct si_shader_selector *sel,
490 union si_shader_key *key)
491 {
492 struct si_context *sctx = (struct si_context *)ctx;
493 unsigned i;
494
495 memset(key, 0, sizeof(*key));
496
497 switch (sel->type) {
498 case PIPE_SHADER_VERTEX:
499 if (sctx->vertex_elements)
500 for (i = 0; i < sctx->vertex_elements->count; ++i)
501 key->vs.instance_divisors[i] =
502 sctx->vertex_elements->elements[i].instance_divisor;
503
504 if (sctx->tes_shader)
505 key->vs.as_ls = 1;
506 else if (sctx->gs_shader) {
507 key->vs.as_es = 1;
508 key->vs.es_enabled_outputs = sctx->gs_shader->inputs_read;
509 }
510 break;
511 case PIPE_SHADER_TESS_CTRL:
512 key->tcs.prim_mode =
513 sctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
514 break;
515 case PIPE_SHADER_TESS_EVAL:
516 if (sctx->gs_shader) {
517 key->tes.as_es = 1;
518 key->tes.es_enabled_outputs = sctx->gs_shader->inputs_read;
519 }
520 break;
521 case PIPE_SHADER_GEOMETRY:
522 break;
523 case PIPE_SHADER_FRAGMENT: {
524 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
525
526 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
527 key->ps.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
528 key->ps.export_16bpc = sctx->framebuffer.export_16bpc;
529
530 if (rs) {
531 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
532 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
533 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
534 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
535
536 key->ps.color_two_side = rs->two_side;
537
538 if (sctx->queued.named.blend) {
539 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
540 rs->multisample_enable &&
541 !sctx->framebuffer.cb0_is_integer;
542 }
543
544 key->ps.poly_stipple = rs->poly_stipple_enable && is_poly;
545 key->ps.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
546 (is_line && rs->line_smooth)) &&
547 sctx->framebuffer.nr_samples <= 1;
548 }
549
550 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
551 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
552 if (sctx->queued.named.dsa &&
553 !sctx->framebuffer.cb0_is_integer)
554 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
555 break;
556 }
557 default:
558 assert(0);
559 }
560 }
561
562 /* Select the hw shader variant depending on the current state. */
563 static int si_shader_select(struct pipe_context *ctx,
564 struct si_shader_selector *sel)
565 {
566 struct si_context *sctx = (struct si_context *)ctx;
567 union si_shader_key key;
568 struct si_shader * shader = NULL;
569 int r;
570
571 si_shader_selector_key(ctx, sel, &key);
572
573 /* Check if we don't need to change anything.
574 * This path is also used for most shaders that don't need multiple
575 * variants, it will cost just a computation of the key and this
576 * test. */
577 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
578 return 0;
579 }
580
581 /* lookup if we have other variants in the list */
582 if (sel->num_shaders > 1) {
583 struct si_shader *p = sel->current, *c = p->next_variant;
584
585 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
586 p = c;
587 c = c->next_variant;
588 }
589
590 if (c) {
591 p->next_variant = c->next_variant;
592 shader = c;
593 }
594 }
595
596 if (shader) {
597 shader->next_variant = sel->current;
598 sel->current = shader;
599 } else {
600 shader = CALLOC(1, sizeof(struct si_shader));
601 shader->selector = sel;
602 shader->key = key;
603
604 shader->next_variant = sel->current;
605 sel->current = shader;
606 r = si_shader_create((struct si_screen*)ctx->screen, sctx->tm,
607 shader);
608 if (unlikely(r)) {
609 R600_ERR("Failed to build shader variant (type=%u) %d\n",
610 sel->type, r);
611 sel->current = NULL;
612 FREE(shader);
613 return r;
614 }
615 si_shader_init_pm4_state(shader);
616 sel->num_shaders++;
617 }
618
619 return 0;
620 }
621
622 static void *si_create_shader_state(struct pipe_context *ctx,
623 const struct pipe_shader_state *state,
624 unsigned pipe_shader_type)
625 {
626 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
627 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
628 int i;
629
630 sel->type = pipe_shader_type;
631 sel->tokens = tgsi_dup_tokens(state->tokens);
632 sel->so = state->stream_output;
633 tgsi_scan_shader(state->tokens, &sel->info);
634
635 switch (pipe_shader_type) {
636 case PIPE_SHADER_GEOMETRY:
637 sel->gs_output_prim =
638 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
639 sel->gs_max_out_vertices =
640 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
641 sel->gs_num_invocations =
642 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
643
644 for (i = 0; i < sel->info.num_inputs; i++) {
645 unsigned name = sel->info.input_semantic_name[i];
646 unsigned index = sel->info.input_semantic_index[i];
647
648 switch (name) {
649 case TGSI_SEMANTIC_PRIMID:
650 break;
651 default:
652 sel->inputs_read |=
653 1llu << si_shader_io_get_unique_index(name, index);
654 }
655 }
656 break;
657
658 case PIPE_SHADER_VERTEX:
659 case PIPE_SHADER_TESS_CTRL:
660 for (i = 0; i < sel->info.num_outputs; i++) {
661 unsigned name = sel->info.output_semantic_name[i];
662 unsigned index = sel->info.output_semantic_index[i];
663
664 switch (name) {
665 case TGSI_SEMANTIC_TESSINNER:
666 case TGSI_SEMANTIC_TESSOUTER:
667 case TGSI_SEMANTIC_PATCH:
668 sel->patch_outputs_written |=
669 1llu << si_shader_io_get_unique_index(name, index);
670 break;
671 default:
672 sel->outputs_written |=
673 1llu << si_shader_io_get_unique_index(name, index);
674 }
675 }
676 break;
677 }
678
679 if (sscreen->b.debug_flags & DBG_PRECOMPILE)
680 si_shader_select(ctx, sel);
681
682 return sel;
683 }
684
685 static void *si_create_fs_state(struct pipe_context *ctx,
686 const struct pipe_shader_state *state)
687 {
688 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
689 }
690
691 static void *si_create_gs_state(struct pipe_context *ctx,
692 const struct pipe_shader_state *state)
693 {
694 return si_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
695 }
696
697 static void *si_create_vs_state(struct pipe_context *ctx,
698 const struct pipe_shader_state *state)
699 {
700 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
701 }
702
703 static void *si_create_tcs_state(struct pipe_context *ctx,
704 const struct pipe_shader_state *state)
705 {
706 return si_create_shader_state(ctx, state, PIPE_SHADER_TESS_CTRL);
707 }
708
709 static void *si_create_tes_state(struct pipe_context *ctx,
710 const struct pipe_shader_state *state)
711 {
712 return si_create_shader_state(ctx, state, PIPE_SHADER_TESS_EVAL);
713 }
714
715 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
716 {
717 struct si_context *sctx = (struct si_context *)ctx;
718 struct si_shader_selector *sel = state;
719
720 if (sctx->vs_shader == sel || !sel)
721 return;
722
723 sctx->vs_shader = sel;
724 sctx->clip_regs.dirty = true;
725 }
726
727 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
728 {
729 struct si_context *sctx = (struct si_context *)ctx;
730 struct si_shader_selector *sel = state;
731 bool enable_changed = !!sctx->gs_shader != !!sel;
732
733 if (sctx->gs_shader == sel)
734 return;
735
736 sctx->gs_shader = sel;
737 sctx->clip_regs.dirty = true;
738 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
739
740 if (enable_changed)
741 si_shader_change_notify(sctx);
742 }
743
744 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
745 {
746 struct si_context *sctx = (struct si_context *)ctx;
747 struct si_shader_selector *sel = state;
748
749 if (sctx->tcs_shader == sel)
750 return;
751
752 sctx->tcs_shader = sel;
753 }
754
755 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
756 {
757 struct si_context *sctx = (struct si_context *)ctx;
758 struct si_shader_selector *sel = state;
759 bool enable_changed = !!sctx->tes_shader != !!sel;
760
761 if (sctx->tes_shader == sel)
762 return;
763
764 sctx->tes_shader = sel;
765 sctx->clip_regs.dirty = true;
766 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
767
768 if (enable_changed)
769 si_shader_change_notify(sctx);
770 }
771
772 static void si_make_dummy_ps(struct si_context *sctx)
773 {
774 if (!sctx->dummy_pixel_shader) {
775 sctx->dummy_pixel_shader =
776 util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
777 TGSI_SEMANTIC_GENERIC,
778 TGSI_INTERPOLATE_CONSTANT);
779 }
780 }
781
782 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
783 {
784 struct si_context *sctx = (struct si_context *)ctx;
785 struct si_shader_selector *sel = state;
786
787 /* skip if supplied shader is one already in use */
788 if (sctx->ps_shader == sel)
789 return;
790
791 /* use a dummy shader if binding a NULL shader */
792 if (!sel) {
793 si_make_dummy_ps(sctx);
794 sel = sctx->dummy_pixel_shader;
795 }
796
797 sctx->ps_shader = sel;
798 }
799
800 static void si_delete_shader_selector(struct pipe_context *ctx,
801 struct si_shader_selector *sel)
802 {
803 struct si_context *sctx = (struct si_context *)ctx;
804 struct si_shader *p = sel->current, *c;
805
806 while (p) {
807 c = p->next_variant;
808 switch (sel->type) {
809 case PIPE_SHADER_VERTEX:
810 if (p->key.vs.as_ls)
811 si_pm4_delete_state(sctx, ls, p->pm4);
812 else if (p->key.vs.as_es)
813 si_pm4_delete_state(sctx, es, p->pm4);
814 else
815 si_pm4_delete_state(sctx, vs, p->pm4);
816 break;
817 case PIPE_SHADER_TESS_CTRL:
818 si_pm4_delete_state(sctx, hs, p->pm4);
819 break;
820 case PIPE_SHADER_TESS_EVAL:
821 if (p->key.tes.as_es)
822 si_pm4_delete_state(sctx, es, p->pm4);
823 else
824 si_pm4_delete_state(sctx, vs, p->pm4);
825 break;
826 case PIPE_SHADER_GEOMETRY:
827 si_pm4_delete_state(sctx, gs, p->pm4);
828 si_pm4_delete_state(sctx, vs, p->gs_copy_shader->pm4);
829 break;
830 case PIPE_SHADER_FRAGMENT:
831 si_pm4_delete_state(sctx, ps, p->pm4);
832 break;
833 }
834
835 si_shader_destroy(ctx, p);
836 free(p);
837 p = c;
838 }
839
840 free(sel->tokens);
841 free(sel);
842 }
843
844 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
845 {
846 struct si_context *sctx = (struct si_context *)ctx;
847 struct si_shader_selector *sel = (struct si_shader_selector *)state;
848
849 if (sctx->vs_shader == sel) {
850 sctx->vs_shader = NULL;
851 }
852
853 si_delete_shader_selector(ctx, sel);
854 }
855
856 static void si_delete_gs_shader(struct pipe_context *ctx, void *state)
857 {
858 struct si_context *sctx = (struct si_context *)ctx;
859 struct si_shader_selector *sel = (struct si_shader_selector *)state;
860
861 if (sctx->gs_shader == sel) {
862 sctx->gs_shader = NULL;
863 }
864
865 si_delete_shader_selector(ctx, sel);
866 }
867
868 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
869 {
870 struct si_context *sctx = (struct si_context *)ctx;
871 struct si_shader_selector *sel = (struct si_shader_selector *)state;
872
873 if (sctx->ps_shader == sel) {
874 sctx->ps_shader = NULL;
875 }
876
877 si_delete_shader_selector(ctx, sel);
878 }
879
880 static void si_delete_tcs_shader(struct pipe_context *ctx, void *state)
881 {
882 struct si_context *sctx = (struct si_context *)ctx;
883 struct si_shader_selector *sel = (struct si_shader_selector *)state;
884
885 if (sctx->tcs_shader == sel) {
886 sctx->tcs_shader = NULL;
887 }
888
889 si_delete_shader_selector(ctx, sel);
890 }
891
892 static void si_delete_tes_shader(struct pipe_context *ctx, void *state)
893 {
894 struct si_context *sctx = (struct si_context *)ctx;
895 struct si_shader_selector *sel = (struct si_shader_selector *)state;
896
897 if (sctx->tes_shader == sel) {
898 sctx->tes_shader = NULL;
899 }
900
901 si_delete_shader_selector(ctx, sel);
902 }
903
904 static void si_update_spi_map(struct si_context *sctx)
905 {
906 struct si_shader *ps = sctx->ps_shader->current;
907 struct si_shader *vs = si_get_vs_state(sctx);
908 struct tgsi_shader_info *psinfo = &ps->selector->info;
909 struct tgsi_shader_info *vsinfo = &vs->selector->info;
910 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
911 unsigned i, j, tmp;
912
913 for (i = 0; i < psinfo->num_inputs; i++) {
914 unsigned name = psinfo->input_semantic_name[i];
915 unsigned index = psinfo->input_semantic_index[i];
916 unsigned interpolate = psinfo->input_interpolate[i];
917 unsigned param_offset = ps->ps_input_param_offset[i];
918
919 if (name == TGSI_SEMANTIC_POSITION ||
920 name == TGSI_SEMANTIC_FACE)
921 /* Read from preloaded VGPRs, not parameters */
922 continue;
923
924 bcolor:
925 tmp = 0;
926
927 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
928 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
929 tmp |= S_028644_FLAT_SHADE(1);
930
931 if (name == TGSI_SEMANTIC_PCOORD ||
932 (name == TGSI_SEMANTIC_TEXCOORD &&
933 sctx->sprite_coord_enable & (1 << index))) {
934 tmp |= S_028644_PT_SPRITE_TEX(1);
935 }
936
937 for (j = 0; j < vsinfo->num_outputs; j++) {
938 if (name == vsinfo->output_semantic_name[j] &&
939 index == vsinfo->output_semantic_index[j]) {
940 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[j]);
941 break;
942 }
943 }
944
945 if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(tmp)) {
946 /* No corresponding output found, load defaults into input.
947 * Don't set any other bits.
948 * (FLAT_SHADE=1 completely changes behavior) */
949 tmp = S_028644_OFFSET(0x20);
950 }
951
952 si_pm4_set_reg(pm4,
953 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
954 tmp);
955
956 if (name == TGSI_SEMANTIC_COLOR &&
957 ps->key.ps.color_two_side) {
958 name = TGSI_SEMANTIC_BCOLOR;
959 param_offset++;
960 goto bcolor;
961 }
962 }
963
964 si_pm4_set_state(sctx, spi, pm4);
965 }
966
967 /* Initialize state related to ESGS / GSVS ring buffers */
968 static void si_init_gs_rings(struct si_context *sctx)
969 {
970 unsigned esgs_ring_size = 128 * 1024;
971 unsigned gsvs_ring_size = 64 * 1024 * 1024;
972
973 assert(!sctx->gs_rings);
974 sctx->gs_rings = CALLOC_STRUCT(si_pm4_state);
975
976 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
977 PIPE_USAGE_DEFAULT, esgs_ring_size);
978
979 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
980 PIPE_USAGE_DEFAULT, gsvs_ring_size);
981
982 if (sctx->b.chip_class >= CIK) {
983 si_pm4_set_reg(sctx->gs_rings, R_030900_VGT_ESGS_RING_SIZE,
984 esgs_ring_size / 256);
985 si_pm4_set_reg(sctx->gs_rings, R_030904_VGT_GSVS_RING_SIZE,
986 gsvs_ring_size / 256);
987 } else {
988 si_pm4_set_reg(sctx->gs_rings, R_0088C8_VGT_ESGS_RING_SIZE,
989 esgs_ring_size / 256);
990 si_pm4_set_reg(sctx->gs_rings, R_0088CC_VGT_GSVS_RING_SIZE,
991 gsvs_ring_size / 256);
992 }
993
994 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
995 sctx->esgs_ring, 0, esgs_ring_size,
996 true, true, 4, 64);
997 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
998 sctx->esgs_ring, 0, esgs_ring_size,
999 false, false, 0, 0);
1000 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
1001 sctx->gsvs_ring, 0, gsvs_ring_size,
1002 false, false, 0, 0);
1003 }
1004
1005 /**
1006 * @returns 1 if \p sel has been updated to use a new scratch buffer and 0
1007 * otherwise.
1008 */
1009 static unsigned si_update_scratch_buffer(struct si_context *sctx,
1010 struct si_shader_selector *sel)
1011 {
1012 struct si_shader *shader;
1013 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
1014
1015 if (!sel)
1016 return 0;
1017
1018 shader = sel->current;
1019
1020 /* This shader doesn't need a scratch buffer */
1021 if (shader->scratch_bytes_per_wave == 0)
1022 return 0;
1023
1024 /* This shader is already configured to use the current
1025 * scratch buffer. */
1026 if (shader->scratch_bo == sctx->scratch_buffer)
1027 return 0;
1028
1029 assert(sctx->scratch_buffer);
1030
1031 si_shader_apply_scratch_relocs(sctx, shader, scratch_va);
1032
1033 /* Replace the shader bo with a new bo that has the relocs applied. */
1034 si_shader_binary_upload(sctx->screen, shader);
1035
1036 /* Update the shader state to use the new shader bo. */
1037 si_shader_init_pm4_state(shader);
1038
1039 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
1040
1041 return 1;
1042 }
1043
1044 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
1045 {
1046 if (!sctx->scratch_buffer)
1047 return 0;
1048
1049 return sctx->scratch_buffer->b.b.width0;
1050 }
1051
1052 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_context *sctx,
1053 struct si_shader_selector *sel)
1054 {
1055 if (!sel)
1056 return 0;
1057
1058 return sel->current->scratch_bytes_per_wave;
1059 }
1060
1061 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
1062 {
1063
1064 return MAX3(si_get_scratch_buffer_bytes_per_wave(sctx, sctx->ps_shader),
1065 si_get_scratch_buffer_bytes_per_wave(sctx, sctx->gs_shader),
1066 si_get_scratch_buffer_bytes_per_wave(sctx, sctx->vs_shader));
1067 }
1068
1069 static void si_update_spi_tmpring_size(struct si_context *sctx)
1070 {
1071 unsigned current_scratch_buffer_size =
1072 si_get_current_scratch_buffer_size(sctx);
1073 unsigned scratch_bytes_per_wave =
1074 si_get_max_scratch_bytes_per_wave(sctx);
1075 unsigned scratch_needed_size = scratch_bytes_per_wave *
1076 sctx->scratch_waves;
1077
1078 if (scratch_needed_size > 0) {
1079
1080 if (scratch_needed_size > current_scratch_buffer_size) {
1081 /* Create a bigger scratch buffer */
1082 pipe_resource_reference(
1083 (struct pipe_resource**)&sctx->scratch_buffer,
1084 NULL);
1085
1086 sctx->scratch_buffer =
1087 si_resource_create_custom(&sctx->screen->b.b,
1088 PIPE_USAGE_DEFAULT, scratch_needed_size);
1089 }
1090
1091 /* Update the shaders, so they are using the latest scratch. The
1092 * scratch buffer may have been changed since these shaders were
1093 * last used, so we still need to try to update them, even if
1094 * they require scratch buffers smaller than the current size.
1095 */
1096 if (si_update_scratch_buffer(sctx, sctx->ps_shader))
1097 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
1098 if (si_update_scratch_buffer(sctx, sctx->gs_shader))
1099 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
1100
1101 /* VS can be bound as ES or VS. */
1102 if (sctx->gs_shader) {
1103 if (si_update_scratch_buffer(sctx, sctx->vs_shader))
1104 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
1105 } else {
1106 if (si_update_scratch_buffer(sctx, sctx->vs_shader))
1107 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
1108 }
1109 }
1110
1111 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1112 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
1113 "scratch size should already be aligned correctly.");
1114
1115 sctx->spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
1116 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
1117 }
1118
1119 static void si_init_tess_factor_ring(struct si_context *sctx)
1120 {
1121 assert(!sctx->tf_state);
1122 sctx->tf_state = CALLOC_STRUCT(si_pm4_state);
1123
1124 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1125 PIPE_USAGE_DEFAULT,
1126 32768 * sctx->screen->b.info.max_se);
1127 sctx->b.clear_buffer(&sctx->b.b, sctx->tf_ring, 0,
1128 sctx->tf_ring->width0, fui(0), false);
1129 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
1130
1131 if (sctx->b.chip_class >= CIK) {
1132 si_pm4_set_reg(sctx->tf_state, R_030938_VGT_TF_RING_SIZE,
1133 S_030938_SIZE(sctx->tf_ring->width0 / 4));
1134 si_pm4_set_reg(sctx->tf_state, R_030940_VGT_TF_MEMORY_BASE,
1135 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1136 } else {
1137 si_pm4_set_reg(sctx->tf_state, R_008988_VGT_TF_RING_SIZE,
1138 S_008988_SIZE(sctx->tf_ring->width0 / 4));
1139 si_pm4_set_reg(sctx->tf_state, R_0089B8_VGT_TF_MEMORY_BASE,
1140 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1141 }
1142 si_pm4_add_bo(sctx->tf_state, r600_resource(sctx->tf_ring),
1143 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RESOURCE_RW);
1144 si_pm4_bind_state(sctx, tf_ring, sctx->tf_state);
1145
1146 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_TESS_CTRL,
1147 SI_RING_TESS_FACTOR, sctx->tf_ring, 0,
1148 sctx->tf_ring->width0, false, false, 0, 0);
1149
1150 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
1151 }
1152
1153 /**
1154 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
1155 * VS passes its outputs to TES directly, so the fixed-function shader only
1156 * has to write TESSOUTER and TESSINNER.
1157 */
1158 static void si_generate_fixed_func_tcs(struct si_context *sctx)
1159 {
1160 struct ureg_src const0, const1;
1161 struct ureg_dst tessouter, tessinner;
1162 struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
1163
1164 if (!ureg)
1165 return; /* if we get here, we're screwed */
1166
1167 assert(!sctx->fixed_func_tcs_shader);
1168
1169 ureg_DECL_constant2D(ureg, 0, 1, SI_DRIVER_STATE_CONST_BUF);
1170 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 0),
1171 SI_DRIVER_STATE_CONST_BUF);
1172 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 1),
1173 SI_DRIVER_STATE_CONST_BUF);
1174
1175 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1176 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1177
1178 ureg_MOV(ureg, tessouter, const0);
1179 ureg_MOV(ureg, tessinner, const1);
1180 ureg_END(ureg);
1181
1182 sctx->fixed_func_tcs_shader =
1183 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
1184 assert(sctx->fixed_func_tcs_shader);
1185 }
1186
1187 static void si_update_vgt_shader_config(struct si_context *sctx)
1188 {
1189 /* Calculate the index of the config.
1190 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
1191 unsigned index = 2*!!sctx->tes_shader + !!sctx->gs_shader;
1192 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
1193
1194 if (!*pm4) {
1195 uint32_t stages = 0;
1196
1197 *pm4 = CALLOC_STRUCT(si_pm4_state);
1198
1199 if (sctx->tes_shader) {
1200 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1201 S_028B54_HS_EN(1);
1202
1203 if (sctx->gs_shader)
1204 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1205 S_028B54_GS_EN(1) |
1206 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1207 else
1208 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1209 } else if (sctx->gs_shader) {
1210 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1211 S_028B54_GS_EN(1) |
1212 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1213 }
1214
1215 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
1216 if (!sctx->gs_shader)
1217 si_pm4_set_reg(*pm4, R_028A40_VGT_GS_MODE, 0);
1218 }
1219 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
1220 }
1221
1222 void si_update_shaders(struct si_context *sctx)
1223 {
1224 struct pipe_context *ctx = (struct pipe_context*)sctx;
1225 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1226
1227 /* Update stages before GS. */
1228 if (sctx->tes_shader) {
1229 if (!sctx->tf_state)
1230 si_init_tess_factor_ring(sctx);
1231
1232 /* VS as LS */
1233 si_shader_select(ctx, sctx->vs_shader);
1234 si_pm4_bind_state(sctx, ls, sctx->vs_shader->current->pm4);
1235
1236 if (sctx->tcs_shader) {
1237 si_shader_select(ctx, sctx->tcs_shader);
1238 si_pm4_bind_state(sctx, hs, sctx->tcs_shader->current->pm4);
1239 } else {
1240 if (!sctx->fixed_func_tcs_shader)
1241 si_generate_fixed_func_tcs(sctx);
1242 si_shader_select(ctx, sctx->fixed_func_tcs_shader);
1243 si_pm4_bind_state(sctx, hs,
1244 sctx->fixed_func_tcs_shader->current->pm4);
1245 }
1246
1247 si_shader_select(ctx, sctx->tes_shader);
1248 if (sctx->gs_shader) {
1249 /* TES as ES */
1250 si_pm4_bind_state(sctx, es, sctx->tes_shader->current->pm4);
1251 } else {
1252 /* TES as VS */
1253 si_pm4_bind_state(sctx, vs, sctx->tes_shader->current->pm4);
1254 sctx->b.streamout.stride_in_dw = sctx->tes_shader->so.stride;
1255 }
1256 } else if (sctx->gs_shader) {
1257 /* VS as ES */
1258 si_shader_select(ctx, sctx->vs_shader);
1259 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
1260 } else {
1261 /* VS as VS */
1262 si_shader_select(ctx, sctx->vs_shader);
1263 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
1264 sctx->b.streamout.stride_in_dw = sctx->vs_shader->so.stride;
1265 }
1266
1267 /* Update GS. */
1268 if (sctx->gs_shader) {
1269 si_shader_select(ctx, sctx->gs_shader);
1270 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
1271 si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
1272 sctx->b.streamout.stride_in_dw = sctx->gs_shader->so.stride;
1273
1274 if (!sctx->gs_rings)
1275 si_init_gs_rings(sctx);
1276 if (sctx->emitted.named.gs_rings != sctx->gs_rings)
1277 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
1278 si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
1279
1280 si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
1281 sctx->gsvs_ring,
1282 sctx->gs_shader->gs_max_out_vertices *
1283 sctx->gs_shader->info.num_outputs * 16,
1284 64, true, true, 4, 16);
1285 } else {
1286 si_pm4_bind_state(sctx, gs_rings, NULL);
1287 si_pm4_bind_state(sctx, gs, NULL);
1288 si_pm4_bind_state(sctx, es, NULL);
1289 }
1290
1291 si_update_vgt_shader_config(sctx);
1292
1293 si_shader_select(ctx, sctx->ps_shader);
1294
1295 if (!sctx->ps_shader->current) {
1296 struct si_shader_selector *sel;
1297
1298 /* use a dummy shader if compiling the shader (variant) failed */
1299 si_make_dummy_ps(sctx);
1300 sel = sctx->dummy_pixel_shader;
1301 si_shader_select(ctx, sel);
1302 sctx->ps_shader->current = sel->current;
1303 }
1304
1305 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
1306
1307 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
1308 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
1309 sctx->flatshade != rs->flatshade) {
1310 sctx->sprite_coord_enable = rs->sprite_coord_enable;
1311 sctx->flatshade = rs->flatshade;
1312 si_update_spi_map(sctx);
1313 }
1314
1315 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
1316 si_pm4_state_changed(sctx, gs)) {
1317 si_update_spi_tmpring_size(sctx);
1318 }
1319
1320 if (sctx->ps_db_shader_control != sctx->ps_shader->current->db_shader_control) {
1321 sctx->ps_db_shader_control = sctx->ps_shader->current->db_shader_control;
1322 sctx->db_render_state.dirty = true;
1323 }
1324
1325 if (sctx->smoothing_enabled != sctx->ps_shader->current->key.ps.poly_line_smoothing) {
1326 sctx->smoothing_enabled = sctx->ps_shader->current->key.ps.poly_line_smoothing;
1327 sctx->msaa_config.dirty = true;
1328
1329 if (sctx->b.chip_class == SI)
1330 sctx->db_render_state.dirty = true;
1331 }
1332 }
1333
1334 void si_init_shader_functions(struct si_context *sctx)
1335 {
1336 sctx->b.b.create_vs_state = si_create_vs_state;
1337 sctx->b.b.create_tcs_state = si_create_tcs_state;
1338 sctx->b.b.create_tes_state = si_create_tes_state;
1339 sctx->b.b.create_gs_state = si_create_gs_state;
1340 sctx->b.b.create_fs_state = si_create_fs_state;
1341
1342 sctx->b.b.bind_vs_state = si_bind_vs_shader;
1343 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
1344 sctx->b.b.bind_tes_state = si_bind_tes_shader;
1345 sctx->b.b.bind_gs_state = si_bind_gs_shader;
1346 sctx->b.b.bind_fs_state = si_bind_ps_shader;
1347
1348 sctx->b.b.delete_vs_state = si_delete_vs_shader;
1349 sctx->b.b.delete_tcs_state = si_delete_tcs_shader;
1350 sctx->b.b.delete_tes_state = si_delete_tes_shader;
1351 sctx->b.b.delete_gs_state = si_delete_gs_shader;
1352 sctx->b.b.delete_fs_state = si_delete_ps_shader;
1353 }