2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
30 #include "radeon/r600_cs.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_ureg.h"
34 #include "util/hash_table.h"
35 #include "util/u_hash.h"
36 #include "util/u_memory.h"
37 #include "util/u_prim.h"
42 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
45 static void *si_get_tgsi_binary(struct si_shader_selector
*sel
)
47 unsigned tgsi_size
= tgsi_num_tokens(sel
->tokens
) *
48 sizeof(struct tgsi_token
);
49 unsigned size
= 4 + tgsi_size
+ sizeof(sel
->so
);
50 char *result
= (char*)MALLOC(size
);
55 *((uint32_t*)result
) = size
;
56 memcpy(result
+ 4, sel
->tokens
, tgsi_size
);
57 memcpy(result
+ 4 + tgsi_size
, &sel
->so
, sizeof(sel
->so
));
61 /** Copy "data" to "ptr" and return the next dword following copied data. */
62 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
64 /* data may be NULL if size == 0 */
66 memcpy(ptr
, data
, size
);
67 ptr
+= DIV_ROUND_UP(size
, 4);
71 /** Read data from "ptr". Return the next dword following the data. */
72 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
74 memcpy(data
, ptr
, size
);
75 ptr
+= DIV_ROUND_UP(size
, 4);
80 * Write the size as uint followed by the data. Return the next dword
81 * following the copied data.
83 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
86 return write_data(ptr
, data
, size
);
90 * Read the size as uint followed by the data. Return both via parameters.
91 * Return the next dword following the data.
93 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
96 assert(*data
== NULL
);
99 *data
= malloc(*size
);
100 return read_data(ptr
, *data
, *size
);
104 * Return the shader binary in a buffer. The first 4 bytes contain its size
107 static void *si_get_shader_binary(struct si_shader
*shader
)
109 /* There is always a size of data followed by the data itself. */
110 unsigned relocs_size
= shader
->binary
.reloc_count
*
111 sizeof(shader
->binary
.relocs
[0]);
112 unsigned disasm_size
= strlen(shader
->binary
.disasm_string
) + 1;
113 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
114 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
117 4 + /* CRC32 of the data below */
118 align(sizeof(shader
->config
), 4) +
119 align(sizeof(shader
->info
), 4) +
120 4 + align(shader
->binary
.code_size
, 4) +
121 4 + align(shader
->binary
.rodata_size
, 4) +
122 4 + align(relocs_size
, 4) +
123 4 + align(disasm_size
, 4) +
124 4 + align(llvm_ir_size
, 4);
125 void *buffer
= CALLOC(1, size
);
126 uint32_t *ptr
= (uint32_t*)buffer
;
132 ptr
++; /* CRC32 is calculated at the end. */
134 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
135 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
136 ptr
= write_chunk(ptr
, shader
->binary
.code
, shader
->binary
.code_size
);
137 ptr
= write_chunk(ptr
, shader
->binary
.rodata
, shader
->binary
.rodata_size
);
138 ptr
= write_chunk(ptr
, shader
->binary
.relocs
, relocs_size
);
139 ptr
= write_chunk(ptr
, shader
->binary
.disasm_string
, disasm_size
);
140 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
141 assert((char *)ptr
- (char *)buffer
== size
);
144 ptr
= (uint32_t*)buffer
;
146 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
151 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
153 uint32_t *ptr
= (uint32_t*)binary
;
154 uint32_t size
= *ptr
++;
155 uint32_t crc32
= *ptr
++;
158 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
159 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
163 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
164 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
165 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.code
,
166 &shader
->binary
.code_size
);
167 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.rodata
,
168 &shader
->binary
.rodata_size
);
169 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.relocs
, &chunk_size
);
170 shader
->binary
.reloc_count
= chunk_size
/ sizeof(shader
->binary
.relocs
[0]);
171 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.disasm_string
, &chunk_size
);
172 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
178 * Insert a shader into the cache. It's assumed the shader is not in the cache.
179 * Use si_shader_cache_load_shader before calling this.
181 * Returns false on failure, in which case the tgsi_binary should be freed.
183 static bool si_shader_cache_insert_shader(struct si_screen
*sscreen
,
185 struct si_shader
*shader
)
188 struct hash_entry
*entry
;
190 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, tgsi_binary
);
192 return false; /* already added */
194 hw_binary
= si_get_shader_binary(shader
);
198 if (_mesa_hash_table_insert(sscreen
->shader_cache
, tgsi_binary
,
199 hw_binary
) == NULL
) {
207 static bool si_shader_cache_load_shader(struct si_screen
*sscreen
,
209 struct si_shader
*shader
)
211 struct hash_entry
*entry
=
212 _mesa_hash_table_search(sscreen
->shader_cache
, tgsi_binary
);
216 return si_load_shader_binary(shader
, entry
->data
);
219 static uint32_t si_shader_cache_key_hash(const void *key
)
221 /* The first dword is the key size. */
222 return util_hash_crc32(key
, *(uint32_t*)key
);
225 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
227 uint32_t *keya
= (uint32_t*)a
;
228 uint32_t *keyb
= (uint32_t*)b
;
230 /* The first dword is the key size. */
234 return memcmp(keya
, keyb
, *keya
) == 0;
237 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
239 FREE((void*)entry
->key
);
243 bool si_init_shader_cache(struct si_screen
*sscreen
)
245 pipe_mutex_init(sscreen
->shader_cache_mutex
);
246 sscreen
->shader_cache
=
247 _mesa_hash_table_create(NULL
,
248 si_shader_cache_key_hash
,
249 si_shader_cache_key_equals
);
250 return sscreen
->shader_cache
!= NULL
;
253 void si_destroy_shader_cache(struct si_screen
*sscreen
)
255 if (sscreen
->shader_cache
)
256 _mesa_hash_table_destroy(sscreen
->shader_cache
,
257 si_destroy_shader_cache_entry
);
258 pipe_mutex_destroy(sscreen
->shader_cache_mutex
);
263 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
264 struct si_shader
*shader
,
265 struct si_pm4_state
*pm4
)
267 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
268 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
269 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
270 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
271 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
272 unsigned type
, partitioning
, topology
, distribution_mode
;
274 switch (tes_prim_mode
) {
275 case PIPE_PRIM_LINES
:
276 type
= V_028B6C_TESS_ISOLINE
;
278 case PIPE_PRIM_TRIANGLES
:
279 type
= V_028B6C_TESS_TRIANGLE
;
281 case PIPE_PRIM_QUADS
:
282 type
= V_028B6C_TESS_QUAD
;
289 switch (tes_spacing
) {
290 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
291 partitioning
= V_028B6C_PART_FRAC_ODD
;
293 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
294 partitioning
= V_028B6C_PART_FRAC_EVEN
;
296 case PIPE_TESS_SPACING_EQUAL
:
297 partitioning
= V_028B6C_PART_INTEGER
;
305 topology
= V_028B6C_OUTPUT_POINT
;
306 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
307 topology
= V_028B6C_OUTPUT_LINE
;
308 else if (tes_vertex_order_cw
)
309 /* for some reason, this must be the other way around */
310 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
312 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
314 if (sscreen
->has_distributed_tess
) {
315 if (sscreen
->b
.family
== CHIP_FIJI
||
316 sscreen
->b
.family
>= CHIP_POLARIS10
)
317 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
319 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
321 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
323 si_pm4_set_reg(pm4
, R_028B6C_VGT_TF_PARAM
,
324 S_028B6C_TYPE(type
) |
325 S_028B6C_PARTITIONING(partitioning
) |
326 S_028B6C_TOPOLOGY(topology
) |
327 S_028B6C_DISTRIBUTION_MODE(distribution_mode
));
330 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
333 si_pm4_clear_state(shader
->pm4
);
335 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
340 static void si_shader_ls(struct si_shader
*shader
)
342 struct si_pm4_state
*pm4
;
343 unsigned vgpr_comp_cnt
;
346 pm4
= si_get_shader_pm4_state(shader
);
350 va
= shader
->bo
->gpu_address
;
351 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
353 /* We need at least 2 components for LS.
354 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
355 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : 1;
357 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
358 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, va
>> 40);
360 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
361 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
362 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
363 S_00B528_DX10_CLAMP(1) |
364 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
365 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(SI_LS_NUM_USER_SGPR
) |
366 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
369 static void si_shader_hs(struct si_shader
*shader
)
371 struct si_pm4_state
*pm4
;
374 pm4
= si_get_shader_pm4_state(shader
);
378 va
= shader
->bo
->gpu_address
;
379 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
381 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
382 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, va
>> 40);
383 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
384 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
385 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
386 S_00B428_DX10_CLAMP(1) |
387 S_00B428_FLOAT_MODE(shader
->config
.float_mode
));
388 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
389 S_00B42C_USER_SGPR(SI_TCS_NUM_USER_SGPR
) |
390 S_00B42C_OC_LDS_EN(1) |
391 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
394 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
396 struct si_pm4_state
*pm4
;
397 unsigned num_user_sgprs
;
398 unsigned vgpr_comp_cnt
;
402 pm4
= si_get_shader_pm4_state(shader
);
406 va
= shader
->bo
->gpu_address
;
407 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
409 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
410 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : 0;
411 num_user_sgprs
= SI_ES_NUM_USER_SGPR
;
412 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
413 vgpr_comp_cnt
= 3; /* all components are needed for TES */
414 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
416 unreachable("invalid shader selector type");
418 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
420 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
421 shader
->selector
->esgs_itemsize
/ 4);
422 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
423 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
424 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
425 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
426 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
427 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
428 S_00B328_DX10_CLAMP(1) |
429 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
430 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
431 S_00B32C_USER_SGPR(num_user_sgprs
) |
432 S_00B32C_OC_LDS_EN(oc_lds_en
) |
433 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
435 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
436 si_set_tesseval_regs(sscreen
, shader
, pm4
);
440 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
443 static uint32_t si_vgt_gs_mode(struct si_shader
*shader
)
445 unsigned gs_max_vert_out
= shader
->selector
->gs_max_out_vertices
;
448 if (gs_max_vert_out
<= 128) {
449 cut_mode
= V_028A40_GS_CUT_128
;
450 } else if (gs_max_vert_out
<= 256) {
451 cut_mode
= V_028A40_GS_CUT_256
;
452 } else if (gs_max_vert_out
<= 512) {
453 cut_mode
= V_028A40_GS_CUT_512
;
455 assert(gs_max_vert_out
<= 1024);
456 cut_mode
= V_028A40_GS_CUT_1024
;
459 return S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
460 S_028A40_CUT_MODE(cut_mode
)|
461 S_028A40_ES_WRITE_OPTIMIZE(1) |
462 S_028A40_GS_WRITE_OPTIMIZE(1);
465 static void si_shader_gs(struct si_shader
*shader
)
467 unsigned gs_vert_itemsize
= shader
->selector
->gsvs_vertex_size
;
468 unsigned gsvs_itemsize
= shader
->selector
->max_gsvs_emit_size
>> 2;
469 unsigned gs_num_invocations
= shader
->selector
->gs_num_invocations
;
470 struct si_pm4_state
*pm4
;
472 unsigned max_stream
= shader
->selector
->max_gs_stream
;
474 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
475 assert(gsvs_itemsize
< (1 << 15));
477 pm4
= si_get_shader_pm4_state(shader
);
481 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, si_vgt_gs_mode(shader
));
483 si_pm4_set_reg(pm4
, R_028A60_VGT_GSVS_RING_OFFSET_1
, gsvs_itemsize
);
484 si_pm4_set_reg(pm4
, R_028A64_VGT_GSVS_RING_OFFSET_2
, gsvs_itemsize
* ((max_stream
>= 2) ? 2 : 1));
485 si_pm4_set_reg(pm4
, R_028A68_VGT_GSVS_RING_OFFSET_3
, gsvs_itemsize
* ((max_stream
>= 3) ? 3 : 1));
487 si_pm4_set_reg(pm4
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, gsvs_itemsize
* (max_stream
+ 1));
489 si_pm4_set_reg(pm4
, R_028B38_VGT_GS_MAX_VERT_OUT
, shader
->selector
->gs_max_out_vertices
);
491 si_pm4_set_reg(pm4
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, gs_vert_itemsize
>> 2);
492 si_pm4_set_reg(pm4
, R_028B60_VGT_GS_VERT_ITEMSIZE_1
, (max_stream
>= 1) ? gs_vert_itemsize
>> 2 : 0);
493 si_pm4_set_reg(pm4
, R_028B64_VGT_GS_VERT_ITEMSIZE_2
, (max_stream
>= 2) ? gs_vert_itemsize
>> 2 : 0);
494 si_pm4_set_reg(pm4
, R_028B68_VGT_GS_VERT_ITEMSIZE_3
, (max_stream
>= 3) ? gs_vert_itemsize
>> 2 : 0);
496 si_pm4_set_reg(pm4
, R_028B90_VGT_GS_INSTANCE_CNT
,
497 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
498 S_028B90_ENABLE(gs_num_invocations
> 0));
500 va
= shader
->bo
->gpu_address
;
501 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
502 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
503 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, va
>> 40);
505 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
506 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
507 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
508 S_00B228_DX10_CLAMP(1) |
509 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
510 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
511 S_00B22C_USER_SGPR(SI_GS_NUM_USER_SGPR
) |
512 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
516 * Compute the state for \p shader, which will run as a vertex shader on the
519 * If \p gs is non-NULL, it points to the geometry shader for which this shader
520 * is the copy shader.
522 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
523 struct si_shader
*gs
)
525 struct si_pm4_state
*pm4
;
526 unsigned num_user_sgprs
;
527 unsigned nparams
, vgpr_comp_cnt
;
530 unsigned window_space
=
531 shader
->selector
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
532 bool enable_prim_id
= si_vs_exports_prim_id(shader
);
534 pm4
= si_get_shader_pm4_state(shader
);
538 /* We always write VGT_GS_MODE in the VS state, because every switch
539 * between different shader pipelines involving a different GS or no
540 * GS at all involves a switch of the VS (different GS use different
541 * copy shaders). On the other hand, when the API switches from a GS to
542 * no GS and then back to the same GS used originally, the GS state is
546 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
,
547 S_028A40_MODE(enable_prim_id
? V_028A40_GS_SCENARIO_A
: 0));
548 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, enable_prim_id
);
550 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, si_vgt_gs_mode(gs
));
551 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
554 va
= shader
->bo
->gpu_address
;
555 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
558 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
559 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
560 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
561 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : (enable_prim_id
? 2 : 0);
562 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
563 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
564 vgpr_comp_cnt
= 3; /* all components are needed for TES */
565 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
567 unreachable("invalid shader selector type");
569 /* VS is required to export at least one param. */
570 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
571 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
572 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
574 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
575 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
576 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
577 V_02870C_SPI_SHADER_4COMP
:
578 V_02870C_SPI_SHADER_NONE
) |
579 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
580 V_02870C_SPI_SHADER_4COMP
:
581 V_02870C_SPI_SHADER_NONE
) |
582 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
583 V_02870C_SPI_SHADER_4COMP
:
584 V_02870C_SPI_SHADER_NONE
));
586 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
588 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
589 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, va
>> 40);
590 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
591 S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
592 S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
593 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
594 S_00B128_DX10_CLAMP(1) |
595 S_00B128_FLOAT_MODE(shader
->config
.float_mode
));
596 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
597 S_00B12C_USER_SGPR(num_user_sgprs
) |
598 S_00B12C_OC_LDS_EN(oc_lds_en
) |
599 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
600 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
601 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
602 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
603 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
) |
604 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
606 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
607 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
609 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
610 S_028818_VTX_W0_FMT(1) |
611 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
612 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
613 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
615 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
616 si_set_tesseval_regs(sscreen
, shader
, pm4
);
619 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
621 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
622 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
623 !!(info
->colors_read
& 0xf0);
624 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
625 (ps
->key
.ps
.prolog
.color_two_side
? num_colors
: 0);
627 assert(num_interp
<= 32);
628 return MIN2(num_interp
, 32);
631 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
633 unsigned value
= shader
->key
.ps
.epilog
.spi_shader_col_format
;
634 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
636 /* If the i-th target format is set, all previous target formats must
637 * be non-zero to avoid hangs.
639 for (i
= 0; i
< num_targets
; i
++)
640 if (!(value
& (0xf << (i
* 4))))
641 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
646 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format
)
648 unsigned i
, cb_shader_mask
= 0;
650 for (i
= 0; i
< 8; i
++) {
651 switch ((spi_shader_col_format
>> (i
* 4)) & 0xf) {
652 case V_028714_SPI_SHADER_ZERO
:
654 case V_028714_SPI_SHADER_32_R
:
655 cb_shader_mask
|= 0x1 << (i
* 4);
657 case V_028714_SPI_SHADER_32_GR
:
658 cb_shader_mask
|= 0x3 << (i
* 4);
660 case V_028714_SPI_SHADER_32_AR
:
661 cb_shader_mask
|= 0x9 << (i
* 4);
663 case V_028714_SPI_SHADER_FP16_ABGR
:
664 case V_028714_SPI_SHADER_UNORM16_ABGR
:
665 case V_028714_SPI_SHADER_SNORM16_ABGR
:
666 case V_028714_SPI_SHADER_UINT16_ABGR
:
667 case V_028714_SPI_SHADER_SINT16_ABGR
:
668 case V_028714_SPI_SHADER_32_ABGR
:
669 cb_shader_mask
|= 0xf << (i
* 4);
675 return cb_shader_mask
;
678 static void si_shader_ps(struct si_shader
*shader
)
680 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
681 struct si_pm4_state
*pm4
;
682 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
683 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
685 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
687 /* we need to enable at least one of them, otherwise we hang the GPU */
688 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
689 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
690 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
691 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
692 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
693 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
694 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
695 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
696 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
697 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
698 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
699 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
700 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
701 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
703 /* Validate interpolation optimization flags (read as implications). */
704 assert(!shader
->key
.ps
.prolog
.bc_optimize_for_persp
||
705 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
706 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
707 assert(!shader
->key
.ps
.prolog
.bc_optimize_for_linear
||
708 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
709 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
710 assert(!shader
->key
.ps
.prolog
.force_persp_center_interp
||
711 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
712 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
713 assert(!shader
->key
.ps
.prolog
.force_linear_center_interp
||
714 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
715 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
716 assert(!shader
->key
.ps
.prolog
.force_persp_sample_interp
||
717 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
718 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
719 assert(!shader
->key
.ps
.prolog
.force_linear_sample_interp
||
720 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
721 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
723 /* Validate cases when the optimizations are off (read as implications). */
724 assert(shader
->key
.ps
.prolog
.bc_optimize_for_persp
||
725 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
726 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
727 assert(shader
->key
.ps
.prolog
.bc_optimize_for_linear
||
728 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
729 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
731 pm4
= si_get_shader_pm4_state(shader
);
735 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
737 * 0 -> Position = pixel center
738 * 1 -> Position = pixel centroid
739 * 2 -> Position = at sample position
741 * From GLSL 4.5 specification, section 7.1:
742 * "The variable gl_FragCoord is available as an input variable from
743 * within fragment shaders and it holds the window relative coordinates
744 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
745 * value can be for any location within the pixel, or one of the
746 * fragment samples. The use of centroid does not further restrict
747 * this value to be inside the current primitive."
749 * Meaning that centroid has no effect and we can return anything within
750 * the pixel. Thus, return the value at sample position, because that's
751 * the most accurate one shaders can get.
753 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
755 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
756 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
757 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
759 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
760 cb_shader_mask
= si_get_cb_shader_mask(spi_shader_col_format
);
762 /* Ensure that some export memory is always allocated, for two reasons:
764 * 1) Correctness: The hardware ignores the EXEC mask if no export
765 * memory is allocated, so KILL and alpha test do not work correctly
767 * 2) Performance: Every shader needs at least a NULL export, even when
768 * it writes no color/depth output. The NULL export instruction
769 * stalls without this setting.
771 * Don't add this to CB_SHADER_MASK.
773 if (!spi_shader_col_format
&&
774 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
775 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
777 si_pm4_set_reg(pm4
, R_0286CC_SPI_PS_INPUT_ENA
, input_ena
);
778 si_pm4_set_reg(pm4
, R_0286D0_SPI_PS_INPUT_ADDR
,
779 shader
->config
.spi_ps_input_addr
);
781 /* Set interpolation controls. */
782 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
));
785 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
786 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
788 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
,
789 si_get_spi_shader_z_format(info
->writes_z
,
790 info
->writes_stencil
,
791 info
->writes_samplemask
));
793 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
, spi_shader_col_format
);
794 si_pm4_set_reg(pm4
, R_02823C_CB_SHADER_MASK
, cb_shader_mask
);
796 va
= shader
->bo
->gpu_address
;
797 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
798 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
799 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, va
>> 40);
801 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
802 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
803 S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
804 S_00B028_DX10_CLAMP(1) |
805 S_00B028_FLOAT_MODE(shader
->config
.float_mode
));
806 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
807 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
808 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
809 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
811 /* DON'T USE EARLY_Z_THEN_RE_Z !!!
813 * It decreases performance by 15% in DiRT: Showdown on Ultra settings.
814 * And it has pretty complex shaders.
816 * Shaders with side effects that must execute independently of the
817 * depth test require LATE_Z.
819 if (info
->writes_memory
&&
820 !info
->properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
])
821 shader
->z_order
= V_02880C_LATE_Z
;
823 shader
->z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
826 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
827 struct si_shader
*shader
)
829 switch (shader
->selector
->type
) {
830 case PIPE_SHADER_VERTEX
:
831 if (shader
->key
.vs
.as_ls
)
832 si_shader_ls(shader
);
833 else if (shader
->key
.vs
.as_es
)
834 si_shader_es(sscreen
, shader
);
836 si_shader_vs(sscreen
, shader
, NULL
);
838 case PIPE_SHADER_TESS_CTRL
:
839 si_shader_hs(shader
);
841 case PIPE_SHADER_TESS_EVAL
:
842 if (shader
->key
.tes
.as_es
)
843 si_shader_es(sscreen
, shader
);
845 si_shader_vs(sscreen
, shader
, NULL
);
847 case PIPE_SHADER_GEOMETRY
:
848 si_shader_gs(shader
);
849 si_shader_vs(sscreen
, shader
->gs_copy_shader
, shader
);
851 case PIPE_SHADER_FRAGMENT
:
852 si_shader_ps(shader
);
859 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
861 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
862 if (sctx
->queued
.named
.dsa
&&
863 !sctx
->framebuffer
.cb0_is_integer
)
864 return sctx
->queued
.named
.dsa
->alpha_func
;
866 return PIPE_FUNC_ALWAYS
;
869 /* Compute the key for the hw shader variant */
870 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
871 struct si_shader_selector
*sel
,
872 union si_shader_key
*key
)
874 struct si_context
*sctx
= (struct si_context
*)ctx
;
877 memset(key
, 0, sizeof(*key
));
880 case PIPE_SHADER_VERTEX
:
881 if (sctx
->vertex_elements
) {
882 unsigned count
= MIN2(sel
->info
.num_inputs
,
883 sctx
->vertex_elements
->count
);
884 for (i
= 0; i
< count
; ++i
)
885 key
->vs
.prolog
.instance_divisors
[i
] =
886 sctx
->vertex_elements
->elements
[i
].instance_divisor
;
888 if (sctx
->tes_shader
.cso
)
890 else if (sctx
->gs_shader
.cso
)
893 if (!sctx
->gs_shader
.cso
&& sctx
->ps_shader
.cso
&&
894 sctx
->ps_shader
.cso
->info
.uses_primid
)
895 key
->vs
.epilog
.export_prim_id
= 1;
897 case PIPE_SHADER_TESS_CTRL
:
898 key
->tcs
.epilog
.prim_mode
=
899 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
901 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
902 key
->tcs
.epilog
.inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
904 case PIPE_SHADER_TESS_EVAL
:
905 if (sctx
->gs_shader
.cso
)
907 else if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
908 key
->tes
.epilog
.export_prim_id
= 1;
910 case PIPE_SHADER_GEOMETRY
:
912 case PIPE_SHADER_FRAGMENT
: {
913 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
914 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
916 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
917 sel
->info
.colors_written
== 0x1)
918 key
->ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
921 /* Select the shader color format based on whether
922 * blending or alpha are needed.
924 key
->ps
.epilog
.spi_shader_col_format
=
925 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
926 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
927 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
928 sctx
->framebuffer
.spi_shader_col_format_blend
) |
929 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
930 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
931 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
932 sctx
->framebuffer
.spi_shader_col_format
);
934 /* The output for dual source blending should have
935 * the same format as the first output.
937 if (blend
->dual_src_blend
)
938 key
->ps
.epilog
.spi_shader_col_format
|=
939 (key
->ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
941 key
->ps
.epilog
.spi_shader_col_format
= sctx
->framebuffer
.spi_shader_col_format
;
943 /* If alpha-to-coverage is enabled, we have to export alpha
944 * even if there is no color buffer.
946 if (!(key
->ps
.epilog
.spi_shader_col_format
& 0xf) &&
947 blend
&& blend
->alpha_to_coverage
)
948 key
->ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
950 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
951 * to the range supported by the type if a channel has less
952 * than 16 bits and the export format is 16_ABGR.
954 if (sctx
->b
.chip_class
<= CIK
&& sctx
->b
.family
!= CHIP_HAWAII
)
955 key
->ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
957 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
958 if (!key
->ps
.epilog
.last_cbuf
) {
959 key
->ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
960 key
->ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
964 bool is_poly
= (sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES
&&
965 sctx
->current_rast_prim
<= PIPE_PRIM_POLYGON
) ||
966 sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES_ADJACENCY
;
967 bool is_line
= !is_poly
&& sctx
->current_rast_prim
!= PIPE_PRIM_POINTS
;
969 key
->ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
970 key
->ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
972 if (sctx
->queued
.named
.blend
) {
973 key
->ps
.epilog
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
974 rs
->multisample_enable
&&
975 !sctx
->framebuffer
.cb0_is_integer
;
978 key
->ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
979 key
->ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
980 (is_line
&& rs
->line_smooth
)) &&
981 sctx
->framebuffer
.nr_samples
<= 1;
982 key
->ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
984 if (rs
->force_persample_interp
&&
985 rs
->multisample_enable
&&
986 sctx
->framebuffer
.nr_samples
> 1 &&
987 sctx
->ps_iter_samples
> 1) {
988 key
->ps
.prolog
.force_persp_sample_interp
=
989 sel
->info
.uses_persp_center
||
990 sel
->info
.uses_persp_centroid
;
992 key
->ps
.prolog
.force_linear_sample_interp
=
993 sel
->info
.uses_linear_center
||
994 sel
->info
.uses_linear_centroid
;
995 } else if (rs
->multisample_enable
&&
996 sctx
->framebuffer
.nr_samples
> 1) {
997 key
->ps
.prolog
.bc_optimize_for_persp
=
998 sel
->info
.uses_persp_center
&&
999 sel
->info
.uses_persp_centroid
;
1000 key
->ps
.prolog
.bc_optimize_for_linear
=
1001 sel
->info
.uses_linear_center
&&
1002 sel
->info
.uses_linear_centroid
;
1004 /* Make sure SPI doesn't compute more than 1 pair
1005 * of (i,j), which is the optimization here. */
1006 key
->ps
.prolog
.force_persp_center_interp
=
1007 sel
->info
.uses_persp_center
+
1008 sel
->info
.uses_persp_centroid
+
1009 sel
->info
.uses_persp_sample
> 1;
1011 key
->ps
.prolog
.force_linear_center_interp
=
1012 sel
->info
.uses_linear_center
+
1013 sel
->info
.uses_linear_centroid
+
1014 sel
->info
.uses_linear_sample
> 1;
1018 key
->ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
1026 /* Select the hw shader variant depending on the current state. */
1027 static int si_shader_select_with_key(struct si_screen
*sscreen
,
1028 struct si_shader_ctx_state
*state
,
1029 union si_shader_key
*key
,
1030 LLVMTargetMachineRef tm
,
1031 struct pipe_debug_callback
*debug
,
1033 bool is_debug_context
)
1035 struct si_shader_selector
*sel
= state
->cso
;
1036 struct si_shader
*current
= state
->current
;
1037 struct si_shader
*iter
, *shader
= NULL
;
1040 /* Check if we don't need to change anything.
1041 * This path is also used for most shaders that don't need multiple
1042 * variants, it will cost just a computation of the key and this
1044 if (likely(current
&& memcmp(¤t
->key
, key
, sizeof(*key
)) == 0))
1047 /* This must be done before the mutex is locked, because async GS
1048 * compilation calls this function too, and therefore must enter
1052 util_queue_job_wait(&sel
->ready
);
1054 pipe_mutex_lock(sel
->mutex
);
1056 /* Find the shader variant. */
1057 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
1058 /* Don't check the "current" shader. We checked it above. */
1059 if (current
!= iter
&&
1060 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
1061 state
->current
= iter
;
1062 pipe_mutex_unlock(sel
->mutex
);
1067 /* Build a new shader. */
1068 shader
= CALLOC_STRUCT(si_shader
);
1070 pipe_mutex_unlock(sel
->mutex
);
1073 shader
->selector
= sel
;
1076 r
= si_shader_create(sscreen
, tm
, shader
, debug
);
1078 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1081 pipe_mutex_unlock(sel
->mutex
);
1085 if (is_debug_context
) {
1086 FILE *f
= open_memstream(&shader
->shader_log
,
1087 &shader
->shader_log_size
);
1089 si_shader_dump(sscreen
, shader
, NULL
, sel
->type
, f
);
1094 si_shader_init_pm4_state(sscreen
, shader
);
1096 if (!sel
->last_variant
) {
1097 sel
->first_variant
= shader
;
1098 sel
->last_variant
= shader
;
1100 sel
->last_variant
->next_variant
= shader
;
1101 sel
->last_variant
= shader
;
1103 state
->current
= shader
;
1104 pipe_mutex_unlock(sel
->mutex
);
1108 static int si_shader_select(struct pipe_context
*ctx
,
1109 struct si_shader_ctx_state
*state
)
1111 struct si_context
*sctx
= (struct si_context
*)ctx
;
1112 union si_shader_key key
;
1114 si_shader_selector_key(ctx
, state
->cso
, &key
);
1115 return si_shader_select_with_key(sctx
->screen
, state
, &key
,
1116 sctx
->tm
, &sctx
->b
.debug
, true,
1120 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
1121 union si_shader_key
*key
)
1123 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
1125 switch (info
->processor
) {
1126 case PIPE_SHADER_VERTEX
:
1127 switch (next_shader
) {
1128 case PIPE_SHADER_GEOMETRY
:
1131 case PIPE_SHADER_TESS_CTRL
:
1132 case PIPE_SHADER_TESS_EVAL
:
1138 case PIPE_SHADER_TESS_EVAL
:
1139 if (next_shader
== PIPE_SHADER_GEOMETRY
)
1146 * Compile the main shader part or the monolithic shader as part of
1147 * si_shader_selector initialization. Since it can be done asynchronously,
1148 * there is no way to report compile failures to applications.
1150 void si_init_shader_selector_async(void *job
, int thread_index
)
1152 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
1153 struct si_screen
*sscreen
= sel
->screen
;
1154 LLVMTargetMachineRef tm
;
1155 struct pipe_debug_callback
*debug
= &sel
->debug
;
1158 if (thread_index
>= 0) {
1159 assert(thread_index
< ARRAY_SIZE(sscreen
->tm
));
1160 tm
= sscreen
->tm
[thread_index
];
1167 /* Compile the main shader part for use with a prolog and/or epilog.
1168 * If this fails, the driver will try to compile a monolithic shader
1171 if (sel
->type
!= PIPE_SHADER_GEOMETRY
&&
1172 !sscreen
->use_monolithic_shaders
) {
1173 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
1177 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
1181 shader
->selector
= sel
;
1182 si_parse_next_shader_property(&sel
->info
, &shader
->key
);
1184 tgsi_binary
= si_get_tgsi_binary(sel
);
1186 /* Try to load the shader from the shader cache. */
1187 pipe_mutex_lock(sscreen
->shader_cache_mutex
);
1190 si_shader_cache_load_shader(sscreen
, tgsi_binary
, shader
)) {
1192 pipe_mutex_unlock(sscreen
->shader_cache_mutex
);
1194 pipe_mutex_unlock(sscreen
->shader_cache_mutex
);
1196 /* Compile the shader if it hasn't been loaded from the cache. */
1197 if (si_compile_tgsi_shader(sscreen
, tm
, shader
, false,
1201 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
1206 pipe_mutex_lock(sscreen
->shader_cache_mutex
);
1207 if (!si_shader_cache_insert_shader(sscreen
, tgsi_binary
, shader
))
1209 pipe_mutex_unlock(sscreen
->shader_cache_mutex
);
1213 sel
->main_shader_part
= shader
;
1216 /* Pre-compilation. */
1217 if (sel
->type
== PIPE_SHADER_GEOMETRY
||
1218 sscreen
->b
.debug_flags
& DBG_PRECOMPILE
) {
1219 struct si_shader_ctx_state state
= {sel
};
1220 union si_shader_key key
;
1222 memset(&key
, 0, sizeof(key
));
1223 si_parse_next_shader_property(&sel
->info
, &key
);
1225 /* Set reasonable defaults, so that the shader key doesn't
1226 * cause any code to be eliminated.
1228 switch (sel
->type
) {
1229 case PIPE_SHADER_TESS_CTRL
:
1230 key
.tcs
.epilog
.prim_mode
= PIPE_PRIM_TRIANGLES
;
1232 case PIPE_SHADER_FRAGMENT
:
1233 key
.ps
.prolog
.bc_optimize_for_persp
=
1234 sel
->info
.uses_persp_center
&&
1235 sel
->info
.uses_persp_centroid
;
1236 key
.ps
.prolog
.bc_optimize_for_linear
=
1237 sel
->info
.uses_linear_center
&&
1238 sel
->info
.uses_linear_centroid
;
1239 key
.ps
.epilog
.alpha_func
= PIPE_FUNC_ALWAYS
;
1240 for (i
= 0; i
< 8; i
++)
1241 if (sel
->info
.colors_written
& (1 << i
))
1242 key
.ps
.epilog
.spi_shader_col_format
|=
1243 V_028710_SPI_SHADER_FP16_ABGR
<< (i
* 4);
1247 if (si_shader_select_with_key(sscreen
, &state
, &key
, tm
, debug
,
1248 false, sel
->is_debug_context
))
1249 fprintf(stderr
, "radeonsi: can't create a monolithic shader\n");
1253 static void *si_create_shader_selector(struct pipe_context
*ctx
,
1254 const struct pipe_shader_state
*state
)
1256 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
1257 struct si_context
*sctx
= (struct si_context
*)ctx
;
1258 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
1264 sel
->screen
= sscreen
;
1266 sel
->debug
= sctx
->b
.debug
;
1267 sel
->is_debug_context
= sctx
->is_debug
;
1268 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
1274 sel
->so
= state
->stream_output
;
1275 tgsi_scan_shader(state
->tokens
, &sel
->info
);
1276 sel
->type
= sel
->info
.processor
;
1277 p_atomic_inc(&sscreen
->b
.num_shaders_created
);
1279 /* Set which opcode uses which (i,j) pair. */
1280 if (sel
->info
.uses_persp_opcode_interp_centroid
)
1281 sel
->info
.uses_persp_centroid
= true;
1283 if (sel
->info
.uses_linear_opcode_interp_centroid
)
1284 sel
->info
.uses_linear_centroid
= true;
1286 if (sel
->info
.uses_persp_opcode_interp_offset
||
1287 sel
->info
.uses_persp_opcode_interp_sample
)
1288 sel
->info
.uses_persp_center
= true;
1290 if (sel
->info
.uses_linear_opcode_interp_offset
||
1291 sel
->info
.uses_linear_opcode_interp_sample
)
1292 sel
->info
.uses_linear_center
= true;
1294 switch (sel
->type
) {
1295 case PIPE_SHADER_GEOMETRY
:
1296 sel
->gs_output_prim
=
1297 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
1298 sel
->gs_max_out_vertices
=
1299 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
1300 sel
->gs_num_invocations
=
1301 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
1302 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
1303 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
1304 sel
->gs_max_out_vertices
;
1306 sel
->max_gs_stream
= 0;
1307 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
1308 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
1309 sel
->so
.output
[i
].stream
);
1311 sel
->gs_input_verts_per_prim
=
1312 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
1315 case PIPE_SHADER_TESS_CTRL
:
1316 /* Always reserve space for these. */
1317 sel
->patch_outputs_written
|=
1318 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER
, 0)) |
1319 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER
, 0));
1321 case PIPE_SHADER_VERTEX
:
1322 case PIPE_SHADER_TESS_EVAL
:
1323 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
1324 unsigned name
= sel
->info
.output_semantic_name
[i
];
1325 unsigned index
= sel
->info
.output_semantic_index
[i
];
1328 case TGSI_SEMANTIC_TESSINNER
:
1329 case TGSI_SEMANTIC_TESSOUTER
:
1330 case TGSI_SEMANTIC_PATCH
:
1331 sel
->patch_outputs_written
|=
1332 1llu << si_shader_io_get_unique_index(name
, index
);
1335 sel
->outputs_written
|=
1336 1llu << si_shader_io_get_unique_index(name
, index
);
1339 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
1342 case PIPE_SHADER_FRAGMENT
:
1343 for (i
= 0; i
< 8; i
++)
1344 if (sel
->info
.colors_written
& (1 << i
))
1345 sel
->colors_written_4bit
|= 0xf << (4 * i
);
1347 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
1348 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
1349 int index
= sel
->info
.input_semantic_index
[i
];
1350 sel
->color_attr_index
[index
] = i
;
1356 /* DB_SHADER_CONTROL */
1357 sel
->db_shader_control
=
1358 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
1359 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
1360 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
1361 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
1363 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
1364 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
1365 sel
->db_shader_control
|=
1366 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
1368 case TGSI_FS_DEPTH_LAYOUT_LESS
:
1369 sel
->db_shader_control
|=
1370 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
1374 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
])
1375 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1);
1377 if (sel
->info
.writes_memory
)
1378 sel
->db_shader_control
|= S_02880C_EXEC_ON_HIER_FAIL(1) |
1379 S_02880C_EXEC_ON_NOOP(1);
1380 pipe_mutex_init(sel
->mutex
);
1381 util_queue_fence_init(&sel
->ready
);
1383 if ((sctx
->b
.debug
.debug_message
&& !sctx
->b
.debug
.async
) ||
1385 r600_can_dump_shader(&sscreen
->b
, sel
->info
.processor
) ||
1386 !util_queue_is_initialized(&sscreen
->shader_compiler_queue
))
1387 si_init_shader_selector_async(sel
, -1);
1389 util_queue_add_job(&sscreen
->shader_compiler_queue
, sel
,
1390 &sel
->ready
, si_init_shader_selector_async
,
1396 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
1398 struct si_context
*sctx
= (struct si_context
*)ctx
;
1399 struct si_shader_selector
*sel
= state
;
1401 if (sctx
->vs_shader
.cso
== sel
)
1404 sctx
->vs_shader
.cso
= sel
;
1405 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
1406 sctx
->do_update_shaders
= true;
1407 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1408 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
1411 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
1413 struct si_context
*sctx
= (struct si_context
*)ctx
;
1414 struct si_shader_selector
*sel
= state
;
1415 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
1417 if (sctx
->gs_shader
.cso
== sel
)
1420 sctx
->gs_shader
.cso
= sel
;
1421 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
1422 sctx
->do_update_shaders
= true;
1423 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1424 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
1427 si_shader_change_notify(sctx
);
1428 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
1431 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
1433 struct si_context
*sctx
= (struct si_context
*)ctx
;
1434 struct si_shader_selector
*sel
= state
;
1435 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
1437 if (sctx
->tcs_shader
.cso
== sel
)
1440 sctx
->tcs_shader
.cso
= sel
;
1441 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
1442 sctx
->do_update_shaders
= true;
1445 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
1448 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
1450 struct si_context
*sctx
= (struct si_context
*)ctx
;
1451 struct si_shader_selector
*sel
= state
;
1452 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
1454 if (sctx
->tes_shader
.cso
== sel
)
1457 sctx
->tes_shader
.cso
= sel
;
1458 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
1459 sctx
->do_update_shaders
= true;
1460 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1461 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
1463 if (enable_changed
) {
1464 si_shader_change_notify(sctx
);
1465 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
1467 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
1470 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
1472 struct si_context
*sctx
= (struct si_context
*)ctx
;
1473 struct si_shader_selector
*sel
= state
;
1475 /* skip if supplied shader is one already in use */
1476 if (sctx
->ps_shader
.cso
== sel
)
1479 sctx
->ps_shader
.cso
= sel
;
1480 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
1481 sctx
->do_update_shaders
= true;
1482 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
1485 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
1488 switch (shader
->selector
->type
) {
1489 case PIPE_SHADER_VERTEX
:
1490 if (shader
->key
.vs
.as_ls
)
1491 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
1492 else if (shader
->key
.vs
.as_es
)
1493 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
1495 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
1497 case PIPE_SHADER_TESS_CTRL
:
1498 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
1500 case PIPE_SHADER_TESS_EVAL
:
1501 if (shader
->key
.tes
.as_es
)
1502 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
1504 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
1506 case PIPE_SHADER_GEOMETRY
:
1507 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
1508 si_pm4_delete_state(sctx
, vs
, shader
->gs_copy_shader
->pm4
);
1510 case PIPE_SHADER_FRAGMENT
:
1511 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
1516 si_shader_destroy(shader
);
1520 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
1522 struct si_context
*sctx
= (struct si_context
*)ctx
;
1523 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
1524 struct si_shader
*p
= sel
->first_variant
, *c
;
1525 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
1526 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
1527 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
1528 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
1529 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
1530 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
1533 util_queue_job_wait(&sel
->ready
);
1535 if (current_shader
[sel
->type
]->cso
== sel
) {
1536 current_shader
[sel
->type
]->cso
= NULL
;
1537 current_shader
[sel
->type
]->current
= NULL
;
1541 c
= p
->next_variant
;
1542 si_delete_shader(sctx
, p
);
1546 if (sel
->main_shader_part
)
1547 si_delete_shader(sctx
, sel
->main_shader_part
);
1549 util_queue_fence_destroy(&sel
->ready
);
1550 pipe_mutex_destroy(sel
->mutex
);
1555 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
1556 struct si_shader
*vs
, unsigned name
,
1557 unsigned index
, unsigned interpolate
)
1559 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
1560 unsigned j
, ps_input_cntl
= 0;
1562 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
1563 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
))
1564 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
1566 if (name
== TGSI_SEMANTIC_PCOORD
||
1567 (name
== TGSI_SEMANTIC_TEXCOORD
&&
1568 sctx
->sprite_coord_enable
& (1 << index
))) {
1569 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
1572 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
1573 if (name
== vsinfo
->output_semantic_name
[j
] &&
1574 index
== vsinfo
->output_semantic_index
[j
]) {
1575 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[j
]);
1580 if (name
== TGSI_SEMANTIC_PRIMID
)
1581 /* PrimID is written after the last output. */
1582 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
1583 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
1584 /* No corresponding output found, load defaults into input.
1585 * Don't set any other bits.
1586 * (FLAT_SHADE=1 completely changes behavior) */
1587 ps_input_cntl
= S_028644_OFFSET(0x20);
1588 /* D3D 9 behaviour. GL is undefined */
1589 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
1590 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
1592 return ps_input_cntl
;
1595 static void si_emit_spi_map(struct si_context
*sctx
, struct r600_atom
*atom
)
1597 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1598 struct si_shader
*ps
= sctx
->ps_shader
.current
;
1599 struct si_shader
*vs
= si_get_vs_state(sctx
);
1600 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
1601 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
1603 if (!ps
|| !ps
->selector
->info
.num_inputs
)
1606 num_interp
= si_get_ps_num_interp(ps
);
1607 assert(num_interp
> 0);
1608 radeon_set_context_reg_seq(cs
, R_028644_SPI_PS_INPUT_CNTL_0
, num_interp
);
1610 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
1611 unsigned name
= psinfo
->input_semantic_name
[i
];
1612 unsigned index
= psinfo
->input_semantic_index
[i
];
1613 unsigned interpolate
= psinfo
->input_interpolate
[i
];
1615 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, name
, index
,
1619 if (name
== TGSI_SEMANTIC_COLOR
) {
1620 assert(index
< ARRAY_SIZE(bcol_interp
));
1621 bcol_interp
[index
] = interpolate
;
1625 if (ps
->key
.ps
.prolog
.color_two_side
) {
1626 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
1628 for (i
= 0; i
< 2; i
++) {
1629 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
1632 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, bcol
,
1633 i
, bcol_interp
[i
]));
1637 assert(num_interp
== num_written
);
1641 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1643 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
1645 if (sctx
->init_config_has_vgt_flush
)
1648 /* Done by Vulkan before VGT_FLUSH. */
1649 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
1650 si_pm4_cmd_add(sctx
->init_config
,
1651 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1652 si_pm4_cmd_end(sctx
->init_config
, false);
1654 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
1655 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
1656 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1657 si_pm4_cmd_end(sctx
->init_config
, false);
1658 sctx
->init_config_has_vgt_flush
= true;
1661 /* Initialize state related to ESGS / GSVS ring buffers */
1662 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
1664 struct si_shader_selector
*es
=
1665 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
1666 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
1667 struct si_pm4_state
*pm4
;
1669 /* Chip constants. */
1670 unsigned num_se
= sctx
->screen
->b
.info
.max_se
;
1671 unsigned wave_size
= 64;
1672 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1673 unsigned gs_vertex_reuse
= 16 * num_se
; /* GS_VERTEX_REUSE register (per SE) */
1674 unsigned alignment
= 256 * num_se
;
1675 /* The maximum size is 63.999 MB per SE. */
1676 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1678 /* Calculate the minimum size. */
1679 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
1680 wave_size
, alignment
);
1682 /* These are recommended sizes, not minimum sizes. */
1683 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1684 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
1685 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1686 gs
->max_gsvs_emit_size
* (gs
->max_gs_stream
+ 1);
1688 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1689 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1690 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1692 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1693 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1695 /* Some rings don't have to be allocated if shaders don't use them.
1696 * (e.g. no varyings between ES and GS or GS and VS)
1698 bool update_esgs
= esgs_ring_size
&&
1699 (!sctx
->esgs_ring
||
1700 sctx
->esgs_ring
->width0
< esgs_ring_size
);
1701 bool update_gsvs
= gsvs_ring_size
&&
1702 (!sctx
->gsvs_ring
||
1703 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
1705 if (!update_esgs
&& !update_gsvs
)
1709 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
1710 sctx
->esgs_ring
= pipe_buffer_create(sctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1713 if (!sctx
->esgs_ring
)
1718 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
1719 sctx
->gsvs_ring
= pipe_buffer_create(sctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1722 if (!sctx
->gsvs_ring
)
1726 /* Create the "init_config_gs_rings" state. */
1727 pm4
= CALLOC_STRUCT(si_pm4_state
);
1731 if (sctx
->b
.chip_class
>= CIK
) {
1732 if (sctx
->esgs_ring
)
1733 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
1734 sctx
->esgs_ring
->width0
/ 256);
1735 if (sctx
->gsvs_ring
)
1736 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
1737 sctx
->gsvs_ring
->width0
/ 256);
1739 if (sctx
->esgs_ring
)
1740 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
1741 sctx
->esgs_ring
->width0
/ 256);
1742 if (sctx
->gsvs_ring
)
1743 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
1744 sctx
->gsvs_ring
->width0
/ 256);
1747 /* Set the state. */
1748 if (sctx
->init_config_gs_rings
)
1749 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
1750 sctx
->init_config_gs_rings
= pm4
;
1752 if (!sctx
->init_config_has_vgt_flush
) {
1753 si_init_config_add_vgt_flush(sctx
);
1754 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
1757 /* Flush the context to re-emit both init_config states. */
1758 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
1759 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
1761 /* Set ring bindings. */
1762 if (sctx
->esgs_ring
) {
1763 si_set_ring_buffer(&sctx
->b
.b
, SI_ES_RING_ESGS
,
1764 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
1765 true, true, 4, 64, 0);
1766 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_ESGS
,
1767 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
1768 false, false, 0, 0, 0);
1770 if (sctx
->gsvs_ring
)
1771 si_set_ring_buffer(&sctx
->b
.b
, SI_VS_RING_GSVS
,
1772 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
1773 false, false, 0, 0, 0);
1777 static void si_update_gsvs_ring_bindings(struct si_context
*sctx
)
1779 unsigned gsvs_itemsize
= sctx
->gs_shader
.cso
->max_gsvs_emit_size
;
1782 if (!sctx
->gsvs_ring
|| gsvs_itemsize
== sctx
->last_gsvs_itemsize
)
1785 sctx
->last_gsvs_itemsize
= gsvs_itemsize
;
1787 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_GSVS0
,
1788 sctx
->gsvs_ring
, gsvs_itemsize
,
1789 64, true, true, 4, 16, 0);
1791 offset
= gsvs_itemsize
* 64;
1792 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_GSVS1
,
1793 sctx
->gsvs_ring
, gsvs_itemsize
,
1794 64, true, true, 4, 16, offset
);
1796 offset
= (gsvs_itemsize
* 2) * 64;
1797 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_GSVS2
,
1798 sctx
->gsvs_ring
, gsvs_itemsize
,
1799 64, true, true, 4, 16, offset
);
1801 offset
= (gsvs_itemsize
* 3) * 64;
1802 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_GSVS3
,
1803 sctx
->gsvs_ring
, gsvs_itemsize
,
1804 64, true, true, 4, 16, offset
);
1808 * @returns 1 if \p sel has been updated to use a new scratch buffer
1810 * < 0 if there was a failure
1812 static int si_update_scratch_buffer(struct si_context
*sctx
,
1813 struct si_shader
*shader
)
1815 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
1821 /* This shader doesn't need a scratch buffer */
1822 if (shader
->config
.scratch_bytes_per_wave
== 0)
1825 /* This shader is already configured to use the current
1826 * scratch buffer. */
1827 if (shader
->scratch_bo
== sctx
->scratch_buffer
)
1830 assert(sctx
->scratch_buffer
);
1832 si_shader_apply_scratch_relocs(sctx
, shader
, &shader
->config
, scratch_va
);
1834 /* Replace the shader bo with a new bo that has the relocs applied. */
1835 r
= si_shader_binary_upload(sctx
->screen
, shader
);
1839 /* Update the shader state to use the new shader bo. */
1840 si_shader_init_pm4_state(sctx
->screen
, shader
);
1842 r600_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
1847 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
1849 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
1852 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
1854 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
1857 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
1861 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
1862 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
1863 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
1864 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tcs_shader
.current
));
1865 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
1869 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
1871 unsigned current_scratch_buffer_size
=
1872 si_get_current_scratch_buffer_size(sctx
);
1873 unsigned scratch_bytes_per_wave
=
1874 si_get_max_scratch_bytes_per_wave(sctx
);
1875 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
1876 sctx
->scratch_waves
;
1877 unsigned spi_tmpring_size
;
1880 if (scratch_needed_size
> 0) {
1881 if (scratch_needed_size
> current_scratch_buffer_size
) {
1882 /* Create a bigger scratch buffer */
1883 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
1885 sctx
->scratch_buffer
=
1886 si_resource_create_custom(&sctx
->screen
->b
.b
,
1887 PIPE_USAGE_DEFAULT
, scratch_needed_size
);
1888 if (!sctx
->scratch_buffer
)
1890 sctx
->emit_scratch_reloc
= true;
1893 /* Update the shaders, so they are using the latest scratch. The
1894 * scratch buffer may have been changed since these shaders were
1895 * last used, so we still need to try to update them, even if
1896 * they require scratch buffers smaller than the current size.
1898 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
1902 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
1904 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
1908 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
1910 r
= si_update_scratch_buffer(sctx
, sctx
->tcs_shader
.current
);
1914 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
1916 /* VS can be bound as LS, ES, or VS. */
1917 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
1921 if (sctx
->tes_shader
.current
)
1922 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
1923 else if (sctx
->gs_shader
.current
)
1924 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
1926 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
1929 /* TES can be bound as ES or VS. */
1930 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
1934 if (sctx
->gs_shader
.current
)
1935 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
1937 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
1941 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1942 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
1943 "scratch size should already be aligned correctly.");
1945 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
1946 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
1947 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
1948 sctx
->spi_tmpring_size
= spi_tmpring_size
;
1949 sctx
->emit_scratch_reloc
= true;
1954 static void si_init_tess_factor_ring(struct si_context
*sctx
)
1956 bool double_offchip_buffers
= sctx
->b
.chip_class
>= CIK
;
1957 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
1958 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
1959 sctx
->screen
->b
.info
.max_se
;
1960 unsigned offchip_granularity
;
1962 switch (sctx
->screen
->tess_offchip_block_dw_size
) {
1967 offchip_granularity
= V_03093C_X_8K_DWORDS
;
1970 offchip_granularity
= V_03093C_X_4K_DWORDS
;
1974 switch (sctx
->b
.chip_class
) {
1976 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
1979 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
1983 max_offchip_buffers
= MIN2(max_offchip_buffers
, 512);
1987 assert(!sctx
->tf_ring
);
1988 sctx
->tf_ring
= pipe_buffer_create(sctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1990 32768 * sctx
->screen
->b
.info
.max_se
);
1994 assert(((sctx
->tf_ring
->width0
/ 4) & C_030938_SIZE
) == 0);
1996 sctx
->tess_offchip_ring
= pipe_buffer_create(sctx
->b
.b
.screen
,
1999 max_offchip_buffers
*
2000 sctx
->screen
->tess_offchip_block_dw_size
* 4);
2001 if (!sctx
->tess_offchip_ring
)
2004 si_init_config_add_vgt_flush(sctx
);
2006 /* Append these registers to the init config state. */
2007 if (sctx
->b
.chip_class
>= CIK
) {
2008 if (sctx
->b
.chip_class
>= VI
)
2009 --max_offchip_buffers
;
2011 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
2012 S_030938_SIZE(sctx
->tf_ring
->width0
/ 4));
2013 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
2014 r600_resource(sctx
->tf_ring
)->gpu_address
>> 8);
2015 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
2016 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
2017 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
));
2019 assert(offchip_granularity
== V_03093C_X_8K_DWORDS
);
2020 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
2021 S_008988_SIZE(sctx
->tf_ring
->width0
/ 4));
2022 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
2023 r600_resource(sctx
->tf_ring
)->gpu_address
>> 8);
2024 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
2025 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
));
2028 /* Flush the context to re-emit the init_config state.
2029 * This is done only once in a lifetime of a context.
2031 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
2032 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
2033 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
2035 si_set_ring_buffer(&sctx
->b
.b
, SI_HS_RING_TESS_FACTOR
, sctx
->tf_ring
,
2036 0, sctx
->tf_ring
->width0
, false, false, 0, 0, 0);
2038 si_set_ring_buffer(&sctx
->b
.b
, SI_HS_RING_TESS_OFFCHIP
,
2039 sctx
->tess_offchip_ring
, 0,
2040 sctx
->tess_offchip_ring
->width0
, false, false, 0, 0, 0);
2044 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
2045 * VS passes its outputs to TES directly, so the fixed-function shader only
2046 * has to write TESSOUTER and TESSINNER.
2048 static void si_generate_fixed_func_tcs(struct si_context
*sctx
)
2050 struct ureg_src outer
, inner
;
2051 struct ureg_dst tessouter
, tessinner
;
2052 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
2055 return; /* if we get here, we're screwed */
2057 assert(!sctx
->fixed_func_tcs_shader
.cso
);
2059 outer
= ureg_DECL_system_value(ureg
,
2060 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
, 0);
2061 inner
= ureg_DECL_system_value(ureg
,
2062 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
, 0);
2064 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
2065 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
2067 ureg_MOV(ureg
, tessouter
, outer
);
2068 ureg_MOV(ureg
, tessinner
, inner
);
2071 sctx
->fixed_func_tcs_shader
.cso
=
2072 ureg_create_shader_and_destroy(ureg
, &sctx
->b
.b
);
2075 static void si_update_vgt_shader_config(struct si_context
*sctx
)
2077 /* Calculate the index of the config.
2078 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
2079 unsigned index
= 2*!!sctx
->tes_shader
.cso
+ !!sctx
->gs_shader
.cso
;
2080 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[index
];
2083 uint32_t stages
= 0;
2085 *pm4
= CALLOC_STRUCT(si_pm4_state
);
2087 if (sctx
->tes_shader
.cso
) {
2088 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
2089 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2091 if (sctx
->gs_shader
.cso
)
2092 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
2094 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2096 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
2097 } else if (sctx
->gs_shader
.cso
) {
2098 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
2100 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2103 si_pm4_set_reg(*pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
2105 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
2108 static void si_update_so(struct si_context
*sctx
, struct si_shader_selector
*shader
)
2110 struct pipe_stream_output_info
*so
= &shader
->so
;
2111 uint32_t enabled_stream_buffers_mask
= 0;
2114 for (i
= 0; i
< so
->num_outputs
; i
++)
2115 enabled_stream_buffers_mask
|= (1 << so
->output
[i
].output_buffer
) << (so
->output
[i
].stream
* 4);
2116 sctx
->b
.streamout
.enabled_stream_buffers_mask
= enabled_stream_buffers_mask
;
2117 sctx
->b
.streamout
.stride_in_dw
= shader
->so
.stride
;
2120 bool si_update_shaders(struct si_context
*sctx
)
2122 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
2123 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
2126 /* Update stages before GS. */
2127 if (sctx
->tes_shader
.cso
) {
2128 if (!sctx
->tf_ring
) {
2129 si_init_tess_factor_ring(sctx
);
2135 r
= si_shader_select(ctx
, &sctx
->vs_shader
);
2138 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
2140 if (sctx
->tcs_shader
.cso
) {
2141 r
= si_shader_select(ctx
, &sctx
->tcs_shader
);
2144 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
2146 if (!sctx
->fixed_func_tcs_shader
.cso
) {
2147 si_generate_fixed_func_tcs(sctx
);
2148 if (!sctx
->fixed_func_tcs_shader
.cso
)
2152 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
);
2155 si_pm4_bind_state(sctx
, hs
,
2156 sctx
->fixed_func_tcs_shader
.current
->pm4
);
2159 r
= si_shader_select(ctx
, &sctx
->tes_shader
);
2163 if (sctx
->gs_shader
.cso
) {
2165 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
2168 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
2169 si_update_so(sctx
, sctx
->tes_shader
.cso
);
2171 } else if (sctx
->gs_shader
.cso
) {
2173 r
= si_shader_select(ctx
, &sctx
->vs_shader
);
2176 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
2179 r
= si_shader_select(ctx
, &sctx
->vs_shader
);
2182 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
2183 si_update_so(sctx
, sctx
->vs_shader
.cso
);
2187 if (sctx
->gs_shader
.cso
) {
2188 r
= si_shader_select(ctx
, &sctx
->gs_shader
);
2191 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
2192 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.current
->gs_copy_shader
->pm4
);
2193 si_update_so(sctx
, sctx
->gs_shader
.cso
);
2195 if (!si_update_gs_ring_buffers(sctx
))
2198 si_update_gsvs_ring_bindings(sctx
);
2200 si_pm4_bind_state(sctx
, gs
, NULL
);
2201 si_pm4_bind_state(sctx
, es
, NULL
);
2204 si_update_vgt_shader_config(sctx
);
2206 if (sctx
->ps_shader
.cso
) {
2207 unsigned db_shader_control
;
2209 r
= si_shader_select(ctx
, &sctx
->ps_shader
);
2212 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
2215 sctx
->ps_shader
.cso
->db_shader_control
|
2216 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
) |
2217 S_02880C_Z_ORDER(sctx
->ps_shader
.current
->z_order
);
2219 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
2220 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
2221 sctx
->flatshade
!= rs
->flatshade
) {
2222 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
2223 sctx
->flatshade
= rs
->flatshade
;
2224 si_mark_atom_dirty(sctx
, &sctx
->spi_map
);
2227 if (sctx
->b
.family
== CHIP_STONEY
&& si_pm4_state_changed(sctx
, ps
))
2228 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
2230 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
2231 sctx
->ps_db_shader_control
= db_shader_control
;
2232 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2235 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.ps
.epilog
.poly_line_smoothing
) {
2236 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.ps
.epilog
.poly_line_smoothing
;
2237 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2239 if (sctx
->b
.chip_class
== SI
)
2240 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2242 if (sctx
->framebuffer
.nr_samples
<= 1)
2243 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
2247 if (si_pm4_state_changed(sctx
, ls
) ||
2248 si_pm4_state_changed(sctx
, hs
) ||
2249 si_pm4_state_changed(sctx
, es
) ||
2250 si_pm4_state_changed(sctx
, gs
) ||
2251 si_pm4_state_changed(sctx
, vs
) ||
2252 si_pm4_state_changed(sctx
, ps
)) {
2253 if (!si_update_spi_tmpring_size(sctx
))
2257 sctx
->do_update_shaders
= false;
2261 void si_init_shader_functions(struct si_context
*sctx
)
2263 si_init_atom(sctx
, &sctx
->spi_map
, &sctx
->atoms
.s
.spi_map
, si_emit_spi_map
);
2265 sctx
->b
.b
.create_vs_state
= si_create_shader_selector
;
2266 sctx
->b
.b
.create_tcs_state
= si_create_shader_selector
;
2267 sctx
->b
.b
.create_tes_state
= si_create_shader_selector
;
2268 sctx
->b
.b
.create_gs_state
= si_create_shader_selector
;
2269 sctx
->b
.b
.create_fs_state
= si_create_shader_selector
;
2271 sctx
->b
.b
.bind_vs_state
= si_bind_vs_shader
;
2272 sctx
->b
.b
.bind_tcs_state
= si_bind_tcs_shader
;
2273 sctx
->b
.b
.bind_tes_state
= si_bind_tes_shader
;
2274 sctx
->b
.b
.bind_gs_state
= si_bind_gs_shader
;
2275 sctx
->b
.b
.bind_fs_state
= si_bind_ps_shader
;
2277 sctx
->b
.b
.delete_vs_state
= si_delete_shader_selector
;
2278 sctx
->b
.b
.delete_tcs_state
= si_delete_shader_selector
;
2279 sctx
->b
.b
.delete_tes_state
= si_delete_shader_selector
;
2280 sctx
->b
.b
.delete_gs_state
= si_delete_shader_selector
;
2281 sctx
->b
.b
.delete_fs_state
= si_delete_shader_selector
;