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radeonsi: remove function si_init_atom
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_ureg.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
36
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41
42 /* SHADER_CACHE */
43
44 /**
45 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
46 * size as integer.
47 */
48 static void *si_get_ir_binary(struct si_shader_selector *sel)
49 {
50 struct blob blob;
51 unsigned ir_size;
52 void *ir_binary;
53
54 if (sel->tokens) {
55 ir_binary = sel->tokens;
56 ir_size = tgsi_num_tokens(sel->tokens) *
57 sizeof(struct tgsi_token);
58 } else {
59 assert(sel->nir);
60
61 blob_init(&blob);
62 nir_serialize(&blob, sel->nir);
63 ir_binary = blob.data;
64 ir_size = blob.size;
65 }
66
67 unsigned size = 4 + ir_size + sizeof(sel->so);
68 char *result = (char*)MALLOC(size);
69 if (!result)
70 return NULL;
71
72 *((uint32_t*)result) = size;
73 memcpy(result + 4, ir_binary, ir_size);
74 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
75
76 if (sel->nir)
77 blob_finish(&blob);
78
79 return result;
80 }
81
82 /** Copy "data" to "ptr" and return the next dword following copied data. */
83 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
84 {
85 /* data may be NULL if size == 0 */
86 if (size)
87 memcpy(ptr, data, size);
88 ptr += DIV_ROUND_UP(size, 4);
89 return ptr;
90 }
91
92 /** Read data from "ptr". Return the next dword following the data. */
93 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
94 {
95 memcpy(data, ptr, size);
96 ptr += DIV_ROUND_UP(size, 4);
97 return ptr;
98 }
99
100 /**
101 * Write the size as uint followed by the data. Return the next dword
102 * following the copied data.
103 */
104 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
105 {
106 *ptr++ = size;
107 return write_data(ptr, data, size);
108 }
109
110 /**
111 * Read the size as uint followed by the data. Return both via parameters.
112 * Return the next dword following the data.
113 */
114 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
115 {
116 *size = *ptr++;
117 assert(*data == NULL);
118 if (!*size)
119 return ptr;
120 *data = malloc(*size);
121 return read_data(ptr, *data, *size);
122 }
123
124 /**
125 * Return the shader binary in a buffer. The first 4 bytes contain its size
126 * as integer.
127 */
128 static void *si_get_shader_binary(struct si_shader *shader)
129 {
130 /* There is always a size of data followed by the data itself. */
131 unsigned relocs_size = shader->binary.reloc_count *
132 sizeof(shader->binary.relocs[0]);
133 unsigned disasm_size = shader->binary.disasm_string ?
134 strlen(shader->binary.disasm_string) + 1 : 0;
135 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
136 strlen(shader->binary.llvm_ir_string) + 1 : 0;
137 unsigned size =
138 4 + /* total size */
139 4 + /* CRC32 of the data below */
140 align(sizeof(shader->config), 4) +
141 align(sizeof(shader->info), 4) +
142 4 + align(shader->binary.code_size, 4) +
143 4 + align(shader->binary.rodata_size, 4) +
144 4 + align(relocs_size, 4) +
145 4 + align(disasm_size, 4) +
146 4 + align(llvm_ir_size, 4);
147 void *buffer = CALLOC(1, size);
148 uint32_t *ptr = (uint32_t*)buffer;
149
150 if (!buffer)
151 return NULL;
152
153 *ptr++ = size;
154 ptr++; /* CRC32 is calculated at the end. */
155
156 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
157 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
158 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
159 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
160 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
161 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
162 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
163 assert((char *)ptr - (char *)buffer == size);
164
165 /* Compute CRC32. */
166 ptr = (uint32_t*)buffer;
167 ptr++;
168 *ptr = util_hash_crc32(ptr + 1, size - 8);
169
170 return buffer;
171 }
172
173 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
174 {
175 uint32_t *ptr = (uint32_t*)binary;
176 uint32_t size = *ptr++;
177 uint32_t crc32 = *ptr++;
178 unsigned chunk_size;
179
180 if (util_hash_crc32(ptr, size - 8) != crc32) {
181 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
182 return false;
183 }
184
185 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
186 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
187 ptr = read_chunk(ptr, (void**)&shader->binary.code,
188 &shader->binary.code_size);
189 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
190 &shader->binary.rodata_size);
191 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
192 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
193 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
194 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
195
196 return true;
197 }
198
199 /**
200 * Insert a shader into the cache. It's assumed the shader is not in the cache.
201 * Use si_shader_cache_load_shader before calling this.
202 *
203 * Returns false on failure, in which case the ir_binary should be freed.
204 */
205 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
206 void *ir_binary,
207 struct si_shader *shader,
208 bool insert_into_disk_cache)
209 {
210 void *hw_binary;
211 struct hash_entry *entry;
212 uint8_t key[CACHE_KEY_SIZE];
213
214 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
215 if (entry)
216 return false; /* already added */
217
218 hw_binary = si_get_shader_binary(shader);
219 if (!hw_binary)
220 return false;
221
222 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
223 hw_binary) == NULL) {
224 FREE(hw_binary);
225 return false;
226 }
227
228 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
229 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
230 *((uint32_t *)ir_binary), key);
231 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
232 *((uint32_t *) hw_binary), NULL);
233 }
234
235 return true;
236 }
237
238 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
239 void *ir_binary,
240 struct si_shader *shader)
241 {
242 struct hash_entry *entry =
243 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
244 if (!entry) {
245 if (sscreen->disk_shader_cache) {
246 unsigned char sha1[CACHE_KEY_SIZE];
247 size_t tg_size = *((uint32_t *) ir_binary);
248
249 disk_cache_compute_key(sscreen->disk_shader_cache,
250 ir_binary, tg_size, sha1);
251
252 size_t binary_size;
253 uint8_t *buffer =
254 disk_cache_get(sscreen->disk_shader_cache,
255 sha1, &binary_size);
256 if (!buffer)
257 return false;
258
259 if (binary_size < sizeof(uint32_t) ||
260 *((uint32_t*)buffer) != binary_size) {
261 /* Something has gone wrong discard the item
262 * from the cache and rebuild/link from
263 * source.
264 */
265 assert(!"Invalid radeonsi shader disk cache "
266 "item!");
267
268 disk_cache_remove(sscreen->disk_shader_cache,
269 sha1);
270 free(buffer);
271
272 return false;
273 }
274
275 if (!si_load_shader_binary(shader, buffer)) {
276 free(buffer);
277 return false;
278 }
279 free(buffer);
280
281 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
282 shader, false))
283 FREE(ir_binary);
284 } else {
285 return false;
286 }
287 } else {
288 if (si_load_shader_binary(shader, entry->data))
289 FREE(ir_binary);
290 else
291 return false;
292 }
293 p_atomic_inc(&sscreen->num_shader_cache_hits);
294 return true;
295 }
296
297 static uint32_t si_shader_cache_key_hash(const void *key)
298 {
299 /* The first dword is the key size. */
300 return util_hash_crc32(key, *(uint32_t*)key);
301 }
302
303 static bool si_shader_cache_key_equals(const void *a, const void *b)
304 {
305 uint32_t *keya = (uint32_t*)a;
306 uint32_t *keyb = (uint32_t*)b;
307
308 /* The first dword is the key size. */
309 if (*keya != *keyb)
310 return false;
311
312 return memcmp(keya, keyb, *keya) == 0;
313 }
314
315 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
316 {
317 FREE((void*)entry->key);
318 FREE(entry->data);
319 }
320
321 bool si_init_shader_cache(struct si_screen *sscreen)
322 {
323 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
324 sscreen->shader_cache =
325 _mesa_hash_table_create(NULL,
326 si_shader_cache_key_hash,
327 si_shader_cache_key_equals);
328
329 return sscreen->shader_cache != NULL;
330 }
331
332 void si_destroy_shader_cache(struct si_screen *sscreen)
333 {
334 if (sscreen->shader_cache)
335 _mesa_hash_table_destroy(sscreen->shader_cache,
336 si_destroy_shader_cache_entry);
337 mtx_destroy(&sscreen->shader_cache_mutex);
338 }
339
340 /* SHADER STATES */
341
342 static void si_set_tesseval_regs(struct si_screen *sscreen,
343 struct si_shader_selector *tes,
344 struct si_pm4_state *pm4)
345 {
346 struct tgsi_shader_info *info = &tes->info;
347 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
348 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
349 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
350 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
351 unsigned type, partitioning, topology, distribution_mode;
352
353 switch (tes_prim_mode) {
354 case PIPE_PRIM_LINES:
355 type = V_028B6C_TESS_ISOLINE;
356 break;
357 case PIPE_PRIM_TRIANGLES:
358 type = V_028B6C_TESS_TRIANGLE;
359 break;
360 case PIPE_PRIM_QUADS:
361 type = V_028B6C_TESS_QUAD;
362 break;
363 default:
364 assert(0);
365 return;
366 }
367
368 switch (tes_spacing) {
369 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
370 partitioning = V_028B6C_PART_FRAC_ODD;
371 break;
372 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
373 partitioning = V_028B6C_PART_FRAC_EVEN;
374 break;
375 case PIPE_TESS_SPACING_EQUAL:
376 partitioning = V_028B6C_PART_INTEGER;
377 break;
378 default:
379 assert(0);
380 return;
381 }
382
383 if (tes_point_mode)
384 topology = V_028B6C_OUTPUT_POINT;
385 else if (tes_prim_mode == PIPE_PRIM_LINES)
386 topology = V_028B6C_OUTPUT_LINE;
387 else if (tes_vertex_order_cw)
388 /* for some reason, this must be the other way around */
389 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
390 else
391 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
392
393 if (sscreen->has_distributed_tess) {
394 if (sscreen->info.family == CHIP_FIJI ||
395 sscreen->info.family >= CHIP_POLARIS10)
396 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
397 else
398 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
399 } else
400 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
401
402 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
403 S_028B6C_TYPE(type) |
404 S_028B6C_PARTITIONING(partitioning) |
405 S_028B6C_TOPOLOGY(topology) |
406 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
407 }
408
409 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
410 * whether the "fractional odd" tessellation spacing is used.
411 *
412 * Possible VGT configurations and which state should set the register:
413 *
414 * Reg set in | VGT shader configuration | Value
415 * ------------------------------------------------------
416 * VS as VS | VS | 30
417 * VS as ES | ES -> GS -> VS | 30
418 * TES as VS | LS -> HS -> VS | 14 or 30
419 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
420 *
421 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
422 */
423 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
424 struct si_shader_selector *sel,
425 struct si_shader *shader,
426 struct si_pm4_state *pm4)
427 {
428 unsigned type = sel->type;
429
430 if (sscreen->info.family < CHIP_POLARIS10)
431 return;
432
433 /* VS as VS, or VS as ES: */
434 if ((type == PIPE_SHADER_VERTEX &&
435 (!shader ||
436 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
437 /* TES as VS, or TES as ES: */
438 type == PIPE_SHADER_TESS_EVAL) {
439 unsigned vtx_reuse_depth = 30;
440
441 if (type == PIPE_SHADER_TESS_EVAL &&
442 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
443 PIPE_TESS_SPACING_FRACTIONAL_ODD)
444 vtx_reuse_depth = 14;
445
446 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
447 vtx_reuse_depth);
448 }
449 }
450
451 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
452 {
453 if (shader->pm4)
454 si_pm4_clear_state(shader->pm4);
455 else
456 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
457
458 return shader->pm4;
459 }
460
461 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
462 {
463 /* Add the pointer to VBO descriptors. */
464 if (HAVE_32BIT_POINTERS) {
465 return num_always_on_user_sgprs + 1;
466 } else {
467 assert(num_always_on_user_sgprs % 2 == 0);
468 return num_always_on_user_sgprs + 2;
469 }
470 }
471
472 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
473 {
474 struct si_pm4_state *pm4;
475 unsigned vgpr_comp_cnt;
476 uint64_t va;
477
478 assert(sscreen->info.chip_class <= VI);
479
480 pm4 = si_get_shader_pm4_state(shader);
481 if (!pm4)
482 return;
483
484 va = shader->bo->gpu_address;
485 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
486
487 /* We need at least 2 components for LS.
488 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
489 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
490 */
491 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
492
493 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
494 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
495
496 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
497 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
498 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
499 S_00B528_DX10_CLAMP(1) |
500 S_00B528_FLOAT_MODE(shader->config.float_mode);
501 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
502 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
503 }
504
505 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
506 {
507 struct si_pm4_state *pm4;
508 uint64_t va;
509 unsigned ls_vgpr_comp_cnt = 0;
510
511 pm4 = si_get_shader_pm4_state(shader);
512 if (!pm4)
513 return;
514
515 va = shader->bo->gpu_address;
516 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
517
518 if (sscreen->info.chip_class >= GFX9) {
519 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
520 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
521
522 /* We need at least 2 components for LS.
523 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
524 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
525 */
526 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
527
528 unsigned num_user_sgprs =
529 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
530
531 shader->config.rsrc2 =
532 S_00B42C_USER_SGPR(num_user_sgprs) |
533 S_00B42C_USER_SGPR_MSB(num_user_sgprs >> 5) |
534 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
535 } else {
536 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
537 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
538
539 shader->config.rsrc2 =
540 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
541 S_00B42C_OC_LDS_EN(1) |
542 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
543 }
544
545 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
546 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
547 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
548 S_00B428_DX10_CLAMP(1) |
549 S_00B428_FLOAT_MODE(shader->config.float_mode) |
550 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
551
552 if (sscreen->info.chip_class <= VI) {
553 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
554 shader->config.rsrc2);
555 }
556 }
557
558 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
559 {
560 struct si_pm4_state *pm4;
561 unsigned num_user_sgprs;
562 unsigned vgpr_comp_cnt;
563 uint64_t va;
564 unsigned oc_lds_en;
565
566 assert(sscreen->info.chip_class <= VI);
567
568 pm4 = si_get_shader_pm4_state(shader);
569 if (!pm4)
570 return;
571
572 va = shader->bo->gpu_address;
573 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
574
575 if (shader->selector->type == PIPE_SHADER_VERTEX) {
576 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
577 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
578 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
579 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
580 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
581 num_user_sgprs = SI_TES_NUM_USER_SGPR;
582 } else
583 unreachable("invalid shader selector type");
584
585 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
586
587 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
588 shader->selector->esgs_itemsize / 4);
589 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
590 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
591 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
592 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
593 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
594 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
595 S_00B328_DX10_CLAMP(1) |
596 S_00B328_FLOAT_MODE(shader->config.float_mode));
597 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
598 S_00B32C_USER_SGPR(num_user_sgprs) |
599 S_00B32C_OC_LDS_EN(oc_lds_en) |
600 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
601
602 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
603 si_set_tesseval_regs(sscreen, shader->selector, pm4);
604
605 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
606 }
607
608 struct gfx9_gs_info {
609 unsigned es_verts_per_subgroup;
610 unsigned gs_prims_per_subgroup;
611 unsigned gs_inst_prims_in_subgroup;
612 unsigned max_prims_per_subgroup;
613 unsigned lds_size;
614 };
615
616 static void gfx9_get_gs_info(struct si_shader_selector *es,
617 struct si_shader_selector *gs,
618 struct gfx9_gs_info *out)
619 {
620 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
621 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
622 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
623 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
624
625 /* All these are in dwords: */
626 /* We can't allow using the whole LDS, because GS waves compete with
627 * other shader stages for LDS space. */
628 const unsigned max_lds_size = 8 * 1024;
629 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
630 unsigned esgs_lds_size;
631
632 /* All these are per subgroup: */
633 const unsigned max_out_prims = 32 * 1024;
634 const unsigned max_es_verts = 255;
635 const unsigned ideal_gs_prims = 64;
636 unsigned max_gs_prims, gs_prims;
637 unsigned min_es_verts, es_verts, worst_case_es_verts;
638
639 assert(gs_num_invocations <= 32); /* GL maximum */
640
641 if (uses_adjacency || gs_num_invocations > 1)
642 max_gs_prims = 127 / gs_num_invocations;
643 else
644 max_gs_prims = 255;
645
646 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
647 * Make sure we don't go over the maximum value.
648 */
649 if (gs->gs_max_out_vertices > 0) {
650 max_gs_prims = MIN2(max_gs_prims,
651 max_out_prims /
652 (gs->gs_max_out_vertices * gs_num_invocations));
653 }
654 assert(max_gs_prims > 0);
655
656 /* If the primitive has adjacency, halve the number of vertices
657 * that will be reused in multiple primitives.
658 */
659 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
660
661 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
662 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
663
664 /* Compute ESGS LDS size based on the worst case number of ES vertices
665 * needed to create the target number of GS prims per subgroup.
666 */
667 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
668
669 /* If total LDS usage is too big, refactor partitions based on ratio
670 * of ESGS item sizes.
671 */
672 if (esgs_lds_size > max_lds_size) {
673 /* Our target GS Prims Per Subgroup was too large. Calculate
674 * the maximum number of GS Prims Per Subgroup that will fit
675 * into LDS, capped by the maximum that the hardware can support.
676 */
677 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
678 max_gs_prims);
679 assert(gs_prims > 0);
680 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
681 max_es_verts);
682
683 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
684 assert(esgs_lds_size <= max_lds_size);
685 }
686
687 /* Now calculate remaining ESGS information. */
688 if (esgs_lds_size)
689 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
690 else
691 es_verts = max_es_verts;
692
693 /* Vertices for adjacency primitives are not always reused, so restore
694 * it for ES_VERTS_PER_SUBGRP.
695 */
696 min_es_verts = gs->gs_input_verts_per_prim;
697
698 /* For normal primitives, the VGT only checks if they are past the ES
699 * verts per subgroup after allocating a full GS primitive and if they
700 * are, kick off a new subgroup. But if those additional ES verts are
701 * unique (e.g. not reused) we need to make sure there is enough LDS
702 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
703 */
704 es_verts -= min_es_verts - 1;
705
706 out->es_verts_per_subgroup = es_verts;
707 out->gs_prims_per_subgroup = gs_prims;
708 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
709 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
710 gs->gs_max_out_vertices;
711 out->lds_size = align(esgs_lds_size, 128) / 128;
712
713 assert(out->max_prims_per_subgroup <= max_out_prims);
714 }
715
716 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
717 {
718 struct si_shader_selector *sel = shader->selector;
719 const ubyte *num_components = sel->info.num_stream_output_components;
720 unsigned gs_num_invocations = sel->gs_num_invocations;
721 struct si_pm4_state *pm4;
722 uint64_t va;
723 unsigned max_stream = sel->max_gs_stream;
724 unsigned offset;
725
726 pm4 = si_get_shader_pm4_state(shader);
727 if (!pm4)
728 return;
729
730 offset = num_components[0] * sel->gs_max_out_vertices;
731 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
732 if (max_stream >= 1)
733 offset += num_components[1] * sel->gs_max_out_vertices;
734 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
735 if (max_stream >= 2)
736 offset += num_components[2] * sel->gs_max_out_vertices;
737 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
738 if (max_stream >= 3)
739 offset += num_components[3] * sel->gs_max_out_vertices;
740 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
741
742 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
743 assert(offset < (1 << 15));
744
745 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, sel->gs_max_out_vertices);
746
747 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
748 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
749 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
750 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
751
752 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
753 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
754 S_028B90_ENABLE(gs_num_invocations > 0));
755
756 va = shader->bo->gpu_address;
757 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
758
759 if (sscreen->info.chip_class >= GFX9) {
760 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
761 unsigned es_type = shader->key.part.gs.es->type;
762 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
763 struct gfx9_gs_info gs_info;
764
765 if (es_type == PIPE_SHADER_VERTEX)
766 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
767 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
768 else if (es_type == PIPE_SHADER_TESS_EVAL)
769 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
770 else
771 unreachable("invalid shader selector type");
772
773 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
774 * VGPR[0:4] are always loaded.
775 */
776 if (sel->info.uses_invocationid)
777 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
778 else if (sel->info.uses_primid)
779 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
780 else if (input_prim >= PIPE_PRIM_TRIANGLES)
781 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
782 else
783 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
784
785 unsigned num_user_sgprs;
786 if (es_type == PIPE_SHADER_VERTEX)
787 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
788 else
789 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
790
791 gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
792
793 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
794 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
795
796 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
797 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
798 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
799 S_00B228_DX10_CLAMP(1) |
800 S_00B228_FLOAT_MODE(shader->config.float_mode) |
801 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
802 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
803 S_00B22C_USER_SGPR(num_user_sgprs) |
804 S_00B22C_USER_SGPR_MSB(num_user_sgprs >> 5) |
805 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
806 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
807 S_00B22C_LDS_SIZE(gs_info.lds_size) |
808 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
809
810 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
811 S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) |
812 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) |
813 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup));
814 si_pm4_set_reg(pm4, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
815 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup));
816 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
817 shader->key.part.gs.es->esgs_itemsize / 4);
818
819 if (es_type == PIPE_SHADER_TESS_EVAL)
820 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
821
822 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
823 NULL, pm4);
824 } else {
825 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
826 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
827
828 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
829 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
830 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
831 S_00B228_DX10_CLAMP(1) |
832 S_00B228_FLOAT_MODE(shader->config.float_mode));
833 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
834 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
835 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
836 }
837 }
838
839 /**
840 * Compute the state for \p shader, which will run as a vertex shader on the
841 * hardware.
842 *
843 * If \p gs is non-NULL, it points to the geometry shader for which this shader
844 * is the copy shader.
845 */
846 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
847 struct si_shader_selector *gs)
848 {
849 const struct tgsi_shader_info *info = &shader->selector->info;
850 struct si_pm4_state *pm4;
851 unsigned num_user_sgprs;
852 unsigned nparams, vgpr_comp_cnt;
853 uint64_t va;
854 unsigned oc_lds_en;
855 unsigned window_space =
856 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
857 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
858
859 pm4 = si_get_shader_pm4_state(shader);
860 if (!pm4)
861 return;
862
863 /* We always write VGT_GS_MODE in the VS state, because every switch
864 * between different shader pipelines involving a different GS or no
865 * GS at all involves a switch of the VS (different GS use different
866 * copy shaders). On the other hand, when the API switches from a GS to
867 * no GS and then back to the same GS used originally, the GS state is
868 * not sent again.
869 */
870 if (!gs) {
871 unsigned mode = V_028A40_GS_OFF;
872
873 /* PrimID needs GS scenario A. */
874 if (enable_prim_id)
875 mode = V_028A40_GS_SCENARIO_A;
876
877 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, S_028A40_MODE(mode));
878 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
879 } else {
880 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
881 ac_vgt_gs_mode(gs->gs_max_out_vertices,
882 sscreen->info.chip_class));
883 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
884 }
885
886 if (sscreen->info.chip_class <= VI) {
887 /* Reuse needs to be set off if we write oViewport. */
888 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF,
889 S_028AB4_REUSE_OFF(info->writes_viewport_index));
890 }
891
892 va = shader->bo->gpu_address;
893 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
894
895 if (gs) {
896 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
897 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
898 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
899 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
900 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
901 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
902 */
903 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
904
905 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
906 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
907 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
908 } else {
909 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
910 }
911 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
912 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
913 num_user_sgprs = SI_TES_NUM_USER_SGPR;
914 } else
915 unreachable("invalid shader selector type");
916
917 /* VS is required to export at least one param. */
918 nparams = MAX2(shader->info.nr_param_exports, 1);
919 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
920 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
921
922 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
923 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
924 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
925 V_02870C_SPI_SHADER_4COMP :
926 V_02870C_SPI_SHADER_NONE) |
927 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
928 V_02870C_SPI_SHADER_4COMP :
929 V_02870C_SPI_SHADER_NONE) |
930 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
931 V_02870C_SPI_SHADER_4COMP :
932 V_02870C_SPI_SHADER_NONE));
933
934 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
935
936 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
937 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
938 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
939 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
940 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
941 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
942 S_00B128_DX10_CLAMP(1) |
943 S_00B128_FLOAT_MODE(shader->config.float_mode));
944 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
945 S_00B12C_USER_SGPR(num_user_sgprs) |
946 S_00B12C_OC_LDS_EN(oc_lds_en) |
947 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
948 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
949 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
950 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
951 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
952 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
953 if (window_space)
954 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
955 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
956 else
957 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
958 S_028818_VTX_W0_FMT(1) |
959 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
960 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
961 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
962
963 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
964 si_set_tesseval_regs(sscreen, shader->selector, pm4);
965
966 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
967 }
968
969 static unsigned si_get_ps_num_interp(struct si_shader *ps)
970 {
971 struct tgsi_shader_info *info = &ps->selector->info;
972 unsigned num_colors = !!(info->colors_read & 0x0f) +
973 !!(info->colors_read & 0xf0);
974 unsigned num_interp = ps->selector->info.num_inputs +
975 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
976
977 assert(num_interp <= 32);
978 return MIN2(num_interp, 32);
979 }
980
981 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
982 {
983 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
984 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
985
986 /* If the i-th target format is set, all previous target formats must
987 * be non-zero to avoid hangs.
988 */
989 for (i = 0; i < num_targets; i++)
990 if (!(value & (0xf << (i * 4))))
991 value |= V_028714_SPI_SHADER_32_R << (i * 4);
992
993 return value;
994 }
995
996 static void si_shader_ps(struct si_shader *shader)
997 {
998 struct tgsi_shader_info *info = &shader->selector->info;
999 struct si_pm4_state *pm4;
1000 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1001 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1002 uint64_t va;
1003 unsigned input_ena = shader->config.spi_ps_input_ena;
1004
1005 /* we need to enable at least one of them, otherwise we hang the GPU */
1006 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1007 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1008 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1009 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1010 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1011 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1012 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1013 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1014 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1015 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1016 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1017 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1018 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1019 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1020
1021 /* Validate interpolation optimization flags (read as implications). */
1022 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1023 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1024 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1025 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1026 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1027 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1028 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1029 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1030 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1031 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1032 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1033 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1034 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1035 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1036 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1037 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1038 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1039 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1040
1041 /* Validate cases when the optimizations are off (read as implications). */
1042 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1043 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1044 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1045 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1046 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1047 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1048
1049 pm4 = si_get_shader_pm4_state(shader);
1050 if (!pm4)
1051 return;
1052
1053 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1054 * Possible vaules:
1055 * 0 -> Position = pixel center
1056 * 1 -> Position = pixel centroid
1057 * 2 -> Position = at sample position
1058 *
1059 * From GLSL 4.5 specification, section 7.1:
1060 * "The variable gl_FragCoord is available as an input variable from
1061 * within fragment shaders and it holds the window relative coordinates
1062 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1063 * value can be for any location within the pixel, or one of the
1064 * fragment samples. The use of centroid does not further restrict
1065 * this value to be inside the current primitive."
1066 *
1067 * Meaning that centroid has no effect and we can return anything within
1068 * the pixel. Thus, return the value at sample position, because that's
1069 * the most accurate one shaders can get.
1070 */
1071 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1072
1073 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1074 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1075 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1076
1077 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1078 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1079
1080 /* Ensure that some export memory is always allocated, for two reasons:
1081 *
1082 * 1) Correctness: The hardware ignores the EXEC mask if no export
1083 * memory is allocated, so KILL and alpha test do not work correctly
1084 * without this.
1085 * 2) Performance: Every shader needs at least a NULL export, even when
1086 * it writes no color/depth output. The NULL export instruction
1087 * stalls without this setting.
1088 *
1089 * Don't add this to CB_SHADER_MASK.
1090 */
1091 if (!spi_shader_col_format &&
1092 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1093 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1094
1095 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
1096 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
1097 shader->config.spi_ps_input_addr);
1098
1099 /* Set interpolation controls. */
1100 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1101
1102 /* Set registers. */
1103 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1104 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
1105
1106 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
1107 ac_get_spi_shader_z_format(info->writes_z,
1108 info->writes_stencil,
1109 info->writes_samplemask));
1110
1111 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
1112 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
1113
1114 va = shader->bo->gpu_address;
1115 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1116 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1117 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1118
1119 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1120 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1121 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
1122 S_00B028_DX10_CLAMP(1) |
1123 S_00B028_FLOAT_MODE(shader->config.float_mode));
1124 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1125 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1126 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1127 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1128 }
1129
1130 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1131 struct si_shader *shader)
1132 {
1133 switch (shader->selector->type) {
1134 case PIPE_SHADER_VERTEX:
1135 if (shader->key.as_ls)
1136 si_shader_ls(sscreen, shader);
1137 else if (shader->key.as_es)
1138 si_shader_es(sscreen, shader);
1139 else
1140 si_shader_vs(sscreen, shader, NULL);
1141 break;
1142 case PIPE_SHADER_TESS_CTRL:
1143 si_shader_hs(sscreen, shader);
1144 break;
1145 case PIPE_SHADER_TESS_EVAL:
1146 if (shader->key.as_es)
1147 si_shader_es(sscreen, shader);
1148 else
1149 si_shader_vs(sscreen, shader, NULL);
1150 break;
1151 case PIPE_SHADER_GEOMETRY:
1152 si_shader_gs(sscreen, shader);
1153 break;
1154 case PIPE_SHADER_FRAGMENT:
1155 si_shader_ps(shader);
1156 break;
1157 default:
1158 assert(0);
1159 }
1160 }
1161
1162 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1163 {
1164 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1165 if (sctx->queued.named.dsa)
1166 return sctx->queued.named.dsa->alpha_func;
1167
1168 return PIPE_FUNC_ALWAYS;
1169 }
1170
1171 static void si_shader_selector_key_vs(struct si_context *sctx,
1172 struct si_shader_selector *vs,
1173 struct si_shader_key *key,
1174 struct si_vs_prolog_bits *prolog_key)
1175 {
1176 if (!sctx->vertex_elements)
1177 return;
1178
1179 prolog_key->instance_divisor_is_one =
1180 sctx->vertex_elements->instance_divisor_is_one;
1181 prolog_key->instance_divisor_is_fetched =
1182 sctx->vertex_elements->instance_divisor_is_fetched;
1183
1184 /* Prefer a monolithic shader to allow scheduling divisions around
1185 * VBO loads. */
1186 if (prolog_key->instance_divisor_is_fetched)
1187 key->opt.prefer_mono = 1;
1188
1189 unsigned count = MIN2(vs->info.num_inputs,
1190 sctx->vertex_elements->count);
1191 memcpy(key->mono.vs_fix_fetch, sctx->vertex_elements->fix_fetch, count);
1192 }
1193
1194 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1195 struct si_shader_selector *vs,
1196 struct si_shader_key *key)
1197 {
1198 struct si_shader_selector *ps = sctx->ps_shader.cso;
1199
1200 key->opt.clip_disable =
1201 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1202 (vs->info.clipdist_writemask ||
1203 vs->info.writes_clipvertex) &&
1204 !vs->info.culldist_writemask;
1205
1206 /* Find out if PS is disabled. */
1207 bool ps_disabled = true;
1208 if (ps) {
1209 const struct si_state_blend *blend = sctx->queued.named.blend;
1210 bool alpha_to_coverage = blend && blend->alpha_to_coverage;
1211 bool ps_modifies_zs = ps->info.uses_kill ||
1212 ps->info.writes_z ||
1213 ps->info.writes_stencil ||
1214 ps->info.writes_samplemask ||
1215 alpha_to_coverage ||
1216 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1217 unsigned ps_colormask = si_get_total_colormask(sctx);
1218
1219 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1220 (!ps_colormask &&
1221 !ps_modifies_zs &&
1222 !ps->info.writes_memory);
1223 }
1224
1225 /* Find out which VS outputs aren't used by the PS. */
1226 uint64_t outputs_written = vs->outputs_written;
1227 uint64_t inputs_read = 0;
1228
1229 /* ignore POSITION, PSIZE */
1230 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0) |
1231 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0))));
1232
1233 if (!ps_disabled) {
1234 inputs_read = ps->inputs_read;
1235 }
1236
1237 uint64_t linked = outputs_written & inputs_read;
1238
1239 key->opt.kill_outputs = ~linked & outputs_written;
1240 }
1241
1242 /* Compute the key for the hw shader variant */
1243 static inline void si_shader_selector_key(struct pipe_context *ctx,
1244 struct si_shader_selector *sel,
1245 struct si_shader_key *key)
1246 {
1247 struct si_context *sctx = (struct si_context *)ctx;
1248
1249 memset(key, 0, sizeof(*key));
1250
1251 switch (sel->type) {
1252 case PIPE_SHADER_VERTEX:
1253 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1254
1255 if (sctx->tes_shader.cso)
1256 key->as_ls = 1;
1257 else if (sctx->gs_shader.cso)
1258 key->as_es = 1;
1259 else {
1260 si_shader_selector_key_hw_vs(sctx, sel, key);
1261
1262 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1263 key->mono.u.vs_export_prim_id = 1;
1264 }
1265 break;
1266 case PIPE_SHADER_TESS_CTRL:
1267 if (sctx->chip_class >= GFX9) {
1268 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1269 key, &key->part.tcs.ls_prolog);
1270 key->part.tcs.ls = sctx->vs_shader.cso;
1271
1272 /* When the LS VGPR fix is needed, monolithic shaders
1273 * can:
1274 * - avoid initializing EXEC in both the LS prolog
1275 * and the LS main part when !vs_needs_prolog
1276 * - remove the fixup for unused input VGPRs
1277 */
1278 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1279
1280 /* The LS output / HS input layout can be communicated
1281 * directly instead of via user SGPRs for merged LS-HS.
1282 * The LS VGPR fix prefers this too.
1283 */
1284 key->opt.prefer_mono = 1;
1285 }
1286
1287 key->part.tcs.epilog.prim_mode =
1288 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1289 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1290 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1291 key->part.tcs.epilog.tes_reads_tess_factors =
1292 sctx->tes_shader.cso->info.reads_tess_factors;
1293
1294 if (sel == sctx->fixed_func_tcs_shader.cso)
1295 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1296 break;
1297 case PIPE_SHADER_TESS_EVAL:
1298 if (sctx->gs_shader.cso)
1299 key->as_es = 1;
1300 else {
1301 si_shader_selector_key_hw_vs(sctx, sel, key);
1302
1303 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1304 key->mono.u.vs_export_prim_id = 1;
1305 }
1306 break;
1307 case PIPE_SHADER_GEOMETRY:
1308 if (sctx->chip_class >= GFX9) {
1309 if (sctx->tes_shader.cso) {
1310 key->part.gs.es = sctx->tes_shader.cso;
1311 } else {
1312 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1313 key, &key->part.gs.vs_prolog);
1314 key->part.gs.es = sctx->vs_shader.cso;
1315 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1316 }
1317
1318 /* Merged ES-GS can have unbalanced wave usage.
1319 *
1320 * ES threads are per-vertex, while GS threads are
1321 * per-primitive. So without any amplification, there
1322 * are fewer GS threads than ES threads, which can result
1323 * in empty (no-op) GS waves. With too much amplification,
1324 * there are more GS threads than ES threads, which
1325 * can result in empty (no-op) ES waves.
1326 *
1327 * Non-monolithic shaders are implemented by setting EXEC
1328 * at the beginning of shader parts, and don't jump to
1329 * the end if EXEC is 0.
1330 *
1331 * Monolithic shaders use conditional blocks, so they can
1332 * jump and skip empty waves of ES or GS. So set this to
1333 * always use optimized variants, which are monolithic.
1334 */
1335 key->opt.prefer_mono = 1;
1336 }
1337 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1338 break;
1339 case PIPE_SHADER_FRAGMENT: {
1340 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1341 struct si_state_blend *blend = sctx->queued.named.blend;
1342
1343 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1344 sel->info.colors_written == 0x1)
1345 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1346
1347 if (blend) {
1348 /* Select the shader color format based on whether
1349 * blending or alpha are needed.
1350 */
1351 key->part.ps.epilog.spi_shader_col_format =
1352 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1353 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1354 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1355 sctx->framebuffer.spi_shader_col_format_blend) |
1356 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1357 sctx->framebuffer.spi_shader_col_format_alpha) |
1358 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1359 sctx->framebuffer.spi_shader_col_format);
1360 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1361
1362 /* The output for dual source blending should have
1363 * the same format as the first output.
1364 */
1365 if (blend->dual_src_blend)
1366 key->part.ps.epilog.spi_shader_col_format |=
1367 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1368 } else
1369 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1370
1371 /* If alpha-to-coverage is enabled, we have to export alpha
1372 * even if there is no color buffer.
1373 */
1374 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1375 blend && blend->alpha_to_coverage)
1376 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1377
1378 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1379 * to the range supported by the type if a channel has less
1380 * than 16 bits and the export format is 16_ABGR.
1381 */
1382 if (sctx->chip_class <= CIK && sctx->family != CHIP_HAWAII) {
1383 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1384 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1385 }
1386
1387 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1388 if (!key->part.ps.epilog.last_cbuf) {
1389 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1390 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1391 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1392 }
1393
1394 if (rs) {
1395 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
1396 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
1397 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
1398 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
1399
1400 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1401 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1402
1403 if (sctx->queued.named.blend) {
1404 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1405 rs->multisample_enable;
1406 }
1407
1408 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1409 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1410 (is_line && rs->line_smooth)) &&
1411 sctx->framebuffer.nr_samples <= 1;
1412 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1413
1414 if (sctx->ps_iter_samples > 1 &&
1415 sel->info.reads_samplemask) {
1416 key->part.ps.prolog.samplemask_log_ps_iter =
1417 util_logbase2(util_next_power_of_two(sctx->ps_iter_samples));
1418 }
1419
1420 if (rs->force_persample_interp &&
1421 rs->multisample_enable &&
1422 sctx->framebuffer.nr_samples > 1 &&
1423 sctx->ps_iter_samples > 1) {
1424 key->part.ps.prolog.force_persp_sample_interp =
1425 sel->info.uses_persp_center ||
1426 sel->info.uses_persp_centroid;
1427
1428 key->part.ps.prolog.force_linear_sample_interp =
1429 sel->info.uses_linear_center ||
1430 sel->info.uses_linear_centroid;
1431 } else if (rs->multisample_enable &&
1432 sctx->framebuffer.nr_samples > 1) {
1433 key->part.ps.prolog.bc_optimize_for_persp =
1434 sel->info.uses_persp_center &&
1435 sel->info.uses_persp_centroid;
1436 key->part.ps.prolog.bc_optimize_for_linear =
1437 sel->info.uses_linear_center &&
1438 sel->info.uses_linear_centroid;
1439 } else {
1440 /* Make sure SPI doesn't compute more than 1 pair
1441 * of (i,j), which is the optimization here. */
1442 key->part.ps.prolog.force_persp_center_interp =
1443 sel->info.uses_persp_center +
1444 sel->info.uses_persp_centroid +
1445 sel->info.uses_persp_sample > 1;
1446
1447 key->part.ps.prolog.force_linear_center_interp =
1448 sel->info.uses_linear_center +
1449 sel->info.uses_linear_centroid +
1450 sel->info.uses_linear_sample > 1;
1451
1452 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
1453 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1454 }
1455 }
1456
1457 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1458
1459 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1460 if (sctx->ps_uses_fbfetch) {
1461 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
1462 struct pipe_resource *tex = cb0->texture;
1463
1464 /* 1D textures are allocated and used as 2D on GFX9. */
1465 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
1466 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
1467 (tex->target == PIPE_TEXTURE_1D ||
1468 tex->target == PIPE_TEXTURE_1D_ARRAY);
1469 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
1470 tex->target == PIPE_TEXTURE_2D_ARRAY ||
1471 tex->target == PIPE_TEXTURE_CUBE ||
1472 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
1473 tex->target == PIPE_TEXTURE_3D;
1474 }
1475 break;
1476 }
1477 default:
1478 assert(0);
1479 }
1480
1481 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
1482 memset(&key->opt, 0, sizeof(key->opt));
1483 }
1484
1485 static void si_build_shader_variant(struct si_shader *shader,
1486 int thread_index,
1487 bool low_priority)
1488 {
1489 struct si_shader_selector *sel = shader->selector;
1490 struct si_screen *sscreen = sel->screen;
1491 LLVMTargetMachineRef tm;
1492 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1493 int r;
1494
1495 if (thread_index >= 0) {
1496 if (low_priority) {
1497 assert(thread_index < ARRAY_SIZE(sscreen->tm_low_priority));
1498 tm = sscreen->tm_low_priority[thread_index];
1499 } else {
1500 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1501 tm = sscreen->tm[thread_index];
1502 }
1503 if (!debug->async)
1504 debug = NULL;
1505 } else {
1506 assert(!low_priority);
1507 tm = shader->compiler_ctx_state.tm;
1508 }
1509
1510 r = si_shader_create(sscreen, tm, shader, debug);
1511 if (unlikely(r)) {
1512 PRINT_ERR("Failed to build shader variant (type=%u) %d\n",
1513 sel->type, r);
1514 shader->compilation_failed = true;
1515 return;
1516 }
1517
1518 if (shader->compiler_ctx_state.is_debug_context) {
1519 FILE *f = open_memstream(&shader->shader_log,
1520 &shader->shader_log_size);
1521 if (f) {
1522 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1523 fclose(f);
1524 }
1525 }
1526
1527 si_shader_init_pm4_state(sscreen, shader);
1528 }
1529
1530 static void si_build_shader_variant_low_priority(void *job, int thread_index)
1531 {
1532 struct si_shader *shader = (struct si_shader *)job;
1533
1534 assert(thread_index >= 0);
1535
1536 si_build_shader_variant(shader, thread_index, true);
1537 }
1538
1539 static const struct si_shader_key zeroed;
1540
1541 static bool si_check_missing_main_part(struct si_screen *sscreen,
1542 struct si_shader_selector *sel,
1543 struct si_compiler_ctx_state *compiler_state,
1544 struct si_shader_key *key)
1545 {
1546 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1547
1548 if (!*mainp) {
1549 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1550
1551 if (!main_part)
1552 return false;
1553
1554 /* We can leave the fence as permanently signaled because the
1555 * main part becomes visible globally only after it has been
1556 * compiled. */
1557 util_queue_fence_init(&main_part->ready);
1558
1559 main_part->selector = sel;
1560 main_part->key.as_es = key->as_es;
1561 main_part->key.as_ls = key->as_ls;
1562
1563 if (si_compile_tgsi_shader(sscreen, compiler_state->tm,
1564 main_part, false,
1565 &compiler_state->debug) != 0) {
1566 FREE(main_part);
1567 return false;
1568 }
1569 *mainp = main_part;
1570 }
1571 return true;
1572 }
1573
1574 /* Select the hw shader variant depending on the current state. */
1575 static int si_shader_select_with_key(struct si_screen *sscreen,
1576 struct si_shader_ctx_state *state,
1577 struct si_compiler_ctx_state *compiler_state,
1578 struct si_shader_key *key,
1579 int thread_index)
1580 {
1581 struct si_shader_selector *sel = state->cso;
1582 struct si_shader_selector *previous_stage_sel = NULL;
1583 struct si_shader *current = state->current;
1584 struct si_shader *iter, *shader = NULL;
1585
1586 again:
1587 /* Check if we don't need to change anything.
1588 * This path is also used for most shaders that don't need multiple
1589 * variants, it will cost just a computation of the key and this
1590 * test. */
1591 if (likely(current &&
1592 memcmp(&current->key, key, sizeof(*key)) == 0)) {
1593 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
1594 if (current->is_optimized) {
1595 memset(&key->opt, 0, sizeof(key->opt));
1596 goto current_not_ready;
1597 }
1598
1599 util_queue_fence_wait(&current->ready);
1600 }
1601
1602 return current->compilation_failed ? -1 : 0;
1603 }
1604 current_not_ready:
1605
1606 /* This must be done before the mutex is locked, because async GS
1607 * compilation calls this function too, and therefore must enter
1608 * the mutex first.
1609 *
1610 * Only wait if we are in a draw call. Don't wait if we are
1611 * in a compiler thread.
1612 */
1613 if (thread_index < 0)
1614 util_queue_fence_wait(&sel->ready);
1615
1616 mtx_lock(&sel->mutex);
1617
1618 /* Find the shader variant. */
1619 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1620 /* Don't check the "current" shader. We checked it above. */
1621 if (current != iter &&
1622 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1623 mtx_unlock(&sel->mutex);
1624
1625 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
1626 /* If it's an optimized shader and its compilation has
1627 * been started but isn't done, use the unoptimized
1628 * shader so as not to cause a stall due to compilation.
1629 */
1630 if (iter->is_optimized) {
1631 memset(&key->opt, 0, sizeof(key->opt));
1632 goto again;
1633 }
1634
1635 util_queue_fence_wait(&iter->ready);
1636 }
1637
1638 if (iter->compilation_failed) {
1639 return -1; /* skip the draw call */
1640 }
1641
1642 state->current = iter;
1643 return 0;
1644 }
1645 }
1646
1647 /* Build a new shader. */
1648 shader = CALLOC_STRUCT(si_shader);
1649 if (!shader) {
1650 mtx_unlock(&sel->mutex);
1651 return -ENOMEM;
1652 }
1653
1654 util_queue_fence_init(&shader->ready);
1655
1656 shader->selector = sel;
1657 shader->key = *key;
1658 shader->compiler_ctx_state = *compiler_state;
1659
1660 /* If this is a merged shader, get the first shader's selector. */
1661 if (sscreen->info.chip_class >= GFX9) {
1662 if (sel->type == PIPE_SHADER_TESS_CTRL)
1663 previous_stage_sel = key->part.tcs.ls;
1664 else if (sel->type == PIPE_SHADER_GEOMETRY)
1665 previous_stage_sel = key->part.gs.es;
1666
1667 /* We need to wait for the previous shader. */
1668 if (previous_stage_sel && thread_index < 0)
1669 util_queue_fence_wait(&previous_stage_sel->ready);
1670 }
1671
1672 /* Compile the main shader part if it doesn't exist. This can happen
1673 * if the initial guess was wrong. */
1674 bool is_pure_monolithic =
1675 sscreen->use_monolithic_shaders ||
1676 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1677
1678 if (!is_pure_monolithic) {
1679 bool ok;
1680
1681 /* Make sure the main shader part is present. This is needed
1682 * for shaders that can be compiled as VS, LS, or ES, and only
1683 * one of them is compiled at creation.
1684 *
1685 * For merged shaders, check that the starting shader's main
1686 * part is present.
1687 */
1688 if (previous_stage_sel) {
1689 struct si_shader_key shader1_key = zeroed;
1690
1691 if (sel->type == PIPE_SHADER_TESS_CTRL)
1692 shader1_key.as_ls = 1;
1693 else if (sel->type == PIPE_SHADER_GEOMETRY)
1694 shader1_key.as_es = 1;
1695 else
1696 assert(0);
1697
1698 mtx_lock(&previous_stage_sel->mutex);
1699 ok = si_check_missing_main_part(sscreen,
1700 previous_stage_sel,
1701 compiler_state, &shader1_key);
1702 mtx_unlock(&previous_stage_sel->mutex);
1703 } else {
1704 ok = si_check_missing_main_part(sscreen, sel,
1705 compiler_state, key);
1706 }
1707 if (!ok) {
1708 FREE(shader);
1709 mtx_unlock(&sel->mutex);
1710 return -ENOMEM; /* skip the draw call */
1711 }
1712 }
1713
1714 /* Keep the reference to the 1st shader of merged shaders, so that
1715 * Gallium can't destroy it before we destroy the 2nd shader.
1716 *
1717 * Set sctx = NULL, because it's unused if we're not releasing
1718 * the shader, and we don't have any sctx here.
1719 */
1720 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
1721 previous_stage_sel);
1722
1723 /* Monolithic-only shaders don't make a distinction between optimized
1724 * and unoptimized. */
1725 shader->is_monolithic =
1726 is_pure_monolithic ||
1727 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1728
1729 shader->is_optimized =
1730 !is_pure_monolithic &&
1731 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1732
1733 /* If it's an optimized shader, compile it asynchronously. */
1734 if (shader->is_optimized &&
1735 !is_pure_monolithic &&
1736 thread_index < 0) {
1737 /* Compile it asynchronously. */
1738 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
1739 shader, &shader->ready,
1740 si_build_shader_variant_low_priority, NULL);
1741
1742 /* Add only after the ready fence was reset, to guard against a
1743 * race with si_bind_XX_shader. */
1744 if (!sel->last_variant) {
1745 sel->first_variant = shader;
1746 sel->last_variant = shader;
1747 } else {
1748 sel->last_variant->next_variant = shader;
1749 sel->last_variant = shader;
1750 }
1751
1752 /* Use the default (unoptimized) shader for now. */
1753 memset(&key->opt, 0, sizeof(key->opt));
1754 mtx_unlock(&sel->mutex);
1755 goto again;
1756 }
1757
1758 /* Reset the fence before adding to the variant list. */
1759 util_queue_fence_reset(&shader->ready);
1760
1761 if (!sel->last_variant) {
1762 sel->first_variant = shader;
1763 sel->last_variant = shader;
1764 } else {
1765 sel->last_variant->next_variant = shader;
1766 sel->last_variant = shader;
1767 }
1768
1769 mtx_unlock(&sel->mutex);
1770
1771 assert(!shader->is_optimized);
1772 si_build_shader_variant(shader, thread_index, false);
1773
1774 util_queue_fence_signal(&shader->ready);
1775
1776 if (!shader->compilation_failed)
1777 state->current = shader;
1778
1779 return shader->compilation_failed ? -1 : 0;
1780 }
1781
1782 static int si_shader_select(struct pipe_context *ctx,
1783 struct si_shader_ctx_state *state,
1784 struct si_compiler_ctx_state *compiler_state)
1785 {
1786 struct si_context *sctx = (struct si_context *)ctx;
1787 struct si_shader_key key;
1788
1789 si_shader_selector_key(ctx, state->cso, &key);
1790 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1791 &key, -1);
1792 }
1793
1794 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1795 bool streamout,
1796 struct si_shader_key *key)
1797 {
1798 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1799
1800 switch (info->processor) {
1801 case PIPE_SHADER_VERTEX:
1802 switch (next_shader) {
1803 case PIPE_SHADER_GEOMETRY:
1804 key->as_es = 1;
1805 break;
1806 case PIPE_SHADER_TESS_CTRL:
1807 case PIPE_SHADER_TESS_EVAL:
1808 key->as_ls = 1;
1809 break;
1810 default:
1811 /* If POSITION isn't written, it can only be a HW VS
1812 * if streamout is used. If streamout isn't used,
1813 * assume that it's a HW LS. (the next shader is TCS)
1814 * This heuristic is needed for separate shader objects.
1815 */
1816 if (!info->writes_position && !streamout)
1817 key->as_ls = 1;
1818 }
1819 break;
1820
1821 case PIPE_SHADER_TESS_EVAL:
1822 if (next_shader == PIPE_SHADER_GEOMETRY ||
1823 !info->writes_position)
1824 key->as_es = 1;
1825 break;
1826 }
1827 }
1828
1829 /**
1830 * Compile the main shader part or the monolithic shader as part of
1831 * si_shader_selector initialization. Since it can be done asynchronously,
1832 * there is no way to report compile failures to applications.
1833 */
1834 static void si_init_shader_selector_async(void *job, int thread_index)
1835 {
1836 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1837 struct si_screen *sscreen = sel->screen;
1838 LLVMTargetMachineRef tm;
1839 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
1840
1841 assert(!debug->debug_message || debug->async);
1842 assert(thread_index >= 0);
1843 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1844 tm = sscreen->tm[thread_index];
1845
1846 /* Compile the main shader part for use with a prolog and/or epilog.
1847 * If this fails, the driver will try to compile a monolithic shader
1848 * on demand.
1849 */
1850 if (!sscreen->use_monolithic_shaders) {
1851 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1852 void *ir_binary = NULL;
1853
1854 if (!shader) {
1855 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1856 return;
1857 }
1858
1859 /* We can leave the fence signaled because use of the default
1860 * main part is guarded by the selector's ready fence. */
1861 util_queue_fence_init(&shader->ready);
1862
1863 shader->selector = sel;
1864 si_parse_next_shader_property(&sel->info,
1865 sel->so.num_outputs != 0,
1866 &shader->key);
1867
1868 if (sel->tokens || sel->nir)
1869 ir_binary = si_get_ir_binary(sel);
1870
1871 /* Try to load the shader from the shader cache. */
1872 mtx_lock(&sscreen->shader_cache_mutex);
1873
1874 if (ir_binary &&
1875 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
1876 mtx_unlock(&sscreen->shader_cache_mutex);
1877 si_shader_dump_stats_for_shader_db(shader, debug);
1878 } else {
1879 mtx_unlock(&sscreen->shader_cache_mutex);
1880
1881 /* Compile the shader if it hasn't been loaded from the cache. */
1882 if (si_compile_tgsi_shader(sscreen, tm, shader, false,
1883 debug) != 0) {
1884 FREE(shader);
1885 FREE(ir_binary);
1886 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1887 return;
1888 }
1889
1890 if (ir_binary) {
1891 mtx_lock(&sscreen->shader_cache_mutex);
1892 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
1893 FREE(ir_binary);
1894 mtx_unlock(&sscreen->shader_cache_mutex);
1895 }
1896 }
1897
1898 *si_get_main_shader_part(sel, &shader->key) = shader;
1899
1900 /* Unset "outputs_written" flags for outputs converted to
1901 * DEFAULT_VAL, so that later inter-shader optimizations don't
1902 * try to eliminate outputs that don't exist in the final
1903 * shader.
1904 *
1905 * This is only done if non-monolithic shaders are enabled.
1906 */
1907 if ((sel->type == PIPE_SHADER_VERTEX ||
1908 sel->type == PIPE_SHADER_TESS_EVAL) &&
1909 !shader->key.as_ls &&
1910 !shader->key.as_es) {
1911 unsigned i;
1912
1913 for (i = 0; i < sel->info.num_outputs; i++) {
1914 unsigned offset = shader->info.vs_output_param_offset[i];
1915
1916 if (offset <= AC_EXP_PARAM_OFFSET_31)
1917 continue;
1918
1919 unsigned name = sel->info.output_semantic_name[i];
1920 unsigned index = sel->info.output_semantic_index[i];
1921 unsigned id;
1922
1923 switch (name) {
1924 case TGSI_SEMANTIC_GENERIC:
1925 /* don't process indices the function can't handle */
1926 if (index >= SI_MAX_IO_GENERIC)
1927 break;
1928 /* fall through */
1929 default:
1930 id = si_shader_io_get_unique_index(name, index);
1931 sel->outputs_written &= ~(1ull << id);
1932 break;
1933 case TGSI_SEMANTIC_POSITION: /* ignore these */
1934 case TGSI_SEMANTIC_PSIZE:
1935 case TGSI_SEMANTIC_CLIPVERTEX:
1936 case TGSI_SEMANTIC_EDGEFLAG:
1937 break;
1938 }
1939 }
1940 }
1941 }
1942
1943 /* The GS copy shader is always pre-compiled. */
1944 if (sel->type == PIPE_SHADER_GEOMETRY) {
1945 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
1946 if (!sel->gs_copy_shader) {
1947 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
1948 return;
1949 }
1950
1951 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
1952 }
1953 }
1954
1955 /* Return descriptor slot usage masks from the given shader info. */
1956 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
1957 uint32_t *const_and_shader_buffers,
1958 uint64_t *samplers_and_images)
1959 {
1960 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
1961
1962 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
1963 num_constbufs = util_last_bit(info->const_buffers_declared);
1964 /* two 8-byte images share one 16-byte slot */
1965 num_images = align(util_last_bit(info->images_declared), 2);
1966 num_samplers = util_last_bit(info->samplers_declared);
1967
1968 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
1969 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
1970 *const_and_shader_buffers =
1971 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
1972
1973 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
1974 start = si_get_image_slot(num_images - 1) / 2;
1975 *samplers_and_images =
1976 u_bit_consecutive64(start, num_images / 2 + num_samplers);
1977 }
1978
1979 static void *si_create_shader_selector(struct pipe_context *ctx,
1980 const struct pipe_shader_state *state)
1981 {
1982 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1983 struct si_context *sctx = (struct si_context*)ctx;
1984 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
1985 int i;
1986
1987 if (!sel)
1988 return NULL;
1989
1990 pipe_reference_init(&sel->reference, 1);
1991 sel->screen = sscreen;
1992 sel->compiler_ctx_state.debug = sctx->debug;
1993 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
1994
1995 sel->so = state->stream_output;
1996
1997 if (state->type == PIPE_SHADER_IR_TGSI) {
1998 sel->tokens = tgsi_dup_tokens(state->tokens);
1999 if (!sel->tokens) {
2000 FREE(sel);
2001 return NULL;
2002 }
2003
2004 tgsi_scan_shader(state->tokens, &sel->info);
2005 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2006 } else {
2007 assert(state->type == PIPE_SHADER_IR_NIR);
2008
2009 sel->nir = state->ir.nir;
2010
2011 si_nir_scan_shader(sel->nir, &sel->info);
2012 si_nir_scan_tess_ctrl(sel->nir, &sel->info, &sel->tcs_info);
2013
2014 si_lower_nir(sel);
2015 }
2016
2017 sel->type = sel->info.processor;
2018 p_atomic_inc(&sscreen->num_shaders_created);
2019 si_get_active_slot_masks(&sel->info,
2020 &sel->active_const_and_shader_buffers,
2021 &sel->active_samplers_and_images);
2022
2023 /* Record which streamout buffers are enabled. */
2024 for (i = 0; i < sel->so.num_outputs; i++) {
2025 sel->enabled_streamout_buffer_mask |=
2026 (1 << sel->so.output[i].output_buffer) <<
2027 (sel->so.output[i].stream * 4);
2028 }
2029
2030 /* The prolog is a no-op if there are no inputs. */
2031 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2032 sel->info.num_inputs &&
2033 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2034
2035 sel->force_correct_derivs_after_kill =
2036 sel->type == PIPE_SHADER_FRAGMENT &&
2037 sel->info.uses_derivatives &&
2038 sel->info.uses_kill &&
2039 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2040
2041 /* Set which opcode uses which (i,j) pair. */
2042 if (sel->info.uses_persp_opcode_interp_centroid)
2043 sel->info.uses_persp_centroid = true;
2044
2045 if (sel->info.uses_linear_opcode_interp_centroid)
2046 sel->info.uses_linear_centroid = true;
2047
2048 if (sel->info.uses_persp_opcode_interp_offset ||
2049 sel->info.uses_persp_opcode_interp_sample)
2050 sel->info.uses_persp_center = true;
2051
2052 if (sel->info.uses_linear_opcode_interp_offset ||
2053 sel->info.uses_linear_opcode_interp_sample)
2054 sel->info.uses_linear_center = true;
2055
2056 switch (sel->type) {
2057 case PIPE_SHADER_GEOMETRY:
2058 sel->gs_output_prim =
2059 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2060 sel->gs_max_out_vertices =
2061 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2062 sel->gs_num_invocations =
2063 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2064 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2065 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2066 sel->gs_max_out_vertices;
2067
2068 sel->max_gs_stream = 0;
2069 for (i = 0; i < sel->so.num_outputs; i++)
2070 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2071 sel->so.output[i].stream);
2072
2073 sel->gs_input_verts_per_prim =
2074 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2075 break;
2076
2077 case PIPE_SHADER_TESS_CTRL:
2078 /* Always reserve space for these. */
2079 sel->patch_outputs_written |=
2080 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2081 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2082 /* fall through */
2083 case PIPE_SHADER_VERTEX:
2084 case PIPE_SHADER_TESS_EVAL:
2085 for (i = 0; i < sel->info.num_outputs; i++) {
2086 unsigned name = sel->info.output_semantic_name[i];
2087 unsigned index = sel->info.output_semantic_index[i];
2088
2089 switch (name) {
2090 case TGSI_SEMANTIC_TESSINNER:
2091 case TGSI_SEMANTIC_TESSOUTER:
2092 case TGSI_SEMANTIC_PATCH:
2093 sel->patch_outputs_written |=
2094 1ull << si_shader_io_get_unique_index_patch(name, index);
2095 break;
2096
2097 case TGSI_SEMANTIC_GENERIC:
2098 /* don't process indices the function can't handle */
2099 if (index >= SI_MAX_IO_GENERIC)
2100 break;
2101 /* fall through */
2102 default:
2103 sel->outputs_written |=
2104 1ull << si_shader_io_get_unique_index(name, index);
2105 break;
2106 case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
2107 case TGSI_SEMANTIC_EDGEFLAG:
2108 break;
2109 }
2110 }
2111 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2112
2113 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2114 * conflicts, i.e. each vertex will start at a different bank.
2115 */
2116 if (sctx->chip_class >= GFX9)
2117 sel->esgs_itemsize += 4;
2118 break;
2119
2120 case PIPE_SHADER_FRAGMENT:
2121 for (i = 0; i < sel->info.num_inputs; i++) {
2122 unsigned name = sel->info.input_semantic_name[i];
2123 unsigned index = sel->info.input_semantic_index[i];
2124
2125 switch (name) {
2126 case TGSI_SEMANTIC_GENERIC:
2127 /* don't process indices the function can't handle */
2128 if (index >= SI_MAX_IO_GENERIC)
2129 break;
2130 /* fall through */
2131 default:
2132 sel->inputs_read |=
2133 1ull << si_shader_io_get_unique_index(name, index);
2134 break;
2135 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2136 break;
2137 }
2138 }
2139
2140 for (i = 0; i < 8; i++)
2141 if (sel->info.colors_written & (1 << i))
2142 sel->colors_written_4bit |= 0xf << (4 * i);
2143
2144 for (i = 0; i < sel->info.num_inputs; i++) {
2145 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2146 int index = sel->info.input_semantic_index[i];
2147 sel->color_attr_index[index] = i;
2148 }
2149 }
2150 break;
2151 }
2152
2153 /* PA_CL_VS_OUT_CNTL */
2154 bool misc_vec_ena =
2155 sel->info.writes_psize || sel->info.writes_edgeflag ||
2156 sel->info.writes_layer || sel->info.writes_viewport_index;
2157 sel->pa_cl_vs_out_cntl =
2158 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2159 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2160 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2161 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2162 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2163 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2164 sel->clipdist_mask = sel->info.writes_clipvertex ?
2165 SIX_BITS : sel->info.clipdist_writemask;
2166 sel->culldist_mask = sel->info.culldist_writemask <<
2167 sel->info.num_written_clipdistance;
2168
2169 /* DB_SHADER_CONTROL */
2170 sel->db_shader_control =
2171 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2172 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2173 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2174 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2175
2176 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2177 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2178 sel->db_shader_control |=
2179 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2180 break;
2181 case TGSI_FS_DEPTH_LAYOUT_LESS:
2182 sel->db_shader_control |=
2183 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2184 break;
2185 }
2186
2187 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2188 *
2189 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2190 * --|-----------|------------|------------|--------------------|-------------------|-------------
2191 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2192 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2193 * 2 | false | true | n/a | LateZ | 1 | 0
2194 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2195 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2196 *
2197 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2198 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2199 *
2200 * Don't use ReZ without profiling !!!
2201 *
2202 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2203 * shaders.
2204 */
2205 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2206 /* Cases 3, 4. */
2207 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2208 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2209 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2210 } else if (sel->info.writes_memory) {
2211 /* Case 2. */
2212 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2213 S_02880C_EXEC_ON_HIER_FAIL(1);
2214 } else {
2215 /* Case 1. */
2216 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2217 }
2218
2219 (void) mtx_init(&sel->mutex, mtx_plain);
2220 util_queue_fence_init(&sel->ready);
2221
2222 struct util_async_debug_callback async_debug;
2223 bool wait =
2224 (sctx->debug.debug_message && !sctx->debug.async) ||
2225 sctx->is_debug ||
2226 si_can_dump_shader(sscreen, sel->info.processor);
2227
2228 if (wait) {
2229 u_async_debug_init(&async_debug);
2230 sel->compiler_ctx_state.debug = async_debug.base;
2231 }
2232
2233 util_queue_add_job(&sscreen->shader_compiler_queue, sel,
2234 &sel->ready, si_init_shader_selector_async,
2235 NULL);
2236
2237 if (wait) {
2238 util_queue_fence_wait(&sel->ready);
2239 u_async_debug_drain(&async_debug, &sctx->debug);
2240 u_async_debug_cleanup(&async_debug);
2241 }
2242
2243 return sel;
2244 }
2245
2246 static void si_update_streamout_state(struct si_context *sctx)
2247 {
2248 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2249
2250 if (!shader_with_so)
2251 return;
2252
2253 sctx->streamout.enabled_stream_buffers_mask =
2254 shader_with_so->enabled_streamout_buffer_mask;
2255 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2256 }
2257
2258 static void si_update_clip_regs(struct si_context *sctx,
2259 struct si_shader_selector *old_hw_vs,
2260 struct si_shader *old_hw_vs_variant,
2261 struct si_shader_selector *next_hw_vs,
2262 struct si_shader *next_hw_vs_variant)
2263 {
2264 if (next_hw_vs &&
2265 (!old_hw_vs ||
2266 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2267 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2268 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2269 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2270 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2271 !old_hw_vs_variant ||
2272 !next_hw_vs_variant ||
2273 old_hw_vs_variant->key.opt.clip_disable !=
2274 next_hw_vs_variant->key.opt.clip_disable))
2275 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2276 }
2277
2278 static void si_update_common_shader_state(struct si_context *sctx)
2279 {
2280 sctx->uses_bindless_samplers =
2281 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2282 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2283 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2284 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2285 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2286 sctx->uses_bindless_images =
2287 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2288 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2289 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2290 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2291 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2292 sctx->do_update_shaders = true;
2293 }
2294
2295 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2296 {
2297 struct si_context *sctx = (struct si_context *)ctx;
2298 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2299 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2300 struct si_shader_selector *sel = state;
2301
2302 if (sctx->vs_shader.cso == sel)
2303 return;
2304
2305 sctx->vs_shader.cso = sel;
2306 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2307 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2308
2309 si_update_common_shader_state(sctx);
2310 si_update_vs_viewport_state(sctx);
2311 si_set_active_descriptors_for_shader(sctx, sel);
2312 si_update_streamout_state(sctx);
2313 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2314 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2315 }
2316
2317 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2318 {
2319 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2320 (sctx->tes_shader.cso &&
2321 sctx->tes_shader.cso->info.uses_primid) ||
2322 (sctx->tcs_shader.cso &&
2323 sctx->tcs_shader.cso->info.uses_primid) ||
2324 (sctx->gs_shader.cso &&
2325 sctx->gs_shader.cso->info.uses_primid) ||
2326 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2327 sctx->ps_shader.cso->info.uses_primid);
2328 }
2329
2330 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2331 {
2332 struct si_context *sctx = (struct si_context *)ctx;
2333 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2334 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2335 struct si_shader_selector *sel = state;
2336 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2337
2338 if (sctx->gs_shader.cso == sel)
2339 return;
2340
2341 sctx->gs_shader.cso = sel;
2342 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2343 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2344
2345 si_update_common_shader_state(sctx);
2346 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2347
2348 if (enable_changed) {
2349 si_shader_change_notify(sctx);
2350 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2351 si_update_tess_uses_prim_id(sctx);
2352 }
2353 si_update_vs_viewport_state(sctx);
2354 si_set_active_descriptors_for_shader(sctx, sel);
2355 si_update_streamout_state(sctx);
2356 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2357 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2358 }
2359
2360 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2361 {
2362 struct si_context *sctx = (struct si_context *)ctx;
2363 struct si_shader_selector *sel = state;
2364 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2365
2366 if (sctx->tcs_shader.cso == sel)
2367 return;
2368
2369 sctx->tcs_shader.cso = sel;
2370 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2371 si_update_tess_uses_prim_id(sctx);
2372
2373 si_update_common_shader_state(sctx);
2374
2375 if (enable_changed)
2376 sctx->last_tcs = NULL; /* invalidate derived tess state */
2377
2378 si_set_active_descriptors_for_shader(sctx, sel);
2379 }
2380
2381 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2382 {
2383 struct si_context *sctx = (struct si_context *)ctx;
2384 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2385 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2386 struct si_shader_selector *sel = state;
2387 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2388
2389 if (sctx->tes_shader.cso == sel)
2390 return;
2391
2392 sctx->tes_shader.cso = sel;
2393 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2394 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2395 si_update_tess_uses_prim_id(sctx);
2396
2397 si_update_common_shader_state(sctx);
2398 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2399
2400 if (enable_changed) {
2401 si_shader_change_notify(sctx);
2402 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2403 }
2404 si_update_vs_viewport_state(sctx);
2405 si_set_active_descriptors_for_shader(sctx, sel);
2406 si_update_streamout_state(sctx);
2407 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2408 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2409 }
2410
2411 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2412 {
2413 struct si_context *sctx = (struct si_context *)ctx;
2414 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
2415 struct si_shader_selector *sel = state;
2416
2417 /* skip if supplied shader is one already in use */
2418 if (old_sel == sel)
2419 return;
2420
2421 sctx->ps_shader.cso = sel;
2422 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2423
2424 si_update_common_shader_state(sctx);
2425 if (sel) {
2426 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2427 si_update_tess_uses_prim_id(sctx);
2428
2429 if (!old_sel ||
2430 old_sel->info.colors_written != sel->info.colors_written)
2431 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2432
2433 if (sctx->screen->has_out_of_order_rast &&
2434 (!old_sel ||
2435 old_sel->info.writes_memory != sel->info.writes_memory ||
2436 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
2437 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
2438 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2439 }
2440 si_set_active_descriptors_for_shader(sctx, sel);
2441 si_update_ps_colorbuf0_slot(sctx);
2442 }
2443
2444 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2445 {
2446 if (shader->is_optimized) {
2447 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
2448 &shader->ready);
2449 }
2450
2451 util_queue_fence_destroy(&shader->ready);
2452
2453 if (shader->pm4) {
2454 switch (shader->selector->type) {
2455 case PIPE_SHADER_VERTEX:
2456 if (shader->key.as_ls) {
2457 assert(sctx->chip_class <= VI);
2458 si_pm4_delete_state(sctx, ls, shader->pm4);
2459 } else if (shader->key.as_es) {
2460 assert(sctx->chip_class <= VI);
2461 si_pm4_delete_state(sctx, es, shader->pm4);
2462 } else {
2463 si_pm4_delete_state(sctx, vs, shader->pm4);
2464 }
2465 break;
2466 case PIPE_SHADER_TESS_CTRL:
2467 si_pm4_delete_state(sctx, hs, shader->pm4);
2468 break;
2469 case PIPE_SHADER_TESS_EVAL:
2470 if (shader->key.as_es) {
2471 assert(sctx->chip_class <= VI);
2472 si_pm4_delete_state(sctx, es, shader->pm4);
2473 } else {
2474 si_pm4_delete_state(sctx, vs, shader->pm4);
2475 }
2476 break;
2477 case PIPE_SHADER_GEOMETRY:
2478 if (shader->is_gs_copy_shader)
2479 si_pm4_delete_state(sctx, vs, shader->pm4);
2480 else
2481 si_pm4_delete_state(sctx, gs, shader->pm4);
2482 break;
2483 case PIPE_SHADER_FRAGMENT:
2484 si_pm4_delete_state(sctx, ps, shader->pm4);
2485 break;
2486 }
2487 }
2488
2489 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2490 si_shader_destroy(shader);
2491 free(shader);
2492 }
2493
2494 void si_destroy_shader_selector(struct si_context *sctx,
2495 struct si_shader_selector *sel)
2496 {
2497 struct si_shader *p = sel->first_variant, *c;
2498 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2499 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2500 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2501 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2502 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2503 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2504 };
2505
2506 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
2507
2508 if (current_shader[sel->type]->cso == sel) {
2509 current_shader[sel->type]->cso = NULL;
2510 current_shader[sel->type]->current = NULL;
2511 }
2512
2513 while (p) {
2514 c = p->next_variant;
2515 si_delete_shader(sctx, p);
2516 p = c;
2517 }
2518
2519 if (sel->main_shader_part)
2520 si_delete_shader(sctx, sel->main_shader_part);
2521 if (sel->main_shader_part_ls)
2522 si_delete_shader(sctx, sel->main_shader_part_ls);
2523 if (sel->main_shader_part_es)
2524 si_delete_shader(sctx, sel->main_shader_part_es);
2525 if (sel->gs_copy_shader)
2526 si_delete_shader(sctx, sel->gs_copy_shader);
2527
2528 util_queue_fence_destroy(&sel->ready);
2529 mtx_destroy(&sel->mutex);
2530 free(sel->tokens);
2531 ralloc_free(sel->nir);
2532 free(sel);
2533 }
2534
2535 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
2536 {
2537 struct si_context *sctx = (struct si_context *)ctx;
2538 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2539
2540 si_shader_selector_reference(sctx, &sel, NULL);
2541 }
2542
2543 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2544 struct si_shader *vs, unsigned name,
2545 unsigned index, unsigned interpolate)
2546 {
2547 struct tgsi_shader_info *vsinfo = &vs->selector->info;
2548 unsigned j, offset, ps_input_cntl = 0;
2549
2550 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2551 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
2552 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2553
2554 if (name == TGSI_SEMANTIC_PCOORD ||
2555 (name == TGSI_SEMANTIC_TEXCOORD &&
2556 sctx->sprite_coord_enable & (1 << index))) {
2557 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2558 }
2559
2560 for (j = 0; j < vsinfo->num_outputs; j++) {
2561 if (name == vsinfo->output_semantic_name[j] &&
2562 index == vsinfo->output_semantic_index[j]) {
2563 offset = vs->info.vs_output_param_offset[j];
2564
2565 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2566 /* The input is loaded from parameter memory. */
2567 ps_input_cntl |= S_028644_OFFSET(offset);
2568 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2569 if (offset == AC_EXP_PARAM_UNDEFINED) {
2570 /* This can happen with depth-only rendering. */
2571 offset = 0;
2572 } else {
2573 /* The input is a DEFAULT_VAL constant. */
2574 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2575 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2576 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2577 }
2578
2579 ps_input_cntl = S_028644_OFFSET(0x20) |
2580 S_028644_DEFAULT_VAL(offset);
2581 }
2582 break;
2583 }
2584 }
2585
2586 if (name == TGSI_SEMANTIC_PRIMID)
2587 /* PrimID is written after the last output. */
2588 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2589 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2590 /* No corresponding output found, load defaults into input.
2591 * Don't set any other bits.
2592 * (FLAT_SHADE=1 completely changes behavior) */
2593 ps_input_cntl = S_028644_OFFSET(0x20);
2594 /* D3D 9 behaviour. GL is undefined */
2595 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2596 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2597 }
2598 return ps_input_cntl;
2599 }
2600
2601 static void si_emit_spi_map(struct si_context *sctx, struct si_atom *atom)
2602 {
2603 struct radeon_winsys_cs *cs = sctx->gfx_cs;
2604 struct si_shader *ps = sctx->ps_shader.current;
2605 struct si_shader *vs = si_get_vs_state(sctx);
2606 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2607 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2608
2609 if (!ps || !ps->selector->info.num_inputs)
2610 return;
2611
2612 num_interp = si_get_ps_num_interp(ps);
2613 assert(num_interp > 0);
2614 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
2615
2616 for (i = 0; i < psinfo->num_inputs; i++) {
2617 unsigned name = psinfo->input_semantic_name[i];
2618 unsigned index = psinfo->input_semantic_index[i];
2619 unsigned interpolate = psinfo->input_interpolate[i];
2620
2621 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
2622 interpolate));
2623 num_written++;
2624
2625 if (name == TGSI_SEMANTIC_COLOR) {
2626 assert(index < ARRAY_SIZE(bcol_interp));
2627 bcol_interp[index] = interpolate;
2628 }
2629 }
2630
2631 if (ps->key.part.ps.prolog.color_two_side) {
2632 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2633
2634 for (i = 0; i < 2; i++) {
2635 if (!(psinfo->colors_read & (0xf << (i * 4))))
2636 continue;
2637
2638 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
2639 i, bcol_interp[i]));
2640 num_written++;
2641 }
2642 }
2643 assert(num_interp == num_written);
2644 }
2645
2646 /**
2647 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2648 */
2649 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2650 {
2651 if (sctx->init_config_has_vgt_flush)
2652 return;
2653
2654 /* Done by Vulkan before VGT_FLUSH. */
2655 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2656 si_pm4_cmd_add(sctx->init_config,
2657 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2658 si_pm4_cmd_end(sctx->init_config, false);
2659
2660 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2661 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2662 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2663 si_pm4_cmd_end(sctx->init_config, false);
2664 sctx->init_config_has_vgt_flush = true;
2665 }
2666
2667 /* Initialize state related to ESGS / GSVS ring buffers */
2668 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2669 {
2670 struct si_shader_selector *es =
2671 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2672 struct si_shader_selector *gs = sctx->gs_shader.cso;
2673 struct si_pm4_state *pm4;
2674
2675 /* Chip constants. */
2676 unsigned num_se = sctx->screen->info.max_se;
2677 unsigned wave_size = 64;
2678 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2679 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2680 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2681 */
2682 unsigned gs_vertex_reuse = (sctx->chip_class >= VI ? 32 : 16) * num_se;
2683 unsigned alignment = 256 * num_se;
2684 /* The maximum size is 63.999 MB per SE. */
2685 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2686
2687 /* Calculate the minimum size. */
2688 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2689 wave_size, alignment);
2690
2691 /* These are recommended sizes, not minimum sizes. */
2692 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2693 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2694 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2695 gs->max_gsvs_emit_size;
2696
2697 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2698 esgs_ring_size = align(esgs_ring_size, alignment);
2699 gsvs_ring_size = align(gsvs_ring_size, alignment);
2700
2701 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2702 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2703
2704 /* Some rings don't have to be allocated if shaders don't use them.
2705 * (e.g. no varyings between ES and GS or GS and VS)
2706 *
2707 * GFX9 doesn't have the ESGS ring.
2708 */
2709 bool update_esgs = sctx->chip_class <= VI &&
2710 esgs_ring_size &&
2711 (!sctx->esgs_ring ||
2712 sctx->esgs_ring->width0 < esgs_ring_size);
2713 bool update_gsvs = gsvs_ring_size &&
2714 (!sctx->gsvs_ring ||
2715 sctx->gsvs_ring->width0 < gsvs_ring_size);
2716
2717 if (!update_esgs && !update_gsvs)
2718 return true;
2719
2720 if (update_esgs) {
2721 pipe_resource_reference(&sctx->esgs_ring, NULL);
2722 sctx->esgs_ring =
2723 si_aligned_buffer_create(sctx->b.screen,
2724 SI_RESOURCE_FLAG_UNMAPPABLE,
2725 PIPE_USAGE_DEFAULT,
2726 esgs_ring_size, alignment);
2727 if (!sctx->esgs_ring)
2728 return false;
2729 }
2730
2731 if (update_gsvs) {
2732 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2733 sctx->gsvs_ring =
2734 si_aligned_buffer_create(sctx->b.screen,
2735 SI_RESOURCE_FLAG_UNMAPPABLE,
2736 PIPE_USAGE_DEFAULT,
2737 gsvs_ring_size, alignment);
2738 if (!sctx->gsvs_ring)
2739 return false;
2740 }
2741
2742 /* Create the "init_config_gs_rings" state. */
2743 pm4 = CALLOC_STRUCT(si_pm4_state);
2744 if (!pm4)
2745 return false;
2746
2747 if (sctx->chip_class >= CIK) {
2748 if (sctx->esgs_ring) {
2749 assert(sctx->chip_class <= VI);
2750 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2751 sctx->esgs_ring->width0 / 256);
2752 }
2753 if (sctx->gsvs_ring)
2754 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2755 sctx->gsvs_ring->width0 / 256);
2756 } else {
2757 if (sctx->esgs_ring)
2758 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2759 sctx->esgs_ring->width0 / 256);
2760 if (sctx->gsvs_ring)
2761 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2762 sctx->gsvs_ring->width0 / 256);
2763 }
2764
2765 /* Set the state. */
2766 if (sctx->init_config_gs_rings)
2767 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2768 sctx->init_config_gs_rings = pm4;
2769
2770 if (!sctx->init_config_has_vgt_flush) {
2771 si_init_config_add_vgt_flush(sctx);
2772 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2773 }
2774
2775 /* Flush the context to re-emit both init_config states. */
2776 sctx->initial_gfx_cs_size = 0; /* force flush */
2777 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
2778
2779 /* Set ring bindings. */
2780 if (sctx->esgs_ring) {
2781 assert(sctx->chip_class <= VI);
2782 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
2783 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2784 true, true, 4, 64, 0);
2785 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
2786 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2787 false, false, 0, 0, 0);
2788 }
2789 if (sctx->gsvs_ring) {
2790 si_set_ring_buffer(sctx, SI_RING_GSVS,
2791 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2792 false, false, 0, 0, 0);
2793 }
2794
2795 return true;
2796 }
2797
2798 static void si_shader_lock(struct si_shader *shader)
2799 {
2800 mtx_lock(&shader->selector->mutex);
2801 if (shader->previous_stage_sel) {
2802 assert(shader->previous_stage_sel != shader->selector);
2803 mtx_lock(&shader->previous_stage_sel->mutex);
2804 }
2805 }
2806
2807 static void si_shader_unlock(struct si_shader *shader)
2808 {
2809 if (shader->previous_stage_sel)
2810 mtx_unlock(&shader->previous_stage_sel->mutex);
2811 mtx_unlock(&shader->selector->mutex);
2812 }
2813
2814 /**
2815 * @returns 1 if \p sel has been updated to use a new scratch buffer
2816 * 0 if not
2817 * < 0 if there was a failure
2818 */
2819 static int si_update_scratch_buffer(struct si_context *sctx,
2820 struct si_shader *shader)
2821 {
2822 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2823 int r;
2824
2825 if (!shader)
2826 return 0;
2827
2828 /* This shader doesn't need a scratch buffer */
2829 if (shader->config.scratch_bytes_per_wave == 0)
2830 return 0;
2831
2832 /* Prevent race conditions when updating:
2833 * - si_shader::scratch_bo
2834 * - si_shader::binary::code
2835 * - si_shader::previous_stage::binary::code.
2836 */
2837 si_shader_lock(shader);
2838
2839 /* This shader is already configured to use the current
2840 * scratch buffer. */
2841 if (shader->scratch_bo == sctx->scratch_buffer) {
2842 si_shader_unlock(shader);
2843 return 0;
2844 }
2845
2846 assert(sctx->scratch_buffer);
2847
2848 if (shader->previous_stage)
2849 si_shader_apply_scratch_relocs(shader->previous_stage, scratch_va);
2850
2851 si_shader_apply_scratch_relocs(shader, scratch_va);
2852
2853 /* Replace the shader bo with a new bo that has the relocs applied. */
2854 r = si_shader_binary_upload(sctx->screen, shader);
2855 if (r) {
2856 si_shader_unlock(shader);
2857 return r;
2858 }
2859
2860 /* Update the shader state to use the new shader bo. */
2861 si_shader_init_pm4_state(sctx->screen, shader);
2862
2863 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2864
2865 si_shader_unlock(shader);
2866 return 1;
2867 }
2868
2869 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2870 {
2871 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2872 }
2873
2874 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2875 {
2876 return shader ? shader->config.scratch_bytes_per_wave : 0;
2877 }
2878
2879 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
2880 {
2881 if (!sctx->tes_shader.cso)
2882 return NULL; /* tessellation disabled */
2883
2884 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
2885 sctx->fixed_func_tcs_shader.current;
2886 }
2887
2888 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2889 {
2890 unsigned bytes = 0;
2891
2892 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2893 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2894 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2895 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2896
2897 if (sctx->tes_shader.cso) {
2898 struct si_shader *tcs = si_get_tcs_current(sctx);
2899
2900 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
2901 }
2902 return bytes;
2903 }
2904
2905 static bool si_update_scratch_relocs(struct si_context *sctx)
2906 {
2907 struct si_shader *tcs = si_get_tcs_current(sctx);
2908 int r;
2909
2910 /* Update the shaders, so that they are using the latest scratch.
2911 * The scratch buffer may have been changed since these shaders were
2912 * last used, so we still need to try to update them, even if they
2913 * require scratch buffers smaller than the current size.
2914 */
2915 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2916 if (r < 0)
2917 return false;
2918 if (r == 1)
2919 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2920
2921 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2922 if (r < 0)
2923 return false;
2924 if (r == 1)
2925 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2926
2927 r = si_update_scratch_buffer(sctx, tcs);
2928 if (r < 0)
2929 return false;
2930 if (r == 1)
2931 si_pm4_bind_state(sctx, hs, tcs->pm4);
2932
2933 /* VS can be bound as LS, ES, or VS. */
2934 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2935 if (r < 0)
2936 return false;
2937 if (r == 1) {
2938 if (sctx->tes_shader.current)
2939 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2940 else if (sctx->gs_shader.current)
2941 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2942 else
2943 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2944 }
2945
2946 /* TES can be bound as ES or VS. */
2947 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2948 if (r < 0)
2949 return false;
2950 if (r == 1) {
2951 if (sctx->gs_shader.current)
2952 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2953 else
2954 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2955 }
2956
2957 return true;
2958 }
2959
2960 static bool si_update_spi_tmpring_size(struct si_context *sctx)
2961 {
2962 unsigned current_scratch_buffer_size =
2963 si_get_current_scratch_buffer_size(sctx);
2964 unsigned scratch_bytes_per_wave =
2965 si_get_max_scratch_bytes_per_wave(sctx);
2966 unsigned scratch_needed_size = scratch_bytes_per_wave *
2967 sctx->scratch_waves;
2968 unsigned spi_tmpring_size;
2969
2970 if (scratch_needed_size > 0) {
2971 if (scratch_needed_size > current_scratch_buffer_size) {
2972 /* Create a bigger scratch buffer */
2973 r600_resource_reference(&sctx->scratch_buffer, NULL);
2974
2975 sctx->scratch_buffer = (struct r600_resource*)
2976 si_aligned_buffer_create(&sctx->screen->b,
2977 SI_RESOURCE_FLAG_UNMAPPABLE,
2978 PIPE_USAGE_DEFAULT,
2979 scratch_needed_size, 256);
2980 if (!sctx->scratch_buffer)
2981 return false;
2982
2983 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
2984 si_context_add_resource_size(sctx,
2985 &sctx->scratch_buffer->b.b);
2986 }
2987
2988 if (!si_update_scratch_relocs(sctx))
2989 return false;
2990 }
2991
2992 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2993 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
2994 "scratch size should already be aligned correctly.");
2995
2996 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
2997 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
2998 if (spi_tmpring_size != sctx->spi_tmpring_size) {
2999 sctx->spi_tmpring_size = spi_tmpring_size;
3000 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3001 }
3002 return true;
3003 }
3004
3005 static void si_init_tess_factor_ring(struct si_context *sctx)
3006 {
3007 assert(!sctx->tess_rings);
3008
3009 /* The address must be aligned to 2^19, because the shader only
3010 * receives the high 13 bits.
3011 */
3012 sctx->tess_rings = si_aligned_buffer_create(sctx->b.screen,
3013 SI_RESOURCE_FLAG_32BIT,
3014 PIPE_USAGE_DEFAULT,
3015 sctx->screen->tess_offchip_ring_size +
3016 sctx->screen->tess_factor_ring_size,
3017 1 << 19);
3018 if (!sctx->tess_rings)
3019 return;
3020
3021 si_init_config_add_vgt_flush(sctx);
3022
3023 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_rings),
3024 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3025
3026 uint64_t factor_va = r600_resource(sctx->tess_rings)->gpu_address +
3027 sctx->screen->tess_offchip_ring_size;
3028
3029 /* Append these registers to the init config state. */
3030 if (sctx->chip_class >= CIK) {
3031 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3032 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3033 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3034 factor_va >> 8);
3035 if (sctx->chip_class >= GFX9)
3036 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3037 S_030944_BASE_HI(factor_va >> 40));
3038 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3039 sctx->screen->vgt_hs_offchip_param);
3040 } else {
3041 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3042 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3043 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3044 factor_va >> 8);
3045 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3046 sctx->screen->vgt_hs_offchip_param);
3047 }
3048
3049 /* Flush the context to re-emit the init_config state.
3050 * This is done only once in a lifetime of a context.
3051 */
3052 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3053 sctx->initial_gfx_cs_size = 0; /* force flush */
3054 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3055 }
3056
3057 /**
3058 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
3059 * VS passes its outputs to TES directly, so the fixed-function shader only
3060 * has to write TESSOUTER and TESSINNER.
3061 */
3062 static void si_generate_fixed_func_tcs(struct si_context *sctx)
3063 {
3064 struct ureg_src outer, inner;
3065 struct ureg_dst tessouter, tessinner;
3066 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
3067
3068 if (!ureg)
3069 return; /* if we get here, we're screwed */
3070
3071 assert(!sctx->fixed_func_tcs_shader.cso);
3072
3073 outer = ureg_DECL_system_value(ureg,
3074 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
3075 inner = ureg_DECL_system_value(ureg,
3076 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
3077
3078 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
3079 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
3080
3081 ureg_MOV(ureg, tessouter, outer);
3082 ureg_MOV(ureg, tessinner, inner);
3083 ureg_END(ureg);
3084
3085 sctx->fixed_func_tcs_shader.cso =
3086 ureg_create_shader_and_destroy(ureg, &sctx->b);
3087 }
3088
3089 static void si_update_vgt_shader_config(struct si_context *sctx)
3090 {
3091 /* Calculate the index of the config.
3092 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3093 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
3094 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
3095
3096 if (!*pm4) {
3097 uint32_t stages = 0;
3098
3099 *pm4 = CALLOC_STRUCT(si_pm4_state);
3100
3101 if (sctx->tes_shader.cso) {
3102 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3103 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3104
3105 if (sctx->gs_shader.cso)
3106 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3107 S_028B54_GS_EN(1) |
3108 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3109 else
3110 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3111 } else if (sctx->gs_shader.cso) {
3112 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3113 S_028B54_GS_EN(1) |
3114 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3115 }
3116
3117 if (sctx->chip_class >= GFX9)
3118 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3119
3120 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3121 }
3122 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3123 }
3124
3125 bool si_update_shaders(struct si_context *sctx)
3126 {
3127 struct pipe_context *ctx = (struct pipe_context*)sctx;
3128 struct si_compiler_ctx_state compiler_state;
3129 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3130 struct si_shader *old_vs = si_get_vs_state(sctx);
3131 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3132 struct si_shader *old_ps = sctx->ps_shader.current;
3133 unsigned old_spi_shader_col_format =
3134 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3135 int r;
3136
3137 compiler_state.tm = sctx->tm;
3138 compiler_state.debug = sctx->debug;
3139 compiler_state.is_debug_context = sctx->is_debug;
3140
3141 /* Update stages before GS. */
3142 if (sctx->tes_shader.cso) {
3143 if (!sctx->tess_rings) {
3144 si_init_tess_factor_ring(sctx);
3145 if (!sctx->tess_rings)
3146 return false;
3147 }
3148
3149 /* VS as LS */
3150 if (sctx->chip_class <= VI) {
3151 r = si_shader_select(ctx, &sctx->vs_shader,
3152 &compiler_state);
3153 if (r)
3154 return false;
3155 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3156 }
3157
3158 if (sctx->tcs_shader.cso) {
3159 r = si_shader_select(ctx, &sctx->tcs_shader,
3160 &compiler_state);
3161 if (r)
3162 return false;
3163 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3164 } else {
3165 if (!sctx->fixed_func_tcs_shader.cso) {
3166 si_generate_fixed_func_tcs(sctx);
3167 if (!sctx->fixed_func_tcs_shader.cso)
3168 return false;
3169 }
3170
3171 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3172 &compiler_state);
3173 if (r)
3174 return false;
3175 si_pm4_bind_state(sctx, hs,
3176 sctx->fixed_func_tcs_shader.current->pm4);
3177 }
3178
3179 if (sctx->gs_shader.cso) {
3180 /* TES as ES */
3181 if (sctx->chip_class <= VI) {
3182 r = si_shader_select(ctx, &sctx->tes_shader,
3183 &compiler_state);
3184 if (r)
3185 return false;
3186 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3187 }
3188 } else {
3189 /* TES as VS */
3190 r = si_shader_select(ctx, &sctx->tes_shader,
3191 &compiler_state);
3192 if (r)
3193 return false;
3194 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3195 }
3196 } else if (sctx->gs_shader.cso) {
3197 if (sctx->chip_class <= VI) {
3198 /* VS as ES */
3199 r = si_shader_select(ctx, &sctx->vs_shader,
3200 &compiler_state);
3201 if (r)
3202 return false;
3203 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3204
3205 si_pm4_bind_state(sctx, ls, NULL);
3206 si_pm4_bind_state(sctx, hs, NULL);
3207 }
3208 } else {
3209 /* VS as VS */
3210 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
3211 if (r)
3212 return false;
3213 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3214 si_pm4_bind_state(sctx, ls, NULL);
3215 si_pm4_bind_state(sctx, hs, NULL);
3216 }
3217
3218 /* Update GS. */
3219 if (sctx->gs_shader.cso) {
3220 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
3221 if (r)
3222 return false;
3223 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3224 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3225
3226 if (!si_update_gs_ring_buffers(sctx))
3227 return false;
3228 } else {
3229 si_pm4_bind_state(sctx, gs, NULL);
3230 if (sctx->chip_class <= VI)
3231 si_pm4_bind_state(sctx, es, NULL);
3232 }
3233
3234 si_update_vgt_shader_config(sctx);
3235
3236 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3237 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3238
3239 if (sctx->ps_shader.cso) {
3240 unsigned db_shader_control;
3241
3242 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
3243 if (r)
3244 return false;
3245 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3246
3247 db_shader_control =
3248 sctx->ps_shader.cso->db_shader_control |
3249 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3250
3251 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3252 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3253 sctx->flatshade != rs->flatshade) {
3254 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3255 sctx->flatshade = rs->flatshade;
3256 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3257 }
3258
3259 if (sctx->screen->rbplus_allowed &&
3260 si_pm4_state_changed(sctx, ps) &&
3261 (!old_ps ||
3262 old_spi_shader_col_format !=
3263 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3264 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3265
3266 if (sctx->ps_db_shader_control != db_shader_control) {
3267 sctx->ps_db_shader_control = db_shader_control;
3268 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3269 if (sctx->screen->dpbb_allowed)
3270 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3271 }
3272
3273 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3274 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3275 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3276
3277 if (sctx->chip_class == SI)
3278 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3279
3280 if (sctx->framebuffer.nr_samples <= 1)
3281 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3282 }
3283 }
3284
3285 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3286 si_pm4_state_enabled_and_changed(sctx, hs) ||
3287 si_pm4_state_enabled_and_changed(sctx, es) ||
3288 si_pm4_state_enabled_and_changed(sctx, gs) ||
3289 si_pm4_state_enabled_and_changed(sctx, vs) ||
3290 si_pm4_state_enabled_and_changed(sctx, ps)) {
3291 if (!si_update_spi_tmpring_size(sctx))
3292 return false;
3293 }
3294
3295 if (sctx->chip_class >= CIK) {
3296 if (si_pm4_state_enabled_and_changed(sctx, ls))
3297 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3298 else if (!sctx->queued.named.ls)
3299 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3300
3301 if (si_pm4_state_enabled_and_changed(sctx, hs))
3302 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3303 else if (!sctx->queued.named.hs)
3304 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3305
3306 if (si_pm4_state_enabled_and_changed(sctx, es))
3307 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3308 else if (!sctx->queued.named.es)
3309 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3310
3311 if (si_pm4_state_enabled_and_changed(sctx, gs))
3312 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3313 else if (!sctx->queued.named.gs)
3314 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3315
3316 if (si_pm4_state_enabled_and_changed(sctx, vs))
3317 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3318 else if (!sctx->queued.named.vs)
3319 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3320
3321 if (si_pm4_state_enabled_and_changed(sctx, ps))
3322 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3323 else if (!sctx->queued.named.ps)
3324 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3325 }
3326
3327 sctx->do_update_shaders = false;
3328 return true;
3329 }
3330
3331 static void si_emit_scratch_state(struct si_context *sctx,
3332 struct si_atom *atom)
3333 {
3334 struct radeon_winsys_cs *cs = sctx->gfx_cs;
3335
3336 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3337 sctx->spi_tmpring_size);
3338
3339 if (sctx->scratch_buffer) {
3340 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3341 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3342 RADEON_PRIO_SCRATCH_BUFFER);
3343 }
3344 }
3345
3346 void *si_get_blit_vs(struct si_context *sctx, enum blitter_attrib_type type,
3347 unsigned num_layers)
3348 {
3349 unsigned vs_blit_property;
3350 void **vs;
3351
3352 switch (type) {
3353 case UTIL_BLITTER_ATTRIB_NONE:
3354 vs = num_layers > 1 ? &sctx->vs_blit_pos_layered :
3355 &sctx->vs_blit_pos;
3356 vs_blit_property = SI_VS_BLIT_SGPRS_POS;
3357 break;
3358 case UTIL_BLITTER_ATTRIB_COLOR:
3359 vs = num_layers > 1 ? &sctx->vs_blit_color_layered :
3360 &sctx->vs_blit_color;
3361 vs_blit_property = SI_VS_BLIT_SGPRS_POS_COLOR;
3362 break;
3363 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
3364 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
3365 assert(num_layers == 1);
3366 vs = &sctx->vs_blit_texcoord;
3367 vs_blit_property = SI_VS_BLIT_SGPRS_POS_TEXCOORD;
3368 break;
3369 default:
3370 assert(0);
3371 return NULL;
3372 }
3373 if (*vs)
3374 return *vs;
3375
3376 struct ureg_program *ureg = ureg_create(PIPE_SHADER_VERTEX);
3377 if (!ureg)
3378 return NULL;
3379
3380 /* Tell the shader to load VS inputs from SGPRs: */
3381 ureg_property(ureg, TGSI_PROPERTY_VS_BLIT_SGPRS, vs_blit_property);
3382 ureg_property(ureg, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, true);
3383
3384 /* This is just a pass-through shader with 1-3 MOV instructions. */
3385 ureg_MOV(ureg,
3386 ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0),
3387 ureg_DECL_vs_input(ureg, 0));
3388
3389 if (type != UTIL_BLITTER_ATTRIB_NONE) {
3390 ureg_MOV(ureg,
3391 ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 0),
3392 ureg_DECL_vs_input(ureg, 1));
3393 }
3394
3395 if (num_layers > 1) {
3396 struct ureg_src instance_id =
3397 ureg_DECL_system_value(ureg, TGSI_SEMANTIC_INSTANCEID, 0);
3398 struct ureg_dst layer =
3399 ureg_DECL_output(ureg, TGSI_SEMANTIC_LAYER, 0);
3400
3401 ureg_MOV(ureg, ureg_writemask(layer, TGSI_WRITEMASK_X),
3402 ureg_scalar(instance_id, TGSI_SWIZZLE_X));
3403 }
3404 ureg_END(ureg);
3405
3406 *vs = ureg_create_shader_and_destroy(ureg, &sctx->b);
3407 return *vs;
3408 }
3409
3410 void si_init_shader_functions(struct si_context *sctx)
3411 {
3412 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
3413 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
3414
3415 sctx->b.create_vs_state = si_create_shader_selector;
3416 sctx->b.create_tcs_state = si_create_shader_selector;
3417 sctx->b.create_tes_state = si_create_shader_selector;
3418 sctx->b.create_gs_state = si_create_shader_selector;
3419 sctx->b.create_fs_state = si_create_shader_selector;
3420
3421 sctx->b.bind_vs_state = si_bind_vs_shader;
3422 sctx->b.bind_tcs_state = si_bind_tcs_shader;
3423 sctx->b.bind_tes_state = si_bind_tes_shader;
3424 sctx->b.bind_gs_state = si_bind_gs_shader;
3425 sctx->b.bind_fs_state = si_bind_ps_shader;
3426
3427 sctx->b.delete_vs_state = si_delete_shader_selector;
3428 sctx->b.delete_tcs_state = si_delete_shader_selector;
3429 sctx->b.delete_tes_state = si_delete_shader_selector;
3430 sctx->b.delete_gs_state = si_delete_shader_selector;
3431 sctx->b.delete_fs_state = si_delete_shader_selector;
3432 }