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radeonsi: simplify si_get_input_prim and remove incorrect TODO comment
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
45 * size as integer.
46 */
47 void *si_get_ir_binary(struct si_shader_selector *sel)
48 {
49 struct blob blob;
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->tokens) {
54 ir_binary = sel->tokens;
55 ir_size = tgsi_num_tokens(sel->tokens) *
56 sizeof(struct tgsi_token);
57 } else {
58 assert(sel->nir);
59
60 blob_init(&blob);
61 nir_serialize(&blob, sel->nir);
62 ir_binary = blob.data;
63 ir_size = blob.size;
64 }
65
66 unsigned size = 4 + ir_size + sizeof(sel->so);
67 char *result = (char*)MALLOC(size);
68 if (!result)
69 return NULL;
70
71 *((uint32_t*)result) = size;
72 memcpy(result + 4, ir_binary, ir_size);
73 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
74
75 if (sel->nir)
76 blob_finish(&blob);
77
78 return result;
79 }
80
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
83 {
84 /* data may be NULL if size == 0 */
85 if (size)
86 memcpy(ptr, data, size);
87 ptr += DIV_ROUND_UP(size, 4);
88 return ptr;
89 }
90
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
93 {
94 memcpy(data, ptr, size);
95 ptr += DIV_ROUND_UP(size, 4);
96 return ptr;
97 }
98
99 /**
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
102 */
103 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
104 {
105 *ptr++ = size;
106 return write_data(ptr, data, size);
107 }
108
109 /**
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
112 */
113 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
114 {
115 *size = *ptr++;
116 assert(*data == NULL);
117 if (!*size)
118 return ptr;
119 *data = malloc(*size);
120 return read_data(ptr, *data, *size);
121 }
122
123 /**
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
125 * as integer.
126 */
127 static void *si_get_shader_binary(struct si_shader *shader)
128 {
129 /* There is always a size of data followed by the data itself. */
130 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
131 strlen(shader->binary.llvm_ir_string) + 1 : 0;
132
133 /* Refuse to allocate overly large buffers and guard against integer
134 * overflow. */
135 if (shader->binary.elf_size > UINT_MAX / 4 ||
136 llvm_ir_size > UINT_MAX / 4)
137 return NULL;
138
139 unsigned size =
140 4 + /* total size */
141 4 + /* CRC32 of the data below */
142 align(sizeof(shader->config), 4) +
143 align(sizeof(shader->info), 4) +
144 4 + align(shader->binary.elf_size, 4) +
145 4 + align(llvm_ir_size, 4);
146 void *buffer = CALLOC(1, size);
147 uint32_t *ptr = (uint32_t*)buffer;
148
149 if (!buffer)
150 return NULL;
151
152 *ptr++ = size;
153 ptr++; /* CRC32 is calculated at the end. */
154
155 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
156 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
157 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
158 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
159 assert((char *)ptr - (char *)buffer == size);
160
161 /* Compute CRC32. */
162 ptr = (uint32_t*)buffer;
163 ptr++;
164 *ptr = util_hash_crc32(ptr + 1, size - 8);
165
166 return buffer;
167 }
168
169 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
170 {
171 uint32_t *ptr = (uint32_t*)binary;
172 uint32_t size = *ptr++;
173 uint32_t crc32 = *ptr++;
174 unsigned chunk_size;
175 unsigned elf_size;
176
177 if (util_hash_crc32(ptr, size - 8) != crc32) {
178 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
179 return false;
180 }
181
182 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
183 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
184 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
185 &elf_size);
186 shader->binary.elf_size = elf_size;
187 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
188
189 return true;
190 }
191
192 /**
193 * Insert a shader into the cache. It's assumed the shader is not in the cache.
194 * Use si_shader_cache_load_shader before calling this.
195 *
196 * Returns false on failure, in which case the ir_binary should be freed.
197 */
198 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
199 struct si_shader *shader,
200 bool insert_into_disk_cache)
201 {
202 void *hw_binary;
203 struct hash_entry *entry;
204 uint8_t key[CACHE_KEY_SIZE];
205
206 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
207 if (entry)
208 return false; /* already added */
209
210 hw_binary = si_get_shader_binary(shader);
211 if (!hw_binary)
212 return false;
213
214 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
215 hw_binary) == NULL) {
216 FREE(hw_binary);
217 return false;
218 }
219
220 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
221 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
222 *((uint32_t *)ir_binary), key);
223 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
224 *((uint32_t *) hw_binary), NULL);
225 }
226
227 return true;
228 }
229
230 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
231 struct si_shader *shader)
232 {
233 struct hash_entry *entry =
234 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
235 if (!entry) {
236 if (sscreen->disk_shader_cache) {
237 unsigned char sha1[CACHE_KEY_SIZE];
238 size_t tg_size = *((uint32_t *) ir_binary);
239
240 disk_cache_compute_key(sscreen->disk_shader_cache,
241 ir_binary, tg_size, sha1);
242
243 size_t binary_size;
244 uint8_t *buffer =
245 disk_cache_get(sscreen->disk_shader_cache,
246 sha1, &binary_size);
247 if (!buffer)
248 return false;
249
250 if (binary_size < sizeof(uint32_t) ||
251 *((uint32_t*)buffer) != binary_size) {
252 /* Something has gone wrong discard the item
253 * from the cache and rebuild/link from
254 * source.
255 */
256 assert(!"Invalid radeonsi shader disk cache "
257 "item!");
258
259 disk_cache_remove(sscreen->disk_shader_cache,
260 sha1);
261 free(buffer);
262
263 return false;
264 }
265
266 if (!si_load_shader_binary(shader, buffer)) {
267 free(buffer);
268 return false;
269 }
270 free(buffer);
271
272 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
273 shader, false))
274 FREE(ir_binary);
275 } else {
276 return false;
277 }
278 } else {
279 if (si_load_shader_binary(shader, entry->data))
280 FREE(ir_binary);
281 else
282 return false;
283 }
284 p_atomic_inc(&sscreen->num_shader_cache_hits);
285 return true;
286 }
287
288 static uint32_t si_shader_cache_key_hash(const void *key)
289 {
290 /* The first dword is the key size. */
291 return util_hash_crc32(key, *(uint32_t*)key);
292 }
293
294 static bool si_shader_cache_key_equals(const void *a, const void *b)
295 {
296 uint32_t *keya = (uint32_t*)a;
297 uint32_t *keyb = (uint32_t*)b;
298
299 /* The first dword is the key size. */
300 if (*keya != *keyb)
301 return false;
302
303 return memcmp(keya, keyb, *keya) == 0;
304 }
305
306 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
307 {
308 FREE((void*)entry->key);
309 FREE(entry->data);
310 }
311
312 bool si_init_shader_cache(struct si_screen *sscreen)
313 {
314 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
315 sscreen->shader_cache =
316 _mesa_hash_table_create(NULL,
317 si_shader_cache_key_hash,
318 si_shader_cache_key_equals);
319
320 return sscreen->shader_cache != NULL;
321 }
322
323 void si_destroy_shader_cache(struct si_screen *sscreen)
324 {
325 if (sscreen->shader_cache)
326 _mesa_hash_table_destroy(sscreen->shader_cache,
327 si_destroy_shader_cache_entry);
328 mtx_destroy(&sscreen->shader_cache_mutex);
329 }
330
331 /* SHADER STATES */
332
333 static void si_set_tesseval_regs(struct si_screen *sscreen,
334 const struct si_shader_selector *tes,
335 struct si_pm4_state *pm4)
336 {
337 const struct tgsi_shader_info *info = &tes->info;
338 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
339 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
340 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
341 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
342 unsigned type, partitioning, topology, distribution_mode;
343
344 switch (tes_prim_mode) {
345 case PIPE_PRIM_LINES:
346 type = V_028B6C_TESS_ISOLINE;
347 break;
348 case PIPE_PRIM_TRIANGLES:
349 type = V_028B6C_TESS_TRIANGLE;
350 break;
351 case PIPE_PRIM_QUADS:
352 type = V_028B6C_TESS_QUAD;
353 break;
354 default:
355 assert(0);
356 return;
357 }
358
359 switch (tes_spacing) {
360 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
361 partitioning = V_028B6C_PART_FRAC_ODD;
362 break;
363 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
364 partitioning = V_028B6C_PART_FRAC_EVEN;
365 break;
366 case PIPE_TESS_SPACING_EQUAL:
367 partitioning = V_028B6C_PART_INTEGER;
368 break;
369 default:
370 assert(0);
371 return;
372 }
373
374 if (tes_point_mode)
375 topology = V_028B6C_OUTPUT_POINT;
376 else if (tes_prim_mode == PIPE_PRIM_LINES)
377 topology = V_028B6C_OUTPUT_LINE;
378 else if (tes_vertex_order_cw)
379 /* for some reason, this must be the other way around */
380 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
381 else
382 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
383
384 if (sscreen->has_distributed_tess) {
385 if (sscreen->info.family == CHIP_FIJI ||
386 sscreen->info.family >= CHIP_POLARIS10)
387 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
388 else
389 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
390 } else
391 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
392
393 assert(pm4->shader);
394 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
395 S_028B6C_PARTITIONING(partitioning) |
396 S_028B6C_TOPOLOGY(topology) |
397 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
398 }
399
400 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
401 * whether the "fractional odd" tessellation spacing is used.
402 *
403 * Possible VGT configurations and which state should set the register:
404 *
405 * Reg set in | VGT shader configuration | Value
406 * ------------------------------------------------------
407 * VS as VS | VS | 30
408 * VS as ES | ES -> GS -> VS | 30
409 * TES as VS | LS -> HS -> VS | 14 or 30
410 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
411 *
412 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
413 */
414 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
415 struct si_shader_selector *sel,
416 struct si_shader *shader,
417 struct si_pm4_state *pm4)
418 {
419 unsigned type = sel->type;
420
421 if (sscreen->info.family < CHIP_POLARIS10 ||
422 sscreen->info.chip_class >= GFX10)
423 return;
424
425 /* VS as VS, or VS as ES: */
426 if ((type == PIPE_SHADER_VERTEX &&
427 (!shader ||
428 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
429 /* TES as VS, or TES as ES: */
430 type == PIPE_SHADER_TESS_EVAL) {
431 unsigned vtx_reuse_depth = 30;
432
433 if (type == PIPE_SHADER_TESS_EVAL &&
434 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
435 PIPE_TESS_SPACING_FRACTIONAL_ODD)
436 vtx_reuse_depth = 14;
437
438 assert(pm4->shader);
439 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
440 }
441 }
442
443 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
444 {
445 if (shader->pm4)
446 si_pm4_clear_state(shader->pm4);
447 else
448 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
449
450 if (shader->pm4) {
451 shader->pm4->shader = shader;
452 return shader->pm4;
453 } else {
454 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
455 return NULL;
456 }
457 }
458
459 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
460 {
461 /* Add the pointer to VBO descriptors. */
462 return num_always_on_user_sgprs + 1;
463 }
464
465 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
466 {
467 struct si_pm4_state *pm4;
468 unsigned vgpr_comp_cnt;
469 uint64_t va;
470
471 assert(sscreen->info.chip_class <= GFX8);
472
473 pm4 = si_get_shader_pm4_state(shader);
474 if (!pm4)
475 return;
476
477 va = shader->bo->gpu_address;
478 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
479
480 /* We need at least 2 components for LS.
481 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
482 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
483 */
484 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
485
486 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
487 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
488
489 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
490 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
491 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
492 S_00B528_DX10_CLAMP(1) |
493 S_00B528_FLOAT_MODE(shader->config.float_mode);
494 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
495 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
496 }
497
498 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
499 {
500 struct si_pm4_state *pm4;
501 uint64_t va;
502 unsigned ls_vgpr_comp_cnt = 0;
503
504 pm4 = si_get_shader_pm4_state(shader);
505 if (!pm4)
506 return;
507
508 va = shader->bo->gpu_address;
509 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
510
511 if (sscreen->info.chip_class >= GFX9) {
512 if (sscreen->info.chip_class >= GFX10) {
513 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
514 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
515 } else {
516 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
517 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
518 }
519
520 /* We need at least 2 components for LS.
521 * GFX9 VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
522 * GFX10 VGPR0-3: (VertexID, RelAutoindex, UserVGPR1, InstanceID).
523 * On gfx9, StepRate0 is set to 1 so that VGPR3 doesn't have to
524 * be loaded.
525 */
526 ls_vgpr_comp_cnt = 1;
527 if (shader->info.uses_instanceid) {
528 if (sscreen->info.chip_class >= GFX10)
529 ls_vgpr_comp_cnt = 3;
530 else
531 ls_vgpr_comp_cnt = 2;
532 }
533
534 unsigned num_user_sgprs =
535 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
536
537 shader->config.rsrc2 =
538 S_00B42C_USER_SGPR(num_user_sgprs) |
539 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
540
541 if (sscreen->info.chip_class >= GFX10)
542 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
543 else
544 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
545 } else {
546 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
547 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
548
549 shader->config.rsrc2 =
550 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
551 S_00B42C_OC_LDS_EN(1) |
552 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
553 }
554
555 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
556 S_00B428_VGPRS((shader->config.num_vgprs - 1) /
557 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
558 (sscreen->info.chip_class <= GFX9 ?
559 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
560 S_00B428_DX10_CLAMP(1) |
561 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
562 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
563 S_00B428_FLOAT_MODE(shader->config.float_mode) |
564 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
565
566 if (sscreen->info.chip_class <= GFX8) {
567 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
568 shader->config.rsrc2);
569 }
570 }
571
572 static void si_emit_shader_es(struct si_context *sctx)
573 {
574 struct si_shader *shader = sctx->queued.named.es->shader;
575 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
576
577 if (!shader)
578 return;
579
580 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
581 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
582 shader->selector->esgs_itemsize / 4);
583
584 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
585 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
586 SI_TRACKED_VGT_TF_PARAM,
587 shader->vgt_tf_param);
588
589 if (shader->vgt_vertex_reuse_block_cntl)
590 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
591 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
592 shader->vgt_vertex_reuse_block_cntl);
593
594 if (initial_cdw != sctx->gfx_cs->current.cdw)
595 sctx->context_roll = true;
596 }
597
598 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
599 {
600 struct si_pm4_state *pm4;
601 unsigned num_user_sgprs;
602 unsigned vgpr_comp_cnt;
603 uint64_t va;
604 unsigned oc_lds_en;
605
606 assert(sscreen->info.chip_class <= GFX8);
607
608 pm4 = si_get_shader_pm4_state(shader);
609 if (!pm4)
610 return;
611
612 pm4->atom.emit = si_emit_shader_es;
613 va = shader->bo->gpu_address;
614 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
615
616 if (shader->selector->type == PIPE_SHADER_VERTEX) {
617 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
618 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
619 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
620 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
621 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
622 num_user_sgprs = SI_TES_NUM_USER_SGPR;
623 } else
624 unreachable("invalid shader selector type");
625
626 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
627
628 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
629 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
630 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
631 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
632 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
633 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
634 S_00B328_DX10_CLAMP(1) |
635 S_00B328_FLOAT_MODE(shader->config.float_mode));
636 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
637 S_00B32C_USER_SGPR(num_user_sgprs) |
638 S_00B32C_OC_LDS_EN(oc_lds_en) |
639 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
640
641 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
642 si_set_tesseval_regs(sscreen, shader->selector, pm4);
643
644 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
645 }
646
647 void gfx9_get_gs_info(struct si_shader_selector *es,
648 struct si_shader_selector *gs,
649 struct gfx9_gs_info *out)
650 {
651 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
652 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
653 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
654 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
655
656 /* All these are in dwords: */
657 /* We can't allow using the whole LDS, because GS waves compete with
658 * other shader stages for LDS space. */
659 const unsigned max_lds_size = 8 * 1024;
660 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
661 unsigned esgs_lds_size;
662
663 /* All these are per subgroup: */
664 const unsigned max_out_prims = 32 * 1024;
665 const unsigned max_es_verts = 255;
666 const unsigned ideal_gs_prims = 64;
667 unsigned max_gs_prims, gs_prims;
668 unsigned min_es_verts, es_verts, worst_case_es_verts;
669
670 if (uses_adjacency || gs_num_invocations > 1)
671 max_gs_prims = 127 / gs_num_invocations;
672 else
673 max_gs_prims = 255;
674
675 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
676 * Make sure we don't go over the maximum value.
677 */
678 if (gs->gs_max_out_vertices > 0) {
679 max_gs_prims = MIN2(max_gs_prims,
680 max_out_prims /
681 (gs->gs_max_out_vertices * gs_num_invocations));
682 }
683 assert(max_gs_prims > 0);
684
685 /* If the primitive has adjacency, halve the number of vertices
686 * that will be reused in multiple primitives.
687 */
688 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
689
690 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
691 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
692
693 /* Compute ESGS LDS size based on the worst case number of ES vertices
694 * needed to create the target number of GS prims per subgroup.
695 */
696 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
697
698 /* If total LDS usage is too big, refactor partitions based on ratio
699 * of ESGS item sizes.
700 */
701 if (esgs_lds_size > max_lds_size) {
702 /* Our target GS Prims Per Subgroup was too large. Calculate
703 * the maximum number of GS Prims Per Subgroup that will fit
704 * into LDS, capped by the maximum that the hardware can support.
705 */
706 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
707 max_gs_prims);
708 assert(gs_prims > 0);
709 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
710 max_es_verts);
711
712 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
713 assert(esgs_lds_size <= max_lds_size);
714 }
715
716 /* Now calculate remaining ESGS information. */
717 if (esgs_lds_size)
718 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
719 else
720 es_verts = max_es_verts;
721
722 /* Vertices for adjacency primitives are not always reused, so restore
723 * it for ES_VERTS_PER_SUBGRP.
724 */
725 min_es_verts = gs->gs_input_verts_per_prim;
726
727 /* For normal primitives, the VGT only checks if they are past the ES
728 * verts per subgroup after allocating a full GS primitive and if they
729 * are, kick off a new subgroup. But if those additional ES verts are
730 * unique (e.g. not reused) we need to make sure there is enough LDS
731 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
732 */
733 es_verts -= min_es_verts - 1;
734
735 out->es_verts_per_subgroup = es_verts;
736 out->gs_prims_per_subgroup = gs_prims;
737 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
738 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
739 gs->gs_max_out_vertices;
740 out->esgs_ring_size = 4 * esgs_lds_size;
741
742 assert(out->max_prims_per_subgroup <= max_out_prims);
743 }
744
745 static void si_emit_shader_gs(struct si_context *sctx)
746 {
747 struct si_shader *shader = sctx->queued.named.gs->shader;
748 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
749
750 if (!shader)
751 return;
752
753 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
754 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
755 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
756 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
757 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
758 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
759 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
760
761 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
762 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
763 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
764 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
765
766 /* R_028B38_VGT_GS_MAX_VERT_OUT */
767 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
768 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
769 shader->ctx_reg.gs.vgt_gs_max_vert_out);
770
771 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
772 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
773 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
774 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
775 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
776 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
777 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
778 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
779
780 /* R_028B90_VGT_GS_INSTANCE_CNT */
781 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
782 SI_TRACKED_VGT_GS_INSTANCE_CNT,
783 shader->ctx_reg.gs.vgt_gs_instance_cnt);
784
785 if (sctx->chip_class >= GFX9) {
786 /* R_028A44_VGT_GS_ONCHIP_CNTL */
787 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
788 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
789 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
790 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
791 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
792 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
793 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
794 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
795 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
796 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
797 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
798
799 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
800 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
801 SI_TRACKED_VGT_TF_PARAM,
802 shader->vgt_tf_param);
803 if (shader->vgt_vertex_reuse_block_cntl)
804 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
805 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
806 shader->vgt_vertex_reuse_block_cntl);
807 }
808
809 if (initial_cdw != sctx->gfx_cs->current.cdw)
810 sctx->context_roll = true;
811 }
812
813 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
814 {
815 struct si_shader_selector *sel = shader->selector;
816 const ubyte *num_components = sel->info.num_stream_output_components;
817 unsigned gs_num_invocations = sel->gs_num_invocations;
818 struct si_pm4_state *pm4;
819 uint64_t va;
820 unsigned max_stream = sel->max_gs_stream;
821 unsigned offset;
822
823 pm4 = si_get_shader_pm4_state(shader);
824 if (!pm4)
825 return;
826
827 pm4->atom.emit = si_emit_shader_gs;
828
829 offset = num_components[0] * sel->gs_max_out_vertices;
830 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
831
832 if (max_stream >= 1)
833 offset += num_components[1] * sel->gs_max_out_vertices;
834 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
835
836 if (max_stream >= 2)
837 offset += num_components[2] * sel->gs_max_out_vertices;
838 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
839
840 if (max_stream >= 3)
841 offset += num_components[3] * sel->gs_max_out_vertices;
842 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
843
844 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
845 assert(offset < (1 << 15));
846
847 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
848
849 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
850 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
851 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
852 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
853
854 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
855 S_028B90_ENABLE(gs_num_invocations > 0);
856
857 va = shader->bo->gpu_address;
858 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
859
860 if (sscreen->info.chip_class >= GFX9) {
861 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
862 unsigned es_type = shader->key.part.gs.es->type;
863 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
864
865 if (es_type == PIPE_SHADER_VERTEX)
866 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
867 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
868 else if (es_type == PIPE_SHADER_TESS_EVAL)
869 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
870 else
871 unreachable("invalid shader selector type");
872
873 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
874 * VGPR[0:4] are always loaded.
875 */
876 if (sel->info.uses_invocationid)
877 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
878 else if (sel->info.uses_primid)
879 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
880 else if (input_prim >= PIPE_PRIM_TRIANGLES)
881 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
882 else
883 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
884
885 unsigned num_user_sgprs;
886 if (es_type == PIPE_SHADER_VERTEX)
887 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
888 else
889 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
890
891 if (sscreen->info.chip_class >= GFX10) {
892 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
893 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
894 } else {
895 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
896 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
897 }
898
899 uint32_t rsrc1 =
900 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
901 S_00B228_DX10_CLAMP(1) |
902 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
903 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
904 S_00B228_FLOAT_MODE(shader->config.float_mode) |
905 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
906 uint32_t rsrc2 =
907 S_00B22C_USER_SGPR(num_user_sgprs) |
908 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
909 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
910 S_00B22C_LDS_SIZE(shader->config.lds_size) |
911 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
912
913 if (sscreen->info.chip_class >= GFX10) {
914 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
915 } else {
916 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
917 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
918 }
919
920 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
921 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
922
923 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
924 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
925 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
926 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
927 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
928 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
929 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
930 shader->key.part.gs.es->esgs_itemsize / 4;
931
932 if (es_type == PIPE_SHADER_TESS_EVAL)
933 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
934
935 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
936 NULL, pm4);
937 } else {
938 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
939 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
940
941 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
942 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
943 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
944 S_00B228_DX10_CLAMP(1) |
945 S_00B228_FLOAT_MODE(shader->config.float_mode));
946 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
947 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
948 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
949 }
950 }
951
952 /* Common tail code for NGG primitive shaders. */
953 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
954 struct si_shader *shader,
955 unsigned initial_cdw)
956 {
957 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
958 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
959 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
960 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
961 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
962 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
963 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
964 SI_TRACKED_VGT_PRIMITIVEID_EN,
965 shader->ctx_reg.ngg.vgt_primitiveid_en);
966 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
967 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
968 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
969 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
970 SI_TRACKED_VGT_GS_INSTANCE_CNT,
971 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
972 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
973 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
974 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
975 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
976 SI_TRACKED_VGT_REUSE_OFF,
977 shader->ctx_reg.ngg.vgt_reuse_off);
978 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
979 SI_TRACKED_SPI_VS_OUT_CONFIG,
980 shader->ctx_reg.ngg.spi_vs_out_config);
981 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
982 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
983 shader->ctx_reg.ngg.spi_shader_idx_format,
984 shader->ctx_reg.ngg.spi_shader_pos_format);
985 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
986 SI_TRACKED_PA_CL_VTE_CNTL,
987 shader->ctx_reg.ngg.pa_cl_vte_cntl);
988 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
989 SI_TRACKED_PA_CL_NGG_CNTL,
990 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
991
992 if (initial_cdw != sctx->gfx_cs->current.cdw)
993 sctx->context_roll = true;
994 }
995
996 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
997 {
998 struct si_shader *shader = sctx->queued.named.gs->shader;
999 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1000
1001 if (!shader)
1002 return;
1003
1004 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1005 }
1006
1007 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1008 {
1009 struct si_shader *shader = sctx->queued.named.gs->shader;
1010 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1011
1012 if (!shader)
1013 return;
1014
1015 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1016 SI_TRACKED_VGT_TF_PARAM,
1017 shader->vgt_tf_param);
1018
1019 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1020 }
1021
1022 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1023 {
1024 struct si_shader *shader = sctx->queued.named.gs->shader;
1025 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1026
1027 if (!shader)
1028 return;
1029
1030 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1031 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1032 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1033
1034 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1035 }
1036
1037 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1038 {
1039 struct si_shader *shader = sctx->queued.named.gs->shader;
1040 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1041
1042 if (!shader)
1043 return;
1044
1045 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1046 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1047 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1048 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1049 SI_TRACKED_VGT_TF_PARAM,
1050 shader->vgt_tf_param);
1051
1052 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1053 }
1054
1055 static void si_set_ge_pc_alloc(struct si_screen *sscreen,
1056 struct si_pm4_state *pm4, bool culling)
1057 {
1058 si_pm4_set_reg(pm4, R_030980_GE_PC_ALLOC,
1059 S_030980_OVERSUB_EN(1) |
1060 S_030980_NUM_PC_LINES((culling ? 256 : 128) * sscreen->info.max_se - 1));
1061 }
1062
1063 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1064 {
1065 if (gs->type == PIPE_SHADER_GEOMETRY)
1066 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1067
1068 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1069 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1070 return PIPE_PRIM_POINTS;
1071 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1072 return PIPE_PRIM_LINES;
1073 return PIPE_PRIM_TRIANGLES;
1074 }
1075
1076 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1077 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1078 }
1079
1080 /**
1081 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1082 * in NGG mode.
1083 */
1084 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1085 {
1086 const struct si_shader_selector *gs_sel = shader->selector;
1087 const struct tgsi_shader_info *gs_info = &gs_sel->info;
1088 enum pipe_shader_type gs_type = shader->selector->type;
1089 const struct si_shader_selector *es_sel =
1090 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1091 const struct tgsi_shader_info *es_info = &es_sel->info;
1092 enum pipe_shader_type es_type = es_sel->type;
1093 unsigned num_user_sgprs;
1094 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1095 uint64_t va;
1096 unsigned window_space =
1097 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1098 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1099 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1100 unsigned input_prim = si_get_input_prim(gs_sel);
1101 bool break_wave_at_eoi = false;
1102 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1103 if (!pm4)
1104 return;
1105
1106 if (es_type == PIPE_SHADER_TESS_EVAL) {
1107 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1108 : gfx10_emit_shader_ngg_tess_nogs;
1109 } else {
1110 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1111 : gfx10_emit_shader_ngg_notess_nogs;
1112 }
1113
1114 va = shader->bo->gpu_address;
1115 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1116
1117 if (es_type == PIPE_SHADER_VERTEX) {
1118 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1119 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
1120
1121 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1122 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1123 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1124 } else {
1125 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
1126 }
1127 } else {
1128 assert(es_type == PIPE_SHADER_TESS_EVAL);
1129 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1130 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1131
1132 if (es_enable_prim_id || gs_info->uses_primid)
1133 break_wave_at_eoi = true;
1134 }
1135
1136 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1137 * VGPR[0:4] are always loaded.
1138 *
1139 * Vertex shaders always need to load VGPR3, because they need to
1140 * pass edge flags for decomposed primitives (such as quads) to the PA
1141 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1142 */
1143 if (gs_info->uses_invocationid || gs_type == PIPE_SHADER_VERTEX)
1144 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1145 else if (gs_info->uses_primid)
1146 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1147 else if (input_prim >= PIPE_PRIM_TRIANGLES)
1148 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1149 else
1150 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1151
1152 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1153 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1154 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1155 S_00B228_VGPRS((shader->config.num_vgprs - 1) /
1156 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1157 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1158 S_00B228_DX10_CLAMP(1) |
1159 S_00B228_MEM_ORDERED(1) |
1160 S_00B228_WGP_MODE(1) |
1161 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1162 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1163 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1164 S_00B22C_USER_SGPR(num_user_sgprs) |
1165 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1166 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1167 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1168 S_00B22C_LDS_SIZE(shader->config.lds_size));
1169 si_set_ge_pc_alloc(sscreen, pm4, false);
1170
1171 nparams = MAX2(shader->info.nr_param_exports, 1);
1172 shader->ctx_reg.ngg.spi_vs_out_config =
1173 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1174 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1175
1176 shader->ctx_reg.ngg.spi_shader_idx_format =
1177 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1178 shader->ctx_reg.ngg.spi_shader_pos_format =
1179 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1180 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1181 V_02870C_SPI_SHADER_4COMP :
1182 V_02870C_SPI_SHADER_NONE) |
1183 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1184 V_02870C_SPI_SHADER_4COMP :
1185 V_02870C_SPI_SHADER_NONE) |
1186 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1187 V_02870C_SPI_SHADER_4COMP :
1188 V_02870C_SPI_SHADER_NONE);
1189
1190 shader->ctx_reg.ngg.vgt_primitiveid_en =
1191 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1192 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id);
1193
1194 if (gs_type == PIPE_SHADER_GEOMETRY) {
1195 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1196 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1197 } else {
1198 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1199 }
1200
1201 if (es_type == PIPE_SHADER_TESS_EVAL)
1202 si_set_tesseval_regs(sscreen, es_sel, pm4);
1203
1204 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1205 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1206 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1207 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1208 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1209 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1210 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1211 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1212 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1213 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1214 S_028B90_CNT(gs_num_invocations) |
1215 S_028B90_ENABLE(gs_num_invocations > 1) |
1216 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1217 shader->ngg.max_vert_out_per_gs_instance);
1218
1219 /* Always output hw-generated edge flags and pass them via the prim
1220 * export to prevent drawing lines on internal edges of decomposed
1221 * primitives (such as quads) with polygon mode = lines. Only VS needs
1222 * this.
1223 */
1224 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1225 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
1226
1227 shader->ge_cntl =
1228 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1229 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) |
1230 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1231
1232 if (window_space) {
1233 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1234 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1235 } else {
1236 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1237 S_028818_VTX_W0_FMT(1) |
1238 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1239 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1240 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1241 }
1242
1243 shader->ctx_reg.ngg.vgt_reuse_off =
1244 S_028AB4_REUSE_OFF(sscreen->info.family == CHIP_NAVI10 &&
1245 sscreen->info.chip_external_rev == 0x1 &&
1246 es_type == PIPE_SHADER_TESS_EVAL);
1247 }
1248
1249 static void si_emit_shader_vs(struct si_context *sctx)
1250 {
1251 struct si_shader *shader = sctx->queued.named.vs->shader;
1252 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1253
1254 if (!shader)
1255 return;
1256
1257 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1258 SI_TRACKED_VGT_GS_MODE,
1259 shader->ctx_reg.vs.vgt_gs_mode);
1260 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1261 SI_TRACKED_VGT_PRIMITIVEID_EN,
1262 shader->ctx_reg.vs.vgt_primitiveid_en);
1263
1264 if (sctx->chip_class <= GFX8) {
1265 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1266 SI_TRACKED_VGT_REUSE_OFF,
1267 shader->ctx_reg.vs.vgt_reuse_off);
1268 }
1269
1270 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1271 SI_TRACKED_SPI_VS_OUT_CONFIG,
1272 shader->ctx_reg.vs.spi_vs_out_config);
1273
1274 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1275 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1276 shader->ctx_reg.vs.spi_shader_pos_format);
1277
1278 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1279 SI_TRACKED_PA_CL_VTE_CNTL,
1280 shader->ctx_reg.vs.pa_cl_vte_cntl);
1281
1282 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1283 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1284 SI_TRACKED_VGT_TF_PARAM,
1285 shader->vgt_tf_param);
1286
1287 if (shader->vgt_vertex_reuse_block_cntl)
1288 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1289 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1290 shader->vgt_vertex_reuse_block_cntl);
1291
1292 if (initial_cdw != sctx->gfx_cs->current.cdw)
1293 sctx->context_roll = true;
1294 }
1295
1296 /**
1297 * Compute the state for \p shader, which will run as a vertex shader on the
1298 * hardware.
1299 *
1300 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1301 * is the copy shader.
1302 */
1303 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1304 struct si_shader_selector *gs)
1305 {
1306 const struct tgsi_shader_info *info = &shader->selector->info;
1307 struct si_pm4_state *pm4;
1308 unsigned num_user_sgprs, vgpr_comp_cnt;
1309 uint64_t va;
1310 unsigned nparams, oc_lds_en;
1311 unsigned window_space =
1312 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1313 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1314
1315 pm4 = si_get_shader_pm4_state(shader);
1316 if (!pm4)
1317 return;
1318
1319 pm4->atom.emit = si_emit_shader_vs;
1320
1321 /* We always write VGT_GS_MODE in the VS state, because every switch
1322 * between different shader pipelines involving a different GS or no
1323 * GS at all involves a switch of the VS (different GS use different
1324 * copy shaders). On the other hand, when the API switches from a GS to
1325 * no GS and then back to the same GS used originally, the GS state is
1326 * not sent again.
1327 */
1328 if (!gs) {
1329 unsigned mode = V_028A40_GS_OFF;
1330
1331 /* PrimID needs GS scenario A. */
1332 if (enable_prim_id)
1333 mode = V_028A40_GS_SCENARIO_A;
1334
1335 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1336 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1337 } else {
1338 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1339 sscreen->info.chip_class);
1340 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1341 }
1342
1343 if (sscreen->info.chip_class <= GFX8) {
1344 /* Reuse needs to be set off if we write oViewport. */
1345 shader->ctx_reg.vs.vgt_reuse_off =
1346 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1347 }
1348
1349 va = shader->bo->gpu_address;
1350 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1351
1352 if (gs) {
1353 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1354 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1355 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1356 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1357 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1358 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1359 */
1360 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1361
1362 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1363 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1364 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1365 } else {
1366 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1367 }
1368 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1369 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1370 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1371 } else
1372 unreachable("invalid shader selector type");
1373
1374 /* VS is required to export at least one param. */
1375 nparams = MAX2(shader->info.nr_param_exports, 1);
1376 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1377
1378 if (sscreen->info.chip_class >= GFX10) {
1379 shader->ctx_reg.vs.spi_vs_out_config |=
1380 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1381 }
1382
1383 shader->ctx_reg.vs.spi_shader_pos_format =
1384 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1385 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1386 V_02870C_SPI_SHADER_4COMP :
1387 V_02870C_SPI_SHADER_NONE) |
1388 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1389 V_02870C_SPI_SHADER_4COMP :
1390 V_02870C_SPI_SHADER_NONE) |
1391 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1392 V_02870C_SPI_SHADER_4COMP :
1393 V_02870C_SPI_SHADER_NONE);
1394
1395 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1396
1397 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1398 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1399 if (sscreen->info.chip_class >= GFX10)
1400 si_set_ge_pc_alloc(sscreen, pm4, false);
1401
1402 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
1403 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1404 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1405 S_00B128_DX10_CLAMP(1) |
1406 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1407 S_00B128_FLOAT_MODE(shader->config.float_mode);
1408 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1409 S_00B12C_OC_LDS_EN(oc_lds_en) |
1410 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1411
1412 if (sscreen->info.chip_class <= GFX9) {
1413 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1414 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1415 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1416 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1417 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1418 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1419 }
1420
1421 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1422 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1423
1424 if (window_space)
1425 shader->ctx_reg.vs.pa_cl_vte_cntl =
1426 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1427 else
1428 shader->ctx_reg.vs.pa_cl_vte_cntl =
1429 S_028818_VTX_W0_FMT(1) |
1430 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1431 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1432 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1433
1434 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1435 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1436
1437 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1438 }
1439
1440 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1441 {
1442 struct tgsi_shader_info *info = &ps->selector->info;
1443 unsigned num_colors = !!(info->colors_read & 0x0f) +
1444 !!(info->colors_read & 0xf0);
1445 unsigned num_interp = ps->selector->info.num_inputs +
1446 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1447
1448 assert(num_interp <= 32);
1449 return MIN2(num_interp, 32);
1450 }
1451
1452 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1453 {
1454 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1455 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1456
1457 /* If the i-th target format is set, all previous target formats must
1458 * be non-zero to avoid hangs.
1459 */
1460 for (i = 0; i < num_targets; i++)
1461 if (!(value & (0xf << (i * 4))))
1462 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1463
1464 return value;
1465 }
1466
1467 static void si_emit_shader_ps(struct si_context *sctx)
1468 {
1469 struct si_shader *shader = sctx->queued.named.ps->shader;
1470 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1471
1472 if (!shader)
1473 return;
1474
1475 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1476 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1477 SI_TRACKED_SPI_PS_INPUT_ENA,
1478 shader->ctx_reg.ps.spi_ps_input_ena,
1479 shader->ctx_reg.ps.spi_ps_input_addr);
1480
1481 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1482 SI_TRACKED_SPI_BARYC_CNTL,
1483 shader->ctx_reg.ps.spi_baryc_cntl);
1484 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1485 SI_TRACKED_SPI_PS_IN_CONTROL,
1486 shader->ctx_reg.ps.spi_ps_in_control);
1487
1488 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1489 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1490 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1491 shader->ctx_reg.ps.spi_shader_z_format,
1492 shader->ctx_reg.ps.spi_shader_col_format);
1493
1494 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1495 SI_TRACKED_CB_SHADER_MASK,
1496 shader->ctx_reg.ps.cb_shader_mask);
1497
1498 if (initial_cdw != sctx->gfx_cs->current.cdw)
1499 sctx->context_roll = true;
1500 }
1501
1502 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1503 {
1504 struct tgsi_shader_info *info = &shader->selector->info;
1505 struct si_pm4_state *pm4;
1506 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1507 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1508 uint64_t va;
1509 unsigned input_ena = shader->config.spi_ps_input_ena;
1510
1511 /* we need to enable at least one of them, otherwise we hang the GPU */
1512 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1513 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1514 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1515 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1516 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1517 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1518 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1519 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1520 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1521 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1522 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1523 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1524 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1525 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1526
1527 /* Validate interpolation optimization flags (read as implications). */
1528 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1529 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1530 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1531 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1532 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1533 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1534 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1535 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1536 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1537 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1538 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1539 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1540 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1541 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1542 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1543 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1544 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1545 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1546
1547 /* Validate cases when the optimizations are off (read as implications). */
1548 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1549 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1550 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1551 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1552 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1553 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1554
1555 pm4 = si_get_shader_pm4_state(shader);
1556 if (!pm4)
1557 return;
1558
1559 pm4->atom.emit = si_emit_shader_ps;
1560
1561 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1562 * Possible vaules:
1563 * 0 -> Position = pixel center
1564 * 1 -> Position = pixel centroid
1565 * 2 -> Position = at sample position
1566 *
1567 * From GLSL 4.5 specification, section 7.1:
1568 * "The variable gl_FragCoord is available as an input variable from
1569 * within fragment shaders and it holds the window relative coordinates
1570 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1571 * value can be for any location within the pixel, or one of the
1572 * fragment samples. The use of centroid does not further restrict
1573 * this value to be inside the current primitive."
1574 *
1575 * Meaning that centroid has no effect and we can return anything within
1576 * the pixel. Thus, return the value at sample position, because that's
1577 * the most accurate one shaders can get.
1578 */
1579 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1580
1581 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1582 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1583 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1584
1585 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1586 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1587
1588 /* Ensure that some export memory is always allocated, for two reasons:
1589 *
1590 * 1) Correctness: The hardware ignores the EXEC mask if no export
1591 * memory is allocated, so KILL and alpha test do not work correctly
1592 * without this.
1593 * 2) Performance: Every shader needs at least a NULL export, even when
1594 * it writes no color/depth output. The NULL export instruction
1595 * stalls without this setting.
1596 *
1597 * Don't add this to CB_SHADER_MASK.
1598 *
1599 * GFX10 supports pixel shaders without exports by setting both
1600 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1601 * instructions if any are present.
1602 */
1603 if ((sscreen->info.chip_class <= GFX9 ||
1604 info->uses_kill ||
1605 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1606 !spi_shader_col_format &&
1607 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1608 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1609
1610 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1611 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1612
1613 /* Set interpolation controls. */
1614 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1615 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1616
1617 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1618 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1619 shader->ctx_reg.ps.spi_shader_z_format =
1620 ac_get_spi_shader_z_format(info->writes_z,
1621 info->writes_stencil,
1622 info->writes_samplemask);
1623 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1624 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1625
1626 va = shader->bo->gpu_address;
1627 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1628 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1629 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1630
1631 uint32_t rsrc1 =
1632 S_00B028_VGPRS((shader->config.num_vgprs - 1) /
1633 (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1634 S_00B028_DX10_CLAMP(1) |
1635 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1636 S_00B028_FLOAT_MODE(shader->config.float_mode);
1637
1638 if (sscreen->info.chip_class < GFX10) {
1639 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1640 }
1641
1642 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1643 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1644 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1645 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1646 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1647 }
1648
1649 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1650 struct si_shader *shader)
1651 {
1652 switch (shader->selector->type) {
1653 case PIPE_SHADER_VERTEX:
1654 if (shader->key.as_ls)
1655 si_shader_ls(sscreen, shader);
1656 else if (shader->key.as_es)
1657 si_shader_es(sscreen, shader);
1658 else if (shader->key.as_ngg)
1659 gfx10_shader_ngg(sscreen, shader);
1660 else
1661 si_shader_vs(sscreen, shader, NULL);
1662 break;
1663 case PIPE_SHADER_TESS_CTRL:
1664 si_shader_hs(sscreen, shader);
1665 break;
1666 case PIPE_SHADER_TESS_EVAL:
1667 if (shader->key.as_es)
1668 si_shader_es(sscreen, shader);
1669 else if (shader->key.as_ngg)
1670 gfx10_shader_ngg(sscreen, shader);
1671 else
1672 si_shader_vs(sscreen, shader, NULL);
1673 break;
1674 case PIPE_SHADER_GEOMETRY:
1675 if (shader->key.as_ngg)
1676 gfx10_shader_ngg(sscreen, shader);
1677 else
1678 si_shader_gs(sscreen, shader);
1679 break;
1680 case PIPE_SHADER_FRAGMENT:
1681 si_shader_ps(sscreen, shader);
1682 break;
1683 default:
1684 assert(0);
1685 }
1686 }
1687
1688 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1689 {
1690 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1691 if (sctx->queued.named.dsa)
1692 return sctx->queued.named.dsa->alpha_func;
1693
1694 return PIPE_FUNC_ALWAYS;
1695 }
1696
1697 void si_shader_selector_key_vs(struct si_context *sctx,
1698 struct si_shader_selector *vs,
1699 struct si_shader_key *key,
1700 struct si_vs_prolog_bits *prolog_key)
1701 {
1702 if (!sctx->vertex_elements ||
1703 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS])
1704 return;
1705
1706 struct si_vertex_elements *elts = sctx->vertex_elements;
1707
1708 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1709 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1710 prolog_key->unpack_instance_id_from_vertex_id =
1711 sctx->prim_discard_cs_instancing;
1712
1713 /* Prefer a monolithic shader to allow scheduling divisions around
1714 * VBO loads. */
1715 if (prolog_key->instance_divisor_is_fetched)
1716 key->opt.prefer_mono = 1;
1717
1718 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1719 unsigned count_mask = (1 << count) - 1;
1720 unsigned fix = elts->fix_fetch_always & count_mask;
1721 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1722
1723 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1724 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1725 while (mask) {
1726 unsigned i = u_bit_scan(&mask);
1727 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1728 unsigned vbidx = elts->vertex_buffer_index[i];
1729 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1730 unsigned align_mask = (1 << log_hw_load_size) - 1;
1731 if (vb->buffer_offset & align_mask ||
1732 vb->stride & align_mask) {
1733 fix |= 1 << i;
1734 opencode |= 1 << i;
1735 }
1736 }
1737 }
1738
1739 while (fix) {
1740 unsigned i = u_bit_scan(&fix);
1741 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1742 }
1743 key->mono.vs_fetch_opencode = opencode;
1744 }
1745
1746 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1747 struct si_shader_selector *vs,
1748 struct si_shader_key *key)
1749 {
1750 struct si_shader_selector *ps = sctx->ps_shader.cso;
1751
1752 key->opt.clip_disable =
1753 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1754 (vs->info.clipdist_writemask ||
1755 vs->info.writes_clipvertex) &&
1756 !vs->info.culldist_writemask;
1757
1758 /* Find out if PS is disabled. */
1759 bool ps_disabled = true;
1760 if (ps) {
1761 const struct si_state_blend *blend = sctx->queued.named.blend;
1762 bool alpha_to_coverage = blend && blend->alpha_to_coverage;
1763 bool ps_modifies_zs = ps->info.uses_kill ||
1764 ps->info.writes_z ||
1765 ps->info.writes_stencil ||
1766 ps->info.writes_samplemask ||
1767 alpha_to_coverage ||
1768 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1769 unsigned ps_colormask = si_get_total_colormask(sctx);
1770
1771 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1772 (!ps_colormask &&
1773 !ps_modifies_zs &&
1774 !ps->info.writes_memory);
1775 }
1776
1777 /* Find out which VS outputs aren't used by the PS. */
1778 uint64_t outputs_written = vs->outputs_written_before_ps;
1779 uint64_t inputs_read = 0;
1780
1781 /* Ignore outputs that are not passed from VS to PS. */
1782 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1783 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1784 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1785
1786 if (!ps_disabled) {
1787 inputs_read = ps->inputs_read;
1788 }
1789
1790 uint64_t linked = outputs_written & inputs_read;
1791
1792 key->opt.kill_outputs = ~linked & outputs_written;
1793 }
1794
1795 /* Compute the key for the hw shader variant */
1796 static inline void si_shader_selector_key(struct pipe_context *ctx,
1797 struct si_shader_selector *sel,
1798 union si_vgt_stages_key stages_key,
1799 struct si_shader_key *key)
1800 {
1801 struct si_context *sctx = (struct si_context *)ctx;
1802
1803 memset(key, 0, sizeof(*key));
1804
1805 switch (sel->type) {
1806 case PIPE_SHADER_VERTEX:
1807 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1808
1809 if (sctx->tes_shader.cso)
1810 key->as_ls = 1;
1811 else if (sctx->gs_shader.cso)
1812 key->as_es = 1;
1813 else {
1814 key->as_ngg = stages_key.u.ngg;
1815 si_shader_selector_key_hw_vs(sctx, sel, key);
1816
1817 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1818 key->mono.u.vs_export_prim_id = 1;
1819 }
1820 break;
1821 case PIPE_SHADER_TESS_CTRL:
1822 if (sctx->chip_class >= GFX9) {
1823 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1824 key, &key->part.tcs.ls_prolog);
1825 key->part.tcs.ls = sctx->vs_shader.cso;
1826
1827 /* When the LS VGPR fix is needed, monolithic shaders
1828 * can:
1829 * - avoid initializing EXEC in both the LS prolog
1830 * and the LS main part when !vs_needs_prolog
1831 * - remove the fixup for unused input VGPRs
1832 */
1833 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1834
1835 /* The LS output / HS input layout can be communicated
1836 * directly instead of via user SGPRs for merged LS-HS.
1837 * The LS VGPR fix prefers this too.
1838 */
1839 key->opt.prefer_mono = 1;
1840 }
1841
1842 key->part.tcs.epilog.prim_mode =
1843 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1844 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1845 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1846 key->part.tcs.epilog.tes_reads_tess_factors =
1847 sctx->tes_shader.cso->info.reads_tess_factors;
1848
1849 if (sel == sctx->fixed_func_tcs_shader.cso)
1850 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1851 break;
1852 case PIPE_SHADER_TESS_EVAL:
1853 key->as_ngg = stages_key.u.ngg;
1854
1855 if (sctx->gs_shader.cso)
1856 key->as_es = 1;
1857 else {
1858 si_shader_selector_key_hw_vs(sctx, sel, key);
1859
1860 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1861 key->mono.u.vs_export_prim_id = 1;
1862 }
1863 break;
1864 case PIPE_SHADER_GEOMETRY:
1865 if (sctx->chip_class >= GFX9) {
1866 if (sctx->tes_shader.cso) {
1867 key->part.gs.es = sctx->tes_shader.cso;
1868 } else {
1869 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1870 key, &key->part.gs.vs_prolog);
1871 key->part.gs.es = sctx->vs_shader.cso;
1872 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1873 }
1874
1875 key->as_ngg = stages_key.u.ngg;
1876
1877 /* Merged ES-GS can have unbalanced wave usage.
1878 *
1879 * ES threads are per-vertex, while GS threads are
1880 * per-primitive. So without any amplification, there
1881 * are fewer GS threads than ES threads, which can result
1882 * in empty (no-op) GS waves. With too much amplification,
1883 * there are more GS threads than ES threads, which
1884 * can result in empty (no-op) ES waves.
1885 *
1886 * Non-monolithic shaders are implemented by setting EXEC
1887 * at the beginning of shader parts, and don't jump to
1888 * the end if EXEC is 0.
1889 *
1890 * Monolithic shaders use conditional blocks, so they can
1891 * jump and skip empty waves of ES or GS. So set this to
1892 * always use optimized variants, which are monolithic.
1893 */
1894 key->opt.prefer_mono = 1;
1895 }
1896 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1897 break;
1898 case PIPE_SHADER_FRAGMENT: {
1899 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1900 struct si_state_blend *blend = sctx->queued.named.blend;
1901
1902 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1903 sel->info.colors_written == 0x1)
1904 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1905
1906 if (blend) {
1907 /* Select the shader color format based on whether
1908 * blending or alpha are needed.
1909 */
1910 key->part.ps.epilog.spi_shader_col_format =
1911 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1912 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1913 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1914 sctx->framebuffer.spi_shader_col_format_blend) |
1915 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1916 sctx->framebuffer.spi_shader_col_format_alpha) |
1917 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1918 sctx->framebuffer.spi_shader_col_format);
1919 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1920
1921 /* The output for dual source blending should have
1922 * the same format as the first output.
1923 */
1924 if (blend->dual_src_blend)
1925 key->part.ps.epilog.spi_shader_col_format |=
1926 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1927 } else
1928 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1929
1930 /* If alpha-to-coverage is enabled, we have to export alpha
1931 * even if there is no color buffer.
1932 */
1933 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1934 blend && blend->alpha_to_coverage)
1935 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1936
1937 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1938 * to the range supported by the type if a channel has less
1939 * than 16 bits and the export format is 16_ABGR.
1940 */
1941 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1942 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1943 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1944 }
1945
1946 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1947 if (!key->part.ps.epilog.last_cbuf) {
1948 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1949 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1950 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1951 }
1952
1953 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1954 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1955
1956 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1957 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1958
1959 if (sctx->queued.named.blend) {
1960 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1961 rs->multisample_enable;
1962 }
1963
1964 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1965 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1966 (is_line && rs->line_smooth)) &&
1967 sctx->framebuffer.nr_samples <= 1;
1968 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1969
1970 if (sctx->ps_iter_samples > 1 &&
1971 sel->info.reads_samplemask) {
1972 key->part.ps.prolog.samplemask_log_ps_iter =
1973 util_logbase2(sctx->ps_iter_samples);
1974 }
1975
1976 if (rs->force_persample_interp &&
1977 rs->multisample_enable &&
1978 sctx->framebuffer.nr_samples > 1 &&
1979 sctx->ps_iter_samples > 1) {
1980 key->part.ps.prolog.force_persp_sample_interp =
1981 sel->info.uses_persp_center ||
1982 sel->info.uses_persp_centroid;
1983
1984 key->part.ps.prolog.force_linear_sample_interp =
1985 sel->info.uses_linear_center ||
1986 sel->info.uses_linear_centroid;
1987 } else if (rs->multisample_enable &&
1988 sctx->framebuffer.nr_samples > 1) {
1989 key->part.ps.prolog.bc_optimize_for_persp =
1990 sel->info.uses_persp_center &&
1991 sel->info.uses_persp_centroid;
1992 key->part.ps.prolog.bc_optimize_for_linear =
1993 sel->info.uses_linear_center &&
1994 sel->info.uses_linear_centroid;
1995 } else {
1996 /* Make sure SPI doesn't compute more than 1 pair
1997 * of (i,j), which is the optimization here. */
1998 key->part.ps.prolog.force_persp_center_interp =
1999 sel->info.uses_persp_center +
2000 sel->info.uses_persp_centroid +
2001 sel->info.uses_persp_sample > 1;
2002
2003 key->part.ps.prolog.force_linear_center_interp =
2004 sel->info.uses_linear_center +
2005 sel->info.uses_linear_centroid +
2006 sel->info.uses_linear_sample > 1;
2007
2008 if (sel->info.uses_persp_opcode_interp_sample ||
2009 sel->info.uses_linear_opcode_interp_sample)
2010 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2011 }
2012
2013 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2014
2015 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2016 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2017 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2018 struct pipe_resource *tex = cb0->texture;
2019
2020 /* 1D textures are allocated and used as 2D on GFX9. */
2021 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2022 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2023 (tex->target == PIPE_TEXTURE_1D ||
2024 tex->target == PIPE_TEXTURE_1D_ARRAY);
2025 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2026 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2027 tex->target == PIPE_TEXTURE_CUBE ||
2028 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2029 tex->target == PIPE_TEXTURE_3D;
2030 }
2031 break;
2032 }
2033 default:
2034 assert(0);
2035 }
2036
2037 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2038 memset(&key->opt, 0, sizeof(key->opt));
2039 }
2040
2041 static void si_build_shader_variant(struct si_shader *shader,
2042 int thread_index,
2043 bool low_priority)
2044 {
2045 struct si_shader_selector *sel = shader->selector;
2046 struct si_screen *sscreen = sel->screen;
2047 struct ac_llvm_compiler *compiler;
2048 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2049
2050 if (thread_index >= 0) {
2051 if (low_priority) {
2052 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2053 compiler = &sscreen->compiler_lowp[thread_index];
2054 } else {
2055 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2056 compiler = &sscreen->compiler[thread_index];
2057 }
2058 if (!debug->async)
2059 debug = NULL;
2060 } else {
2061 assert(!low_priority);
2062 compiler = shader->compiler_ctx_state.compiler;
2063 }
2064
2065 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
2066 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2067 sel->type);
2068 shader->compilation_failed = true;
2069 return;
2070 }
2071
2072 if (shader->compiler_ctx_state.is_debug_context) {
2073 FILE *f = open_memstream(&shader->shader_log,
2074 &shader->shader_log_size);
2075 if (f) {
2076 si_shader_dump(sscreen, shader, NULL, f, false);
2077 fclose(f);
2078 }
2079 }
2080
2081 si_shader_init_pm4_state(sscreen, shader);
2082 }
2083
2084 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2085 {
2086 struct si_shader *shader = (struct si_shader *)job;
2087
2088 assert(thread_index >= 0);
2089
2090 si_build_shader_variant(shader, thread_index, true);
2091 }
2092
2093 static const struct si_shader_key zeroed;
2094
2095 static bool si_check_missing_main_part(struct si_screen *sscreen,
2096 struct si_shader_selector *sel,
2097 struct si_compiler_ctx_state *compiler_state,
2098 struct si_shader_key *key)
2099 {
2100 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2101
2102 if (!*mainp) {
2103 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2104
2105 if (!main_part)
2106 return false;
2107
2108 /* We can leave the fence as permanently signaled because the
2109 * main part becomes visible globally only after it has been
2110 * compiled. */
2111 util_queue_fence_init(&main_part->ready);
2112
2113 main_part->selector = sel;
2114 main_part->key.as_es = key->as_es;
2115 main_part->key.as_ls = key->as_ls;
2116 main_part->key.as_ngg = key->as_ngg;
2117 main_part->is_monolithic = false;
2118
2119 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
2120 main_part, &compiler_state->debug) != 0) {
2121 FREE(main_part);
2122 return false;
2123 }
2124 *mainp = main_part;
2125 }
2126 return true;
2127 }
2128
2129 /**
2130 * Select a shader variant according to the shader key.
2131 *
2132 * \param optimized_or_none If the key describes an optimized shader variant and
2133 * the compilation isn't finished, don't select any
2134 * shader and return an error.
2135 */
2136 int si_shader_select_with_key(struct si_screen *sscreen,
2137 struct si_shader_ctx_state *state,
2138 struct si_compiler_ctx_state *compiler_state,
2139 struct si_shader_key *key,
2140 int thread_index,
2141 bool optimized_or_none)
2142 {
2143 struct si_shader_selector *sel = state->cso;
2144 struct si_shader_selector *previous_stage_sel = NULL;
2145 struct si_shader *current = state->current;
2146 struct si_shader *iter, *shader = NULL;
2147
2148 again:
2149 /* Check if we don't need to change anything.
2150 * This path is also used for most shaders that don't need multiple
2151 * variants, it will cost just a computation of the key and this
2152 * test. */
2153 if (likely(current &&
2154 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2155 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2156 if (current->is_optimized) {
2157 if (optimized_or_none)
2158 return -1;
2159
2160 memset(&key->opt, 0, sizeof(key->opt));
2161 goto current_not_ready;
2162 }
2163
2164 util_queue_fence_wait(&current->ready);
2165 }
2166
2167 return current->compilation_failed ? -1 : 0;
2168 }
2169 current_not_ready:
2170
2171 /* This must be done before the mutex is locked, because async GS
2172 * compilation calls this function too, and therefore must enter
2173 * the mutex first.
2174 *
2175 * Only wait if we are in a draw call. Don't wait if we are
2176 * in a compiler thread.
2177 */
2178 if (thread_index < 0)
2179 util_queue_fence_wait(&sel->ready);
2180
2181 mtx_lock(&sel->mutex);
2182
2183 /* Find the shader variant. */
2184 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2185 /* Don't check the "current" shader. We checked it above. */
2186 if (current != iter &&
2187 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2188 mtx_unlock(&sel->mutex);
2189
2190 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2191 /* If it's an optimized shader and its compilation has
2192 * been started but isn't done, use the unoptimized
2193 * shader so as not to cause a stall due to compilation.
2194 */
2195 if (iter->is_optimized) {
2196 if (optimized_or_none)
2197 return -1;
2198 memset(&key->opt, 0, sizeof(key->opt));
2199 goto again;
2200 }
2201
2202 util_queue_fence_wait(&iter->ready);
2203 }
2204
2205 if (iter->compilation_failed) {
2206 return -1; /* skip the draw call */
2207 }
2208
2209 state->current = iter;
2210 return 0;
2211 }
2212 }
2213
2214 /* Build a new shader. */
2215 shader = CALLOC_STRUCT(si_shader);
2216 if (!shader) {
2217 mtx_unlock(&sel->mutex);
2218 return -ENOMEM;
2219 }
2220
2221 util_queue_fence_init(&shader->ready);
2222
2223 shader->selector = sel;
2224 shader->key = *key;
2225 shader->compiler_ctx_state = *compiler_state;
2226
2227 /* If this is a merged shader, get the first shader's selector. */
2228 if (sscreen->info.chip_class >= GFX9) {
2229 if (sel->type == PIPE_SHADER_TESS_CTRL)
2230 previous_stage_sel = key->part.tcs.ls;
2231 else if (sel->type == PIPE_SHADER_GEOMETRY)
2232 previous_stage_sel = key->part.gs.es;
2233
2234 /* We need to wait for the previous shader. */
2235 if (previous_stage_sel && thread_index < 0)
2236 util_queue_fence_wait(&previous_stage_sel->ready);
2237 }
2238
2239 bool is_pure_monolithic =
2240 sscreen->use_monolithic_shaders ||
2241 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2242
2243 /* Compile the main shader part if it doesn't exist. This can happen
2244 * if the initial guess was wrong.
2245 *
2246 * The prim discard CS doesn't need the main shader part.
2247 */
2248 if (!is_pure_monolithic &&
2249 !key->opt.vs_as_prim_discard_cs) {
2250 bool ok = true;
2251
2252 /* Make sure the main shader part is present. This is needed
2253 * for shaders that can be compiled as VS, LS, or ES, and only
2254 * one of them is compiled at creation.
2255 *
2256 * It is also needed for GS, which can be compiled as non-NGG
2257 * and NGG.
2258 *
2259 * For merged shaders, check that the starting shader's main
2260 * part is present.
2261 */
2262 if (previous_stage_sel) {
2263 struct si_shader_key shader1_key = zeroed;
2264
2265 if (sel->type == PIPE_SHADER_TESS_CTRL)
2266 shader1_key.as_ls = 1;
2267 else if (sel->type == PIPE_SHADER_GEOMETRY)
2268 shader1_key.as_es = 1;
2269 else
2270 assert(0);
2271
2272 if (sel->type == PIPE_SHADER_GEOMETRY &&
2273 previous_stage_sel->type == PIPE_SHADER_TESS_EVAL)
2274 shader1_key.as_ngg = key->as_ngg;
2275
2276 mtx_lock(&previous_stage_sel->mutex);
2277 ok = si_check_missing_main_part(sscreen,
2278 previous_stage_sel,
2279 compiler_state, &shader1_key);
2280 mtx_unlock(&previous_stage_sel->mutex);
2281 }
2282
2283 if (ok) {
2284 ok = si_check_missing_main_part(sscreen, sel,
2285 compiler_state, key);
2286 }
2287
2288 if (!ok) {
2289 FREE(shader);
2290 mtx_unlock(&sel->mutex);
2291 return -ENOMEM; /* skip the draw call */
2292 }
2293 }
2294
2295 /* Keep the reference to the 1st shader of merged shaders, so that
2296 * Gallium can't destroy it before we destroy the 2nd shader.
2297 *
2298 * Set sctx = NULL, because it's unused if we're not releasing
2299 * the shader, and we don't have any sctx here.
2300 */
2301 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2302 previous_stage_sel);
2303
2304 /* Monolithic-only shaders don't make a distinction between optimized
2305 * and unoptimized. */
2306 shader->is_monolithic =
2307 is_pure_monolithic ||
2308 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2309
2310 /* The prim discard CS is always optimized. */
2311 shader->is_optimized =
2312 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2313 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2314
2315 /* If it's an optimized shader, compile it asynchronously. */
2316 if (shader->is_optimized && thread_index < 0) {
2317 /* Compile it asynchronously. */
2318 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2319 shader, &shader->ready,
2320 si_build_shader_variant_low_priority, NULL);
2321
2322 /* Add only after the ready fence was reset, to guard against a
2323 * race with si_bind_XX_shader. */
2324 if (!sel->last_variant) {
2325 sel->first_variant = shader;
2326 sel->last_variant = shader;
2327 } else {
2328 sel->last_variant->next_variant = shader;
2329 sel->last_variant = shader;
2330 }
2331
2332 /* Use the default (unoptimized) shader for now. */
2333 memset(&key->opt, 0, sizeof(key->opt));
2334 mtx_unlock(&sel->mutex);
2335
2336 if (sscreen->options.sync_compile)
2337 util_queue_fence_wait(&shader->ready);
2338
2339 if (optimized_or_none)
2340 return -1;
2341 goto again;
2342 }
2343
2344 /* Reset the fence before adding to the variant list. */
2345 util_queue_fence_reset(&shader->ready);
2346
2347 if (!sel->last_variant) {
2348 sel->first_variant = shader;
2349 sel->last_variant = shader;
2350 } else {
2351 sel->last_variant->next_variant = shader;
2352 sel->last_variant = shader;
2353 }
2354
2355 mtx_unlock(&sel->mutex);
2356
2357 assert(!shader->is_optimized);
2358 si_build_shader_variant(shader, thread_index, false);
2359
2360 util_queue_fence_signal(&shader->ready);
2361
2362 if (!shader->compilation_failed)
2363 state->current = shader;
2364
2365 return shader->compilation_failed ? -1 : 0;
2366 }
2367
2368 static int si_shader_select(struct pipe_context *ctx,
2369 struct si_shader_ctx_state *state,
2370 union si_vgt_stages_key stages_key,
2371 struct si_compiler_ctx_state *compiler_state)
2372 {
2373 struct si_context *sctx = (struct si_context *)ctx;
2374 struct si_shader_key key;
2375
2376 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2377 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2378 &key, -1, false);
2379 }
2380
2381 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2382 bool streamout,
2383 struct si_shader_key *key)
2384 {
2385 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2386
2387 switch (info->processor) {
2388 case PIPE_SHADER_VERTEX:
2389 switch (next_shader) {
2390 case PIPE_SHADER_GEOMETRY:
2391 key->as_es = 1;
2392 break;
2393 case PIPE_SHADER_TESS_CTRL:
2394 case PIPE_SHADER_TESS_EVAL:
2395 key->as_ls = 1;
2396 break;
2397 default:
2398 /* If POSITION isn't written, it can only be a HW VS
2399 * if streamout is used. If streamout isn't used,
2400 * assume that it's a HW LS. (the next shader is TCS)
2401 * This heuristic is needed for separate shader objects.
2402 */
2403 if (!info->writes_position && !streamout)
2404 key->as_ls = 1;
2405 }
2406 break;
2407
2408 case PIPE_SHADER_TESS_EVAL:
2409 if (next_shader == PIPE_SHADER_GEOMETRY ||
2410 !info->writes_position)
2411 key->as_es = 1;
2412 break;
2413 }
2414 }
2415
2416 /**
2417 * Compile the main shader part or the monolithic shader as part of
2418 * si_shader_selector initialization. Since it can be done asynchronously,
2419 * there is no way to report compile failures to applications.
2420 */
2421 static void si_init_shader_selector_async(void *job, int thread_index)
2422 {
2423 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2424 struct si_screen *sscreen = sel->screen;
2425 struct ac_llvm_compiler *compiler;
2426 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2427
2428 assert(!debug->debug_message || debug->async);
2429 assert(thread_index >= 0);
2430 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2431 compiler = &sscreen->compiler[thread_index];
2432
2433 if (sel->nir) {
2434 /* TODO: GS always sets wave size = default. Legacy GS will have
2435 * incorrect subgroup_size and ballot_bit_size. */
2436 si_lower_nir(sel, si_get_wave_size(sscreen, sel->type, true, false));
2437 }
2438
2439 /* Compile the main shader part for use with a prolog and/or epilog.
2440 * If this fails, the driver will try to compile a monolithic shader
2441 * on demand.
2442 */
2443 if (!sscreen->use_monolithic_shaders) {
2444 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2445 void *ir_binary = NULL;
2446
2447 if (!shader) {
2448 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2449 return;
2450 }
2451
2452 /* We can leave the fence signaled because use of the default
2453 * main part is guarded by the selector's ready fence. */
2454 util_queue_fence_init(&shader->ready);
2455
2456 shader->selector = sel;
2457 shader->is_monolithic = false;
2458 si_parse_next_shader_property(&sel->info,
2459 sel->so.num_outputs != 0,
2460 &shader->key);
2461 if (sscreen->info.chip_class >= GFX10 &&
2462 ((sel->type == PIPE_SHADER_VERTEX &&
2463 !shader->key.as_ls && !shader->key.as_es) ||
2464 sel->type == PIPE_SHADER_TESS_EVAL ||
2465 sel->type == PIPE_SHADER_GEOMETRY))
2466 shader->key.as_ngg = 1;
2467
2468 if (sel->tokens || sel->nir)
2469 ir_binary = si_get_ir_binary(sel);
2470
2471 /* Try to load the shader from the shader cache. */
2472 mtx_lock(&sscreen->shader_cache_mutex);
2473
2474 if (ir_binary &&
2475 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2476 mtx_unlock(&sscreen->shader_cache_mutex);
2477 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2478 } else {
2479 mtx_unlock(&sscreen->shader_cache_mutex);
2480
2481 /* Compile the shader if it hasn't been loaded from the cache. */
2482 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2483 debug) != 0) {
2484 FREE(shader);
2485 FREE(ir_binary);
2486 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2487 return;
2488 }
2489
2490 if (ir_binary) {
2491 mtx_lock(&sscreen->shader_cache_mutex);
2492 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2493 FREE(ir_binary);
2494 mtx_unlock(&sscreen->shader_cache_mutex);
2495 }
2496 }
2497
2498 *si_get_main_shader_part(sel, &shader->key) = shader;
2499
2500 /* Unset "outputs_written" flags for outputs converted to
2501 * DEFAULT_VAL, so that later inter-shader optimizations don't
2502 * try to eliminate outputs that don't exist in the final
2503 * shader.
2504 *
2505 * This is only done if non-monolithic shaders are enabled.
2506 */
2507 if ((sel->type == PIPE_SHADER_VERTEX ||
2508 sel->type == PIPE_SHADER_TESS_EVAL) &&
2509 !shader->key.as_ls &&
2510 !shader->key.as_es) {
2511 unsigned i;
2512
2513 for (i = 0; i < sel->info.num_outputs; i++) {
2514 unsigned offset = shader->info.vs_output_param_offset[i];
2515
2516 if (offset <= AC_EXP_PARAM_OFFSET_31)
2517 continue;
2518
2519 unsigned name = sel->info.output_semantic_name[i];
2520 unsigned index = sel->info.output_semantic_index[i];
2521 unsigned id;
2522
2523 switch (name) {
2524 case TGSI_SEMANTIC_GENERIC:
2525 /* don't process indices the function can't handle */
2526 if (index >= SI_MAX_IO_GENERIC)
2527 break;
2528 /* fall through */
2529 default:
2530 id = si_shader_io_get_unique_index(name, index, true);
2531 sel->outputs_written_before_ps &= ~(1ull << id);
2532 break;
2533 case TGSI_SEMANTIC_POSITION: /* ignore these */
2534 case TGSI_SEMANTIC_PSIZE:
2535 case TGSI_SEMANTIC_CLIPVERTEX:
2536 case TGSI_SEMANTIC_EDGEFLAG:
2537 break;
2538 }
2539 }
2540 }
2541 }
2542
2543 /* The GS copy shader is always pre-compiled. */
2544 if (sel->type == PIPE_SHADER_GEOMETRY &&
2545 (sscreen->info.chip_class <= GFX9 || sel->tess_turns_off_ngg)) {
2546 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2547 if (!sel->gs_copy_shader) {
2548 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2549 return;
2550 }
2551
2552 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2553 }
2554 }
2555
2556 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2557 struct util_queue_fence *ready_fence,
2558 struct si_compiler_ctx_state *compiler_ctx_state,
2559 void *job, util_queue_execute_func execute)
2560 {
2561 util_queue_fence_init(ready_fence);
2562
2563 struct util_async_debug_callback async_debug;
2564 bool debug =
2565 (sctx->debug.debug_message && !sctx->debug.async) ||
2566 sctx->is_debug ||
2567 si_can_dump_shader(sctx->screen, processor);
2568
2569 if (debug) {
2570 u_async_debug_init(&async_debug);
2571 compiler_ctx_state->debug = async_debug.base;
2572 }
2573
2574 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2575 ready_fence, execute, NULL);
2576
2577 if (debug) {
2578 util_queue_fence_wait(ready_fence);
2579 u_async_debug_drain(&async_debug, &sctx->debug);
2580 u_async_debug_cleanup(&async_debug);
2581 }
2582
2583 if (sctx->screen->options.sync_compile)
2584 util_queue_fence_wait(ready_fence);
2585 }
2586
2587 /* Return descriptor slot usage masks from the given shader info. */
2588 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2589 uint32_t *const_and_shader_buffers,
2590 uint64_t *samplers_and_images)
2591 {
2592 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2593
2594 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2595 num_constbufs = util_last_bit(info->const_buffers_declared);
2596 /* two 8-byte images share one 16-byte slot */
2597 num_images = align(util_last_bit(info->images_declared), 2);
2598 num_samplers = util_last_bit(info->samplers_declared);
2599
2600 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2601 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2602 *const_and_shader_buffers =
2603 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2604
2605 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2606 start = si_get_image_slot(num_images - 1) / 2;
2607 *samplers_and_images =
2608 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2609 }
2610
2611 static void *si_create_shader_selector(struct pipe_context *ctx,
2612 const struct pipe_shader_state *state)
2613 {
2614 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2615 struct si_context *sctx = (struct si_context*)ctx;
2616 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2617 int i;
2618
2619 if (!sel)
2620 return NULL;
2621
2622 pipe_reference_init(&sel->reference, 1);
2623 sel->screen = sscreen;
2624 sel->compiler_ctx_state.debug = sctx->debug;
2625 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2626
2627 sel->so = state->stream_output;
2628
2629 if (state->type == PIPE_SHADER_IR_TGSI) {
2630 sel->tokens = tgsi_dup_tokens(state->tokens);
2631 if (!sel->tokens) {
2632 FREE(sel);
2633 return NULL;
2634 }
2635
2636 tgsi_scan_shader(state->tokens, &sel->info);
2637 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2638 } else {
2639 assert(state->type == PIPE_SHADER_IR_NIR);
2640
2641 sel->nir = state->ir.nir;
2642
2643 si_nir_opts(sel->nir);
2644 si_nir_scan_shader(sel->nir, &sel->info);
2645 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2646 }
2647
2648 sel->type = sel->info.processor;
2649 p_atomic_inc(&sscreen->num_shaders_created);
2650 si_get_active_slot_masks(&sel->info,
2651 &sel->active_const_and_shader_buffers,
2652 &sel->active_samplers_and_images);
2653
2654 /* Record which streamout buffers are enabled. */
2655 for (i = 0; i < sel->so.num_outputs; i++) {
2656 sel->enabled_streamout_buffer_mask |=
2657 (1 << sel->so.output[i].output_buffer) <<
2658 (sel->so.output[i].stream * 4);
2659 }
2660
2661 /* The prolog is a no-op if there are no inputs. */
2662 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2663 sel->info.num_inputs &&
2664 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2665
2666 sel->force_correct_derivs_after_kill =
2667 sel->type == PIPE_SHADER_FRAGMENT &&
2668 sel->info.uses_derivatives &&
2669 sel->info.uses_kill &&
2670 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2671
2672 sel->prim_discard_cs_allowed =
2673 sel->type == PIPE_SHADER_VERTEX &&
2674 !sel->info.uses_bindless_images &&
2675 !sel->info.uses_bindless_samplers &&
2676 !sel->info.writes_memory &&
2677 !sel->info.writes_viewport_index &&
2678 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2679 !sel->so.num_outputs;
2680
2681 if (sel->type == PIPE_SHADER_VERTEX &&
2682 sel->info.writes_edgeflag) {
2683 if (sscreen->info.chip_class >= GFX10)
2684 sel->ngg_writes_edgeflag = true;
2685 else
2686 sel->pos_writes_edgeflag = true;
2687 }
2688
2689 /* Set which opcode uses which (i,j) pair. */
2690 if (sel->info.uses_persp_opcode_interp_centroid)
2691 sel->info.uses_persp_centroid = true;
2692
2693 if (sel->info.uses_linear_opcode_interp_centroid)
2694 sel->info.uses_linear_centroid = true;
2695
2696 if (sel->info.uses_persp_opcode_interp_offset ||
2697 sel->info.uses_persp_opcode_interp_sample)
2698 sel->info.uses_persp_center = true;
2699
2700 if (sel->info.uses_linear_opcode_interp_offset ||
2701 sel->info.uses_linear_opcode_interp_sample)
2702 sel->info.uses_linear_center = true;
2703
2704 switch (sel->type) {
2705 case PIPE_SHADER_GEOMETRY:
2706 sel->gs_output_prim =
2707 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2708
2709 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2710 sel->rast_prim = sel->gs_output_prim;
2711 if (util_rast_prim_is_triangles(sel->rast_prim))
2712 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2713
2714 sel->gs_max_out_vertices =
2715 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2716 sel->gs_num_invocations =
2717 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2718 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2719 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2720 sel->gs_max_out_vertices;
2721
2722 sel->max_gs_stream = 0;
2723 for (i = 0; i < sel->so.num_outputs; i++)
2724 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2725 sel->so.output[i].stream);
2726
2727 sel->gs_input_verts_per_prim =
2728 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2729
2730 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2731 sel->tess_turns_off_ngg =
2732 (sscreen->info.family == CHIP_NAVI10 ||
2733 sscreen->info.family == CHIP_NAVI12 ||
2734 sscreen->info.family == CHIP_NAVI14) &&
2735 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2736 break;
2737
2738 case PIPE_SHADER_TESS_CTRL:
2739 /* Always reserve space for these. */
2740 sel->patch_outputs_written |=
2741 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2742 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2743 /* fall through */
2744 case PIPE_SHADER_VERTEX:
2745 case PIPE_SHADER_TESS_EVAL:
2746 for (i = 0; i < sel->info.num_outputs; i++) {
2747 unsigned name = sel->info.output_semantic_name[i];
2748 unsigned index = sel->info.output_semantic_index[i];
2749
2750 switch (name) {
2751 case TGSI_SEMANTIC_TESSINNER:
2752 case TGSI_SEMANTIC_TESSOUTER:
2753 case TGSI_SEMANTIC_PATCH:
2754 sel->patch_outputs_written |=
2755 1ull << si_shader_io_get_unique_index_patch(name, index);
2756 break;
2757
2758 case TGSI_SEMANTIC_GENERIC:
2759 /* don't process indices the function can't handle */
2760 if (index >= SI_MAX_IO_GENERIC)
2761 break;
2762 /* fall through */
2763 default:
2764 sel->outputs_written |=
2765 1ull << si_shader_io_get_unique_index(name, index, false);
2766 sel->outputs_written_before_ps |=
2767 1ull << si_shader_io_get_unique_index(name, index, true);
2768 break;
2769 case TGSI_SEMANTIC_EDGEFLAG:
2770 break;
2771 }
2772 }
2773 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2774 sel->lshs_vertex_stride = sel->esgs_itemsize;
2775
2776 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2777 * will start on a different bank. (except for the maximum 32*16).
2778 */
2779 if (sel->lshs_vertex_stride < 32*16)
2780 sel->lshs_vertex_stride += 4;
2781
2782 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2783 * conflicts, i.e. each vertex will start at a different bank.
2784 */
2785 if (sctx->chip_class >= GFX9)
2786 sel->esgs_itemsize += 4;
2787
2788 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2789
2790 /* Only for TES: */
2791 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2792 sel->rast_prim = PIPE_PRIM_POINTS;
2793 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2794 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2795 else
2796 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2797 break;
2798
2799 case PIPE_SHADER_FRAGMENT:
2800 for (i = 0; i < sel->info.num_inputs; i++) {
2801 unsigned name = sel->info.input_semantic_name[i];
2802 unsigned index = sel->info.input_semantic_index[i];
2803
2804 switch (name) {
2805 case TGSI_SEMANTIC_GENERIC:
2806 /* don't process indices the function can't handle */
2807 if (index >= SI_MAX_IO_GENERIC)
2808 break;
2809 /* fall through */
2810 default:
2811 sel->inputs_read |=
2812 1ull << si_shader_io_get_unique_index(name, index, true);
2813 break;
2814 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2815 break;
2816 }
2817 }
2818
2819 for (i = 0; i < 8; i++)
2820 if (sel->info.colors_written & (1 << i))
2821 sel->colors_written_4bit |= 0xf << (4 * i);
2822
2823 for (i = 0; i < sel->info.num_inputs; i++) {
2824 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2825 int index = sel->info.input_semantic_index[i];
2826 sel->color_attr_index[index] = i;
2827 }
2828 }
2829 break;
2830 default:;
2831 }
2832
2833 /* PA_CL_VS_OUT_CNTL */
2834 bool misc_vec_ena =
2835 sel->info.writes_psize || sel->pos_writes_edgeflag ||
2836 sel->info.writes_layer || sel->info.writes_viewport_index;
2837 sel->pa_cl_vs_out_cntl =
2838 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2839 S_02881C_USE_VTX_EDGE_FLAG(sel->pos_writes_edgeflag) |
2840 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2841 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2842 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2843 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2844 sel->clipdist_mask = sel->info.writes_clipvertex ?
2845 SIX_BITS : sel->info.clipdist_writemask;
2846 sel->culldist_mask = sel->info.culldist_writemask <<
2847 sel->info.num_written_clipdistance;
2848
2849 /* DB_SHADER_CONTROL */
2850 sel->db_shader_control =
2851 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2852 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2853 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2854 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2855
2856 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2857 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2858 sel->db_shader_control |=
2859 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2860 break;
2861 case TGSI_FS_DEPTH_LAYOUT_LESS:
2862 sel->db_shader_control |=
2863 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2864 break;
2865 }
2866
2867 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2868 *
2869 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2870 * --|-----------|------------|------------|--------------------|-------------------|-------------
2871 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2872 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2873 * 2 | false | true | n/a | LateZ | 1 | 0
2874 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2875 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2876 *
2877 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2878 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2879 *
2880 * Don't use ReZ without profiling !!!
2881 *
2882 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2883 * shaders.
2884 */
2885 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2886 /* Cases 3, 4. */
2887 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2888 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2889 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2890 } else if (sel->info.writes_memory) {
2891 /* Case 2. */
2892 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2893 S_02880C_EXEC_ON_HIER_FAIL(1);
2894 } else {
2895 /* Case 1. */
2896 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2897 }
2898
2899 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
2900 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2901
2902 (void) mtx_init(&sel->mutex, mtx_plain);
2903
2904 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2905 &sel->compiler_ctx_state, sel,
2906 si_init_shader_selector_async);
2907 return sel;
2908 }
2909
2910 static void si_update_streamout_state(struct si_context *sctx)
2911 {
2912 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2913
2914 if (!shader_with_so)
2915 return;
2916
2917 sctx->streamout.enabled_stream_buffers_mask =
2918 shader_with_so->enabled_streamout_buffer_mask;
2919 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2920 }
2921
2922 static void si_update_clip_regs(struct si_context *sctx,
2923 struct si_shader_selector *old_hw_vs,
2924 struct si_shader *old_hw_vs_variant,
2925 struct si_shader_selector *next_hw_vs,
2926 struct si_shader *next_hw_vs_variant)
2927 {
2928 if (next_hw_vs &&
2929 (!old_hw_vs ||
2930 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2931 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2932 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2933 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2934 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2935 !old_hw_vs_variant ||
2936 !next_hw_vs_variant ||
2937 old_hw_vs_variant->key.opt.clip_disable !=
2938 next_hw_vs_variant->key.opt.clip_disable))
2939 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2940 }
2941
2942 static void si_update_common_shader_state(struct si_context *sctx)
2943 {
2944 sctx->uses_bindless_samplers =
2945 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2946 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2947 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2948 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2949 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2950 sctx->uses_bindless_images =
2951 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2952 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2953 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2954 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2955 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2956 sctx->do_update_shaders = true;
2957 }
2958
2959 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2960 {
2961 struct si_context *sctx = (struct si_context *)ctx;
2962 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2963 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2964 struct si_shader_selector *sel = state;
2965
2966 if (sctx->vs_shader.cso == sel)
2967 return;
2968
2969 sctx->vs_shader.cso = sel;
2970 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2971 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2972
2973 si_update_common_shader_state(sctx);
2974 si_update_vs_viewport_state(sctx);
2975 si_set_active_descriptors_for_shader(sctx, sel);
2976 si_update_streamout_state(sctx);
2977 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2978 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2979 }
2980
2981 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2982 {
2983 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2984 (sctx->tes_shader.cso &&
2985 sctx->tes_shader.cso->info.uses_primid) ||
2986 (sctx->tcs_shader.cso &&
2987 sctx->tcs_shader.cso->info.uses_primid) ||
2988 (sctx->gs_shader.cso &&
2989 sctx->gs_shader.cso->info.uses_primid) ||
2990 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2991 sctx->ps_shader.cso->info.uses_primid);
2992 }
2993
2994 static bool si_update_ngg(struct si_context *sctx)
2995 {
2996 if (sctx->chip_class <= GFX9)
2997 return false;
2998
2999 bool new_ngg = true;
3000
3001 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
3002 sctx->gs_shader.cso->tess_turns_off_ngg)
3003 new_ngg = false;
3004
3005 if (new_ngg != sctx->ngg) {
3006 sctx->ngg = new_ngg;
3007 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3008 return true;
3009 }
3010 return false;
3011 }
3012
3013 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3014 {
3015 struct si_context *sctx = (struct si_context *)ctx;
3016 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3017 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3018 struct si_shader_selector *sel = state;
3019 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3020 bool ngg_changed;
3021
3022 if (sctx->gs_shader.cso == sel)
3023 return;
3024
3025 sctx->gs_shader.cso = sel;
3026 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3027 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3028
3029 si_update_common_shader_state(sctx);
3030 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3031
3032 ngg_changed = si_update_ngg(sctx);
3033 if (ngg_changed || enable_changed)
3034 si_shader_change_notify(sctx);
3035 if (enable_changed) {
3036 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3037 si_update_tess_uses_prim_id(sctx);
3038 }
3039 si_update_vs_viewport_state(sctx);
3040 si_set_active_descriptors_for_shader(sctx, sel);
3041 si_update_streamout_state(sctx);
3042 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3043 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3044 }
3045
3046 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3047 {
3048 struct si_context *sctx = (struct si_context *)ctx;
3049 struct si_shader_selector *sel = state;
3050 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3051
3052 if (sctx->tcs_shader.cso == sel)
3053 return;
3054
3055 sctx->tcs_shader.cso = sel;
3056 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3057 si_update_tess_uses_prim_id(sctx);
3058
3059 si_update_common_shader_state(sctx);
3060
3061 if (enable_changed)
3062 sctx->last_tcs = NULL; /* invalidate derived tess state */
3063
3064 si_set_active_descriptors_for_shader(sctx, sel);
3065 }
3066
3067 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3068 {
3069 struct si_context *sctx = (struct si_context *)ctx;
3070 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3071 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3072 struct si_shader_selector *sel = state;
3073 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3074
3075 if (sctx->tes_shader.cso == sel)
3076 return;
3077
3078 sctx->tes_shader.cso = sel;
3079 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3080 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3081 si_update_tess_uses_prim_id(sctx);
3082
3083 si_update_common_shader_state(sctx);
3084 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3085
3086 if (enable_changed) {
3087 si_update_ngg(sctx);
3088 si_shader_change_notify(sctx);
3089 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3090 }
3091 si_update_vs_viewport_state(sctx);
3092 si_set_active_descriptors_for_shader(sctx, sel);
3093 si_update_streamout_state(sctx);
3094 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3095 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3096 }
3097
3098 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3099 {
3100 struct si_context *sctx = (struct si_context *)ctx;
3101 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3102 struct si_shader_selector *sel = state;
3103
3104 /* skip if supplied shader is one already in use */
3105 if (old_sel == sel)
3106 return;
3107
3108 sctx->ps_shader.cso = sel;
3109 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3110
3111 si_update_common_shader_state(sctx);
3112 if (sel) {
3113 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3114 si_update_tess_uses_prim_id(sctx);
3115
3116 if (!old_sel ||
3117 old_sel->info.colors_written != sel->info.colors_written)
3118 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3119
3120 if (sctx->screen->has_out_of_order_rast &&
3121 (!old_sel ||
3122 old_sel->info.writes_memory != sel->info.writes_memory ||
3123 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3124 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3125 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3126 }
3127 si_set_active_descriptors_for_shader(sctx, sel);
3128 si_update_ps_colorbuf0_slot(sctx);
3129 }
3130
3131 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3132 {
3133 if (shader->is_optimized) {
3134 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3135 &shader->ready);
3136 }
3137
3138 util_queue_fence_destroy(&shader->ready);
3139
3140 if (shader->pm4) {
3141 /* If destroyed shaders were not unbound, the next compiled
3142 * shader variant could get the same pointer address and so
3143 * binding it to the same shader stage would be considered
3144 * a no-op, causing random behavior.
3145 */
3146 switch (shader->selector->type) {
3147 case PIPE_SHADER_VERTEX:
3148 if (shader->key.as_ls) {
3149 assert(sctx->chip_class <= GFX8);
3150 si_pm4_delete_state(sctx, ls, shader->pm4);
3151 } else if (shader->key.as_es) {
3152 assert(sctx->chip_class <= GFX8);
3153 si_pm4_delete_state(sctx, es, shader->pm4);
3154 } else if (shader->key.as_ngg) {
3155 si_pm4_delete_state(sctx, gs, shader->pm4);
3156 } else {
3157 si_pm4_delete_state(sctx, vs, shader->pm4);
3158 }
3159 break;
3160 case PIPE_SHADER_TESS_CTRL:
3161 si_pm4_delete_state(sctx, hs, shader->pm4);
3162 break;
3163 case PIPE_SHADER_TESS_EVAL:
3164 if (shader->key.as_es) {
3165 assert(sctx->chip_class <= GFX8);
3166 si_pm4_delete_state(sctx, es, shader->pm4);
3167 } else if (shader->key.as_ngg) {
3168 si_pm4_delete_state(sctx, gs, shader->pm4);
3169 } else {
3170 si_pm4_delete_state(sctx, vs, shader->pm4);
3171 }
3172 break;
3173 case PIPE_SHADER_GEOMETRY:
3174 if (shader->is_gs_copy_shader)
3175 si_pm4_delete_state(sctx, vs, shader->pm4);
3176 else
3177 si_pm4_delete_state(sctx, gs, shader->pm4);
3178 break;
3179 case PIPE_SHADER_FRAGMENT:
3180 si_pm4_delete_state(sctx, ps, shader->pm4);
3181 break;
3182 default:;
3183 }
3184 }
3185
3186 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3187 si_shader_destroy(shader);
3188 free(shader);
3189 }
3190
3191 void si_destroy_shader_selector(struct si_context *sctx,
3192 struct si_shader_selector *sel)
3193 {
3194 struct si_shader *p = sel->first_variant, *c;
3195 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3196 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3197 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3198 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3199 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3200 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3201 };
3202
3203 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3204
3205 if (current_shader[sel->type]->cso == sel) {
3206 current_shader[sel->type]->cso = NULL;
3207 current_shader[sel->type]->current = NULL;
3208 }
3209
3210 while (p) {
3211 c = p->next_variant;
3212 si_delete_shader(sctx, p);
3213 p = c;
3214 }
3215
3216 if (sel->main_shader_part)
3217 si_delete_shader(sctx, sel->main_shader_part);
3218 if (sel->main_shader_part_ls)
3219 si_delete_shader(sctx, sel->main_shader_part_ls);
3220 if (sel->main_shader_part_es)
3221 si_delete_shader(sctx, sel->main_shader_part_es);
3222 if (sel->main_shader_part_ngg)
3223 si_delete_shader(sctx, sel->main_shader_part_ngg);
3224 if (sel->gs_copy_shader)
3225 si_delete_shader(sctx, sel->gs_copy_shader);
3226
3227 util_queue_fence_destroy(&sel->ready);
3228 mtx_destroy(&sel->mutex);
3229 free(sel->tokens);
3230 ralloc_free(sel->nir);
3231 free(sel);
3232 }
3233
3234 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3235 {
3236 struct si_context *sctx = (struct si_context *)ctx;
3237 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3238
3239 si_shader_selector_reference(sctx, &sel, NULL);
3240 }
3241
3242 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3243 struct si_shader *vs, unsigned name,
3244 unsigned index, unsigned interpolate)
3245 {
3246 struct tgsi_shader_info *vsinfo = &vs->selector->info;
3247 unsigned j, offset, ps_input_cntl = 0;
3248
3249 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3250 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3251 name == TGSI_SEMANTIC_PRIMID)
3252 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3253
3254 if (name == TGSI_SEMANTIC_PCOORD ||
3255 (name == TGSI_SEMANTIC_TEXCOORD &&
3256 sctx->sprite_coord_enable & (1 << index))) {
3257 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3258 }
3259
3260 for (j = 0; j < vsinfo->num_outputs; j++) {
3261 if (name == vsinfo->output_semantic_name[j] &&
3262 index == vsinfo->output_semantic_index[j]) {
3263 offset = vs->info.vs_output_param_offset[j];
3264
3265 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3266 /* The input is loaded from parameter memory. */
3267 ps_input_cntl |= S_028644_OFFSET(offset);
3268 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3269 if (offset == AC_EXP_PARAM_UNDEFINED) {
3270 /* This can happen with depth-only rendering. */
3271 offset = 0;
3272 } else {
3273 /* The input is a DEFAULT_VAL constant. */
3274 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3275 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3276 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3277 }
3278
3279 ps_input_cntl = S_028644_OFFSET(0x20) |
3280 S_028644_DEFAULT_VAL(offset);
3281 }
3282 break;
3283 }
3284 }
3285
3286 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3287 /* PrimID is written after the last output when HW VS is used. */
3288 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3289 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3290 /* No corresponding output found, load defaults into input.
3291 * Don't set any other bits.
3292 * (FLAT_SHADE=1 completely changes behavior) */
3293 ps_input_cntl = S_028644_OFFSET(0x20);
3294 /* D3D 9 behaviour. GL is undefined */
3295 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3296 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3297 }
3298 return ps_input_cntl;
3299 }
3300
3301 static void si_emit_spi_map(struct si_context *sctx)
3302 {
3303 struct si_shader *ps = sctx->ps_shader.current;
3304 struct si_shader *vs = si_get_vs_state(sctx);
3305 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3306 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3307 unsigned spi_ps_input_cntl[32];
3308
3309 if (!ps || !ps->selector->info.num_inputs)
3310 return;
3311
3312 num_interp = si_get_ps_num_interp(ps);
3313 assert(num_interp > 0);
3314
3315 for (i = 0; i < psinfo->num_inputs; i++) {
3316 unsigned name = psinfo->input_semantic_name[i];
3317 unsigned index = psinfo->input_semantic_index[i];
3318 unsigned interpolate = psinfo->input_interpolate[i];
3319
3320 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3321 index, interpolate);
3322
3323 if (name == TGSI_SEMANTIC_COLOR) {
3324 assert(index < ARRAY_SIZE(bcol_interp));
3325 bcol_interp[index] = interpolate;
3326 }
3327 }
3328
3329 if (ps->key.part.ps.prolog.color_two_side) {
3330 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3331
3332 for (i = 0; i < 2; i++) {
3333 if (!(psinfo->colors_read & (0xf << (i * 4))))
3334 continue;
3335
3336 spi_ps_input_cntl[num_written++] =
3337 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3338
3339 }
3340 }
3341 assert(num_interp == num_written);
3342
3343 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3344 /* Dota 2: Only ~16% of SPI map updates set different values. */
3345 /* Talos: Only ~9% of SPI map updates set different values. */
3346 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3347 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3348 spi_ps_input_cntl,
3349 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3350
3351 if (initial_cdw != sctx->gfx_cs->current.cdw)
3352 sctx->context_roll = true;
3353 }
3354
3355 /**
3356 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3357 */
3358 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3359 {
3360 if (sctx->init_config_has_vgt_flush)
3361 return;
3362
3363 /* Done by Vulkan before VGT_FLUSH. */
3364 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3365 si_pm4_cmd_add(sctx->init_config,
3366 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3367 si_pm4_cmd_end(sctx->init_config, false);
3368
3369 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3370 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3371 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3372 si_pm4_cmd_end(sctx->init_config, false);
3373 sctx->init_config_has_vgt_flush = true;
3374 }
3375
3376 /* Initialize state related to ESGS / GSVS ring buffers */
3377 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3378 {
3379 struct si_shader_selector *es =
3380 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3381 struct si_shader_selector *gs = sctx->gs_shader.cso;
3382 struct si_pm4_state *pm4;
3383
3384 /* Chip constants. */
3385 unsigned num_se = sctx->screen->info.max_se;
3386 unsigned wave_size = 64;
3387 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3388 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3389 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3390 */
3391 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3392 unsigned alignment = 256 * num_se;
3393 /* The maximum size is 63.999 MB per SE. */
3394 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3395
3396 /* Calculate the minimum size. */
3397 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3398 wave_size, alignment);
3399
3400 /* These are recommended sizes, not minimum sizes. */
3401 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3402 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3403 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3404 gs->max_gsvs_emit_size;
3405
3406 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3407 esgs_ring_size = align(esgs_ring_size, alignment);
3408 gsvs_ring_size = align(gsvs_ring_size, alignment);
3409
3410 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3411 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3412
3413 /* Some rings don't have to be allocated if shaders don't use them.
3414 * (e.g. no varyings between ES and GS or GS and VS)
3415 *
3416 * GFX9 doesn't have the ESGS ring.
3417 */
3418 bool update_esgs = sctx->chip_class <= GFX8 &&
3419 esgs_ring_size &&
3420 (!sctx->esgs_ring ||
3421 sctx->esgs_ring->width0 < esgs_ring_size);
3422 bool update_gsvs = gsvs_ring_size &&
3423 (!sctx->gsvs_ring ||
3424 sctx->gsvs_ring->width0 < gsvs_ring_size);
3425
3426 if (!update_esgs && !update_gsvs)
3427 return true;
3428
3429 if (update_esgs) {
3430 pipe_resource_reference(&sctx->esgs_ring, NULL);
3431 sctx->esgs_ring =
3432 pipe_aligned_buffer_create(sctx->b.screen,
3433 SI_RESOURCE_FLAG_UNMAPPABLE,
3434 PIPE_USAGE_DEFAULT,
3435 esgs_ring_size, alignment);
3436 if (!sctx->esgs_ring)
3437 return false;
3438 }
3439
3440 if (update_gsvs) {
3441 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3442 sctx->gsvs_ring =
3443 pipe_aligned_buffer_create(sctx->b.screen,
3444 SI_RESOURCE_FLAG_UNMAPPABLE,
3445 PIPE_USAGE_DEFAULT,
3446 gsvs_ring_size, alignment);
3447 if (!sctx->gsvs_ring)
3448 return false;
3449 }
3450
3451 /* Create the "init_config_gs_rings" state. */
3452 pm4 = CALLOC_STRUCT(si_pm4_state);
3453 if (!pm4)
3454 return false;
3455
3456 if (sctx->chip_class >= GFX7) {
3457 if (sctx->esgs_ring) {
3458 assert(sctx->chip_class <= GFX8);
3459 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3460 sctx->esgs_ring->width0 / 256);
3461 }
3462 if (sctx->gsvs_ring)
3463 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3464 sctx->gsvs_ring->width0 / 256);
3465 } else {
3466 if (sctx->esgs_ring)
3467 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3468 sctx->esgs_ring->width0 / 256);
3469 if (sctx->gsvs_ring)
3470 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3471 sctx->gsvs_ring->width0 / 256);
3472 }
3473
3474 /* Set the state. */
3475 if (sctx->init_config_gs_rings)
3476 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3477 sctx->init_config_gs_rings = pm4;
3478
3479 if (!sctx->init_config_has_vgt_flush) {
3480 si_init_config_add_vgt_flush(sctx);
3481 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3482 }
3483
3484 /* Flush the context to re-emit both init_config states. */
3485 sctx->initial_gfx_cs_size = 0; /* force flush */
3486 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3487
3488 /* Set ring bindings. */
3489 if (sctx->esgs_ring) {
3490 assert(sctx->chip_class <= GFX8);
3491 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3492 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3493 true, true, 4, 64, 0);
3494 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3495 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3496 false, false, 0, 0, 0);
3497 }
3498 if (sctx->gsvs_ring) {
3499 si_set_ring_buffer(sctx, SI_RING_GSVS,
3500 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3501 false, false, 0, 0, 0);
3502 }
3503
3504 return true;
3505 }
3506
3507 static void si_shader_lock(struct si_shader *shader)
3508 {
3509 mtx_lock(&shader->selector->mutex);
3510 if (shader->previous_stage_sel) {
3511 assert(shader->previous_stage_sel != shader->selector);
3512 mtx_lock(&shader->previous_stage_sel->mutex);
3513 }
3514 }
3515
3516 static void si_shader_unlock(struct si_shader *shader)
3517 {
3518 if (shader->previous_stage_sel)
3519 mtx_unlock(&shader->previous_stage_sel->mutex);
3520 mtx_unlock(&shader->selector->mutex);
3521 }
3522
3523 /**
3524 * @returns 1 if \p sel has been updated to use a new scratch buffer
3525 * 0 if not
3526 * < 0 if there was a failure
3527 */
3528 static int si_update_scratch_buffer(struct si_context *sctx,
3529 struct si_shader *shader)
3530 {
3531 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3532
3533 if (!shader)
3534 return 0;
3535
3536 /* This shader doesn't need a scratch buffer */
3537 if (shader->config.scratch_bytes_per_wave == 0)
3538 return 0;
3539
3540 /* Prevent race conditions when updating:
3541 * - si_shader::scratch_bo
3542 * - si_shader::binary::code
3543 * - si_shader::previous_stage::binary::code.
3544 */
3545 si_shader_lock(shader);
3546
3547 /* This shader is already configured to use the current
3548 * scratch buffer. */
3549 if (shader->scratch_bo == sctx->scratch_buffer) {
3550 si_shader_unlock(shader);
3551 return 0;
3552 }
3553
3554 assert(sctx->scratch_buffer);
3555
3556 /* Replace the shader bo with a new bo that has the relocs applied. */
3557 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3558 si_shader_unlock(shader);
3559 return -1;
3560 }
3561
3562 /* Update the shader state to use the new shader bo. */
3563 si_shader_init_pm4_state(sctx->screen, shader);
3564
3565 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3566
3567 si_shader_unlock(shader);
3568 return 1;
3569 }
3570
3571 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3572 {
3573 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3574 }
3575
3576 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3577 {
3578 return shader ? shader->config.scratch_bytes_per_wave : 0;
3579 }
3580
3581 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3582 {
3583 if (!sctx->tes_shader.cso)
3584 return NULL; /* tessellation disabled */
3585
3586 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3587 sctx->fixed_func_tcs_shader.current;
3588 }
3589
3590 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3591 {
3592 unsigned bytes = 0;
3593
3594 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3595 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3596 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3597 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3598
3599 if (sctx->tes_shader.cso) {
3600 struct si_shader *tcs = si_get_tcs_current(sctx);
3601
3602 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3603 }
3604 return bytes;
3605 }
3606
3607 static bool si_update_scratch_relocs(struct si_context *sctx)
3608 {
3609 struct si_shader *tcs = si_get_tcs_current(sctx);
3610 int r;
3611
3612 /* Update the shaders, so that they are using the latest scratch.
3613 * The scratch buffer may have been changed since these shaders were
3614 * last used, so we still need to try to update them, even if they
3615 * require scratch buffers smaller than the current size.
3616 */
3617 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3618 if (r < 0)
3619 return false;
3620 if (r == 1)
3621 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3622
3623 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3624 if (r < 0)
3625 return false;
3626 if (r == 1)
3627 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3628
3629 r = si_update_scratch_buffer(sctx, tcs);
3630 if (r < 0)
3631 return false;
3632 if (r == 1)
3633 si_pm4_bind_state(sctx, hs, tcs->pm4);
3634
3635 /* VS can be bound as LS, ES, or VS. */
3636 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3637 if (r < 0)
3638 return false;
3639 if (r == 1) {
3640 if (sctx->vs_shader.current->key.as_ls)
3641 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3642 else if (sctx->vs_shader.current->key.as_es)
3643 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3644 else if (sctx->vs_shader.current->key.as_ngg)
3645 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3646 else
3647 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3648 }
3649
3650 /* TES can be bound as ES or VS. */
3651 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3652 if (r < 0)
3653 return false;
3654 if (r == 1) {
3655 if (sctx->tes_shader.current->key.as_es)
3656 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3657 else if (sctx->tes_shader.current->key.as_ngg)
3658 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3659 else
3660 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3661 }
3662
3663 return true;
3664 }
3665
3666 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3667 {
3668 unsigned current_scratch_buffer_size =
3669 si_get_current_scratch_buffer_size(sctx);
3670 unsigned scratch_bytes_per_wave =
3671 si_get_max_scratch_bytes_per_wave(sctx);
3672 unsigned scratch_needed_size = scratch_bytes_per_wave *
3673 sctx->scratch_waves;
3674 unsigned spi_tmpring_size;
3675
3676 if (scratch_needed_size > 0) {
3677 if (scratch_needed_size > current_scratch_buffer_size) {
3678 /* Create a bigger scratch buffer */
3679 si_resource_reference(&sctx->scratch_buffer, NULL);
3680
3681 sctx->scratch_buffer =
3682 si_aligned_buffer_create(&sctx->screen->b,
3683 SI_RESOURCE_FLAG_UNMAPPABLE,
3684 PIPE_USAGE_DEFAULT,
3685 scratch_needed_size, 256);
3686 if (!sctx->scratch_buffer)
3687 return false;
3688
3689 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3690 si_context_add_resource_size(sctx,
3691 &sctx->scratch_buffer->b.b);
3692 }
3693
3694 if (!si_update_scratch_relocs(sctx))
3695 return false;
3696 }
3697
3698 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3699 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3700 "scratch size should already be aligned correctly.");
3701
3702 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3703 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3704 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3705 sctx->spi_tmpring_size = spi_tmpring_size;
3706 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3707 }
3708 return true;
3709 }
3710
3711 static void si_init_tess_factor_ring(struct si_context *sctx)
3712 {
3713 assert(!sctx->tess_rings);
3714
3715 /* The address must be aligned to 2^19, because the shader only
3716 * receives the high 13 bits.
3717 */
3718 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3719 SI_RESOURCE_FLAG_32BIT,
3720 PIPE_USAGE_DEFAULT,
3721 sctx->screen->tess_offchip_ring_size +
3722 sctx->screen->tess_factor_ring_size,
3723 1 << 19);
3724 if (!sctx->tess_rings)
3725 return;
3726
3727 si_init_config_add_vgt_flush(sctx);
3728
3729 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3730 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3731
3732 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3733 sctx->screen->tess_offchip_ring_size;
3734
3735 /* Append these registers to the init config state. */
3736 if (sctx->chip_class >= GFX7) {
3737 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3738 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3739 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3740 factor_va >> 8);
3741 if (sctx->chip_class >= GFX10)
3742 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3743 S_030984_BASE_HI(factor_va >> 40));
3744 else if (sctx->chip_class == GFX9)
3745 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3746 S_030944_BASE_HI(factor_va >> 40));
3747 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3748 sctx->screen->vgt_hs_offchip_param);
3749 } else {
3750 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3751 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3752 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3753 factor_va >> 8);
3754 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3755 sctx->screen->vgt_hs_offchip_param);
3756 }
3757
3758 /* Flush the context to re-emit the init_config state.
3759 * This is done only once in a lifetime of a context.
3760 */
3761 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3762 sctx->initial_gfx_cs_size = 0; /* force flush */
3763 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3764 }
3765
3766 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3767 union si_vgt_stages_key key)
3768 {
3769 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3770 uint32_t stages = 0;
3771
3772 if (key.u.tess) {
3773 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3774 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3775
3776 if (key.u.gs)
3777 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3778 S_028B54_GS_EN(1);
3779 else if (key.u.ngg)
3780 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3781 else
3782 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3783 } else if (key.u.gs) {
3784 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3785 S_028B54_GS_EN(1);
3786 } else if (key.u.ngg) {
3787 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3788 }
3789
3790 if (key.u.ngg) {
3791 stages |= S_028B54_PRIMGEN_EN(1);
3792 if (key.u.streamout)
3793 stages |= S_028B54_NGG_WAVE_ID_EN(1);
3794 } else if (key.u.gs)
3795 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3796
3797 if (screen->info.chip_class >= GFX9)
3798 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3799
3800 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
3801 stages |= S_028B54_HS_W32_EN(1) |
3802 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3803 S_028B54_VS_W32_EN(1);
3804 }
3805
3806 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3807 return pm4;
3808 }
3809
3810 static void si_update_vgt_shader_config(struct si_context *sctx,
3811 union si_vgt_stages_key key)
3812 {
3813 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3814
3815 if (unlikely(!*pm4))
3816 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3817 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3818 }
3819
3820 bool si_update_shaders(struct si_context *sctx)
3821 {
3822 struct pipe_context *ctx = (struct pipe_context*)sctx;
3823 struct si_compiler_ctx_state compiler_state;
3824 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3825 struct si_shader *old_vs = si_get_vs_state(sctx);
3826 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3827 struct si_shader *old_ps = sctx->ps_shader.current;
3828 union si_vgt_stages_key key;
3829 unsigned old_spi_shader_col_format =
3830 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3831 int r;
3832
3833 compiler_state.compiler = &sctx->compiler;
3834 compiler_state.debug = sctx->debug;
3835 compiler_state.is_debug_context = sctx->is_debug;
3836
3837 key.index = 0;
3838
3839 if (sctx->tes_shader.cso)
3840 key.u.tess = 1;
3841 if (sctx->gs_shader.cso)
3842 key.u.gs = 1;
3843
3844 if (sctx->chip_class >= GFX10) {
3845 key.u.ngg = sctx->ngg;
3846
3847 if (sctx->gs_shader.cso)
3848 key.u.streamout = !!sctx->gs_shader.cso->so.num_outputs;
3849 else if (sctx->tes_shader.cso)
3850 key.u.streamout = !!sctx->tes_shader.cso->so.num_outputs;
3851 else
3852 key.u.streamout = !!sctx->vs_shader.cso->so.num_outputs;
3853 }
3854
3855 /* Update TCS and TES. */
3856 if (sctx->tes_shader.cso) {
3857 if (!sctx->tess_rings) {
3858 si_init_tess_factor_ring(sctx);
3859 if (!sctx->tess_rings)
3860 return false;
3861 }
3862
3863 if (sctx->tcs_shader.cso) {
3864 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3865 &compiler_state);
3866 if (r)
3867 return false;
3868 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3869 } else {
3870 if (!sctx->fixed_func_tcs_shader.cso) {
3871 sctx->fixed_func_tcs_shader.cso =
3872 si_create_fixed_func_tcs(sctx);
3873 if (!sctx->fixed_func_tcs_shader.cso)
3874 return false;
3875 }
3876
3877 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3878 key, &compiler_state);
3879 if (r)
3880 return false;
3881 si_pm4_bind_state(sctx, hs,
3882 sctx->fixed_func_tcs_shader.current->pm4);
3883 }
3884
3885 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3886 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3887 if (r)
3888 return false;
3889
3890 if (sctx->gs_shader.cso) {
3891 /* TES as ES */
3892 assert(sctx->chip_class <= GFX8);
3893 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3894 } else if (key.u.ngg) {
3895 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3896 } else {
3897 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3898 }
3899 }
3900 } else {
3901 if (sctx->chip_class <= GFX8)
3902 si_pm4_bind_state(sctx, ls, NULL);
3903 si_pm4_bind_state(sctx, hs, NULL);
3904 }
3905
3906 /* Update GS. */
3907 if (sctx->gs_shader.cso) {
3908 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3909 if (r)
3910 return false;
3911 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3912 if (!key.u.ngg) {
3913 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3914
3915 if (!si_update_gs_ring_buffers(sctx))
3916 return false;
3917 } else {
3918 si_pm4_bind_state(sctx, vs, NULL);
3919 }
3920 } else {
3921 if (!key.u.ngg) {
3922 si_pm4_bind_state(sctx, gs, NULL);
3923 if (sctx->chip_class <= GFX8)
3924 si_pm4_bind_state(sctx, es, NULL);
3925 }
3926 }
3927
3928 /* Update VS. */
3929 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
3930 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
3931 if (r)
3932 return false;
3933
3934 if (!key.u.tess && !key.u.gs) {
3935 if (key.u.ngg) {
3936 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3937 si_pm4_bind_state(sctx, vs, NULL);
3938 } else {
3939 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3940 }
3941 } else if (sctx->tes_shader.cso) {
3942 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3943 } else {
3944 assert(sctx->gs_shader.cso);
3945 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3946 }
3947 }
3948
3949 si_update_vgt_shader_config(sctx, key);
3950
3951 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3952 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3953
3954 if (sctx->ps_shader.cso) {
3955 unsigned db_shader_control;
3956
3957 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
3958 if (r)
3959 return false;
3960 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3961
3962 db_shader_control =
3963 sctx->ps_shader.cso->db_shader_control |
3964 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3965
3966 if (si_pm4_state_changed(sctx, ps) ||
3967 si_pm4_state_changed(sctx, vs) ||
3968 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
3969 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3970 sctx->flatshade != rs->flatshade) {
3971 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3972 sctx->flatshade = rs->flatshade;
3973 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3974 }
3975
3976 if (sctx->screen->rbplus_allowed &&
3977 si_pm4_state_changed(sctx, ps) &&
3978 (!old_ps ||
3979 old_spi_shader_col_format !=
3980 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3981 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3982
3983 if (sctx->ps_db_shader_control != db_shader_control) {
3984 sctx->ps_db_shader_control = db_shader_control;
3985 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3986 if (sctx->screen->dpbb_allowed)
3987 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3988 }
3989
3990 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3991 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3992 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3993
3994 if (sctx->chip_class == GFX6)
3995 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3996
3997 if (sctx->framebuffer.nr_samples <= 1)
3998 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3999 }
4000 }
4001
4002 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
4003 si_pm4_state_enabled_and_changed(sctx, hs) ||
4004 si_pm4_state_enabled_and_changed(sctx, es) ||
4005 si_pm4_state_enabled_and_changed(sctx, gs) ||
4006 si_pm4_state_enabled_and_changed(sctx, vs) ||
4007 si_pm4_state_enabled_and_changed(sctx, ps)) {
4008 if (!si_update_spi_tmpring_size(sctx))
4009 return false;
4010 }
4011
4012 if (sctx->chip_class >= GFX7) {
4013 if (si_pm4_state_enabled_and_changed(sctx, ls))
4014 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
4015 else if (!sctx->queued.named.ls)
4016 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
4017
4018 if (si_pm4_state_enabled_and_changed(sctx, hs))
4019 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
4020 else if (!sctx->queued.named.hs)
4021 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
4022
4023 if (si_pm4_state_enabled_and_changed(sctx, es))
4024 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4025 else if (!sctx->queued.named.es)
4026 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4027
4028 if (si_pm4_state_enabled_and_changed(sctx, gs))
4029 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4030 else if (!sctx->queued.named.gs)
4031 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4032
4033 if (si_pm4_state_enabled_and_changed(sctx, vs))
4034 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4035 else if (!sctx->queued.named.vs)
4036 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4037
4038 if (si_pm4_state_enabled_and_changed(sctx, ps))
4039 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4040 else if (!sctx->queued.named.ps)
4041 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4042 }
4043
4044 sctx->do_update_shaders = false;
4045 return true;
4046 }
4047
4048 static void si_emit_scratch_state(struct si_context *sctx)
4049 {
4050 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4051
4052 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4053 sctx->spi_tmpring_size);
4054
4055 if (sctx->scratch_buffer) {
4056 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4057 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4058 RADEON_PRIO_SCRATCH_BUFFER);
4059 }
4060 }
4061
4062 void si_init_shader_functions(struct si_context *sctx)
4063 {
4064 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4065 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4066
4067 sctx->b.create_vs_state = si_create_shader_selector;
4068 sctx->b.create_tcs_state = si_create_shader_selector;
4069 sctx->b.create_tes_state = si_create_shader_selector;
4070 sctx->b.create_gs_state = si_create_shader_selector;
4071 sctx->b.create_fs_state = si_create_shader_selector;
4072
4073 sctx->b.bind_vs_state = si_bind_vs_shader;
4074 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4075 sctx->b.bind_tes_state = si_bind_tes_shader;
4076 sctx->b.bind_gs_state = si_bind_gs_shader;
4077 sctx->b.bind_fs_state = si_bind_ps_shader;
4078
4079 sctx->b.delete_vs_state = si_delete_shader_selector;
4080 sctx->b.delete_tcs_state = si_delete_shader_selector;
4081 sctx->b.delete_tes_state = si_delete_shader_selector;
4082 sctx->b.delete_gs_state = si_delete_shader_selector;
4083 sctx->b.delete_fs_state = si_delete_shader_selector;
4084 }