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radeonsi/gfx10: improve performance for TES using PrimID but not exporting it
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
36
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41
42 /* SHADER_CACHE */
43
44 /**
45 * Return the IR key for the shader cache.
46 */
47 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
48 unsigned char ir_sha1_cache_key[20])
49 {
50 struct blob blob = {};
51 unsigned ir_size;
52 void *ir_binary;
53
54 if (sel->tokens) {
55 ir_binary = sel->tokens;
56 ir_size = tgsi_num_tokens(sel->tokens) *
57 sizeof(struct tgsi_token);
58 } else if (sel->nir_binary) {
59 ir_binary = sel->nir_binary;
60 ir_size = sel->nir_size;
61 } else {
62 assert(sel->nir);
63
64 blob_init(&blob);
65 nir_serialize(&blob, sel->nir, true);
66 ir_binary = blob.data;
67 ir_size = blob.size;
68 }
69
70 /* These settings affect the compilation, but they are not derived
71 * from the input shader IR.
72 */
73 unsigned shader_variant_flags = 0;
74
75 if (ngg)
76 shader_variant_flags |= 1 << 0;
77 if (sel->nir)
78 shader_variant_flags |= 1 << 1;
79 if (si_get_wave_size(sel->screen, sel->type, ngg, es) == 32)
80 shader_variant_flags |= 1 << 2;
81 if (sel->force_correct_derivs_after_kill)
82 shader_variant_flags |= 1 << 3;
83
84 struct mesa_sha1 ctx;
85 _mesa_sha1_init(&ctx);
86 _mesa_sha1_update(&ctx, &shader_variant_flags, 4);
87 _mesa_sha1_update(&ctx, ir_binary, ir_size);
88 if (sel->type == PIPE_SHADER_VERTEX ||
89 sel->type == PIPE_SHADER_TESS_EVAL ||
90 sel->type == PIPE_SHADER_GEOMETRY)
91 _mesa_sha1_update(&ctx, &sel->so, sizeof(sel->so));
92 _mesa_sha1_final(&ctx, ir_sha1_cache_key);
93
94 if (ir_binary == blob.data)
95 blob_finish(&blob);
96 }
97
98 /** Copy "data" to "ptr" and return the next dword following copied data. */
99 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
100 {
101 /* data may be NULL if size == 0 */
102 if (size)
103 memcpy(ptr, data, size);
104 ptr += DIV_ROUND_UP(size, 4);
105 return ptr;
106 }
107
108 /** Read data from "ptr". Return the next dword following the data. */
109 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
110 {
111 memcpy(data, ptr, size);
112 ptr += DIV_ROUND_UP(size, 4);
113 return ptr;
114 }
115
116 /**
117 * Write the size as uint followed by the data. Return the next dword
118 * following the copied data.
119 */
120 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
121 {
122 *ptr++ = size;
123 return write_data(ptr, data, size);
124 }
125
126 /**
127 * Read the size as uint followed by the data. Return both via parameters.
128 * Return the next dword following the data.
129 */
130 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
131 {
132 *size = *ptr++;
133 assert(*data == NULL);
134 if (!*size)
135 return ptr;
136 *data = malloc(*size);
137 return read_data(ptr, *data, *size);
138 }
139
140 /**
141 * Return the shader binary in a buffer. The first 4 bytes contain its size
142 * as integer.
143 */
144 static void *si_get_shader_binary(struct si_shader *shader)
145 {
146 /* There is always a size of data followed by the data itself. */
147 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
148 strlen(shader->binary.llvm_ir_string) + 1 : 0;
149
150 /* Refuse to allocate overly large buffers and guard against integer
151 * overflow. */
152 if (shader->binary.elf_size > UINT_MAX / 4 ||
153 llvm_ir_size > UINT_MAX / 4)
154 return NULL;
155
156 unsigned size =
157 4 + /* total size */
158 4 + /* CRC32 of the data below */
159 align(sizeof(shader->config), 4) +
160 align(sizeof(shader->info), 4) +
161 4 + align(shader->binary.elf_size, 4) +
162 4 + align(llvm_ir_size, 4);
163 void *buffer = CALLOC(1, size);
164 uint32_t *ptr = (uint32_t*)buffer;
165
166 if (!buffer)
167 return NULL;
168
169 *ptr++ = size;
170 ptr++; /* CRC32 is calculated at the end. */
171
172 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
173 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
174 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
175 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
176 assert((char *)ptr - (char *)buffer == size);
177
178 /* Compute CRC32. */
179 ptr = (uint32_t*)buffer;
180 ptr++;
181 *ptr = util_hash_crc32(ptr + 1, size - 8);
182
183 return buffer;
184 }
185
186 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
187 {
188 uint32_t *ptr = (uint32_t*)binary;
189 uint32_t size = *ptr++;
190 uint32_t crc32 = *ptr++;
191 unsigned chunk_size;
192 unsigned elf_size;
193
194 if (util_hash_crc32(ptr, size - 8) != crc32) {
195 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
196 return false;
197 }
198
199 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
200 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
201 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
202 &elf_size);
203 shader->binary.elf_size = elf_size;
204 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
205
206 return true;
207 }
208
209 /**
210 * Insert a shader into the cache. It's assumed the shader is not in the cache.
211 * Use si_shader_cache_load_shader before calling this.
212 */
213 void si_shader_cache_insert_shader(struct si_screen *sscreen,
214 unsigned char ir_sha1_cache_key[20],
215 struct si_shader *shader,
216 bool insert_into_disk_cache)
217 {
218 void *hw_binary;
219 struct hash_entry *entry;
220 uint8_t key[CACHE_KEY_SIZE];
221
222 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
223 if (entry)
224 return; /* already added */
225
226 hw_binary = si_get_shader_binary(shader);
227 if (!hw_binary)
228 return;
229
230 if (_mesa_hash_table_insert(sscreen->shader_cache,
231 mem_dup(ir_sha1_cache_key, 20),
232 hw_binary) == NULL) {
233 FREE(hw_binary);
234 return;
235 }
236
237 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
238 disk_cache_compute_key(sscreen->disk_shader_cache,
239 ir_sha1_cache_key, 20, key);
240 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
241 *((uint32_t *) hw_binary), NULL);
242 }
243 }
244
245 bool si_shader_cache_load_shader(struct si_screen *sscreen,
246 unsigned char ir_sha1_cache_key[20],
247 struct si_shader *shader)
248 {
249 struct hash_entry *entry =
250 _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
251 if (!entry) {
252 if (sscreen->disk_shader_cache) {
253 unsigned char sha1[CACHE_KEY_SIZE];
254
255 disk_cache_compute_key(sscreen->disk_shader_cache,
256 ir_sha1_cache_key, 20, sha1);
257
258 size_t binary_size;
259 uint8_t *buffer =
260 disk_cache_get(sscreen->disk_shader_cache,
261 sha1, &binary_size);
262 if (!buffer)
263 return false;
264
265 if (binary_size < sizeof(uint32_t) ||
266 *((uint32_t*)buffer) != binary_size) {
267 /* Something has gone wrong discard the item
268 * from the cache and rebuild/link from
269 * source.
270 */
271 assert(!"Invalid radeonsi shader disk cache "
272 "item!");
273
274 disk_cache_remove(sscreen->disk_shader_cache,
275 sha1);
276 free(buffer);
277
278 return false;
279 }
280
281 if (!si_load_shader_binary(shader, buffer)) {
282 free(buffer);
283 return false;
284 }
285 free(buffer);
286
287 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
288 shader, false);
289 } else {
290 return false;
291 }
292 } else {
293 if (!si_load_shader_binary(shader, entry->data))
294 return false;
295 }
296 p_atomic_inc(&sscreen->num_shader_cache_hits);
297 return true;
298 }
299
300 static uint32_t si_shader_cache_key_hash(const void *key)
301 {
302 /* Take the first dword of SHA1. */
303 return *(uint32_t*)key;
304 }
305
306 static bool si_shader_cache_key_equals(const void *a, const void *b)
307 {
308 /* Compare SHA1s. */
309 return memcmp(a, b, 20) == 0;
310 }
311
312 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
313 {
314 FREE((void*)entry->key);
315 FREE(entry->data);
316 }
317
318 bool si_init_shader_cache(struct si_screen *sscreen)
319 {
320 (void) simple_mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
321 sscreen->shader_cache =
322 _mesa_hash_table_create(NULL,
323 si_shader_cache_key_hash,
324 si_shader_cache_key_equals);
325
326 return sscreen->shader_cache != NULL;
327 }
328
329 void si_destroy_shader_cache(struct si_screen *sscreen)
330 {
331 if (sscreen->shader_cache)
332 _mesa_hash_table_destroy(sscreen->shader_cache,
333 si_destroy_shader_cache_entry);
334 simple_mtx_destroy(&sscreen->shader_cache_mutex);
335 }
336
337 /* SHADER STATES */
338
339 static void si_set_tesseval_regs(struct si_screen *sscreen,
340 const struct si_shader_selector *tes,
341 struct si_pm4_state *pm4)
342 {
343 const struct tgsi_shader_info *info = &tes->info;
344 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
345 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
346 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
347 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
348 unsigned type, partitioning, topology, distribution_mode;
349
350 switch (tes_prim_mode) {
351 case PIPE_PRIM_LINES:
352 type = V_028B6C_TESS_ISOLINE;
353 break;
354 case PIPE_PRIM_TRIANGLES:
355 type = V_028B6C_TESS_TRIANGLE;
356 break;
357 case PIPE_PRIM_QUADS:
358 type = V_028B6C_TESS_QUAD;
359 break;
360 default:
361 assert(0);
362 return;
363 }
364
365 switch (tes_spacing) {
366 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
367 partitioning = V_028B6C_PART_FRAC_ODD;
368 break;
369 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
370 partitioning = V_028B6C_PART_FRAC_EVEN;
371 break;
372 case PIPE_TESS_SPACING_EQUAL:
373 partitioning = V_028B6C_PART_INTEGER;
374 break;
375 default:
376 assert(0);
377 return;
378 }
379
380 if (tes_point_mode)
381 topology = V_028B6C_OUTPUT_POINT;
382 else if (tes_prim_mode == PIPE_PRIM_LINES)
383 topology = V_028B6C_OUTPUT_LINE;
384 else if (tes_vertex_order_cw)
385 /* for some reason, this must be the other way around */
386 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
387 else
388 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
389
390 if (sscreen->info.has_distributed_tess) {
391 if (sscreen->info.family == CHIP_FIJI ||
392 sscreen->info.family >= CHIP_POLARIS10)
393 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
394 else
395 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
396 } else
397 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
398
399 assert(pm4->shader);
400 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
401 S_028B6C_PARTITIONING(partitioning) |
402 S_028B6C_TOPOLOGY(topology) |
403 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
404 }
405
406 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
407 * whether the "fractional odd" tessellation spacing is used.
408 *
409 * Possible VGT configurations and which state should set the register:
410 *
411 * Reg set in | VGT shader configuration | Value
412 * ------------------------------------------------------
413 * VS as VS | VS | 30
414 * VS as ES | ES -> GS -> VS | 30
415 * TES as VS | LS -> HS -> VS | 14 or 30
416 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
417 *
418 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
419 */
420 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
421 struct si_shader_selector *sel,
422 struct si_shader *shader,
423 struct si_pm4_state *pm4)
424 {
425 unsigned type = sel->type;
426
427 if (sscreen->info.family < CHIP_POLARIS10 ||
428 sscreen->info.chip_class >= GFX10)
429 return;
430
431 /* VS as VS, or VS as ES: */
432 if ((type == PIPE_SHADER_VERTEX &&
433 (!shader ||
434 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
435 /* TES as VS, or TES as ES: */
436 type == PIPE_SHADER_TESS_EVAL) {
437 unsigned vtx_reuse_depth = 30;
438
439 if (type == PIPE_SHADER_TESS_EVAL &&
440 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
441 PIPE_TESS_SPACING_FRACTIONAL_ODD)
442 vtx_reuse_depth = 14;
443
444 assert(pm4->shader);
445 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
446 }
447 }
448
449 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
450 {
451 if (shader->pm4)
452 si_pm4_clear_state(shader->pm4);
453 else
454 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
455
456 if (shader->pm4) {
457 shader->pm4->shader = shader;
458 return shader->pm4;
459 } else {
460 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
461 return NULL;
462 }
463 }
464
465 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
466 {
467 /* Add the pointer to VBO descriptors. */
468 return num_always_on_user_sgprs + 1;
469 }
470
471 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
472 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen,
473 struct si_shader *shader, bool legacy_vs_prim_id)
474 {
475 assert(shader->selector->type == PIPE_SHADER_VERTEX ||
476 (shader->previous_stage_sel &&
477 shader->previous_stage_sel->type == PIPE_SHADER_VERTEX));
478
479 /* GFX6-9 LS (VertexID, RelAutoindex, InstanceID / StepRate0(==1), ...).
480 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID, ...)
481 * GFX10 LS (VertexID, RelAutoindex, UserVGPR1, InstanceID).
482 * GFX10 ES,VS (VertexID, UserVGPR0, UserVGPR1 or VSPrimID, UserVGPR2 or InstanceID)
483 */
484 bool is_ls = shader->selector->type == PIPE_SHADER_TESS_CTRL || shader->key.as_ls;
485
486 if (sscreen->info.chip_class >= GFX10 && shader->info.uses_instanceid)
487 return 3;
488 else if ((is_ls && shader->info.uses_instanceid) || legacy_vs_prim_id)
489 return 2;
490 else if (is_ls || shader->info.uses_instanceid)
491 return 1;
492 else
493 return 0;
494 }
495
496 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
497 {
498 struct si_pm4_state *pm4;
499 uint64_t va;
500
501 assert(sscreen->info.chip_class <= GFX8);
502
503 pm4 = si_get_shader_pm4_state(shader);
504 if (!pm4)
505 return;
506
507 va = shader->bo->gpu_address;
508 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
509
510 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
511 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
512
513 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
514 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
515 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen, shader, false)) |
516 S_00B528_DX10_CLAMP(1) |
517 S_00B528_FLOAT_MODE(shader->config.float_mode);
518 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
519 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
520 }
521
522 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
523 {
524 struct si_pm4_state *pm4;
525 uint64_t va;
526
527 pm4 = si_get_shader_pm4_state(shader);
528 if (!pm4)
529 return;
530
531 va = shader->bo->gpu_address;
532 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
533
534 if (sscreen->info.chip_class >= GFX9) {
535 if (sscreen->info.chip_class >= GFX10) {
536 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
537 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
538 } else {
539 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
540 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
541 }
542
543 unsigned num_user_sgprs =
544 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
545
546 shader->config.rsrc2 =
547 S_00B42C_USER_SGPR(num_user_sgprs) |
548 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
549
550 if (sscreen->info.chip_class >= GFX10)
551 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
552 else
553 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
554 } else {
555 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
556 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
557
558 shader->config.rsrc2 =
559 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
560 S_00B42C_OC_LDS_EN(1) |
561 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
562 }
563
564 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
565 S_00B428_VGPRS((shader->config.num_vgprs - 1) /
566 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
567 (sscreen->info.chip_class <= GFX9 ?
568 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
569 S_00B428_DX10_CLAMP(1) |
570 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
571 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
572 S_00B428_FLOAT_MODE(shader->config.float_mode) |
573 S_00B428_LS_VGPR_COMP_CNT(sscreen->info.chip_class >= GFX9 ?
574 si_get_vs_vgpr_comp_cnt(sscreen, shader, false) : 0));
575
576 if (sscreen->info.chip_class <= GFX8) {
577 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
578 shader->config.rsrc2);
579 }
580 }
581
582 static void si_emit_shader_es(struct si_context *sctx)
583 {
584 struct si_shader *shader = sctx->queued.named.es->shader;
585 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
586
587 if (!shader)
588 return;
589
590 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
591 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
592 shader->selector->esgs_itemsize / 4);
593
594 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
595 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
596 SI_TRACKED_VGT_TF_PARAM,
597 shader->vgt_tf_param);
598
599 if (shader->vgt_vertex_reuse_block_cntl)
600 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
601 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
602 shader->vgt_vertex_reuse_block_cntl);
603
604 if (initial_cdw != sctx->gfx_cs->current.cdw)
605 sctx->context_roll = true;
606 }
607
608 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
609 {
610 struct si_pm4_state *pm4;
611 unsigned num_user_sgprs;
612 unsigned vgpr_comp_cnt;
613 uint64_t va;
614 unsigned oc_lds_en;
615
616 assert(sscreen->info.chip_class <= GFX8);
617
618 pm4 = si_get_shader_pm4_state(shader);
619 if (!pm4)
620 return;
621
622 pm4->atom.emit = si_emit_shader_es;
623 va = shader->bo->gpu_address;
624 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
625
626 if (shader->selector->type == PIPE_SHADER_VERTEX) {
627 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
628 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
629 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
630 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
631 num_user_sgprs = SI_TES_NUM_USER_SGPR;
632 } else
633 unreachable("invalid shader selector type");
634
635 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
636
637 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
638 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
639 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
640 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
641 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
642 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
643 S_00B328_DX10_CLAMP(1) |
644 S_00B328_FLOAT_MODE(shader->config.float_mode));
645 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
646 S_00B32C_USER_SGPR(num_user_sgprs) |
647 S_00B32C_OC_LDS_EN(oc_lds_en) |
648 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
649
650 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
651 si_set_tesseval_regs(sscreen, shader->selector, pm4);
652
653 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
654 }
655
656 void gfx9_get_gs_info(struct si_shader_selector *es,
657 struct si_shader_selector *gs,
658 struct gfx9_gs_info *out)
659 {
660 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
661 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
662 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
663 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
664
665 /* All these are in dwords: */
666 /* We can't allow using the whole LDS, because GS waves compete with
667 * other shader stages for LDS space. */
668 const unsigned max_lds_size = 8 * 1024;
669 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
670 unsigned esgs_lds_size;
671
672 /* All these are per subgroup: */
673 const unsigned max_out_prims = 32 * 1024;
674 const unsigned max_es_verts = 255;
675 const unsigned ideal_gs_prims = 64;
676 unsigned max_gs_prims, gs_prims;
677 unsigned min_es_verts, es_verts, worst_case_es_verts;
678
679 if (uses_adjacency || gs_num_invocations > 1)
680 max_gs_prims = 127 / gs_num_invocations;
681 else
682 max_gs_prims = 255;
683
684 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
685 * Make sure we don't go over the maximum value.
686 */
687 if (gs->gs_max_out_vertices > 0) {
688 max_gs_prims = MIN2(max_gs_prims,
689 max_out_prims /
690 (gs->gs_max_out_vertices * gs_num_invocations));
691 }
692 assert(max_gs_prims > 0);
693
694 /* If the primitive has adjacency, halve the number of vertices
695 * that will be reused in multiple primitives.
696 */
697 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
698
699 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
700 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
701
702 /* Compute ESGS LDS size based on the worst case number of ES vertices
703 * needed to create the target number of GS prims per subgroup.
704 */
705 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
706
707 /* If total LDS usage is too big, refactor partitions based on ratio
708 * of ESGS item sizes.
709 */
710 if (esgs_lds_size > max_lds_size) {
711 /* Our target GS Prims Per Subgroup was too large. Calculate
712 * the maximum number of GS Prims Per Subgroup that will fit
713 * into LDS, capped by the maximum that the hardware can support.
714 */
715 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
716 max_gs_prims);
717 assert(gs_prims > 0);
718 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
719 max_es_verts);
720
721 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
722 assert(esgs_lds_size <= max_lds_size);
723 }
724
725 /* Now calculate remaining ESGS information. */
726 if (esgs_lds_size)
727 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
728 else
729 es_verts = max_es_verts;
730
731 /* Vertices for adjacency primitives are not always reused, so restore
732 * it for ES_VERTS_PER_SUBGRP.
733 */
734 min_es_verts = gs->gs_input_verts_per_prim;
735
736 /* For normal primitives, the VGT only checks if they are past the ES
737 * verts per subgroup after allocating a full GS primitive and if they
738 * are, kick off a new subgroup. But if those additional ES verts are
739 * unique (e.g. not reused) we need to make sure there is enough LDS
740 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
741 */
742 es_verts -= min_es_verts - 1;
743
744 out->es_verts_per_subgroup = es_verts;
745 out->gs_prims_per_subgroup = gs_prims;
746 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
747 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
748 gs->gs_max_out_vertices;
749 out->esgs_ring_size = 4 * esgs_lds_size;
750
751 assert(out->max_prims_per_subgroup <= max_out_prims);
752 }
753
754 static void si_emit_shader_gs(struct si_context *sctx)
755 {
756 struct si_shader *shader = sctx->queued.named.gs->shader;
757 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
758
759 if (!shader)
760 return;
761
762 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
763 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
764 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
765 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
766 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
767 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
768 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
769
770 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
771 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
772 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
773 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
774
775 /* R_028B38_VGT_GS_MAX_VERT_OUT */
776 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
777 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
778 shader->ctx_reg.gs.vgt_gs_max_vert_out);
779
780 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
781 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
782 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
783 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
784 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
785 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
786 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
787 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
788
789 /* R_028B90_VGT_GS_INSTANCE_CNT */
790 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
791 SI_TRACKED_VGT_GS_INSTANCE_CNT,
792 shader->ctx_reg.gs.vgt_gs_instance_cnt);
793
794 if (sctx->chip_class >= GFX9) {
795 /* R_028A44_VGT_GS_ONCHIP_CNTL */
796 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
797 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
798 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
799 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
800 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
801 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
802 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
803 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
804 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
805 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
806 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
807
808 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
809 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
810 SI_TRACKED_VGT_TF_PARAM,
811 shader->vgt_tf_param);
812 if (shader->vgt_vertex_reuse_block_cntl)
813 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
814 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
815 shader->vgt_vertex_reuse_block_cntl);
816 }
817
818 if (initial_cdw != sctx->gfx_cs->current.cdw)
819 sctx->context_roll = true;
820 }
821
822 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
823 {
824 struct si_shader_selector *sel = shader->selector;
825 const ubyte *num_components = sel->info.num_stream_output_components;
826 unsigned gs_num_invocations = sel->gs_num_invocations;
827 struct si_pm4_state *pm4;
828 uint64_t va;
829 unsigned max_stream = sel->max_gs_stream;
830 unsigned offset;
831
832 pm4 = si_get_shader_pm4_state(shader);
833 if (!pm4)
834 return;
835
836 pm4->atom.emit = si_emit_shader_gs;
837
838 offset = num_components[0] * sel->gs_max_out_vertices;
839 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
840
841 if (max_stream >= 1)
842 offset += num_components[1] * sel->gs_max_out_vertices;
843 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
844
845 if (max_stream >= 2)
846 offset += num_components[2] * sel->gs_max_out_vertices;
847 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
848
849 if (max_stream >= 3)
850 offset += num_components[3] * sel->gs_max_out_vertices;
851 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
852
853 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
854 assert(offset < (1 << 15));
855
856 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
857
858 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
859 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
860 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
861 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
862
863 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
864 S_028B90_ENABLE(gs_num_invocations > 0);
865
866 va = shader->bo->gpu_address;
867 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
868
869 if (sscreen->info.chip_class >= GFX9) {
870 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
871 unsigned es_type = shader->key.part.gs.es->type;
872 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
873
874 if (es_type == PIPE_SHADER_VERTEX) {
875 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
876 } else if (es_type == PIPE_SHADER_TESS_EVAL)
877 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
878 else
879 unreachable("invalid shader selector type");
880
881 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
882 * VGPR[0:4] are always loaded.
883 */
884 if (sel->info.uses_invocationid)
885 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
886 else if (sel->info.uses_primid)
887 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
888 else if (input_prim >= PIPE_PRIM_TRIANGLES)
889 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
890 else
891 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
892
893 unsigned num_user_sgprs;
894 if (es_type == PIPE_SHADER_VERTEX)
895 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
896 else
897 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
898
899 if (sscreen->info.chip_class >= GFX10) {
900 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
901 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
902 } else {
903 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
904 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
905 }
906
907 uint32_t rsrc1 =
908 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
909 S_00B228_DX10_CLAMP(1) |
910 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
911 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
912 S_00B228_FLOAT_MODE(shader->config.float_mode) |
913 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
914 uint32_t rsrc2 =
915 S_00B22C_USER_SGPR(num_user_sgprs) |
916 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
917 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
918 S_00B22C_LDS_SIZE(shader->config.lds_size) |
919 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
920
921 if (sscreen->info.chip_class >= GFX10) {
922 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
923 } else {
924 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
925 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
926 }
927
928 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
929 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
930
931 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
932 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
933 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
934 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
935 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
936 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
937 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
938 shader->key.part.gs.es->esgs_itemsize / 4;
939
940 if (es_type == PIPE_SHADER_TESS_EVAL)
941 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
942
943 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
944 NULL, pm4);
945 } else {
946 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
947 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
948
949 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
950 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
951 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
952 S_00B228_DX10_CLAMP(1) |
953 S_00B228_FLOAT_MODE(shader->config.float_mode));
954 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
955 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
956 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
957 }
958 }
959
960 /* Common tail code for NGG primitive shaders. */
961 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
962 struct si_shader *shader,
963 unsigned initial_cdw)
964 {
965 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
966 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
967 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
968 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
969 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
970 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
971 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
972 SI_TRACKED_VGT_PRIMITIVEID_EN,
973 shader->ctx_reg.ngg.vgt_primitiveid_en);
974 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
975 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
976 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
977 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
978 SI_TRACKED_VGT_GS_INSTANCE_CNT,
979 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
980 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
981 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
982 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
983 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
984 SI_TRACKED_SPI_VS_OUT_CONFIG,
985 shader->ctx_reg.ngg.spi_vs_out_config);
986 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
987 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
988 shader->ctx_reg.ngg.spi_shader_idx_format,
989 shader->ctx_reg.ngg.spi_shader_pos_format);
990 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
991 SI_TRACKED_PA_CL_VTE_CNTL,
992 shader->ctx_reg.ngg.pa_cl_vte_cntl);
993 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
994 SI_TRACKED_PA_CL_NGG_CNTL,
995 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
996
997 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
998 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
999 shader->pa_cl_vs_out_cntl,
1000 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1001
1002 if (initial_cdw != sctx->gfx_cs->current.cdw)
1003 sctx->context_roll = true;
1004 }
1005
1006 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
1007 {
1008 struct si_shader *shader = sctx->queued.named.gs->shader;
1009 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1010
1011 if (!shader)
1012 return;
1013
1014 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1015 }
1016
1017 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1018 {
1019 struct si_shader *shader = sctx->queued.named.gs->shader;
1020 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1021
1022 if (!shader)
1023 return;
1024
1025 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1026 SI_TRACKED_VGT_TF_PARAM,
1027 shader->vgt_tf_param);
1028
1029 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1030 }
1031
1032 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1033 {
1034 struct si_shader *shader = sctx->queued.named.gs->shader;
1035 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1036
1037 if (!shader)
1038 return;
1039
1040 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1041 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1042 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1043
1044 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1045 }
1046
1047 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1048 {
1049 struct si_shader *shader = sctx->queued.named.gs->shader;
1050 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1051
1052 if (!shader)
1053 return;
1054
1055 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1056 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1057 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1058 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1059 SI_TRACKED_VGT_TF_PARAM,
1060 shader->vgt_tf_param);
1061
1062 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1063 }
1064
1065 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1066 {
1067 if (gs->type == PIPE_SHADER_GEOMETRY)
1068 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1069
1070 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1071 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1072 return PIPE_PRIM_POINTS;
1073 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1074 return PIPE_PRIM_LINES;
1075 return PIPE_PRIM_TRIANGLES;
1076 }
1077
1078 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1079 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1080 }
1081
1082 static unsigned si_get_vs_out_cntl(const struct si_shader_selector *sel, bool ngg)
1083 {
1084 bool misc_vec_ena =
1085 sel->info.writes_psize || (sel->info.writes_edgeflag && !ngg) ||
1086 sel->info.writes_layer || sel->info.writes_viewport_index;
1087 return S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
1088 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag && !ngg) |
1089 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
1090 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
1091 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1092 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
1093 }
1094
1095 /**
1096 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1097 * in NGG mode.
1098 */
1099 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1100 {
1101 const struct si_shader_selector *gs_sel = shader->selector;
1102 const struct tgsi_shader_info *gs_info = &gs_sel->info;
1103 enum pipe_shader_type gs_type = shader->selector->type;
1104 const struct si_shader_selector *es_sel =
1105 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1106 const struct tgsi_shader_info *es_info = &es_sel->info;
1107 enum pipe_shader_type es_type = es_sel->type;
1108 unsigned num_user_sgprs;
1109 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1110 uint64_t va;
1111 unsigned window_space =
1112 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1113 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1114 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1115 unsigned input_prim = si_get_input_prim(gs_sel);
1116 bool break_wave_at_eoi = false;
1117 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1118 if (!pm4)
1119 return;
1120
1121 if (es_type == PIPE_SHADER_TESS_EVAL) {
1122 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1123 : gfx10_emit_shader_ngg_tess_nogs;
1124 } else {
1125 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1126 : gfx10_emit_shader_ngg_notess_nogs;
1127 }
1128
1129 va = shader->bo->gpu_address;
1130 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1131
1132 if (es_type == PIPE_SHADER_VERTEX) {
1133 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
1134
1135 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1136 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1137 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1138 } else {
1139 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
1140 }
1141 } else {
1142 assert(es_type == PIPE_SHADER_TESS_EVAL);
1143 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1144 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1145
1146 if (es_enable_prim_id || gs_info->uses_primid)
1147 break_wave_at_eoi = true;
1148 }
1149
1150 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1151 * VGPR[0:4] are always loaded.
1152 *
1153 * Vertex shaders always need to load VGPR3, because they need to
1154 * pass edge flags for decomposed primitives (such as quads) to the PA
1155 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1156 */
1157 if (gs_info->uses_invocationid || gs_type == PIPE_SHADER_VERTEX)
1158 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1159 else if (gs_info->uses_primid)
1160 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1161 else if (input_prim >= PIPE_PRIM_TRIANGLES)
1162 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1163 else
1164 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1165
1166 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1167 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1168 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1169 S_00B228_VGPRS((shader->config.num_vgprs - 1) /
1170 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1171 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1172 S_00B228_DX10_CLAMP(1) |
1173 S_00B228_MEM_ORDERED(1) |
1174 S_00B228_WGP_MODE(1) |
1175 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1176 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1177 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1178 S_00B22C_USER_SGPR(num_user_sgprs) |
1179 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1180 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1181 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1182 S_00B22C_LDS_SIZE(shader->config.lds_size));
1183
1184 nparams = MAX2(shader->info.nr_param_exports, 1);
1185 shader->ctx_reg.ngg.spi_vs_out_config =
1186 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1187 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1188
1189 shader->ctx_reg.ngg.spi_shader_idx_format =
1190 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1191 shader->ctx_reg.ngg.spi_shader_pos_format =
1192 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1193 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1194 V_02870C_SPI_SHADER_4COMP :
1195 V_02870C_SPI_SHADER_NONE) |
1196 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1197 V_02870C_SPI_SHADER_4COMP :
1198 V_02870C_SPI_SHADER_NONE) |
1199 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1200 V_02870C_SPI_SHADER_4COMP :
1201 V_02870C_SPI_SHADER_NONE);
1202
1203 shader->ctx_reg.ngg.vgt_primitiveid_en =
1204 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1205 S_028A84_NGG_DISABLE_PROVOK_REUSE(shader->key.mono.u.vs_export_prim_id ||
1206 gs_sel->info.writes_primid);
1207
1208 if (gs_type == PIPE_SHADER_GEOMETRY) {
1209 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1210 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1211 } else {
1212 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1213 }
1214
1215 if (es_type == PIPE_SHADER_TESS_EVAL)
1216 si_set_tesseval_regs(sscreen, es_sel, pm4);
1217
1218 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1219 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1220 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1221 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1222 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1223 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1224 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1225 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1226 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1227 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1228 S_028B90_CNT(gs_num_invocations) |
1229 S_028B90_ENABLE(gs_num_invocations > 1) |
1230 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1231 shader->ngg.max_vert_out_per_gs_instance);
1232
1233 /* Always output hw-generated edge flags and pass them via the prim
1234 * export to prevent drawing lines on internal edges of decomposed
1235 * primitives (such as quads) with polygon mode = lines. Only VS needs
1236 * this.
1237 */
1238 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1239 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
1240 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(gs_sel, true);
1241
1242 shader->ge_cntl =
1243 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1244 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
1245 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1246
1247 /* Bug workaround for a possible hang with non-tessellation cases.
1248 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1249 *
1250 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1251 */
1252 if ((sscreen->info.family == CHIP_NAVI10 ||
1253 sscreen->info.family == CHIP_NAVI12 ||
1254 sscreen->info.family == CHIP_NAVI14) &&
1255 (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
1256 shader->ngg.hw_max_esverts != 256) {
1257 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1258
1259 if (shader->ngg.hw_max_esverts > 5) {
1260 shader->ge_cntl |=
1261 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1262 }
1263 }
1264
1265 if (window_space) {
1266 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1267 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1268 } else {
1269 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1270 S_028818_VTX_W0_FMT(1) |
1271 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1272 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1273 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1274 }
1275 }
1276
1277 static void si_emit_shader_vs(struct si_context *sctx)
1278 {
1279 struct si_shader *shader = sctx->queued.named.vs->shader;
1280 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1281
1282 if (!shader)
1283 return;
1284
1285 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1286 SI_TRACKED_VGT_GS_MODE,
1287 shader->ctx_reg.vs.vgt_gs_mode);
1288 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1289 SI_TRACKED_VGT_PRIMITIVEID_EN,
1290 shader->ctx_reg.vs.vgt_primitiveid_en);
1291
1292 if (sctx->chip_class <= GFX8) {
1293 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1294 SI_TRACKED_VGT_REUSE_OFF,
1295 shader->ctx_reg.vs.vgt_reuse_off);
1296 }
1297
1298 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1299 SI_TRACKED_SPI_VS_OUT_CONFIG,
1300 shader->ctx_reg.vs.spi_vs_out_config);
1301
1302 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1303 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1304 shader->ctx_reg.vs.spi_shader_pos_format);
1305
1306 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1307 SI_TRACKED_PA_CL_VTE_CNTL,
1308 shader->ctx_reg.vs.pa_cl_vte_cntl);
1309
1310 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1311 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1312 SI_TRACKED_VGT_TF_PARAM,
1313 shader->vgt_tf_param);
1314
1315 if (shader->vgt_vertex_reuse_block_cntl)
1316 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1317 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1318 shader->vgt_vertex_reuse_block_cntl);
1319
1320 if (initial_cdw != sctx->gfx_cs->current.cdw)
1321 sctx->context_roll = true;
1322
1323 /* Required programming for tessellation. (legacy pipeline only) */
1324 if (sctx->chip_class == GFX10 &&
1325 shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1326 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1327 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1328 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1329 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1330 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1331 }
1332
1333 if (sctx->chip_class >= GFX10) {
1334 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1335 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
1336 shader->pa_cl_vs_out_cntl,
1337 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1338 }
1339 }
1340
1341 /**
1342 * Compute the state for \p shader, which will run as a vertex shader on the
1343 * hardware.
1344 *
1345 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1346 * is the copy shader.
1347 */
1348 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1349 struct si_shader_selector *gs)
1350 {
1351 const struct tgsi_shader_info *info = &shader->selector->info;
1352 struct si_pm4_state *pm4;
1353 unsigned num_user_sgprs, vgpr_comp_cnt;
1354 uint64_t va;
1355 unsigned nparams, oc_lds_en;
1356 unsigned window_space =
1357 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1358 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1359
1360 pm4 = si_get_shader_pm4_state(shader);
1361 if (!pm4)
1362 return;
1363
1364 pm4->atom.emit = si_emit_shader_vs;
1365
1366 /* We always write VGT_GS_MODE in the VS state, because every switch
1367 * between different shader pipelines involving a different GS or no
1368 * GS at all involves a switch of the VS (different GS use different
1369 * copy shaders). On the other hand, when the API switches from a GS to
1370 * no GS and then back to the same GS used originally, the GS state is
1371 * not sent again.
1372 */
1373 if (!gs) {
1374 unsigned mode = V_028A40_GS_OFF;
1375
1376 /* PrimID needs GS scenario A. */
1377 if (enable_prim_id)
1378 mode = V_028A40_GS_SCENARIO_A;
1379
1380 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1381 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1382 } else {
1383 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1384 sscreen->info.chip_class);
1385 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1386 }
1387
1388 if (sscreen->info.chip_class <= GFX8) {
1389 /* Reuse needs to be set off if we write oViewport. */
1390 shader->ctx_reg.vs.vgt_reuse_off =
1391 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1392 }
1393
1394 va = shader->bo->gpu_address;
1395 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1396
1397 if (gs) {
1398 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1399 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1400 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1401 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
1402
1403 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1404 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1405 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1406 } else {
1407 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1408 }
1409 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1410 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1411 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1412 } else
1413 unreachable("invalid shader selector type");
1414
1415 /* VS is required to export at least one param. */
1416 nparams = MAX2(shader->info.nr_param_exports, 1);
1417 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1418
1419 if (sscreen->info.chip_class >= GFX10) {
1420 shader->ctx_reg.vs.spi_vs_out_config |=
1421 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1422 }
1423
1424 shader->ctx_reg.vs.spi_shader_pos_format =
1425 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1426 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1427 V_02870C_SPI_SHADER_4COMP :
1428 V_02870C_SPI_SHADER_NONE) |
1429 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1430 V_02870C_SPI_SHADER_4COMP :
1431 V_02870C_SPI_SHADER_NONE) |
1432 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1433 V_02870C_SPI_SHADER_4COMP :
1434 V_02870C_SPI_SHADER_NONE);
1435 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, false);
1436
1437 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1438
1439 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1440 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1441
1442 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
1443 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1444 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1445 S_00B128_DX10_CLAMP(1) |
1446 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1447 S_00B128_FLOAT_MODE(shader->config.float_mode);
1448 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1449 S_00B12C_OC_LDS_EN(oc_lds_en) |
1450 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1451
1452 if (sscreen->info.chip_class <= GFX9)
1453 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1454
1455 if (!sscreen->use_ngg_streamout) {
1456 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1457 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1458 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1459 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1460 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1461 }
1462
1463 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1464 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1465
1466 if (window_space)
1467 shader->ctx_reg.vs.pa_cl_vte_cntl =
1468 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1469 else
1470 shader->ctx_reg.vs.pa_cl_vte_cntl =
1471 S_028818_VTX_W0_FMT(1) |
1472 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1473 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1474 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1475
1476 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1477 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1478
1479 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1480 }
1481
1482 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1483 {
1484 struct tgsi_shader_info *info = &ps->selector->info;
1485 unsigned num_colors = !!(info->colors_read & 0x0f) +
1486 !!(info->colors_read & 0xf0);
1487 unsigned num_interp = ps->selector->info.num_inputs +
1488 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1489
1490 assert(num_interp <= 32);
1491 return MIN2(num_interp, 32);
1492 }
1493
1494 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1495 {
1496 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1497 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1498
1499 /* If the i-th target format is set, all previous target formats must
1500 * be non-zero to avoid hangs.
1501 */
1502 for (i = 0; i < num_targets; i++)
1503 if (!(value & (0xf << (i * 4))))
1504 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1505
1506 return value;
1507 }
1508
1509 static void si_emit_shader_ps(struct si_context *sctx)
1510 {
1511 struct si_shader *shader = sctx->queued.named.ps->shader;
1512 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1513
1514 if (!shader)
1515 return;
1516
1517 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1518 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1519 SI_TRACKED_SPI_PS_INPUT_ENA,
1520 shader->ctx_reg.ps.spi_ps_input_ena,
1521 shader->ctx_reg.ps.spi_ps_input_addr);
1522
1523 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1524 SI_TRACKED_SPI_BARYC_CNTL,
1525 shader->ctx_reg.ps.spi_baryc_cntl);
1526 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1527 SI_TRACKED_SPI_PS_IN_CONTROL,
1528 shader->ctx_reg.ps.spi_ps_in_control);
1529
1530 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1531 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1532 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1533 shader->ctx_reg.ps.spi_shader_z_format,
1534 shader->ctx_reg.ps.spi_shader_col_format);
1535
1536 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1537 SI_TRACKED_CB_SHADER_MASK,
1538 shader->ctx_reg.ps.cb_shader_mask);
1539
1540 if (initial_cdw != sctx->gfx_cs->current.cdw)
1541 sctx->context_roll = true;
1542 }
1543
1544 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1545 {
1546 struct tgsi_shader_info *info = &shader->selector->info;
1547 struct si_pm4_state *pm4;
1548 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1549 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1550 uint64_t va;
1551 unsigned input_ena = shader->config.spi_ps_input_ena;
1552
1553 /* we need to enable at least one of them, otherwise we hang the GPU */
1554 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1555 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1556 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1557 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1558 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1559 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1560 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1561 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1562 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1563 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1564 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1565 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1566 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1567 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1568
1569 /* Validate interpolation optimization flags (read as implications). */
1570 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1571 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1572 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1573 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1574 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1575 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1576 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1577 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1578 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1579 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1580 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1581 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1582 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1583 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1584 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1585 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1586 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1587 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1588
1589 /* Validate cases when the optimizations are off (read as implications). */
1590 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1591 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1592 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1593 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1594 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1595 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1596
1597 pm4 = si_get_shader_pm4_state(shader);
1598 if (!pm4)
1599 return;
1600
1601 pm4->atom.emit = si_emit_shader_ps;
1602
1603 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1604 * Possible vaules:
1605 * 0 -> Position = pixel center
1606 * 1 -> Position = pixel centroid
1607 * 2 -> Position = at sample position
1608 *
1609 * From GLSL 4.5 specification, section 7.1:
1610 * "The variable gl_FragCoord is available as an input variable from
1611 * within fragment shaders and it holds the window relative coordinates
1612 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1613 * value can be for any location within the pixel, or one of the
1614 * fragment samples. The use of centroid does not further restrict
1615 * this value to be inside the current primitive."
1616 *
1617 * Meaning that centroid has no effect and we can return anything within
1618 * the pixel. Thus, return the value at sample position, because that's
1619 * the most accurate one shaders can get.
1620 */
1621 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1622
1623 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1624 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1625 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1626
1627 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1628 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1629
1630 /* Ensure that some export memory is always allocated, for two reasons:
1631 *
1632 * 1) Correctness: The hardware ignores the EXEC mask if no export
1633 * memory is allocated, so KILL and alpha test do not work correctly
1634 * without this.
1635 * 2) Performance: Every shader needs at least a NULL export, even when
1636 * it writes no color/depth output. The NULL export instruction
1637 * stalls without this setting.
1638 *
1639 * Don't add this to CB_SHADER_MASK.
1640 *
1641 * GFX10 supports pixel shaders without exports by setting both
1642 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1643 * instructions if any are present.
1644 */
1645 if ((sscreen->info.chip_class <= GFX9 ||
1646 info->uses_kill ||
1647 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1648 !spi_shader_col_format &&
1649 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1650 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1651
1652 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1653 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1654
1655 /* Set interpolation controls. */
1656 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1657 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1658
1659 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1660 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1661 shader->ctx_reg.ps.spi_shader_z_format =
1662 ac_get_spi_shader_z_format(info->writes_z,
1663 info->writes_stencil,
1664 info->writes_samplemask);
1665 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1666 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1667
1668 va = shader->bo->gpu_address;
1669 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1670 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1671 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1672
1673 uint32_t rsrc1 =
1674 S_00B028_VGPRS((shader->config.num_vgprs - 1) /
1675 (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1676 S_00B028_DX10_CLAMP(1) |
1677 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1678 S_00B028_FLOAT_MODE(shader->config.float_mode);
1679
1680 if (sscreen->info.chip_class < GFX10) {
1681 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1682 }
1683
1684 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1685 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1686 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1687 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1688 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1689 }
1690
1691 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1692 struct si_shader *shader)
1693 {
1694 switch (shader->selector->type) {
1695 case PIPE_SHADER_VERTEX:
1696 if (shader->key.as_ls)
1697 si_shader_ls(sscreen, shader);
1698 else if (shader->key.as_es)
1699 si_shader_es(sscreen, shader);
1700 else if (shader->key.as_ngg)
1701 gfx10_shader_ngg(sscreen, shader);
1702 else
1703 si_shader_vs(sscreen, shader, NULL);
1704 break;
1705 case PIPE_SHADER_TESS_CTRL:
1706 si_shader_hs(sscreen, shader);
1707 break;
1708 case PIPE_SHADER_TESS_EVAL:
1709 if (shader->key.as_es)
1710 si_shader_es(sscreen, shader);
1711 else if (shader->key.as_ngg)
1712 gfx10_shader_ngg(sscreen, shader);
1713 else
1714 si_shader_vs(sscreen, shader, NULL);
1715 break;
1716 case PIPE_SHADER_GEOMETRY:
1717 if (shader->key.as_ngg)
1718 gfx10_shader_ngg(sscreen, shader);
1719 else
1720 si_shader_gs(sscreen, shader);
1721 break;
1722 case PIPE_SHADER_FRAGMENT:
1723 si_shader_ps(sscreen, shader);
1724 break;
1725 default:
1726 assert(0);
1727 }
1728 }
1729
1730 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1731 {
1732 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1733 return sctx->queued.named.dsa->alpha_func;
1734 }
1735
1736 void si_shader_selector_key_vs(struct si_context *sctx,
1737 struct si_shader_selector *vs,
1738 struct si_shader_key *key,
1739 struct si_vs_prolog_bits *prolog_key)
1740 {
1741 if (!sctx->vertex_elements ||
1742 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
1743 return;
1744
1745 struct si_vertex_elements *elts = sctx->vertex_elements;
1746
1747 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1748 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1749 prolog_key->unpack_instance_id_from_vertex_id =
1750 sctx->prim_discard_cs_instancing;
1751
1752 /* Prefer a monolithic shader to allow scheduling divisions around
1753 * VBO loads. */
1754 if (prolog_key->instance_divisor_is_fetched)
1755 key->opt.prefer_mono = 1;
1756
1757 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1758 unsigned count_mask = (1 << count) - 1;
1759 unsigned fix = elts->fix_fetch_always & count_mask;
1760 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1761
1762 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1763 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1764 while (mask) {
1765 unsigned i = u_bit_scan(&mask);
1766 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1767 unsigned vbidx = elts->vertex_buffer_index[i];
1768 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1769 unsigned align_mask = (1 << log_hw_load_size) - 1;
1770 if (vb->buffer_offset & align_mask ||
1771 vb->stride & align_mask) {
1772 fix |= 1 << i;
1773 opencode |= 1 << i;
1774 }
1775 }
1776 }
1777
1778 while (fix) {
1779 unsigned i = u_bit_scan(&fix);
1780 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1781 }
1782 key->mono.vs_fetch_opencode = opencode;
1783 }
1784
1785 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1786 struct si_shader_selector *vs,
1787 struct si_shader_key *key)
1788 {
1789 struct si_shader_selector *ps = sctx->ps_shader.cso;
1790
1791 key->opt.clip_disable =
1792 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1793 (vs->info.clipdist_writemask ||
1794 vs->info.writes_clipvertex) &&
1795 !vs->info.culldist_writemask;
1796
1797 /* Find out if PS is disabled. */
1798 bool ps_disabled = true;
1799 if (ps) {
1800 bool ps_modifies_zs = ps->info.uses_kill ||
1801 ps->info.writes_z ||
1802 ps->info.writes_stencil ||
1803 ps->info.writes_samplemask ||
1804 sctx->queued.named.blend->alpha_to_coverage ||
1805 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1806 unsigned ps_colormask = si_get_total_colormask(sctx);
1807
1808 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1809 (!ps_colormask &&
1810 !ps_modifies_zs &&
1811 !ps->info.writes_memory);
1812 }
1813
1814 /* Find out which VS outputs aren't used by the PS. */
1815 uint64_t outputs_written = vs->outputs_written_before_ps;
1816 uint64_t inputs_read = 0;
1817
1818 /* Ignore outputs that are not passed from VS to PS. */
1819 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1820 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1821 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1822
1823 if (!ps_disabled) {
1824 inputs_read = ps->inputs_read;
1825 }
1826
1827 uint64_t linked = outputs_written & inputs_read;
1828
1829 key->opt.kill_outputs = ~linked & outputs_written;
1830 }
1831
1832 /* Compute the key for the hw shader variant */
1833 static inline void si_shader_selector_key(struct pipe_context *ctx,
1834 struct si_shader_selector *sel,
1835 union si_vgt_stages_key stages_key,
1836 struct si_shader_key *key)
1837 {
1838 struct si_context *sctx = (struct si_context *)ctx;
1839
1840 memset(key, 0, sizeof(*key));
1841
1842 switch (sel->type) {
1843 case PIPE_SHADER_VERTEX:
1844 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1845
1846 if (sctx->tes_shader.cso)
1847 key->as_ls = 1;
1848 else if (sctx->gs_shader.cso) {
1849 key->as_es = 1;
1850 key->as_ngg = stages_key.u.ngg;
1851 } else {
1852 key->as_ngg = stages_key.u.ngg;
1853 si_shader_selector_key_hw_vs(sctx, sel, key);
1854
1855 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1856 key->mono.u.vs_export_prim_id = 1;
1857 }
1858 break;
1859 case PIPE_SHADER_TESS_CTRL:
1860 if (sctx->chip_class >= GFX9) {
1861 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1862 key, &key->part.tcs.ls_prolog);
1863 key->part.tcs.ls = sctx->vs_shader.cso;
1864
1865 /* When the LS VGPR fix is needed, monolithic shaders
1866 * can:
1867 * - avoid initializing EXEC in both the LS prolog
1868 * and the LS main part when !vs_needs_prolog
1869 * - remove the fixup for unused input VGPRs
1870 */
1871 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1872
1873 /* The LS output / HS input layout can be communicated
1874 * directly instead of via user SGPRs for merged LS-HS.
1875 * The LS VGPR fix prefers this too.
1876 */
1877 key->opt.prefer_mono = 1;
1878 }
1879
1880 key->part.tcs.epilog.prim_mode =
1881 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1882 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1883 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1884 key->part.tcs.epilog.tes_reads_tess_factors =
1885 sctx->tes_shader.cso->info.reads_tess_factors;
1886
1887 if (sel == sctx->fixed_func_tcs_shader.cso)
1888 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1889 break;
1890 case PIPE_SHADER_TESS_EVAL:
1891 key->as_ngg = stages_key.u.ngg;
1892
1893 if (sctx->gs_shader.cso)
1894 key->as_es = 1;
1895 else {
1896 si_shader_selector_key_hw_vs(sctx, sel, key);
1897
1898 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1899 key->mono.u.vs_export_prim_id = 1;
1900 }
1901 break;
1902 case PIPE_SHADER_GEOMETRY:
1903 if (sctx->chip_class >= GFX9) {
1904 if (sctx->tes_shader.cso) {
1905 key->part.gs.es = sctx->tes_shader.cso;
1906 } else {
1907 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1908 key, &key->part.gs.vs_prolog);
1909 key->part.gs.es = sctx->vs_shader.cso;
1910 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1911 }
1912
1913 key->as_ngg = stages_key.u.ngg;
1914
1915 /* Merged ES-GS can have unbalanced wave usage.
1916 *
1917 * ES threads are per-vertex, while GS threads are
1918 * per-primitive. So without any amplification, there
1919 * are fewer GS threads than ES threads, which can result
1920 * in empty (no-op) GS waves. With too much amplification,
1921 * there are more GS threads than ES threads, which
1922 * can result in empty (no-op) ES waves.
1923 *
1924 * Non-monolithic shaders are implemented by setting EXEC
1925 * at the beginning of shader parts, and don't jump to
1926 * the end if EXEC is 0.
1927 *
1928 * Monolithic shaders use conditional blocks, so they can
1929 * jump and skip empty waves of ES or GS. So set this to
1930 * always use optimized variants, which are monolithic.
1931 */
1932 key->opt.prefer_mono = 1;
1933 }
1934 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1935 break;
1936 case PIPE_SHADER_FRAGMENT: {
1937 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1938 struct si_state_blend *blend = sctx->queued.named.blend;
1939
1940 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1941 sel->info.colors_written == 0x1)
1942 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1943
1944 /* Select the shader color format based on whether
1945 * blending or alpha are needed.
1946 */
1947 key->part.ps.epilog.spi_shader_col_format =
1948 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1949 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1950 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1951 sctx->framebuffer.spi_shader_col_format_blend) |
1952 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1953 sctx->framebuffer.spi_shader_col_format_alpha) |
1954 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1955 sctx->framebuffer.spi_shader_col_format);
1956 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1957
1958 /* The output for dual source blending should have
1959 * the same format as the first output.
1960 */
1961 if (blend->dual_src_blend) {
1962 key->part.ps.epilog.spi_shader_col_format |=
1963 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1964 }
1965
1966 /* If alpha-to-coverage is enabled, we have to export alpha
1967 * even if there is no color buffer.
1968 */
1969 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1970 blend->alpha_to_coverage)
1971 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1972
1973 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1974 * to the range supported by the type if a channel has less
1975 * than 16 bits and the export format is 16_ABGR.
1976 */
1977 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1978 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1979 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1980 }
1981
1982 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1983 if (!key->part.ps.epilog.last_cbuf) {
1984 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1985 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1986 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1987 }
1988
1989 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1990 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1991
1992 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1993 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1994
1995 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one &&
1996 rs->multisample_enable;
1997
1998 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1999 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
2000 (is_line && rs->line_smooth)) &&
2001 sctx->framebuffer.nr_samples <= 1;
2002 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
2003
2004 if (sctx->ps_iter_samples > 1 &&
2005 sel->info.reads_samplemask) {
2006 key->part.ps.prolog.samplemask_log_ps_iter =
2007 util_logbase2(sctx->ps_iter_samples);
2008 }
2009
2010 if (rs->force_persample_interp &&
2011 rs->multisample_enable &&
2012 sctx->framebuffer.nr_samples > 1 &&
2013 sctx->ps_iter_samples > 1) {
2014 key->part.ps.prolog.force_persp_sample_interp =
2015 sel->info.uses_persp_center ||
2016 sel->info.uses_persp_centroid;
2017
2018 key->part.ps.prolog.force_linear_sample_interp =
2019 sel->info.uses_linear_center ||
2020 sel->info.uses_linear_centroid;
2021 } else if (rs->multisample_enable &&
2022 sctx->framebuffer.nr_samples > 1) {
2023 key->part.ps.prolog.bc_optimize_for_persp =
2024 sel->info.uses_persp_center &&
2025 sel->info.uses_persp_centroid;
2026 key->part.ps.prolog.bc_optimize_for_linear =
2027 sel->info.uses_linear_center &&
2028 sel->info.uses_linear_centroid;
2029 } else {
2030 /* Make sure SPI doesn't compute more than 1 pair
2031 * of (i,j), which is the optimization here. */
2032 key->part.ps.prolog.force_persp_center_interp =
2033 sel->info.uses_persp_center +
2034 sel->info.uses_persp_centroid +
2035 sel->info.uses_persp_sample > 1;
2036
2037 key->part.ps.prolog.force_linear_center_interp =
2038 sel->info.uses_linear_center +
2039 sel->info.uses_linear_centroid +
2040 sel->info.uses_linear_sample > 1;
2041
2042 if (sel->info.uses_persp_opcode_interp_sample ||
2043 sel->info.uses_linear_opcode_interp_sample)
2044 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2045 }
2046
2047 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2048
2049 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2050 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2051 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2052 struct pipe_resource *tex = cb0->texture;
2053
2054 /* 1D textures are allocated and used as 2D on GFX9. */
2055 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2056 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2057 (tex->target == PIPE_TEXTURE_1D ||
2058 tex->target == PIPE_TEXTURE_1D_ARRAY);
2059 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2060 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2061 tex->target == PIPE_TEXTURE_CUBE ||
2062 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2063 tex->target == PIPE_TEXTURE_3D;
2064 }
2065 break;
2066 }
2067 default:
2068 assert(0);
2069 }
2070
2071 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2072 memset(&key->opt, 0, sizeof(key->opt));
2073 }
2074
2075 static void si_build_shader_variant(struct si_shader *shader,
2076 int thread_index,
2077 bool low_priority)
2078 {
2079 struct si_shader_selector *sel = shader->selector;
2080 struct si_screen *sscreen = sel->screen;
2081 struct ac_llvm_compiler *compiler;
2082 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2083
2084 if (thread_index >= 0) {
2085 if (low_priority) {
2086 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2087 compiler = &sscreen->compiler_lowp[thread_index];
2088 } else {
2089 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2090 compiler = &sscreen->compiler[thread_index];
2091 }
2092 if (!debug->async)
2093 debug = NULL;
2094 } else {
2095 assert(!low_priority);
2096 compiler = shader->compiler_ctx_state.compiler;
2097 }
2098
2099 if (!compiler->passes)
2100 si_init_compiler(sscreen, compiler);
2101
2102 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
2103 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2104 sel->type);
2105 shader->compilation_failed = true;
2106 return;
2107 }
2108
2109 if (shader->compiler_ctx_state.is_debug_context) {
2110 FILE *f = open_memstream(&shader->shader_log,
2111 &shader->shader_log_size);
2112 if (f) {
2113 si_shader_dump(sscreen, shader, NULL, f, false);
2114 fclose(f);
2115 }
2116 }
2117
2118 si_shader_init_pm4_state(sscreen, shader);
2119 }
2120
2121 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2122 {
2123 struct si_shader *shader = (struct si_shader *)job;
2124
2125 assert(thread_index >= 0);
2126
2127 si_build_shader_variant(shader, thread_index, true);
2128 }
2129
2130 static const struct si_shader_key zeroed;
2131
2132 static bool si_check_missing_main_part(struct si_screen *sscreen,
2133 struct si_shader_selector *sel,
2134 struct si_compiler_ctx_state *compiler_state,
2135 struct si_shader_key *key)
2136 {
2137 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2138
2139 if (!*mainp) {
2140 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2141
2142 if (!main_part)
2143 return false;
2144
2145 /* We can leave the fence as permanently signaled because the
2146 * main part becomes visible globally only after it has been
2147 * compiled. */
2148 util_queue_fence_init(&main_part->ready);
2149
2150 main_part->selector = sel;
2151 main_part->key.as_es = key->as_es;
2152 main_part->key.as_ls = key->as_ls;
2153 main_part->key.as_ngg = key->as_ngg;
2154 main_part->is_monolithic = false;
2155
2156 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
2157 main_part, &compiler_state->debug) != 0) {
2158 FREE(main_part);
2159 return false;
2160 }
2161 *mainp = main_part;
2162 }
2163 return true;
2164 }
2165
2166 /**
2167 * Select a shader variant according to the shader key.
2168 *
2169 * \param optimized_or_none If the key describes an optimized shader variant and
2170 * the compilation isn't finished, don't select any
2171 * shader and return an error.
2172 */
2173 int si_shader_select_with_key(struct si_screen *sscreen,
2174 struct si_shader_ctx_state *state,
2175 struct si_compiler_ctx_state *compiler_state,
2176 struct si_shader_key *key,
2177 int thread_index,
2178 bool optimized_or_none)
2179 {
2180 struct si_shader_selector *sel = state->cso;
2181 struct si_shader_selector *previous_stage_sel = NULL;
2182 struct si_shader *current = state->current;
2183 struct si_shader *iter, *shader = NULL;
2184
2185 again:
2186 /* Check if we don't need to change anything.
2187 * This path is also used for most shaders that don't need multiple
2188 * variants, it will cost just a computation of the key and this
2189 * test. */
2190 if (likely(current &&
2191 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2192 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2193 if (current->is_optimized) {
2194 if (optimized_or_none)
2195 return -1;
2196
2197 memset(&key->opt, 0, sizeof(key->opt));
2198 goto current_not_ready;
2199 }
2200
2201 util_queue_fence_wait(&current->ready);
2202 }
2203
2204 return current->compilation_failed ? -1 : 0;
2205 }
2206 current_not_ready:
2207
2208 /* This must be done before the mutex is locked, because async GS
2209 * compilation calls this function too, and therefore must enter
2210 * the mutex first.
2211 *
2212 * Only wait if we are in a draw call. Don't wait if we are
2213 * in a compiler thread.
2214 */
2215 if (thread_index < 0)
2216 util_queue_fence_wait(&sel->ready);
2217
2218 simple_mtx_lock(&sel->mutex);
2219
2220 /* Find the shader variant. */
2221 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2222 /* Don't check the "current" shader. We checked it above. */
2223 if (current != iter &&
2224 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2225 simple_mtx_unlock(&sel->mutex);
2226
2227 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2228 /* If it's an optimized shader and its compilation has
2229 * been started but isn't done, use the unoptimized
2230 * shader so as not to cause a stall due to compilation.
2231 */
2232 if (iter->is_optimized) {
2233 if (optimized_or_none)
2234 return -1;
2235 memset(&key->opt, 0, sizeof(key->opt));
2236 goto again;
2237 }
2238
2239 util_queue_fence_wait(&iter->ready);
2240 }
2241
2242 if (iter->compilation_failed) {
2243 return -1; /* skip the draw call */
2244 }
2245
2246 state->current = iter;
2247 return 0;
2248 }
2249 }
2250
2251 /* Build a new shader. */
2252 shader = CALLOC_STRUCT(si_shader);
2253 if (!shader) {
2254 simple_mtx_unlock(&sel->mutex);
2255 return -ENOMEM;
2256 }
2257
2258 util_queue_fence_init(&shader->ready);
2259
2260 shader->selector = sel;
2261 shader->key = *key;
2262 shader->compiler_ctx_state = *compiler_state;
2263
2264 /* If this is a merged shader, get the first shader's selector. */
2265 if (sscreen->info.chip_class >= GFX9) {
2266 if (sel->type == PIPE_SHADER_TESS_CTRL)
2267 previous_stage_sel = key->part.tcs.ls;
2268 else if (sel->type == PIPE_SHADER_GEOMETRY)
2269 previous_stage_sel = key->part.gs.es;
2270
2271 /* We need to wait for the previous shader. */
2272 if (previous_stage_sel && thread_index < 0)
2273 util_queue_fence_wait(&previous_stage_sel->ready);
2274 }
2275
2276 bool is_pure_monolithic =
2277 sscreen->use_monolithic_shaders ||
2278 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2279
2280 /* Compile the main shader part if it doesn't exist. This can happen
2281 * if the initial guess was wrong.
2282 *
2283 * The prim discard CS doesn't need the main shader part.
2284 */
2285 if (!is_pure_monolithic &&
2286 !key->opt.vs_as_prim_discard_cs) {
2287 bool ok = true;
2288
2289 /* Make sure the main shader part is present. This is needed
2290 * for shaders that can be compiled as VS, LS, or ES, and only
2291 * one of them is compiled at creation.
2292 *
2293 * It is also needed for GS, which can be compiled as non-NGG
2294 * and NGG.
2295 *
2296 * For merged shaders, check that the starting shader's main
2297 * part is present.
2298 */
2299 if (previous_stage_sel) {
2300 struct si_shader_key shader1_key = zeroed;
2301
2302 if (sel->type == PIPE_SHADER_TESS_CTRL) {
2303 shader1_key.as_ls = 1;
2304 } else if (sel->type == PIPE_SHADER_GEOMETRY) {
2305 shader1_key.as_es = 1;
2306 shader1_key.as_ngg = key->as_ngg; /* for Wave32 vs Wave64 */
2307 } else {
2308 assert(0);
2309 }
2310
2311 simple_mtx_lock(&previous_stage_sel->mutex);
2312 ok = si_check_missing_main_part(sscreen,
2313 previous_stage_sel,
2314 compiler_state, &shader1_key);
2315 simple_mtx_unlock(&previous_stage_sel->mutex);
2316 }
2317
2318 if (ok) {
2319 ok = si_check_missing_main_part(sscreen, sel,
2320 compiler_state, key);
2321 }
2322
2323 if (!ok) {
2324 FREE(shader);
2325 simple_mtx_unlock(&sel->mutex);
2326 return -ENOMEM; /* skip the draw call */
2327 }
2328 }
2329
2330 /* Keep the reference to the 1st shader of merged shaders, so that
2331 * Gallium can't destroy it before we destroy the 2nd shader.
2332 *
2333 * Set sctx = NULL, because it's unused if we're not releasing
2334 * the shader, and we don't have any sctx here.
2335 */
2336 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2337 previous_stage_sel);
2338
2339 /* Monolithic-only shaders don't make a distinction between optimized
2340 * and unoptimized. */
2341 shader->is_monolithic =
2342 is_pure_monolithic ||
2343 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2344
2345 /* The prim discard CS is always optimized. */
2346 shader->is_optimized =
2347 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2348 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2349
2350 /* If it's an optimized shader, compile it asynchronously. */
2351 if (shader->is_optimized && thread_index < 0) {
2352 /* Compile it asynchronously. */
2353 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2354 shader, &shader->ready,
2355 si_build_shader_variant_low_priority, NULL,
2356 0);
2357
2358 /* Add only after the ready fence was reset, to guard against a
2359 * race with si_bind_XX_shader. */
2360 if (!sel->last_variant) {
2361 sel->first_variant = shader;
2362 sel->last_variant = shader;
2363 } else {
2364 sel->last_variant->next_variant = shader;
2365 sel->last_variant = shader;
2366 }
2367
2368 /* Use the default (unoptimized) shader for now. */
2369 memset(&key->opt, 0, sizeof(key->opt));
2370 simple_mtx_unlock(&sel->mutex);
2371
2372 if (sscreen->options.sync_compile)
2373 util_queue_fence_wait(&shader->ready);
2374
2375 if (optimized_or_none)
2376 return -1;
2377 goto again;
2378 }
2379
2380 /* Reset the fence before adding to the variant list. */
2381 util_queue_fence_reset(&shader->ready);
2382
2383 if (!sel->last_variant) {
2384 sel->first_variant = shader;
2385 sel->last_variant = shader;
2386 } else {
2387 sel->last_variant->next_variant = shader;
2388 sel->last_variant = shader;
2389 }
2390
2391 simple_mtx_unlock(&sel->mutex);
2392
2393 assert(!shader->is_optimized);
2394 si_build_shader_variant(shader, thread_index, false);
2395
2396 util_queue_fence_signal(&shader->ready);
2397
2398 if (!shader->compilation_failed)
2399 state->current = shader;
2400
2401 return shader->compilation_failed ? -1 : 0;
2402 }
2403
2404 static int si_shader_select(struct pipe_context *ctx,
2405 struct si_shader_ctx_state *state,
2406 union si_vgt_stages_key stages_key,
2407 struct si_compiler_ctx_state *compiler_state)
2408 {
2409 struct si_context *sctx = (struct si_context *)ctx;
2410 struct si_shader_key key;
2411
2412 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2413 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2414 &key, -1, false);
2415 }
2416
2417 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2418 bool streamout,
2419 struct si_shader_key *key)
2420 {
2421 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2422
2423 switch (info->processor) {
2424 case PIPE_SHADER_VERTEX:
2425 switch (next_shader) {
2426 case PIPE_SHADER_GEOMETRY:
2427 key->as_es = 1;
2428 break;
2429 case PIPE_SHADER_TESS_CTRL:
2430 case PIPE_SHADER_TESS_EVAL:
2431 key->as_ls = 1;
2432 break;
2433 default:
2434 /* If POSITION isn't written, it can only be a HW VS
2435 * if streamout is used. If streamout isn't used,
2436 * assume that it's a HW LS. (the next shader is TCS)
2437 * This heuristic is needed for separate shader objects.
2438 */
2439 if (!info->writes_position && !streamout)
2440 key->as_ls = 1;
2441 }
2442 break;
2443
2444 case PIPE_SHADER_TESS_EVAL:
2445 if (next_shader == PIPE_SHADER_GEOMETRY ||
2446 !info->writes_position)
2447 key->as_es = 1;
2448 break;
2449 }
2450 }
2451
2452 /**
2453 * Compile the main shader part or the monolithic shader as part of
2454 * si_shader_selector initialization. Since it can be done asynchronously,
2455 * there is no way to report compile failures to applications.
2456 */
2457 static void si_init_shader_selector_async(void *job, int thread_index)
2458 {
2459 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2460 struct si_screen *sscreen = sel->screen;
2461 struct ac_llvm_compiler *compiler;
2462 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2463
2464 assert(!debug->debug_message || debug->async);
2465 assert(thread_index >= 0);
2466 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2467 compiler = &sscreen->compiler[thread_index];
2468
2469 if (!compiler->passes)
2470 si_init_compiler(sscreen, compiler);
2471
2472 /* Serialize NIR to save memory. Monolithic shader variants
2473 * have to deserialize NIR before compilation.
2474 */
2475 if (sel->nir) {
2476 struct blob blob;
2477 size_t size;
2478
2479 blob_init(&blob);
2480 /* true = remove optional debugging data to increase
2481 * the likehood of getting more shader cache hits.
2482 * It also drops variable names, so we'll save more memory.
2483 */
2484 nir_serialize(&blob, sel->nir, true);
2485 blob_finish_get_buffer(&blob, &sel->nir_binary, &size);
2486 sel->nir_size = size;
2487 }
2488
2489 /* Compile the main shader part for use with a prolog and/or epilog.
2490 * If this fails, the driver will try to compile a monolithic shader
2491 * on demand.
2492 */
2493 if (!sscreen->use_monolithic_shaders) {
2494 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2495 unsigned char ir_sha1_cache_key[20];
2496
2497 if (!shader) {
2498 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2499 return;
2500 }
2501
2502 /* We can leave the fence signaled because use of the default
2503 * main part is guarded by the selector's ready fence. */
2504 util_queue_fence_init(&shader->ready);
2505
2506 shader->selector = sel;
2507 shader->is_monolithic = false;
2508 si_parse_next_shader_property(&sel->info,
2509 sel->so.num_outputs != 0,
2510 &shader->key);
2511
2512 if (sscreen->use_ngg &&
2513 (!sel->so.num_outputs || sscreen->use_ngg_streamout) &&
2514 ((sel->type == PIPE_SHADER_VERTEX && !shader->key.as_ls) ||
2515 sel->type == PIPE_SHADER_TESS_EVAL ||
2516 sel->type == PIPE_SHADER_GEOMETRY))
2517 shader->key.as_ngg = 1;
2518
2519 if (sel->tokens || sel->nir) {
2520 si_get_ir_cache_key(sel, shader->key.as_ngg,
2521 shader->key.as_es, ir_sha1_cache_key);
2522 }
2523
2524 /* Try to load the shader from the shader cache. */
2525 simple_mtx_lock(&sscreen->shader_cache_mutex);
2526
2527 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
2528 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2529 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2530 } else {
2531 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2532
2533 /* Compile the shader if it hasn't been loaded from the cache. */
2534 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2535 debug) != 0) {
2536 FREE(shader);
2537 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2538 return;
2539 }
2540
2541 simple_mtx_lock(&sscreen->shader_cache_mutex);
2542 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
2543 shader, true);
2544 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2545 }
2546
2547 *si_get_main_shader_part(sel, &shader->key) = shader;
2548
2549 /* Unset "outputs_written" flags for outputs converted to
2550 * DEFAULT_VAL, so that later inter-shader optimizations don't
2551 * try to eliminate outputs that don't exist in the final
2552 * shader.
2553 *
2554 * This is only done if non-monolithic shaders are enabled.
2555 */
2556 if ((sel->type == PIPE_SHADER_VERTEX ||
2557 sel->type == PIPE_SHADER_TESS_EVAL) &&
2558 !shader->key.as_ls &&
2559 !shader->key.as_es) {
2560 unsigned i;
2561
2562 for (i = 0; i < sel->info.num_outputs; i++) {
2563 unsigned offset = shader->info.vs_output_param_offset[i];
2564
2565 if (offset <= AC_EXP_PARAM_OFFSET_31)
2566 continue;
2567
2568 unsigned name = sel->info.output_semantic_name[i];
2569 unsigned index = sel->info.output_semantic_index[i];
2570 unsigned id;
2571
2572 switch (name) {
2573 case TGSI_SEMANTIC_GENERIC:
2574 /* don't process indices the function can't handle */
2575 if (index >= SI_MAX_IO_GENERIC)
2576 break;
2577 /* fall through */
2578 default:
2579 id = si_shader_io_get_unique_index(name, index, true);
2580 sel->outputs_written_before_ps &= ~(1ull << id);
2581 break;
2582 case TGSI_SEMANTIC_POSITION: /* ignore these */
2583 case TGSI_SEMANTIC_PSIZE:
2584 case TGSI_SEMANTIC_CLIPVERTEX:
2585 case TGSI_SEMANTIC_EDGEFLAG:
2586 break;
2587 }
2588 }
2589 }
2590 }
2591
2592 /* The GS copy shader is always pre-compiled. */
2593 if (sel->type == PIPE_SHADER_GEOMETRY &&
2594 (!sscreen->use_ngg ||
2595 !sscreen->use_ngg_streamout || /* also for PRIMITIVES_GENERATED */
2596 sel->tess_turns_off_ngg)) {
2597 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2598 if (!sel->gs_copy_shader) {
2599 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2600 return;
2601 }
2602
2603 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2604 }
2605
2606 /* Free NIR. We only keep serialized NIR after this point. */
2607 if (sel->nir) {
2608 ralloc_free(sel->nir);
2609 sel->nir = NULL;
2610 }
2611 }
2612
2613 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2614 struct util_queue_fence *ready_fence,
2615 struct si_compiler_ctx_state *compiler_ctx_state,
2616 void *job, util_queue_execute_func execute)
2617 {
2618 util_queue_fence_init(ready_fence);
2619
2620 struct util_async_debug_callback async_debug;
2621 bool debug =
2622 (sctx->debug.debug_message && !sctx->debug.async) ||
2623 sctx->is_debug ||
2624 si_can_dump_shader(sctx->screen, processor);
2625
2626 if (debug) {
2627 u_async_debug_init(&async_debug);
2628 compiler_ctx_state->debug = async_debug.base;
2629 }
2630
2631 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2632 ready_fence, execute, NULL, 0);
2633
2634 if (debug) {
2635 util_queue_fence_wait(ready_fence);
2636 u_async_debug_drain(&async_debug, &sctx->debug);
2637 u_async_debug_cleanup(&async_debug);
2638 }
2639
2640 if (sctx->screen->options.sync_compile)
2641 util_queue_fence_wait(ready_fence);
2642 }
2643
2644 /* Return descriptor slot usage masks from the given shader info. */
2645 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2646 uint32_t *const_and_shader_buffers,
2647 uint64_t *samplers_and_images)
2648 {
2649 unsigned start, num_shaderbufs, num_constbufs, num_images, num_msaa_images, num_samplers;
2650
2651 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2652 num_constbufs = util_last_bit(info->const_buffers_declared);
2653 /* two 8-byte images share one 16-byte slot */
2654 num_images = align(util_last_bit(info->images_declared), 2);
2655 num_msaa_images = align(util_last_bit(info->msaa_images_declared), 2);
2656 num_samplers = util_last_bit(info->samplers_declared);
2657
2658 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2659 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2660 *const_and_shader_buffers =
2661 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2662
2663 /* The layout is:
2664 * - fmask[last] ... fmask[0] go to [15-last .. 15]
2665 * - image[last] ... image[0] go to [31-last .. 31]
2666 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
2667 *
2668 * FMASKs for images are placed separately, because MSAA images are rare,
2669 * and so we can benefit from a better cache hit rate if we keep image
2670 * descriptors together.
2671 */
2672 if (num_msaa_images)
2673 num_images = SI_NUM_IMAGES + num_msaa_images; /* add FMASK descriptors */
2674
2675 start = si_get_image_slot(num_images - 1) / 2;
2676 *samplers_and_images =
2677 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2678 }
2679
2680 static void *si_create_shader_selector(struct pipe_context *ctx,
2681 const struct pipe_shader_state *state)
2682 {
2683 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2684 struct si_context *sctx = (struct si_context*)ctx;
2685 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2686 int i;
2687
2688 if (!sel)
2689 return NULL;
2690
2691 pipe_reference_init(&sel->reference, 1);
2692 sel->screen = sscreen;
2693 sel->compiler_ctx_state.debug = sctx->debug;
2694 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2695
2696 sel->so = state->stream_output;
2697
2698 if (state->type == PIPE_SHADER_IR_TGSI &&
2699 !sscreen->options.enable_nir) {
2700 sel->tokens = tgsi_dup_tokens(state->tokens);
2701 if (!sel->tokens) {
2702 FREE(sel);
2703 return NULL;
2704 }
2705
2706 tgsi_scan_shader(state->tokens, &sel->info);
2707 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2708
2709 /* Fixup for TGSI: Set which opcode uses which (i,j) pair. */
2710 if (sel->info.uses_persp_opcode_interp_centroid)
2711 sel->info.uses_persp_centroid = true;
2712
2713 if (sel->info.uses_linear_opcode_interp_centroid)
2714 sel->info.uses_linear_centroid = true;
2715
2716 if (sel->info.uses_persp_opcode_interp_offset ||
2717 sel->info.uses_persp_opcode_interp_sample)
2718 sel->info.uses_persp_center = true;
2719
2720 if (sel->info.uses_linear_opcode_interp_offset ||
2721 sel->info.uses_linear_opcode_interp_sample)
2722 sel->info.uses_linear_center = true;
2723 } else {
2724 if (state->type == PIPE_SHADER_IR_TGSI) {
2725 sel->nir = tgsi_to_nir(state->tokens, ctx->screen);
2726 } else {
2727 assert(state->type == PIPE_SHADER_IR_NIR);
2728 sel->nir = state->ir.nir;
2729 }
2730
2731 si_nir_scan_shader(sel->nir, &sel->info);
2732 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2733 si_nir_adjust_driver_locations(sel->nir);
2734 }
2735
2736 sel->type = sel->info.processor;
2737 p_atomic_inc(&sscreen->num_shaders_created);
2738 si_get_active_slot_masks(&sel->info,
2739 &sel->active_const_and_shader_buffers,
2740 &sel->active_samplers_and_images);
2741
2742 /* Record which streamout buffers are enabled. */
2743 for (i = 0; i < sel->so.num_outputs; i++) {
2744 sel->enabled_streamout_buffer_mask |=
2745 (1 << sel->so.output[i].output_buffer) <<
2746 (sel->so.output[i].stream * 4);
2747 }
2748
2749 /* The prolog is a no-op if there are no inputs. */
2750 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2751 sel->info.num_inputs &&
2752 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
2753
2754 sel->force_correct_derivs_after_kill =
2755 sel->type == PIPE_SHADER_FRAGMENT &&
2756 sel->info.uses_derivatives &&
2757 sel->info.uses_kill &&
2758 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2759
2760 sel->prim_discard_cs_allowed =
2761 sel->type == PIPE_SHADER_VERTEX &&
2762 !sel->info.uses_bindless_images &&
2763 !sel->info.uses_bindless_samplers &&
2764 !sel->info.writes_memory &&
2765 !sel->info.writes_viewport_index &&
2766 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2767 !sel->so.num_outputs;
2768
2769 switch (sel->type) {
2770 case PIPE_SHADER_GEOMETRY:
2771 sel->gs_output_prim =
2772 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2773
2774 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2775 sel->rast_prim = sel->gs_output_prim;
2776 if (util_rast_prim_is_triangles(sel->rast_prim))
2777 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2778
2779 sel->gs_max_out_vertices =
2780 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2781 sel->gs_num_invocations =
2782 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2783 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2784 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2785 sel->gs_max_out_vertices;
2786
2787 sel->max_gs_stream = 0;
2788 for (i = 0; i < sel->so.num_outputs; i++)
2789 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2790 sel->so.output[i].stream);
2791
2792 sel->gs_input_verts_per_prim =
2793 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2794
2795 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2796 sel->tess_turns_off_ngg =
2797 sscreen->info.chip_class == GFX10 &&
2798 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2799 break;
2800
2801 case PIPE_SHADER_TESS_CTRL:
2802 /* Always reserve space for these. */
2803 sel->patch_outputs_written |=
2804 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2805 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2806 /* fall through */
2807 case PIPE_SHADER_VERTEX:
2808 case PIPE_SHADER_TESS_EVAL:
2809 for (i = 0; i < sel->info.num_outputs; i++) {
2810 unsigned name = sel->info.output_semantic_name[i];
2811 unsigned index = sel->info.output_semantic_index[i];
2812
2813 switch (name) {
2814 case TGSI_SEMANTIC_TESSINNER:
2815 case TGSI_SEMANTIC_TESSOUTER:
2816 case TGSI_SEMANTIC_PATCH:
2817 sel->patch_outputs_written |=
2818 1ull << si_shader_io_get_unique_index_patch(name, index);
2819 break;
2820
2821 case TGSI_SEMANTIC_GENERIC:
2822 /* don't process indices the function can't handle */
2823 if (index >= SI_MAX_IO_GENERIC)
2824 break;
2825 /* fall through */
2826 default:
2827 sel->outputs_written |=
2828 1ull << si_shader_io_get_unique_index(name, index, false);
2829 sel->outputs_written_before_ps |=
2830 1ull << si_shader_io_get_unique_index(name, index, true);
2831 break;
2832 case TGSI_SEMANTIC_EDGEFLAG:
2833 break;
2834 }
2835 }
2836 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2837 sel->lshs_vertex_stride = sel->esgs_itemsize;
2838
2839 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2840 * will start on a different bank. (except for the maximum 32*16).
2841 */
2842 if (sel->lshs_vertex_stride < 32*16)
2843 sel->lshs_vertex_stride += 4;
2844
2845 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2846 * conflicts, i.e. each vertex will start at a different bank.
2847 */
2848 if (sctx->chip_class >= GFX9)
2849 sel->esgs_itemsize += 4;
2850
2851 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2852
2853 /* Only for TES: */
2854 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2855 sel->rast_prim = PIPE_PRIM_POINTS;
2856 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2857 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2858 else
2859 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2860 break;
2861
2862 case PIPE_SHADER_FRAGMENT:
2863 for (i = 0; i < sel->info.num_inputs; i++) {
2864 unsigned name = sel->info.input_semantic_name[i];
2865 unsigned index = sel->info.input_semantic_index[i];
2866
2867 switch (name) {
2868 case TGSI_SEMANTIC_GENERIC:
2869 /* don't process indices the function can't handle */
2870 if (index >= SI_MAX_IO_GENERIC)
2871 break;
2872 /* fall through */
2873 default:
2874 sel->inputs_read |=
2875 1ull << si_shader_io_get_unique_index(name, index, true);
2876 break;
2877 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2878 break;
2879 }
2880 }
2881
2882 for (i = 0; i < 8; i++)
2883 if (sel->info.colors_written & (1 << i))
2884 sel->colors_written_4bit |= 0xf << (4 * i);
2885
2886 for (i = 0; i < sel->info.num_inputs; i++) {
2887 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2888 int index = sel->info.input_semantic_index[i];
2889 sel->color_attr_index[index] = i;
2890 }
2891 }
2892 break;
2893 default:;
2894 }
2895
2896 /* PA_CL_VS_OUT_CNTL */
2897 if (sctx->chip_class <= GFX9)
2898 sel->pa_cl_vs_out_cntl = si_get_vs_out_cntl(sel, false);
2899
2900 sel->clipdist_mask = sel->info.writes_clipvertex ?
2901 SIX_BITS : sel->info.clipdist_writemask;
2902 sel->culldist_mask = sel->info.culldist_writemask <<
2903 sel->info.num_written_clipdistance;
2904
2905 /* DB_SHADER_CONTROL */
2906 sel->db_shader_control =
2907 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2908 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2909 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2910 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2911
2912 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2913 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2914 sel->db_shader_control |=
2915 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2916 break;
2917 case TGSI_FS_DEPTH_LAYOUT_LESS:
2918 sel->db_shader_control |=
2919 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2920 break;
2921 }
2922
2923 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2924 *
2925 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2926 * --|-----------|------------|------------|--------------------|-------------------|-------------
2927 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2928 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2929 * 2 | false | true | n/a | LateZ | 1 | 0
2930 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2931 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2932 *
2933 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2934 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2935 *
2936 * Don't use ReZ without profiling !!!
2937 *
2938 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2939 * shaders.
2940 */
2941 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2942 /* Cases 3, 4. */
2943 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2944 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2945 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2946 } else if (sel->info.writes_memory) {
2947 /* Case 2. */
2948 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2949 S_02880C_EXEC_ON_HIER_FAIL(1);
2950 } else {
2951 /* Case 1. */
2952 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2953 }
2954
2955 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
2956 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2957
2958 (void) simple_mtx_init(&sel->mutex, mtx_plain);
2959
2960 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2961 &sel->compiler_ctx_state, sel,
2962 si_init_shader_selector_async);
2963 return sel;
2964 }
2965
2966 static void si_update_streamout_state(struct si_context *sctx)
2967 {
2968 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2969
2970 if (!shader_with_so)
2971 return;
2972
2973 sctx->streamout.enabled_stream_buffers_mask =
2974 shader_with_so->enabled_streamout_buffer_mask;
2975 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2976 }
2977
2978 static void si_update_clip_regs(struct si_context *sctx,
2979 struct si_shader_selector *old_hw_vs,
2980 struct si_shader *old_hw_vs_variant,
2981 struct si_shader_selector *next_hw_vs,
2982 struct si_shader *next_hw_vs_variant)
2983 {
2984 if (next_hw_vs &&
2985 (!old_hw_vs ||
2986 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2987 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2988 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2989 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2990 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2991 !old_hw_vs_variant ||
2992 !next_hw_vs_variant ||
2993 old_hw_vs_variant->key.opt.clip_disable !=
2994 next_hw_vs_variant->key.opt.clip_disable))
2995 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2996 }
2997
2998 static void si_update_common_shader_state(struct si_context *sctx)
2999 {
3000 sctx->uses_bindless_samplers =
3001 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
3002 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
3003 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
3004 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
3005 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
3006 sctx->uses_bindless_images =
3007 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
3008 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
3009 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
3010 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
3011 si_shader_uses_bindless_images(sctx->tes_shader.cso);
3012 sctx->do_update_shaders = true;
3013 }
3014
3015 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
3016 {
3017 struct si_context *sctx = (struct si_context *)ctx;
3018 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3019 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3020 struct si_shader_selector *sel = state;
3021
3022 if (sctx->vs_shader.cso == sel)
3023 return;
3024
3025 sctx->vs_shader.cso = sel;
3026 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
3027 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] : 0;
3028
3029 if (si_update_ngg(sctx))
3030 si_shader_change_notify(sctx);
3031
3032 si_update_common_shader_state(sctx);
3033 si_update_vs_viewport_state(sctx);
3034 si_set_active_descriptors_for_shader(sctx, sel);
3035 si_update_streamout_state(sctx);
3036 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3037 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3038 }
3039
3040 static void si_update_tess_uses_prim_id(struct si_context *sctx)
3041 {
3042 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
3043 (sctx->tes_shader.cso &&
3044 sctx->tes_shader.cso->info.uses_primid) ||
3045 (sctx->tcs_shader.cso &&
3046 sctx->tcs_shader.cso->info.uses_primid) ||
3047 (sctx->gs_shader.cso &&
3048 sctx->gs_shader.cso->info.uses_primid) ||
3049 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
3050 sctx->ps_shader.cso->info.uses_primid);
3051 }
3052
3053 bool si_update_ngg(struct si_context *sctx)
3054 {
3055 if (!sctx->screen->use_ngg) {
3056 assert(!sctx->ngg);
3057 return false;
3058 }
3059
3060 bool new_ngg = true;
3061
3062 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
3063 sctx->gs_shader.cso->tess_turns_off_ngg) {
3064 new_ngg = false;
3065 } else if (!sctx->screen->use_ngg_streamout) {
3066 struct si_shader_selector *last = si_get_vs(sctx)->cso;
3067
3068 if ((last && last->so.num_outputs) ||
3069 sctx->streamout.prims_gen_query_enabled)
3070 new_ngg = false;
3071 }
3072
3073 if (new_ngg != sctx->ngg) {
3074 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3075 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3076 * pointers are set.
3077 */
3078 if ((sctx->family == CHIP_NAVI10 ||
3079 sctx->family == CHIP_NAVI12 ||
3080 sctx->family == CHIP_NAVI14) &&
3081 !new_ngg)
3082 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
3083
3084 sctx->ngg = new_ngg;
3085 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3086 return true;
3087 }
3088 return false;
3089 }
3090
3091 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3092 {
3093 struct si_context *sctx = (struct si_context *)ctx;
3094 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3095 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3096 struct si_shader_selector *sel = state;
3097 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3098 bool ngg_changed;
3099
3100 if (sctx->gs_shader.cso == sel)
3101 return;
3102
3103 sctx->gs_shader.cso = sel;
3104 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3105 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3106
3107 si_update_common_shader_state(sctx);
3108 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3109
3110 ngg_changed = si_update_ngg(sctx);
3111 if (ngg_changed || enable_changed)
3112 si_shader_change_notify(sctx);
3113 if (enable_changed) {
3114 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3115 si_update_tess_uses_prim_id(sctx);
3116 }
3117 si_update_vs_viewport_state(sctx);
3118 si_set_active_descriptors_for_shader(sctx, sel);
3119 si_update_streamout_state(sctx);
3120 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3121 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3122 }
3123
3124 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3125 {
3126 struct si_context *sctx = (struct si_context *)ctx;
3127 struct si_shader_selector *sel = state;
3128 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3129
3130 if (sctx->tcs_shader.cso == sel)
3131 return;
3132
3133 sctx->tcs_shader.cso = sel;
3134 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3135 si_update_tess_uses_prim_id(sctx);
3136
3137 si_update_common_shader_state(sctx);
3138
3139 if (enable_changed)
3140 sctx->last_tcs = NULL; /* invalidate derived tess state */
3141
3142 si_set_active_descriptors_for_shader(sctx, sel);
3143 }
3144
3145 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3146 {
3147 struct si_context *sctx = (struct si_context *)ctx;
3148 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3149 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3150 struct si_shader_selector *sel = state;
3151 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3152
3153 if (sctx->tes_shader.cso == sel)
3154 return;
3155
3156 sctx->tes_shader.cso = sel;
3157 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3158 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3159 si_update_tess_uses_prim_id(sctx);
3160
3161 si_update_common_shader_state(sctx);
3162 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3163
3164 bool ngg_changed = si_update_ngg(sctx);
3165 if (ngg_changed || enable_changed)
3166 si_shader_change_notify(sctx);
3167 if (enable_changed)
3168 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3169 si_update_vs_viewport_state(sctx);
3170 si_set_active_descriptors_for_shader(sctx, sel);
3171 si_update_streamout_state(sctx);
3172 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3173 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3174 }
3175
3176 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3177 {
3178 struct si_context *sctx = (struct si_context *)ctx;
3179 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3180 struct si_shader_selector *sel = state;
3181
3182 /* skip if supplied shader is one already in use */
3183 if (old_sel == sel)
3184 return;
3185
3186 sctx->ps_shader.cso = sel;
3187 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3188
3189 si_update_common_shader_state(sctx);
3190 if (sel) {
3191 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3192 si_update_tess_uses_prim_id(sctx);
3193
3194 if (!old_sel ||
3195 old_sel->info.colors_written != sel->info.colors_written)
3196 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3197
3198 if (sctx->screen->has_out_of_order_rast &&
3199 (!old_sel ||
3200 old_sel->info.writes_memory != sel->info.writes_memory ||
3201 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3202 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3203 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3204 }
3205 si_set_active_descriptors_for_shader(sctx, sel);
3206 si_update_ps_colorbuf0_slot(sctx);
3207 }
3208
3209 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3210 {
3211 if (shader->is_optimized) {
3212 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3213 &shader->ready);
3214 }
3215
3216 util_queue_fence_destroy(&shader->ready);
3217
3218 if (shader->pm4) {
3219 /* If destroyed shaders were not unbound, the next compiled
3220 * shader variant could get the same pointer address and so
3221 * binding it to the same shader stage would be considered
3222 * a no-op, causing random behavior.
3223 */
3224 switch (shader->selector->type) {
3225 case PIPE_SHADER_VERTEX:
3226 if (shader->key.as_ls) {
3227 assert(sctx->chip_class <= GFX8);
3228 si_pm4_delete_state(sctx, ls, shader->pm4);
3229 } else if (shader->key.as_es) {
3230 assert(sctx->chip_class <= GFX8);
3231 si_pm4_delete_state(sctx, es, shader->pm4);
3232 } else if (shader->key.as_ngg) {
3233 si_pm4_delete_state(sctx, gs, shader->pm4);
3234 } else {
3235 si_pm4_delete_state(sctx, vs, shader->pm4);
3236 }
3237 break;
3238 case PIPE_SHADER_TESS_CTRL:
3239 si_pm4_delete_state(sctx, hs, shader->pm4);
3240 break;
3241 case PIPE_SHADER_TESS_EVAL:
3242 if (shader->key.as_es) {
3243 assert(sctx->chip_class <= GFX8);
3244 si_pm4_delete_state(sctx, es, shader->pm4);
3245 } else if (shader->key.as_ngg) {
3246 si_pm4_delete_state(sctx, gs, shader->pm4);
3247 } else {
3248 si_pm4_delete_state(sctx, vs, shader->pm4);
3249 }
3250 break;
3251 case PIPE_SHADER_GEOMETRY:
3252 if (shader->is_gs_copy_shader)
3253 si_pm4_delete_state(sctx, vs, shader->pm4);
3254 else
3255 si_pm4_delete_state(sctx, gs, shader->pm4);
3256 break;
3257 case PIPE_SHADER_FRAGMENT:
3258 si_pm4_delete_state(sctx, ps, shader->pm4);
3259 break;
3260 default:;
3261 }
3262 }
3263
3264 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3265 si_shader_destroy(shader);
3266 free(shader);
3267 }
3268
3269 void si_destroy_shader_selector(struct si_context *sctx,
3270 struct si_shader_selector *sel)
3271 {
3272 struct si_shader *p = sel->first_variant, *c;
3273 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3274 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3275 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3276 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3277 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3278 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3279 };
3280
3281 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3282
3283 if (current_shader[sel->type]->cso == sel) {
3284 current_shader[sel->type]->cso = NULL;
3285 current_shader[sel->type]->current = NULL;
3286 }
3287
3288 while (p) {
3289 c = p->next_variant;
3290 si_delete_shader(sctx, p);
3291 p = c;
3292 }
3293
3294 if (sel->main_shader_part)
3295 si_delete_shader(sctx, sel->main_shader_part);
3296 if (sel->main_shader_part_ls)
3297 si_delete_shader(sctx, sel->main_shader_part_ls);
3298 if (sel->main_shader_part_es)
3299 si_delete_shader(sctx, sel->main_shader_part_es);
3300 if (sel->main_shader_part_ngg)
3301 si_delete_shader(sctx, sel->main_shader_part_ngg);
3302 if (sel->gs_copy_shader)
3303 si_delete_shader(sctx, sel->gs_copy_shader);
3304
3305 util_queue_fence_destroy(&sel->ready);
3306 simple_mtx_destroy(&sel->mutex);
3307 free(sel->tokens);
3308 ralloc_free(sel->nir);
3309 free(sel->nir_binary);
3310 free(sel);
3311 }
3312
3313 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3314 {
3315 struct si_context *sctx = (struct si_context *)ctx;
3316 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3317
3318 si_shader_selector_reference(sctx, &sel, NULL);
3319 }
3320
3321 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3322 struct si_shader *vs, unsigned name,
3323 unsigned index, unsigned interpolate)
3324 {
3325 struct tgsi_shader_info *vsinfo = &vs->selector->info;
3326 unsigned j, offset, ps_input_cntl = 0;
3327
3328 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3329 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3330 name == TGSI_SEMANTIC_PRIMID)
3331 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3332
3333 if (name == TGSI_SEMANTIC_PCOORD ||
3334 (name == TGSI_SEMANTIC_TEXCOORD &&
3335 sctx->sprite_coord_enable & (1 << index))) {
3336 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3337 }
3338
3339 for (j = 0; j < vsinfo->num_outputs; j++) {
3340 if (name == vsinfo->output_semantic_name[j] &&
3341 index == vsinfo->output_semantic_index[j]) {
3342 offset = vs->info.vs_output_param_offset[j];
3343
3344 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3345 /* The input is loaded from parameter memory. */
3346 ps_input_cntl |= S_028644_OFFSET(offset);
3347 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3348 if (offset == AC_EXP_PARAM_UNDEFINED) {
3349 /* This can happen with depth-only rendering. */
3350 offset = 0;
3351 } else {
3352 /* The input is a DEFAULT_VAL constant. */
3353 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3354 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3355 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3356 }
3357
3358 ps_input_cntl = S_028644_OFFSET(0x20) |
3359 S_028644_DEFAULT_VAL(offset);
3360 }
3361 break;
3362 }
3363 }
3364
3365 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3366 /* PrimID is written after the last output when HW VS is used. */
3367 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3368 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3369 /* No corresponding output found, load defaults into input.
3370 * Don't set any other bits.
3371 * (FLAT_SHADE=1 completely changes behavior) */
3372 ps_input_cntl = S_028644_OFFSET(0x20);
3373 /* D3D 9 behaviour. GL is undefined */
3374 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3375 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3376 }
3377 return ps_input_cntl;
3378 }
3379
3380 static void si_emit_spi_map(struct si_context *sctx)
3381 {
3382 struct si_shader *ps = sctx->ps_shader.current;
3383 struct si_shader *vs = si_get_vs_state(sctx);
3384 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3385 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3386 unsigned spi_ps_input_cntl[32];
3387
3388 if (!ps || !ps->selector->info.num_inputs)
3389 return;
3390
3391 num_interp = si_get_ps_num_interp(ps);
3392 assert(num_interp > 0);
3393
3394 for (i = 0; i < psinfo->num_inputs; i++) {
3395 unsigned name = psinfo->input_semantic_name[i];
3396 unsigned index = psinfo->input_semantic_index[i];
3397 unsigned interpolate = psinfo->input_interpolate[i];
3398
3399 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3400 index, interpolate);
3401
3402 if (name == TGSI_SEMANTIC_COLOR) {
3403 assert(index < ARRAY_SIZE(bcol_interp));
3404 bcol_interp[index] = interpolate;
3405 }
3406 }
3407
3408 if (ps->key.part.ps.prolog.color_two_side) {
3409 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3410
3411 for (i = 0; i < 2; i++) {
3412 if (!(psinfo->colors_read & (0xf << (i * 4))))
3413 continue;
3414
3415 spi_ps_input_cntl[num_written++] =
3416 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3417
3418 }
3419 }
3420 assert(num_interp == num_written);
3421
3422 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3423 /* Dota 2: Only ~16% of SPI map updates set different values. */
3424 /* Talos: Only ~9% of SPI map updates set different values. */
3425 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3426 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3427 spi_ps_input_cntl,
3428 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3429
3430 if (initial_cdw != sctx->gfx_cs->current.cdw)
3431 sctx->context_roll = true;
3432 }
3433
3434 /**
3435 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3436 */
3437 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3438 {
3439 if (sctx->init_config_has_vgt_flush)
3440 return;
3441
3442 /* Done by Vulkan before VGT_FLUSH. */
3443 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3444 si_pm4_cmd_add(sctx->init_config,
3445 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3446 si_pm4_cmd_end(sctx->init_config, false);
3447
3448 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3449 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3450 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3451 si_pm4_cmd_end(sctx->init_config, false);
3452 sctx->init_config_has_vgt_flush = true;
3453 }
3454
3455 /* Initialize state related to ESGS / GSVS ring buffers */
3456 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3457 {
3458 struct si_shader_selector *es =
3459 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3460 struct si_shader_selector *gs = sctx->gs_shader.cso;
3461 struct si_pm4_state *pm4;
3462
3463 /* Chip constants. */
3464 unsigned num_se = sctx->screen->info.max_se;
3465 unsigned wave_size = 64;
3466 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3467 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3468 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3469 */
3470 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3471 unsigned alignment = 256 * num_se;
3472 /* The maximum size is 63.999 MB per SE. */
3473 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3474
3475 /* Calculate the minimum size. */
3476 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3477 wave_size, alignment);
3478
3479 /* These are recommended sizes, not minimum sizes. */
3480 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3481 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3482 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3483 gs->max_gsvs_emit_size;
3484
3485 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3486 esgs_ring_size = align(esgs_ring_size, alignment);
3487 gsvs_ring_size = align(gsvs_ring_size, alignment);
3488
3489 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3490 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3491
3492 /* Some rings don't have to be allocated if shaders don't use them.
3493 * (e.g. no varyings between ES and GS or GS and VS)
3494 *
3495 * GFX9 doesn't have the ESGS ring.
3496 */
3497 bool update_esgs = sctx->chip_class <= GFX8 &&
3498 esgs_ring_size &&
3499 (!sctx->esgs_ring ||
3500 sctx->esgs_ring->width0 < esgs_ring_size);
3501 bool update_gsvs = gsvs_ring_size &&
3502 (!sctx->gsvs_ring ||
3503 sctx->gsvs_ring->width0 < gsvs_ring_size);
3504
3505 if (!update_esgs && !update_gsvs)
3506 return true;
3507
3508 if (update_esgs) {
3509 pipe_resource_reference(&sctx->esgs_ring, NULL);
3510 sctx->esgs_ring =
3511 pipe_aligned_buffer_create(sctx->b.screen,
3512 SI_RESOURCE_FLAG_UNMAPPABLE,
3513 PIPE_USAGE_DEFAULT,
3514 esgs_ring_size,
3515 sctx->screen->info.pte_fragment_size);
3516 if (!sctx->esgs_ring)
3517 return false;
3518 }
3519
3520 if (update_gsvs) {
3521 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3522 sctx->gsvs_ring =
3523 pipe_aligned_buffer_create(sctx->b.screen,
3524 SI_RESOURCE_FLAG_UNMAPPABLE,
3525 PIPE_USAGE_DEFAULT,
3526 gsvs_ring_size,
3527 sctx->screen->info.pte_fragment_size);
3528 if (!sctx->gsvs_ring)
3529 return false;
3530 }
3531
3532 /* Create the "init_config_gs_rings" state. */
3533 pm4 = CALLOC_STRUCT(si_pm4_state);
3534 if (!pm4)
3535 return false;
3536
3537 if (sctx->chip_class >= GFX7) {
3538 if (sctx->esgs_ring) {
3539 assert(sctx->chip_class <= GFX8);
3540 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3541 sctx->esgs_ring->width0 / 256);
3542 }
3543 if (sctx->gsvs_ring)
3544 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3545 sctx->gsvs_ring->width0 / 256);
3546 } else {
3547 if (sctx->esgs_ring)
3548 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3549 sctx->esgs_ring->width0 / 256);
3550 if (sctx->gsvs_ring)
3551 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3552 sctx->gsvs_ring->width0 / 256);
3553 }
3554
3555 /* Set the state. */
3556 if (sctx->init_config_gs_rings)
3557 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3558 sctx->init_config_gs_rings = pm4;
3559
3560 if (!sctx->init_config_has_vgt_flush) {
3561 si_init_config_add_vgt_flush(sctx);
3562 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3563 }
3564
3565 /* Flush the context to re-emit both init_config states. */
3566 sctx->initial_gfx_cs_size = 0; /* force flush */
3567 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3568
3569 /* Set ring bindings. */
3570 if (sctx->esgs_ring) {
3571 assert(sctx->chip_class <= GFX8);
3572 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3573 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3574 true, true, 4, 64, 0);
3575 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3576 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3577 false, false, 0, 0, 0);
3578 }
3579 if (sctx->gsvs_ring) {
3580 si_set_ring_buffer(sctx, SI_RING_GSVS,
3581 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3582 false, false, 0, 0, 0);
3583 }
3584
3585 return true;
3586 }
3587
3588 static void si_shader_lock(struct si_shader *shader)
3589 {
3590 simple_mtx_lock(&shader->selector->mutex);
3591 if (shader->previous_stage_sel) {
3592 assert(shader->previous_stage_sel != shader->selector);
3593 simple_mtx_lock(&shader->previous_stage_sel->mutex);
3594 }
3595 }
3596
3597 static void si_shader_unlock(struct si_shader *shader)
3598 {
3599 if (shader->previous_stage_sel)
3600 simple_mtx_unlock(&shader->previous_stage_sel->mutex);
3601 simple_mtx_unlock(&shader->selector->mutex);
3602 }
3603
3604 /**
3605 * @returns 1 if \p sel has been updated to use a new scratch buffer
3606 * 0 if not
3607 * < 0 if there was a failure
3608 */
3609 static int si_update_scratch_buffer(struct si_context *sctx,
3610 struct si_shader *shader)
3611 {
3612 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3613
3614 if (!shader)
3615 return 0;
3616
3617 /* This shader doesn't need a scratch buffer */
3618 if (shader->config.scratch_bytes_per_wave == 0)
3619 return 0;
3620
3621 /* Prevent race conditions when updating:
3622 * - si_shader::scratch_bo
3623 * - si_shader::binary::code
3624 * - si_shader::previous_stage::binary::code.
3625 */
3626 si_shader_lock(shader);
3627
3628 /* This shader is already configured to use the current
3629 * scratch buffer. */
3630 if (shader->scratch_bo == sctx->scratch_buffer) {
3631 si_shader_unlock(shader);
3632 return 0;
3633 }
3634
3635 assert(sctx->scratch_buffer);
3636
3637 /* Replace the shader bo with a new bo that has the relocs applied. */
3638 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3639 si_shader_unlock(shader);
3640 return -1;
3641 }
3642
3643 /* Update the shader state to use the new shader bo. */
3644 si_shader_init_pm4_state(sctx->screen, shader);
3645
3646 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3647
3648 si_shader_unlock(shader);
3649 return 1;
3650 }
3651
3652 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3653 {
3654 return shader ? shader->config.scratch_bytes_per_wave : 0;
3655 }
3656
3657 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3658 {
3659 if (!sctx->tes_shader.cso)
3660 return NULL; /* tessellation disabled */
3661
3662 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3663 sctx->fixed_func_tcs_shader.current;
3664 }
3665
3666 static bool si_update_scratch_relocs(struct si_context *sctx)
3667 {
3668 struct si_shader *tcs = si_get_tcs_current(sctx);
3669 int r;
3670
3671 /* Update the shaders, so that they are using the latest scratch.
3672 * The scratch buffer may have been changed since these shaders were
3673 * last used, so we still need to try to update them, even if they
3674 * require scratch buffers smaller than the current size.
3675 */
3676 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3677 if (r < 0)
3678 return false;
3679 if (r == 1)
3680 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3681
3682 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3683 if (r < 0)
3684 return false;
3685 if (r == 1)
3686 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3687
3688 r = si_update_scratch_buffer(sctx, tcs);
3689 if (r < 0)
3690 return false;
3691 if (r == 1)
3692 si_pm4_bind_state(sctx, hs, tcs->pm4);
3693
3694 /* VS can be bound as LS, ES, or VS. */
3695 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3696 if (r < 0)
3697 return false;
3698 if (r == 1) {
3699 if (sctx->vs_shader.current->key.as_ls)
3700 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3701 else if (sctx->vs_shader.current->key.as_es)
3702 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3703 else if (sctx->vs_shader.current->key.as_ngg)
3704 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3705 else
3706 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3707 }
3708
3709 /* TES can be bound as ES or VS. */
3710 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3711 if (r < 0)
3712 return false;
3713 if (r == 1) {
3714 if (sctx->tes_shader.current->key.as_es)
3715 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3716 else if (sctx->tes_shader.current->key.as_ngg)
3717 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3718 else
3719 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3720 }
3721
3722 return true;
3723 }
3724
3725 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3726 {
3727 /* SPI_TMPRING_SIZE.WAVESIZE must be constant for each scratch buffer.
3728 * There are 2 cases to handle:
3729 *
3730 * - If the current needed size is less than the maximum seen size,
3731 * use the maximum seen size, so that WAVESIZE remains the same.
3732 *
3733 * - If the current needed size is greater than the maximum seen size,
3734 * the scratch buffer is reallocated, so we can increase WAVESIZE.
3735 *
3736 * Shaders that set SCRATCH_EN=0 don't allocate scratch space.
3737 * Otherwise, the number of waves that can use scratch is
3738 * SPI_TMPRING_SIZE.WAVES.
3739 */
3740 unsigned bytes = 0;
3741
3742 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3743 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3744 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3745
3746 if (sctx->tes_shader.cso) {
3747 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3748 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(si_get_tcs_current(sctx)));
3749 }
3750
3751 sctx->max_seen_scratch_bytes_per_wave =
3752 MAX2(sctx->max_seen_scratch_bytes_per_wave, bytes);
3753
3754 unsigned scratch_needed_size =
3755 sctx->max_seen_scratch_bytes_per_wave * sctx->scratch_waves;
3756 unsigned spi_tmpring_size;
3757
3758 if (scratch_needed_size > 0) {
3759 if (!sctx->scratch_buffer ||
3760 scratch_needed_size > sctx->scratch_buffer->b.b.width0) {
3761 /* Create a bigger scratch buffer */
3762 si_resource_reference(&sctx->scratch_buffer, NULL);
3763
3764 sctx->scratch_buffer =
3765 si_aligned_buffer_create(&sctx->screen->b,
3766 SI_RESOURCE_FLAG_UNMAPPABLE,
3767 PIPE_USAGE_DEFAULT,
3768 scratch_needed_size,
3769 sctx->screen->info.pte_fragment_size);
3770 if (!sctx->scratch_buffer)
3771 return false;
3772
3773 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3774 si_context_add_resource_size(sctx,
3775 &sctx->scratch_buffer->b.b);
3776 }
3777
3778 if (!si_update_scratch_relocs(sctx))
3779 return false;
3780 }
3781
3782 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3783 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3784 "scratch size should already be aligned correctly.");
3785
3786 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3787 S_0286E8_WAVESIZE(sctx->max_seen_scratch_bytes_per_wave >> 10);
3788 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3789 sctx->spi_tmpring_size = spi_tmpring_size;
3790 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3791 }
3792 return true;
3793 }
3794
3795 static void si_init_tess_factor_ring(struct si_context *sctx)
3796 {
3797 assert(!sctx->tess_rings);
3798 assert(((sctx->screen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
3799
3800 /* The address must be aligned to 2^19, because the shader only
3801 * receives the high 13 bits.
3802 */
3803 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3804 SI_RESOURCE_FLAG_32BIT,
3805 PIPE_USAGE_DEFAULT,
3806 sctx->screen->tess_offchip_ring_size +
3807 sctx->screen->tess_factor_ring_size,
3808 1 << 19);
3809 if (!sctx->tess_rings)
3810 return;
3811
3812 si_init_config_add_vgt_flush(sctx);
3813
3814 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3815 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3816
3817 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3818 sctx->screen->tess_offchip_ring_size;
3819
3820 /* Append these registers to the init config state. */
3821 if (sctx->chip_class >= GFX7) {
3822 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3823 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3824 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3825 factor_va >> 8);
3826 if (sctx->chip_class >= GFX10)
3827 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3828 S_030984_BASE_HI(factor_va >> 40));
3829 else if (sctx->chip_class == GFX9)
3830 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3831 S_030944_BASE_HI(factor_va >> 40));
3832 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3833 sctx->screen->vgt_hs_offchip_param);
3834 } else {
3835 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3836 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3837 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3838 factor_va >> 8);
3839 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3840 sctx->screen->vgt_hs_offchip_param);
3841 }
3842
3843 /* Flush the context to re-emit the init_config state.
3844 * This is done only once in a lifetime of a context.
3845 */
3846 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3847 sctx->initial_gfx_cs_size = 0; /* force flush */
3848 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3849 }
3850
3851 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3852 union si_vgt_stages_key key)
3853 {
3854 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3855 uint32_t stages = 0;
3856
3857 if (key.u.tess) {
3858 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3859 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3860
3861 if (key.u.gs)
3862 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3863 S_028B54_GS_EN(1);
3864 else if (key.u.ngg)
3865 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3866 else
3867 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3868 } else if (key.u.gs) {
3869 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3870 S_028B54_GS_EN(1);
3871 } else if (key.u.ngg) {
3872 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3873 }
3874
3875 if (key.u.ngg) {
3876 stages |= S_028B54_PRIMGEN_EN(1) |
3877 S_028B54_NGG_WAVE_ID_EN(key.u.streamout) |
3878 S_028B54_PRIMGEN_PASSTHRU_EN(key.u.ngg_passthrough);
3879 } else if (key.u.gs)
3880 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3881
3882 if (screen->info.chip_class >= GFX9)
3883 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3884
3885 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
3886 stages |= S_028B54_HS_W32_EN(1) |
3887 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3888 S_028B54_VS_W32_EN(1);
3889 }
3890
3891 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3892 return pm4;
3893 }
3894
3895 static void si_update_vgt_shader_config(struct si_context *sctx,
3896 union si_vgt_stages_key key)
3897 {
3898 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3899
3900 if (unlikely(!*pm4))
3901 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3902 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3903 }
3904
3905 bool si_update_shaders(struct si_context *sctx)
3906 {
3907 struct pipe_context *ctx = (struct pipe_context*)sctx;
3908 struct si_compiler_ctx_state compiler_state;
3909 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3910 struct si_shader *old_vs = si_get_vs_state(sctx);
3911 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3912 struct si_shader *old_ps = sctx->ps_shader.current;
3913 union si_vgt_stages_key key;
3914 unsigned old_spi_shader_col_format =
3915 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3916 int r;
3917
3918 if (!sctx->compiler.passes)
3919 si_init_compiler(sctx->screen, &sctx->compiler);
3920
3921 compiler_state.compiler = &sctx->compiler;
3922 compiler_state.debug = sctx->debug;
3923 compiler_state.is_debug_context = sctx->is_debug;
3924
3925 key.index = 0;
3926
3927 if (sctx->tes_shader.cso)
3928 key.u.tess = 1;
3929 if (sctx->gs_shader.cso)
3930 key.u.gs = 1;
3931
3932 if (sctx->ngg) {
3933 key.u.ngg = 1;
3934 key.u.streamout = !!si_get_vs(sctx)->cso->so.num_outputs;
3935 }
3936
3937 /* Update TCS and TES. */
3938 if (sctx->tes_shader.cso) {
3939 if (!sctx->tess_rings) {
3940 si_init_tess_factor_ring(sctx);
3941 if (!sctx->tess_rings)
3942 return false;
3943 }
3944
3945 if (sctx->tcs_shader.cso) {
3946 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3947 &compiler_state);
3948 if (r)
3949 return false;
3950 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3951 } else {
3952 if (!sctx->fixed_func_tcs_shader.cso) {
3953 sctx->fixed_func_tcs_shader.cso =
3954 si_create_fixed_func_tcs(sctx);
3955 if (!sctx->fixed_func_tcs_shader.cso)
3956 return false;
3957 }
3958
3959 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3960 key, &compiler_state);
3961 if (r)
3962 return false;
3963 si_pm4_bind_state(sctx, hs,
3964 sctx->fixed_func_tcs_shader.current->pm4);
3965 }
3966
3967 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3968 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3969 if (r)
3970 return false;
3971
3972 if (sctx->gs_shader.cso) {
3973 /* TES as ES */
3974 assert(sctx->chip_class <= GFX8);
3975 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3976 } else if (key.u.ngg) {
3977 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3978 } else {
3979 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3980 }
3981 }
3982 } else {
3983 if (sctx->chip_class <= GFX8)
3984 si_pm4_bind_state(sctx, ls, NULL);
3985 si_pm4_bind_state(sctx, hs, NULL);
3986 }
3987
3988 /* Update GS. */
3989 if (sctx->gs_shader.cso) {
3990 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3991 if (r)
3992 return false;
3993 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3994 if (!key.u.ngg) {
3995 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3996
3997 if (!si_update_gs_ring_buffers(sctx))
3998 return false;
3999 } else {
4000 si_pm4_bind_state(sctx, vs, NULL);
4001 }
4002 } else {
4003 if (!key.u.ngg) {
4004 si_pm4_bind_state(sctx, gs, NULL);
4005 if (sctx->chip_class <= GFX8)
4006 si_pm4_bind_state(sctx, es, NULL);
4007 }
4008 }
4009
4010 /* Update VS. */
4011 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
4012 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
4013 if (r)
4014 return false;
4015
4016 if (!key.u.tess && !key.u.gs) {
4017 if (key.u.ngg) {
4018 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
4019 si_pm4_bind_state(sctx, vs, NULL);
4020 } else {
4021 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
4022 }
4023 } else if (sctx->tes_shader.cso) {
4024 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
4025 } else {
4026 assert(sctx->gs_shader.cso);
4027 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
4028 }
4029 }
4030
4031 /* This must be done after the shader variant is selected. */
4032 if (sctx->ngg)
4033 key.u.ngg_passthrough = gfx10_is_ngg_passthrough(si_get_vs(sctx)->current);
4034
4035 si_update_vgt_shader_config(sctx, key);
4036
4037 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
4038 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
4039
4040 if (sctx->ps_shader.cso) {
4041 unsigned db_shader_control;
4042
4043 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
4044 if (r)
4045 return false;
4046 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
4047
4048 db_shader_control =
4049 sctx->ps_shader.cso->db_shader_control |
4050 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
4051
4052 if (si_pm4_state_changed(sctx, ps) ||
4053 si_pm4_state_changed(sctx, vs) ||
4054 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
4055 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
4056 sctx->flatshade != rs->flatshade) {
4057 sctx->sprite_coord_enable = rs->sprite_coord_enable;
4058 sctx->flatshade = rs->flatshade;
4059 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
4060 }
4061
4062 if (sctx->screen->info.rbplus_allowed &&
4063 si_pm4_state_changed(sctx, ps) &&
4064 (!old_ps ||
4065 old_spi_shader_col_format !=
4066 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
4067 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
4068
4069 if (sctx->ps_db_shader_control != db_shader_control) {
4070 sctx->ps_db_shader_control = db_shader_control;
4071 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4072 if (sctx->screen->dpbb_allowed)
4073 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
4074 }
4075
4076 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
4077 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
4078 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
4079
4080 if (sctx->chip_class == GFX6)
4081 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4082
4083 if (sctx->framebuffer.nr_samples <= 1)
4084 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
4085 }
4086 }
4087
4088 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
4089 si_pm4_state_enabled_and_changed(sctx, hs) ||
4090 si_pm4_state_enabled_and_changed(sctx, es) ||
4091 si_pm4_state_enabled_and_changed(sctx, gs) ||
4092 si_pm4_state_enabled_and_changed(sctx, vs) ||
4093 si_pm4_state_enabled_and_changed(sctx, ps)) {
4094 if (!si_update_spi_tmpring_size(sctx))
4095 return false;
4096 }
4097
4098 if (sctx->chip_class >= GFX7) {
4099 if (si_pm4_state_enabled_and_changed(sctx, ls))
4100 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
4101 else if (!sctx->queued.named.ls)
4102 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
4103
4104 if (si_pm4_state_enabled_and_changed(sctx, hs))
4105 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
4106 else if (!sctx->queued.named.hs)
4107 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
4108
4109 if (si_pm4_state_enabled_and_changed(sctx, es))
4110 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4111 else if (!sctx->queued.named.es)
4112 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4113
4114 if (si_pm4_state_enabled_and_changed(sctx, gs))
4115 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4116 else if (!sctx->queued.named.gs)
4117 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4118
4119 if (si_pm4_state_enabled_and_changed(sctx, vs))
4120 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4121 else if (!sctx->queued.named.vs)
4122 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4123
4124 if (si_pm4_state_enabled_and_changed(sctx, ps))
4125 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4126 else if (!sctx->queued.named.ps)
4127 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4128 }
4129
4130 sctx->do_update_shaders = false;
4131 return true;
4132 }
4133
4134 static void si_emit_scratch_state(struct si_context *sctx)
4135 {
4136 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4137
4138 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4139 sctx->spi_tmpring_size);
4140
4141 if (sctx->scratch_buffer) {
4142 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4143 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4144 RADEON_PRIO_SCRATCH_BUFFER);
4145 }
4146 }
4147
4148 void si_init_shader_functions(struct si_context *sctx)
4149 {
4150 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4151 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4152
4153 sctx->b.create_vs_state = si_create_shader_selector;
4154 sctx->b.create_tcs_state = si_create_shader_selector;
4155 sctx->b.create_tes_state = si_create_shader_selector;
4156 sctx->b.create_gs_state = si_create_shader_selector;
4157 sctx->b.create_fs_state = si_create_shader_selector;
4158
4159 sctx->b.bind_vs_state = si_bind_vs_shader;
4160 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4161 sctx->b.bind_tes_state = si_bind_tes_shader;
4162 sctx->b.bind_gs_state = si_bind_gs_shader;
4163 sctx->b.bind_fs_state = si_bind_ps_shader;
4164
4165 sctx->b.delete_vs_state = si_delete_shader_selector;
4166 sctx->b.delete_tcs_state = si_delete_shader_selector;
4167 sctx->b.delete_tes_state = si_delete_shader_selector;
4168 sctx->b.delete_gs_state = si_delete_shader_selector;
4169 sctx->b.delete_fs_state = si_delete_shader_selector;
4170 }