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radeonsi: Don't offset OFFCHIP_BUFFERING on pre-VI cards.
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31 #include "radeon/r600_cs.h"
32
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/hash_table.h"
36 #include "util/u_hash.h"
37 #include "util/u_memory.h"
38 #include "util/u_prim.h"
39 #include "util/u_simple_shaders.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
45 * integer.
46 */
47 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
48 {
49 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
50 sizeof(struct tgsi_token);
51 unsigned size = 4 + tgsi_size + sizeof(sel->so);
52 char *result = (char*)MALLOC(size);
53
54 if (!result)
55 return NULL;
56
57 *((uint32_t*)result) = size;
58 memcpy(result + 4, sel->tokens, tgsi_size);
59 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
60 return result;
61 }
62
63 /** Copy "data" to "ptr" and return the next dword following copied data. */
64 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
65 {
66 /* data may be NULL if size == 0 */
67 if (size)
68 memcpy(ptr, data, size);
69 ptr += DIV_ROUND_UP(size, 4);
70 return ptr;
71 }
72
73 /** Read data from "ptr". Return the next dword following the data. */
74 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
75 {
76 memcpy(data, ptr, size);
77 ptr += DIV_ROUND_UP(size, 4);
78 return ptr;
79 }
80
81 /**
82 * Write the size as uint followed by the data. Return the next dword
83 * following the copied data.
84 */
85 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
86 {
87 *ptr++ = size;
88 return write_data(ptr, data, size);
89 }
90
91 /**
92 * Read the size as uint followed by the data. Return both via parameters.
93 * Return the next dword following the data.
94 */
95 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
96 {
97 *size = *ptr++;
98 assert(*data == NULL);
99 *data = malloc(*size);
100 return read_data(ptr, *data, *size);
101 }
102
103 /**
104 * Return the shader binary in a buffer. The first 4 bytes contain its size
105 * as integer.
106 */
107 static void *si_get_shader_binary(struct si_shader *shader)
108 {
109 /* There is always a size of data followed by the data itself. */
110 unsigned relocs_size = shader->binary.reloc_count *
111 sizeof(shader->binary.relocs[0]);
112 unsigned disasm_size = strlen(shader->binary.disasm_string) + 1;
113 unsigned size =
114 4 + /* total size */
115 4 + /* CRC32 of the data below */
116 align(sizeof(shader->config), 4) +
117 align(sizeof(shader->info), 4) +
118 4 + align(shader->binary.code_size, 4) +
119 4 + align(shader->binary.rodata_size, 4) +
120 4 + align(relocs_size, 4) +
121 4 + align(disasm_size, 4);
122 void *buffer = CALLOC(1, size);
123 uint32_t *ptr = (uint32_t*)buffer;
124
125 if (!buffer)
126 return NULL;
127
128 *ptr++ = size;
129 ptr++; /* CRC32 is calculated at the end. */
130
131 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
132 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
133 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
134 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
135 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
136 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
137 assert((char *)ptr - (char *)buffer == size);
138
139 /* Compute CRC32. */
140 ptr = (uint32_t*)buffer;
141 ptr++;
142 *ptr = util_hash_crc32(ptr + 1, size - 8);
143
144 return buffer;
145 }
146
147 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
148 {
149 uint32_t *ptr = (uint32_t*)binary;
150 uint32_t size = *ptr++;
151 uint32_t crc32 = *ptr++;
152 unsigned chunk_size;
153
154 if (util_hash_crc32(ptr, size - 8) != crc32) {
155 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
156 return false;
157 }
158
159 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
160 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
161 ptr = read_chunk(ptr, (void**)&shader->binary.code,
162 &shader->binary.code_size);
163 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
164 &shader->binary.rodata_size);
165 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
166 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
167 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
168
169 return true;
170 }
171
172 /**
173 * Insert a shader into the cache. It's assumed the shader is not in the cache.
174 * Use si_shader_cache_load_shader before calling this.
175 *
176 * Returns false on failure, in which case the tgsi_binary should be freed.
177 */
178 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
179 void *tgsi_binary,
180 struct si_shader *shader)
181 {
182 void *hw_binary = si_get_shader_binary(shader);
183
184 if (!hw_binary)
185 return false;
186
187 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
188 hw_binary) == NULL) {
189 FREE(hw_binary);
190 return false;
191 }
192
193 return true;
194 }
195
196 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
197 void *tgsi_binary,
198 struct si_shader *shader)
199 {
200 struct hash_entry *entry =
201 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
202 if (!entry)
203 return false;
204
205 return si_load_shader_binary(shader, entry->data);
206 }
207
208 static uint32_t si_shader_cache_key_hash(const void *key)
209 {
210 /* The first dword is the key size. */
211 return util_hash_crc32(key, *(uint32_t*)key);
212 }
213
214 static bool si_shader_cache_key_equals(const void *a, const void *b)
215 {
216 uint32_t *keya = (uint32_t*)a;
217 uint32_t *keyb = (uint32_t*)b;
218
219 /* The first dword is the key size. */
220 if (*keya != *keyb)
221 return false;
222
223 return memcmp(keya, keyb, *keya) == 0;
224 }
225
226 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
227 {
228 FREE((void*)entry->key);
229 FREE(entry->data);
230 }
231
232 bool si_init_shader_cache(struct si_screen *sscreen)
233 {
234 pipe_mutex_init(sscreen->shader_cache_mutex);
235 sscreen->shader_cache =
236 _mesa_hash_table_create(NULL,
237 si_shader_cache_key_hash,
238 si_shader_cache_key_equals);
239 return sscreen->shader_cache != NULL;
240 }
241
242 void si_destroy_shader_cache(struct si_screen *sscreen)
243 {
244 if (sscreen->shader_cache)
245 _mesa_hash_table_destroy(sscreen->shader_cache,
246 si_destroy_shader_cache_entry);
247 pipe_mutex_destroy(sscreen->shader_cache_mutex);
248 }
249
250 /* SHADER STATES */
251
252 static void si_set_tesseval_regs(struct si_screen *sscreen,
253 struct si_shader *shader,
254 struct si_pm4_state *pm4)
255 {
256 struct tgsi_shader_info *info = &shader->selector->info;
257 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
258 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
259 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
260 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
261 unsigned type, partitioning, topology, distribution_mode;
262
263 switch (tes_prim_mode) {
264 case PIPE_PRIM_LINES:
265 type = V_028B6C_TESS_ISOLINE;
266 break;
267 case PIPE_PRIM_TRIANGLES:
268 type = V_028B6C_TESS_TRIANGLE;
269 break;
270 case PIPE_PRIM_QUADS:
271 type = V_028B6C_TESS_QUAD;
272 break;
273 default:
274 assert(0);
275 return;
276 }
277
278 switch (tes_spacing) {
279 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
280 partitioning = V_028B6C_PART_FRAC_ODD;
281 break;
282 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
283 partitioning = V_028B6C_PART_FRAC_EVEN;
284 break;
285 case PIPE_TESS_SPACING_EQUAL:
286 partitioning = V_028B6C_PART_INTEGER;
287 break;
288 default:
289 assert(0);
290 return;
291 }
292
293 if (tes_point_mode)
294 topology = V_028B6C_OUTPUT_POINT;
295 else if (tes_prim_mode == PIPE_PRIM_LINES)
296 topology = V_028B6C_OUTPUT_LINE;
297 else if (tes_vertex_order_cw)
298 /* for some reason, this must be the other way around */
299 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
300 else
301 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
302
303 if (sscreen->b.chip_class >= VI)
304 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
305 else
306 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
307
308 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
309 S_028B6C_TYPE(type) |
310 S_028B6C_PARTITIONING(partitioning) |
311 S_028B6C_TOPOLOGY(topology) |
312 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
313 }
314
315 static void si_shader_ls(struct si_shader *shader)
316 {
317 struct si_pm4_state *pm4;
318 unsigned vgpr_comp_cnt;
319 uint64_t va;
320
321 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
322 if (!pm4)
323 return;
324
325 va = shader->bo->gpu_address;
326 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
327
328 /* We need at least 2 components for LS.
329 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
330 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 1;
331
332 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
333 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
334
335 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
336 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
337 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
338 S_00B528_DX10_CLAMP(1) |
339 S_00B528_FLOAT_MODE(shader->config.float_mode);
340 shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_LS_NUM_USER_SGPR) |
341 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
342 }
343
344 static void si_shader_hs(struct si_shader *shader)
345 {
346 struct si_pm4_state *pm4;
347 uint64_t va;
348
349 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
350 if (!pm4)
351 return;
352
353 va = shader->bo->gpu_address;
354 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
355
356 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
357 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
358 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
359 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
360 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
361 S_00B428_DX10_CLAMP(1) |
362 S_00B428_FLOAT_MODE(shader->config.float_mode));
363 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
364 S_00B42C_USER_SGPR(SI_TCS_NUM_USER_SGPR) |
365 S_00B42C_OC_LDS_EN(1) |
366 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
367 }
368
369 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
370 {
371 struct si_pm4_state *pm4;
372 unsigned num_user_sgprs;
373 unsigned vgpr_comp_cnt;
374 uint64_t va;
375 unsigned oc_lds_en;
376
377 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
378
379 if (!pm4)
380 return;
381
382 va = shader->bo->gpu_address;
383 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
384
385 if (shader->selector->type == PIPE_SHADER_VERTEX) {
386 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
387 num_user_sgprs = SI_ES_NUM_USER_SGPR;
388 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
389 vgpr_comp_cnt = 3; /* all components are needed for TES */
390 num_user_sgprs = SI_TES_NUM_USER_SGPR;
391 } else
392 unreachable("invalid shader selector type");
393
394 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
395
396 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
397 shader->selector->esgs_itemsize / 4);
398 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
399 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
400 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
401 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
402 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
403 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
404 S_00B328_DX10_CLAMP(1) |
405 S_00B328_FLOAT_MODE(shader->config.float_mode));
406 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
407 S_00B32C_USER_SGPR(num_user_sgprs) |
408 S_00B32C_OC_LDS_EN(oc_lds_en) |
409 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
410
411 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
412 si_set_tesseval_regs(sscreen, shader, pm4);
413 }
414
415 /**
416 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
417 * geometry shader.
418 */
419 static uint32_t si_vgt_gs_mode(struct si_shader *shader)
420 {
421 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
422 unsigned cut_mode;
423
424 if (gs_max_vert_out <= 128) {
425 cut_mode = V_028A40_GS_CUT_128;
426 } else if (gs_max_vert_out <= 256) {
427 cut_mode = V_028A40_GS_CUT_256;
428 } else if (gs_max_vert_out <= 512) {
429 cut_mode = V_028A40_GS_CUT_512;
430 } else {
431 assert(gs_max_vert_out <= 1024);
432 cut_mode = V_028A40_GS_CUT_1024;
433 }
434
435 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
436 S_028A40_CUT_MODE(cut_mode)|
437 S_028A40_ES_WRITE_OPTIMIZE(1) |
438 S_028A40_GS_WRITE_OPTIMIZE(1);
439 }
440
441 static void si_shader_gs(struct si_shader *shader)
442 {
443 unsigned gs_vert_itemsize = shader->selector->gsvs_vertex_size;
444 unsigned gsvs_itemsize = shader->selector->max_gsvs_emit_size >> 2;
445 unsigned gs_num_invocations = shader->selector->gs_num_invocations;
446 struct si_pm4_state *pm4;
447 uint64_t va;
448 unsigned max_stream = shader->selector->max_gs_stream;
449
450 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
451 assert(gsvs_itemsize < (1 << 15));
452
453 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
454
455 if (!pm4)
456 return;
457
458 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(shader));
459
460 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
461 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize * ((max_stream >= 2) ? 2 : 1));
462 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize * ((max_stream >= 3) ? 3 : 1));
463
464 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize * (max_stream + 1));
465
466 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, shader->selector->gs_max_out_vertices);
467
468 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize >> 2);
469 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? gs_vert_itemsize >> 2 : 0);
470 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? gs_vert_itemsize >> 2 : 0);
471 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? gs_vert_itemsize >> 2 : 0);
472
473 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
474 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
475 S_028B90_ENABLE(gs_num_invocations > 0));
476
477 va = shader->bo->gpu_address;
478 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
479 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
480 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
481
482 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
483 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
484 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
485 S_00B228_DX10_CLAMP(1) |
486 S_00B228_FLOAT_MODE(shader->config.float_mode));
487 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
488 S_00B22C_USER_SGPR(SI_GS_NUM_USER_SGPR) |
489 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
490 }
491
492 /**
493 * Compute the state for \p shader, which will run as a vertex shader on the
494 * hardware.
495 *
496 * If \p gs is non-NULL, it points to the geometry shader for which this shader
497 * is the copy shader.
498 */
499 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
500 struct si_shader *gs)
501 {
502 struct si_pm4_state *pm4;
503 unsigned num_user_sgprs;
504 unsigned nparams, vgpr_comp_cnt;
505 uint64_t va;
506 unsigned oc_lds_en;
507 unsigned window_space =
508 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
509 bool enable_prim_id = si_vs_exports_prim_id(shader);
510
511 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
512
513 if (!pm4)
514 return;
515
516 /* We always write VGT_GS_MODE in the VS state, because every switch
517 * between different shader pipelines involving a different GS or no
518 * GS at all involves a switch of the VS (different GS use different
519 * copy shaders). On the other hand, when the API switches from a GS to
520 * no GS and then back to the same GS used originally, the GS state is
521 * not sent again.
522 */
523 if (!gs) {
524 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
525 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
526 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
527 } else {
528 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
529 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
530 }
531
532 va = shader->bo->gpu_address;
533 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
534
535 if (gs) {
536 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
537 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
538 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
539 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
540 num_user_sgprs = SI_VS_NUM_USER_SGPR;
541 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
542 vgpr_comp_cnt = 3; /* all components are needed for TES */
543 num_user_sgprs = SI_TES_NUM_USER_SGPR;
544 } else
545 unreachable("invalid shader selector type");
546
547 /* VS is required to export at least one param. */
548 nparams = MAX2(shader->info.nr_param_exports, 1);
549 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
550 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
551
552 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
553 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
554 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
555 V_02870C_SPI_SHADER_4COMP :
556 V_02870C_SPI_SHADER_NONE) |
557 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
558 V_02870C_SPI_SHADER_4COMP :
559 V_02870C_SPI_SHADER_NONE) |
560 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
561 V_02870C_SPI_SHADER_4COMP :
562 V_02870C_SPI_SHADER_NONE));
563
564 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
565
566 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
567 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
568 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
569 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
570 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
571 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
572 S_00B128_DX10_CLAMP(1) |
573 S_00B128_FLOAT_MODE(shader->config.float_mode));
574 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
575 S_00B12C_USER_SGPR(num_user_sgprs) |
576 S_00B12C_OC_LDS_EN(oc_lds_en) |
577 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
578 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
579 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
580 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
581 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
582 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
583 if (window_space)
584 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
585 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
586 else
587 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
588 S_028818_VTX_W0_FMT(1) |
589 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
590 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
591 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
592
593 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
594 si_set_tesseval_regs(sscreen, shader, pm4);
595 }
596
597 static unsigned si_get_ps_num_interp(struct si_shader *ps)
598 {
599 struct tgsi_shader_info *info = &ps->selector->info;
600 unsigned num_colors = !!(info->colors_read & 0x0f) +
601 !!(info->colors_read & 0xf0);
602 unsigned num_interp = ps->selector->info.num_inputs +
603 (ps->key.ps.prolog.color_two_side ? num_colors : 0);
604
605 assert(num_interp <= 32);
606 return MIN2(num_interp, 32);
607 }
608
609 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
610 {
611 unsigned value = shader->key.ps.epilog.spi_shader_col_format;
612 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
613
614 /* If the i-th target format is set, all previous target formats must
615 * be non-zero to avoid hangs.
616 */
617 for (i = 0; i < num_targets; i++)
618 if (!(value & (0xf << (i * 4))))
619 value |= V_028714_SPI_SHADER_32_R << (i * 4);
620
621 return value;
622 }
623
624 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
625 {
626 unsigned i, cb_shader_mask = 0;
627
628 for (i = 0; i < 8; i++) {
629 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
630 case V_028714_SPI_SHADER_ZERO:
631 break;
632 case V_028714_SPI_SHADER_32_R:
633 cb_shader_mask |= 0x1 << (i * 4);
634 break;
635 case V_028714_SPI_SHADER_32_GR:
636 cb_shader_mask |= 0x3 << (i * 4);
637 break;
638 case V_028714_SPI_SHADER_32_AR:
639 cb_shader_mask |= 0x9 << (i * 4);
640 break;
641 case V_028714_SPI_SHADER_FP16_ABGR:
642 case V_028714_SPI_SHADER_UNORM16_ABGR:
643 case V_028714_SPI_SHADER_SNORM16_ABGR:
644 case V_028714_SPI_SHADER_UINT16_ABGR:
645 case V_028714_SPI_SHADER_SINT16_ABGR:
646 case V_028714_SPI_SHADER_32_ABGR:
647 cb_shader_mask |= 0xf << (i * 4);
648 break;
649 default:
650 assert(0);
651 }
652 }
653 return cb_shader_mask;
654 }
655
656 static void si_shader_ps(struct si_shader *shader)
657 {
658 struct tgsi_shader_info *info = &shader->selector->info;
659 struct si_pm4_state *pm4;
660 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
661 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
662 uint64_t va;
663 bool has_centroid;
664 unsigned input_ena = shader->config.spi_ps_input_ena;
665
666 /* we need to enable at least one of them, otherwise we hang the GPU */
667 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
668 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
669 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
670 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
671 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
672 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
673 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
674 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
675
676 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
677
678 if (!pm4)
679 return;
680
681 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
682 * Possible vaules:
683 * 0 -> Position = pixel center
684 * 1 -> Position = pixel centroid
685 * 2 -> Position = at sample position
686 *
687 * From GLSL 4.5 specification, section 7.1:
688 * "The variable gl_FragCoord is available as an input variable from
689 * within fragment shaders and it holds the window relative coordinates
690 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
691 * value can be for any location within the pixel, or one of the
692 * fragment samples. The use of centroid does not further restrict
693 * this value to be inside the current primitive."
694 *
695 * Meaning that centroid has no effect and we can return anything within
696 * the pixel. Thus, return the value at sample position, because that's
697 * the most accurate one shaders can get.
698 */
699 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
700
701 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
702 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
703 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
704
705 spi_shader_col_format = si_get_spi_shader_col_format(shader);
706 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
707
708 /* Ensure that some export memory is always allocated, for two reasons:
709 *
710 * 1) Correctness: The hardware ignores the EXEC mask if no export
711 * memory is allocated, so KILL and alpha test do not work correctly
712 * without this.
713 * 2) Performance: Every shader needs at least a NULL export, even when
714 * it writes no color/depth output. The NULL export instruction
715 * stalls without this setting.
716 *
717 * Don't add this to CB_SHADER_MASK.
718 */
719 if (!spi_shader_col_format &&
720 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
721 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
722
723 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
724 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
725 shader->config.spi_ps_input_addr);
726
727 /* Set interpolation controls. */
728 has_centroid = G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena) ||
729 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena);
730
731 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
732 S_0286D8_BC_OPTIMIZE_DISABLE(has_centroid);
733
734 /* Set registers. */
735 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
736 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
737
738 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
739 info->writes_samplemask ? V_028710_SPI_SHADER_32_ABGR :
740 info->writes_stencil ? V_028710_SPI_SHADER_32_GR :
741 info->writes_z ? V_028710_SPI_SHADER_32_R :
742 V_028710_SPI_SHADER_ZERO);
743
744 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
745 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
746
747 va = shader->bo->gpu_address;
748 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
749 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
750 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
751
752 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
753 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
754 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
755 S_00B028_DX10_CLAMP(1) |
756 S_00B028_FLOAT_MODE(shader->config.float_mode));
757 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
758 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
759 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
760 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
761
762 /* Prefer RE_Z if the shader is complex enough. The requirement is either:
763 * - the shader uses at least 2 VMEM instructions, or
764 * - the code size is at least 50 2-dword instructions or 100 1-dword
765 * instructions.
766 *
767 * Shaders with side effects that must execute independently of the
768 * depth test require LATE_Z.
769 */
770 if (info->writes_memory &&
771 !info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL])
772 shader->z_order = V_02880C_LATE_Z;
773 else if (info->num_memory_instructions >= 2 ||
774 shader->binary.code_size > 100*4)
775 shader->z_order = V_02880C_EARLY_Z_THEN_RE_Z;
776 else
777 shader->z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
778 }
779
780 static void si_shader_init_pm4_state(struct si_screen *sscreen,
781 struct si_shader *shader)
782 {
783
784 if (shader->pm4)
785 si_pm4_free_state_simple(shader->pm4);
786
787 switch (shader->selector->type) {
788 case PIPE_SHADER_VERTEX:
789 if (shader->key.vs.as_ls)
790 si_shader_ls(shader);
791 else if (shader->key.vs.as_es)
792 si_shader_es(sscreen, shader);
793 else
794 si_shader_vs(sscreen, shader, NULL);
795 break;
796 case PIPE_SHADER_TESS_CTRL:
797 si_shader_hs(shader);
798 break;
799 case PIPE_SHADER_TESS_EVAL:
800 if (shader->key.tes.as_es)
801 si_shader_es(sscreen, shader);
802 else
803 si_shader_vs(sscreen, shader, NULL);
804 break;
805 case PIPE_SHADER_GEOMETRY:
806 si_shader_gs(shader);
807 si_shader_vs(sscreen, shader->gs_copy_shader, shader);
808 break;
809 case PIPE_SHADER_FRAGMENT:
810 si_shader_ps(shader);
811 break;
812 default:
813 assert(0);
814 }
815 }
816
817 static unsigned si_get_alpha_test_func(struct si_context *sctx)
818 {
819 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
820 if (sctx->queued.named.dsa &&
821 !sctx->framebuffer.cb0_is_integer)
822 return sctx->queued.named.dsa->alpha_func;
823
824 return PIPE_FUNC_ALWAYS;
825 }
826
827 /* Compute the key for the hw shader variant */
828 static inline void si_shader_selector_key(struct pipe_context *ctx,
829 struct si_shader_selector *sel,
830 union si_shader_key *key)
831 {
832 struct si_context *sctx = (struct si_context *)ctx;
833 unsigned i;
834
835 memset(key, 0, sizeof(*key));
836
837 switch (sel->type) {
838 case PIPE_SHADER_VERTEX:
839 if (sctx->vertex_elements) {
840 unsigned count = MIN2(sel->info.num_inputs,
841 sctx->vertex_elements->count);
842 for (i = 0; i < count; ++i)
843 key->vs.prolog.instance_divisors[i] =
844 sctx->vertex_elements->elements[i].instance_divisor;
845 }
846 if (sctx->tes_shader.cso)
847 key->vs.as_ls = 1;
848 else if (sctx->gs_shader.cso)
849 key->vs.as_es = 1;
850
851 if (!sctx->gs_shader.cso && sctx->ps_shader.cso &&
852 sctx->ps_shader.cso->info.uses_primid)
853 key->vs.epilog.export_prim_id = 1;
854 break;
855 case PIPE_SHADER_TESS_CTRL:
856 key->tcs.epilog.prim_mode =
857 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
858
859 if (sel == sctx->fixed_func_tcs_shader.cso)
860 key->tcs.epilog.inputs_to_copy = sctx->vs_shader.cso->outputs_written;
861 break;
862 case PIPE_SHADER_TESS_EVAL:
863 if (sctx->gs_shader.cso)
864 key->tes.as_es = 1;
865 else if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
866 key->tes.epilog.export_prim_id = 1;
867 break;
868 case PIPE_SHADER_GEOMETRY:
869 break;
870 case PIPE_SHADER_FRAGMENT: {
871 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
872 struct si_state_blend *blend = sctx->queued.named.blend;
873
874 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
875 sel->info.colors_written == 0x1)
876 key->ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
877
878 if (blend) {
879 /* Select the shader color format based on whether
880 * blending or alpha are needed.
881 */
882 key->ps.epilog.spi_shader_col_format =
883 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
884 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
885 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
886 sctx->framebuffer.spi_shader_col_format_blend) |
887 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
888 sctx->framebuffer.spi_shader_col_format_alpha) |
889 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
890 sctx->framebuffer.spi_shader_col_format);
891 } else
892 key->ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
893
894 /* If alpha-to-coverage is enabled, we have to export alpha
895 * even if there is no color buffer.
896 */
897 if (!(key->ps.epilog.spi_shader_col_format & 0xf) &&
898 blend && blend->alpha_to_coverage)
899 key->ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
900
901 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
902 * to the range supported by the type if a channel has less
903 * than 16 bits and the export format is 16_ABGR.
904 */
905 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII)
906 key->ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
907
908 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
909 if (!key->ps.epilog.last_cbuf) {
910 key->ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
911 key->ps.epilog.color_is_int8 &= sel->info.colors_written;
912 }
913
914 if (rs) {
915 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
916 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
917 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
918 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
919
920 key->ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
921
922 if (sctx->queued.named.blend) {
923 key->ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
924 rs->multisample_enable &&
925 !sctx->framebuffer.cb0_is_integer;
926 }
927
928 key->ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
929 key->ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
930 (is_line && rs->line_smooth)) &&
931 sctx->framebuffer.nr_samples <= 1;
932 key->ps.epilog.clamp_color = rs->clamp_fragment_color;
933
934 key->ps.prolog.force_persample_interp =
935 rs->force_persample_interp &&
936 rs->multisample_enable &&
937 sctx->framebuffer.nr_samples > 1 &&
938 sctx->ps_iter_samples > 1 &&
939 (sel->info.uses_persp_center ||
940 sel->info.uses_persp_centroid ||
941 sel->info.uses_linear_center ||
942 sel->info.uses_linear_centroid);
943 }
944
945 key->ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
946 break;
947 }
948 default:
949 assert(0);
950 }
951 }
952
953 /* Select the hw shader variant depending on the current state. */
954 static int si_shader_select_with_key(struct pipe_context *ctx,
955 struct si_shader_ctx_state *state,
956 union si_shader_key *key)
957 {
958 struct si_context *sctx = (struct si_context *)ctx;
959 struct si_shader_selector *sel = state->cso;
960 struct si_shader *current = state->current;
961 struct si_shader *iter, *shader = NULL;
962 int r;
963
964 /* Check if we don't need to change anything.
965 * This path is also used for most shaders that don't need multiple
966 * variants, it will cost just a computation of the key and this
967 * test. */
968 if (likely(current && memcmp(&current->key, key, sizeof(*key)) == 0))
969 return 0;
970
971 pipe_mutex_lock(sel->mutex);
972
973 /* Find the shader variant. */
974 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
975 /* Don't check the "current" shader. We checked it above. */
976 if (current != iter &&
977 memcmp(&iter->key, key, sizeof(*key)) == 0) {
978 state->current = iter;
979 pipe_mutex_unlock(sel->mutex);
980 return 0;
981 }
982 }
983
984 /* Build a new shader. */
985 shader = CALLOC_STRUCT(si_shader);
986 if (!shader) {
987 pipe_mutex_unlock(sel->mutex);
988 return -ENOMEM;
989 }
990 shader->selector = sel;
991 shader->key = *key;
992
993 r = si_shader_create(sctx->screen, sctx->tm, shader, &sctx->b.debug);
994 if (unlikely(r)) {
995 R600_ERR("Failed to build shader variant (type=%u) %d\n",
996 sel->type, r);
997 FREE(shader);
998 pipe_mutex_unlock(sel->mutex);
999 return r;
1000 }
1001 si_shader_init_pm4_state(sctx->screen, shader);
1002
1003 if (!sel->last_variant) {
1004 sel->first_variant = shader;
1005 sel->last_variant = shader;
1006 } else {
1007 sel->last_variant->next_variant = shader;
1008 sel->last_variant = shader;
1009 }
1010 state->current = shader;
1011 pipe_mutex_unlock(sel->mutex);
1012 return 0;
1013 }
1014
1015 static int si_shader_select(struct pipe_context *ctx,
1016 struct si_shader_ctx_state *state)
1017 {
1018 union si_shader_key key;
1019
1020 si_shader_selector_key(ctx, state->cso, &key);
1021 return si_shader_select_with_key(ctx, state, &key);
1022 }
1023
1024 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1025 union si_shader_key *key)
1026 {
1027 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1028
1029 switch (info->processor) {
1030 case PIPE_SHADER_VERTEX:
1031 switch (next_shader) {
1032 case PIPE_SHADER_GEOMETRY:
1033 key->vs.as_es = 1;
1034 break;
1035 case PIPE_SHADER_TESS_CTRL:
1036 case PIPE_SHADER_TESS_EVAL:
1037 key->vs.as_ls = 1;
1038 break;
1039 }
1040 break;
1041
1042 case PIPE_SHADER_TESS_EVAL:
1043 if (next_shader == PIPE_SHADER_GEOMETRY)
1044 key->tes.as_es = 1;
1045 break;
1046 }
1047 }
1048
1049 static void *si_create_shader_selector(struct pipe_context *ctx,
1050 const struct pipe_shader_state *state)
1051 {
1052 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1053 struct si_context *sctx = (struct si_context*)ctx;
1054 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
1055 int i;
1056
1057 if (!sel)
1058 return NULL;
1059
1060 sel->tokens = tgsi_dup_tokens(state->tokens);
1061 if (!sel->tokens) {
1062 FREE(sel);
1063 return NULL;
1064 }
1065
1066 sel->so = state->stream_output;
1067 tgsi_scan_shader(state->tokens, &sel->info);
1068 sel->type = sel->info.processor;
1069 p_atomic_inc(&sscreen->b.num_shaders_created);
1070
1071 /* Set which opcode uses which (i,j) pair. */
1072 if (sel->info.uses_persp_opcode_interp_centroid)
1073 sel->info.uses_persp_centroid = true;
1074
1075 if (sel->info.uses_linear_opcode_interp_centroid)
1076 sel->info.uses_linear_centroid = true;
1077
1078 if (sel->info.uses_persp_opcode_interp_offset ||
1079 sel->info.uses_persp_opcode_interp_sample)
1080 sel->info.uses_persp_center = true;
1081
1082 if (sel->info.uses_linear_opcode_interp_offset ||
1083 sel->info.uses_linear_opcode_interp_sample)
1084 sel->info.uses_linear_center = true;
1085
1086 switch (sel->type) {
1087 case PIPE_SHADER_GEOMETRY:
1088 sel->gs_output_prim =
1089 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
1090 sel->gs_max_out_vertices =
1091 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
1092 sel->gs_num_invocations =
1093 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
1094 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
1095 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
1096 sel->gs_max_out_vertices;
1097
1098 sel->max_gs_stream = 0;
1099 for (i = 0; i < sel->so.num_outputs; i++)
1100 sel->max_gs_stream = MAX2(sel->max_gs_stream,
1101 sel->so.output[i].stream);
1102
1103 sel->gs_input_verts_per_prim =
1104 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
1105 break;
1106
1107 case PIPE_SHADER_TESS_CTRL:
1108 /* Always reserve space for these. */
1109 sel->patch_outputs_written |=
1110 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0)) |
1111 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0));
1112 /* fall through */
1113 case PIPE_SHADER_VERTEX:
1114 case PIPE_SHADER_TESS_EVAL:
1115 for (i = 0; i < sel->info.num_outputs; i++) {
1116 unsigned name = sel->info.output_semantic_name[i];
1117 unsigned index = sel->info.output_semantic_index[i];
1118
1119 switch (name) {
1120 case TGSI_SEMANTIC_TESSINNER:
1121 case TGSI_SEMANTIC_TESSOUTER:
1122 case TGSI_SEMANTIC_PATCH:
1123 sel->patch_outputs_written |=
1124 1llu << si_shader_io_get_unique_index(name, index);
1125 break;
1126 default:
1127 sel->outputs_written |=
1128 1llu << si_shader_io_get_unique_index(name, index);
1129 }
1130 }
1131 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
1132 break;
1133
1134 case PIPE_SHADER_FRAGMENT:
1135 for (i = 0; i < 8; i++)
1136 if (sel->info.colors_written & (1 << i))
1137 sel->colors_written_4bit |= 0xf << (4 * i);
1138
1139 for (i = 0; i < sel->info.num_inputs; i++) {
1140 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
1141 int index = sel->info.input_semantic_index[i];
1142 sel->color_attr_index[index] = i;
1143 }
1144 }
1145 break;
1146 }
1147
1148 /* DB_SHADER_CONTROL */
1149 sel->db_shader_control =
1150 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
1151 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
1152 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
1153 S_02880C_KILL_ENABLE(sel->info.uses_kill);
1154
1155 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
1156 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1157 sel->db_shader_control |=
1158 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
1159 break;
1160 case TGSI_FS_DEPTH_LAYOUT_LESS:
1161 sel->db_shader_control |=
1162 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
1163 break;
1164 }
1165
1166 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL])
1167 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1);
1168
1169 if (sel->info.writes_memory)
1170 sel->db_shader_control |= S_02880C_EXEC_ON_HIER_FAIL(1) |
1171 S_02880C_EXEC_ON_NOOP(1);
1172
1173 /* Compile the main shader part for use with a prolog and/or epilog. */
1174 if (sel->type != PIPE_SHADER_GEOMETRY &&
1175 !sscreen->use_monolithic_shaders) {
1176 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1177 void *tgsi_binary;
1178
1179 if (!shader)
1180 goto error;
1181
1182 shader->selector = sel;
1183 si_parse_next_shader_property(&sel->info, &shader->key);
1184
1185 tgsi_binary = si_get_tgsi_binary(sel);
1186
1187 /* Try to load the shader from the shader cache. */
1188 pipe_mutex_lock(sscreen->shader_cache_mutex);
1189
1190 if (tgsi_binary &&
1191 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1192 FREE(tgsi_binary);
1193 } else {
1194 /* Compile the shader if it hasn't been loaded from the cache. */
1195 if (si_compile_tgsi_shader(sscreen, sctx->tm, shader, false,
1196 &sctx->b.debug) != 0) {
1197 FREE(shader);
1198 FREE(tgsi_binary);
1199 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1200 goto error;
1201 }
1202
1203 if (tgsi_binary &&
1204 !si_shader_cache_insert_shader(sscreen, tgsi_binary, shader))
1205 FREE(tgsi_binary);
1206 }
1207 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1208
1209 sel->main_shader_part = shader;
1210 }
1211
1212 /* Pre-compilation. */
1213 if (sel->type == PIPE_SHADER_GEOMETRY ||
1214 sscreen->b.debug_flags & DBG_PRECOMPILE) {
1215 struct si_shader_ctx_state state = {sel};
1216 union si_shader_key key;
1217
1218 memset(&key, 0, sizeof(key));
1219 si_parse_next_shader_property(&sel->info, &key);
1220
1221 /* Set reasonable defaults, so that the shader key doesn't
1222 * cause any code to be eliminated.
1223 */
1224 switch (sel->type) {
1225 case PIPE_SHADER_TESS_CTRL:
1226 key.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1227 break;
1228 case PIPE_SHADER_FRAGMENT:
1229 key.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1230 for (i = 0; i < 8; i++)
1231 if (sel->info.colors_written & (1 << i))
1232 key.ps.epilog.spi_shader_col_format |=
1233 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1234 break;
1235 }
1236
1237 if (si_shader_select_with_key(ctx, &state, &key))
1238 goto error;
1239 }
1240
1241 pipe_mutex_init(sel->mutex);
1242 return sel;
1243
1244 error:
1245 fprintf(stderr, "radeonsi: can't create a shader\n");
1246 tgsi_free_tokens(sel->tokens);
1247 FREE(sel);
1248 return NULL;
1249 }
1250
1251 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1252 {
1253 struct si_context *sctx = (struct si_context *)ctx;
1254 struct si_shader_selector *sel = state;
1255
1256 if (sctx->vs_shader.cso == sel)
1257 return;
1258
1259 sctx->vs_shader.cso = sel;
1260 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
1261 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1262 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1263 }
1264
1265 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
1266 {
1267 struct si_context *sctx = (struct si_context *)ctx;
1268 struct si_shader_selector *sel = state;
1269 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
1270
1271 if (sctx->gs_shader.cso == sel)
1272 return;
1273
1274 sctx->gs_shader.cso = sel;
1275 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
1276 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1277 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1278
1279 if (enable_changed)
1280 si_shader_change_notify(sctx);
1281 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1282 }
1283
1284 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
1285 {
1286 struct si_context *sctx = (struct si_context *)ctx;
1287 struct si_shader_selector *sel = state;
1288 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
1289
1290 if (sctx->tcs_shader.cso == sel)
1291 return;
1292
1293 sctx->tcs_shader.cso = sel;
1294 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
1295
1296 if (enable_changed)
1297 sctx->last_tcs = NULL; /* invalidate derived tess state */
1298 }
1299
1300 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
1301 {
1302 struct si_context *sctx = (struct si_context *)ctx;
1303 struct si_shader_selector *sel = state;
1304 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
1305
1306 if (sctx->tes_shader.cso == sel)
1307 return;
1308
1309 sctx->tes_shader.cso = sel;
1310 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
1311 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1312 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1313
1314 if (enable_changed) {
1315 si_shader_change_notify(sctx);
1316 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
1317 }
1318 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1319 }
1320
1321 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1322 {
1323 struct si_context *sctx = (struct si_context *)ctx;
1324 struct si_shader_selector *sel = state;
1325
1326 /* skip if supplied shader is one already in use */
1327 if (sctx->ps_shader.cso == sel)
1328 return;
1329
1330 sctx->ps_shader.cso = sel;
1331 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
1332 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
1333 }
1334
1335 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
1336 {
1337 if (shader->pm4) {
1338 switch (shader->selector->type) {
1339 case PIPE_SHADER_VERTEX:
1340 if (shader->key.vs.as_ls)
1341 si_pm4_delete_state(sctx, ls, shader->pm4);
1342 else if (shader->key.vs.as_es)
1343 si_pm4_delete_state(sctx, es, shader->pm4);
1344 else
1345 si_pm4_delete_state(sctx, vs, shader->pm4);
1346 break;
1347 case PIPE_SHADER_TESS_CTRL:
1348 si_pm4_delete_state(sctx, hs, shader->pm4);
1349 break;
1350 case PIPE_SHADER_TESS_EVAL:
1351 if (shader->key.tes.as_es)
1352 si_pm4_delete_state(sctx, es, shader->pm4);
1353 else
1354 si_pm4_delete_state(sctx, vs, shader->pm4);
1355 break;
1356 case PIPE_SHADER_GEOMETRY:
1357 si_pm4_delete_state(sctx, gs, shader->pm4);
1358 si_pm4_delete_state(sctx, vs, shader->gs_copy_shader->pm4);
1359 break;
1360 case PIPE_SHADER_FRAGMENT:
1361 si_pm4_delete_state(sctx, ps, shader->pm4);
1362 break;
1363 }
1364 }
1365
1366 si_shader_destroy(shader);
1367 free(shader);
1368 }
1369
1370 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
1371 {
1372 struct si_context *sctx = (struct si_context *)ctx;
1373 struct si_shader_selector *sel = (struct si_shader_selector *)state;
1374 struct si_shader *p = sel->first_variant, *c;
1375 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
1376 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
1377 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
1378 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
1379 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
1380 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
1381 };
1382
1383 if (current_shader[sel->type]->cso == sel) {
1384 current_shader[sel->type]->cso = NULL;
1385 current_shader[sel->type]->current = NULL;
1386 }
1387
1388 while (p) {
1389 c = p->next_variant;
1390 si_delete_shader(sctx, p);
1391 p = c;
1392 }
1393
1394 if (sel->main_shader_part)
1395 si_delete_shader(sctx, sel->main_shader_part);
1396
1397 pipe_mutex_destroy(sel->mutex);
1398 free(sel->tokens);
1399 free(sel);
1400 }
1401
1402 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
1403 struct si_shader *vs, unsigned name,
1404 unsigned index, unsigned interpolate)
1405 {
1406 struct tgsi_shader_info *vsinfo = &vs->selector->info;
1407 unsigned j, ps_input_cntl = 0;
1408
1409 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
1410 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
1411 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1412
1413 if (name == TGSI_SEMANTIC_PCOORD ||
1414 (name == TGSI_SEMANTIC_TEXCOORD &&
1415 sctx->sprite_coord_enable & (1 << index))) {
1416 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
1417 }
1418
1419 for (j = 0; j < vsinfo->num_outputs; j++) {
1420 if (name == vsinfo->output_semantic_name[j] &&
1421 index == vsinfo->output_semantic_index[j]) {
1422 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[j]);
1423 break;
1424 }
1425 }
1426
1427 if (name == TGSI_SEMANTIC_PRIMID)
1428 /* PrimID is written after the last output. */
1429 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
1430 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
1431 /* No corresponding output found, load defaults into input.
1432 * Don't set any other bits.
1433 * (FLAT_SHADE=1 completely changes behavior) */
1434 ps_input_cntl = S_028644_OFFSET(0x20);
1435 /* D3D 9 behaviour. GL is undefined */
1436 if (name == TGSI_SEMANTIC_COLOR && index == 0)
1437 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
1438 }
1439 return ps_input_cntl;
1440 }
1441
1442 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
1443 {
1444 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1445 struct si_shader *ps = sctx->ps_shader.current;
1446 struct si_shader *vs = si_get_vs_state(sctx);
1447 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
1448 unsigned i, num_interp, num_written = 0, bcol_interp[2];
1449
1450 if (!ps || !ps->selector->info.num_inputs)
1451 return;
1452
1453 num_interp = si_get_ps_num_interp(ps);
1454 assert(num_interp > 0);
1455 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
1456
1457 for (i = 0; i < psinfo->num_inputs; i++) {
1458 unsigned name = psinfo->input_semantic_name[i];
1459 unsigned index = psinfo->input_semantic_index[i];
1460 unsigned interpolate = psinfo->input_interpolate[i];
1461
1462 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
1463 interpolate));
1464 num_written++;
1465
1466 if (name == TGSI_SEMANTIC_COLOR) {
1467 assert(index < ARRAY_SIZE(bcol_interp));
1468 bcol_interp[index] = interpolate;
1469 }
1470 }
1471
1472 if (ps->key.ps.prolog.color_two_side) {
1473 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
1474
1475 for (i = 0; i < 2; i++) {
1476 if (!(psinfo->colors_read & (0xf << (i * 4))))
1477 continue;
1478
1479 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
1480 i, bcol_interp[i]));
1481 num_written++;
1482 }
1483 }
1484 assert(num_interp == num_written);
1485 }
1486
1487 /**
1488 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1489 */
1490 static void si_init_config_add_vgt_flush(struct si_context *sctx)
1491 {
1492 if (sctx->init_config_has_vgt_flush)
1493 return;
1494
1495 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
1496 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
1497 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1498 si_pm4_cmd_end(sctx->init_config, false);
1499 sctx->init_config_has_vgt_flush = true;
1500 }
1501
1502 /* Initialize state related to ESGS / GSVS ring buffers */
1503 static bool si_update_gs_ring_buffers(struct si_context *sctx)
1504 {
1505 struct si_shader_selector *es =
1506 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
1507 struct si_shader_selector *gs = sctx->gs_shader.cso;
1508 struct si_pm4_state *pm4;
1509
1510 /* Chip constants. */
1511 unsigned num_se = sctx->screen->b.info.max_se;
1512 unsigned wave_size = 64;
1513 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1514 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1515 unsigned alignment = 256 * num_se;
1516 /* The maximum size is 63.999 MB per SE. */
1517 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1518
1519 /* Calculate the minimum size. */
1520 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
1521 wave_size, alignment);
1522
1523 /* These are recommended sizes, not minimum sizes. */
1524 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1525 es->esgs_itemsize * gs->gs_input_verts_per_prim;
1526 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1527 gs->max_gsvs_emit_size * (gs->max_gs_stream + 1);
1528
1529 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1530 esgs_ring_size = align(esgs_ring_size, alignment);
1531 gsvs_ring_size = align(gsvs_ring_size, alignment);
1532
1533 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1534 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1535
1536 /* Some rings don't have to be allocated if shaders don't use them.
1537 * (e.g. no varyings between ES and GS or GS and VS)
1538 */
1539 bool update_esgs = esgs_ring_size &&
1540 (!sctx->esgs_ring ||
1541 sctx->esgs_ring->width0 < esgs_ring_size);
1542 bool update_gsvs = gsvs_ring_size &&
1543 (!sctx->gsvs_ring ||
1544 sctx->gsvs_ring->width0 < gsvs_ring_size);
1545
1546 if (!update_esgs && !update_gsvs)
1547 return true;
1548
1549 if (update_esgs) {
1550 pipe_resource_reference(&sctx->esgs_ring, NULL);
1551 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1552 PIPE_USAGE_DEFAULT,
1553 esgs_ring_size);
1554 if (!sctx->esgs_ring)
1555 return false;
1556 }
1557
1558 if (update_gsvs) {
1559 pipe_resource_reference(&sctx->gsvs_ring, NULL);
1560 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1561 PIPE_USAGE_DEFAULT,
1562 gsvs_ring_size);
1563 if (!sctx->gsvs_ring)
1564 return false;
1565 }
1566
1567 /* Create the "init_config_gs_rings" state. */
1568 pm4 = CALLOC_STRUCT(si_pm4_state);
1569 if (!pm4)
1570 return false;
1571
1572 if (sctx->b.chip_class >= CIK) {
1573 if (sctx->esgs_ring)
1574 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
1575 sctx->esgs_ring->width0 / 256);
1576 if (sctx->gsvs_ring)
1577 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
1578 sctx->gsvs_ring->width0 / 256);
1579 } else {
1580 if (sctx->esgs_ring)
1581 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
1582 sctx->esgs_ring->width0 / 256);
1583 if (sctx->gsvs_ring)
1584 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
1585 sctx->gsvs_ring->width0 / 256);
1586 }
1587
1588 /* Set the state. */
1589 if (sctx->init_config_gs_rings)
1590 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
1591 sctx->init_config_gs_rings = pm4;
1592
1593 if (!sctx->init_config_has_vgt_flush) {
1594 si_init_config_add_vgt_flush(sctx);
1595 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1596 }
1597
1598 /* Flush the context to re-emit both init_config states. */
1599 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1600 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1601
1602 /* Set ring bindings. */
1603 if (sctx->esgs_ring) {
1604 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
1605 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1606 true, true, 4, 64, 0);
1607 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
1608 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1609 false, false, 0, 0, 0);
1610 }
1611 if (sctx->gsvs_ring)
1612 si_set_ring_buffer(&sctx->b.b, SI_VS_RING_GSVS,
1613 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
1614 false, false, 0, 0, 0);
1615 return true;
1616 }
1617
1618 static void si_update_gsvs_ring_bindings(struct si_context *sctx)
1619 {
1620 unsigned gsvs_itemsize = sctx->gs_shader.cso->max_gsvs_emit_size;
1621 uint64_t offset;
1622
1623 if (!sctx->gsvs_ring || gsvs_itemsize == sctx->last_gsvs_itemsize)
1624 return;
1625
1626 sctx->last_gsvs_itemsize = gsvs_itemsize;
1627
1628 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS0,
1629 sctx->gsvs_ring, gsvs_itemsize,
1630 64, true, true, 4, 16, 0);
1631
1632 offset = gsvs_itemsize * 64;
1633 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS1,
1634 sctx->gsvs_ring, gsvs_itemsize,
1635 64, true, true, 4, 16, offset);
1636
1637 offset = (gsvs_itemsize * 2) * 64;
1638 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS2,
1639 sctx->gsvs_ring, gsvs_itemsize,
1640 64, true, true, 4, 16, offset);
1641
1642 offset = (gsvs_itemsize * 3) * 64;
1643 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS3,
1644 sctx->gsvs_ring, gsvs_itemsize,
1645 64, true, true, 4, 16, offset);
1646 }
1647
1648 /**
1649 * @returns 1 if \p sel has been updated to use a new scratch buffer
1650 * 0 if not
1651 * < 0 if there was a failure
1652 */
1653 static int si_update_scratch_buffer(struct si_context *sctx,
1654 struct si_shader *shader)
1655 {
1656 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
1657 int r;
1658
1659 if (!shader)
1660 return 0;
1661
1662 /* This shader doesn't need a scratch buffer */
1663 if (shader->config.scratch_bytes_per_wave == 0)
1664 return 0;
1665
1666 /* This shader is already configured to use the current
1667 * scratch buffer. */
1668 if (shader->scratch_bo == sctx->scratch_buffer)
1669 return 0;
1670
1671 assert(sctx->scratch_buffer);
1672
1673 si_shader_apply_scratch_relocs(sctx, shader, &shader->config, scratch_va);
1674
1675 /* Replace the shader bo with a new bo that has the relocs applied. */
1676 r = si_shader_binary_upload(sctx->screen, shader);
1677 if (r)
1678 return r;
1679
1680 /* Update the shader state to use the new shader bo. */
1681 si_shader_init_pm4_state(sctx->screen, shader);
1682
1683 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
1684
1685 return 1;
1686 }
1687
1688 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
1689 {
1690 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
1691 }
1692
1693 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
1694 {
1695 return shader ? shader->config.scratch_bytes_per_wave : 0;
1696 }
1697
1698 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
1699 {
1700 unsigned bytes = 0;
1701
1702 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
1703 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
1704 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
1705 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
1706 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
1707 return bytes;
1708 }
1709
1710 static bool si_update_spi_tmpring_size(struct si_context *sctx)
1711 {
1712 unsigned current_scratch_buffer_size =
1713 si_get_current_scratch_buffer_size(sctx);
1714 unsigned scratch_bytes_per_wave =
1715 si_get_max_scratch_bytes_per_wave(sctx);
1716 unsigned scratch_needed_size = scratch_bytes_per_wave *
1717 sctx->scratch_waves;
1718 unsigned spi_tmpring_size;
1719 int r;
1720
1721 if (scratch_needed_size > 0) {
1722 if (scratch_needed_size > current_scratch_buffer_size) {
1723 /* Create a bigger scratch buffer */
1724 pipe_resource_reference(
1725 (struct pipe_resource**)&sctx->scratch_buffer,
1726 NULL);
1727
1728 sctx->scratch_buffer =
1729 si_resource_create_custom(&sctx->screen->b.b,
1730 PIPE_USAGE_DEFAULT, scratch_needed_size);
1731 if (!sctx->scratch_buffer)
1732 return false;
1733 sctx->emit_scratch_reloc = true;
1734 }
1735
1736 /* Update the shaders, so they are using the latest scratch. The
1737 * scratch buffer may have been changed since these shaders were
1738 * last used, so we still need to try to update them, even if
1739 * they require scratch buffers smaller than the current size.
1740 */
1741 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
1742 if (r < 0)
1743 return false;
1744 if (r == 1)
1745 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1746
1747 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
1748 if (r < 0)
1749 return false;
1750 if (r == 1)
1751 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1752
1753 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
1754 if (r < 0)
1755 return false;
1756 if (r == 1)
1757 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1758
1759 /* VS can be bound as LS, ES, or VS. */
1760 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
1761 if (r < 0)
1762 return false;
1763 if (r == 1) {
1764 if (sctx->tes_shader.current)
1765 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1766 else if (sctx->gs_shader.current)
1767 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1768 else
1769 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1770 }
1771
1772 /* TES can be bound as ES or VS. */
1773 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
1774 if (r < 0)
1775 return false;
1776 if (r == 1) {
1777 if (sctx->gs_shader.current)
1778 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1779 else
1780 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1781 }
1782 }
1783
1784 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1785 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
1786 "scratch size should already be aligned correctly.");
1787
1788 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
1789 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
1790 if (spi_tmpring_size != sctx->spi_tmpring_size) {
1791 sctx->spi_tmpring_size = spi_tmpring_size;
1792 sctx->emit_scratch_reloc = true;
1793 }
1794 return true;
1795 }
1796
1797 static void si_init_tess_factor_ring(struct si_context *sctx)
1798 {
1799 unsigned offchip_blocks = sctx->b.chip_class >= CIK ? 256 : 64;
1800 assert(!sctx->tf_ring);
1801
1802 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1803 PIPE_USAGE_DEFAULT,
1804 32768 * sctx->screen->b.info.max_se);
1805 if (!sctx->tf_ring)
1806 return;
1807
1808 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
1809
1810 sctx->tess_offchip_ring = pipe_buffer_create(sctx->b.b.screen,
1811 PIPE_BIND_CUSTOM,
1812 PIPE_USAGE_DEFAULT,
1813 offchip_blocks *
1814 SI_TESS_OFFCHIP_BLOCK_SIZE);
1815 if (!sctx->tess_offchip_ring)
1816 return;
1817
1818 si_init_config_add_vgt_flush(sctx);
1819
1820 /* Append these registers to the init config state. */
1821 if (sctx->b.chip_class >= CIK) {
1822 unsigned offchip_buffering = offchip_blocks;
1823 if(sctx->b.chip_class >= VI)
1824 --offchip_buffering;
1825
1826 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
1827 S_030938_SIZE(sctx->tf_ring->width0 / 4));
1828 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
1829 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1830 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
1831 S_03093C_OFFCHIP_BUFFERING(offchip_buffering) |
1832 S_03093C_OFFCHIP_GRANULARITY(V_03093C_X_8K_DWORDS));
1833 } else {
1834 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
1835 S_008988_SIZE(sctx->tf_ring->width0 / 4));
1836 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
1837 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1838 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1839 S_0089B0_OFFCHIP_BUFFERING(offchip_blocks));
1840 }
1841
1842 /* Flush the context to re-emit the init_config state.
1843 * This is done only once in a lifetime of a context.
1844 */
1845 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1846 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1847 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1848
1849 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_FACTOR, sctx->tf_ring,
1850 0, sctx->tf_ring->width0, false, false, 0, 0, 0);
1851
1852 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_OFFCHIP,
1853 sctx->tess_offchip_ring, 0,
1854 sctx->tess_offchip_ring->width0, false, false, 0, 0, 0);
1855 }
1856
1857 /**
1858 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
1859 * VS passes its outputs to TES directly, so the fixed-function shader only
1860 * has to write TESSOUTER and TESSINNER.
1861 */
1862 static void si_generate_fixed_func_tcs(struct si_context *sctx)
1863 {
1864 struct ureg_src outer, inner;
1865 struct ureg_dst tessouter, tessinner;
1866 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
1867
1868 if (!ureg)
1869 return; /* if we get here, we're screwed */
1870
1871 assert(!sctx->fixed_func_tcs_shader.cso);
1872
1873 outer = ureg_DECL_system_value(ureg,
1874 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
1875 inner = ureg_DECL_system_value(ureg,
1876 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
1877
1878 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1879 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1880
1881 ureg_MOV(ureg, tessouter, outer);
1882 ureg_MOV(ureg, tessinner, inner);
1883 ureg_END(ureg);
1884
1885 sctx->fixed_func_tcs_shader.cso =
1886 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
1887 }
1888
1889 static void si_update_vgt_shader_config(struct si_context *sctx)
1890 {
1891 /* Calculate the index of the config.
1892 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
1893 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
1894 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
1895
1896 if (!*pm4) {
1897 uint32_t stages = 0;
1898
1899 *pm4 = CALLOC_STRUCT(si_pm4_state);
1900
1901 if (sctx->tes_shader.cso) {
1902 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1903 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
1904
1905 if (sctx->gs_shader.cso)
1906 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1907 S_028B54_GS_EN(1) |
1908 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1909 else
1910 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1911 } else if (sctx->gs_shader.cso) {
1912 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1913 S_028B54_GS_EN(1) |
1914 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1915 }
1916
1917 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
1918 }
1919 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
1920 }
1921
1922 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
1923 {
1924 struct pipe_stream_output_info *so = &shader->so;
1925 uint32_t enabled_stream_buffers_mask = 0;
1926 int i;
1927
1928 for (i = 0; i < so->num_outputs; i++)
1929 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
1930 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
1931 sctx->b.streamout.stride_in_dw = shader->so.stride;
1932 }
1933
1934 bool si_update_shaders(struct si_context *sctx)
1935 {
1936 struct pipe_context *ctx = (struct pipe_context*)sctx;
1937 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1938 int r;
1939
1940 /* Update stages before GS. */
1941 if (sctx->tes_shader.cso) {
1942 if (!sctx->tf_ring) {
1943 si_init_tess_factor_ring(sctx);
1944 if (!sctx->tf_ring)
1945 return false;
1946 }
1947
1948 /* VS as LS */
1949 r = si_shader_select(ctx, &sctx->vs_shader);
1950 if (r)
1951 return false;
1952 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1953
1954 if (sctx->tcs_shader.cso) {
1955 r = si_shader_select(ctx, &sctx->tcs_shader);
1956 if (r)
1957 return false;
1958 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1959 } else {
1960 if (!sctx->fixed_func_tcs_shader.cso) {
1961 si_generate_fixed_func_tcs(sctx);
1962 if (!sctx->fixed_func_tcs_shader.cso)
1963 return false;
1964 }
1965
1966 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader);
1967 if (r)
1968 return false;
1969 si_pm4_bind_state(sctx, hs,
1970 sctx->fixed_func_tcs_shader.current->pm4);
1971 }
1972
1973 r = si_shader_select(ctx, &sctx->tes_shader);
1974 if (r)
1975 return false;
1976
1977 if (sctx->gs_shader.cso) {
1978 /* TES as ES */
1979 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1980 } else {
1981 /* TES as VS */
1982 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1983 si_update_so(sctx, sctx->tes_shader.cso);
1984 }
1985 } else if (sctx->gs_shader.cso) {
1986 /* VS as ES */
1987 r = si_shader_select(ctx, &sctx->vs_shader);
1988 if (r)
1989 return false;
1990 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1991 } else {
1992 /* VS as VS */
1993 r = si_shader_select(ctx, &sctx->vs_shader);
1994 if (r)
1995 return false;
1996 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1997 si_update_so(sctx, sctx->vs_shader.cso);
1998 }
1999
2000 /* Update GS. */
2001 if (sctx->gs_shader.cso) {
2002 r = si_shader_select(ctx, &sctx->gs_shader);
2003 if (r)
2004 return false;
2005 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2006 si_pm4_bind_state(sctx, vs, sctx->gs_shader.current->gs_copy_shader->pm4);
2007 si_update_so(sctx, sctx->gs_shader.cso);
2008
2009 if (!si_update_gs_ring_buffers(sctx))
2010 return false;
2011
2012 si_update_gsvs_ring_bindings(sctx);
2013 } else {
2014 si_pm4_bind_state(sctx, gs, NULL);
2015 si_pm4_bind_state(sctx, es, NULL);
2016 }
2017
2018 si_update_vgt_shader_config(sctx);
2019
2020 if (sctx->ps_shader.cso) {
2021 unsigned db_shader_control;
2022
2023 r = si_shader_select(ctx, &sctx->ps_shader);
2024 if (r)
2025 return false;
2026 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2027
2028 db_shader_control =
2029 sctx->ps_shader.cso->db_shader_control |
2030 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS) |
2031 S_02880C_Z_ORDER(sctx->ps_shader.current->z_order);
2032
2033 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
2034 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
2035 sctx->flatshade != rs->flatshade) {
2036 sctx->sprite_coord_enable = rs->sprite_coord_enable;
2037 sctx->flatshade = rs->flatshade;
2038 si_mark_atom_dirty(sctx, &sctx->spi_map);
2039 }
2040
2041 if (sctx->b.family == CHIP_STONEY && si_pm4_state_changed(sctx, ps))
2042 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2043
2044 if (sctx->ps_db_shader_control != db_shader_control) {
2045 sctx->ps_db_shader_control = db_shader_control;
2046 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2047 }
2048
2049 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.ps.epilog.poly_line_smoothing) {
2050 sctx->smoothing_enabled = sctx->ps_shader.current->key.ps.epilog.poly_line_smoothing;
2051 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2052
2053 if (sctx->b.chip_class == SI)
2054 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2055 }
2056 }
2057
2058 if (si_pm4_state_changed(sctx, ls) ||
2059 si_pm4_state_changed(sctx, hs) ||
2060 si_pm4_state_changed(sctx, es) ||
2061 si_pm4_state_changed(sctx, gs) ||
2062 si_pm4_state_changed(sctx, vs) ||
2063 si_pm4_state_changed(sctx, ps)) {
2064 if (!si_update_spi_tmpring_size(sctx))
2065 return false;
2066 }
2067 return true;
2068 }
2069
2070 void si_init_shader_functions(struct si_context *sctx)
2071 {
2072 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
2073
2074 sctx->b.b.create_vs_state = si_create_shader_selector;
2075 sctx->b.b.create_tcs_state = si_create_shader_selector;
2076 sctx->b.b.create_tes_state = si_create_shader_selector;
2077 sctx->b.b.create_gs_state = si_create_shader_selector;
2078 sctx->b.b.create_fs_state = si_create_shader_selector;
2079
2080 sctx->b.b.bind_vs_state = si_bind_vs_shader;
2081 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
2082 sctx->b.b.bind_tes_state = si_bind_tes_shader;
2083 sctx->b.b.bind_gs_state = si_bind_gs_shader;
2084 sctx->b.b.bind_fs_state = si_bind_ps_shader;
2085
2086 sctx->b.b.delete_vs_state = si_delete_shader_selector;
2087 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
2088 sctx->b.b.delete_tes_state = si_delete_shader_selector;
2089 sctx->b.b.delete_gs_state = si_delete_shader_selector;
2090 sctx->b.b.delete_fs_state = si_delete_shader_selector;
2091 }