2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
30 #include "radeon/r600_cs.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_ureg.h"
34 #include "util/hash_table.h"
35 #include "util/crc32.h"
36 #include "util/u_memory.h"
37 #include "util/u_prim.h"
42 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
45 static void *si_get_tgsi_binary(struct si_shader_selector
*sel
)
47 unsigned tgsi_size
= tgsi_num_tokens(sel
->tokens
) *
48 sizeof(struct tgsi_token
);
49 unsigned size
= 4 + tgsi_size
+ sizeof(sel
->so
);
50 char *result
= (char*)MALLOC(size
);
55 *((uint32_t*)result
) = size
;
56 memcpy(result
+ 4, sel
->tokens
, tgsi_size
);
57 memcpy(result
+ 4 + tgsi_size
, &sel
->so
, sizeof(sel
->so
));
61 /** Copy "data" to "ptr" and return the next dword following copied data. */
62 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
64 /* data may be NULL if size == 0 */
66 memcpy(ptr
, data
, size
);
67 ptr
+= DIV_ROUND_UP(size
, 4);
71 /** Read data from "ptr". Return the next dword following the data. */
72 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
74 memcpy(data
, ptr
, size
);
75 ptr
+= DIV_ROUND_UP(size
, 4);
80 * Write the size as uint followed by the data. Return the next dword
81 * following the copied data.
83 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
86 return write_data(ptr
, data
, size
);
90 * Read the size as uint followed by the data. Return both via parameters.
91 * Return the next dword following the data.
93 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
96 assert(*data
== NULL
);
99 *data
= malloc(*size
);
100 return read_data(ptr
, *data
, *size
);
104 * Return the shader binary in a buffer. The first 4 bytes contain its size
107 static void *si_get_shader_binary(struct si_shader
*shader
)
109 /* There is always a size of data followed by the data itself. */
110 unsigned relocs_size
= shader
->binary
.reloc_count
*
111 sizeof(shader
->binary
.relocs
[0]);
112 unsigned disasm_size
= strlen(shader
->binary
.disasm_string
) + 1;
113 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
114 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
117 4 + /* CRC32 of the data below */
118 align(sizeof(shader
->config
), 4) +
119 align(sizeof(shader
->info
), 4) +
120 4 + align(shader
->binary
.code_size
, 4) +
121 4 + align(shader
->binary
.rodata_size
, 4) +
122 4 + align(relocs_size
, 4) +
123 4 + align(disasm_size
, 4) +
124 4 + align(llvm_ir_size
, 4);
125 void *buffer
= CALLOC(1, size
);
126 uint32_t *ptr
= (uint32_t*)buffer
;
132 ptr
++; /* CRC32 is calculated at the end. */
134 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
135 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
136 ptr
= write_chunk(ptr
, shader
->binary
.code
, shader
->binary
.code_size
);
137 ptr
= write_chunk(ptr
, shader
->binary
.rodata
, shader
->binary
.rodata_size
);
138 ptr
= write_chunk(ptr
, shader
->binary
.relocs
, relocs_size
);
139 ptr
= write_chunk(ptr
, shader
->binary
.disasm_string
, disasm_size
);
140 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
141 assert((char *)ptr
- (char *)buffer
== size
);
144 ptr
= (uint32_t*)buffer
;
146 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
151 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
153 uint32_t *ptr
= (uint32_t*)binary
;
154 uint32_t size
= *ptr
++;
155 uint32_t crc32
= *ptr
++;
158 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
159 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
163 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
164 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
165 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.code
,
166 &shader
->binary
.code_size
);
167 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.rodata
,
168 &shader
->binary
.rodata_size
);
169 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.relocs
, &chunk_size
);
170 shader
->binary
.reloc_count
= chunk_size
/ sizeof(shader
->binary
.relocs
[0]);
171 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.disasm_string
, &chunk_size
);
172 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
178 * Insert a shader into the cache. It's assumed the shader is not in the cache.
179 * Use si_shader_cache_load_shader before calling this.
181 * Returns false on failure, in which case the tgsi_binary should be freed.
183 static bool si_shader_cache_insert_shader(struct si_screen
*sscreen
,
185 struct si_shader
*shader
)
188 struct hash_entry
*entry
;
190 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, tgsi_binary
);
192 return false; /* already added */
194 hw_binary
= si_get_shader_binary(shader
);
198 if (_mesa_hash_table_insert(sscreen
->shader_cache
, tgsi_binary
,
199 hw_binary
) == NULL
) {
207 static bool si_shader_cache_load_shader(struct si_screen
*sscreen
,
209 struct si_shader
*shader
)
211 struct hash_entry
*entry
=
212 _mesa_hash_table_search(sscreen
->shader_cache
, tgsi_binary
);
216 if (!si_load_shader_binary(shader
, entry
->data
))
219 p_atomic_inc(&sscreen
->b
.num_shader_cache_hits
);
223 static uint32_t si_shader_cache_key_hash(const void *key
)
225 /* The first dword is the key size. */
226 return util_hash_crc32(key
, *(uint32_t*)key
);
229 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
231 uint32_t *keya
= (uint32_t*)a
;
232 uint32_t *keyb
= (uint32_t*)b
;
234 /* The first dword is the key size. */
238 return memcmp(keya
, keyb
, *keya
) == 0;
241 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
243 FREE((void*)entry
->key
);
247 bool si_init_shader_cache(struct si_screen
*sscreen
)
249 pipe_mutex_init(sscreen
->shader_cache_mutex
);
250 sscreen
->shader_cache
=
251 _mesa_hash_table_create(NULL
,
252 si_shader_cache_key_hash
,
253 si_shader_cache_key_equals
);
254 return sscreen
->shader_cache
!= NULL
;
257 void si_destroy_shader_cache(struct si_screen
*sscreen
)
259 if (sscreen
->shader_cache
)
260 _mesa_hash_table_destroy(sscreen
->shader_cache
,
261 si_destroy_shader_cache_entry
);
262 pipe_mutex_destroy(sscreen
->shader_cache_mutex
);
267 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
268 struct si_shader
*shader
,
269 struct si_pm4_state
*pm4
)
271 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
272 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
273 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
274 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
275 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
276 unsigned type
, partitioning
, topology
, distribution_mode
;
278 switch (tes_prim_mode
) {
279 case PIPE_PRIM_LINES
:
280 type
= V_028B6C_TESS_ISOLINE
;
282 case PIPE_PRIM_TRIANGLES
:
283 type
= V_028B6C_TESS_TRIANGLE
;
285 case PIPE_PRIM_QUADS
:
286 type
= V_028B6C_TESS_QUAD
;
293 switch (tes_spacing
) {
294 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
295 partitioning
= V_028B6C_PART_FRAC_ODD
;
297 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
298 partitioning
= V_028B6C_PART_FRAC_EVEN
;
300 case PIPE_TESS_SPACING_EQUAL
:
301 partitioning
= V_028B6C_PART_INTEGER
;
309 topology
= V_028B6C_OUTPUT_POINT
;
310 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
311 topology
= V_028B6C_OUTPUT_LINE
;
312 else if (tes_vertex_order_cw
)
313 /* for some reason, this must be the other way around */
314 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
316 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
318 if (sscreen
->has_distributed_tess
) {
319 if (sscreen
->b
.family
== CHIP_FIJI
||
320 sscreen
->b
.family
>= CHIP_POLARIS10
)
321 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
323 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
325 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
327 si_pm4_set_reg(pm4
, R_028B6C_VGT_TF_PARAM
,
328 S_028B6C_TYPE(type
) |
329 S_028B6C_PARTITIONING(partitioning
) |
330 S_028B6C_TOPOLOGY(topology
) |
331 S_028B6C_DISTRIBUTION_MODE(distribution_mode
));
334 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
337 si_pm4_clear_state(shader
->pm4
);
339 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
344 static void si_shader_ls(struct si_shader
*shader
)
346 struct si_pm4_state
*pm4
;
347 unsigned vgpr_comp_cnt
;
350 pm4
= si_get_shader_pm4_state(shader
);
354 va
= shader
->bo
->gpu_address
;
355 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
357 /* We need at least 2 components for LS.
358 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
359 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : 1;
361 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
362 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, va
>> 40);
364 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
365 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
366 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
367 S_00B528_DX10_CLAMP(1) |
368 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
369 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(SI_LS_NUM_USER_SGPR
) |
370 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
373 static void si_shader_hs(struct si_shader
*shader
)
375 struct si_pm4_state
*pm4
;
378 pm4
= si_get_shader_pm4_state(shader
);
382 va
= shader
->bo
->gpu_address
;
383 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
385 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
386 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, va
>> 40);
387 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
388 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
389 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
390 S_00B428_DX10_CLAMP(1) |
391 S_00B428_FLOAT_MODE(shader
->config
.float_mode
));
392 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
393 S_00B42C_USER_SGPR(SI_TCS_NUM_USER_SGPR
) |
394 S_00B42C_OC_LDS_EN(1) |
395 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
398 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
400 struct si_pm4_state
*pm4
;
401 unsigned num_user_sgprs
;
402 unsigned vgpr_comp_cnt
;
406 pm4
= si_get_shader_pm4_state(shader
);
410 va
= shader
->bo
->gpu_address
;
411 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
413 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
414 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : 0;
415 num_user_sgprs
= SI_ES_NUM_USER_SGPR
;
416 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
417 vgpr_comp_cnt
= 3; /* all components are needed for TES */
418 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
420 unreachable("invalid shader selector type");
422 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
424 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
425 shader
->selector
->esgs_itemsize
/ 4);
426 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
427 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
428 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
429 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
430 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
431 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
432 S_00B328_DX10_CLAMP(1) |
433 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
434 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
435 S_00B32C_USER_SGPR(num_user_sgprs
) |
436 S_00B32C_OC_LDS_EN(oc_lds_en
) |
437 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
439 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
440 si_set_tesseval_regs(sscreen
, shader
, pm4
);
444 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
447 static uint32_t si_vgt_gs_mode(struct si_shader_selector
*sel
)
449 unsigned gs_max_vert_out
= sel
->gs_max_out_vertices
;
452 if (gs_max_vert_out
<= 128) {
453 cut_mode
= V_028A40_GS_CUT_128
;
454 } else if (gs_max_vert_out
<= 256) {
455 cut_mode
= V_028A40_GS_CUT_256
;
456 } else if (gs_max_vert_out
<= 512) {
457 cut_mode
= V_028A40_GS_CUT_512
;
459 assert(gs_max_vert_out
<= 1024);
460 cut_mode
= V_028A40_GS_CUT_1024
;
463 return S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
464 S_028A40_CUT_MODE(cut_mode
)|
465 S_028A40_ES_WRITE_OPTIMIZE(1) |
466 S_028A40_GS_WRITE_OPTIMIZE(1);
469 static void si_shader_gs(struct si_shader
*shader
)
471 struct si_shader_selector
*sel
= shader
->selector
;
472 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
473 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
474 struct si_pm4_state
*pm4
;
476 unsigned max_stream
= sel
->max_gs_stream
;
479 pm4
= si_get_shader_pm4_state(shader
);
483 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, si_vgt_gs_mode(shader
->selector
));
485 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
486 si_pm4_set_reg(pm4
, R_028A60_VGT_GSVS_RING_OFFSET_1
, offset
);
488 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
489 si_pm4_set_reg(pm4
, R_028A64_VGT_GSVS_RING_OFFSET_2
, offset
);
491 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
492 si_pm4_set_reg(pm4
, R_028A68_VGT_GSVS_RING_OFFSET_3
, offset
);
494 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
495 si_pm4_set_reg(pm4
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
497 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
498 assert(offset
< (1 << 15));
500 si_pm4_set_reg(pm4
, R_028B38_VGT_GS_MAX_VERT_OUT
, shader
->selector
->gs_max_out_vertices
);
502 si_pm4_set_reg(pm4
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, num_components
[0]);
503 si_pm4_set_reg(pm4
, R_028B60_VGT_GS_VERT_ITEMSIZE_1
, (max_stream
>= 1) ? num_components
[1] : 0);
504 si_pm4_set_reg(pm4
, R_028B64_VGT_GS_VERT_ITEMSIZE_2
, (max_stream
>= 2) ? num_components
[2] : 0);
505 si_pm4_set_reg(pm4
, R_028B68_VGT_GS_VERT_ITEMSIZE_3
, (max_stream
>= 3) ? num_components
[3] : 0);
507 si_pm4_set_reg(pm4
, R_028B90_VGT_GS_INSTANCE_CNT
,
508 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
509 S_028B90_ENABLE(gs_num_invocations
> 0));
511 va
= shader
->bo
->gpu_address
;
512 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
513 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
514 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, va
>> 40);
516 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
517 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
518 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
519 S_00B228_DX10_CLAMP(1) |
520 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
521 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
522 S_00B22C_USER_SGPR(SI_GS_NUM_USER_SGPR
) |
523 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
527 * Compute the state for \p shader, which will run as a vertex shader on the
530 * If \p gs is non-NULL, it points to the geometry shader for which this shader
531 * is the copy shader.
533 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
534 struct si_shader_selector
*gs
)
536 struct si_pm4_state
*pm4
;
537 unsigned num_user_sgprs
;
538 unsigned nparams
, vgpr_comp_cnt
;
541 unsigned window_space
=
542 shader
->selector
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
543 bool enable_prim_id
= si_vs_exports_prim_id(shader
);
545 pm4
= si_get_shader_pm4_state(shader
);
549 /* We always write VGT_GS_MODE in the VS state, because every switch
550 * between different shader pipelines involving a different GS or no
551 * GS at all involves a switch of the VS (different GS use different
552 * copy shaders). On the other hand, when the API switches from a GS to
553 * no GS and then back to the same GS used originally, the GS state is
557 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
,
558 S_028A40_MODE(enable_prim_id
? V_028A40_GS_SCENARIO_A
: 0));
559 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, enable_prim_id
);
561 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, si_vgt_gs_mode(gs
));
562 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
565 va
= shader
->bo
->gpu_address
;
566 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
569 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
570 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
571 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
572 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : (enable_prim_id
? 2 : 0);
573 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
574 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
575 vgpr_comp_cnt
= 3; /* all components are needed for TES */
576 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
578 unreachable("invalid shader selector type");
580 /* VS is required to export at least one param. */
581 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
582 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
583 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
585 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
586 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
587 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
588 V_02870C_SPI_SHADER_4COMP
:
589 V_02870C_SPI_SHADER_NONE
) |
590 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
591 V_02870C_SPI_SHADER_4COMP
:
592 V_02870C_SPI_SHADER_NONE
) |
593 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
594 V_02870C_SPI_SHADER_4COMP
:
595 V_02870C_SPI_SHADER_NONE
));
597 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
599 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
600 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, va
>> 40);
601 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
602 S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
603 S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
604 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
605 S_00B128_DX10_CLAMP(1) |
606 S_00B128_FLOAT_MODE(shader
->config
.float_mode
));
607 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
608 S_00B12C_USER_SGPR(num_user_sgprs
) |
609 S_00B12C_OC_LDS_EN(oc_lds_en
) |
610 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
611 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
612 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
613 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
614 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
) |
615 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
617 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
618 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
620 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
621 S_028818_VTX_W0_FMT(1) |
622 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
623 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
624 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
626 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
627 si_set_tesseval_regs(sscreen
, shader
, pm4
);
630 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
632 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
633 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
634 !!(info
->colors_read
& 0xf0);
635 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
636 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
638 assert(num_interp
<= 32);
639 return MIN2(num_interp
, 32);
642 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
644 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
645 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
647 /* If the i-th target format is set, all previous target formats must
648 * be non-zero to avoid hangs.
650 for (i
= 0; i
< num_targets
; i
++)
651 if (!(value
& (0xf << (i
* 4))))
652 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
657 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format
)
659 unsigned i
, cb_shader_mask
= 0;
661 for (i
= 0; i
< 8; i
++) {
662 switch ((spi_shader_col_format
>> (i
* 4)) & 0xf) {
663 case V_028714_SPI_SHADER_ZERO
:
665 case V_028714_SPI_SHADER_32_R
:
666 cb_shader_mask
|= 0x1 << (i
* 4);
668 case V_028714_SPI_SHADER_32_GR
:
669 cb_shader_mask
|= 0x3 << (i
* 4);
671 case V_028714_SPI_SHADER_32_AR
:
672 cb_shader_mask
|= 0x9 << (i
* 4);
674 case V_028714_SPI_SHADER_FP16_ABGR
:
675 case V_028714_SPI_SHADER_UNORM16_ABGR
:
676 case V_028714_SPI_SHADER_SNORM16_ABGR
:
677 case V_028714_SPI_SHADER_UINT16_ABGR
:
678 case V_028714_SPI_SHADER_SINT16_ABGR
:
679 case V_028714_SPI_SHADER_32_ABGR
:
680 cb_shader_mask
|= 0xf << (i
* 4);
686 return cb_shader_mask
;
689 static void si_shader_ps(struct si_shader
*shader
)
691 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
692 struct si_pm4_state
*pm4
;
693 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
694 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
696 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
698 /* we need to enable at least one of them, otherwise we hang the GPU */
699 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
700 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
701 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
702 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
703 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
704 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
705 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
706 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
707 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
708 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
709 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
710 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
711 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
712 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
714 /* Validate interpolation optimization flags (read as implications). */
715 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
716 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
717 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
718 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
719 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
720 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
721 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
722 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
723 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
724 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
725 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
726 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
727 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
728 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
729 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
730 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
731 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
732 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
734 /* Validate cases when the optimizations are off (read as implications). */
735 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
736 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
737 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
738 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
739 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
740 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
742 pm4
= si_get_shader_pm4_state(shader
);
746 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
748 * 0 -> Position = pixel center
749 * 1 -> Position = pixel centroid
750 * 2 -> Position = at sample position
752 * From GLSL 4.5 specification, section 7.1:
753 * "The variable gl_FragCoord is available as an input variable from
754 * within fragment shaders and it holds the window relative coordinates
755 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
756 * value can be for any location within the pixel, or one of the
757 * fragment samples. The use of centroid does not further restrict
758 * this value to be inside the current primitive."
760 * Meaning that centroid has no effect and we can return anything within
761 * the pixel. Thus, return the value at sample position, because that's
762 * the most accurate one shaders can get.
764 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
766 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
767 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
768 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
770 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
771 cb_shader_mask
= si_get_cb_shader_mask(spi_shader_col_format
);
773 /* Ensure that some export memory is always allocated, for two reasons:
775 * 1) Correctness: The hardware ignores the EXEC mask if no export
776 * memory is allocated, so KILL and alpha test do not work correctly
778 * 2) Performance: Every shader needs at least a NULL export, even when
779 * it writes no color/depth output. The NULL export instruction
780 * stalls without this setting.
782 * Don't add this to CB_SHADER_MASK.
784 if (!spi_shader_col_format
&&
785 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
786 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
788 si_pm4_set_reg(pm4
, R_0286CC_SPI_PS_INPUT_ENA
, input_ena
);
789 si_pm4_set_reg(pm4
, R_0286D0_SPI_PS_INPUT_ADDR
,
790 shader
->config
.spi_ps_input_addr
);
792 /* Set interpolation controls. */
793 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
));
796 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
797 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
799 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
,
800 si_get_spi_shader_z_format(info
->writes_z
,
801 info
->writes_stencil
,
802 info
->writes_samplemask
));
804 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
, spi_shader_col_format
);
805 si_pm4_set_reg(pm4
, R_02823C_CB_SHADER_MASK
, cb_shader_mask
);
807 va
= shader
->bo
->gpu_address
;
808 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
809 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
810 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, va
>> 40);
812 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
813 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
814 S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
815 S_00B028_DX10_CLAMP(1) |
816 S_00B028_FLOAT_MODE(shader
->config
.float_mode
));
817 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
818 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
819 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
820 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
823 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
824 struct si_shader
*shader
)
826 switch (shader
->selector
->type
) {
827 case PIPE_SHADER_VERTEX
:
828 if (shader
->key
.as_ls
)
829 si_shader_ls(shader
);
830 else if (shader
->key
.as_es
)
831 si_shader_es(sscreen
, shader
);
833 si_shader_vs(sscreen
, shader
, NULL
);
835 case PIPE_SHADER_TESS_CTRL
:
836 si_shader_hs(shader
);
838 case PIPE_SHADER_TESS_EVAL
:
839 if (shader
->key
.as_es
)
840 si_shader_es(sscreen
, shader
);
842 si_shader_vs(sscreen
, shader
, NULL
);
844 case PIPE_SHADER_GEOMETRY
:
845 si_shader_gs(shader
);
847 case PIPE_SHADER_FRAGMENT
:
848 si_shader_ps(shader
);
855 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
857 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
858 if (sctx
->queued
.named
.dsa
)
859 return sctx
->queued
.named
.dsa
->alpha_func
;
861 return PIPE_FUNC_ALWAYS
;
864 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
865 struct si_shader_selector
*vs
,
866 struct si_shader_key
*key
)
868 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
870 key
->opt
.hw_vs
.clip_disable
=
871 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
872 (vs
->info
.clipdist_writemask
||
873 vs
->info
.writes_clipvertex
) &&
874 !vs
->info
.culldist_writemask
;
876 /* Find out if PS is disabled. */
877 bool ps_disabled
= true;
879 bool ps_modifies_zs
= ps
->info
.uses_kill
||
881 ps
->info
.writes_stencil
||
882 ps
->info
.writes_samplemask
||
883 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
885 unsigned ps_colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
886 sctx
->queued
.named
.blend
->cb_target_mask
;
887 if (!ps
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
888 ps_colormask
&= ps
->colors_written_4bit
;
890 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
893 !ps
->info
.writes_memory
);
896 /* Find out which VS outputs aren't used by the PS. */
897 uint64_t outputs_written
= vs
->outputs_written
;
898 uint32_t outputs_written2
= vs
->outputs_written2
;
899 uint64_t inputs_read
= 0;
900 uint32_t inputs_read2
= 0;
902 outputs_written
&= ~0x3; /* ignore POSITION, PSIZE */
905 inputs_read
= ps
->inputs_read
;
906 inputs_read2
= ps
->inputs_read2
;
909 uint64_t linked
= outputs_written
& inputs_read
;
910 uint32_t linked2
= outputs_written2
& inputs_read2
;
912 key
->opt
.hw_vs
.kill_outputs
= ~linked
& outputs_written
;
913 key
->opt
.hw_vs
.kill_outputs2
= ~linked2
& outputs_written2
;
916 /* Compute the key for the hw shader variant */
917 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
918 struct si_shader_selector
*sel
,
919 struct si_shader_key
*key
)
921 struct si_context
*sctx
= (struct si_context
*)ctx
;
924 memset(key
, 0, sizeof(*key
));
927 case PIPE_SHADER_VERTEX
:
928 if (sctx
->vertex_elements
) {
929 unsigned count
= MIN2(sel
->info
.num_inputs
,
930 sctx
->vertex_elements
->count
);
931 for (i
= 0; i
< count
; ++i
)
932 key
->part
.vs
.prolog
.instance_divisors
[i
] =
933 sctx
->vertex_elements
->elements
[i
].instance_divisor
;
935 key
->mono
.vs
.fix_fetch
=
936 sctx
->vertex_elements
->fix_fetch
&
937 u_bit_consecutive(0, 2 * count
);
939 if (sctx
->tes_shader
.cso
)
941 else if (sctx
->gs_shader
.cso
)
944 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
946 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
947 key
->part
.vs
.epilog
.export_prim_id
= 1;
950 case PIPE_SHADER_TESS_CTRL
:
951 key
->part
.tcs
.epilog
.prim_mode
=
952 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
954 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
955 key
->mono
.tcs
.inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
957 case PIPE_SHADER_TESS_EVAL
:
958 if (sctx
->gs_shader
.cso
)
961 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
963 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
964 key
->part
.tes
.epilog
.export_prim_id
= 1;
967 case PIPE_SHADER_GEOMETRY
:
968 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
970 case PIPE_SHADER_FRAGMENT
: {
971 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
972 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
974 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
975 sel
->info
.colors_written
== 0x1)
976 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
979 /* Select the shader color format based on whether
980 * blending or alpha are needed.
982 key
->part
.ps
.epilog
.spi_shader_col_format
=
983 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
984 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
985 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
986 sctx
->framebuffer
.spi_shader_col_format_blend
) |
987 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
988 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
989 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
990 sctx
->framebuffer
.spi_shader_col_format
);
992 /* The output for dual source blending should have
993 * the same format as the first output.
995 if (blend
->dual_src_blend
)
996 key
->part
.ps
.epilog
.spi_shader_col_format
|=
997 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
999 key
->part
.ps
.epilog
.spi_shader_col_format
= sctx
->framebuffer
.spi_shader_col_format
;
1001 /* If alpha-to-coverage is enabled, we have to export alpha
1002 * even if there is no color buffer.
1004 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1005 blend
&& blend
->alpha_to_coverage
)
1006 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1008 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1009 * to the range supported by the type if a channel has less
1010 * than 16 bits and the export format is 16_ABGR.
1012 if (sctx
->b
.chip_class
<= CIK
&& sctx
->b
.family
!= CHIP_HAWAII
)
1013 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1015 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1016 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1017 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1018 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1022 bool is_poly
= (sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES
&&
1023 sctx
->current_rast_prim
<= PIPE_PRIM_POLYGON
) ||
1024 sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES_ADJACENCY
;
1025 bool is_line
= !is_poly
&& sctx
->current_rast_prim
!= PIPE_PRIM_POINTS
;
1027 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1028 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1030 if (sctx
->queued
.named
.blend
) {
1031 key
->part
.ps
.epilog
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
1032 rs
->multisample_enable
;
1035 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1036 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1037 (is_line
&& rs
->line_smooth
)) &&
1038 sctx
->framebuffer
.nr_samples
<= 1;
1039 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1041 if (rs
->force_persample_interp
&&
1042 rs
->multisample_enable
&&
1043 sctx
->framebuffer
.nr_samples
> 1 &&
1044 sctx
->ps_iter_samples
> 1) {
1045 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1046 sel
->info
.uses_persp_center
||
1047 sel
->info
.uses_persp_centroid
;
1049 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1050 sel
->info
.uses_linear_center
||
1051 sel
->info
.uses_linear_centroid
;
1052 } else if (rs
->multisample_enable
&&
1053 sctx
->framebuffer
.nr_samples
> 1) {
1054 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
1055 sel
->info
.uses_persp_center
&&
1056 sel
->info
.uses_persp_centroid
;
1057 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
1058 sel
->info
.uses_linear_center
&&
1059 sel
->info
.uses_linear_centroid
;
1061 /* Make sure SPI doesn't compute more than 1 pair
1062 * of (i,j), which is the optimization here. */
1063 key
->part
.ps
.prolog
.force_persp_center_interp
=
1064 sel
->info
.uses_persp_center
+
1065 sel
->info
.uses_persp_centroid
+
1066 sel
->info
.uses_persp_sample
> 1;
1068 key
->part
.ps
.prolog
.force_linear_center_interp
=
1069 sel
->info
.uses_linear_center
+
1070 sel
->info
.uses_linear_centroid
+
1071 sel
->info
.uses_linear_sample
> 1;
1075 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
1083 static void si_build_shader_variant(void *job
, int thread_index
)
1085 struct si_shader
*shader
= (struct si_shader
*)job
;
1086 struct si_shader_selector
*sel
= shader
->selector
;
1087 struct si_screen
*sscreen
= sel
->screen
;
1088 LLVMTargetMachineRef tm
;
1089 struct pipe_debug_callback
*debug
= &sel
->debug
;
1092 if (thread_index
>= 0) {
1093 assert(thread_index
< ARRAY_SIZE(sscreen
->tm
));
1094 tm
= sscreen
->tm
[thread_index
];
1101 r
= si_shader_create(sscreen
, tm
, shader
, debug
);
1103 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1105 shader
->compilation_failed
= true;
1109 if (sel
->is_debug_context
) {
1110 FILE *f
= open_memstream(&shader
->shader_log
,
1111 &shader
->shader_log_size
);
1113 si_shader_dump(sscreen
, shader
, NULL
, sel
->type
, f
);
1118 si_shader_init_pm4_state(sscreen
, shader
);
1121 /* Select the hw shader variant depending on the current state. */
1122 static int si_shader_select_with_key(struct si_screen
*sscreen
,
1123 struct si_shader_ctx_state
*state
,
1124 struct si_shader_key
*key
,
1127 static const struct si_shader_key zeroed
;
1128 struct si_shader_selector
*sel
= state
->cso
;
1129 struct si_shader
*current
= state
->current
;
1130 struct si_shader
*iter
, *shader
= NULL
;
1132 if (unlikely(sscreen
->b
.chip_class
& DBG_NO_OPT_VARIANT
)) {
1133 memset(&key
->opt
, 0, sizeof(key
->opt
));
1137 /* Check if we don't need to change anything.
1138 * This path is also used for most shaders that don't need multiple
1139 * variants, it will cost just a computation of the key and this
1141 if (likely(current
&&
1142 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0 &&
1143 (!current
->is_optimized
||
1144 util_queue_fence_is_signalled(¤t
->optimized_ready
))))
1147 /* This must be done before the mutex is locked, because async GS
1148 * compilation calls this function too, and therefore must enter
1151 * Only wait if we are in a draw call. Don't wait if we are
1152 * in a compiler thread.
1154 if (thread_index
< 0)
1155 util_queue_job_wait(&sel
->ready
);
1157 pipe_mutex_lock(sel
->mutex
);
1159 /* Find the shader variant. */
1160 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
1161 /* Don't check the "current" shader. We checked it above. */
1162 if (current
!= iter
&&
1163 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
1164 /* If it's an optimized shader and its compilation has
1165 * been started but isn't done, use the unoptimized
1166 * shader so as not to cause a stall due to compilation.
1168 if (iter
->is_optimized
&&
1169 !util_queue_fence_is_signalled(&iter
->optimized_ready
)) {
1170 memset(&key
->opt
, 0, sizeof(key
->opt
));
1171 pipe_mutex_unlock(sel
->mutex
);
1175 if (iter
->compilation_failed
) {
1176 pipe_mutex_unlock(sel
->mutex
);
1177 return -1; /* skip the draw call */
1180 state
->current
= iter
;
1181 pipe_mutex_unlock(sel
->mutex
);
1186 /* Build a new shader. */
1187 shader
= CALLOC_STRUCT(si_shader
);
1189 pipe_mutex_unlock(sel
->mutex
);
1192 shader
->selector
= sel
;
1195 /* Monolithic-only shaders don't make a distinction between optimized
1196 * and unoptimized. */
1197 shader
->is_monolithic
=
1198 !sel
->main_shader_part
||
1199 sel
->main_shader_part
->key
.as_ls
!= key
->as_ls
||
1200 sel
->main_shader_part
->key
.as_es
!= key
->as_es
||
1201 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0 ||
1202 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
1204 shader
->is_optimized
=
1205 !sscreen
->use_monolithic_shaders
&&
1206 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1207 if (shader
->is_optimized
)
1208 util_queue_fence_init(&shader
->optimized_ready
);
1210 if (!sel
->last_variant
) {
1211 sel
->first_variant
= shader
;
1212 sel
->last_variant
= shader
;
1214 sel
->last_variant
->next_variant
= shader
;
1215 sel
->last_variant
= shader
;
1218 /* If it's an optimized shader, compile it asynchronously. */
1219 if (shader
->is_optimized
&&
1221 /* Compile it asynchronously. */
1222 util_queue_add_job(&sscreen
->shader_compiler_queue
,
1223 shader
, &shader
->optimized_ready
,
1224 si_build_shader_variant
, NULL
);
1226 /* Use the default (unoptimized) shader for now. */
1227 memset(&key
->opt
, 0, sizeof(key
->opt
));
1228 pipe_mutex_unlock(sel
->mutex
);
1232 assert(!shader
->is_optimized
);
1233 si_build_shader_variant(shader
, thread_index
);
1235 if (!shader
->compilation_failed
)
1236 state
->current
= shader
;
1238 pipe_mutex_unlock(sel
->mutex
);
1239 return shader
->compilation_failed
? -1 : 0;
1242 static int si_shader_select(struct pipe_context
*ctx
,
1243 struct si_shader_ctx_state
*state
)
1245 struct si_context
*sctx
= (struct si_context
*)ctx
;
1246 struct si_shader_key key
;
1248 si_shader_selector_key(ctx
, state
->cso
, &key
);
1249 return si_shader_select_with_key(sctx
->screen
, state
, &key
, -1);
1252 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
1253 struct si_shader_key
*key
)
1255 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
1257 switch (info
->processor
) {
1258 case PIPE_SHADER_VERTEX
:
1259 switch (next_shader
) {
1260 case PIPE_SHADER_GEOMETRY
:
1263 case PIPE_SHADER_TESS_CTRL
:
1264 case PIPE_SHADER_TESS_EVAL
:
1268 /* If POSITION isn't written, it can't be a HW VS.
1269 * Assume that it's a HW LS. (the next shader is TCS)
1270 * This heuristic is needed for separate shader objects.
1272 if (!info
->writes_position
)
1277 case PIPE_SHADER_TESS_EVAL
:
1278 if (next_shader
== PIPE_SHADER_GEOMETRY
)
1285 * Compile the main shader part or the monolithic shader as part of
1286 * si_shader_selector initialization. Since it can be done asynchronously,
1287 * there is no way to report compile failures to applications.
1289 void si_init_shader_selector_async(void *job
, int thread_index
)
1291 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
1292 struct si_screen
*sscreen
= sel
->screen
;
1293 LLVMTargetMachineRef tm
;
1294 struct pipe_debug_callback
*debug
= &sel
->debug
;
1297 if (thread_index
>= 0) {
1298 assert(thread_index
< ARRAY_SIZE(sscreen
->tm
));
1299 tm
= sscreen
->tm
[thread_index
];
1306 /* Compile the main shader part for use with a prolog and/or epilog.
1307 * If this fails, the driver will try to compile a monolithic shader
1310 if (!sscreen
->use_monolithic_shaders
) {
1311 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
1315 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
1319 shader
->selector
= sel
;
1320 si_parse_next_shader_property(&sel
->info
, &shader
->key
);
1322 tgsi_binary
= si_get_tgsi_binary(sel
);
1324 /* Try to load the shader from the shader cache. */
1325 pipe_mutex_lock(sscreen
->shader_cache_mutex
);
1328 si_shader_cache_load_shader(sscreen
, tgsi_binary
, shader
)) {
1330 pipe_mutex_unlock(sscreen
->shader_cache_mutex
);
1332 pipe_mutex_unlock(sscreen
->shader_cache_mutex
);
1334 /* Compile the shader if it hasn't been loaded from the cache. */
1335 if (si_compile_tgsi_shader(sscreen
, tm
, shader
, false,
1339 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
1344 pipe_mutex_lock(sscreen
->shader_cache_mutex
);
1345 if (!si_shader_cache_insert_shader(sscreen
, tgsi_binary
, shader
))
1347 pipe_mutex_unlock(sscreen
->shader_cache_mutex
);
1351 sel
->main_shader_part
= shader
;
1353 /* Unset "outputs_written" flags for outputs converted to
1354 * DEFAULT_VAL, so that later inter-shader optimizations don't
1355 * try to eliminate outputs that don't exist in the final
1358 * This is only done if non-monolithic shaders are enabled.
1360 if ((sel
->type
== PIPE_SHADER_VERTEX
||
1361 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
1362 !shader
->key
.as_ls
&&
1363 !shader
->key
.as_es
) {
1366 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
1367 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
1369 if (offset
<= EXP_PARAM_OFFSET_31
)
1372 unsigned name
= sel
->info
.output_semantic_name
[i
];
1373 unsigned index
= sel
->info
.output_semantic_index
[i
];
1377 case TGSI_SEMANTIC_GENERIC
:
1378 /* don't process indices the function can't handle */
1382 case TGSI_SEMANTIC_CLIPDIST
:
1383 id
= si_shader_io_get_unique_index(name
, index
);
1384 sel
->outputs_written
&= ~(1ull << id
);
1386 case TGSI_SEMANTIC_POSITION
: /* ignore these */
1387 case TGSI_SEMANTIC_PSIZE
:
1388 case TGSI_SEMANTIC_CLIPVERTEX
:
1389 case TGSI_SEMANTIC_EDGEFLAG
:
1392 id
= si_shader_io_get_unique_index2(name
, index
);
1393 sel
->outputs_written2
&= ~(1u << id
);
1399 /* Pre-compilation. */
1400 if (sscreen
->b
.debug_flags
& DBG_PRECOMPILE
) {
1401 struct si_shader_ctx_state state
= {sel
};
1402 struct si_shader_key key
;
1404 memset(&key
, 0, sizeof(key
));
1405 si_parse_next_shader_property(&sel
->info
, &key
);
1407 /* Set reasonable defaults, so that the shader key doesn't
1408 * cause any code to be eliminated.
1410 switch (sel
->type
) {
1411 case PIPE_SHADER_TESS_CTRL
:
1412 key
.part
.tcs
.epilog
.prim_mode
= PIPE_PRIM_TRIANGLES
;
1414 case PIPE_SHADER_FRAGMENT
:
1415 key
.part
.ps
.prolog
.bc_optimize_for_persp
=
1416 sel
->info
.uses_persp_center
&&
1417 sel
->info
.uses_persp_centroid
;
1418 key
.part
.ps
.prolog
.bc_optimize_for_linear
=
1419 sel
->info
.uses_linear_center
&&
1420 sel
->info
.uses_linear_centroid
;
1421 key
.part
.ps
.epilog
.alpha_func
= PIPE_FUNC_ALWAYS
;
1422 for (i
= 0; i
< 8; i
++)
1423 if (sel
->info
.colors_written
& (1 << i
))
1424 key
.part
.ps
.epilog
.spi_shader_col_format
|=
1425 V_028710_SPI_SHADER_FP16_ABGR
<< (i
* 4);
1429 if (si_shader_select_with_key(sscreen
, &state
, &key
, thread_index
))
1430 fprintf(stderr
, "radeonsi: can't create a monolithic shader\n");
1433 /* The GS copy shader is always pre-compiled. */
1434 if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
1435 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, tm
, sel
, debug
);
1436 if (!sel
->gs_copy_shader
) {
1437 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
1441 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
1445 static void *si_create_shader_selector(struct pipe_context
*ctx
,
1446 const struct pipe_shader_state
*state
)
1448 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
1449 struct si_context
*sctx
= (struct si_context
*)ctx
;
1450 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
1456 sel
->screen
= sscreen
;
1458 sel
->debug
= sctx
->b
.debug
;
1459 sel
->is_debug_context
= sctx
->is_debug
;
1460 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
1466 sel
->so
= state
->stream_output
;
1467 tgsi_scan_shader(state
->tokens
, &sel
->info
);
1468 sel
->type
= sel
->info
.processor
;
1469 p_atomic_inc(&sscreen
->b
.num_shaders_created
);
1471 /* Set which opcode uses which (i,j) pair. */
1472 if (sel
->info
.uses_persp_opcode_interp_centroid
)
1473 sel
->info
.uses_persp_centroid
= true;
1475 if (sel
->info
.uses_linear_opcode_interp_centroid
)
1476 sel
->info
.uses_linear_centroid
= true;
1478 if (sel
->info
.uses_persp_opcode_interp_offset
||
1479 sel
->info
.uses_persp_opcode_interp_sample
)
1480 sel
->info
.uses_persp_center
= true;
1482 if (sel
->info
.uses_linear_opcode_interp_offset
||
1483 sel
->info
.uses_linear_opcode_interp_sample
)
1484 sel
->info
.uses_linear_center
= true;
1486 switch (sel
->type
) {
1487 case PIPE_SHADER_GEOMETRY
:
1488 sel
->gs_output_prim
=
1489 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
1490 sel
->gs_max_out_vertices
=
1491 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
1492 sel
->gs_num_invocations
=
1493 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
1494 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
1495 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
1496 sel
->gs_max_out_vertices
;
1498 sel
->max_gs_stream
= 0;
1499 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
1500 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
1501 sel
->so
.output
[i
].stream
);
1503 sel
->gs_input_verts_per_prim
=
1504 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
1507 case PIPE_SHADER_TESS_CTRL
:
1508 /* Always reserve space for these. */
1509 sel
->patch_outputs_written
|=
1510 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER
, 0)) |
1511 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER
, 0));
1513 case PIPE_SHADER_VERTEX
:
1514 case PIPE_SHADER_TESS_EVAL
:
1515 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
1516 unsigned name
= sel
->info
.output_semantic_name
[i
];
1517 unsigned index
= sel
->info
.output_semantic_index
[i
];
1520 case TGSI_SEMANTIC_TESSINNER
:
1521 case TGSI_SEMANTIC_TESSOUTER
:
1522 case TGSI_SEMANTIC_PATCH
:
1523 sel
->patch_outputs_written
|=
1524 1llu << si_shader_io_get_unique_index(name
, index
);
1527 case TGSI_SEMANTIC_GENERIC
:
1528 /* don't process indices the function can't handle */
1532 case TGSI_SEMANTIC_POSITION
:
1533 case TGSI_SEMANTIC_PSIZE
:
1534 case TGSI_SEMANTIC_CLIPDIST
:
1535 sel
->outputs_written
|=
1536 1llu << si_shader_io_get_unique_index(name
, index
);
1538 case TGSI_SEMANTIC_CLIPVERTEX
: /* ignore these */
1539 case TGSI_SEMANTIC_EDGEFLAG
:
1542 sel
->outputs_written2
|=
1543 1u << si_shader_io_get_unique_index2(name
, index
);
1546 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
1549 case PIPE_SHADER_FRAGMENT
:
1550 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
1551 unsigned name
= sel
->info
.input_semantic_name
[i
];
1552 unsigned index
= sel
->info
.input_semantic_index
[i
];
1555 case TGSI_SEMANTIC_CLIPDIST
:
1556 case TGSI_SEMANTIC_GENERIC
:
1558 1llu << si_shader_io_get_unique_index(name
, index
);
1560 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
1563 sel
->inputs_read2
|=
1564 1u << si_shader_io_get_unique_index2(name
, index
);
1568 for (i
= 0; i
< 8; i
++)
1569 if (sel
->info
.colors_written
& (1 << i
))
1570 sel
->colors_written_4bit
|= 0xf << (4 * i
);
1572 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
1573 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
1574 int index
= sel
->info
.input_semantic_index
[i
];
1575 sel
->color_attr_index
[index
] = i
;
1581 /* DB_SHADER_CONTROL */
1582 sel
->db_shader_control
=
1583 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
1584 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
1585 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
1586 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
1588 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
1589 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
1590 sel
->db_shader_control
|=
1591 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
1593 case TGSI_FS_DEPTH_LAYOUT_LESS
:
1594 sel
->db_shader_control
|=
1595 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
1599 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
1601 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
1602 * --|-----------|------------|------------|--------------------|-------------------|-------------
1603 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
1604 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
1605 * 2 | false | true | n/a | LateZ | 1 | 0
1606 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
1607 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
1609 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
1610 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
1612 * Don't use ReZ without profiling !!!
1614 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
1617 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
1619 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
1620 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
1621 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
1622 } else if (sel
->info
.writes_memory
) {
1624 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
1625 S_02880C_EXEC_ON_HIER_FAIL(1);
1628 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
1631 pipe_mutex_init(sel
->mutex
);
1632 util_queue_fence_init(&sel
->ready
);
1634 if ((sctx
->b
.debug
.debug_message
&& !sctx
->b
.debug
.async
) ||
1636 r600_can_dump_shader(&sscreen
->b
, sel
->info
.processor
) ||
1637 !util_queue_is_initialized(&sscreen
->shader_compiler_queue
))
1638 si_init_shader_selector_async(sel
, -1);
1640 util_queue_add_job(&sscreen
->shader_compiler_queue
, sel
,
1641 &sel
->ready
, si_init_shader_selector_async
,
1647 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
1649 struct si_context
*sctx
= (struct si_context
*)ctx
;
1650 struct si_shader_selector
*sel
= state
;
1652 if (sctx
->vs_shader
.cso
== sel
)
1655 sctx
->vs_shader
.cso
= sel
;
1656 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
1657 sctx
->do_update_shaders
= true;
1658 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1659 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
1662 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
1664 struct si_context
*sctx
= (struct si_context
*)ctx
;
1665 struct si_shader_selector
*sel
= state
;
1666 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
1668 if (sctx
->gs_shader
.cso
== sel
)
1671 sctx
->gs_shader
.cso
= sel
;
1672 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
1673 sctx
->do_update_shaders
= true;
1674 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1675 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
1678 si_shader_change_notify(sctx
);
1679 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
1682 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
1684 struct si_context
*sctx
= (struct si_context
*)ctx
;
1685 struct si_shader_selector
*sel
= state
;
1686 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
1688 if (sctx
->tcs_shader
.cso
== sel
)
1691 sctx
->tcs_shader
.cso
= sel
;
1692 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
1693 sctx
->do_update_shaders
= true;
1696 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
1699 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
1701 struct si_context
*sctx
= (struct si_context
*)ctx
;
1702 struct si_shader_selector
*sel
= state
;
1703 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
1705 if (sctx
->tes_shader
.cso
== sel
)
1708 sctx
->tes_shader
.cso
= sel
;
1709 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
1710 sctx
->do_update_shaders
= true;
1711 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1712 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
1714 if (enable_changed
) {
1715 si_shader_change_notify(sctx
);
1716 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
1718 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
1721 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
1723 struct si_context
*sctx
= (struct si_context
*)ctx
;
1724 struct si_shader_selector
*sel
= state
;
1726 /* skip if supplied shader is one already in use */
1727 if (sctx
->ps_shader
.cso
== sel
)
1730 sctx
->ps_shader
.cso
= sel
;
1731 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
1732 sctx
->do_update_shaders
= true;
1733 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
1736 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
1738 if (shader
->is_optimized
) {
1739 util_queue_job_wait(&shader
->optimized_ready
);
1740 util_queue_fence_destroy(&shader
->optimized_ready
);
1744 switch (shader
->selector
->type
) {
1745 case PIPE_SHADER_VERTEX
:
1746 if (shader
->key
.as_ls
)
1747 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
1748 else if (shader
->key
.as_es
)
1749 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
1751 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
1753 case PIPE_SHADER_TESS_CTRL
:
1754 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
1756 case PIPE_SHADER_TESS_EVAL
:
1757 if (shader
->key
.as_es
)
1758 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
1760 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
1762 case PIPE_SHADER_GEOMETRY
:
1763 if (shader
->is_gs_copy_shader
)
1764 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
1766 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
1768 case PIPE_SHADER_FRAGMENT
:
1769 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
1774 si_shader_destroy(shader
);
1778 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
1780 struct si_context
*sctx
= (struct si_context
*)ctx
;
1781 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
1782 struct si_shader
*p
= sel
->first_variant
, *c
;
1783 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
1784 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
1785 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
1786 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
1787 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
1788 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
1791 util_queue_job_wait(&sel
->ready
);
1793 if (current_shader
[sel
->type
]->cso
== sel
) {
1794 current_shader
[sel
->type
]->cso
= NULL
;
1795 current_shader
[sel
->type
]->current
= NULL
;
1799 c
= p
->next_variant
;
1800 si_delete_shader(sctx
, p
);
1804 if (sel
->main_shader_part
)
1805 si_delete_shader(sctx
, sel
->main_shader_part
);
1806 if (sel
->gs_copy_shader
)
1807 si_delete_shader(sctx
, sel
->gs_copy_shader
);
1809 util_queue_fence_destroy(&sel
->ready
);
1810 pipe_mutex_destroy(sel
->mutex
);
1815 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
1816 struct si_shader
*vs
, unsigned name
,
1817 unsigned index
, unsigned interpolate
)
1819 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
1820 unsigned j
, offset
, ps_input_cntl
= 0;
1822 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
1823 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
))
1824 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
1826 if (name
== TGSI_SEMANTIC_PCOORD
||
1827 (name
== TGSI_SEMANTIC_TEXCOORD
&&
1828 sctx
->sprite_coord_enable
& (1 << index
))) {
1829 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
1832 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
1833 if (name
== vsinfo
->output_semantic_name
[j
] &&
1834 index
== vsinfo
->output_semantic_index
[j
]) {
1835 offset
= vs
->info
.vs_output_param_offset
[j
];
1837 if (offset
<= EXP_PARAM_OFFSET_31
) {
1838 /* The input is loaded from parameter memory. */
1839 ps_input_cntl
|= S_028644_OFFSET(offset
);
1840 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
1841 if (offset
== EXP_PARAM_UNDEFINED
) {
1842 /* This can happen with depth-only rendering. */
1845 /* The input is a DEFAULT_VAL constant. */
1846 assert(offset
>= EXP_PARAM_DEFAULT_VAL_0000
&&
1847 offset
<= EXP_PARAM_DEFAULT_VAL_1111
);
1848 offset
-= EXP_PARAM_DEFAULT_VAL_0000
;
1851 ps_input_cntl
= S_028644_OFFSET(0x20) |
1852 S_028644_DEFAULT_VAL(offset
);
1858 if (name
== TGSI_SEMANTIC_PRIMID
)
1859 /* PrimID is written after the last output. */
1860 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
1861 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
1862 /* No corresponding output found, load defaults into input.
1863 * Don't set any other bits.
1864 * (FLAT_SHADE=1 completely changes behavior) */
1865 ps_input_cntl
= S_028644_OFFSET(0x20);
1866 /* D3D 9 behaviour. GL is undefined */
1867 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
1868 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
1870 return ps_input_cntl
;
1873 static void si_emit_spi_map(struct si_context
*sctx
, struct r600_atom
*atom
)
1875 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1876 struct si_shader
*ps
= sctx
->ps_shader
.current
;
1877 struct si_shader
*vs
= si_get_vs_state(sctx
);
1878 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
1879 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
1881 if (!ps
|| !ps
->selector
->info
.num_inputs
)
1884 num_interp
= si_get_ps_num_interp(ps
);
1885 assert(num_interp
> 0);
1886 radeon_set_context_reg_seq(cs
, R_028644_SPI_PS_INPUT_CNTL_0
, num_interp
);
1888 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
1889 unsigned name
= psinfo
->input_semantic_name
[i
];
1890 unsigned index
= psinfo
->input_semantic_index
[i
];
1891 unsigned interpolate
= psinfo
->input_interpolate
[i
];
1893 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, name
, index
,
1897 if (name
== TGSI_SEMANTIC_COLOR
) {
1898 assert(index
< ARRAY_SIZE(bcol_interp
));
1899 bcol_interp
[index
] = interpolate
;
1903 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
1904 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
1906 for (i
= 0; i
< 2; i
++) {
1907 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
1910 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, bcol
,
1911 i
, bcol_interp
[i
]));
1915 assert(num_interp
== num_written
);
1919 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1921 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
1923 if (sctx
->init_config_has_vgt_flush
)
1926 /* Done by Vulkan before VGT_FLUSH. */
1927 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
1928 si_pm4_cmd_add(sctx
->init_config
,
1929 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1930 si_pm4_cmd_end(sctx
->init_config
, false);
1932 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
1933 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
1934 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1935 si_pm4_cmd_end(sctx
->init_config
, false);
1936 sctx
->init_config_has_vgt_flush
= true;
1939 /* Initialize state related to ESGS / GSVS ring buffers */
1940 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
1942 struct si_shader_selector
*es
=
1943 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
1944 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
1945 struct si_pm4_state
*pm4
;
1947 /* Chip constants. */
1948 unsigned num_se
= sctx
->screen
->b
.info
.max_se
;
1949 unsigned wave_size
= 64;
1950 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1951 unsigned gs_vertex_reuse
= 16 * num_se
; /* GS_VERTEX_REUSE register (per SE) */
1952 unsigned alignment
= 256 * num_se
;
1953 /* The maximum size is 63.999 MB per SE. */
1954 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1956 /* Calculate the minimum size. */
1957 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
1958 wave_size
, alignment
);
1960 /* These are recommended sizes, not minimum sizes. */
1961 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1962 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
1963 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1964 gs
->max_gsvs_emit_size
;
1966 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1967 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1968 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1970 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1971 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1973 /* Some rings don't have to be allocated if shaders don't use them.
1974 * (e.g. no varyings between ES and GS or GS and VS)
1976 bool update_esgs
= esgs_ring_size
&&
1977 (!sctx
->esgs_ring
||
1978 sctx
->esgs_ring
->width0
< esgs_ring_size
);
1979 bool update_gsvs
= gsvs_ring_size
&&
1980 (!sctx
->gsvs_ring
||
1981 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
1983 if (!update_esgs
&& !update_gsvs
)
1987 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
1988 sctx
->esgs_ring
= pipe_buffer_create(sctx
->b
.b
.screen
, 0,
1991 if (!sctx
->esgs_ring
)
1996 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
1997 sctx
->gsvs_ring
= pipe_buffer_create(sctx
->b
.b
.screen
, 0,
2000 if (!sctx
->gsvs_ring
)
2004 /* Create the "init_config_gs_rings" state. */
2005 pm4
= CALLOC_STRUCT(si_pm4_state
);
2009 if (sctx
->b
.chip_class
>= CIK
) {
2010 if (sctx
->esgs_ring
)
2011 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
2012 sctx
->esgs_ring
->width0
/ 256);
2013 if (sctx
->gsvs_ring
)
2014 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
2015 sctx
->gsvs_ring
->width0
/ 256);
2017 if (sctx
->esgs_ring
)
2018 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
2019 sctx
->esgs_ring
->width0
/ 256);
2020 if (sctx
->gsvs_ring
)
2021 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
2022 sctx
->gsvs_ring
->width0
/ 256);
2025 /* Set the state. */
2026 if (sctx
->init_config_gs_rings
)
2027 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
2028 sctx
->init_config_gs_rings
= pm4
;
2030 if (!sctx
->init_config_has_vgt_flush
) {
2031 si_init_config_add_vgt_flush(sctx
);
2032 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
2035 /* Flush the context to re-emit both init_config states. */
2036 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
2037 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
2039 /* Set ring bindings. */
2040 if (sctx
->esgs_ring
) {
2041 si_set_ring_buffer(&sctx
->b
.b
, SI_ES_RING_ESGS
,
2042 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2043 true, true, 4, 64, 0);
2044 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_ESGS
,
2045 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2046 false, false, 0, 0, 0);
2048 if (sctx
->gsvs_ring
) {
2049 si_set_ring_buffer(&sctx
->b
.b
, SI_RING_GSVS
,
2050 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
2051 false, false, 0, 0, 0);
2058 * @returns 1 if \p sel has been updated to use a new scratch buffer
2060 * < 0 if there was a failure
2062 static int si_update_scratch_buffer(struct si_context
*sctx
,
2063 struct si_shader
*shader
)
2065 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
2071 /* This shader doesn't need a scratch buffer */
2072 if (shader
->config
.scratch_bytes_per_wave
== 0)
2075 /* This shader is already configured to use the current
2076 * scratch buffer. */
2077 if (shader
->scratch_bo
== sctx
->scratch_buffer
)
2080 assert(sctx
->scratch_buffer
);
2082 si_shader_apply_scratch_relocs(sctx
, shader
, &shader
->config
, scratch_va
);
2084 /* Replace the shader bo with a new bo that has the relocs applied. */
2085 r
= si_shader_binary_upload(sctx
->screen
, shader
);
2089 /* Update the shader state to use the new shader bo. */
2090 si_shader_init_pm4_state(sctx
->screen
, shader
);
2092 r600_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
2097 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
2099 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
2102 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
2104 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
2107 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
2111 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
2112 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
2113 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
2114 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tcs_shader
.current
));
2115 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
2119 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
2121 unsigned current_scratch_buffer_size
=
2122 si_get_current_scratch_buffer_size(sctx
);
2123 unsigned scratch_bytes_per_wave
=
2124 si_get_max_scratch_bytes_per_wave(sctx
);
2125 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
2126 sctx
->scratch_waves
;
2127 unsigned spi_tmpring_size
;
2130 if (scratch_needed_size
> 0) {
2131 if (scratch_needed_size
> current_scratch_buffer_size
) {
2132 /* Create a bigger scratch buffer */
2133 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
2135 sctx
->scratch_buffer
= (struct r600_resource
*)
2136 pipe_buffer_create(&sctx
->screen
->b
.b
, 0,
2137 PIPE_USAGE_DEFAULT
, scratch_needed_size
);
2138 if (!sctx
->scratch_buffer
)
2140 sctx
->emit_scratch_reloc
= true;
2143 /* Update the shaders, so they are using the latest scratch. The
2144 * scratch buffer may have been changed since these shaders were
2145 * last used, so we still need to try to update them, even if
2146 * they require scratch buffers smaller than the current size.
2148 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
2152 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
2154 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
2158 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
2160 r
= si_update_scratch_buffer(sctx
, sctx
->tcs_shader
.current
);
2164 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
2166 /* VS can be bound as LS, ES, or VS. */
2167 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
2171 if (sctx
->tes_shader
.current
)
2172 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
2173 else if (sctx
->gs_shader
.current
)
2174 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
2176 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
2179 /* TES can be bound as ES or VS. */
2180 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
2184 if (sctx
->gs_shader
.current
)
2185 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
2187 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
2191 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2192 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
2193 "scratch size should already be aligned correctly.");
2195 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
2196 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
2197 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
2198 sctx
->spi_tmpring_size
= spi_tmpring_size
;
2199 sctx
->emit_scratch_reloc
= true;
2204 static void si_init_tess_factor_ring(struct si_context
*sctx
)
2206 bool double_offchip_buffers
= sctx
->b
.chip_class
>= CIK
;
2207 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
2208 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
2209 sctx
->screen
->b
.info
.max_se
;
2210 unsigned offchip_granularity
;
2212 switch (sctx
->screen
->tess_offchip_block_dw_size
) {
2217 offchip_granularity
= V_03093C_X_8K_DWORDS
;
2220 offchip_granularity
= V_03093C_X_4K_DWORDS
;
2224 switch (sctx
->b
.chip_class
) {
2226 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
2229 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
2233 max_offchip_buffers
= MIN2(max_offchip_buffers
, 512);
2237 assert(!sctx
->tf_ring
);
2238 sctx
->tf_ring
= pipe_buffer_create(sctx
->b
.b
.screen
, 0,
2240 32768 * sctx
->screen
->b
.info
.max_se
);
2244 assert(((sctx
->tf_ring
->width0
/ 4) & C_030938_SIZE
) == 0);
2246 sctx
->tess_offchip_ring
= pipe_buffer_create(sctx
->b
.b
.screen
, 0,
2248 max_offchip_buffers
*
2249 sctx
->screen
->tess_offchip_block_dw_size
* 4);
2250 if (!sctx
->tess_offchip_ring
)
2253 si_init_config_add_vgt_flush(sctx
);
2255 /* Append these registers to the init config state. */
2256 if (sctx
->b
.chip_class
>= CIK
) {
2257 if (sctx
->b
.chip_class
>= VI
)
2258 --max_offchip_buffers
;
2260 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
2261 S_030938_SIZE(sctx
->tf_ring
->width0
/ 4));
2262 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
2263 r600_resource(sctx
->tf_ring
)->gpu_address
>> 8);
2264 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
2265 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
2266 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
));
2268 assert(offchip_granularity
== V_03093C_X_8K_DWORDS
);
2269 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
2270 S_008988_SIZE(sctx
->tf_ring
->width0
/ 4));
2271 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
2272 r600_resource(sctx
->tf_ring
)->gpu_address
>> 8);
2273 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
2274 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
));
2277 /* Flush the context to re-emit the init_config state.
2278 * This is done only once in a lifetime of a context.
2280 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
2281 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
2282 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
2284 si_set_ring_buffer(&sctx
->b
.b
, SI_HS_RING_TESS_FACTOR
, sctx
->tf_ring
,
2285 0, sctx
->tf_ring
->width0
, false, false, 0, 0, 0);
2287 si_set_ring_buffer(&sctx
->b
.b
, SI_HS_RING_TESS_OFFCHIP
,
2288 sctx
->tess_offchip_ring
, 0,
2289 sctx
->tess_offchip_ring
->width0
, false, false, 0, 0, 0);
2293 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
2294 * VS passes its outputs to TES directly, so the fixed-function shader only
2295 * has to write TESSOUTER and TESSINNER.
2297 static void si_generate_fixed_func_tcs(struct si_context
*sctx
)
2299 struct ureg_src outer
, inner
;
2300 struct ureg_dst tessouter
, tessinner
;
2301 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
2304 return; /* if we get here, we're screwed */
2306 assert(!sctx
->fixed_func_tcs_shader
.cso
);
2308 outer
= ureg_DECL_system_value(ureg
,
2309 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
, 0);
2310 inner
= ureg_DECL_system_value(ureg
,
2311 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
, 0);
2313 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
2314 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
2316 ureg_MOV(ureg
, tessouter
, outer
);
2317 ureg_MOV(ureg
, tessinner
, inner
);
2320 sctx
->fixed_func_tcs_shader
.cso
=
2321 ureg_create_shader_and_destroy(ureg
, &sctx
->b
.b
);
2324 static void si_update_vgt_shader_config(struct si_context
*sctx
)
2326 /* Calculate the index of the config.
2327 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
2328 unsigned index
= 2*!!sctx
->tes_shader
.cso
+ !!sctx
->gs_shader
.cso
;
2329 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[index
];
2332 uint32_t stages
= 0;
2334 *pm4
= CALLOC_STRUCT(si_pm4_state
);
2336 if (sctx
->tes_shader
.cso
) {
2337 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
2338 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2340 if (sctx
->gs_shader
.cso
)
2341 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
2343 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2345 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
2346 } else if (sctx
->gs_shader
.cso
) {
2347 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
2349 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2352 si_pm4_set_reg(*pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
2354 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
2357 static void si_update_so(struct si_context
*sctx
, struct si_shader_selector
*shader
)
2359 struct pipe_stream_output_info
*so
= &shader
->so
;
2360 uint32_t enabled_stream_buffers_mask
= 0;
2363 for (i
= 0; i
< so
->num_outputs
; i
++)
2364 enabled_stream_buffers_mask
|= (1 << so
->output
[i
].output_buffer
) << (so
->output
[i
].stream
* 4);
2365 sctx
->b
.streamout
.enabled_stream_buffers_mask
= enabled_stream_buffers_mask
;
2366 sctx
->b
.streamout
.stride_in_dw
= shader
->so
.stride
;
2369 bool si_update_shaders(struct si_context
*sctx
)
2371 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
2372 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
2375 /* Update stages before GS. */
2376 if (sctx
->tes_shader
.cso
) {
2377 if (!sctx
->tf_ring
) {
2378 si_init_tess_factor_ring(sctx
);
2384 r
= si_shader_select(ctx
, &sctx
->vs_shader
);
2387 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
2389 if (sctx
->tcs_shader
.cso
) {
2390 r
= si_shader_select(ctx
, &sctx
->tcs_shader
);
2393 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
2395 if (!sctx
->fixed_func_tcs_shader
.cso
) {
2396 si_generate_fixed_func_tcs(sctx
);
2397 if (!sctx
->fixed_func_tcs_shader
.cso
)
2401 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
);
2404 si_pm4_bind_state(sctx
, hs
,
2405 sctx
->fixed_func_tcs_shader
.current
->pm4
);
2408 r
= si_shader_select(ctx
, &sctx
->tes_shader
);
2412 if (sctx
->gs_shader
.cso
) {
2414 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
2417 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
2418 si_update_so(sctx
, sctx
->tes_shader
.cso
);
2420 } else if (sctx
->gs_shader
.cso
) {
2422 r
= si_shader_select(ctx
, &sctx
->vs_shader
);
2425 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
2428 r
= si_shader_select(ctx
, &sctx
->vs_shader
);
2431 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
2432 si_update_so(sctx
, sctx
->vs_shader
.cso
);
2436 if (sctx
->gs_shader
.cso
) {
2437 r
= si_shader_select(ctx
, &sctx
->gs_shader
);
2440 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
2441 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
2442 si_update_so(sctx
, sctx
->gs_shader
.cso
);
2444 if (!si_update_gs_ring_buffers(sctx
))
2447 si_pm4_bind_state(sctx
, gs
, NULL
);
2448 si_pm4_bind_state(sctx
, es
, NULL
);
2451 si_update_vgt_shader_config(sctx
);
2453 if (sctx
->ps_shader
.cso
) {
2454 unsigned db_shader_control
;
2456 r
= si_shader_select(ctx
, &sctx
->ps_shader
);
2459 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
2462 sctx
->ps_shader
.cso
->db_shader_control
|
2463 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
2465 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
2466 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
2467 sctx
->flatshade
!= rs
->flatshade
) {
2468 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
2469 sctx
->flatshade
= rs
->flatshade
;
2470 si_mark_atom_dirty(sctx
, &sctx
->spi_map
);
2473 if (sctx
->b
.family
== CHIP_STONEY
&& si_pm4_state_changed(sctx
, ps
))
2474 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
2476 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
2477 sctx
->ps_db_shader_control
= db_shader_control
;
2478 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2481 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
2482 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
2483 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2485 if (sctx
->b
.chip_class
== SI
)
2486 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2488 if (sctx
->framebuffer
.nr_samples
<= 1)
2489 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
2493 if (si_pm4_state_changed(sctx
, ls
) ||
2494 si_pm4_state_changed(sctx
, hs
) ||
2495 si_pm4_state_changed(sctx
, es
) ||
2496 si_pm4_state_changed(sctx
, gs
) ||
2497 si_pm4_state_changed(sctx
, vs
) ||
2498 si_pm4_state_changed(sctx
, ps
)) {
2499 if (!si_update_spi_tmpring_size(sctx
))
2503 sctx
->do_update_shaders
= false;
2507 void si_init_shader_functions(struct si_context
*sctx
)
2509 si_init_atom(sctx
, &sctx
->spi_map
, &sctx
->atoms
.s
.spi_map
, si_emit_spi_map
);
2511 sctx
->b
.b
.create_vs_state
= si_create_shader_selector
;
2512 sctx
->b
.b
.create_tcs_state
= si_create_shader_selector
;
2513 sctx
->b
.b
.create_tes_state
= si_create_shader_selector
;
2514 sctx
->b
.b
.create_gs_state
= si_create_shader_selector
;
2515 sctx
->b
.b
.create_fs_state
= si_create_shader_selector
;
2517 sctx
->b
.b
.bind_vs_state
= si_bind_vs_shader
;
2518 sctx
->b
.b
.bind_tcs_state
= si_bind_tcs_shader
;
2519 sctx
->b
.b
.bind_tes_state
= si_bind_tes_shader
;
2520 sctx
->b
.b
.bind_gs_state
= si_bind_gs_shader
;
2521 sctx
->b
.b
.bind_fs_state
= si_bind_ps_shader
;
2523 sctx
->b
.b
.delete_vs_state
= si_delete_shader_selector
;
2524 sctx
->b
.b
.delete_tcs_state
= si_delete_shader_selector
;
2525 sctx
->b
.b
.delete_tes_state
= si_delete_shader_selector
;
2526 sctx
->b
.b
.delete_gs_state
= si_delete_shader_selector
;
2527 sctx
->b
.b
.delete_fs_state
= si_delete_shader_selector
;