2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
47 void *si_get_ir_binary(struct si_shader_selector
*sel
)
54 ir_binary
= sel
->tokens
;
55 ir_size
= tgsi_num_tokens(sel
->tokens
) *
56 sizeof(struct tgsi_token
);
61 nir_serialize(&blob
, sel
->nir
);
62 ir_binary
= blob
.data
;
66 unsigned size
= 4 + ir_size
+ sizeof(sel
->so
);
67 char *result
= (char*)MALLOC(size
);
71 *((uint32_t*)result
) = size
;
72 memcpy(result
+ 4, ir_binary
, ir_size
);
73 memcpy(result
+ 4 + ir_size
, &sel
->so
, sizeof(sel
->so
));
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
84 /* data may be NULL if size == 0 */
86 memcpy(ptr
, data
, size
);
87 ptr
+= DIV_ROUND_UP(size
, 4);
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
94 memcpy(data
, ptr
, size
);
95 ptr
+= DIV_ROUND_UP(size
, 4);
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
103 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
106 return write_data(ptr
, data
, size
);
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
113 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
116 assert(*data
== NULL
);
119 *data
= malloc(*size
);
120 return read_data(ptr
, *data
, *size
);
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
127 static void *si_get_shader_binary(struct si_shader
*shader
)
129 /* There is always a size of data followed by the data itself. */
130 unsigned relocs_size
= shader
->binary
.reloc_count
*
131 sizeof(shader
->binary
.relocs
[0]);
132 unsigned disasm_size
= shader
->binary
.disasm_string
?
133 strlen(shader
->binary
.disasm_string
) + 1 : 0;
134 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
135 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
138 4 + /* CRC32 of the data below */
139 align(sizeof(shader
->config
), 4) +
140 align(sizeof(shader
->info
), 4) +
141 4 + align(shader
->binary
.code_size
, 4) +
142 4 + align(shader
->binary
.rodata_size
, 4) +
143 4 + align(relocs_size
, 4) +
144 4 + align(disasm_size
, 4) +
145 4 + align(llvm_ir_size
, 4);
146 void *buffer
= CALLOC(1, size
);
147 uint32_t *ptr
= (uint32_t*)buffer
;
153 ptr
++; /* CRC32 is calculated at the end. */
155 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
156 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
157 ptr
= write_chunk(ptr
, shader
->binary
.code
, shader
->binary
.code_size
);
158 ptr
= write_chunk(ptr
, shader
->binary
.rodata
, shader
->binary
.rodata_size
);
159 ptr
= write_chunk(ptr
, shader
->binary
.relocs
, relocs_size
);
160 ptr
= write_chunk(ptr
, shader
->binary
.disasm_string
, disasm_size
);
161 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
162 assert((char *)ptr
- (char *)buffer
== size
);
165 ptr
= (uint32_t*)buffer
;
167 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
172 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
174 uint32_t *ptr
= (uint32_t*)binary
;
175 uint32_t size
= *ptr
++;
176 uint32_t crc32
= *ptr
++;
179 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
180 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
184 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
185 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
186 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.code
,
187 &shader
->binary
.code_size
);
188 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.rodata
,
189 &shader
->binary
.rodata_size
);
190 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.relocs
, &chunk_size
);
191 shader
->binary
.reloc_count
= chunk_size
/ sizeof(shader
->binary
.relocs
[0]);
192 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.disasm_string
, &chunk_size
);
193 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
199 * Insert a shader into the cache. It's assumed the shader is not in the cache.
200 * Use si_shader_cache_load_shader before calling this.
202 * Returns false on failure, in which case the ir_binary should be freed.
204 bool si_shader_cache_insert_shader(struct si_screen
*sscreen
, void *ir_binary
,
205 struct si_shader
*shader
,
206 bool insert_into_disk_cache
)
209 struct hash_entry
*entry
;
210 uint8_t key
[CACHE_KEY_SIZE
];
212 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
214 return false; /* already added */
216 hw_binary
= si_get_shader_binary(shader
);
220 if (_mesa_hash_table_insert(sscreen
->shader_cache
, ir_binary
,
221 hw_binary
) == NULL
) {
226 if (sscreen
->disk_shader_cache
&& insert_into_disk_cache
) {
227 disk_cache_compute_key(sscreen
->disk_shader_cache
, ir_binary
,
228 *((uint32_t *)ir_binary
), key
);
229 disk_cache_put(sscreen
->disk_shader_cache
, key
, hw_binary
,
230 *((uint32_t *) hw_binary
), NULL
);
236 bool si_shader_cache_load_shader(struct si_screen
*sscreen
, void *ir_binary
,
237 struct si_shader
*shader
)
239 struct hash_entry
*entry
=
240 _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
242 if (sscreen
->disk_shader_cache
) {
243 unsigned char sha1
[CACHE_KEY_SIZE
];
244 size_t tg_size
= *((uint32_t *) ir_binary
);
246 disk_cache_compute_key(sscreen
->disk_shader_cache
,
247 ir_binary
, tg_size
, sha1
);
251 disk_cache_get(sscreen
->disk_shader_cache
,
256 if (binary_size
< sizeof(uint32_t) ||
257 *((uint32_t*)buffer
) != binary_size
) {
258 /* Something has gone wrong discard the item
259 * from the cache and rebuild/link from
262 assert(!"Invalid radeonsi shader disk cache "
265 disk_cache_remove(sscreen
->disk_shader_cache
,
272 if (!si_load_shader_binary(shader
, buffer
)) {
278 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
,
285 if (si_load_shader_binary(shader
, entry
->data
))
290 p_atomic_inc(&sscreen
->num_shader_cache_hits
);
294 static uint32_t si_shader_cache_key_hash(const void *key
)
296 /* The first dword is the key size. */
297 return util_hash_crc32(key
, *(uint32_t*)key
);
300 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
302 uint32_t *keya
= (uint32_t*)a
;
303 uint32_t *keyb
= (uint32_t*)b
;
305 /* The first dword is the key size. */
309 return memcmp(keya
, keyb
, *keya
) == 0;
312 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
314 FREE((void*)entry
->key
);
318 bool si_init_shader_cache(struct si_screen
*sscreen
)
320 (void) mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
321 sscreen
->shader_cache
=
322 _mesa_hash_table_create(NULL
,
323 si_shader_cache_key_hash
,
324 si_shader_cache_key_equals
);
326 return sscreen
->shader_cache
!= NULL
;
329 void si_destroy_shader_cache(struct si_screen
*sscreen
)
331 if (sscreen
->shader_cache
)
332 _mesa_hash_table_destroy(sscreen
->shader_cache
,
333 si_destroy_shader_cache_entry
);
334 mtx_destroy(&sscreen
->shader_cache_mutex
);
339 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
340 struct si_shader_selector
*tes
,
341 struct si_pm4_state
*pm4
)
343 struct tgsi_shader_info
*info
= &tes
->info
;
344 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
345 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
346 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
347 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
348 unsigned type
, partitioning
, topology
, distribution_mode
;
350 switch (tes_prim_mode
) {
351 case PIPE_PRIM_LINES
:
352 type
= V_028B6C_TESS_ISOLINE
;
354 case PIPE_PRIM_TRIANGLES
:
355 type
= V_028B6C_TESS_TRIANGLE
;
357 case PIPE_PRIM_QUADS
:
358 type
= V_028B6C_TESS_QUAD
;
365 switch (tes_spacing
) {
366 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
367 partitioning
= V_028B6C_PART_FRAC_ODD
;
369 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
370 partitioning
= V_028B6C_PART_FRAC_EVEN
;
372 case PIPE_TESS_SPACING_EQUAL
:
373 partitioning
= V_028B6C_PART_INTEGER
;
381 topology
= V_028B6C_OUTPUT_POINT
;
382 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
383 topology
= V_028B6C_OUTPUT_LINE
;
384 else if (tes_vertex_order_cw
)
385 /* for some reason, this must be the other way around */
386 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
388 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
390 if (sscreen
->has_distributed_tess
) {
391 if (sscreen
->info
.family
== CHIP_FIJI
||
392 sscreen
->info
.family
>= CHIP_POLARIS10
)
393 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
395 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
397 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
399 si_pm4_set_reg(pm4
, R_028B6C_VGT_TF_PARAM
,
400 S_028B6C_TYPE(type
) |
401 S_028B6C_PARTITIONING(partitioning
) |
402 S_028B6C_TOPOLOGY(topology
) |
403 S_028B6C_DISTRIBUTION_MODE(distribution_mode
));
406 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
407 * whether the "fractional odd" tessellation spacing is used.
409 * Possible VGT configurations and which state should set the register:
411 * Reg set in | VGT shader configuration | Value
412 * ------------------------------------------------------
414 * VS as ES | ES -> GS -> VS | 30
415 * TES as VS | LS -> HS -> VS | 14 or 30
416 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
418 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
420 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
421 struct si_shader_selector
*sel
,
422 struct si_shader
*shader
,
423 struct si_pm4_state
*pm4
)
425 unsigned type
= sel
->type
;
427 if (sscreen
->info
.family
< CHIP_POLARIS10
)
430 /* VS as VS, or VS as ES: */
431 if ((type
== PIPE_SHADER_VERTEX
&&
433 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
434 /* TES as VS, or TES as ES: */
435 type
== PIPE_SHADER_TESS_EVAL
) {
436 unsigned vtx_reuse_depth
= 30;
438 if (type
== PIPE_SHADER_TESS_EVAL
&&
439 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
440 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
441 vtx_reuse_depth
= 14;
443 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
448 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
451 si_pm4_clear_state(shader
->pm4
);
453 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
456 shader
->pm4
->shader
= shader
;
459 fprintf(stderr
, "radeonsi: Failed to create pm4 state.\n");
464 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs
)
466 /* Add the pointer to VBO descriptors. */
467 if (HAVE_32BIT_POINTERS
) {
468 return num_always_on_user_sgprs
+ 1;
470 assert(num_always_on_user_sgprs
% 2 == 0);
471 return num_always_on_user_sgprs
+ 2;
475 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
477 struct si_pm4_state
*pm4
;
478 unsigned vgpr_comp_cnt
;
481 assert(sscreen
->info
.chip_class
<= VI
);
483 pm4
= si_get_shader_pm4_state(shader
);
487 va
= shader
->bo
->gpu_address
;
488 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
490 /* We need at least 2 components for LS.
491 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
492 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
494 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
496 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
497 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
499 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
500 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
501 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
502 S_00B528_DX10_CLAMP(1) |
503 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
504 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
)) |
505 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
508 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
510 struct si_pm4_state
*pm4
;
512 unsigned ls_vgpr_comp_cnt
= 0;
514 pm4
= si_get_shader_pm4_state(shader
);
518 va
= shader
->bo
->gpu_address
;
519 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
521 if (sscreen
->info
.chip_class
>= GFX9
) {
522 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
523 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, S_00B414_MEM_BASE(va
>> 40));
525 /* We need at least 2 components for LS.
526 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
527 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
529 ls_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
531 unsigned num_user_sgprs
=
532 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR
);
534 shader
->config
.rsrc2
=
535 S_00B42C_USER_SGPR(num_user_sgprs
) |
536 S_00B42C_USER_SGPR_MSB(num_user_sgprs
>> 5) |
537 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
539 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
540 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, S_00B424_MEM_BASE(va
>> 40));
542 shader
->config
.rsrc2
=
543 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
544 S_00B42C_OC_LDS_EN(1) |
545 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
548 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
549 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
550 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
551 S_00B428_DX10_CLAMP(1) |
552 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
553 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt
));
555 if (sscreen
->info
.chip_class
<= VI
) {
556 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
557 shader
->config
.rsrc2
);
561 static void si_emit_shader_es(struct si_context
*sctx
)
563 struct si_shader
*shader
= sctx
->queued
.named
.es
->shader
;
568 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
569 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
570 shader
->selector
->esgs_itemsize
/ 4);
573 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
575 struct si_pm4_state
*pm4
;
576 unsigned num_user_sgprs
;
577 unsigned vgpr_comp_cnt
;
581 assert(sscreen
->info
.chip_class
<= VI
);
583 pm4
= si_get_shader_pm4_state(shader
);
587 pm4
->atom
.emit
= si_emit_shader_es
;
588 va
= shader
->bo
->gpu_address
;
589 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
591 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
592 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
593 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
594 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
595 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
596 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
597 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
599 unreachable("invalid shader selector type");
601 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
603 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
604 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
605 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
606 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
607 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
608 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
609 S_00B328_DX10_CLAMP(1) |
610 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
611 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
612 S_00B32C_USER_SGPR(num_user_sgprs
) |
613 S_00B32C_OC_LDS_EN(oc_lds_en
) |
614 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
616 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
617 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
619 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
622 static unsigned si_conv_prim_to_gs_out(unsigned mode
)
624 static const int prim_conv
[] = {
625 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
626 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
627 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
628 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
629 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
630 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
631 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
632 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
633 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
634 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
635 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
636 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
637 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
638 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
639 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
641 assert(mode
< ARRAY_SIZE(prim_conv
));
643 return prim_conv
[mode
];
646 struct gfx9_gs_info
{
647 unsigned es_verts_per_subgroup
;
648 unsigned gs_prims_per_subgroup
;
649 unsigned gs_inst_prims_in_subgroup
;
650 unsigned max_prims_per_subgroup
;
654 static void gfx9_get_gs_info(struct si_shader_selector
*es
,
655 struct si_shader_selector
*gs
,
656 struct gfx9_gs_info
*out
)
658 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
659 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
660 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
661 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
663 /* All these are in dwords: */
664 /* We can't allow using the whole LDS, because GS waves compete with
665 * other shader stages for LDS space. */
666 const unsigned max_lds_size
= 8 * 1024;
667 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
668 unsigned esgs_lds_size
;
670 /* All these are per subgroup: */
671 const unsigned max_out_prims
= 32 * 1024;
672 const unsigned max_es_verts
= 255;
673 const unsigned ideal_gs_prims
= 64;
674 unsigned max_gs_prims
, gs_prims
;
675 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
677 if (uses_adjacency
|| gs_num_invocations
> 1)
678 max_gs_prims
= 127 / gs_num_invocations
;
682 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
683 * Make sure we don't go over the maximum value.
685 if (gs
->gs_max_out_vertices
> 0) {
686 max_gs_prims
= MIN2(max_gs_prims
,
688 (gs
->gs_max_out_vertices
* gs_num_invocations
));
690 assert(max_gs_prims
> 0);
692 /* If the primitive has adjacency, halve the number of vertices
693 * that will be reused in multiple primitives.
695 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
697 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
698 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
700 /* Compute ESGS LDS size based on the worst case number of ES vertices
701 * needed to create the target number of GS prims per subgroup.
703 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
705 /* If total LDS usage is too big, refactor partitions based on ratio
706 * of ESGS item sizes.
708 if (esgs_lds_size
> max_lds_size
) {
709 /* Our target GS Prims Per Subgroup was too large. Calculate
710 * the maximum number of GS Prims Per Subgroup that will fit
711 * into LDS, capped by the maximum that the hardware can support.
713 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
715 assert(gs_prims
> 0);
716 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
719 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
720 assert(esgs_lds_size
<= max_lds_size
);
723 /* Now calculate remaining ESGS information. */
725 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
727 es_verts
= max_es_verts
;
729 /* Vertices for adjacency primitives are not always reused, so restore
730 * it for ES_VERTS_PER_SUBGRP.
732 min_es_verts
= gs
->gs_input_verts_per_prim
;
734 /* For normal primitives, the VGT only checks if they are past the ES
735 * verts per subgroup after allocating a full GS primitive and if they
736 * are, kick off a new subgroup. But if those additional ES verts are
737 * unique (e.g. not reused) we need to make sure there is enough LDS
738 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
740 es_verts
-= min_es_verts
- 1;
742 out
->es_verts_per_subgroup
= es_verts
;
743 out
->gs_prims_per_subgroup
= gs_prims
;
744 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
745 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
746 gs
->gs_max_out_vertices
;
747 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
749 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
752 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
754 struct si_shader_selector
*sel
= shader
->selector
;
755 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
756 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
757 struct si_pm4_state
*pm4
;
759 unsigned max_stream
= sel
->max_gs_stream
;
762 pm4
= si_get_shader_pm4_state(shader
);
766 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
767 si_pm4_set_reg(pm4
, R_028A60_VGT_GSVS_RING_OFFSET_1
, offset
);
769 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
770 si_pm4_set_reg(pm4
, R_028A64_VGT_GSVS_RING_OFFSET_2
, offset
);
772 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
773 si_pm4_set_reg(pm4
, R_028A68_VGT_GSVS_RING_OFFSET_3
, offset
);
774 si_pm4_set_reg(pm4
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
,
775 si_conv_prim_to_gs_out(sel
->gs_output_prim
));
777 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
778 si_pm4_set_reg(pm4
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
780 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
781 assert(offset
< (1 << 15));
783 si_pm4_set_reg(pm4
, R_028B38_VGT_GS_MAX_VERT_OUT
, sel
->gs_max_out_vertices
);
785 si_pm4_set_reg(pm4
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, num_components
[0]);
786 si_pm4_set_reg(pm4
, R_028B60_VGT_GS_VERT_ITEMSIZE_1
, (max_stream
>= 1) ? num_components
[1] : 0);
787 si_pm4_set_reg(pm4
, R_028B64_VGT_GS_VERT_ITEMSIZE_2
, (max_stream
>= 2) ? num_components
[2] : 0);
788 si_pm4_set_reg(pm4
, R_028B68_VGT_GS_VERT_ITEMSIZE_3
, (max_stream
>= 3) ? num_components
[3] : 0);
790 si_pm4_set_reg(pm4
, R_028B90_VGT_GS_INSTANCE_CNT
,
791 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
792 S_028B90_ENABLE(gs_num_invocations
> 0));
794 va
= shader
->bo
->gpu_address
;
795 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
797 if (sscreen
->info
.chip_class
>= GFX9
) {
798 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
799 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
800 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
801 struct gfx9_gs_info gs_info
;
803 if (es_type
== PIPE_SHADER_VERTEX
)
804 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
805 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
806 else if (es_type
== PIPE_SHADER_TESS_EVAL
)
807 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
809 unreachable("invalid shader selector type");
811 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
812 * VGPR[0:4] are always loaded.
814 if (sel
->info
.uses_invocationid
)
815 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
816 else if (sel
->info
.uses_primid
)
817 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
818 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
819 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
821 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
823 unsigned num_user_sgprs
;
824 if (es_type
== PIPE_SHADER_VERTEX
)
825 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
827 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
829 gfx9_get_gs_info(shader
->key
.part
.gs
.es
, sel
, &gs_info
);
831 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
832 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, S_00B214_MEM_BASE(va
>> 40));
834 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
835 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
836 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
837 S_00B228_DX10_CLAMP(1) |
838 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
839 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
840 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
841 S_00B22C_USER_SGPR(num_user_sgprs
) |
842 S_00B22C_USER_SGPR_MSB(num_user_sgprs
>> 5) |
843 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
844 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
845 S_00B22C_LDS_SIZE(gs_info
.lds_size
) |
846 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
848 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
849 S_028A44_ES_VERTS_PER_SUBGRP(gs_info
.es_verts_per_subgroup
) |
850 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info
.gs_prims_per_subgroup
) |
851 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info
.gs_inst_prims_in_subgroup
));
852 si_pm4_set_reg(pm4
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
853 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info
.max_prims_per_subgroup
));
854 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
855 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4);
857 if (es_type
== PIPE_SHADER_TESS_EVAL
)
858 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
860 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
863 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
864 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, S_00B224_MEM_BASE(va
>> 40));
866 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
867 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
868 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
869 S_00B228_DX10_CLAMP(1) |
870 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
871 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
872 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
873 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
878 * Compute the state for \p shader, which will run as a vertex shader on the
881 * If \p gs is non-NULL, it points to the geometry shader for which this shader
882 * is the copy shader.
884 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
885 struct si_shader_selector
*gs
)
887 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
888 struct si_pm4_state
*pm4
;
889 unsigned num_user_sgprs
;
890 unsigned nparams
, vgpr_comp_cnt
;
893 unsigned window_space
=
894 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
895 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
897 pm4
= si_get_shader_pm4_state(shader
);
901 /* We always write VGT_GS_MODE in the VS state, because every switch
902 * between different shader pipelines involving a different GS or no
903 * GS at all involves a switch of the VS (different GS use different
904 * copy shaders). On the other hand, when the API switches from a GS to
905 * no GS and then back to the same GS used originally, the GS state is
909 unsigned mode
= V_028A40_GS_OFF
;
911 /* PrimID needs GS scenario A. */
913 mode
= V_028A40_GS_SCENARIO_A
;
915 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, S_028A40_MODE(mode
));
916 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, enable_prim_id
);
918 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
,
919 ac_vgt_gs_mode(gs
->gs_max_out_vertices
,
920 sscreen
->info
.chip_class
));
921 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
924 if (sscreen
->info
.chip_class
<= VI
) {
925 /* Reuse needs to be set off if we write oViewport. */
926 si_pm4_set_reg(pm4
, R_028AB4_VGT_REUSE_OFF
,
927 S_028AB4_REUSE_OFF(info
->writes_viewport_index
));
930 va
= shader
->bo
->gpu_address
;
931 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
934 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
935 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
936 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
937 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
938 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
939 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
941 vgpr_comp_cnt
= enable_prim_id
? 2 : (shader
->info
.uses_instanceid
? 1 : 0);
943 if (info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
]) {
944 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
945 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
947 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
949 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
950 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
951 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
953 unreachable("invalid shader selector type");
955 /* VS is required to export at least one param. */
956 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
957 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
958 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
960 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
961 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
962 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
963 V_02870C_SPI_SHADER_4COMP
:
964 V_02870C_SPI_SHADER_NONE
) |
965 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
966 V_02870C_SPI_SHADER_4COMP
:
967 V_02870C_SPI_SHADER_NONE
) |
968 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
969 V_02870C_SPI_SHADER_4COMP
:
970 V_02870C_SPI_SHADER_NONE
));
972 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
974 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
975 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, S_00B124_MEM_BASE(va
>> 40));
976 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
977 S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
978 S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
979 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
980 S_00B128_DX10_CLAMP(1) |
981 S_00B128_FLOAT_MODE(shader
->config
.float_mode
));
982 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
983 S_00B12C_USER_SGPR(num_user_sgprs
) |
984 S_00B12C_OC_LDS_EN(oc_lds_en
) |
985 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
986 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
987 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
988 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
989 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
) |
990 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
992 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
993 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
995 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
996 S_028818_VTX_W0_FMT(1) |
997 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
998 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
999 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
1001 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1002 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
1004 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
1007 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
1009 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
1010 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
1011 !!(info
->colors_read
& 0xf0);
1012 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
1013 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
1015 assert(num_interp
<= 32);
1016 return MIN2(num_interp
, 32);
1019 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
1021 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
1022 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
1024 /* If the i-th target format is set, all previous target formats must
1025 * be non-zero to avoid hangs.
1027 for (i
= 0; i
< num_targets
; i
++)
1028 if (!(value
& (0xf << (i
* 4))))
1029 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
1034 static void si_shader_ps(struct si_shader
*shader
)
1036 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1037 struct si_pm4_state
*pm4
;
1038 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1039 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1041 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1043 /* we need to enable at least one of them, otherwise we hang the GPU */
1044 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1045 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1046 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1047 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1048 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1049 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1050 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1051 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1052 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1053 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
1054 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1055 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1056 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1057 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1059 /* Validate interpolation optimization flags (read as implications). */
1060 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1061 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1062 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1063 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1064 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1065 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1066 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1067 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1068 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1069 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1070 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1071 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1072 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1073 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1074 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1075 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1076 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1077 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1079 /* Validate cases when the optimizations are off (read as implications). */
1080 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1081 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1082 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1083 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1084 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1085 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1087 pm4
= si_get_shader_pm4_state(shader
);
1091 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1093 * 0 -> Position = pixel center
1094 * 1 -> Position = pixel centroid
1095 * 2 -> Position = at sample position
1097 * From GLSL 4.5 specification, section 7.1:
1098 * "The variable gl_FragCoord is available as an input variable from
1099 * within fragment shaders and it holds the window relative coordinates
1100 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1101 * value can be for any location within the pixel, or one of the
1102 * fragment samples. The use of centroid does not further restrict
1103 * this value to be inside the current primitive."
1105 * Meaning that centroid has no effect and we can return anything within
1106 * the pixel. Thus, return the value at sample position, because that's
1107 * the most accurate one shaders can get.
1109 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1111 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1112 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1113 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1115 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1116 cb_shader_mask
= ac_get_cb_shader_mask(spi_shader_col_format
);
1118 /* Ensure that some export memory is always allocated, for two reasons:
1120 * 1) Correctness: The hardware ignores the EXEC mask if no export
1121 * memory is allocated, so KILL and alpha test do not work correctly
1123 * 2) Performance: Every shader needs at least a NULL export, even when
1124 * it writes no color/depth output. The NULL export instruction
1125 * stalls without this setting.
1127 * Don't add this to CB_SHADER_MASK.
1129 if (!spi_shader_col_format
&&
1130 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1131 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1133 si_pm4_set_reg(pm4
, R_0286CC_SPI_PS_INPUT_ENA
, input_ena
);
1134 si_pm4_set_reg(pm4
, R_0286D0_SPI_PS_INPUT_ADDR
,
1135 shader
->config
.spi_ps_input_addr
);
1137 /* Set interpolation controls. */
1138 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
));
1140 /* Set registers. */
1141 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
1142 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
1144 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
,
1145 ac_get_spi_shader_z_format(info
->writes_z
,
1146 info
->writes_stencil
,
1147 info
->writes_samplemask
));
1149 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
, spi_shader_col_format
);
1150 si_pm4_set_reg(pm4
, R_02823C_CB_SHADER_MASK
, cb_shader_mask
);
1152 va
= shader
->bo
->gpu_address
;
1153 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1154 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1155 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, S_00B024_MEM_BASE(va
>> 40));
1157 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
1158 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1159 S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
1160 S_00B028_DX10_CLAMP(1) |
1161 S_00B028_FLOAT_MODE(shader
->config
.float_mode
));
1162 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1163 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1164 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1165 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1168 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1169 struct si_shader
*shader
)
1171 switch (shader
->selector
->type
) {
1172 case PIPE_SHADER_VERTEX
:
1173 if (shader
->key
.as_ls
)
1174 si_shader_ls(sscreen
, shader
);
1175 else if (shader
->key
.as_es
)
1176 si_shader_es(sscreen
, shader
);
1178 si_shader_vs(sscreen
, shader
, NULL
);
1180 case PIPE_SHADER_TESS_CTRL
:
1181 si_shader_hs(sscreen
, shader
);
1183 case PIPE_SHADER_TESS_EVAL
:
1184 if (shader
->key
.as_es
)
1185 si_shader_es(sscreen
, shader
);
1187 si_shader_vs(sscreen
, shader
, NULL
);
1189 case PIPE_SHADER_GEOMETRY
:
1190 si_shader_gs(sscreen
, shader
);
1192 case PIPE_SHADER_FRAGMENT
:
1193 si_shader_ps(shader
);
1200 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1202 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1203 if (sctx
->queued
.named
.dsa
)
1204 return sctx
->queued
.named
.dsa
->alpha_func
;
1206 return PIPE_FUNC_ALWAYS
;
1209 static void si_shader_selector_key_vs(struct si_context
*sctx
,
1210 struct si_shader_selector
*vs
,
1211 struct si_shader_key
*key
,
1212 struct si_vs_prolog_bits
*prolog_key
)
1214 if (!sctx
->vertex_elements
||
1215 vs
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
])
1218 prolog_key
->instance_divisor_is_one
=
1219 sctx
->vertex_elements
->instance_divisor_is_one
;
1220 prolog_key
->instance_divisor_is_fetched
=
1221 sctx
->vertex_elements
->instance_divisor_is_fetched
;
1223 /* Prefer a monolithic shader to allow scheduling divisions around
1225 if (prolog_key
->instance_divisor_is_fetched
)
1226 key
->opt
.prefer_mono
= 1;
1228 unsigned count
= MIN2(vs
->info
.num_inputs
,
1229 sctx
->vertex_elements
->count
);
1230 memcpy(key
->mono
.vs_fix_fetch
, sctx
->vertex_elements
->fix_fetch
, count
);
1233 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1234 struct si_shader_selector
*vs
,
1235 struct si_shader_key
*key
)
1237 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1239 key
->opt
.clip_disable
=
1240 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1241 (vs
->info
.clipdist_writemask
||
1242 vs
->info
.writes_clipvertex
) &&
1243 !vs
->info
.culldist_writemask
;
1245 /* Find out if PS is disabled. */
1246 bool ps_disabled
= true;
1248 const struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1249 bool alpha_to_coverage
= blend
&& blend
->alpha_to_coverage
;
1250 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1251 ps
->info
.writes_z
||
1252 ps
->info
.writes_stencil
||
1253 ps
->info
.writes_samplemask
||
1254 alpha_to_coverage
||
1255 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1256 unsigned ps_colormask
= si_get_total_colormask(sctx
);
1258 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1261 !ps
->info
.writes_memory
);
1264 /* Find out which VS outputs aren't used by the PS. */
1265 uint64_t outputs_written
= vs
->outputs_written_before_ps
;
1266 uint64_t inputs_read
= 0;
1268 /* Ignore outputs that are not passed from VS to PS. */
1269 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION
, 0, true)) |
1270 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE
, 0, true)) |
1271 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX
, 0, true)));
1274 inputs_read
= ps
->inputs_read
;
1277 uint64_t linked
= outputs_written
& inputs_read
;
1279 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1282 /* Compute the key for the hw shader variant */
1283 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1284 struct si_shader_selector
*sel
,
1285 struct si_shader_key
*key
)
1287 struct si_context
*sctx
= (struct si_context
*)ctx
;
1289 memset(key
, 0, sizeof(*key
));
1291 switch (sel
->type
) {
1292 case PIPE_SHADER_VERTEX
:
1293 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1295 if (sctx
->tes_shader
.cso
)
1297 else if (sctx
->gs_shader
.cso
)
1300 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1302 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1303 key
->mono
.u
.vs_export_prim_id
= 1;
1306 case PIPE_SHADER_TESS_CTRL
:
1307 if (sctx
->chip_class
>= GFX9
) {
1308 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1309 key
, &key
->part
.tcs
.ls_prolog
);
1310 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1312 /* When the LS VGPR fix is needed, monolithic shaders
1314 * - avoid initializing EXEC in both the LS prolog
1315 * and the LS main part when !vs_needs_prolog
1316 * - remove the fixup for unused input VGPRs
1318 key
->part
.tcs
.ls_prolog
.ls_vgpr_fix
= sctx
->ls_vgpr_fix
;
1320 /* The LS output / HS input layout can be communicated
1321 * directly instead of via user SGPRs for merged LS-HS.
1322 * The LS VGPR fix prefers this too.
1324 key
->opt
.prefer_mono
= 1;
1327 key
->part
.tcs
.epilog
.prim_mode
=
1328 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1329 key
->part
.tcs
.epilog
.invoc0_tess_factors_are_def
=
1330 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1331 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1332 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1334 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1335 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1337 case PIPE_SHADER_TESS_EVAL
:
1338 if (sctx
->gs_shader
.cso
)
1341 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1343 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1344 key
->mono
.u
.vs_export_prim_id
= 1;
1347 case PIPE_SHADER_GEOMETRY
:
1348 if (sctx
->chip_class
>= GFX9
) {
1349 if (sctx
->tes_shader
.cso
) {
1350 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1352 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1353 key
, &key
->part
.gs
.vs_prolog
);
1354 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1355 key
->part
.gs
.prolog
.gfx9_prev_is_vs
= 1;
1358 /* Merged ES-GS can have unbalanced wave usage.
1360 * ES threads are per-vertex, while GS threads are
1361 * per-primitive. So without any amplification, there
1362 * are fewer GS threads than ES threads, which can result
1363 * in empty (no-op) GS waves. With too much amplification,
1364 * there are more GS threads than ES threads, which
1365 * can result in empty (no-op) ES waves.
1367 * Non-monolithic shaders are implemented by setting EXEC
1368 * at the beginning of shader parts, and don't jump to
1369 * the end if EXEC is 0.
1371 * Monolithic shaders use conditional blocks, so they can
1372 * jump and skip empty waves of ES or GS. So set this to
1373 * always use optimized variants, which are monolithic.
1375 key
->opt
.prefer_mono
= 1;
1377 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1379 case PIPE_SHADER_FRAGMENT
: {
1380 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1381 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1383 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1384 sel
->info
.colors_written
== 0x1)
1385 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1388 /* Select the shader color format based on whether
1389 * blending or alpha are needed.
1391 key
->part
.ps
.epilog
.spi_shader_col_format
=
1392 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1393 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1394 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1395 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1396 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1397 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1398 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1399 sctx
->framebuffer
.spi_shader_col_format
);
1400 key
->part
.ps
.epilog
.spi_shader_col_format
&= blend
->cb_target_enabled_4bit
;
1402 /* The output for dual source blending should have
1403 * the same format as the first output.
1405 if (blend
->dual_src_blend
)
1406 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1407 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1409 key
->part
.ps
.epilog
.spi_shader_col_format
= sctx
->framebuffer
.spi_shader_col_format
;
1411 /* If alpha-to-coverage is enabled, we have to export alpha
1412 * even if there is no color buffer.
1414 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1415 blend
&& blend
->alpha_to_coverage
)
1416 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1418 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1419 * to the range supported by the type if a channel has less
1420 * than 16 bits and the export format is 16_ABGR.
1422 if (sctx
->chip_class
<= CIK
&& sctx
->family
!= CHIP_HAWAII
) {
1423 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1424 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1427 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1428 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1429 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1430 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1431 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1434 bool is_poly
= !util_prim_is_points_or_lines(sctx
->current_rast_prim
);
1435 bool is_line
= util_prim_is_lines(sctx
->current_rast_prim
);
1437 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1438 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1440 if (sctx
->queued
.named
.blend
) {
1441 key
->part
.ps
.epilog
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
1442 rs
->multisample_enable
;
1445 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1446 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1447 (is_line
&& rs
->line_smooth
)) &&
1448 sctx
->framebuffer
.nr_samples
<= 1;
1449 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1451 if (sctx
->ps_iter_samples
> 1 &&
1452 sel
->info
.reads_samplemask
) {
1453 key
->part
.ps
.prolog
.samplemask_log_ps_iter
=
1454 util_logbase2(sctx
->ps_iter_samples
);
1457 if (rs
->force_persample_interp
&&
1458 rs
->multisample_enable
&&
1459 sctx
->framebuffer
.nr_samples
> 1 &&
1460 sctx
->ps_iter_samples
> 1) {
1461 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1462 sel
->info
.uses_persp_center
||
1463 sel
->info
.uses_persp_centroid
;
1465 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1466 sel
->info
.uses_linear_center
||
1467 sel
->info
.uses_linear_centroid
;
1468 } else if (rs
->multisample_enable
&&
1469 sctx
->framebuffer
.nr_samples
> 1) {
1470 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
1471 sel
->info
.uses_persp_center
&&
1472 sel
->info
.uses_persp_centroid
;
1473 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
1474 sel
->info
.uses_linear_center
&&
1475 sel
->info
.uses_linear_centroid
;
1477 /* Make sure SPI doesn't compute more than 1 pair
1478 * of (i,j), which is the optimization here. */
1479 key
->part
.ps
.prolog
.force_persp_center_interp
=
1480 sel
->info
.uses_persp_center
+
1481 sel
->info
.uses_persp_centroid
+
1482 sel
->info
.uses_persp_sample
> 1;
1484 key
->part
.ps
.prolog
.force_linear_center_interp
=
1485 sel
->info
.uses_linear_center
+
1486 sel
->info
.uses_linear_centroid
+
1487 sel
->info
.uses_linear_sample
> 1;
1489 if (sel
->info
.opcode_count
[TGSI_OPCODE_INTERP_SAMPLE
])
1490 key
->mono
.u
.ps
.interpolate_at_sample_force_center
= 1;
1493 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
1495 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1496 if (sctx
->ps_uses_fbfetch
) {
1497 struct pipe_surface
*cb0
= sctx
->framebuffer
.state
.cbufs
[0];
1498 struct pipe_resource
*tex
= cb0
->texture
;
1500 /* 1D textures are allocated and used as 2D on GFX9. */
1501 key
->mono
.u
.ps
.fbfetch_msaa
= sctx
->framebuffer
.nr_samples
> 1;
1502 key
->mono
.u
.ps
.fbfetch_is_1D
= sctx
->chip_class
!= GFX9
&&
1503 (tex
->target
== PIPE_TEXTURE_1D
||
1504 tex
->target
== PIPE_TEXTURE_1D_ARRAY
);
1505 key
->mono
.u
.ps
.fbfetch_layered
= tex
->target
== PIPE_TEXTURE_1D_ARRAY
||
1506 tex
->target
== PIPE_TEXTURE_2D_ARRAY
||
1507 tex
->target
== PIPE_TEXTURE_CUBE
||
1508 tex
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
1509 tex
->target
== PIPE_TEXTURE_3D
;
1517 if (unlikely(sctx
->screen
->debug_flags
& DBG(NO_OPT_VARIANT
)))
1518 memset(&key
->opt
, 0, sizeof(key
->opt
));
1521 static void si_build_shader_variant(struct si_shader
*shader
,
1525 struct si_shader_selector
*sel
= shader
->selector
;
1526 struct si_screen
*sscreen
= sel
->screen
;
1527 struct ac_llvm_compiler
*compiler
;
1528 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
1531 if (thread_index
>= 0) {
1533 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler_lowp
));
1534 compiler
= &sscreen
->compiler_lowp
[thread_index
];
1536 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
1537 compiler
= &sscreen
->compiler
[thread_index
];
1542 assert(!low_priority
);
1543 compiler
= shader
->compiler_ctx_state
.compiler
;
1546 r
= si_shader_create(sscreen
, compiler
, shader
, debug
);
1548 PRINT_ERR("Failed to build shader variant (type=%u) %d\n",
1550 shader
->compilation_failed
= true;
1554 if (shader
->compiler_ctx_state
.is_debug_context
) {
1555 FILE *f
= open_memstream(&shader
->shader_log
,
1556 &shader
->shader_log_size
);
1558 si_shader_dump(sscreen
, shader
, NULL
, sel
->type
, f
, false);
1563 si_shader_init_pm4_state(sscreen
, shader
);
1566 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
1568 struct si_shader
*shader
= (struct si_shader
*)job
;
1570 assert(thread_index
>= 0);
1572 si_build_shader_variant(shader
, thread_index
, true);
1575 static const struct si_shader_key zeroed
;
1577 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
1578 struct si_shader_selector
*sel
,
1579 struct si_compiler_ctx_state
*compiler_state
,
1580 struct si_shader_key
*key
)
1582 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
1585 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
1590 /* We can leave the fence as permanently signaled because the
1591 * main part becomes visible globally only after it has been
1593 util_queue_fence_init(&main_part
->ready
);
1595 main_part
->selector
= sel
;
1596 main_part
->key
.as_es
= key
->as_es
;
1597 main_part
->key
.as_ls
= key
->as_ls
;
1598 main_part
->is_monolithic
= false;
1600 if (si_compile_tgsi_shader(sscreen
, compiler_state
->compiler
,
1601 main_part
, &compiler_state
->debug
) != 0) {
1610 /* Select the hw shader variant depending on the current state. */
1611 static int si_shader_select_with_key(struct si_screen
*sscreen
,
1612 struct si_shader_ctx_state
*state
,
1613 struct si_compiler_ctx_state
*compiler_state
,
1614 struct si_shader_key
*key
,
1617 struct si_shader_selector
*sel
= state
->cso
;
1618 struct si_shader_selector
*previous_stage_sel
= NULL
;
1619 struct si_shader
*current
= state
->current
;
1620 struct si_shader
*iter
, *shader
= NULL
;
1623 /* Check if we don't need to change anything.
1624 * This path is also used for most shaders that don't need multiple
1625 * variants, it will cost just a computation of the key and this
1627 if (likely(current
&&
1628 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0)) {
1629 if (unlikely(!util_queue_fence_is_signalled(¤t
->ready
))) {
1630 if (current
->is_optimized
) {
1631 memset(&key
->opt
, 0, sizeof(key
->opt
));
1632 goto current_not_ready
;
1635 util_queue_fence_wait(¤t
->ready
);
1638 return current
->compilation_failed
? -1 : 0;
1642 /* This must be done before the mutex is locked, because async GS
1643 * compilation calls this function too, and therefore must enter
1646 * Only wait if we are in a draw call. Don't wait if we are
1647 * in a compiler thread.
1649 if (thread_index
< 0)
1650 util_queue_fence_wait(&sel
->ready
);
1652 mtx_lock(&sel
->mutex
);
1654 /* Find the shader variant. */
1655 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
1656 /* Don't check the "current" shader. We checked it above. */
1657 if (current
!= iter
&&
1658 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
1659 mtx_unlock(&sel
->mutex
);
1661 if (unlikely(!util_queue_fence_is_signalled(&iter
->ready
))) {
1662 /* If it's an optimized shader and its compilation has
1663 * been started but isn't done, use the unoptimized
1664 * shader so as not to cause a stall due to compilation.
1666 if (iter
->is_optimized
) {
1667 memset(&key
->opt
, 0, sizeof(key
->opt
));
1671 util_queue_fence_wait(&iter
->ready
);
1674 if (iter
->compilation_failed
) {
1675 return -1; /* skip the draw call */
1678 state
->current
= iter
;
1683 /* Build a new shader. */
1684 shader
= CALLOC_STRUCT(si_shader
);
1686 mtx_unlock(&sel
->mutex
);
1690 util_queue_fence_init(&shader
->ready
);
1692 shader
->selector
= sel
;
1694 shader
->compiler_ctx_state
= *compiler_state
;
1696 /* If this is a merged shader, get the first shader's selector. */
1697 if (sscreen
->info
.chip_class
>= GFX9
) {
1698 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1699 previous_stage_sel
= key
->part
.tcs
.ls
;
1700 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1701 previous_stage_sel
= key
->part
.gs
.es
;
1703 /* We need to wait for the previous shader. */
1704 if (previous_stage_sel
&& thread_index
< 0)
1705 util_queue_fence_wait(&previous_stage_sel
->ready
);
1708 /* Compile the main shader part if it doesn't exist. This can happen
1709 * if the initial guess was wrong. */
1710 bool is_pure_monolithic
=
1711 sscreen
->use_monolithic_shaders
||
1712 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
1714 if (!is_pure_monolithic
) {
1717 /* Make sure the main shader part is present. This is needed
1718 * for shaders that can be compiled as VS, LS, or ES, and only
1719 * one of them is compiled at creation.
1721 * For merged shaders, check that the starting shader's main
1724 if (previous_stage_sel
) {
1725 struct si_shader_key shader1_key
= zeroed
;
1727 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1728 shader1_key
.as_ls
= 1;
1729 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1730 shader1_key
.as_es
= 1;
1734 mtx_lock(&previous_stage_sel
->mutex
);
1735 ok
= si_check_missing_main_part(sscreen
,
1737 compiler_state
, &shader1_key
);
1738 mtx_unlock(&previous_stage_sel
->mutex
);
1740 ok
= si_check_missing_main_part(sscreen
, sel
,
1741 compiler_state
, key
);
1745 mtx_unlock(&sel
->mutex
);
1746 return -ENOMEM
; /* skip the draw call */
1750 /* Keep the reference to the 1st shader of merged shaders, so that
1751 * Gallium can't destroy it before we destroy the 2nd shader.
1753 * Set sctx = NULL, because it's unused if we're not releasing
1754 * the shader, and we don't have any sctx here.
1756 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
1757 previous_stage_sel
);
1759 /* Monolithic-only shaders don't make a distinction between optimized
1760 * and unoptimized. */
1761 shader
->is_monolithic
=
1762 is_pure_monolithic
||
1763 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1765 shader
->is_optimized
=
1766 !is_pure_monolithic
&&
1767 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1769 /* If it's an optimized shader, compile it asynchronously. */
1770 if (shader
->is_optimized
&&
1771 !is_pure_monolithic
&&
1773 /* Compile it asynchronously. */
1774 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
,
1775 shader
, &shader
->ready
,
1776 si_build_shader_variant_low_priority
, NULL
);
1778 /* Add only after the ready fence was reset, to guard against a
1779 * race with si_bind_XX_shader. */
1780 if (!sel
->last_variant
) {
1781 sel
->first_variant
= shader
;
1782 sel
->last_variant
= shader
;
1784 sel
->last_variant
->next_variant
= shader
;
1785 sel
->last_variant
= shader
;
1788 /* Use the default (unoptimized) shader for now. */
1789 memset(&key
->opt
, 0, sizeof(key
->opt
));
1790 mtx_unlock(&sel
->mutex
);
1794 /* Reset the fence before adding to the variant list. */
1795 util_queue_fence_reset(&shader
->ready
);
1797 if (!sel
->last_variant
) {
1798 sel
->first_variant
= shader
;
1799 sel
->last_variant
= shader
;
1801 sel
->last_variant
->next_variant
= shader
;
1802 sel
->last_variant
= shader
;
1805 mtx_unlock(&sel
->mutex
);
1807 assert(!shader
->is_optimized
);
1808 si_build_shader_variant(shader
, thread_index
, false);
1810 util_queue_fence_signal(&shader
->ready
);
1812 if (!shader
->compilation_failed
)
1813 state
->current
= shader
;
1815 return shader
->compilation_failed
? -1 : 0;
1818 static int si_shader_select(struct pipe_context
*ctx
,
1819 struct si_shader_ctx_state
*state
,
1820 struct si_compiler_ctx_state
*compiler_state
)
1822 struct si_context
*sctx
= (struct si_context
*)ctx
;
1823 struct si_shader_key key
;
1825 si_shader_selector_key(ctx
, state
->cso
, &key
);
1826 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
1830 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
1832 struct si_shader_key
*key
)
1834 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
1836 switch (info
->processor
) {
1837 case PIPE_SHADER_VERTEX
:
1838 switch (next_shader
) {
1839 case PIPE_SHADER_GEOMETRY
:
1842 case PIPE_SHADER_TESS_CTRL
:
1843 case PIPE_SHADER_TESS_EVAL
:
1847 /* If POSITION isn't written, it can only be a HW VS
1848 * if streamout is used. If streamout isn't used,
1849 * assume that it's a HW LS. (the next shader is TCS)
1850 * This heuristic is needed for separate shader objects.
1852 if (!info
->writes_position
&& !streamout
)
1857 case PIPE_SHADER_TESS_EVAL
:
1858 if (next_shader
== PIPE_SHADER_GEOMETRY
||
1859 !info
->writes_position
)
1866 * Compile the main shader part or the monolithic shader as part of
1867 * si_shader_selector initialization. Since it can be done asynchronously,
1868 * there is no way to report compile failures to applications.
1870 static void si_init_shader_selector_async(void *job
, int thread_index
)
1872 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
1873 struct si_screen
*sscreen
= sel
->screen
;
1874 struct ac_llvm_compiler
*compiler
;
1875 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
1877 assert(!debug
->debug_message
|| debug
->async
);
1878 assert(thread_index
>= 0);
1879 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
1880 compiler
= &sscreen
->compiler
[thread_index
];
1882 /* Compile the main shader part for use with a prolog and/or epilog.
1883 * If this fails, the driver will try to compile a monolithic shader
1886 if (!sscreen
->use_monolithic_shaders
) {
1887 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
1888 void *ir_binary
= NULL
;
1891 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
1895 /* We can leave the fence signaled because use of the default
1896 * main part is guarded by the selector's ready fence. */
1897 util_queue_fence_init(&shader
->ready
);
1899 shader
->selector
= sel
;
1900 shader
->is_monolithic
= false;
1901 si_parse_next_shader_property(&sel
->info
,
1902 sel
->so
.num_outputs
!= 0,
1905 if (sel
->tokens
|| sel
->nir
)
1906 ir_binary
= si_get_ir_binary(sel
);
1908 /* Try to load the shader from the shader cache. */
1909 mtx_lock(&sscreen
->shader_cache_mutex
);
1912 si_shader_cache_load_shader(sscreen
, ir_binary
, shader
)) {
1913 mtx_unlock(&sscreen
->shader_cache_mutex
);
1914 si_shader_dump_stats_for_shader_db(shader
, debug
);
1916 mtx_unlock(&sscreen
->shader_cache_mutex
);
1918 /* Compile the shader if it hasn't been loaded from the cache. */
1919 if (si_compile_tgsi_shader(sscreen
, compiler
, shader
,
1923 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
1928 mtx_lock(&sscreen
->shader_cache_mutex
);
1929 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
, shader
, true))
1931 mtx_unlock(&sscreen
->shader_cache_mutex
);
1935 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
1937 /* Unset "outputs_written" flags for outputs converted to
1938 * DEFAULT_VAL, so that later inter-shader optimizations don't
1939 * try to eliminate outputs that don't exist in the final
1942 * This is only done if non-monolithic shaders are enabled.
1944 if ((sel
->type
== PIPE_SHADER_VERTEX
||
1945 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
1946 !shader
->key
.as_ls
&&
1947 !shader
->key
.as_es
) {
1950 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
1951 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
1953 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
1956 unsigned name
= sel
->info
.output_semantic_name
[i
];
1957 unsigned index
= sel
->info
.output_semantic_index
[i
];
1961 case TGSI_SEMANTIC_GENERIC
:
1962 /* don't process indices the function can't handle */
1963 if (index
>= SI_MAX_IO_GENERIC
)
1967 id
= si_shader_io_get_unique_index(name
, index
, true);
1968 sel
->outputs_written_before_ps
&= ~(1ull << id
);
1970 case TGSI_SEMANTIC_POSITION
: /* ignore these */
1971 case TGSI_SEMANTIC_PSIZE
:
1972 case TGSI_SEMANTIC_CLIPVERTEX
:
1973 case TGSI_SEMANTIC_EDGEFLAG
:
1980 /* The GS copy shader is always pre-compiled. */
1981 if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
1982 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, compiler
, sel
, debug
);
1983 if (!sel
->gs_copy_shader
) {
1984 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
1988 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
1992 void si_schedule_initial_compile(struct si_context
*sctx
, unsigned processor
,
1993 struct util_queue_fence
*ready_fence
,
1994 struct si_compiler_ctx_state
*compiler_ctx_state
,
1995 void *job
, util_queue_execute_func execute
)
1997 util_queue_fence_init(ready_fence
);
1999 struct util_async_debug_callback async_debug
;
2001 (sctx
->debug
.debug_message
&& !sctx
->debug
.async
) ||
2003 si_can_dump_shader(sctx
->screen
, processor
);
2006 u_async_debug_init(&async_debug
);
2007 compiler_ctx_state
->debug
= async_debug
.base
;
2010 util_queue_add_job(&sctx
->screen
->shader_compiler_queue
, job
,
2011 ready_fence
, execute
, NULL
);
2014 util_queue_fence_wait(ready_fence
);
2015 u_async_debug_drain(&async_debug
, &sctx
->debug
);
2016 u_async_debug_cleanup(&async_debug
);
2020 /* Return descriptor slot usage masks from the given shader info. */
2021 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
2022 uint32_t *const_and_shader_buffers
,
2023 uint64_t *samplers_and_images
)
2025 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_samplers
;
2027 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
2028 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
2029 /* two 8-byte images share one 16-byte slot */
2030 num_images
= align(util_last_bit(info
->images_declared
), 2);
2031 num_samplers
= util_last_bit(info
->samplers_declared
);
2033 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2034 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
2035 *const_and_shader_buffers
=
2036 u_bit_consecutive(start
, num_shaderbufs
+ num_constbufs
);
2038 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2039 start
= si_get_image_slot(num_images
- 1) / 2;
2040 *samplers_and_images
=
2041 u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
2044 static void *si_create_shader_selector(struct pipe_context
*ctx
,
2045 const struct pipe_shader_state
*state
)
2047 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
2048 struct si_context
*sctx
= (struct si_context
*)ctx
;
2049 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
2055 pipe_reference_init(&sel
->reference
, 1);
2056 sel
->screen
= sscreen
;
2057 sel
->compiler_ctx_state
.debug
= sctx
->debug
;
2058 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
2060 sel
->so
= state
->stream_output
;
2062 if (state
->type
== PIPE_SHADER_IR_TGSI
) {
2063 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
2069 tgsi_scan_shader(state
->tokens
, &sel
->info
);
2070 tgsi_scan_tess_ctrl(state
->tokens
, &sel
->info
, &sel
->tcs_info
);
2072 assert(state
->type
== PIPE_SHADER_IR_NIR
);
2074 sel
->nir
= state
->ir
.nir
;
2076 si_nir_scan_shader(sel
->nir
, &sel
->info
);
2077 si_nir_scan_tess_ctrl(sel
->nir
, &sel
->info
, &sel
->tcs_info
);
2082 sel
->type
= sel
->info
.processor
;
2083 p_atomic_inc(&sscreen
->num_shaders_created
);
2084 si_get_active_slot_masks(&sel
->info
,
2085 &sel
->active_const_and_shader_buffers
,
2086 &sel
->active_samplers_and_images
);
2088 /* Record which streamout buffers are enabled. */
2089 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
2090 sel
->enabled_streamout_buffer_mask
|=
2091 (1 << sel
->so
.output
[i
].output_buffer
) <<
2092 (sel
->so
.output
[i
].stream
* 4);
2095 /* The prolog is a no-op if there are no inputs. */
2096 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
2097 sel
->info
.num_inputs
&&
2098 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
2100 sel
->force_correct_derivs_after_kill
=
2101 sel
->type
== PIPE_SHADER_FRAGMENT
&&
2102 sel
->info
.uses_derivatives
&&
2103 sel
->info
.uses_kill
&&
2104 sctx
->screen
->debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
2106 /* Set which opcode uses which (i,j) pair. */
2107 if (sel
->info
.uses_persp_opcode_interp_centroid
)
2108 sel
->info
.uses_persp_centroid
= true;
2110 if (sel
->info
.uses_linear_opcode_interp_centroid
)
2111 sel
->info
.uses_linear_centroid
= true;
2113 if (sel
->info
.uses_persp_opcode_interp_offset
||
2114 sel
->info
.uses_persp_opcode_interp_sample
)
2115 sel
->info
.uses_persp_center
= true;
2117 if (sel
->info
.uses_linear_opcode_interp_offset
||
2118 sel
->info
.uses_linear_opcode_interp_sample
)
2119 sel
->info
.uses_linear_center
= true;
2121 switch (sel
->type
) {
2122 case PIPE_SHADER_GEOMETRY
:
2123 sel
->gs_output_prim
=
2124 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
2125 sel
->gs_max_out_vertices
=
2126 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
2127 sel
->gs_num_invocations
=
2128 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2129 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2130 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
2131 sel
->gs_max_out_vertices
;
2133 sel
->max_gs_stream
= 0;
2134 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2135 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
2136 sel
->so
.output
[i
].stream
);
2138 sel
->gs_input_verts_per_prim
=
2139 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2142 case PIPE_SHADER_TESS_CTRL
:
2143 /* Always reserve space for these. */
2144 sel
->patch_outputs_written
|=
2145 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0)) |
2146 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0));
2148 case PIPE_SHADER_VERTEX
:
2149 case PIPE_SHADER_TESS_EVAL
:
2150 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2151 unsigned name
= sel
->info
.output_semantic_name
[i
];
2152 unsigned index
= sel
->info
.output_semantic_index
[i
];
2155 case TGSI_SEMANTIC_TESSINNER
:
2156 case TGSI_SEMANTIC_TESSOUTER
:
2157 case TGSI_SEMANTIC_PATCH
:
2158 sel
->patch_outputs_written
|=
2159 1ull << si_shader_io_get_unique_index_patch(name
, index
);
2162 case TGSI_SEMANTIC_GENERIC
:
2163 /* don't process indices the function can't handle */
2164 if (index
>= SI_MAX_IO_GENERIC
)
2168 sel
->outputs_written
|=
2169 1ull << si_shader_io_get_unique_index(name
, index
, false);
2170 sel
->outputs_written_before_ps
|=
2171 1ull << si_shader_io_get_unique_index(name
, index
, true);
2173 case TGSI_SEMANTIC_EDGEFLAG
:
2177 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2178 sel
->lshs_vertex_stride
= sel
->esgs_itemsize
;
2180 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2181 * will start on a different bank. (except for the maximum 32*16).
2183 if (sel
->lshs_vertex_stride
< 32*16)
2184 sel
->lshs_vertex_stride
+= 4;
2186 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2187 * conflicts, i.e. each vertex will start at a different bank.
2189 if (sctx
->chip_class
>= GFX9
)
2190 sel
->esgs_itemsize
+= 4;
2192 assert(((sel
->esgs_itemsize
/ 4) & C_028AAC_ITEMSIZE
) == 0);
2195 case PIPE_SHADER_FRAGMENT
:
2196 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2197 unsigned name
= sel
->info
.input_semantic_name
[i
];
2198 unsigned index
= sel
->info
.input_semantic_index
[i
];
2201 case TGSI_SEMANTIC_GENERIC
:
2202 /* don't process indices the function can't handle */
2203 if (index
>= SI_MAX_IO_GENERIC
)
2208 1ull << si_shader_io_get_unique_index(name
, index
, true);
2210 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2215 for (i
= 0; i
< 8; i
++)
2216 if (sel
->info
.colors_written
& (1 << i
))
2217 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2219 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2220 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2221 int index
= sel
->info
.input_semantic_index
[i
];
2222 sel
->color_attr_index
[index
] = i
;
2228 /* PA_CL_VS_OUT_CNTL */
2230 sel
->info
.writes_psize
|| sel
->info
.writes_edgeflag
||
2231 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
2232 sel
->pa_cl_vs_out_cntl
=
2233 S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
2234 S_02881C_USE_VTX_EDGE_FLAG(sel
->info
.writes_edgeflag
) |
2235 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
2236 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
2237 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
2238 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
2239 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
?
2240 SIX_BITS
: sel
->info
.clipdist_writemask
;
2241 sel
->culldist_mask
= sel
->info
.culldist_writemask
<<
2242 sel
->info
.num_written_clipdistance
;
2244 /* DB_SHADER_CONTROL */
2245 sel
->db_shader_control
=
2246 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2247 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2248 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2249 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2251 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2252 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2253 sel
->db_shader_control
|=
2254 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2256 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2257 sel
->db_shader_control
|=
2258 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2262 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2264 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2265 * --|-----------|------------|------------|--------------------|-------------------|-------------
2266 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2267 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2268 * 2 | false | true | n/a | LateZ | 1 | 0
2269 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2270 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2272 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2273 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2275 * Don't use ReZ without profiling !!!
2277 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2280 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2282 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2283 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2284 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
2285 } else if (sel
->info
.writes_memory
) {
2287 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
2288 S_02880C_EXEC_ON_HIER_FAIL(1);
2291 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2294 (void) mtx_init(&sel
->mutex
, mtx_plain
);
2296 si_schedule_initial_compile(sctx
, sel
->info
.processor
, &sel
->ready
,
2297 &sel
->compiler_ctx_state
, sel
,
2298 si_init_shader_selector_async
);
2302 static void si_update_streamout_state(struct si_context
*sctx
)
2304 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
2306 if (!shader_with_so
)
2309 sctx
->streamout
.enabled_stream_buffers_mask
=
2310 shader_with_so
->enabled_streamout_buffer_mask
;
2311 sctx
->streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
2314 static void si_update_clip_regs(struct si_context
*sctx
,
2315 struct si_shader_selector
*old_hw_vs
,
2316 struct si_shader
*old_hw_vs_variant
,
2317 struct si_shader_selector
*next_hw_vs
,
2318 struct si_shader
*next_hw_vs_variant
)
2322 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
2323 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
2324 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
2325 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
2326 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
||
2327 !old_hw_vs_variant
||
2328 !next_hw_vs_variant
||
2329 old_hw_vs_variant
->key
.opt
.clip_disable
!=
2330 next_hw_vs_variant
->key
.opt
.clip_disable
))
2331 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
2334 static void si_update_common_shader_state(struct si_context
*sctx
)
2336 sctx
->uses_bindless_samplers
=
2337 si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
2338 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
2339 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
2340 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
2341 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
2342 sctx
->uses_bindless_images
=
2343 si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
2344 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
2345 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
2346 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
2347 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
2348 sctx
->do_update_shaders
= true;
2351 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2353 struct si_context
*sctx
= (struct si_context
*)ctx
;
2354 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2355 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2356 struct si_shader_selector
*sel
= state
;
2358 if (sctx
->vs_shader
.cso
== sel
)
2361 sctx
->vs_shader
.cso
= sel
;
2362 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2363 sctx
->num_vs_blit_sgprs
= sel
? sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
] : 0;
2365 si_update_common_shader_state(sctx
);
2366 si_update_vs_viewport_state(sctx
);
2367 si_set_active_descriptors_for_shader(sctx
, sel
);
2368 si_update_streamout_state(sctx
);
2369 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2370 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2373 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
2375 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
2376 (sctx
->tes_shader
.cso
&&
2377 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
2378 (sctx
->tcs_shader
.cso
&&
2379 sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
2380 (sctx
->gs_shader
.cso
&&
2381 sctx
->gs_shader
.cso
->info
.uses_primid
) ||
2382 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&&
2383 sctx
->ps_shader
.cso
->info
.uses_primid
);
2386 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
2388 struct si_context
*sctx
= (struct si_context
*)ctx
;
2389 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2390 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2391 struct si_shader_selector
*sel
= state
;
2392 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
2394 if (sctx
->gs_shader
.cso
== sel
)
2397 sctx
->gs_shader
.cso
= sel
;
2398 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2399 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
2401 si_update_common_shader_state(sctx
);
2402 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2404 if (enable_changed
) {
2405 si_shader_change_notify(sctx
);
2406 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2407 si_update_tess_uses_prim_id(sctx
);
2409 si_update_vs_viewport_state(sctx
);
2410 si_set_active_descriptors_for_shader(sctx
, sel
);
2411 si_update_streamout_state(sctx
);
2412 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2413 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2416 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
2418 struct si_context
*sctx
= (struct si_context
*)ctx
;
2419 struct si_shader_selector
*sel
= state
;
2420 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
2422 if (sctx
->tcs_shader
.cso
== sel
)
2425 sctx
->tcs_shader
.cso
= sel
;
2426 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2427 si_update_tess_uses_prim_id(sctx
);
2429 si_update_common_shader_state(sctx
);
2432 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
2434 si_set_active_descriptors_for_shader(sctx
, sel
);
2437 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
2439 struct si_context
*sctx
= (struct si_context
*)ctx
;
2440 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2441 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2442 struct si_shader_selector
*sel
= state
;
2443 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
2445 if (sctx
->tes_shader
.cso
== sel
)
2448 sctx
->tes_shader
.cso
= sel
;
2449 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
2450 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
2451 si_update_tess_uses_prim_id(sctx
);
2453 si_update_common_shader_state(sctx
);
2454 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2456 if (enable_changed
) {
2457 si_shader_change_notify(sctx
);
2458 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
2460 si_update_vs_viewport_state(sctx
);
2461 si_set_active_descriptors_for_shader(sctx
, sel
);
2462 si_update_streamout_state(sctx
);
2463 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2464 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2467 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
2469 struct si_context
*sctx
= (struct si_context
*)ctx
;
2470 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
2471 struct si_shader_selector
*sel
= state
;
2473 /* skip if supplied shader is one already in use */
2477 sctx
->ps_shader
.cso
= sel
;
2478 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
2480 si_update_common_shader_state(sctx
);
2482 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2483 si_update_tess_uses_prim_id(sctx
);
2486 old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
2487 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
2489 if (sctx
->screen
->has_out_of_order_rast
&&
2491 old_sel
->info
.writes_memory
!= sel
->info
.writes_memory
||
2492 old_sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] !=
2493 sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]))
2494 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2496 si_set_active_descriptors_for_shader(sctx
, sel
);
2497 si_update_ps_colorbuf0_slot(sctx
);
2500 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
2502 if (shader
->is_optimized
) {
2503 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
,
2507 util_queue_fence_destroy(&shader
->ready
);
2510 switch (shader
->selector
->type
) {
2511 case PIPE_SHADER_VERTEX
:
2512 if (shader
->key
.as_ls
) {
2513 assert(sctx
->chip_class
<= VI
);
2514 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
2515 } else if (shader
->key
.as_es
) {
2516 assert(sctx
->chip_class
<= VI
);
2517 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2519 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2522 case PIPE_SHADER_TESS_CTRL
:
2523 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
2525 case PIPE_SHADER_TESS_EVAL
:
2526 if (shader
->key
.as_es
) {
2527 assert(sctx
->chip_class
<= VI
);
2528 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2530 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2533 case PIPE_SHADER_GEOMETRY
:
2534 if (shader
->is_gs_copy_shader
)
2535 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2537 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
2539 case PIPE_SHADER_FRAGMENT
:
2540 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
2545 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
2546 si_shader_destroy(shader
);
2550 void si_destroy_shader_selector(struct si_context
*sctx
,
2551 struct si_shader_selector
*sel
)
2553 struct si_shader
*p
= sel
->first_variant
, *c
;
2554 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
2555 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
2556 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
2557 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
2558 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
2559 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
2562 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
2564 if (current_shader
[sel
->type
]->cso
== sel
) {
2565 current_shader
[sel
->type
]->cso
= NULL
;
2566 current_shader
[sel
->type
]->current
= NULL
;
2570 c
= p
->next_variant
;
2571 si_delete_shader(sctx
, p
);
2575 if (sel
->main_shader_part
)
2576 si_delete_shader(sctx
, sel
->main_shader_part
);
2577 if (sel
->main_shader_part_ls
)
2578 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
2579 if (sel
->main_shader_part_es
)
2580 si_delete_shader(sctx
, sel
->main_shader_part_es
);
2581 if (sel
->gs_copy_shader
)
2582 si_delete_shader(sctx
, sel
->gs_copy_shader
);
2584 util_queue_fence_destroy(&sel
->ready
);
2585 mtx_destroy(&sel
->mutex
);
2587 ralloc_free(sel
->nir
);
2591 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
2593 struct si_context
*sctx
= (struct si_context
*)ctx
;
2594 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
2596 si_shader_selector_reference(sctx
, &sel
, NULL
);
2599 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
2600 struct si_shader
*vs
, unsigned name
,
2601 unsigned index
, unsigned interpolate
)
2603 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
2604 unsigned j
, offset
, ps_input_cntl
= 0;
2606 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2607 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
))
2608 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
2610 if (name
== TGSI_SEMANTIC_PCOORD
||
2611 (name
== TGSI_SEMANTIC_TEXCOORD
&&
2612 sctx
->sprite_coord_enable
& (1 << index
))) {
2613 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
2616 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
2617 if (name
== vsinfo
->output_semantic_name
[j
] &&
2618 index
== vsinfo
->output_semantic_index
[j
]) {
2619 offset
= vs
->info
.vs_output_param_offset
[j
];
2621 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
2622 /* The input is loaded from parameter memory. */
2623 ps_input_cntl
|= S_028644_OFFSET(offset
);
2624 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2625 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
2626 /* This can happen with depth-only rendering. */
2629 /* The input is a DEFAULT_VAL constant. */
2630 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
2631 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
2632 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
2635 ps_input_cntl
= S_028644_OFFSET(0x20) |
2636 S_028644_DEFAULT_VAL(offset
);
2642 if (name
== TGSI_SEMANTIC_PRIMID
)
2643 /* PrimID is written after the last output. */
2644 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
2645 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2646 /* No corresponding output found, load defaults into input.
2647 * Don't set any other bits.
2648 * (FLAT_SHADE=1 completely changes behavior) */
2649 ps_input_cntl
= S_028644_OFFSET(0x20);
2650 /* D3D 9 behaviour. GL is undefined */
2651 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
2652 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
2654 return ps_input_cntl
;
2657 static void si_emit_spi_map(struct si_context
*sctx
)
2659 struct si_shader
*ps
= sctx
->ps_shader
.current
;
2660 struct si_shader
*vs
= si_get_vs_state(sctx
);
2661 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
2662 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
2663 unsigned spi_ps_input_cntl
[32];
2665 if (!ps
|| !ps
->selector
->info
.num_inputs
)
2668 num_interp
= si_get_ps_num_interp(ps
);
2669 assert(num_interp
> 0);
2671 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
2672 unsigned name
= psinfo
->input_semantic_name
[i
];
2673 unsigned index
= psinfo
->input_semantic_index
[i
];
2674 unsigned interpolate
= psinfo
->input_interpolate
[i
];
2676 spi_ps_input_cntl
[num_written
++] = si_get_ps_input_cntl(sctx
, vs
, name
,
2677 index
, interpolate
);
2679 if (name
== TGSI_SEMANTIC_COLOR
) {
2680 assert(index
< ARRAY_SIZE(bcol_interp
));
2681 bcol_interp
[index
] = interpolate
;
2685 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
2686 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
2688 for (i
= 0; i
< 2; i
++) {
2689 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
2692 spi_ps_input_cntl
[num_written
++] =
2693 si_get_ps_input_cntl(sctx
, vs
, bcol
, i
, bcol_interp
[i
]);
2697 assert(num_interp
== num_written
);
2699 /* R_028644_SPI_PS_INPUT_CNTL_0 */
2700 /* Dota 2: Only ~16% of SPI map updates set different values. */
2701 /* Talos: Only ~9% of SPI map updates set different values. */
2702 radeon_opt_set_context_regn(sctx
, R_028644_SPI_PS_INPUT_CNTL_0
,
2704 sctx
->tracked_regs
.spi_ps_input_cntl
, num_interp
);
2708 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2710 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
2712 if (sctx
->init_config_has_vgt_flush
)
2715 /* Done by Vulkan before VGT_FLUSH. */
2716 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2717 si_pm4_cmd_add(sctx
->init_config
,
2718 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2719 si_pm4_cmd_end(sctx
->init_config
, false);
2721 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2722 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2723 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2724 si_pm4_cmd_end(sctx
->init_config
, false);
2725 sctx
->init_config_has_vgt_flush
= true;
2728 /* Initialize state related to ESGS / GSVS ring buffers */
2729 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
2731 struct si_shader_selector
*es
=
2732 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
2733 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
2734 struct si_pm4_state
*pm4
;
2736 /* Chip constants. */
2737 unsigned num_se
= sctx
->screen
->info
.max_se
;
2738 unsigned wave_size
= 64;
2739 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
2740 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2741 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2743 unsigned gs_vertex_reuse
= (sctx
->chip_class
>= VI
? 32 : 16) * num_se
;
2744 unsigned alignment
= 256 * num_se
;
2745 /* The maximum size is 63.999 MB per SE. */
2746 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
2748 /* Calculate the minimum size. */
2749 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
2750 wave_size
, alignment
);
2752 /* These are recommended sizes, not minimum sizes. */
2753 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
2754 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
2755 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
2756 gs
->max_gsvs_emit_size
;
2758 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
2759 esgs_ring_size
= align(esgs_ring_size
, alignment
);
2760 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
2762 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
2763 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
2765 /* Some rings don't have to be allocated if shaders don't use them.
2766 * (e.g. no varyings between ES and GS or GS and VS)
2768 * GFX9 doesn't have the ESGS ring.
2770 bool update_esgs
= sctx
->chip_class
<= VI
&&
2772 (!sctx
->esgs_ring
||
2773 sctx
->esgs_ring
->width0
< esgs_ring_size
);
2774 bool update_gsvs
= gsvs_ring_size
&&
2775 (!sctx
->gsvs_ring
||
2776 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
2778 if (!update_esgs
&& !update_gsvs
)
2782 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
2784 pipe_aligned_buffer_create(sctx
->b
.screen
,
2785 SI_RESOURCE_FLAG_UNMAPPABLE
,
2787 esgs_ring_size
, alignment
);
2788 if (!sctx
->esgs_ring
)
2793 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
2795 pipe_aligned_buffer_create(sctx
->b
.screen
,
2796 SI_RESOURCE_FLAG_UNMAPPABLE
,
2798 gsvs_ring_size
, alignment
);
2799 if (!sctx
->gsvs_ring
)
2803 /* Create the "init_config_gs_rings" state. */
2804 pm4
= CALLOC_STRUCT(si_pm4_state
);
2808 if (sctx
->chip_class
>= CIK
) {
2809 if (sctx
->esgs_ring
) {
2810 assert(sctx
->chip_class
<= VI
);
2811 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
2812 sctx
->esgs_ring
->width0
/ 256);
2814 if (sctx
->gsvs_ring
)
2815 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
2816 sctx
->gsvs_ring
->width0
/ 256);
2818 if (sctx
->esgs_ring
)
2819 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
2820 sctx
->esgs_ring
->width0
/ 256);
2821 if (sctx
->gsvs_ring
)
2822 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
2823 sctx
->gsvs_ring
->width0
/ 256);
2826 /* Set the state. */
2827 if (sctx
->init_config_gs_rings
)
2828 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
2829 sctx
->init_config_gs_rings
= pm4
;
2831 if (!sctx
->init_config_has_vgt_flush
) {
2832 si_init_config_add_vgt_flush(sctx
);
2833 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
2836 /* Flush the context to re-emit both init_config states. */
2837 sctx
->initial_gfx_cs_size
= 0; /* force flush */
2838 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
2840 /* Set ring bindings. */
2841 if (sctx
->esgs_ring
) {
2842 assert(sctx
->chip_class
<= VI
);
2843 si_set_ring_buffer(sctx
, SI_ES_RING_ESGS
,
2844 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2845 true, true, 4, 64, 0);
2846 si_set_ring_buffer(sctx
, SI_GS_RING_ESGS
,
2847 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2848 false, false, 0, 0, 0);
2850 if (sctx
->gsvs_ring
) {
2851 si_set_ring_buffer(sctx
, SI_RING_GSVS
,
2852 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
2853 false, false, 0, 0, 0);
2859 static void si_shader_lock(struct si_shader
*shader
)
2861 mtx_lock(&shader
->selector
->mutex
);
2862 if (shader
->previous_stage_sel
) {
2863 assert(shader
->previous_stage_sel
!= shader
->selector
);
2864 mtx_lock(&shader
->previous_stage_sel
->mutex
);
2868 static void si_shader_unlock(struct si_shader
*shader
)
2870 if (shader
->previous_stage_sel
)
2871 mtx_unlock(&shader
->previous_stage_sel
->mutex
);
2872 mtx_unlock(&shader
->selector
->mutex
);
2876 * @returns 1 if \p sel has been updated to use a new scratch buffer
2878 * < 0 if there was a failure
2880 static int si_update_scratch_buffer(struct si_context
*sctx
,
2881 struct si_shader
*shader
)
2883 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
2889 /* This shader doesn't need a scratch buffer */
2890 if (shader
->config
.scratch_bytes_per_wave
== 0)
2893 /* Prevent race conditions when updating:
2894 * - si_shader::scratch_bo
2895 * - si_shader::binary::code
2896 * - si_shader::previous_stage::binary::code.
2898 si_shader_lock(shader
);
2900 /* This shader is already configured to use the current
2901 * scratch buffer. */
2902 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
2903 si_shader_unlock(shader
);
2907 assert(sctx
->scratch_buffer
);
2909 if (shader
->previous_stage
)
2910 si_shader_apply_scratch_relocs(shader
->previous_stage
, scratch_va
);
2912 si_shader_apply_scratch_relocs(shader
, scratch_va
);
2914 /* Replace the shader bo with a new bo that has the relocs applied. */
2915 r
= si_shader_binary_upload(sctx
->screen
, shader
);
2917 si_shader_unlock(shader
);
2921 /* Update the shader state to use the new shader bo. */
2922 si_shader_init_pm4_state(sctx
->screen
, shader
);
2924 r600_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
2926 si_shader_unlock(shader
);
2930 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
2932 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
2935 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
2937 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
2940 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
2942 if (!sctx
->tes_shader
.cso
)
2943 return NULL
; /* tessellation disabled */
2945 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
:
2946 sctx
->fixed_func_tcs_shader
.current
;
2949 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
2953 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
2954 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
2955 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
2956 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
2958 if (sctx
->tes_shader
.cso
) {
2959 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
2961 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(tcs
));
2966 static bool si_update_scratch_relocs(struct si_context
*sctx
)
2968 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
2971 /* Update the shaders, so that they are using the latest scratch.
2972 * The scratch buffer may have been changed since these shaders were
2973 * last used, so we still need to try to update them, even if they
2974 * require scratch buffers smaller than the current size.
2976 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
2980 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
2982 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
2986 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
2988 r
= si_update_scratch_buffer(sctx
, tcs
);
2992 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
2994 /* VS can be bound as LS, ES, or VS. */
2995 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
2999 if (sctx
->tes_shader
.current
)
3000 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3001 else if (sctx
->gs_shader
.current
)
3002 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3004 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3007 /* TES can be bound as ES or VS. */
3008 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
3012 if (sctx
->gs_shader
.current
)
3013 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3015 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3021 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
3023 unsigned current_scratch_buffer_size
=
3024 si_get_current_scratch_buffer_size(sctx
);
3025 unsigned scratch_bytes_per_wave
=
3026 si_get_max_scratch_bytes_per_wave(sctx
);
3027 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
3028 sctx
->scratch_waves
;
3029 unsigned spi_tmpring_size
;
3031 if (scratch_needed_size
> 0) {
3032 if (scratch_needed_size
> current_scratch_buffer_size
) {
3033 /* Create a bigger scratch buffer */
3034 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
3036 sctx
->scratch_buffer
=
3037 si_aligned_buffer_create(&sctx
->screen
->b
,
3038 SI_RESOURCE_FLAG_UNMAPPABLE
,
3040 scratch_needed_size
, 256);
3041 if (!sctx
->scratch_buffer
)
3044 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3045 si_context_add_resource_size(sctx
,
3046 &sctx
->scratch_buffer
->b
.b
);
3049 if (!si_update_scratch_relocs(sctx
))
3053 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3054 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
3055 "scratch size should already be aligned correctly.");
3057 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
3058 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
3059 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
3060 sctx
->spi_tmpring_size
= spi_tmpring_size
;
3061 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3066 static void si_init_tess_factor_ring(struct si_context
*sctx
)
3068 assert(!sctx
->tess_rings
);
3070 /* The address must be aligned to 2^19, because the shader only
3071 * receives the high 13 bits.
3073 sctx
->tess_rings
= pipe_aligned_buffer_create(sctx
->b
.screen
,
3074 SI_RESOURCE_FLAG_32BIT
,
3076 sctx
->screen
->tess_offchip_ring_size
+
3077 sctx
->screen
->tess_factor_ring_size
,
3079 if (!sctx
->tess_rings
)
3082 si_init_config_add_vgt_flush(sctx
);
3084 si_pm4_add_bo(sctx
->init_config
, r600_resource(sctx
->tess_rings
),
3085 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3087 uint64_t factor_va
= r600_resource(sctx
->tess_rings
)->gpu_address
+
3088 sctx
->screen
->tess_offchip_ring_size
;
3090 /* Append these registers to the init config state. */
3091 if (sctx
->chip_class
>= CIK
) {
3092 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
3093 S_030938_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3094 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
3096 if (sctx
->chip_class
>= GFX9
)
3097 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3098 S_030944_BASE_HI(factor_va
>> 40));
3099 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3100 sctx
->screen
->vgt_hs_offchip_param
);
3102 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
3103 S_008988_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3104 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
3106 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3107 sctx
->screen
->vgt_hs_offchip_param
);
3110 /* Flush the context to re-emit the init_config state.
3111 * This is done only once in a lifetime of a context.
3113 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3114 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3115 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3118 static void si_update_vgt_shader_config(struct si_context
*sctx
)
3120 /* Calculate the index of the config.
3121 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3122 unsigned index
= 2*!!sctx
->tes_shader
.cso
+ !!sctx
->gs_shader
.cso
;
3123 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[index
];
3126 uint32_t stages
= 0;
3128 *pm4
= CALLOC_STRUCT(si_pm4_state
);
3130 if (sctx
->tes_shader
.cso
) {
3131 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3132 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3134 if (sctx
->gs_shader
.cso
)
3135 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3137 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3139 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3140 } else if (sctx
->gs_shader
.cso
) {
3141 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3143 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3146 if (sctx
->chip_class
>= GFX9
)
3147 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3149 si_pm4_set_reg(*pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3151 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3154 bool si_update_shaders(struct si_context
*sctx
)
3156 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3157 struct si_compiler_ctx_state compiler_state
;
3158 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3159 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3160 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
3161 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
3162 unsigned old_spi_shader_col_format
=
3163 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
3166 compiler_state
.compiler
= &sctx
->compiler
;
3167 compiler_state
.debug
= sctx
->debug
;
3168 compiler_state
.is_debug_context
= sctx
->is_debug
;
3170 /* Update stages before GS. */
3171 if (sctx
->tes_shader
.cso
) {
3172 if (!sctx
->tess_rings
) {
3173 si_init_tess_factor_ring(sctx
);
3174 if (!sctx
->tess_rings
)
3179 if (sctx
->chip_class
<= VI
) {
3180 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3184 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3187 if (sctx
->tcs_shader
.cso
) {
3188 r
= si_shader_select(ctx
, &sctx
->tcs_shader
,
3192 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3194 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3195 sctx
->fixed_func_tcs_shader
.cso
=
3196 si_create_fixed_func_tcs(sctx
);
3197 if (!sctx
->fixed_func_tcs_shader
.cso
)
3201 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
3205 si_pm4_bind_state(sctx
, hs
,
3206 sctx
->fixed_func_tcs_shader
.current
->pm4
);
3209 if (sctx
->gs_shader
.cso
) {
3211 if (sctx
->chip_class
<= VI
) {
3212 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3216 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3220 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3224 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3226 } else if (sctx
->gs_shader
.cso
) {
3227 if (sctx
->chip_class
<= VI
) {
3229 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3233 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3235 si_pm4_bind_state(sctx
, ls
, NULL
);
3236 si_pm4_bind_state(sctx
, hs
, NULL
);
3240 r
= si_shader_select(ctx
, &sctx
->vs_shader
, &compiler_state
);
3243 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3244 si_pm4_bind_state(sctx
, ls
, NULL
);
3245 si_pm4_bind_state(sctx
, hs
, NULL
);
3249 if (sctx
->gs_shader
.cso
) {
3250 r
= si_shader_select(ctx
, &sctx
->gs_shader
, &compiler_state
);
3253 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3254 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3256 if (!si_update_gs_ring_buffers(sctx
))
3259 si_pm4_bind_state(sctx
, gs
, NULL
);
3260 if (sctx
->chip_class
<= VI
)
3261 si_pm4_bind_state(sctx
, es
, NULL
);
3264 si_update_vgt_shader_config(sctx
);
3266 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
3267 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
3269 if (sctx
->ps_shader
.cso
) {
3270 unsigned db_shader_control
;
3272 r
= si_shader_select(ctx
, &sctx
->ps_shader
, &compiler_state
);
3275 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3278 sctx
->ps_shader
.cso
->db_shader_control
|
3279 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
3281 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
3282 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
3283 sctx
->flatshade
!= rs
->flatshade
) {
3284 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
3285 sctx
->flatshade
= rs
->flatshade
;
3286 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.spi_map
);
3289 if (sctx
->screen
->rbplus_allowed
&&
3290 si_pm4_state_changed(sctx
, ps
) &&
3292 old_spi_shader_col_format
!=
3293 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
3294 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3296 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
3297 sctx
->ps_db_shader_control
= db_shader_control
;
3298 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3299 if (sctx
->screen
->dpbb_allowed
)
3300 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3303 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
3304 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
3305 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3307 if (sctx
->chip_class
== SI
)
3308 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3310 if (sctx
->framebuffer
.nr_samples
<= 1)
3311 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
3315 if (si_pm4_state_enabled_and_changed(sctx
, ls
) ||
3316 si_pm4_state_enabled_and_changed(sctx
, hs
) ||
3317 si_pm4_state_enabled_and_changed(sctx
, es
) ||
3318 si_pm4_state_enabled_and_changed(sctx
, gs
) ||
3319 si_pm4_state_enabled_and_changed(sctx
, vs
) ||
3320 si_pm4_state_enabled_and_changed(sctx
, ps
)) {
3321 if (!si_update_spi_tmpring_size(sctx
))
3325 if (sctx
->chip_class
>= CIK
) {
3326 if (si_pm4_state_enabled_and_changed(sctx
, ls
))
3327 sctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
3328 else if (!sctx
->queued
.named
.ls
)
3329 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_LS
;
3331 if (si_pm4_state_enabled_and_changed(sctx
, hs
))
3332 sctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
3333 else if (!sctx
->queued
.named
.hs
)
3334 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_HS
;
3336 if (si_pm4_state_enabled_and_changed(sctx
, es
))
3337 sctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
3338 else if (!sctx
->queued
.named
.es
)
3339 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_ES
;
3341 if (si_pm4_state_enabled_and_changed(sctx
, gs
))
3342 sctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
3343 else if (!sctx
->queued
.named
.gs
)
3344 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_GS
;
3346 if (si_pm4_state_enabled_and_changed(sctx
, vs
))
3347 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
3348 else if (!sctx
->queued
.named
.vs
)
3349 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VS
;
3351 if (si_pm4_state_enabled_and_changed(sctx
, ps
))
3352 sctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
3353 else if (!sctx
->queued
.named
.ps
)
3354 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_PS
;
3357 sctx
->do_update_shaders
= false;
3361 static void si_emit_scratch_state(struct si_context
*sctx
)
3363 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3365 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3366 sctx
->spi_tmpring_size
);
3368 if (sctx
->scratch_buffer
) {
3369 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3370 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
3371 RADEON_PRIO_SCRATCH_BUFFER
);
3375 void si_init_shader_functions(struct si_context
*sctx
)
3377 sctx
->atoms
.s
.spi_map
.emit
= si_emit_spi_map
;
3378 sctx
->atoms
.s
.scratch_state
.emit
= si_emit_scratch_state
;
3380 sctx
->b
.create_vs_state
= si_create_shader_selector
;
3381 sctx
->b
.create_tcs_state
= si_create_shader_selector
;
3382 sctx
->b
.create_tes_state
= si_create_shader_selector
;
3383 sctx
->b
.create_gs_state
= si_create_shader_selector
;
3384 sctx
->b
.create_fs_state
= si_create_shader_selector
;
3386 sctx
->b
.bind_vs_state
= si_bind_vs_shader
;
3387 sctx
->b
.bind_tcs_state
= si_bind_tcs_shader
;
3388 sctx
->b
.bind_tes_state
= si_bind_tes_shader
;
3389 sctx
->b
.bind_gs_state
= si_bind_gs_shader
;
3390 sctx
->b
.bind_fs_state
= si_bind_ps_shader
;
3392 sctx
->b
.delete_vs_state
= si_delete_shader_selector
;
3393 sctx
->b
.delete_tcs_state
= si_delete_shader_selector
;
3394 sctx
->b
.delete_tes_state
= si_delete_shader_selector
;
3395 sctx
->b
.delete_gs_state
= si_delete_shader_selector
;
3396 sctx
->b
.delete_fs_state
= si_delete_shader_selector
;