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radeonsi: clean up passing the is_monolithic flag for compilation
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_ureg.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
36
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41
42 /* SHADER_CACHE */
43
44 /**
45 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
46 * size as integer.
47 */
48 static void *si_get_ir_binary(struct si_shader_selector *sel)
49 {
50 struct blob blob;
51 unsigned ir_size;
52 void *ir_binary;
53
54 if (sel->tokens) {
55 ir_binary = sel->tokens;
56 ir_size = tgsi_num_tokens(sel->tokens) *
57 sizeof(struct tgsi_token);
58 } else {
59 assert(sel->nir);
60
61 blob_init(&blob);
62 nir_serialize(&blob, sel->nir);
63 ir_binary = blob.data;
64 ir_size = blob.size;
65 }
66
67 unsigned size = 4 + ir_size + sizeof(sel->so);
68 char *result = (char*)MALLOC(size);
69 if (!result)
70 return NULL;
71
72 *((uint32_t*)result) = size;
73 memcpy(result + 4, ir_binary, ir_size);
74 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
75
76 if (sel->nir)
77 blob_finish(&blob);
78
79 return result;
80 }
81
82 /** Copy "data" to "ptr" and return the next dword following copied data. */
83 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
84 {
85 /* data may be NULL if size == 0 */
86 if (size)
87 memcpy(ptr, data, size);
88 ptr += DIV_ROUND_UP(size, 4);
89 return ptr;
90 }
91
92 /** Read data from "ptr". Return the next dword following the data. */
93 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
94 {
95 memcpy(data, ptr, size);
96 ptr += DIV_ROUND_UP(size, 4);
97 return ptr;
98 }
99
100 /**
101 * Write the size as uint followed by the data. Return the next dword
102 * following the copied data.
103 */
104 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
105 {
106 *ptr++ = size;
107 return write_data(ptr, data, size);
108 }
109
110 /**
111 * Read the size as uint followed by the data. Return both via parameters.
112 * Return the next dword following the data.
113 */
114 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
115 {
116 *size = *ptr++;
117 assert(*data == NULL);
118 if (!*size)
119 return ptr;
120 *data = malloc(*size);
121 return read_data(ptr, *data, *size);
122 }
123
124 /**
125 * Return the shader binary in a buffer. The first 4 bytes contain its size
126 * as integer.
127 */
128 static void *si_get_shader_binary(struct si_shader *shader)
129 {
130 /* There is always a size of data followed by the data itself. */
131 unsigned relocs_size = shader->binary.reloc_count *
132 sizeof(shader->binary.relocs[0]);
133 unsigned disasm_size = shader->binary.disasm_string ?
134 strlen(shader->binary.disasm_string) + 1 : 0;
135 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
136 strlen(shader->binary.llvm_ir_string) + 1 : 0;
137 unsigned size =
138 4 + /* total size */
139 4 + /* CRC32 of the data below */
140 align(sizeof(shader->config), 4) +
141 align(sizeof(shader->info), 4) +
142 4 + align(shader->binary.code_size, 4) +
143 4 + align(shader->binary.rodata_size, 4) +
144 4 + align(relocs_size, 4) +
145 4 + align(disasm_size, 4) +
146 4 + align(llvm_ir_size, 4);
147 void *buffer = CALLOC(1, size);
148 uint32_t *ptr = (uint32_t*)buffer;
149
150 if (!buffer)
151 return NULL;
152
153 *ptr++ = size;
154 ptr++; /* CRC32 is calculated at the end. */
155
156 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
157 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
158 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
159 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
160 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
161 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
162 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
163 assert((char *)ptr - (char *)buffer == size);
164
165 /* Compute CRC32. */
166 ptr = (uint32_t*)buffer;
167 ptr++;
168 *ptr = util_hash_crc32(ptr + 1, size - 8);
169
170 return buffer;
171 }
172
173 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
174 {
175 uint32_t *ptr = (uint32_t*)binary;
176 uint32_t size = *ptr++;
177 uint32_t crc32 = *ptr++;
178 unsigned chunk_size;
179
180 if (util_hash_crc32(ptr, size - 8) != crc32) {
181 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
182 return false;
183 }
184
185 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
186 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
187 ptr = read_chunk(ptr, (void**)&shader->binary.code,
188 &shader->binary.code_size);
189 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
190 &shader->binary.rodata_size);
191 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
192 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
193 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
194 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
195
196 return true;
197 }
198
199 /**
200 * Insert a shader into the cache. It's assumed the shader is not in the cache.
201 * Use si_shader_cache_load_shader before calling this.
202 *
203 * Returns false on failure, in which case the ir_binary should be freed.
204 */
205 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
206 void *ir_binary,
207 struct si_shader *shader,
208 bool insert_into_disk_cache)
209 {
210 void *hw_binary;
211 struct hash_entry *entry;
212 uint8_t key[CACHE_KEY_SIZE];
213
214 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
215 if (entry)
216 return false; /* already added */
217
218 hw_binary = si_get_shader_binary(shader);
219 if (!hw_binary)
220 return false;
221
222 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
223 hw_binary) == NULL) {
224 FREE(hw_binary);
225 return false;
226 }
227
228 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
229 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
230 *((uint32_t *)ir_binary), key);
231 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
232 *((uint32_t *) hw_binary), NULL);
233 }
234
235 return true;
236 }
237
238 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
239 void *ir_binary,
240 struct si_shader *shader)
241 {
242 struct hash_entry *entry =
243 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
244 if (!entry) {
245 if (sscreen->disk_shader_cache) {
246 unsigned char sha1[CACHE_KEY_SIZE];
247 size_t tg_size = *((uint32_t *) ir_binary);
248
249 disk_cache_compute_key(sscreen->disk_shader_cache,
250 ir_binary, tg_size, sha1);
251
252 size_t binary_size;
253 uint8_t *buffer =
254 disk_cache_get(sscreen->disk_shader_cache,
255 sha1, &binary_size);
256 if (!buffer)
257 return false;
258
259 if (binary_size < sizeof(uint32_t) ||
260 *((uint32_t*)buffer) != binary_size) {
261 /* Something has gone wrong discard the item
262 * from the cache and rebuild/link from
263 * source.
264 */
265 assert(!"Invalid radeonsi shader disk cache "
266 "item!");
267
268 disk_cache_remove(sscreen->disk_shader_cache,
269 sha1);
270 free(buffer);
271
272 return false;
273 }
274
275 if (!si_load_shader_binary(shader, buffer)) {
276 free(buffer);
277 return false;
278 }
279 free(buffer);
280
281 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
282 shader, false))
283 FREE(ir_binary);
284 } else {
285 return false;
286 }
287 } else {
288 if (si_load_shader_binary(shader, entry->data))
289 FREE(ir_binary);
290 else
291 return false;
292 }
293 p_atomic_inc(&sscreen->num_shader_cache_hits);
294 return true;
295 }
296
297 static uint32_t si_shader_cache_key_hash(const void *key)
298 {
299 /* The first dword is the key size. */
300 return util_hash_crc32(key, *(uint32_t*)key);
301 }
302
303 static bool si_shader_cache_key_equals(const void *a, const void *b)
304 {
305 uint32_t *keya = (uint32_t*)a;
306 uint32_t *keyb = (uint32_t*)b;
307
308 /* The first dword is the key size. */
309 if (*keya != *keyb)
310 return false;
311
312 return memcmp(keya, keyb, *keya) == 0;
313 }
314
315 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
316 {
317 FREE((void*)entry->key);
318 FREE(entry->data);
319 }
320
321 bool si_init_shader_cache(struct si_screen *sscreen)
322 {
323 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
324 sscreen->shader_cache =
325 _mesa_hash_table_create(NULL,
326 si_shader_cache_key_hash,
327 si_shader_cache_key_equals);
328
329 return sscreen->shader_cache != NULL;
330 }
331
332 void si_destroy_shader_cache(struct si_screen *sscreen)
333 {
334 if (sscreen->shader_cache)
335 _mesa_hash_table_destroy(sscreen->shader_cache,
336 si_destroy_shader_cache_entry);
337 mtx_destroy(&sscreen->shader_cache_mutex);
338 }
339
340 /* SHADER STATES */
341
342 static void si_set_tesseval_regs(struct si_screen *sscreen,
343 struct si_shader_selector *tes,
344 struct si_pm4_state *pm4)
345 {
346 struct tgsi_shader_info *info = &tes->info;
347 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
348 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
349 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
350 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
351 unsigned type, partitioning, topology, distribution_mode;
352
353 switch (tes_prim_mode) {
354 case PIPE_PRIM_LINES:
355 type = V_028B6C_TESS_ISOLINE;
356 break;
357 case PIPE_PRIM_TRIANGLES:
358 type = V_028B6C_TESS_TRIANGLE;
359 break;
360 case PIPE_PRIM_QUADS:
361 type = V_028B6C_TESS_QUAD;
362 break;
363 default:
364 assert(0);
365 return;
366 }
367
368 switch (tes_spacing) {
369 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
370 partitioning = V_028B6C_PART_FRAC_ODD;
371 break;
372 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
373 partitioning = V_028B6C_PART_FRAC_EVEN;
374 break;
375 case PIPE_TESS_SPACING_EQUAL:
376 partitioning = V_028B6C_PART_INTEGER;
377 break;
378 default:
379 assert(0);
380 return;
381 }
382
383 if (tes_point_mode)
384 topology = V_028B6C_OUTPUT_POINT;
385 else if (tes_prim_mode == PIPE_PRIM_LINES)
386 topology = V_028B6C_OUTPUT_LINE;
387 else if (tes_vertex_order_cw)
388 /* for some reason, this must be the other way around */
389 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
390 else
391 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
392
393 if (sscreen->has_distributed_tess) {
394 if (sscreen->info.family == CHIP_FIJI ||
395 sscreen->info.family >= CHIP_POLARIS10)
396 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
397 else
398 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
399 } else
400 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
401
402 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
403 S_028B6C_TYPE(type) |
404 S_028B6C_PARTITIONING(partitioning) |
405 S_028B6C_TOPOLOGY(topology) |
406 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
407 }
408
409 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
410 * whether the "fractional odd" tessellation spacing is used.
411 *
412 * Possible VGT configurations and which state should set the register:
413 *
414 * Reg set in | VGT shader configuration | Value
415 * ------------------------------------------------------
416 * VS as VS | VS | 30
417 * VS as ES | ES -> GS -> VS | 30
418 * TES as VS | LS -> HS -> VS | 14 or 30
419 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
420 *
421 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
422 */
423 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
424 struct si_shader_selector *sel,
425 struct si_shader *shader,
426 struct si_pm4_state *pm4)
427 {
428 unsigned type = sel->type;
429
430 if (sscreen->info.family < CHIP_POLARIS10)
431 return;
432
433 /* VS as VS, or VS as ES: */
434 if ((type == PIPE_SHADER_VERTEX &&
435 (!shader ||
436 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
437 /* TES as VS, or TES as ES: */
438 type == PIPE_SHADER_TESS_EVAL) {
439 unsigned vtx_reuse_depth = 30;
440
441 if (type == PIPE_SHADER_TESS_EVAL &&
442 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
443 PIPE_TESS_SPACING_FRACTIONAL_ODD)
444 vtx_reuse_depth = 14;
445
446 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
447 vtx_reuse_depth);
448 }
449 }
450
451 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
452 {
453 if (shader->pm4)
454 si_pm4_clear_state(shader->pm4);
455 else
456 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
457
458 return shader->pm4;
459 }
460
461 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
462 {
463 /* Add the pointer to VBO descriptors. */
464 if (HAVE_32BIT_POINTERS) {
465 return num_always_on_user_sgprs + 1;
466 } else {
467 assert(num_always_on_user_sgprs % 2 == 0);
468 return num_always_on_user_sgprs + 2;
469 }
470 }
471
472 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
473 {
474 struct si_pm4_state *pm4;
475 unsigned vgpr_comp_cnt;
476 uint64_t va;
477
478 assert(sscreen->info.chip_class <= VI);
479
480 pm4 = si_get_shader_pm4_state(shader);
481 if (!pm4)
482 return;
483
484 va = shader->bo->gpu_address;
485 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
486
487 /* We need at least 2 components for LS.
488 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
489 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
490 */
491 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
492
493 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
494 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
495
496 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
497 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
498 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
499 S_00B528_DX10_CLAMP(1) |
500 S_00B528_FLOAT_MODE(shader->config.float_mode);
501 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
502 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
503 }
504
505 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
506 {
507 struct si_pm4_state *pm4;
508 uint64_t va;
509 unsigned ls_vgpr_comp_cnt = 0;
510
511 pm4 = si_get_shader_pm4_state(shader);
512 if (!pm4)
513 return;
514
515 va = shader->bo->gpu_address;
516 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
517
518 if (sscreen->info.chip_class >= GFX9) {
519 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
520 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
521
522 /* We need at least 2 components for LS.
523 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
524 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
525 */
526 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
527
528 unsigned num_user_sgprs =
529 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
530
531 shader->config.rsrc2 =
532 S_00B42C_USER_SGPR(num_user_sgprs) |
533 S_00B42C_USER_SGPR_MSB(num_user_sgprs >> 5) |
534 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
535 } else {
536 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
537 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
538
539 shader->config.rsrc2 =
540 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
541 S_00B42C_OC_LDS_EN(1) |
542 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
543 }
544
545 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
546 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
547 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
548 S_00B428_DX10_CLAMP(1) |
549 S_00B428_FLOAT_MODE(shader->config.float_mode) |
550 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
551
552 if (sscreen->info.chip_class <= VI) {
553 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
554 shader->config.rsrc2);
555 }
556 }
557
558 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
559 {
560 struct si_pm4_state *pm4;
561 unsigned num_user_sgprs;
562 unsigned vgpr_comp_cnt;
563 uint64_t va;
564 unsigned oc_lds_en;
565
566 assert(sscreen->info.chip_class <= VI);
567
568 pm4 = si_get_shader_pm4_state(shader);
569 if (!pm4)
570 return;
571
572 va = shader->bo->gpu_address;
573 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
574
575 if (shader->selector->type == PIPE_SHADER_VERTEX) {
576 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
577 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
578 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
579 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
580 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
581 num_user_sgprs = SI_TES_NUM_USER_SGPR;
582 } else
583 unreachable("invalid shader selector type");
584
585 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
586
587 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
588 shader->selector->esgs_itemsize / 4);
589 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
590 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
591 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
592 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
593 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
594 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
595 S_00B328_DX10_CLAMP(1) |
596 S_00B328_FLOAT_MODE(shader->config.float_mode));
597 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
598 S_00B32C_USER_SGPR(num_user_sgprs) |
599 S_00B32C_OC_LDS_EN(oc_lds_en) |
600 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
601
602 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
603 si_set_tesseval_regs(sscreen, shader->selector, pm4);
604
605 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
606 }
607
608 static unsigned si_conv_prim_to_gs_out(unsigned mode)
609 {
610 static const int prim_conv[] = {
611 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
612 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
613 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
614 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
615 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
616 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
617 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
618 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
619 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
620 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
621 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
622 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
623 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
624 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
625 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
626 };
627 assert(mode < ARRAY_SIZE(prim_conv));
628
629 return prim_conv[mode];
630 }
631
632 struct gfx9_gs_info {
633 unsigned es_verts_per_subgroup;
634 unsigned gs_prims_per_subgroup;
635 unsigned gs_inst_prims_in_subgroup;
636 unsigned max_prims_per_subgroup;
637 unsigned lds_size;
638 };
639
640 static void gfx9_get_gs_info(struct si_shader_selector *es,
641 struct si_shader_selector *gs,
642 struct gfx9_gs_info *out)
643 {
644 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
645 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
646 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
647 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
648
649 /* All these are in dwords: */
650 /* We can't allow using the whole LDS, because GS waves compete with
651 * other shader stages for LDS space. */
652 const unsigned max_lds_size = 8 * 1024;
653 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
654 unsigned esgs_lds_size;
655
656 /* All these are per subgroup: */
657 const unsigned max_out_prims = 32 * 1024;
658 const unsigned max_es_verts = 255;
659 const unsigned ideal_gs_prims = 64;
660 unsigned max_gs_prims, gs_prims;
661 unsigned min_es_verts, es_verts, worst_case_es_verts;
662
663 assert(gs_num_invocations <= 32); /* GL maximum */
664
665 if (uses_adjacency || gs_num_invocations > 1)
666 max_gs_prims = 127 / gs_num_invocations;
667 else
668 max_gs_prims = 255;
669
670 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
671 * Make sure we don't go over the maximum value.
672 */
673 if (gs->gs_max_out_vertices > 0) {
674 max_gs_prims = MIN2(max_gs_prims,
675 max_out_prims /
676 (gs->gs_max_out_vertices * gs_num_invocations));
677 }
678 assert(max_gs_prims > 0);
679
680 /* If the primitive has adjacency, halve the number of vertices
681 * that will be reused in multiple primitives.
682 */
683 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
684
685 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
686 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
687
688 /* Compute ESGS LDS size based on the worst case number of ES vertices
689 * needed to create the target number of GS prims per subgroup.
690 */
691 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
692
693 /* If total LDS usage is too big, refactor partitions based on ratio
694 * of ESGS item sizes.
695 */
696 if (esgs_lds_size > max_lds_size) {
697 /* Our target GS Prims Per Subgroup was too large. Calculate
698 * the maximum number of GS Prims Per Subgroup that will fit
699 * into LDS, capped by the maximum that the hardware can support.
700 */
701 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
702 max_gs_prims);
703 assert(gs_prims > 0);
704 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
705 max_es_verts);
706
707 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
708 assert(esgs_lds_size <= max_lds_size);
709 }
710
711 /* Now calculate remaining ESGS information. */
712 if (esgs_lds_size)
713 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
714 else
715 es_verts = max_es_verts;
716
717 /* Vertices for adjacency primitives are not always reused, so restore
718 * it for ES_VERTS_PER_SUBGRP.
719 */
720 min_es_verts = gs->gs_input_verts_per_prim;
721
722 /* For normal primitives, the VGT only checks if they are past the ES
723 * verts per subgroup after allocating a full GS primitive and if they
724 * are, kick off a new subgroup. But if those additional ES verts are
725 * unique (e.g. not reused) we need to make sure there is enough LDS
726 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
727 */
728 es_verts -= min_es_verts - 1;
729
730 out->es_verts_per_subgroup = es_verts;
731 out->gs_prims_per_subgroup = gs_prims;
732 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
733 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
734 gs->gs_max_out_vertices;
735 out->lds_size = align(esgs_lds_size, 128) / 128;
736
737 assert(out->max_prims_per_subgroup <= max_out_prims);
738 }
739
740 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
741 {
742 struct si_shader_selector *sel = shader->selector;
743 const ubyte *num_components = sel->info.num_stream_output_components;
744 unsigned gs_num_invocations = sel->gs_num_invocations;
745 struct si_pm4_state *pm4;
746 uint64_t va;
747 unsigned max_stream = sel->max_gs_stream;
748 unsigned offset;
749
750 pm4 = si_get_shader_pm4_state(shader);
751 if (!pm4)
752 return;
753
754 offset = num_components[0] * sel->gs_max_out_vertices;
755 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
756 if (max_stream >= 1)
757 offset += num_components[1] * sel->gs_max_out_vertices;
758 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
759 if (max_stream >= 2)
760 offset += num_components[2] * sel->gs_max_out_vertices;
761 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
762 si_pm4_set_reg(pm4, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
763 si_conv_prim_to_gs_out(sel->gs_output_prim));
764 if (max_stream >= 3)
765 offset += num_components[3] * sel->gs_max_out_vertices;
766 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
767
768 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
769 assert(offset < (1 << 15));
770
771 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, sel->gs_max_out_vertices);
772
773 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
774 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
775 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
776 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
777
778 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
779 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
780 S_028B90_ENABLE(gs_num_invocations > 0));
781
782 va = shader->bo->gpu_address;
783 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
784
785 if (sscreen->info.chip_class >= GFX9) {
786 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
787 unsigned es_type = shader->key.part.gs.es->type;
788 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
789 struct gfx9_gs_info gs_info;
790
791 if (es_type == PIPE_SHADER_VERTEX)
792 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
793 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
794 else if (es_type == PIPE_SHADER_TESS_EVAL)
795 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
796 else
797 unreachable("invalid shader selector type");
798
799 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
800 * VGPR[0:4] are always loaded.
801 */
802 if (sel->info.uses_invocationid)
803 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
804 else if (sel->info.uses_primid)
805 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
806 else if (input_prim >= PIPE_PRIM_TRIANGLES)
807 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
808 else
809 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
810
811 unsigned num_user_sgprs;
812 if (es_type == PIPE_SHADER_VERTEX)
813 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
814 else
815 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
816
817 gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
818
819 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
820 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
821
822 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
823 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
824 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
825 S_00B228_DX10_CLAMP(1) |
826 S_00B228_FLOAT_MODE(shader->config.float_mode) |
827 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
828 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
829 S_00B22C_USER_SGPR(num_user_sgprs) |
830 S_00B22C_USER_SGPR_MSB(num_user_sgprs >> 5) |
831 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
832 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
833 S_00B22C_LDS_SIZE(gs_info.lds_size) |
834 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
835
836 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
837 S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) |
838 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) |
839 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup));
840 si_pm4_set_reg(pm4, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
841 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup));
842 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
843 shader->key.part.gs.es->esgs_itemsize / 4);
844
845 if (es_type == PIPE_SHADER_TESS_EVAL)
846 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
847
848 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
849 NULL, pm4);
850 } else {
851 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
852 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
853
854 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
855 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
856 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
857 S_00B228_DX10_CLAMP(1) |
858 S_00B228_FLOAT_MODE(shader->config.float_mode));
859 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
860 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
861 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
862 }
863 }
864
865 /**
866 * Compute the state for \p shader, which will run as a vertex shader on the
867 * hardware.
868 *
869 * If \p gs is non-NULL, it points to the geometry shader for which this shader
870 * is the copy shader.
871 */
872 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
873 struct si_shader_selector *gs)
874 {
875 const struct tgsi_shader_info *info = &shader->selector->info;
876 struct si_pm4_state *pm4;
877 unsigned num_user_sgprs;
878 unsigned nparams, vgpr_comp_cnt;
879 uint64_t va;
880 unsigned oc_lds_en;
881 unsigned window_space =
882 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
883 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
884
885 pm4 = si_get_shader_pm4_state(shader);
886 if (!pm4)
887 return;
888
889 /* We always write VGT_GS_MODE in the VS state, because every switch
890 * between different shader pipelines involving a different GS or no
891 * GS at all involves a switch of the VS (different GS use different
892 * copy shaders). On the other hand, when the API switches from a GS to
893 * no GS and then back to the same GS used originally, the GS state is
894 * not sent again.
895 */
896 if (!gs) {
897 unsigned mode = V_028A40_GS_OFF;
898
899 /* PrimID needs GS scenario A. */
900 if (enable_prim_id)
901 mode = V_028A40_GS_SCENARIO_A;
902
903 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, S_028A40_MODE(mode));
904 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
905 } else {
906 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
907 ac_vgt_gs_mode(gs->gs_max_out_vertices,
908 sscreen->info.chip_class));
909 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
910 }
911
912 if (sscreen->info.chip_class <= VI) {
913 /* Reuse needs to be set off if we write oViewport. */
914 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF,
915 S_028AB4_REUSE_OFF(info->writes_viewport_index));
916 }
917
918 va = shader->bo->gpu_address;
919 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
920
921 if (gs) {
922 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
923 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
924 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
925 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
926 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
927 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
928 */
929 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
930
931 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
932 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
933 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
934 } else {
935 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
936 }
937 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
938 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
939 num_user_sgprs = SI_TES_NUM_USER_SGPR;
940 } else
941 unreachable("invalid shader selector type");
942
943 /* VS is required to export at least one param. */
944 nparams = MAX2(shader->info.nr_param_exports, 1);
945 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
946 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
947
948 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
949 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
950 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
951 V_02870C_SPI_SHADER_4COMP :
952 V_02870C_SPI_SHADER_NONE) |
953 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
954 V_02870C_SPI_SHADER_4COMP :
955 V_02870C_SPI_SHADER_NONE) |
956 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
957 V_02870C_SPI_SHADER_4COMP :
958 V_02870C_SPI_SHADER_NONE));
959
960 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
961
962 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
963 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
964 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
965 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
966 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
967 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
968 S_00B128_DX10_CLAMP(1) |
969 S_00B128_FLOAT_MODE(shader->config.float_mode));
970 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
971 S_00B12C_USER_SGPR(num_user_sgprs) |
972 S_00B12C_OC_LDS_EN(oc_lds_en) |
973 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
974 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
975 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
976 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
977 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
978 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
979 if (window_space)
980 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
981 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
982 else
983 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
984 S_028818_VTX_W0_FMT(1) |
985 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
986 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
987 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
988
989 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
990 si_set_tesseval_regs(sscreen, shader->selector, pm4);
991
992 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
993 }
994
995 static unsigned si_get_ps_num_interp(struct si_shader *ps)
996 {
997 struct tgsi_shader_info *info = &ps->selector->info;
998 unsigned num_colors = !!(info->colors_read & 0x0f) +
999 !!(info->colors_read & 0xf0);
1000 unsigned num_interp = ps->selector->info.num_inputs +
1001 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1002
1003 assert(num_interp <= 32);
1004 return MIN2(num_interp, 32);
1005 }
1006
1007 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1008 {
1009 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1010 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1011
1012 /* If the i-th target format is set, all previous target formats must
1013 * be non-zero to avoid hangs.
1014 */
1015 for (i = 0; i < num_targets; i++)
1016 if (!(value & (0xf << (i * 4))))
1017 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1018
1019 return value;
1020 }
1021
1022 static void si_shader_ps(struct si_shader *shader)
1023 {
1024 struct tgsi_shader_info *info = &shader->selector->info;
1025 struct si_pm4_state *pm4;
1026 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1027 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1028 uint64_t va;
1029 unsigned input_ena = shader->config.spi_ps_input_ena;
1030
1031 /* we need to enable at least one of them, otherwise we hang the GPU */
1032 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1033 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1034 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1035 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1036 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1037 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1038 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1039 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1040 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1041 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1042 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1043 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1044 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1045 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1046
1047 /* Validate interpolation optimization flags (read as implications). */
1048 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1049 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1050 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1051 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1052 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1053 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1054 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1055 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1056 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1057 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1058 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1059 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1060 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1061 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1062 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1063 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1064 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1065 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1066
1067 /* Validate cases when the optimizations are off (read as implications). */
1068 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1069 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1070 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1071 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1072 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1073 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1074
1075 pm4 = si_get_shader_pm4_state(shader);
1076 if (!pm4)
1077 return;
1078
1079 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1080 * Possible vaules:
1081 * 0 -> Position = pixel center
1082 * 1 -> Position = pixel centroid
1083 * 2 -> Position = at sample position
1084 *
1085 * From GLSL 4.5 specification, section 7.1:
1086 * "The variable gl_FragCoord is available as an input variable from
1087 * within fragment shaders and it holds the window relative coordinates
1088 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1089 * value can be for any location within the pixel, or one of the
1090 * fragment samples. The use of centroid does not further restrict
1091 * this value to be inside the current primitive."
1092 *
1093 * Meaning that centroid has no effect and we can return anything within
1094 * the pixel. Thus, return the value at sample position, because that's
1095 * the most accurate one shaders can get.
1096 */
1097 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1098
1099 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1100 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1101 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1102
1103 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1104 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1105
1106 /* Ensure that some export memory is always allocated, for two reasons:
1107 *
1108 * 1) Correctness: The hardware ignores the EXEC mask if no export
1109 * memory is allocated, so KILL and alpha test do not work correctly
1110 * without this.
1111 * 2) Performance: Every shader needs at least a NULL export, even when
1112 * it writes no color/depth output. The NULL export instruction
1113 * stalls without this setting.
1114 *
1115 * Don't add this to CB_SHADER_MASK.
1116 */
1117 if (!spi_shader_col_format &&
1118 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1119 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1120
1121 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
1122 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
1123 shader->config.spi_ps_input_addr);
1124
1125 /* Set interpolation controls. */
1126 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1127
1128 /* Set registers. */
1129 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1130 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
1131
1132 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
1133 ac_get_spi_shader_z_format(info->writes_z,
1134 info->writes_stencil,
1135 info->writes_samplemask));
1136
1137 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
1138 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
1139
1140 va = shader->bo->gpu_address;
1141 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1142 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1143 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1144
1145 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1146 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1147 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
1148 S_00B028_DX10_CLAMP(1) |
1149 S_00B028_FLOAT_MODE(shader->config.float_mode));
1150 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1151 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1152 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1153 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1154 }
1155
1156 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1157 struct si_shader *shader)
1158 {
1159 switch (shader->selector->type) {
1160 case PIPE_SHADER_VERTEX:
1161 if (shader->key.as_ls)
1162 si_shader_ls(sscreen, shader);
1163 else if (shader->key.as_es)
1164 si_shader_es(sscreen, shader);
1165 else
1166 si_shader_vs(sscreen, shader, NULL);
1167 break;
1168 case PIPE_SHADER_TESS_CTRL:
1169 si_shader_hs(sscreen, shader);
1170 break;
1171 case PIPE_SHADER_TESS_EVAL:
1172 if (shader->key.as_es)
1173 si_shader_es(sscreen, shader);
1174 else
1175 si_shader_vs(sscreen, shader, NULL);
1176 break;
1177 case PIPE_SHADER_GEOMETRY:
1178 si_shader_gs(sscreen, shader);
1179 break;
1180 case PIPE_SHADER_FRAGMENT:
1181 si_shader_ps(shader);
1182 break;
1183 default:
1184 assert(0);
1185 }
1186 }
1187
1188 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1189 {
1190 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1191 if (sctx->queued.named.dsa)
1192 return sctx->queued.named.dsa->alpha_func;
1193
1194 return PIPE_FUNC_ALWAYS;
1195 }
1196
1197 static void si_shader_selector_key_vs(struct si_context *sctx,
1198 struct si_shader_selector *vs,
1199 struct si_shader_key *key,
1200 struct si_vs_prolog_bits *prolog_key)
1201 {
1202 if (!sctx->vertex_elements)
1203 return;
1204
1205 prolog_key->instance_divisor_is_one =
1206 sctx->vertex_elements->instance_divisor_is_one;
1207 prolog_key->instance_divisor_is_fetched =
1208 sctx->vertex_elements->instance_divisor_is_fetched;
1209
1210 /* Prefer a monolithic shader to allow scheduling divisions around
1211 * VBO loads. */
1212 if (prolog_key->instance_divisor_is_fetched)
1213 key->opt.prefer_mono = 1;
1214
1215 unsigned count = MIN2(vs->info.num_inputs,
1216 sctx->vertex_elements->count);
1217 memcpy(key->mono.vs_fix_fetch, sctx->vertex_elements->fix_fetch, count);
1218 }
1219
1220 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1221 struct si_shader_selector *vs,
1222 struct si_shader_key *key)
1223 {
1224 struct si_shader_selector *ps = sctx->ps_shader.cso;
1225
1226 key->opt.clip_disable =
1227 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1228 (vs->info.clipdist_writemask ||
1229 vs->info.writes_clipvertex) &&
1230 !vs->info.culldist_writemask;
1231
1232 /* Find out if PS is disabled. */
1233 bool ps_disabled = true;
1234 if (ps) {
1235 const struct si_state_blend *blend = sctx->queued.named.blend;
1236 bool alpha_to_coverage = blend && blend->alpha_to_coverage;
1237 bool ps_modifies_zs = ps->info.uses_kill ||
1238 ps->info.writes_z ||
1239 ps->info.writes_stencil ||
1240 ps->info.writes_samplemask ||
1241 alpha_to_coverage ||
1242 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1243 unsigned ps_colormask = si_get_total_colormask(sctx);
1244
1245 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1246 (!ps_colormask &&
1247 !ps_modifies_zs &&
1248 !ps->info.writes_memory);
1249 }
1250
1251 /* Find out which VS outputs aren't used by the PS. */
1252 uint64_t outputs_written = vs->outputs_written_before_ps;
1253 uint64_t inputs_read = 0;
1254
1255 /* Ignore outputs that are not passed from VS to PS. */
1256 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1257 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1258 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1259
1260 if (!ps_disabled) {
1261 inputs_read = ps->inputs_read;
1262 }
1263
1264 uint64_t linked = outputs_written & inputs_read;
1265
1266 key->opt.kill_outputs = ~linked & outputs_written;
1267 }
1268
1269 /* Compute the key for the hw shader variant */
1270 static inline void si_shader_selector_key(struct pipe_context *ctx,
1271 struct si_shader_selector *sel,
1272 struct si_shader_key *key)
1273 {
1274 struct si_context *sctx = (struct si_context *)ctx;
1275
1276 memset(key, 0, sizeof(*key));
1277
1278 switch (sel->type) {
1279 case PIPE_SHADER_VERTEX:
1280 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1281
1282 if (sctx->tes_shader.cso)
1283 key->as_ls = 1;
1284 else if (sctx->gs_shader.cso)
1285 key->as_es = 1;
1286 else {
1287 si_shader_selector_key_hw_vs(sctx, sel, key);
1288
1289 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1290 key->mono.u.vs_export_prim_id = 1;
1291 }
1292 break;
1293 case PIPE_SHADER_TESS_CTRL:
1294 if (sctx->chip_class >= GFX9) {
1295 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1296 key, &key->part.tcs.ls_prolog);
1297 key->part.tcs.ls = sctx->vs_shader.cso;
1298
1299 /* When the LS VGPR fix is needed, monolithic shaders
1300 * can:
1301 * - avoid initializing EXEC in both the LS prolog
1302 * and the LS main part when !vs_needs_prolog
1303 * - remove the fixup for unused input VGPRs
1304 */
1305 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1306
1307 /* The LS output / HS input layout can be communicated
1308 * directly instead of via user SGPRs for merged LS-HS.
1309 * The LS VGPR fix prefers this too.
1310 */
1311 key->opt.prefer_mono = 1;
1312 }
1313
1314 key->part.tcs.epilog.prim_mode =
1315 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1316 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1317 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1318 key->part.tcs.epilog.tes_reads_tess_factors =
1319 sctx->tes_shader.cso->info.reads_tess_factors;
1320
1321 if (sel == sctx->fixed_func_tcs_shader.cso)
1322 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1323 break;
1324 case PIPE_SHADER_TESS_EVAL:
1325 if (sctx->gs_shader.cso)
1326 key->as_es = 1;
1327 else {
1328 si_shader_selector_key_hw_vs(sctx, sel, key);
1329
1330 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1331 key->mono.u.vs_export_prim_id = 1;
1332 }
1333 break;
1334 case PIPE_SHADER_GEOMETRY:
1335 if (sctx->chip_class >= GFX9) {
1336 if (sctx->tes_shader.cso) {
1337 key->part.gs.es = sctx->tes_shader.cso;
1338 } else {
1339 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1340 key, &key->part.gs.vs_prolog);
1341 key->part.gs.es = sctx->vs_shader.cso;
1342 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1343 }
1344
1345 /* Merged ES-GS can have unbalanced wave usage.
1346 *
1347 * ES threads are per-vertex, while GS threads are
1348 * per-primitive. So without any amplification, there
1349 * are fewer GS threads than ES threads, which can result
1350 * in empty (no-op) GS waves. With too much amplification,
1351 * there are more GS threads than ES threads, which
1352 * can result in empty (no-op) ES waves.
1353 *
1354 * Non-monolithic shaders are implemented by setting EXEC
1355 * at the beginning of shader parts, and don't jump to
1356 * the end if EXEC is 0.
1357 *
1358 * Monolithic shaders use conditional blocks, so they can
1359 * jump and skip empty waves of ES or GS. So set this to
1360 * always use optimized variants, which are monolithic.
1361 */
1362 key->opt.prefer_mono = 1;
1363 }
1364 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1365 break;
1366 case PIPE_SHADER_FRAGMENT: {
1367 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1368 struct si_state_blend *blend = sctx->queued.named.blend;
1369
1370 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1371 sel->info.colors_written == 0x1)
1372 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1373
1374 if (blend) {
1375 /* Select the shader color format based on whether
1376 * blending or alpha are needed.
1377 */
1378 key->part.ps.epilog.spi_shader_col_format =
1379 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1380 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1381 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1382 sctx->framebuffer.spi_shader_col_format_blend) |
1383 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1384 sctx->framebuffer.spi_shader_col_format_alpha) |
1385 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1386 sctx->framebuffer.spi_shader_col_format);
1387 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1388
1389 /* The output for dual source blending should have
1390 * the same format as the first output.
1391 */
1392 if (blend->dual_src_blend)
1393 key->part.ps.epilog.spi_shader_col_format |=
1394 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1395 } else
1396 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1397
1398 /* If alpha-to-coverage is enabled, we have to export alpha
1399 * even if there is no color buffer.
1400 */
1401 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1402 blend && blend->alpha_to_coverage)
1403 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1404
1405 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1406 * to the range supported by the type if a channel has less
1407 * than 16 bits and the export format is 16_ABGR.
1408 */
1409 if (sctx->chip_class <= CIK && sctx->family != CHIP_HAWAII) {
1410 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1411 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1412 }
1413
1414 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1415 if (!key->part.ps.epilog.last_cbuf) {
1416 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1417 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1418 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1419 }
1420
1421 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1422 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1423
1424 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1425 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1426
1427 if (sctx->queued.named.blend) {
1428 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1429 rs->multisample_enable;
1430 }
1431
1432 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1433 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1434 (is_line && rs->line_smooth)) &&
1435 sctx->framebuffer.nr_samples <= 1;
1436 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1437
1438 if (sctx->ps_iter_samples > 1 &&
1439 sel->info.reads_samplemask) {
1440 key->part.ps.prolog.samplemask_log_ps_iter =
1441 util_logbase2(sctx->ps_iter_samples);
1442 }
1443
1444 if (rs->force_persample_interp &&
1445 rs->multisample_enable &&
1446 sctx->framebuffer.nr_samples > 1 &&
1447 sctx->ps_iter_samples > 1) {
1448 key->part.ps.prolog.force_persp_sample_interp =
1449 sel->info.uses_persp_center ||
1450 sel->info.uses_persp_centroid;
1451
1452 key->part.ps.prolog.force_linear_sample_interp =
1453 sel->info.uses_linear_center ||
1454 sel->info.uses_linear_centroid;
1455 } else if (rs->multisample_enable &&
1456 sctx->framebuffer.nr_samples > 1) {
1457 key->part.ps.prolog.bc_optimize_for_persp =
1458 sel->info.uses_persp_center &&
1459 sel->info.uses_persp_centroid;
1460 key->part.ps.prolog.bc_optimize_for_linear =
1461 sel->info.uses_linear_center &&
1462 sel->info.uses_linear_centroid;
1463 } else {
1464 /* Make sure SPI doesn't compute more than 1 pair
1465 * of (i,j), which is the optimization here. */
1466 key->part.ps.prolog.force_persp_center_interp =
1467 sel->info.uses_persp_center +
1468 sel->info.uses_persp_centroid +
1469 sel->info.uses_persp_sample > 1;
1470
1471 key->part.ps.prolog.force_linear_center_interp =
1472 sel->info.uses_linear_center +
1473 sel->info.uses_linear_centroid +
1474 sel->info.uses_linear_sample > 1;
1475
1476 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
1477 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1478 }
1479
1480 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1481
1482 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1483 if (sctx->ps_uses_fbfetch) {
1484 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
1485 struct pipe_resource *tex = cb0->texture;
1486
1487 /* 1D textures are allocated and used as 2D on GFX9. */
1488 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
1489 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
1490 (tex->target == PIPE_TEXTURE_1D ||
1491 tex->target == PIPE_TEXTURE_1D_ARRAY);
1492 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
1493 tex->target == PIPE_TEXTURE_2D_ARRAY ||
1494 tex->target == PIPE_TEXTURE_CUBE ||
1495 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
1496 tex->target == PIPE_TEXTURE_3D;
1497 }
1498 break;
1499 }
1500 default:
1501 assert(0);
1502 }
1503
1504 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
1505 memset(&key->opt, 0, sizeof(key->opt));
1506 }
1507
1508 static void si_build_shader_variant(struct si_shader *shader,
1509 int thread_index,
1510 bool low_priority)
1511 {
1512 struct si_shader_selector *sel = shader->selector;
1513 struct si_screen *sscreen = sel->screen;
1514 struct si_compiler *compiler;
1515 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1516 int r;
1517
1518 if (thread_index >= 0) {
1519 if (low_priority) {
1520 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
1521 compiler = &sscreen->compiler_lowp[thread_index];
1522 } else {
1523 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
1524 compiler = &sscreen->compiler[thread_index];
1525 }
1526 if (!debug->async)
1527 debug = NULL;
1528 } else {
1529 assert(!low_priority);
1530 compiler = shader->compiler_ctx_state.compiler;
1531 }
1532
1533 r = si_shader_create(sscreen, compiler, shader, debug);
1534 if (unlikely(r)) {
1535 PRINT_ERR("Failed to build shader variant (type=%u) %d\n",
1536 sel->type, r);
1537 shader->compilation_failed = true;
1538 return;
1539 }
1540
1541 if (shader->compiler_ctx_state.is_debug_context) {
1542 FILE *f = open_memstream(&shader->shader_log,
1543 &shader->shader_log_size);
1544 if (f) {
1545 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1546 fclose(f);
1547 }
1548 }
1549
1550 si_shader_init_pm4_state(sscreen, shader);
1551 }
1552
1553 static void si_build_shader_variant_low_priority(void *job, int thread_index)
1554 {
1555 struct si_shader *shader = (struct si_shader *)job;
1556
1557 assert(thread_index >= 0);
1558
1559 si_build_shader_variant(shader, thread_index, true);
1560 }
1561
1562 static const struct si_shader_key zeroed;
1563
1564 static bool si_check_missing_main_part(struct si_screen *sscreen,
1565 struct si_shader_selector *sel,
1566 struct si_compiler_ctx_state *compiler_state,
1567 struct si_shader_key *key)
1568 {
1569 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1570
1571 if (!*mainp) {
1572 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1573
1574 if (!main_part)
1575 return false;
1576
1577 /* We can leave the fence as permanently signaled because the
1578 * main part becomes visible globally only after it has been
1579 * compiled. */
1580 util_queue_fence_init(&main_part->ready);
1581
1582 main_part->selector = sel;
1583 main_part->key.as_es = key->as_es;
1584 main_part->key.as_ls = key->as_ls;
1585 main_part->is_monolithic = false;
1586
1587 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
1588 main_part, &compiler_state->debug) != 0) {
1589 FREE(main_part);
1590 return false;
1591 }
1592 *mainp = main_part;
1593 }
1594 return true;
1595 }
1596
1597 /* Select the hw shader variant depending on the current state. */
1598 static int si_shader_select_with_key(struct si_screen *sscreen,
1599 struct si_shader_ctx_state *state,
1600 struct si_compiler_ctx_state *compiler_state,
1601 struct si_shader_key *key,
1602 int thread_index)
1603 {
1604 struct si_shader_selector *sel = state->cso;
1605 struct si_shader_selector *previous_stage_sel = NULL;
1606 struct si_shader *current = state->current;
1607 struct si_shader *iter, *shader = NULL;
1608
1609 again:
1610 /* Check if we don't need to change anything.
1611 * This path is also used for most shaders that don't need multiple
1612 * variants, it will cost just a computation of the key and this
1613 * test. */
1614 if (likely(current &&
1615 memcmp(&current->key, key, sizeof(*key)) == 0)) {
1616 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
1617 if (current->is_optimized) {
1618 memset(&key->opt, 0, sizeof(key->opt));
1619 goto current_not_ready;
1620 }
1621
1622 util_queue_fence_wait(&current->ready);
1623 }
1624
1625 return current->compilation_failed ? -1 : 0;
1626 }
1627 current_not_ready:
1628
1629 /* This must be done before the mutex is locked, because async GS
1630 * compilation calls this function too, and therefore must enter
1631 * the mutex first.
1632 *
1633 * Only wait if we are in a draw call. Don't wait if we are
1634 * in a compiler thread.
1635 */
1636 if (thread_index < 0)
1637 util_queue_fence_wait(&sel->ready);
1638
1639 mtx_lock(&sel->mutex);
1640
1641 /* Find the shader variant. */
1642 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1643 /* Don't check the "current" shader. We checked it above. */
1644 if (current != iter &&
1645 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1646 mtx_unlock(&sel->mutex);
1647
1648 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
1649 /* If it's an optimized shader and its compilation has
1650 * been started but isn't done, use the unoptimized
1651 * shader so as not to cause a stall due to compilation.
1652 */
1653 if (iter->is_optimized) {
1654 memset(&key->opt, 0, sizeof(key->opt));
1655 goto again;
1656 }
1657
1658 util_queue_fence_wait(&iter->ready);
1659 }
1660
1661 if (iter->compilation_failed) {
1662 return -1; /* skip the draw call */
1663 }
1664
1665 state->current = iter;
1666 return 0;
1667 }
1668 }
1669
1670 /* Build a new shader. */
1671 shader = CALLOC_STRUCT(si_shader);
1672 if (!shader) {
1673 mtx_unlock(&sel->mutex);
1674 return -ENOMEM;
1675 }
1676
1677 util_queue_fence_init(&shader->ready);
1678
1679 shader->selector = sel;
1680 shader->key = *key;
1681 shader->compiler_ctx_state = *compiler_state;
1682
1683 /* If this is a merged shader, get the first shader's selector. */
1684 if (sscreen->info.chip_class >= GFX9) {
1685 if (sel->type == PIPE_SHADER_TESS_CTRL)
1686 previous_stage_sel = key->part.tcs.ls;
1687 else if (sel->type == PIPE_SHADER_GEOMETRY)
1688 previous_stage_sel = key->part.gs.es;
1689
1690 /* We need to wait for the previous shader. */
1691 if (previous_stage_sel && thread_index < 0)
1692 util_queue_fence_wait(&previous_stage_sel->ready);
1693 }
1694
1695 /* Compile the main shader part if it doesn't exist. This can happen
1696 * if the initial guess was wrong. */
1697 bool is_pure_monolithic =
1698 sscreen->use_monolithic_shaders ||
1699 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1700
1701 if (!is_pure_monolithic) {
1702 bool ok;
1703
1704 /* Make sure the main shader part is present. This is needed
1705 * for shaders that can be compiled as VS, LS, or ES, and only
1706 * one of them is compiled at creation.
1707 *
1708 * For merged shaders, check that the starting shader's main
1709 * part is present.
1710 */
1711 if (previous_stage_sel) {
1712 struct si_shader_key shader1_key = zeroed;
1713
1714 if (sel->type == PIPE_SHADER_TESS_CTRL)
1715 shader1_key.as_ls = 1;
1716 else if (sel->type == PIPE_SHADER_GEOMETRY)
1717 shader1_key.as_es = 1;
1718 else
1719 assert(0);
1720
1721 mtx_lock(&previous_stage_sel->mutex);
1722 ok = si_check_missing_main_part(sscreen,
1723 previous_stage_sel,
1724 compiler_state, &shader1_key);
1725 mtx_unlock(&previous_stage_sel->mutex);
1726 } else {
1727 ok = si_check_missing_main_part(sscreen, sel,
1728 compiler_state, key);
1729 }
1730 if (!ok) {
1731 FREE(shader);
1732 mtx_unlock(&sel->mutex);
1733 return -ENOMEM; /* skip the draw call */
1734 }
1735 }
1736
1737 /* Keep the reference to the 1st shader of merged shaders, so that
1738 * Gallium can't destroy it before we destroy the 2nd shader.
1739 *
1740 * Set sctx = NULL, because it's unused if we're not releasing
1741 * the shader, and we don't have any sctx here.
1742 */
1743 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
1744 previous_stage_sel);
1745
1746 /* Monolithic-only shaders don't make a distinction between optimized
1747 * and unoptimized. */
1748 shader->is_monolithic =
1749 is_pure_monolithic ||
1750 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1751
1752 shader->is_optimized =
1753 !is_pure_monolithic &&
1754 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1755
1756 /* If it's an optimized shader, compile it asynchronously. */
1757 if (shader->is_optimized &&
1758 !is_pure_monolithic &&
1759 thread_index < 0) {
1760 /* Compile it asynchronously. */
1761 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
1762 shader, &shader->ready,
1763 si_build_shader_variant_low_priority, NULL);
1764
1765 /* Add only after the ready fence was reset, to guard against a
1766 * race with si_bind_XX_shader. */
1767 if (!sel->last_variant) {
1768 sel->first_variant = shader;
1769 sel->last_variant = shader;
1770 } else {
1771 sel->last_variant->next_variant = shader;
1772 sel->last_variant = shader;
1773 }
1774
1775 /* Use the default (unoptimized) shader for now. */
1776 memset(&key->opt, 0, sizeof(key->opt));
1777 mtx_unlock(&sel->mutex);
1778 goto again;
1779 }
1780
1781 /* Reset the fence before adding to the variant list. */
1782 util_queue_fence_reset(&shader->ready);
1783
1784 if (!sel->last_variant) {
1785 sel->first_variant = shader;
1786 sel->last_variant = shader;
1787 } else {
1788 sel->last_variant->next_variant = shader;
1789 sel->last_variant = shader;
1790 }
1791
1792 mtx_unlock(&sel->mutex);
1793
1794 assert(!shader->is_optimized);
1795 si_build_shader_variant(shader, thread_index, false);
1796
1797 util_queue_fence_signal(&shader->ready);
1798
1799 if (!shader->compilation_failed)
1800 state->current = shader;
1801
1802 return shader->compilation_failed ? -1 : 0;
1803 }
1804
1805 static int si_shader_select(struct pipe_context *ctx,
1806 struct si_shader_ctx_state *state,
1807 struct si_compiler_ctx_state *compiler_state)
1808 {
1809 struct si_context *sctx = (struct si_context *)ctx;
1810 struct si_shader_key key;
1811
1812 si_shader_selector_key(ctx, state->cso, &key);
1813 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1814 &key, -1);
1815 }
1816
1817 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1818 bool streamout,
1819 struct si_shader_key *key)
1820 {
1821 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1822
1823 switch (info->processor) {
1824 case PIPE_SHADER_VERTEX:
1825 switch (next_shader) {
1826 case PIPE_SHADER_GEOMETRY:
1827 key->as_es = 1;
1828 break;
1829 case PIPE_SHADER_TESS_CTRL:
1830 case PIPE_SHADER_TESS_EVAL:
1831 key->as_ls = 1;
1832 break;
1833 default:
1834 /* If POSITION isn't written, it can only be a HW VS
1835 * if streamout is used. If streamout isn't used,
1836 * assume that it's a HW LS. (the next shader is TCS)
1837 * This heuristic is needed for separate shader objects.
1838 */
1839 if (!info->writes_position && !streamout)
1840 key->as_ls = 1;
1841 }
1842 break;
1843
1844 case PIPE_SHADER_TESS_EVAL:
1845 if (next_shader == PIPE_SHADER_GEOMETRY ||
1846 !info->writes_position)
1847 key->as_es = 1;
1848 break;
1849 }
1850 }
1851
1852 /**
1853 * Compile the main shader part or the monolithic shader as part of
1854 * si_shader_selector initialization. Since it can be done asynchronously,
1855 * there is no way to report compile failures to applications.
1856 */
1857 static void si_init_shader_selector_async(void *job, int thread_index)
1858 {
1859 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1860 struct si_screen *sscreen = sel->screen;
1861 struct si_compiler *compiler;
1862 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
1863
1864 assert(!debug->debug_message || debug->async);
1865 assert(thread_index >= 0);
1866 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
1867 compiler = &sscreen->compiler[thread_index];
1868
1869 /* Compile the main shader part for use with a prolog and/or epilog.
1870 * If this fails, the driver will try to compile a monolithic shader
1871 * on demand.
1872 */
1873 if (!sscreen->use_monolithic_shaders) {
1874 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1875 void *ir_binary = NULL;
1876
1877 if (!shader) {
1878 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1879 return;
1880 }
1881
1882 /* We can leave the fence signaled because use of the default
1883 * main part is guarded by the selector's ready fence. */
1884 util_queue_fence_init(&shader->ready);
1885
1886 shader->selector = sel;
1887 shader->is_monolithic = false;
1888 si_parse_next_shader_property(&sel->info,
1889 sel->so.num_outputs != 0,
1890 &shader->key);
1891
1892 if (sel->tokens || sel->nir)
1893 ir_binary = si_get_ir_binary(sel);
1894
1895 /* Try to load the shader from the shader cache. */
1896 mtx_lock(&sscreen->shader_cache_mutex);
1897
1898 if (ir_binary &&
1899 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
1900 mtx_unlock(&sscreen->shader_cache_mutex);
1901 si_shader_dump_stats_for_shader_db(shader, debug);
1902 } else {
1903 mtx_unlock(&sscreen->shader_cache_mutex);
1904
1905 /* Compile the shader if it hasn't been loaded from the cache. */
1906 if (si_compile_tgsi_shader(sscreen, compiler, shader,
1907 debug) != 0) {
1908 FREE(shader);
1909 FREE(ir_binary);
1910 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1911 return;
1912 }
1913
1914 if (ir_binary) {
1915 mtx_lock(&sscreen->shader_cache_mutex);
1916 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
1917 FREE(ir_binary);
1918 mtx_unlock(&sscreen->shader_cache_mutex);
1919 }
1920 }
1921
1922 *si_get_main_shader_part(sel, &shader->key) = shader;
1923
1924 /* Unset "outputs_written" flags for outputs converted to
1925 * DEFAULT_VAL, so that later inter-shader optimizations don't
1926 * try to eliminate outputs that don't exist in the final
1927 * shader.
1928 *
1929 * This is only done if non-monolithic shaders are enabled.
1930 */
1931 if ((sel->type == PIPE_SHADER_VERTEX ||
1932 sel->type == PIPE_SHADER_TESS_EVAL) &&
1933 !shader->key.as_ls &&
1934 !shader->key.as_es) {
1935 unsigned i;
1936
1937 for (i = 0; i < sel->info.num_outputs; i++) {
1938 unsigned offset = shader->info.vs_output_param_offset[i];
1939
1940 if (offset <= AC_EXP_PARAM_OFFSET_31)
1941 continue;
1942
1943 unsigned name = sel->info.output_semantic_name[i];
1944 unsigned index = sel->info.output_semantic_index[i];
1945 unsigned id;
1946
1947 switch (name) {
1948 case TGSI_SEMANTIC_GENERIC:
1949 /* don't process indices the function can't handle */
1950 if (index >= SI_MAX_IO_GENERIC)
1951 break;
1952 /* fall through */
1953 default:
1954 id = si_shader_io_get_unique_index(name, index, true);
1955 sel->outputs_written_before_ps &= ~(1ull << id);
1956 break;
1957 case TGSI_SEMANTIC_POSITION: /* ignore these */
1958 case TGSI_SEMANTIC_PSIZE:
1959 case TGSI_SEMANTIC_CLIPVERTEX:
1960 case TGSI_SEMANTIC_EDGEFLAG:
1961 break;
1962 }
1963 }
1964 }
1965 }
1966
1967 /* The GS copy shader is always pre-compiled. */
1968 if (sel->type == PIPE_SHADER_GEOMETRY) {
1969 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
1970 if (!sel->gs_copy_shader) {
1971 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
1972 return;
1973 }
1974
1975 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
1976 }
1977 }
1978
1979 /* Return descriptor slot usage masks from the given shader info. */
1980 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
1981 uint32_t *const_and_shader_buffers,
1982 uint64_t *samplers_and_images)
1983 {
1984 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
1985
1986 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
1987 num_constbufs = util_last_bit(info->const_buffers_declared);
1988 /* two 8-byte images share one 16-byte slot */
1989 num_images = align(util_last_bit(info->images_declared), 2);
1990 num_samplers = util_last_bit(info->samplers_declared);
1991
1992 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
1993 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
1994 *const_and_shader_buffers =
1995 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
1996
1997 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
1998 start = si_get_image_slot(num_images - 1) / 2;
1999 *samplers_and_images =
2000 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2001 }
2002
2003 static void *si_create_shader_selector(struct pipe_context *ctx,
2004 const struct pipe_shader_state *state)
2005 {
2006 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2007 struct si_context *sctx = (struct si_context*)ctx;
2008 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2009 int i;
2010
2011 if (!sel)
2012 return NULL;
2013
2014 pipe_reference_init(&sel->reference, 1);
2015 sel->screen = sscreen;
2016 sel->compiler_ctx_state.debug = sctx->debug;
2017 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2018
2019 sel->so = state->stream_output;
2020
2021 if (state->type == PIPE_SHADER_IR_TGSI) {
2022 sel->tokens = tgsi_dup_tokens(state->tokens);
2023 if (!sel->tokens) {
2024 FREE(sel);
2025 return NULL;
2026 }
2027
2028 tgsi_scan_shader(state->tokens, &sel->info);
2029 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2030 } else {
2031 assert(state->type == PIPE_SHADER_IR_NIR);
2032
2033 sel->nir = state->ir.nir;
2034
2035 si_nir_scan_shader(sel->nir, &sel->info);
2036 si_nir_scan_tess_ctrl(sel->nir, &sel->info, &sel->tcs_info);
2037
2038 si_lower_nir(sel);
2039 }
2040
2041 sel->type = sel->info.processor;
2042 p_atomic_inc(&sscreen->num_shaders_created);
2043 si_get_active_slot_masks(&sel->info,
2044 &sel->active_const_and_shader_buffers,
2045 &sel->active_samplers_and_images);
2046
2047 /* Record which streamout buffers are enabled. */
2048 for (i = 0; i < sel->so.num_outputs; i++) {
2049 sel->enabled_streamout_buffer_mask |=
2050 (1 << sel->so.output[i].output_buffer) <<
2051 (sel->so.output[i].stream * 4);
2052 }
2053
2054 /* The prolog is a no-op if there are no inputs. */
2055 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2056 sel->info.num_inputs &&
2057 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2058
2059 sel->force_correct_derivs_after_kill =
2060 sel->type == PIPE_SHADER_FRAGMENT &&
2061 sel->info.uses_derivatives &&
2062 sel->info.uses_kill &&
2063 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2064
2065 /* Set which opcode uses which (i,j) pair. */
2066 if (sel->info.uses_persp_opcode_interp_centroid)
2067 sel->info.uses_persp_centroid = true;
2068
2069 if (sel->info.uses_linear_opcode_interp_centroid)
2070 sel->info.uses_linear_centroid = true;
2071
2072 if (sel->info.uses_persp_opcode_interp_offset ||
2073 sel->info.uses_persp_opcode_interp_sample)
2074 sel->info.uses_persp_center = true;
2075
2076 if (sel->info.uses_linear_opcode_interp_offset ||
2077 sel->info.uses_linear_opcode_interp_sample)
2078 sel->info.uses_linear_center = true;
2079
2080 switch (sel->type) {
2081 case PIPE_SHADER_GEOMETRY:
2082 sel->gs_output_prim =
2083 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2084 sel->gs_max_out_vertices =
2085 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2086 sel->gs_num_invocations =
2087 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2088 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2089 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2090 sel->gs_max_out_vertices;
2091
2092 sel->max_gs_stream = 0;
2093 for (i = 0; i < sel->so.num_outputs; i++)
2094 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2095 sel->so.output[i].stream);
2096
2097 sel->gs_input_verts_per_prim =
2098 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2099 break;
2100
2101 case PIPE_SHADER_TESS_CTRL:
2102 /* Always reserve space for these. */
2103 sel->patch_outputs_written |=
2104 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2105 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2106 /* fall through */
2107 case PIPE_SHADER_VERTEX:
2108 case PIPE_SHADER_TESS_EVAL:
2109 for (i = 0; i < sel->info.num_outputs; i++) {
2110 unsigned name = sel->info.output_semantic_name[i];
2111 unsigned index = sel->info.output_semantic_index[i];
2112
2113 switch (name) {
2114 case TGSI_SEMANTIC_TESSINNER:
2115 case TGSI_SEMANTIC_TESSOUTER:
2116 case TGSI_SEMANTIC_PATCH:
2117 sel->patch_outputs_written |=
2118 1ull << si_shader_io_get_unique_index_patch(name, index);
2119 break;
2120
2121 case TGSI_SEMANTIC_GENERIC:
2122 /* don't process indices the function can't handle */
2123 if (index >= SI_MAX_IO_GENERIC)
2124 break;
2125 /* fall through */
2126 default:
2127 sel->outputs_written |=
2128 1ull << si_shader_io_get_unique_index(name, index, false);
2129 sel->outputs_written_before_ps |=
2130 1ull << si_shader_io_get_unique_index(name, index, true);
2131 break;
2132 case TGSI_SEMANTIC_EDGEFLAG:
2133 break;
2134 }
2135 }
2136 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2137
2138 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2139 * conflicts, i.e. each vertex will start at a different bank.
2140 */
2141 if (sctx->chip_class >= GFX9)
2142 sel->esgs_itemsize += 4;
2143
2144 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2145 break;
2146
2147 case PIPE_SHADER_FRAGMENT:
2148 for (i = 0; i < sel->info.num_inputs; i++) {
2149 unsigned name = sel->info.input_semantic_name[i];
2150 unsigned index = sel->info.input_semantic_index[i];
2151
2152 switch (name) {
2153 case TGSI_SEMANTIC_GENERIC:
2154 /* don't process indices the function can't handle */
2155 if (index >= SI_MAX_IO_GENERIC)
2156 break;
2157 /* fall through */
2158 default:
2159 sel->inputs_read |=
2160 1ull << si_shader_io_get_unique_index(name, index, true);
2161 break;
2162 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2163 break;
2164 }
2165 }
2166
2167 for (i = 0; i < 8; i++)
2168 if (sel->info.colors_written & (1 << i))
2169 sel->colors_written_4bit |= 0xf << (4 * i);
2170
2171 for (i = 0; i < sel->info.num_inputs; i++) {
2172 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2173 int index = sel->info.input_semantic_index[i];
2174 sel->color_attr_index[index] = i;
2175 }
2176 }
2177 break;
2178 }
2179
2180 /* PA_CL_VS_OUT_CNTL */
2181 bool misc_vec_ena =
2182 sel->info.writes_psize || sel->info.writes_edgeflag ||
2183 sel->info.writes_layer || sel->info.writes_viewport_index;
2184 sel->pa_cl_vs_out_cntl =
2185 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2186 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2187 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2188 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2189 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2190 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2191 sel->clipdist_mask = sel->info.writes_clipvertex ?
2192 SIX_BITS : sel->info.clipdist_writemask;
2193 sel->culldist_mask = sel->info.culldist_writemask <<
2194 sel->info.num_written_clipdistance;
2195
2196 /* DB_SHADER_CONTROL */
2197 sel->db_shader_control =
2198 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2199 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2200 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2201 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2202
2203 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2204 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2205 sel->db_shader_control |=
2206 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2207 break;
2208 case TGSI_FS_DEPTH_LAYOUT_LESS:
2209 sel->db_shader_control |=
2210 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2211 break;
2212 }
2213
2214 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2215 *
2216 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2217 * --|-----------|------------|------------|--------------------|-------------------|-------------
2218 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2219 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2220 * 2 | false | true | n/a | LateZ | 1 | 0
2221 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2222 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2223 *
2224 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2225 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2226 *
2227 * Don't use ReZ without profiling !!!
2228 *
2229 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2230 * shaders.
2231 */
2232 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2233 /* Cases 3, 4. */
2234 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2235 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2236 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2237 } else if (sel->info.writes_memory) {
2238 /* Case 2. */
2239 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2240 S_02880C_EXEC_ON_HIER_FAIL(1);
2241 } else {
2242 /* Case 1. */
2243 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2244 }
2245
2246 (void) mtx_init(&sel->mutex, mtx_plain);
2247 util_queue_fence_init(&sel->ready);
2248
2249 struct util_async_debug_callback async_debug;
2250 bool wait =
2251 (sctx->debug.debug_message && !sctx->debug.async) ||
2252 sctx->is_debug ||
2253 si_can_dump_shader(sscreen, sel->info.processor);
2254
2255 if (wait) {
2256 u_async_debug_init(&async_debug);
2257 sel->compiler_ctx_state.debug = async_debug.base;
2258 }
2259
2260 util_queue_add_job(&sscreen->shader_compiler_queue, sel,
2261 &sel->ready, si_init_shader_selector_async,
2262 NULL);
2263
2264 if (wait) {
2265 util_queue_fence_wait(&sel->ready);
2266 u_async_debug_drain(&async_debug, &sctx->debug);
2267 u_async_debug_cleanup(&async_debug);
2268 }
2269
2270 return sel;
2271 }
2272
2273 static void si_update_streamout_state(struct si_context *sctx)
2274 {
2275 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2276
2277 if (!shader_with_so)
2278 return;
2279
2280 sctx->streamout.enabled_stream_buffers_mask =
2281 shader_with_so->enabled_streamout_buffer_mask;
2282 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2283 }
2284
2285 static void si_update_clip_regs(struct si_context *sctx,
2286 struct si_shader_selector *old_hw_vs,
2287 struct si_shader *old_hw_vs_variant,
2288 struct si_shader_selector *next_hw_vs,
2289 struct si_shader *next_hw_vs_variant)
2290 {
2291 if (next_hw_vs &&
2292 (!old_hw_vs ||
2293 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2294 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2295 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2296 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2297 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2298 !old_hw_vs_variant ||
2299 !next_hw_vs_variant ||
2300 old_hw_vs_variant->key.opt.clip_disable !=
2301 next_hw_vs_variant->key.opt.clip_disable))
2302 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2303 }
2304
2305 static void si_update_common_shader_state(struct si_context *sctx)
2306 {
2307 sctx->uses_bindless_samplers =
2308 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2309 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2310 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2311 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2312 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2313 sctx->uses_bindless_images =
2314 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2315 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2316 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2317 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2318 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2319 sctx->do_update_shaders = true;
2320 }
2321
2322 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2323 {
2324 struct si_context *sctx = (struct si_context *)ctx;
2325 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2326 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2327 struct si_shader_selector *sel = state;
2328
2329 if (sctx->vs_shader.cso == sel)
2330 return;
2331
2332 sctx->vs_shader.cso = sel;
2333 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2334 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2335
2336 si_update_common_shader_state(sctx);
2337 si_update_vs_viewport_state(sctx);
2338 si_set_active_descriptors_for_shader(sctx, sel);
2339 si_update_streamout_state(sctx);
2340 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2341 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2342 }
2343
2344 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2345 {
2346 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2347 (sctx->tes_shader.cso &&
2348 sctx->tes_shader.cso->info.uses_primid) ||
2349 (sctx->tcs_shader.cso &&
2350 sctx->tcs_shader.cso->info.uses_primid) ||
2351 (sctx->gs_shader.cso &&
2352 sctx->gs_shader.cso->info.uses_primid) ||
2353 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2354 sctx->ps_shader.cso->info.uses_primid);
2355 }
2356
2357 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2358 {
2359 struct si_context *sctx = (struct si_context *)ctx;
2360 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2361 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2362 struct si_shader_selector *sel = state;
2363 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2364
2365 if (sctx->gs_shader.cso == sel)
2366 return;
2367
2368 sctx->gs_shader.cso = sel;
2369 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2370 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2371
2372 si_update_common_shader_state(sctx);
2373 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2374
2375 if (enable_changed) {
2376 si_shader_change_notify(sctx);
2377 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2378 si_update_tess_uses_prim_id(sctx);
2379 }
2380 si_update_vs_viewport_state(sctx);
2381 si_set_active_descriptors_for_shader(sctx, sel);
2382 si_update_streamout_state(sctx);
2383 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2384 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2385 }
2386
2387 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2388 {
2389 struct si_context *sctx = (struct si_context *)ctx;
2390 struct si_shader_selector *sel = state;
2391 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2392
2393 if (sctx->tcs_shader.cso == sel)
2394 return;
2395
2396 sctx->tcs_shader.cso = sel;
2397 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2398 si_update_tess_uses_prim_id(sctx);
2399
2400 si_update_common_shader_state(sctx);
2401
2402 if (enable_changed)
2403 sctx->last_tcs = NULL; /* invalidate derived tess state */
2404
2405 si_set_active_descriptors_for_shader(sctx, sel);
2406 }
2407
2408 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2409 {
2410 struct si_context *sctx = (struct si_context *)ctx;
2411 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2412 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2413 struct si_shader_selector *sel = state;
2414 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2415
2416 if (sctx->tes_shader.cso == sel)
2417 return;
2418
2419 sctx->tes_shader.cso = sel;
2420 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2421 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2422 si_update_tess_uses_prim_id(sctx);
2423
2424 si_update_common_shader_state(sctx);
2425 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2426
2427 if (enable_changed) {
2428 si_shader_change_notify(sctx);
2429 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2430 }
2431 si_update_vs_viewport_state(sctx);
2432 si_set_active_descriptors_for_shader(sctx, sel);
2433 si_update_streamout_state(sctx);
2434 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2435 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2436 }
2437
2438 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2439 {
2440 struct si_context *sctx = (struct si_context *)ctx;
2441 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
2442 struct si_shader_selector *sel = state;
2443
2444 /* skip if supplied shader is one already in use */
2445 if (old_sel == sel)
2446 return;
2447
2448 sctx->ps_shader.cso = sel;
2449 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2450
2451 si_update_common_shader_state(sctx);
2452 if (sel) {
2453 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2454 si_update_tess_uses_prim_id(sctx);
2455
2456 if (!old_sel ||
2457 old_sel->info.colors_written != sel->info.colors_written)
2458 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2459
2460 if (sctx->screen->has_out_of_order_rast &&
2461 (!old_sel ||
2462 old_sel->info.writes_memory != sel->info.writes_memory ||
2463 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
2464 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
2465 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2466 }
2467 si_set_active_descriptors_for_shader(sctx, sel);
2468 si_update_ps_colorbuf0_slot(sctx);
2469 }
2470
2471 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2472 {
2473 if (shader->is_optimized) {
2474 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
2475 &shader->ready);
2476 }
2477
2478 util_queue_fence_destroy(&shader->ready);
2479
2480 if (shader->pm4) {
2481 switch (shader->selector->type) {
2482 case PIPE_SHADER_VERTEX:
2483 if (shader->key.as_ls) {
2484 assert(sctx->chip_class <= VI);
2485 si_pm4_delete_state(sctx, ls, shader->pm4);
2486 } else if (shader->key.as_es) {
2487 assert(sctx->chip_class <= VI);
2488 si_pm4_delete_state(sctx, es, shader->pm4);
2489 } else {
2490 si_pm4_delete_state(sctx, vs, shader->pm4);
2491 }
2492 break;
2493 case PIPE_SHADER_TESS_CTRL:
2494 si_pm4_delete_state(sctx, hs, shader->pm4);
2495 break;
2496 case PIPE_SHADER_TESS_EVAL:
2497 if (shader->key.as_es) {
2498 assert(sctx->chip_class <= VI);
2499 si_pm4_delete_state(sctx, es, shader->pm4);
2500 } else {
2501 si_pm4_delete_state(sctx, vs, shader->pm4);
2502 }
2503 break;
2504 case PIPE_SHADER_GEOMETRY:
2505 if (shader->is_gs_copy_shader)
2506 si_pm4_delete_state(sctx, vs, shader->pm4);
2507 else
2508 si_pm4_delete_state(sctx, gs, shader->pm4);
2509 break;
2510 case PIPE_SHADER_FRAGMENT:
2511 si_pm4_delete_state(sctx, ps, shader->pm4);
2512 break;
2513 }
2514 }
2515
2516 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2517 si_shader_destroy(shader);
2518 free(shader);
2519 }
2520
2521 void si_destroy_shader_selector(struct si_context *sctx,
2522 struct si_shader_selector *sel)
2523 {
2524 struct si_shader *p = sel->first_variant, *c;
2525 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2526 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2527 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2528 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2529 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2530 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2531 };
2532
2533 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
2534
2535 if (current_shader[sel->type]->cso == sel) {
2536 current_shader[sel->type]->cso = NULL;
2537 current_shader[sel->type]->current = NULL;
2538 }
2539
2540 while (p) {
2541 c = p->next_variant;
2542 si_delete_shader(sctx, p);
2543 p = c;
2544 }
2545
2546 if (sel->main_shader_part)
2547 si_delete_shader(sctx, sel->main_shader_part);
2548 if (sel->main_shader_part_ls)
2549 si_delete_shader(sctx, sel->main_shader_part_ls);
2550 if (sel->main_shader_part_es)
2551 si_delete_shader(sctx, sel->main_shader_part_es);
2552 if (sel->gs_copy_shader)
2553 si_delete_shader(sctx, sel->gs_copy_shader);
2554
2555 util_queue_fence_destroy(&sel->ready);
2556 mtx_destroy(&sel->mutex);
2557 free(sel->tokens);
2558 ralloc_free(sel->nir);
2559 free(sel);
2560 }
2561
2562 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
2563 {
2564 struct si_context *sctx = (struct si_context *)ctx;
2565 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2566
2567 si_shader_selector_reference(sctx, &sel, NULL);
2568 }
2569
2570 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2571 struct si_shader *vs, unsigned name,
2572 unsigned index, unsigned interpolate)
2573 {
2574 struct tgsi_shader_info *vsinfo = &vs->selector->info;
2575 unsigned j, offset, ps_input_cntl = 0;
2576
2577 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2578 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
2579 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2580
2581 if (name == TGSI_SEMANTIC_PCOORD ||
2582 (name == TGSI_SEMANTIC_TEXCOORD &&
2583 sctx->sprite_coord_enable & (1 << index))) {
2584 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2585 }
2586
2587 for (j = 0; j < vsinfo->num_outputs; j++) {
2588 if (name == vsinfo->output_semantic_name[j] &&
2589 index == vsinfo->output_semantic_index[j]) {
2590 offset = vs->info.vs_output_param_offset[j];
2591
2592 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2593 /* The input is loaded from parameter memory. */
2594 ps_input_cntl |= S_028644_OFFSET(offset);
2595 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2596 if (offset == AC_EXP_PARAM_UNDEFINED) {
2597 /* This can happen with depth-only rendering. */
2598 offset = 0;
2599 } else {
2600 /* The input is a DEFAULT_VAL constant. */
2601 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2602 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2603 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2604 }
2605
2606 ps_input_cntl = S_028644_OFFSET(0x20) |
2607 S_028644_DEFAULT_VAL(offset);
2608 }
2609 break;
2610 }
2611 }
2612
2613 if (name == TGSI_SEMANTIC_PRIMID)
2614 /* PrimID is written after the last output. */
2615 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2616 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2617 /* No corresponding output found, load defaults into input.
2618 * Don't set any other bits.
2619 * (FLAT_SHADE=1 completely changes behavior) */
2620 ps_input_cntl = S_028644_OFFSET(0x20);
2621 /* D3D 9 behaviour. GL is undefined */
2622 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2623 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2624 }
2625 return ps_input_cntl;
2626 }
2627
2628 static void si_emit_spi_map(struct si_context *sctx)
2629 {
2630 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2631 struct si_shader *ps = sctx->ps_shader.current;
2632 struct si_shader *vs = si_get_vs_state(sctx);
2633 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2634 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2635
2636 if (!ps || !ps->selector->info.num_inputs)
2637 return;
2638
2639 num_interp = si_get_ps_num_interp(ps);
2640 assert(num_interp > 0);
2641 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
2642
2643 for (i = 0; i < psinfo->num_inputs; i++) {
2644 unsigned name = psinfo->input_semantic_name[i];
2645 unsigned index = psinfo->input_semantic_index[i];
2646 unsigned interpolate = psinfo->input_interpolate[i];
2647
2648 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
2649 interpolate));
2650 num_written++;
2651
2652 if (name == TGSI_SEMANTIC_COLOR) {
2653 assert(index < ARRAY_SIZE(bcol_interp));
2654 bcol_interp[index] = interpolate;
2655 }
2656 }
2657
2658 if (ps->key.part.ps.prolog.color_two_side) {
2659 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2660
2661 for (i = 0; i < 2; i++) {
2662 if (!(psinfo->colors_read & (0xf << (i * 4))))
2663 continue;
2664
2665 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
2666 i, bcol_interp[i]));
2667 num_written++;
2668 }
2669 }
2670 assert(num_interp == num_written);
2671 }
2672
2673 /**
2674 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2675 */
2676 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2677 {
2678 if (sctx->init_config_has_vgt_flush)
2679 return;
2680
2681 /* Done by Vulkan before VGT_FLUSH. */
2682 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2683 si_pm4_cmd_add(sctx->init_config,
2684 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2685 si_pm4_cmd_end(sctx->init_config, false);
2686
2687 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2688 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2689 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2690 si_pm4_cmd_end(sctx->init_config, false);
2691 sctx->init_config_has_vgt_flush = true;
2692 }
2693
2694 /* Initialize state related to ESGS / GSVS ring buffers */
2695 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2696 {
2697 struct si_shader_selector *es =
2698 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2699 struct si_shader_selector *gs = sctx->gs_shader.cso;
2700 struct si_pm4_state *pm4;
2701
2702 /* Chip constants. */
2703 unsigned num_se = sctx->screen->info.max_se;
2704 unsigned wave_size = 64;
2705 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2706 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2707 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2708 */
2709 unsigned gs_vertex_reuse = (sctx->chip_class >= VI ? 32 : 16) * num_se;
2710 unsigned alignment = 256 * num_se;
2711 /* The maximum size is 63.999 MB per SE. */
2712 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2713
2714 /* Calculate the minimum size. */
2715 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2716 wave_size, alignment);
2717
2718 /* These are recommended sizes, not minimum sizes. */
2719 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2720 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2721 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2722 gs->max_gsvs_emit_size;
2723
2724 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2725 esgs_ring_size = align(esgs_ring_size, alignment);
2726 gsvs_ring_size = align(gsvs_ring_size, alignment);
2727
2728 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2729 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2730
2731 /* Some rings don't have to be allocated if shaders don't use them.
2732 * (e.g. no varyings between ES and GS or GS and VS)
2733 *
2734 * GFX9 doesn't have the ESGS ring.
2735 */
2736 bool update_esgs = sctx->chip_class <= VI &&
2737 esgs_ring_size &&
2738 (!sctx->esgs_ring ||
2739 sctx->esgs_ring->width0 < esgs_ring_size);
2740 bool update_gsvs = gsvs_ring_size &&
2741 (!sctx->gsvs_ring ||
2742 sctx->gsvs_ring->width0 < gsvs_ring_size);
2743
2744 if (!update_esgs && !update_gsvs)
2745 return true;
2746
2747 if (update_esgs) {
2748 pipe_resource_reference(&sctx->esgs_ring, NULL);
2749 sctx->esgs_ring =
2750 pipe_aligned_buffer_create(sctx->b.screen,
2751 SI_RESOURCE_FLAG_UNMAPPABLE,
2752 PIPE_USAGE_DEFAULT,
2753 esgs_ring_size, alignment);
2754 if (!sctx->esgs_ring)
2755 return false;
2756 }
2757
2758 if (update_gsvs) {
2759 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2760 sctx->gsvs_ring =
2761 pipe_aligned_buffer_create(sctx->b.screen,
2762 SI_RESOURCE_FLAG_UNMAPPABLE,
2763 PIPE_USAGE_DEFAULT,
2764 gsvs_ring_size, alignment);
2765 if (!sctx->gsvs_ring)
2766 return false;
2767 }
2768
2769 /* Create the "init_config_gs_rings" state. */
2770 pm4 = CALLOC_STRUCT(si_pm4_state);
2771 if (!pm4)
2772 return false;
2773
2774 if (sctx->chip_class >= CIK) {
2775 if (sctx->esgs_ring) {
2776 assert(sctx->chip_class <= VI);
2777 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2778 sctx->esgs_ring->width0 / 256);
2779 }
2780 if (sctx->gsvs_ring)
2781 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2782 sctx->gsvs_ring->width0 / 256);
2783 } else {
2784 if (sctx->esgs_ring)
2785 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2786 sctx->esgs_ring->width0 / 256);
2787 if (sctx->gsvs_ring)
2788 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2789 sctx->gsvs_ring->width0 / 256);
2790 }
2791
2792 /* Set the state. */
2793 if (sctx->init_config_gs_rings)
2794 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2795 sctx->init_config_gs_rings = pm4;
2796
2797 if (!sctx->init_config_has_vgt_flush) {
2798 si_init_config_add_vgt_flush(sctx);
2799 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2800 }
2801
2802 /* Flush the context to re-emit both init_config states. */
2803 sctx->initial_gfx_cs_size = 0; /* force flush */
2804 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
2805
2806 /* Set ring bindings. */
2807 if (sctx->esgs_ring) {
2808 assert(sctx->chip_class <= VI);
2809 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
2810 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2811 true, true, 4, 64, 0);
2812 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
2813 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2814 false, false, 0, 0, 0);
2815 }
2816 if (sctx->gsvs_ring) {
2817 si_set_ring_buffer(sctx, SI_RING_GSVS,
2818 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2819 false, false, 0, 0, 0);
2820 }
2821
2822 return true;
2823 }
2824
2825 static void si_shader_lock(struct si_shader *shader)
2826 {
2827 mtx_lock(&shader->selector->mutex);
2828 if (shader->previous_stage_sel) {
2829 assert(shader->previous_stage_sel != shader->selector);
2830 mtx_lock(&shader->previous_stage_sel->mutex);
2831 }
2832 }
2833
2834 static void si_shader_unlock(struct si_shader *shader)
2835 {
2836 if (shader->previous_stage_sel)
2837 mtx_unlock(&shader->previous_stage_sel->mutex);
2838 mtx_unlock(&shader->selector->mutex);
2839 }
2840
2841 /**
2842 * @returns 1 if \p sel has been updated to use a new scratch buffer
2843 * 0 if not
2844 * < 0 if there was a failure
2845 */
2846 static int si_update_scratch_buffer(struct si_context *sctx,
2847 struct si_shader *shader)
2848 {
2849 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2850 int r;
2851
2852 if (!shader)
2853 return 0;
2854
2855 /* This shader doesn't need a scratch buffer */
2856 if (shader->config.scratch_bytes_per_wave == 0)
2857 return 0;
2858
2859 /* Prevent race conditions when updating:
2860 * - si_shader::scratch_bo
2861 * - si_shader::binary::code
2862 * - si_shader::previous_stage::binary::code.
2863 */
2864 si_shader_lock(shader);
2865
2866 /* This shader is already configured to use the current
2867 * scratch buffer. */
2868 if (shader->scratch_bo == sctx->scratch_buffer) {
2869 si_shader_unlock(shader);
2870 return 0;
2871 }
2872
2873 assert(sctx->scratch_buffer);
2874
2875 if (shader->previous_stage)
2876 si_shader_apply_scratch_relocs(shader->previous_stage, scratch_va);
2877
2878 si_shader_apply_scratch_relocs(shader, scratch_va);
2879
2880 /* Replace the shader bo with a new bo that has the relocs applied. */
2881 r = si_shader_binary_upload(sctx->screen, shader);
2882 if (r) {
2883 si_shader_unlock(shader);
2884 return r;
2885 }
2886
2887 /* Update the shader state to use the new shader bo. */
2888 si_shader_init_pm4_state(sctx->screen, shader);
2889
2890 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2891
2892 si_shader_unlock(shader);
2893 return 1;
2894 }
2895
2896 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2897 {
2898 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2899 }
2900
2901 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2902 {
2903 return shader ? shader->config.scratch_bytes_per_wave : 0;
2904 }
2905
2906 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
2907 {
2908 if (!sctx->tes_shader.cso)
2909 return NULL; /* tessellation disabled */
2910
2911 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
2912 sctx->fixed_func_tcs_shader.current;
2913 }
2914
2915 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2916 {
2917 unsigned bytes = 0;
2918
2919 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2920 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2921 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2922 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2923
2924 if (sctx->tes_shader.cso) {
2925 struct si_shader *tcs = si_get_tcs_current(sctx);
2926
2927 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
2928 }
2929 return bytes;
2930 }
2931
2932 static bool si_update_scratch_relocs(struct si_context *sctx)
2933 {
2934 struct si_shader *tcs = si_get_tcs_current(sctx);
2935 int r;
2936
2937 /* Update the shaders, so that they are using the latest scratch.
2938 * The scratch buffer may have been changed since these shaders were
2939 * last used, so we still need to try to update them, even if they
2940 * require scratch buffers smaller than the current size.
2941 */
2942 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2943 if (r < 0)
2944 return false;
2945 if (r == 1)
2946 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2947
2948 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2949 if (r < 0)
2950 return false;
2951 if (r == 1)
2952 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2953
2954 r = si_update_scratch_buffer(sctx, tcs);
2955 if (r < 0)
2956 return false;
2957 if (r == 1)
2958 si_pm4_bind_state(sctx, hs, tcs->pm4);
2959
2960 /* VS can be bound as LS, ES, or VS. */
2961 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2962 if (r < 0)
2963 return false;
2964 if (r == 1) {
2965 if (sctx->tes_shader.current)
2966 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2967 else if (sctx->gs_shader.current)
2968 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2969 else
2970 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2971 }
2972
2973 /* TES can be bound as ES or VS. */
2974 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2975 if (r < 0)
2976 return false;
2977 if (r == 1) {
2978 if (sctx->gs_shader.current)
2979 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2980 else
2981 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2982 }
2983
2984 return true;
2985 }
2986
2987 static bool si_update_spi_tmpring_size(struct si_context *sctx)
2988 {
2989 unsigned current_scratch_buffer_size =
2990 si_get_current_scratch_buffer_size(sctx);
2991 unsigned scratch_bytes_per_wave =
2992 si_get_max_scratch_bytes_per_wave(sctx);
2993 unsigned scratch_needed_size = scratch_bytes_per_wave *
2994 sctx->scratch_waves;
2995 unsigned spi_tmpring_size;
2996
2997 if (scratch_needed_size > 0) {
2998 if (scratch_needed_size > current_scratch_buffer_size) {
2999 /* Create a bigger scratch buffer */
3000 r600_resource_reference(&sctx->scratch_buffer, NULL);
3001
3002 sctx->scratch_buffer =
3003 si_aligned_buffer_create(&sctx->screen->b,
3004 SI_RESOURCE_FLAG_UNMAPPABLE,
3005 PIPE_USAGE_DEFAULT,
3006 scratch_needed_size, 256);
3007 if (!sctx->scratch_buffer)
3008 return false;
3009
3010 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3011 si_context_add_resource_size(sctx,
3012 &sctx->scratch_buffer->b.b);
3013 }
3014
3015 if (!si_update_scratch_relocs(sctx))
3016 return false;
3017 }
3018
3019 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3020 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3021 "scratch size should already be aligned correctly.");
3022
3023 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3024 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3025 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3026 sctx->spi_tmpring_size = spi_tmpring_size;
3027 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3028 }
3029 return true;
3030 }
3031
3032 static void si_init_tess_factor_ring(struct si_context *sctx)
3033 {
3034 assert(!sctx->tess_rings);
3035
3036 /* The address must be aligned to 2^19, because the shader only
3037 * receives the high 13 bits.
3038 */
3039 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3040 SI_RESOURCE_FLAG_32BIT,
3041 PIPE_USAGE_DEFAULT,
3042 sctx->screen->tess_offchip_ring_size +
3043 sctx->screen->tess_factor_ring_size,
3044 1 << 19);
3045 if (!sctx->tess_rings)
3046 return;
3047
3048 si_init_config_add_vgt_flush(sctx);
3049
3050 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_rings),
3051 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3052
3053 uint64_t factor_va = r600_resource(sctx->tess_rings)->gpu_address +
3054 sctx->screen->tess_offchip_ring_size;
3055
3056 /* Append these registers to the init config state. */
3057 if (sctx->chip_class >= CIK) {
3058 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3059 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3060 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3061 factor_va >> 8);
3062 if (sctx->chip_class >= GFX9)
3063 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3064 S_030944_BASE_HI(factor_va >> 40));
3065 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3066 sctx->screen->vgt_hs_offchip_param);
3067 } else {
3068 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3069 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3070 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3071 factor_va >> 8);
3072 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3073 sctx->screen->vgt_hs_offchip_param);
3074 }
3075
3076 /* Flush the context to re-emit the init_config state.
3077 * This is done only once in a lifetime of a context.
3078 */
3079 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3080 sctx->initial_gfx_cs_size = 0; /* force flush */
3081 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3082 }
3083
3084 /**
3085 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
3086 * VS passes its outputs to TES directly, so the fixed-function shader only
3087 * has to write TESSOUTER and TESSINNER.
3088 */
3089 static void si_generate_fixed_func_tcs(struct si_context *sctx)
3090 {
3091 struct ureg_src outer, inner;
3092 struct ureg_dst tessouter, tessinner;
3093 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
3094
3095 if (!ureg)
3096 return; /* if we get here, we're screwed */
3097
3098 assert(!sctx->fixed_func_tcs_shader.cso);
3099
3100 outer = ureg_DECL_system_value(ureg,
3101 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
3102 inner = ureg_DECL_system_value(ureg,
3103 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
3104
3105 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
3106 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
3107
3108 ureg_MOV(ureg, tessouter, outer);
3109 ureg_MOV(ureg, tessinner, inner);
3110 ureg_END(ureg);
3111
3112 sctx->fixed_func_tcs_shader.cso =
3113 ureg_create_shader_and_destroy(ureg, &sctx->b);
3114 }
3115
3116 static void si_update_vgt_shader_config(struct si_context *sctx)
3117 {
3118 /* Calculate the index of the config.
3119 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3120 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
3121 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
3122
3123 if (!*pm4) {
3124 uint32_t stages = 0;
3125
3126 *pm4 = CALLOC_STRUCT(si_pm4_state);
3127
3128 if (sctx->tes_shader.cso) {
3129 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3130 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3131
3132 if (sctx->gs_shader.cso)
3133 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3134 S_028B54_GS_EN(1) |
3135 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3136 else
3137 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3138 } else if (sctx->gs_shader.cso) {
3139 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3140 S_028B54_GS_EN(1) |
3141 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3142 }
3143
3144 if (sctx->chip_class >= GFX9)
3145 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3146
3147 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3148 }
3149 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3150 }
3151
3152 bool si_update_shaders(struct si_context *sctx)
3153 {
3154 struct pipe_context *ctx = (struct pipe_context*)sctx;
3155 struct si_compiler_ctx_state compiler_state;
3156 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3157 struct si_shader *old_vs = si_get_vs_state(sctx);
3158 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3159 struct si_shader *old_ps = sctx->ps_shader.current;
3160 unsigned old_spi_shader_col_format =
3161 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3162 int r;
3163
3164 compiler_state.compiler = &sctx->compiler;
3165 compiler_state.debug = sctx->debug;
3166 compiler_state.is_debug_context = sctx->is_debug;
3167
3168 /* Update stages before GS. */
3169 if (sctx->tes_shader.cso) {
3170 if (!sctx->tess_rings) {
3171 si_init_tess_factor_ring(sctx);
3172 if (!sctx->tess_rings)
3173 return false;
3174 }
3175
3176 /* VS as LS */
3177 if (sctx->chip_class <= VI) {
3178 r = si_shader_select(ctx, &sctx->vs_shader,
3179 &compiler_state);
3180 if (r)
3181 return false;
3182 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3183 }
3184
3185 if (sctx->tcs_shader.cso) {
3186 r = si_shader_select(ctx, &sctx->tcs_shader,
3187 &compiler_state);
3188 if (r)
3189 return false;
3190 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3191 } else {
3192 if (!sctx->fixed_func_tcs_shader.cso) {
3193 si_generate_fixed_func_tcs(sctx);
3194 if (!sctx->fixed_func_tcs_shader.cso)
3195 return false;
3196 }
3197
3198 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3199 &compiler_state);
3200 if (r)
3201 return false;
3202 si_pm4_bind_state(sctx, hs,
3203 sctx->fixed_func_tcs_shader.current->pm4);
3204 }
3205
3206 if (sctx->gs_shader.cso) {
3207 /* TES as ES */
3208 if (sctx->chip_class <= VI) {
3209 r = si_shader_select(ctx, &sctx->tes_shader,
3210 &compiler_state);
3211 if (r)
3212 return false;
3213 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3214 }
3215 } else {
3216 /* TES as VS */
3217 r = si_shader_select(ctx, &sctx->tes_shader,
3218 &compiler_state);
3219 if (r)
3220 return false;
3221 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3222 }
3223 } else if (sctx->gs_shader.cso) {
3224 if (sctx->chip_class <= VI) {
3225 /* VS as ES */
3226 r = si_shader_select(ctx, &sctx->vs_shader,
3227 &compiler_state);
3228 if (r)
3229 return false;
3230 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3231
3232 si_pm4_bind_state(sctx, ls, NULL);
3233 si_pm4_bind_state(sctx, hs, NULL);
3234 }
3235 } else {
3236 /* VS as VS */
3237 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
3238 if (r)
3239 return false;
3240 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3241 si_pm4_bind_state(sctx, ls, NULL);
3242 si_pm4_bind_state(sctx, hs, NULL);
3243 }
3244
3245 /* Update GS. */
3246 if (sctx->gs_shader.cso) {
3247 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
3248 if (r)
3249 return false;
3250 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3251 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3252
3253 if (!si_update_gs_ring_buffers(sctx))
3254 return false;
3255 } else {
3256 si_pm4_bind_state(sctx, gs, NULL);
3257 if (sctx->chip_class <= VI)
3258 si_pm4_bind_state(sctx, es, NULL);
3259 }
3260
3261 si_update_vgt_shader_config(sctx);
3262
3263 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3264 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3265
3266 if (sctx->ps_shader.cso) {
3267 unsigned db_shader_control;
3268
3269 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
3270 if (r)
3271 return false;
3272 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3273
3274 db_shader_control =
3275 sctx->ps_shader.cso->db_shader_control |
3276 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3277
3278 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3279 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3280 sctx->flatshade != rs->flatshade) {
3281 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3282 sctx->flatshade = rs->flatshade;
3283 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3284 }
3285
3286 if (sctx->screen->rbplus_allowed &&
3287 si_pm4_state_changed(sctx, ps) &&
3288 (!old_ps ||
3289 old_spi_shader_col_format !=
3290 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3291 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3292
3293 if (sctx->ps_db_shader_control != db_shader_control) {
3294 sctx->ps_db_shader_control = db_shader_control;
3295 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3296 if (sctx->screen->dpbb_allowed)
3297 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3298 }
3299
3300 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3301 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3302 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3303
3304 if (sctx->chip_class == SI)
3305 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3306
3307 if (sctx->framebuffer.nr_samples <= 1)
3308 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3309 }
3310 }
3311
3312 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3313 si_pm4_state_enabled_and_changed(sctx, hs) ||
3314 si_pm4_state_enabled_and_changed(sctx, es) ||
3315 si_pm4_state_enabled_and_changed(sctx, gs) ||
3316 si_pm4_state_enabled_and_changed(sctx, vs) ||
3317 si_pm4_state_enabled_and_changed(sctx, ps)) {
3318 if (!si_update_spi_tmpring_size(sctx))
3319 return false;
3320 }
3321
3322 if (sctx->chip_class >= CIK) {
3323 if (si_pm4_state_enabled_and_changed(sctx, ls))
3324 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3325 else if (!sctx->queued.named.ls)
3326 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3327
3328 if (si_pm4_state_enabled_and_changed(sctx, hs))
3329 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3330 else if (!sctx->queued.named.hs)
3331 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3332
3333 if (si_pm4_state_enabled_and_changed(sctx, es))
3334 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3335 else if (!sctx->queued.named.es)
3336 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3337
3338 if (si_pm4_state_enabled_and_changed(sctx, gs))
3339 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3340 else if (!sctx->queued.named.gs)
3341 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3342
3343 if (si_pm4_state_enabled_and_changed(sctx, vs))
3344 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3345 else if (!sctx->queued.named.vs)
3346 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3347
3348 if (si_pm4_state_enabled_and_changed(sctx, ps))
3349 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3350 else if (!sctx->queued.named.ps)
3351 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3352 }
3353
3354 sctx->do_update_shaders = false;
3355 return true;
3356 }
3357
3358 static void si_emit_scratch_state(struct si_context *sctx)
3359 {
3360 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3361
3362 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3363 sctx->spi_tmpring_size);
3364
3365 if (sctx->scratch_buffer) {
3366 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3367 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3368 RADEON_PRIO_SCRATCH_BUFFER);
3369 }
3370 }
3371
3372 void *si_get_blit_vs(struct si_context *sctx, enum blitter_attrib_type type,
3373 unsigned num_layers)
3374 {
3375 unsigned vs_blit_property;
3376 void **vs;
3377
3378 switch (type) {
3379 case UTIL_BLITTER_ATTRIB_NONE:
3380 vs = num_layers > 1 ? &sctx->vs_blit_pos_layered :
3381 &sctx->vs_blit_pos;
3382 vs_blit_property = SI_VS_BLIT_SGPRS_POS;
3383 break;
3384 case UTIL_BLITTER_ATTRIB_COLOR:
3385 vs = num_layers > 1 ? &sctx->vs_blit_color_layered :
3386 &sctx->vs_blit_color;
3387 vs_blit_property = SI_VS_BLIT_SGPRS_POS_COLOR;
3388 break;
3389 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
3390 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
3391 assert(num_layers == 1);
3392 vs = &sctx->vs_blit_texcoord;
3393 vs_blit_property = SI_VS_BLIT_SGPRS_POS_TEXCOORD;
3394 break;
3395 default:
3396 assert(0);
3397 return NULL;
3398 }
3399 if (*vs)
3400 return *vs;
3401
3402 struct ureg_program *ureg = ureg_create(PIPE_SHADER_VERTEX);
3403 if (!ureg)
3404 return NULL;
3405
3406 /* Tell the shader to load VS inputs from SGPRs: */
3407 ureg_property(ureg, TGSI_PROPERTY_VS_BLIT_SGPRS, vs_blit_property);
3408 ureg_property(ureg, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, true);
3409
3410 /* This is just a pass-through shader with 1-3 MOV instructions. */
3411 ureg_MOV(ureg,
3412 ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0),
3413 ureg_DECL_vs_input(ureg, 0));
3414
3415 if (type != UTIL_BLITTER_ATTRIB_NONE) {
3416 ureg_MOV(ureg,
3417 ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 0),
3418 ureg_DECL_vs_input(ureg, 1));
3419 }
3420
3421 if (num_layers > 1) {
3422 struct ureg_src instance_id =
3423 ureg_DECL_system_value(ureg, TGSI_SEMANTIC_INSTANCEID, 0);
3424 struct ureg_dst layer =
3425 ureg_DECL_output(ureg, TGSI_SEMANTIC_LAYER, 0);
3426
3427 ureg_MOV(ureg, ureg_writemask(layer, TGSI_WRITEMASK_X),
3428 ureg_scalar(instance_id, TGSI_SWIZZLE_X));
3429 }
3430 ureg_END(ureg);
3431
3432 *vs = ureg_create_shader_and_destroy(ureg, &sctx->b);
3433 return *vs;
3434 }
3435
3436 void si_init_shader_functions(struct si_context *sctx)
3437 {
3438 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
3439 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
3440
3441 sctx->b.create_vs_state = si_create_shader_selector;
3442 sctx->b.create_tcs_state = si_create_shader_selector;
3443 sctx->b.create_tes_state = si_create_shader_selector;
3444 sctx->b.create_gs_state = si_create_shader_selector;
3445 sctx->b.create_fs_state = si_create_shader_selector;
3446
3447 sctx->b.bind_vs_state = si_bind_vs_shader;
3448 sctx->b.bind_tcs_state = si_bind_tcs_shader;
3449 sctx->b.bind_tes_state = si_bind_tes_shader;
3450 sctx->b.bind_gs_state = si_bind_gs_shader;
3451 sctx->b.bind_fs_state = si_bind_ps_shader;
3452
3453 sctx->b.delete_vs_state = si_delete_shader_selector;
3454 sctx->b.delete_tcs_state = si_delete_shader_selector;
3455 sctx->b.delete_tes_state = si_delete_shader_selector;
3456 sctx->b.delete_gs_state = si_delete_shader_selector;
3457 sctx->b.delete_fs_state = si_delete_shader_selector;
3458 }