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radeonsi/gfx10: support pixel shaders without exports
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
45 * size as integer.
46 */
47 void *si_get_ir_binary(struct si_shader_selector *sel)
48 {
49 struct blob blob;
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->tokens) {
54 ir_binary = sel->tokens;
55 ir_size = tgsi_num_tokens(sel->tokens) *
56 sizeof(struct tgsi_token);
57 } else {
58 assert(sel->nir);
59
60 blob_init(&blob);
61 nir_serialize(&blob, sel->nir);
62 ir_binary = blob.data;
63 ir_size = blob.size;
64 }
65
66 unsigned size = 4 + ir_size + sizeof(sel->so);
67 char *result = (char*)MALLOC(size);
68 if (!result)
69 return NULL;
70
71 *((uint32_t*)result) = size;
72 memcpy(result + 4, ir_binary, ir_size);
73 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
74
75 if (sel->nir)
76 blob_finish(&blob);
77
78 return result;
79 }
80
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
83 {
84 /* data may be NULL if size == 0 */
85 if (size)
86 memcpy(ptr, data, size);
87 ptr += DIV_ROUND_UP(size, 4);
88 return ptr;
89 }
90
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
93 {
94 memcpy(data, ptr, size);
95 ptr += DIV_ROUND_UP(size, 4);
96 return ptr;
97 }
98
99 /**
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
102 */
103 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
104 {
105 *ptr++ = size;
106 return write_data(ptr, data, size);
107 }
108
109 /**
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
112 */
113 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
114 {
115 *size = *ptr++;
116 assert(*data == NULL);
117 if (!*size)
118 return ptr;
119 *data = malloc(*size);
120 return read_data(ptr, *data, *size);
121 }
122
123 /**
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
125 * as integer.
126 */
127 static void *si_get_shader_binary(struct si_shader *shader)
128 {
129 /* There is always a size of data followed by the data itself. */
130 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
131 strlen(shader->binary.llvm_ir_string) + 1 : 0;
132
133 /* Refuse to allocate overly large buffers and guard against integer
134 * overflow. */
135 if (shader->binary.elf_size > UINT_MAX / 4 ||
136 llvm_ir_size > UINT_MAX / 4)
137 return NULL;
138
139 unsigned size =
140 4 + /* total size */
141 4 + /* CRC32 of the data below */
142 align(sizeof(shader->config), 4) +
143 align(sizeof(shader->info), 4) +
144 4 + align(shader->binary.elf_size, 4) +
145 4 + align(llvm_ir_size, 4);
146 void *buffer = CALLOC(1, size);
147 uint32_t *ptr = (uint32_t*)buffer;
148
149 if (!buffer)
150 return NULL;
151
152 *ptr++ = size;
153 ptr++; /* CRC32 is calculated at the end. */
154
155 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
156 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
157 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
158 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
159 assert((char *)ptr - (char *)buffer == size);
160
161 /* Compute CRC32. */
162 ptr = (uint32_t*)buffer;
163 ptr++;
164 *ptr = util_hash_crc32(ptr + 1, size - 8);
165
166 return buffer;
167 }
168
169 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
170 {
171 uint32_t *ptr = (uint32_t*)binary;
172 uint32_t size = *ptr++;
173 uint32_t crc32 = *ptr++;
174 unsigned chunk_size;
175 unsigned elf_size;
176
177 if (util_hash_crc32(ptr, size - 8) != crc32) {
178 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
179 return false;
180 }
181
182 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
183 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
184 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
185 &elf_size);
186 shader->binary.elf_size = elf_size;
187 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
188
189 return true;
190 }
191
192 /**
193 * Insert a shader into the cache. It's assumed the shader is not in the cache.
194 * Use si_shader_cache_load_shader before calling this.
195 *
196 * Returns false on failure, in which case the ir_binary should be freed.
197 */
198 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
199 struct si_shader *shader,
200 bool insert_into_disk_cache)
201 {
202 void *hw_binary;
203 struct hash_entry *entry;
204 uint8_t key[CACHE_KEY_SIZE];
205
206 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
207 if (entry)
208 return false; /* already added */
209
210 hw_binary = si_get_shader_binary(shader);
211 if (!hw_binary)
212 return false;
213
214 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
215 hw_binary) == NULL) {
216 FREE(hw_binary);
217 return false;
218 }
219
220 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
221 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
222 *((uint32_t *)ir_binary), key);
223 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
224 *((uint32_t *) hw_binary), NULL);
225 }
226
227 return true;
228 }
229
230 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
231 struct si_shader *shader)
232 {
233 struct hash_entry *entry =
234 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
235 if (!entry) {
236 if (sscreen->disk_shader_cache) {
237 unsigned char sha1[CACHE_KEY_SIZE];
238 size_t tg_size = *((uint32_t *) ir_binary);
239
240 disk_cache_compute_key(sscreen->disk_shader_cache,
241 ir_binary, tg_size, sha1);
242
243 size_t binary_size;
244 uint8_t *buffer =
245 disk_cache_get(sscreen->disk_shader_cache,
246 sha1, &binary_size);
247 if (!buffer)
248 return false;
249
250 if (binary_size < sizeof(uint32_t) ||
251 *((uint32_t*)buffer) != binary_size) {
252 /* Something has gone wrong discard the item
253 * from the cache and rebuild/link from
254 * source.
255 */
256 assert(!"Invalid radeonsi shader disk cache "
257 "item!");
258
259 disk_cache_remove(sscreen->disk_shader_cache,
260 sha1);
261 free(buffer);
262
263 return false;
264 }
265
266 if (!si_load_shader_binary(shader, buffer)) {
267 free(buffer);
268 return false;
269 }
270 free(buffer);
271
272 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
273 shader, false))
274 FREE(ir_binary);
275 } else {
276 return false;
277 }
278 } else {
279 if (si_load_shader_binary(shader, entry->data))
280 FREE(ir_binary);
281 else
282 return false;
283 }
284 p_atomic_inc(&sscreen->num_shader_cache_hits);
285 return true;
286 }
287
288 static uint32_t si_shader_cache_key_hash(const void *key)
289 {
290 /* The first dword is the key size. */
291 return util_hash_crc32(key, *(uint32_t*)key);
292 }
293
294 static bool si_shader_cache_key_equals(const void *a, const void *b)
295 {
296 uint32_t *keya = (uint32_t*)a;
297 uint32_t *keyb = (uint32_t*)b;
298
299 /* The first dword is the key size. */
300 if (*keya != *keyb)
301 return false;
302
303 return memcmp(keya, keyb, *keya) == 0;
304 }
305
306 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
307 {
308 FREE((void*)entry->key);
309 FREE(entry->data);
310 }
311
312 bool si_init_shader_cache(struct si_screen *sscreen)
313 {
314 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
315 sscreen->shader_cache =
316 _mesa_hash_table_create(NULL,
317 si_shader_cache_key_hash,
318 si_shader_cache_key_equals);
319
320 return sscreen->shader_cache != NULL;
321 }
322
323 void si_destroy_shader_cache(struct si_screen *sscreen)
324 {
325 if (sscreen->shader_cache)
326 _mesa_hash_table_destroy(sscreen->shader_cache,
327 si_destroy_shader_cache_entry);
328 mtx_destroy(&sscreen->shader_cache_mutex);
329 }
330
331 /* SHADER STATES */
332
333 static void si_set_tesseval_regs(struct si_screen *sscreen,
334 const struct si_shader_selector *tes,
335 struct si_pm4_state *pm4)
336 {
337 const struct tgsi_shader_info *info = &tes->info;
338 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
339 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
340 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
341 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
342 unsigned type, partitioning, topology, distribution_mode;
343
344 switch (tes_prim_mode) {
345 case PIPE_PRIM_LINES:
346 type = V_028B6C_TESS_ISOLINE;
347 break;
348 case PIPE_PRIM_TRIANGLES:
349 type = V_028B6C_TESS_TRIANGLE;
350 break;
351 case PIPE_PRIM_QUADS:
352 type = V_028B6C_TESS_QUAD;
353 break;
354 default:
355 assert(0);
356 return;
357 }
358
359 switch (tes_spacing) {
360 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
361 partitioning = V_028B6C_PART_FRAC_ODD;
362 break;
363 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
364 partitioning = V_028B6C_PART_FRAC_EVEN;
365 break;
366 case PIPE_TESS_SPACING_EQUAL:
367 partitioning = V_028B6C_PART_INTEGER;
368 break;
369 default:
370 assert(0);
371 return;
372 }
373
374 if (tes_point_mode)
375 topology = V_028B6C_OUTPUT_POINT;
376 else if (tes_prim_mode == PIPE_PRIM_LINES)
377 topology = V_028B6C_OUTPUT_LINE;
378 else if (tes_vertex_order_cw)
379 /* for some reason, this must be the other way around */
380 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
381 else
382 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
383
384 if (sscreen->has_distributed_tess) {
385 if (sscreen->info.family == CHIP_FIJI ||
386 sscreen->info.family >= CHIP_POLARIS10)
387 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
388 else
389 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
390 } else
391 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
392
393 assert(pm4->shader);
394 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
395 S_028B6C_PARTITIONING(partitioning) |
396 S_028B6C_TOPOLOGY(topology) |
397 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
398 }
399
400 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
401 * whether the "fractional odd" tessellation spacing is used.
402 *
403 * Possible VGT configurations and which state should set the register:
404 *
405 * Reg set in | VGT shader configuration | Value
406 * ------------------------------------------------------
407 * VS as VS | VS | 30
408 * VS as ES | ES -> GS -> VS | 30
409 * TES as VS | LS -> HS -> VS | 14 or 30
410 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
411 *
412 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
413 */
414 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
415 struct si_shader_selector *sel,
416 struct si_shader *shader,
417 struct si_pm4_state *pm4)
418 {
419 unsigned type = sel->type;
420
421 if (sscreen->info.family < CHIP_POLARIS10 ||
422 sscreen->info.chip_class >= GFX10)
423 return;
424
425 /* VS as VS, or VS as ES: */
426 if ((type == PIPE_SHADER_VERTEX &&
427 (!shader ||
428 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
429 /* TES as VS, or TES as ES: */
430 type == PIPE_SHADER_TESS_EVAL) {
431 unsigned vtx_reuse_depth = 30;
432
433 if (type == PIPE_SHADER_TESS_EVAL &&
434 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
435 PIPE_TESS_SPACING_FRACTIONAL_ODD)
436 vtx_reuse_depth = 14;
437
438 assert(pm4->shader);
439 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
440 }
441 }
442
443 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
444 {
445 if (shader->pm4)
446 si_pm4_clear_state(shader->pm4);
447 else
448 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
449
450 if (shader->pm4) {
451 shader->pm4->shader = shader;
452 return shader->pm4;
453 } else {
454 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
455 return NULL;
456 }
457 }
458
459 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
460 {
461 /* Add the pointer to VBO descriptors. */
462 return num_always_on_user_sgprs + 1;
463 }
464
465 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
466 {
467 struct si_pm4_state *pm4;
468 unsigned vgpr_comp_cnt;
469 uint64_t va;
470
471 assert(sscreen->info.chip_class <= GFX8);
472
473 pm4 = si_get_shader_pm4_state(shader);
474 if (!pm4)
475 return;
476
477 va = shader->bo->gpu_address;
478 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
479
480 /* We need at least 2 components for LS.
481 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
482 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
483 */
484 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
485
486 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
487 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
488
489 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
490 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
491 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
492 S_00B528_DX10_CLAMP(1) |
493 S_00B528_FLOAT_MODE(shader->config.float_mode);
494 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
495 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
496 }
497
498 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
499 {
500 struct si_pm4_state *pm4;
501 uint64_t va;
502 unsigned ls_vgpr_comp_cnt = 0;
503
504 pm4 = si_get_shader_pm4_state(shader);
505 if (!pm4)
506 return;
507
508 va = shader->bo->gpu_address;
509 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
510
511 if (sscreen->info.chip_class >= GFX9) {
512 if (sscreen->info.chip_class >= GFX10) {
513 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
514 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
515 } else {
516 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
517 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
518 }
519
520 /* We need at least 2 components for LS.
521 * GFX9 VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
522 * GFX10 VGPR0-3: (VertexID, RelAutoindex, UserVGPR1, InstanceID).
523 * On gfx9, StepRate0 is set to 1 so that VGPR3 doesn't have to
524 * be loaded.
525 */
526 ls_vgpr_comp_cnt = 1;
527 if (shader->info.uses_instanceid) {
528 if (sscreen->info.chip_class >= GFX10)
529 ls_vgpr_comp_cnt = 3;
530 else
531 ls_vgpr_comp_cnt = 2;
532 }
533
534 unsigned num_user_sgprs =
535 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
536
537 shader->config.rsrc2 =
538 S_00B42C_USER_SGPR(num_user_sgprs) |
539 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
540
541 if (sscreen->info.chip_class >= GFX10)
542 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
543 else
544 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
545 } else {
546 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
547 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
548
549 shader->config.rsrc2 =
550 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
551 S_00B42C_OC_LDS_EN(1) |
552 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
553 }
554
555 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
556 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
557 (sscreen->info.chip_class <= GFX9 ?
558 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
559 S_00B428_DX10_CLAMP(1) |
560 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
561 S_00B428_FLOAT_MODE(shader->config.float_mode) |
562 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
563
564 if (sscreen->info.chip_class <= GFX8) {
565 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
566 shader->config.rsrc2);
567 }
568 }
569
570 static void si_emit_shader_es(struct si_context *sctx)
571 {
572 struct si_shader *shader = sctx->queued.named.es->shader;
573 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
574
575 if (!shader)
576 return;
577
578 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
579 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
580 shader->selector->esgs_itemsize / 4);
581
582 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
583 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
584 SI_TRACKED_VGT_TF_PARAM,
585 shader->vgt_tf_param);
586
587 if (shader->vgt_vertex_reuse_block_cntl)
588 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
589 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
590 shader->vgt_vertex_reuse_block_cntl);
591
592 if (initial_cdw != sctx->gfx_cs->current.cdw)
593 sctx->context_roll = true;
594 }
595
596 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
597 {
598 struct si_pm4_state *pm4;
599 unsigned num_user_sgprs;
600 unsigned vgpr_comp_cnt;
601 uint64_t va;
602 unsigned oc_lds_en;
603
604 assert(sscreen->info.chip_class <= GFX8);
605
606 pm4 = si_get_shader_pm4_state(shader);
607 if (!pm4)
608 return;
609
610 pm4->atom.emit = si_emit_shader_es;
611 va = shader->bo->gpu_address;
612 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
613
614 if (shader->selector->type == PIPE_SHADER_VERTEX) {
615 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
616 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
617 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
618 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
619 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
620 num_user_sgprs = SI_TES_NUM_USER_SGPR;
621 } else
622 unreachable("invalid shader selector type");
623
624 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
625
626 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
627 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
628 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
629 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
630 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
631 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
632 S_00B328_DX10_CLAMP(1) |
633 S_00B328_FLOAT_MODE(shader->config.float_mode));
634 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
635 S_00B32C_USER_SGPR(num_user_sgprs) |
636 S_00B32C_OC_LDS_EN(oc_lds_en) |
637 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
638
639 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
640 si_set_tesseval_regs(sscreen, shader->selector, pm4);
641
642 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
643 }
644
645 void gfx9_get_gs_info(struct si_shader_selector *es,
646 struct si_shader_selector *gs,
647 struct gfx9_gs_info *out)
648 {
649 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
650 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
651 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
652 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
653
654 /* All these are in dwords: */
655 /* We can't allow using the whole LDS, because GS waves compete with
656 * other shader stages for LDS space. */
657 const unsigned max_lds_size = 8 * 1024;
658 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
659 unsigned esgs_lds_size;
660
661 /* All these are per subgroup: */
662 const unsigned max_out_prims = 32 * 1024;
663 const unsigned max_es_verts = 255;
664 const unsigned ideal_gs_prims = 64;
665 unsigned max_gs_prims, gs_prims;
666 unsigned min_es_verts, es_verts, worst_case_es_verts;
667
668 if (uses_adjacency || gs_num_invocations > 1)
669 max_gs_prims = 127 / gs_num_invocations;
670 else
671 max_gs_prims = 255;
672
673 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
674 * Make sure we don't go over the maximum value.
675 */
676 if (gs->gs_max_out_vertices > 0) {
677 max_gs_prims = MIN2(max_gs_prims,
678 max_out_prims /
679 (gs->gs_max_out_vertices * gs_num_invocations));
680 }
681 assert(max_gs_prims > 0);
682
683 /* If the primitive has adjacency, halve the number of vertices
684 * that will be reused in multiple primitives.
685 */
686 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
687
688 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
689 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
690
691 /* Compute ESGS LDS size based on the worst case number of ES vertices
692 * needed to create the target number of GS prims per subgroup.
693 */
694 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
695
696 /* If total LDS usage is too big, refactor partitions based on ratio
697 * of ESGS item sizes.
698 */
699 if (esgs_lds_size > max_lds_size) {
700 /* Our target GS Prims Per Subgroup was too large. Calculate
701 * the maximum number of GS Prims Per Subgroup that will fit
702 * into LDS, capped by the maximum that the hardware can support.
703 */
704 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
705 max_gs_prims);
706 assert(gs_prims > 0);
707 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
708 max_es_verts);
709
710 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
711 assert(esgs_lds_size <= max_lds_size);
712 }
713
714 /* Now calculate remaining ESGS information. */
715 if (esgs_lds_size)
716 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
717 else
718 es_verts = max_es_verts;
719
720 /* Vertices for adjacency primitives are not always reused, so restore
721 * it for ES_VERTS_PER_SUBGRP.
722 */
723 min_es_verts = gs->gs_input_verts_per_prim;
724
725 /* For normal primitives, the VGT only checks if they are past the ES
726 * verts per subgroup after allocating a full GS primitive and if they
727 * are, kick off a new subgroup. But if those additional ES verts are
728 * unique (e.g. not reused) we need to make sure there is enough LDS
729 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
730 */
731 es_verts -= min_es_verts - 1;
732
733 out->es_verts_per_subgroup = es_verts;
734 out->gs_prims_per_subgroup = gs_prims;
735 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
736 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
737 gs->gs_max_out_vertices;
738 out->esgs_ring_size = 4 * esgs_lds_size;
739
740 assert(out->max_prims_per_subgroup <= max_out_prims);
741 }
742
743 static void si_emit_shader_gs(struct si_context *sctx)
744 {
745 struct si_shader *shader = sctx->queued.named.gs->shader;
746 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
747
748 if (!shader)
749 return;
750
751 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
752 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
753 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
754 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
755 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
756 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
757 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
758
759 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
760 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
761 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
762 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
763
764 /* R_028B38_VGT_GS_MAX_VERT_OUT */
765 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
766 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
767 shader->ctx_reg.gs.vgt_gs_max_vert_out);
768
769 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
770 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
771 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
772 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
773 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
774 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
775 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
776 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
777
778 /* R_028B90_VGT_GS_INSTANCE_CNT */
779 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
780 SI_TRACKED_VGT_GS_INSTANCE_CNT,
781 shader->ctx_reg.gs.vgt_gs_instance_cnt);
782
783 if (sctx->chip_class >= GFX9) {
784 /* R_028A44_VGT_GS_ONCHIP_CNTL */
785 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
786 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
787 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
788 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
789 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
790 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
791 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
792 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
793 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
794 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
795 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
796
797 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
798 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
799 SI_TRACKED_VGT_TF_PARAM,
800 shader->vgt_tf_param);
801 if (shader->vgt_vertex_reuse_block_cntl)
802 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
803 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
804 shader->vgt_vertex_reuse_block_cntl);
805 }
806
807 if (initial_cdw != sctx->gfx_cs->current.cdw)
808 sctx->context_roll = true;
809 }
810
811 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
812 {
813 struct si_shader_selector *sel = shader->selector;
814 const ubyte *num_components = sel->info.num_stream_output_components;
815 unsigned gs_num_invocations = sel->gs_num_invocations;
816 struct si_pm4_state *pm4;
817 uint64_t va;
818 unsigned max_stream = sel->max_gs_stream;
819 unsigned offset;
820
821 pm4 = si_get_shader_pm4_state(shader);
822 if (!pm4)
823 return;
824
825 pm4->atom.emit = si_emit_shader_gs;
826
827 offset = num_components[0] * sel->gs_max_out_vertices;
828 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
829
830 if (max_stream >= 1)
831 offset += num_components[1] * sel->gs_max_out_vertices;
832 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
833
834 if (max_stream >= 2)
835 offset += num_components[2] * sel->gs_max_out_vertices;
836 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
837
838 if (max_stream >= 3)
839 offset += num_components[3] * sel->gs_max_out_vertices;
840 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
841
842 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
843 assert(offset < (1 << 15));
844
845 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
846
847 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
848 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
849 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
850 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
851
852 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
853 S_028B90_ENABLE(gs_num_invocations > 0);
854
855 va = shader->bo->gpu_address;
856 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
857
858 if (sscreen->info.chip_class >= GFX9) {
859 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
860 unsigned es_type = shader->key.part.gs.es->type;
861 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
862
863 if (es_type == PIPE_SHADER_VERTEX)
864 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
865 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
866 else if (es_type == PIPE_SHADER_TESS_EVAL)
867 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
868 else
869 unreachable("invalid shader selector type");
870
871 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
872 * VGPR[0:4] are always loaded.
873 */
874 if (sel->info.uses_invocationid)
875 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
876 else if (sel->info.uses_primid)
877 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
878 else if (input_prim >= PIPE_PRIM_TRIANGLES)
879 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
880 else
881 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
882
883 unsigned num_user_sgprs;
884 if (es_type == PIPE_SHADER_VERTEX)
885 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
886 else
887 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
888
889 if (sscreen->info.chip_class >= GFX10) {
890 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
891 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
892 } else {
893 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
894 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
895 }
896
897 uint32_t rsrc1 =
898 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
899 S_00B228_DX10_CLAMP(1) |
900 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
901 S_00B228_FLOAT_MODE(shader->config.float_mode) |
902 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
903 uint32_t rsrc2 =
904 S_00B22C_USER_SGPR(num_user_sgprs) |
905 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
906 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
907 S_00B22C_LDS_SIZE(shader->config.lds_size) |
908 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
909
910 if (sscreen->info.chip_class >= GFX10) {
911 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
912 } else {
913 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
914 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
915 }
916
917 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
918 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
919
920 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
921 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
922 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
923 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
924 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
925 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
926 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
927 shader->key.part.gs.es->esgs_itemsize / 4;
928
929 if (es_type == PIPE_SHADER_TESS_EVAL)
930 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
931
932 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
933 NULL, pm4);
934 } else {
935 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
936 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
937
938 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
939 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
940 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
941 S_00B228_DX10_CLAMP(1) |
942 S_00B228_FLOAT_MODE(shader->config.float_mode));
943 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
944 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
945 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
946 }
947 }
948
949 /* Common tail code for NGG primitive shaders. */
950 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
951 struct si_shader *shader,
952 unsigned initial_cdw)
953 {
954 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
955 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
956 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
957 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
958 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
959 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
960 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
961 SI_TRACKED_VGT_PRIMITIVEID_EN,
962 shader->ctx_reg.ngg.vgt_primitiveid_en);
963 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
964 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
965 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
966 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
967 SI_TRACKED_VGT_GS_INSTANCE_CNT,
968 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
969 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
970 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
971 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
972 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
973 SI_TRACKED_VGT_REUSE_OFF,
974 shader->ctx_reg.ngg.vgt_reuse_off);
975 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
976 SI_TRACKED_SPI_VS_OUT_CONFIG,
977 shader->ctx_reg.ngg.spi_vs_out_config);
978 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
979 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
980 shader->ctx_reg.ngg.spi_shader_idx_format,
981 shader->ctx_reg.ngg.spi_shader_pos_format);
982 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
983 SI_TRACKED_PA_CL_VTE_CNTL,
984 shader->ctx_reg.ngg.pa_cl_vte_cntl);
985 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
986 SI_TRACKED_PA_CL_NGG_CNTL,
987 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
988
989 if (initial_cdw != sctx->gfx_cs->current.cdw)
990 sctx->context_roll = true;
991
992 if (shader->ge_cntl != sctx->last_multi_vgt_param) {
993 radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, shader->ge_cntl);
994 sctx->last_multi_vgt_param = shader->ge_cntl;
995 }
996 }
997
998 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
999 {
1000 struct si_shader *shader = sctx->queued.named.gs->shader;
1001 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1002
1003 if (!shader)
1004 return;
1005
1006 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1007 }
1008
1009 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1010 {
1011 struct si_shader *shader = sctx->queued.named.gs->shader;
1012 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1013
1014 if (!shader)
1015 return;
1016
1017 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1018 SI_TRACKED_VGT_TF_PARAM,
1019 shader->vgt_tf_param);
1020
1021 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1022 }
1023
1024 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1025 {
1026 struct si_shader *shader = sctx->queued.named.gs->shader;
1027 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1028
1029 if (!shader)
1030 return;
1031
1032 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1033 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1034 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1035
1036 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1037 }
1038
1039 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1040 {
1041 struct si_shader *shader = sctx->queued.named.gs->shader;
1042 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1043
1044 if (!shader)
1045 return;
1046
1047 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1048 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1049 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1050 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1051 SI_TRACKED_VGT_TF_PARAM,
1052 shader->vgt_tf_param);
1053
1054 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1055 }
1056
1057 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1058 {
1059 if (gs->type == PIPE_SHADER_GEOMETRY)
1060 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1061
1062 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1063 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1064 return PIPE_PRIM_POINTS;
1065 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1066 return PIPE_PRIM_LINES;
1067 return PIPE_PRIM_TRIANGLES;
1068 }
1069
1070 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1071 return PIPE_PRIM_TRIANGLES;
1072 }
1073
1074 /**
1075 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1076 * in NGG mode.
1077 */
1078 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1079 {
1080 const struct si_shader_selector *gs_sel = shader->selector;
1081 const struct tgsi_shader_info *gs_info = &gs_sel->info;
1082 enum pipe_shader_type gs_type = shader->selector->type;
1083 const struct si_shader_selector *es_sel =
1084 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1085 const struct tgsi_shader_info *es_info = &es_sel->info;
1086 enum pipe_shader_type es_type = es_sel->type;
1087 unsigned num_user_sgprs;
1088 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1089 uint64_t va;
1090 unsigned window_space =
1091 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1092 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1093 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1094 unsigned input_prim = si_get_input_prim(gs_sel);
1095 bool break_wave_at_eoi = false;
1096 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1097 if (!pm4)
1098 return;
1099
1100 if (es_type == PIPE_SHADER_TESS_EVAL) {
1101 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1102 : gfx10_emit_shader_ngg_tess_nogs;
1103 } else {
1104 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1105 : gfx10_emit_shader_ngg_notess_nogs;
1106 }
1107
1108 va = shader->bo->gpu_address;
1109 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1110
1111 if (es_type == PIPE_SHADER_VERTEX) {
1112 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1113 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
1114
1115 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1116 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1117 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1118 } else {
1119 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
1120 }
1121 } else {
1122 assert(es_type == PIPE_SHADER_TESS_EVAL);
1123 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1124 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1125
1126 if (es_enable_prim_id || gs_info->uses_primid)
1127 break_wave_at_eoi = true;
1128 }
1129
1130 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1131 * VGPR[0:4] are always loaded.
1132 *
1133 * Vertex shaders always need to load VGPR3, because they need to
1134 * pass edge flags for decomposed primitives (such as quads) to the PA
1135 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1136 */
1137 if (gs_info->uses_invocationid || gs_type == PIPE_SHADER_VERTEX)
1138 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1139 else if (gs_info->uses_primid)
1140 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1141 else if (input_prim >= PIPE_PRIM_TRIANGLES)
1142 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1143 else
1144 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1145
1146 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1147 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1148 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1149 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
1150 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1151 S_00B228_DX10_CLAMP(1) |
1152 S_00B228_MEM_ORDERED(1) |
1153 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1154 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1155 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1156 S_00B22C_USER_SGPR(num_user_sgprs) |
1157 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1158 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1159 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1160 S_00B22C_LDS_SIZE(shader->config.lds_size));
1161
1162 nparams = MAX2(shader->info.nr_param_exports, 1);
1163 shader->ctx_reg.ngg.spi_vs_out_config =
1164 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1165 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1166
1167 shader->ctx_reg.ngg.spi_shader_idx_format =
1168 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1169 shader->ctx_reg.ngg.spi_shader_pos_format =
1170 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1171 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1172 V_02870C_SPI_SHADER_4COMP :
1173 V_02870C_SPI_SHADER_NONE) |
1174 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1175 V_02870C_SPI_SHADER_4COMP :
1176 V_02870C_SPI_SHADER_NONE) |
1177 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1178 V_02870C_SPI_SHADER_4COMP :
1179 V_02870C_SPI_SHADER_NONE);
1180
1181 shader->ctx_reg.ngg.vgt_primitiveid_en =
1182 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1183 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id);
1184
1185 if (gs_type == PIPE_SHADER_GEOMETRY) {
1186 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1187 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1188 } else {
1189 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1190 }
1191
1192 if (es_type == PIPE_SHADER_TESS_EVAL)
1193 si_set_tesseval_regs(sscreen, es_sel, pm4);
1194
1195 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1196 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1197 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1198 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1199 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1200 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1201 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1202 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1203 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1204 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1205 S_028B90_CNT(gs_num_invocations) |
1206 S_028B90_ENABLE(gs_num_invocations > 1) |
1207 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1208 shader->ngg.max_vert_out_per_gs_instance);
1209
1210 /* User edge flags are set by the pos exports. If user edge flags are
1211 * not used, we must use hw-generated edge flags and pass them via
1212 * the prim export to prevent drawing lines on internal edges of
1213 * decomposed primitives (such as quads) with polygon mode = lines.
1214 *
1215 * TODO: We should combine hw-generated edge flags with user edge
1216 * flags in the shader.
1217 */
1218 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1219 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX &&
1220 !gs_info->writes_edgeflag);
1221
1222 shader->ge_cntl =
1223 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1224 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) |
1225 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1226
1227 if (window_space) {
1228 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1229 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1230 } else {
1231 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1232 S_028818_VTX_W0_FMT(1) |
1233 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1234 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1235 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1236 }
1237
1238 shader->ctx_reg.ngg.vgt_reuse_off =
1239 S_028AB4_REUSE_OFF(sscreen->info.family == CHIP_NAVI10 &&
1240 sscreen->info.chip_external_rev == 0x1 &&
1241 es_type == PIPE_SHADER_TESS_EVAL);
1242 }
1243
1244 static void si_emit_shader_vs(struct si_context *sctx)
1245 {
1246 struct si_shader *shader = sctx->queued.named.vs->shader;
1247 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1248
1249 if (!shader)
1250 return;
1251
1252 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1253 SI_TRACKED_VGT_GS_MODE,
1254 shader->ctx_reg.vs.vgt_gs_mode);
1255 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1256 SI_TRACKED_VGT_PRIMITIVEID_EN,
1257 shader->ctx_reg.vs.vgt_primitiveid_en);
1258
1259 if (sctx->chip_class <= GFX8) {
1260 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1261 SI_TRACKED_VGT_REUSE_OFF,
1262 shader->ctx_reg.vs.vgt_reuse_off);
1263 }
1264
1265 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1266 SI_TRACKED_SPI_VS_OUT_CONFIG,
1267 shader->ctx_reg.vs.spi_vs_out_config);
1268
1269 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1270 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1271 shader->ctx_reg.vs.spi_shader_pos_format);
1272
1273 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1274 SI_TRACKED_PA_CL_VTE_CNTL,
1275 shader->ctx_reg.vs.pa_cl_vte_cntl);
1276
1277 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1278 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1279 SI_TRACKED_VGT_TF_PARAM,
1280 shader->vgt_tf_param);
1281
1282 if (shader->vgt_vertex_reuse_block_cntl)
1283 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1284 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1285 shader->vgt_vertex_reuse_block_cntl);
1286
1287 if (initial_cdw != sctx->gfx_cs->current.cdw)
1288 sctx->context_roll = true;
1289 }
1290
1291 /**
1292 * Compute the state for \p shader, which will run as a vertex shader on the
1293 * hardware.
1294 *
1295 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1296 * is the copy shader.
1297 */
1298 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1299 struct si_shader_selector *gs)
1300 {
1301 const struct tgsi_shader_info *info = &shader->selector->info;
1302 struct si_pm4_state *pm4;
1303 unsigned num_user_sgprs, vgpr_comp_cnt;
1304 uint64_t va;
1305 unsigned nparams, oc_lds_en;
1306 unsigned window_space =
1307 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1308 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1309
1310 pm4 = si_get_shader_pm4_state(shader);
1311 if (!pm4)
1312 return;
1313
1314 pm4->atom.emit = si_emit_shader_vs;
1315
1316 /* We always write VGT_GS_MODE in the VS state, because every switch
1317 * between different shader pipelines involving a different GS or no
1318 * GS at all involves a switch of the VS (different GS use different
1319 * copy shaders). On the other hand, when the API switches from a GS to
1320 * no GS and then back to the same GS used originally, the GS state is
1321 * not sent again.
1322 */
1323 if (!gs) {
1324 unsigned mode = V_028A40_GS_OFF;
1325
1326 /* PrimID needs GS scenario A. */
1327 if (enable_prim_id)
1328 mode = V_028A40_GS_SCENARIO_A;
1329
1330 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1331 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1332 } else {
1333 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1334 sscreen->info.chip_class);
1335 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1336 }
1337
1338 if (sscreen->info.chip_class <= GFX8) {
1339 /* Reuse needs to be set off if we write oViewport. */
1340 shader->ctx_reg.vs.vgt_reuse_off =
1341 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1342 }
1343
1344 va = shader->bo->gpu_address;
1345 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1346
1347 if (gs) {
1348 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1349 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1350 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1351 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1352 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1353 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1354 */
1355 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1356
1357 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1358 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1359 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1360 } else {
1361 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1362 }
1363 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1364 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1365 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1366 } else
1367 unreachable("invalid shader selector type");
1368
1369 /* VS is required to export at least one param. */
1370 nparams = MAX2(shader->info.nr_param_exports, 1);
1371 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1372
1373 if (sscreen->info.chip_class >= GFX10) {
1374 shader->ctx_reg.vs.spi_vs_out_config |=
1375 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1376 }
1377
1378 shader->ctx_reg.vs.spi_shader_pos_format =
1379 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1380 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1381 V_02870C_SPI_SHADER_4COMP :
1382 V_02870C_SPI_SHADER_NONE) |
1383 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1384 V_02870C_SPI_SHADER_4COMP :
1385 V_02870C_SPI_SHADER_NONE) |
1386 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1387 V_02870C_SPI_SHADER_4COMP :
1388 V_02870C_SPI_SHADER_NONE);
1389
1390 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1391
1392 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1393 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1394
1395 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
1396 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1397 S_00B128_DX10_CLAMP(1) |
1398 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1399 S_00B128_FLOAT_MODE(shader->config.float_mode);
1400 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1401 S_00B12C_OC_LDS_EN(oc_lds_en) |
1402 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1403
1404 if (sscreen->info.chip_class <= GFX9) {
1405 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1406 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1407 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1408 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1409 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1410 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1411 }
1412
1413 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1414 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1415
1416 if (window_space)
1417 shader->ctx_reg.vs.pa_cl_vte_cntl =
1418 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1419 else
1420 shader->ctx_reg.vs.pa_cl_vte_cntl =
1421 S_028818_VTX_W0_FMT(1) |
1422 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1423 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1424 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1425
1426 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1427 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1428
1429 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1430 }
1431
1432 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1433 {
1434 struct tgsi_shader_info *info = &ps->selector->info;
1435 unsigned num_colors = !!(info->colors_read & 0x0f) +
1436 !!(info->colors_read & 0xf0);
1437 unsigned num_interp = ps->selector->info.num_inputs +
1438 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1439
1440 assert(num_interp <= 32);
1441 return MIN2(num_interp, 32);
1442 }
1443
1444 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1445 {
1446 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1447 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1448
1449 /* If the i-th target format is set, all previous target formats must
1450 * be non-zero to avoid hangs.
1451 */
1452 for (i = 0; i < num_targets; i++)
1453 if (!(value & (0xf << (i * 4))))
1454 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1455
1456 return value;
1457 }
1458
1459 static void si_emit_shader_ps(struct si_context *sctx)
1460 {
1461 struct si_shader *shader = sctx->queued.named.ps->shader;
1462 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1463
1464 if (!shader)
1465 return;
1466
1467 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1468 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1469 SI_TRACKED_SPI_PS_INPUT_ENA,
1470 shader->ctx_reg.ps.spi_ps_input_ena,
1471 shader->ctx_reg.ps.spi_ps_input_addr);
1472
1473 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1474 SI_TRACKED_SPI_BARYC_CNTL,
1475 shader->ctx_reg.ps.spi_baryc_cntl);
1476 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1477 SI_TRACKED_SPI_PS_IN_CONTROL,
1478 shader->ctx_reg.ps.spi_ps_in_control);
1479
1480 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1481 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1482 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1483 shader->ctx_reg.ps.spi_shader_z_format,
1484 shader->ctx_reg.ps.spi_shader_col_format);
1485
1486 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1487 SI_TRACKED_CB_SHADER_MASK,
1488 shader->ctx_reg.ps.cb_shader_mask);
1489
1490 if (initial_cdw != sctx->gfx_cs->current.cdw)
1491 sctx->context_roll = true;
1492 }
1493
1494 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1495 {
1496 struct tgsi_shader_info *info = &shader->selector->info;
1497 struct si_pm4_state *pm4;
1498 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1499 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1500 uint64_t va;
1501 unsigned input_ena = shader->config.spi_ps_input_ena;
1502
1503 /* we need to enable at least one of them, otherwise we hang the GPU */
1504 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1505 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1506 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1507 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1508 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1509 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1510 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1511 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1512 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1513 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1514 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1515 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1516 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1517 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1518
1519 /* Validate interpolation optimization flags (read as implications). */
1520 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1521 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1522 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1523 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1524 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1525 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1526 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1527 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1528 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1529 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1530 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1531 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1532 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1533 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1534 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1535 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1536 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1537 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1538
1539 /* Validate cases when the optimizations are off (read as implications). */
1540 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1541 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1542 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1543 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1544 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1545 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1546
1547 pm4 = si_get_shader_pm4_state(shader);
1548 if (!pm4)
1549 return;
1550
1551 pm4->atom.emit = si_emit_shader_ps;
1552
1553 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1554 * Possible vaules:
1555 * 0 -> Position = pixel center
1556 * 1 -> Position = pixel centroid
1557 * 2 -> Position = at sample position
1558 *
1559 * From GLSL 4.5 specification, section 7.1:
1560 * "The variable gl_FragCoord is available as an input variable from
1561 * within fragment shaders and it holds the window relative coordinates
1562 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1563 * value can be for any location within the pixel, or one of the
1564 * fragment samples. The use of centroid does not further restrict
1565 * this value to be inside the current primitive."
1566 *
1567 * Meaning that centroid has no effect and we can return anything within
1568 * the pixel. Thus, return the value at sample position, because that's
1569 * the most accurate one shaders can get.
1570 */
1571 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1572
1573 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1574 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1575 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1576
1577 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1578 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1579
1580 /* Ensure that some export memory is always allocated, for two reasons:
1581 *
1582 * 1) Correctness: The hardware ignores the EXEC mask if no export
1583 * memory is allocated, so KILL and alpha test do not work correctly
1584 * without this.
1585 * 2) Performance: Every shader needs at least a NULL export, even when
1586 * it writes no color/depth output. The NULL export instruction
1587 * stalls without this setting.
1588 *
1589 * Don't add this to CB_SHADER_MASK.
1590 *
1591 * GFX10 supports pixel shaders without exports by setting both
1592 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1593 * instructions if any are present.
1594 */
1595 if ((sscreen->info.chip_class <= GFX9 ||
1596 info->uses_kill ||
1597 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1598 !spi_shader_col_format &&
1599 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1600 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1601
1602 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1603 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1604
1605 /* Set interpolation controls. */
1606 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1607
1608 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1609 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1610 shader->ctx_reg.ps.spi_shader_z_format =
1611 ac_get_spi_shader_z_format(info->writes_z,
1612 info->writes_stencil,
1613 info->writes_samplemask);
1614 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1615 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1616
1617 va = shader->bo->gpu_address;
1618 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1619 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1620 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1621
1622 uint32_t rsrc1 =
1623 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1624 S_00B028_DX10_CLAMP(1) |
1625 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1626 S_00B028_FLOAT_MODE(shader->config.float_mode);
1627
1628 if (sscreen->info.chip_class < GFX10) {
1629 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1630 }
1631
1632 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1633 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1634 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1635 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1636 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1637 }
1638
1639 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1640 struct si_shader *shader)
1641 {
1642 switch (shader->selector->type) {
1643 case PIPE_SHADER_VERTEX:
1644 if (shader->key.as_ls)
1645 si_shader_ls(sscreen, shader);
1646 else if (shader->key.as_es)
1647 si_shader_es(sscreen, shader);
1648 else if (shader->key.as_ngg)
1649 gfx10_shader_ngg(sscreen, shader);
1650 else
1651 si_shader_vs(sscreen, shader, NULL);
1652 break;
1653 case PIPE_SHADER_TESS_CTRL:
1654 si_shader_hs(sscreen, shader);
1655 break;
1656 case PIPE_SHADER_TESS_EVAL:
1657 if (shader->key.as_es)
1658 si_shader_es(sscreen, shader);
1659 else if (shader->key.as_ngg)
1660 gfx10_shader_ngg(sscreen, shader);
1661 else
1662 si_shader_vs(sscreen, shader, NULL);
1663 break;
1664 case PIPE_SHADER_GEOMETRY:
1665 if (shader->key.as_ngg)
1666 gfx10_shader_ngg(sscreen, shader);
1667 else
1668 si_shader_gs(sscreen, shader);
1669 break;
1670 case PIPE_SHADER_FRAGMENT:
1671 si_shader_ps(sscreen, shader);
1672 break;
1673 default:
1674 assert(0);
1675 }
1676 }
1677
1678 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1679 {
1680 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1681 if (sctx->queued.named.dsa)
1682 return sctx->queued.named.dsa->alpha_func;
1683
1684 return PIPE_FUNC_ALWAYS;
1685 }
1686
1687 void si_shader_selector_key_vs(struct si_context *sctx,
1688 struct si_shader_selector *vs,
1689 struct si_shader_key *key,
1690 struct si_vs_prolog_bits *prolog_key)
1691 {
1692 if (!sctx->vertex_elements ||
1693 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS])
1694 return;
1695
1696 struct si_vertex_elements *elts = sctx->vertex_elements;
1697
1698 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1699 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1700 prolog_key->unpack_instance_id_from_vertex_id =
1701 sctx->prim_discard_cs_instancing;
1702
1703 /* Prefer a monolithic shader to allow scheduling divisions around
1704 * VBO loads. */
1705 if (prolog_key->instance_divisor_is_fetched)
1706 key->opt.prefer_mono = 1;
1707
1708 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1709 unsigned count_mask = (1 << count) - 1;
1710 unsigned fix = elts->fix_fetch_always & count_mask;
1711 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1712
1713 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1714 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1715 while (mask) {
1716 unsigned i = u_bit_scan(&mask);
1717 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1718 unsigned vbidx = elts->vertex_buffer_index[i];
1719 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1720 unsigned align_mask = (1 << log_hw_load_size) - 1;
1721 if (vb->buffer_offset & align_mask ||
1722 vb->stride & align_mask) {
1723 fix |= 1 << i;
1724 opencode |= 1 << i;
1725 }
1726 }
1727 }
1728
1729 while (fix) {
1730 unsigned i = u_bit_scan(&fix);
1731 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1732 }
1733 key->mono.vs_fetch_opencode = opencode;
1734 }
1735
1736 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1737 struct si_shader_selector *vs,
1738 struct si_shader_key *key)
1739 {
1740 struct si_shader_selector *ps = sctx->ps_shader.cso;
1741
1742 key->opt.clip_disable =
1743 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1744 (vs->info.clipdist_writemask ||
1745 vs->info.writes_clipvertex) &&
1746 !vs->info.culldist_writemask;
1747
1748 /* Find out if PS is disabled. */
1749 bool ps_disabled = true;
1750 if (ps) {
1751 const struct si_state_blend *blend = sctx->queued.named.blend;
1752 bool alpha_to_coverage = blend && blend->alpha_to_coverage;
1753 bool ps_modifies_zs = ps->info.uses_kill ||
1754 ps->info.writes_z ||
1755 ps->info.writes_stencil ||
1756 ps->info.writes_samplemask ||
1757 alpha_to_coverage ||
1758 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1759 unsigned ps_colormask = si_get_total_colormask(sctx);
1760
1761 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1762 (!ps_colormask &&
1763 !ps_modifies_zs &&
1764 !ps->info.writes_memory);
1765 }
1766
1767 /* Find out which VS outputs aren't used by the PS. */
1768 uint64_t outputs_written = vs->outputs_written_before_ps;
1769 uint64_t inputs_read = 0;
1770
1771 /* Ignore outputs that are not passed from VS to PS. */
1772 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1773 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1774 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1775
1776 if (!ps_disabled) {
1777 inputs_read = ps->inputs_read;
1778 }
1779
1780 uint64_t linked = outputs_written & inputs_read;
1781
1782 key->opt.kill_outputs = ~linked & outputs_written;
1783 }
1784
1785 /* Compute the key for the hw shader variant */
1786 static inline void si_shader_selector_key(struct pipe_context *ctx,
1787 struct si_shader_selector *sel,
1788 union si_vgt_stages_key stages_key,
1789 struct si_shader_key *key)
1790 {
1791 struct si_context *sctx = (struct si_context *)ctx;
1792
1793 memset(key, 0, sizeof(*key));
1794
1795 switch (sel->type) {
1796 case PIPE_SHADER_VERTEX:
1797 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1798
1799 if (sctx->tes_shader.cso)
1800 key->as_ls = 1;
1801 else if (sctx->gs_shader.cso)
1802 key->as_es = 1;
1803 else {
1804 key->as_ngg = stages_key.u.ngg;
1805 si_shader_selector_key_hw_vs(sctx, sel, key);
1806
1807 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1808 key->mono.u.vs_export_prim_id = 1;
1809 }
1810 break;
1811 case PIPE_SHADER_TESS_CTRL:
1812 if (sctx->chip_class >= GFX9) {
1813 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1814 key, &key->part.tcs.ls_prolog);
1815 key->part.tcs.ls = sctx->vs_shader.cso;
1816
1817 /* When the LS VGPR fix is needed, monolithic shaders
1818 * can:
1819 * - avoid initializing EXEC in both the LS prolog
1820 * and the LS main part when !vs_needs_prolog
1821 * - remove the fixup for unused input VGPRs
1822 */
1823 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1824
1825 /* The LS output / HS input layout can be communicated
1826 * directly instead of via user SGPRs for merged LS-HS.
1827 * The LS VGPR fix prefers this too.
1828 */
1829 key->opt.prefer_mono = 1;
1830 }
1831
1832 key->part.tcs.epilog.prim_mode =
1833 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1834 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1835 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1836 key->part.tcs.epilog.tes_reads_tess_factors =
1837 sctx->tes_shader.cso->info.reads_tess_factors;
1838
1839 if (sel == sctx->fixed_func_tcs_shader.cso)
1840 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1841 break;
1842 case PIPE_SHADER_TESS_EVAL:
1843 if (sctx->gs_shader.cso)
1844 key->as_es = 1;
1845 else {
1846 key->as_ngg = stages_key.u.ngg;
1847 si_shader_selector_key_hw_vs(sctx, sel, key);
1848
1849 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1850 key->mono.u.vs_export_prim_id = 1;
1851 }
1852 break;
1853 case PIPE_SHADER_GEOMETRY:
1854 if (sctx->chip_class >= GFX9) {
1855 if (sctx->tes_shader.cso) {
1856 key->part.gs.es = sctx->tes_shader.cso;
1857 } else {
1858 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1859 key, &key->part.gs.vs_prolog);
1860 key->part.gs.es = sctx->vs_shader.cso;
1861 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1862 }
1863
1864 key->as_ngg = stages_key.u.ngg;
1865
1866 /* Merged ES-GS can have unbalanced wave usage.
1867 *
1868 * ES threads are per-vertex, while GS threads are
1869 * per-primitive. So without any amplification, there
1870 * are fewer GS threads than ES threads, which can result
1871 * in empty (no-op) GS waves. With too much amplification,
1872 * there are more GS threads than ES threads, which
1873 * can result in empty (no-op) ES waves.
1874 *
1875 * Non-monolithic shaders are implemented by setting EXEC
1876 * at the beginning of shader parts, and don't jump to
1877 * the end if EXEC is 0.
1878 *
1879 * Monolithic shaders use conditional blocks, so they can
1880 * jump and skip empty waves of ES or GS. So set this to
1881 * always use optimized variants, which are monolithic.
1882 */
1883 key->opt.prefer_mono = 1;
1884 }
1885 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1886 break;
1887 case PIPE_SHADER_FRAGMENT: {
1888 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1889 struct si_state_blend *blend = sctx->queued.named.blend;
1890
1891 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1892 sel->info.colors_written == 0x1)
1893 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1894
1895 if (blend) {
1896 /* Select the shader color format based on whether
1897 * blending or alpha are needed.
1898 */
1899 key->part.ps.epilog.spi_shader_col_format =
1900 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1901 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1902 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1903 sctx->framebuffer.spi_shader_col_format_blend) |
1904 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1905 sctx->framebuffer.spi_shader_col_format_alpha) |
1906 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1907 sctx->framebuffer.spi_shader_col_format);
1908 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1909
1910 /* The output for dual source blending should have
1911 * the same format as the first output.
1912 */
1913 if (blend->dual_src_blend)
1914 key->part.ps.epilog.spi_shader_col_format |=
1915 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1916 } else
1917 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1918
1919 /* If alpha-to-coverage is enabled, we have to export alpha
1920 * even if there is no color buffer.
1921 */
1922 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1923 blend && blend->alpha_to_coverage)
1924 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1925
1926 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1927 * to the range supported by the type if a channel has less
1928 * than 16 bits and the export format is 16_ABGR.
1929 */
1930 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1931 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1932 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1933 }
1934
1935 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1936 if (!key->part.ps.epilog.last_cbuf) {
1937 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1938 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1939 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1940 }
1941
1942 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1943 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1944
1945 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1946 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1947
1948 if (sctx->queued.named.blend) {
1949 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1950 rs->multisample_enable;
1951 }
1952
1953 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1954 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1955 (is_line && rs->line_smooth)) &&
1956 sctx->framebuffer.nr_samples <= 1;
1957 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1958
1959 if (sctx->ps_iter_samples > 1 &&
1960 sel->info.reads_samplemask) {
1961 key->part.ps.prolog.samplemask_log_ps_iter =
1962 util_logbase2(sctx->ps_iter_samples);
1963 }
1964
1965 if (rs->force_persample_interp &&
1966 rs->multisample_enable &&
1967 sctx->framebuffer.nr_samples > 1 &&
1968 sctx->ps_iter_samples > 1) {
1969 key->part.ps.prolog.force_persp_sample_interp =
1970 sel->info.uses_persp_center ||
1971 sel->info.uses_persp_centroid;
1972
1973 key->part.ps.prolog.force_linear_sample_interp =
1974 sel->info.uses_linear_center ||
1975 sel->info.uses_linear_centroid;
1976 } else if (rs->multisample_enable &&
1977 sctx->framebuffer.nr_samples > 1) {
1978 key->part.ps.prolog.bc_optimize_for_persp =
1979 sel->info.uses_persp_center &&
1980 sel->info.uses_persp_centroid;
1981 key->part.ps.prolog.bc_optimize_for_linear =
1982 sel->info.uses_linear_center &&
1983 sel->info.uses_linear_centroid;
1984 } else {
1985 /* Make sure SPI doesn't compute more than 1 pair
1986 * of (i,j), which is the optimization here. */
1987 key->part.ps.prolog.force_persp_center_interp =
1988 sel->info.uses_persp_center +
1989 sel->info.uses_persp_centroid +
1990 sel->info.uses_persp_sample > 1;
1991
1992 key->part.ps.prolog.force_linear_center_interp =
1993 sel->info.uses_linear_center +
1994 sel->info.uses_linear_centroid +
1995 sel->info.uses_linear_sample > 1;
1996
1997 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
1998 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1999 }
2000
2001 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2002
2003 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2004 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2005 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2006 struct pipe_resource *tex = cb0->texture;
2007
2008 /* 1D textures are allocated and used as 2D on GFX9. */
2009 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2010 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2011 (tex->target == PIPE_TEXTURE_1D ||
2012 tex->target == PIPE_TEXTURE_1D_ARRAY);
2013 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2014 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2015 tex->target == PIPE_TEXTURE_CUBE ||
2016 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2017 tex->target == PIPE_TEXTURE_3D;
2018 }
2019 break;
2020 }
2021 default:
2022 assert(0);
2023 }
2024
2025 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2026 memset(&key->opt, 0, sizeof(key->opt));
2027 }
2028
2029 static void si_build_shader_variant(struct si_shader *shader,
2030 int thread_index,
2031 bool low_priority)
2032 {
2033 struct si_shader_selector *sel = shader->selector;
2034 struct si_screen *sscreen = sel->screen;
2035 struct ac_llvm_compiler *compiler;
2036 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2037
2038 if (thread_index >= 0) {
2039 if (low_priority) {
2040 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2041 compiler = &sscreen->compiler_lowp[thread_index];
2042 } else {
2043 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2044 compiler = &sscreen->compiler[thread_index];
2045 }
2046 if (!debug->async)
2047 debug = NULL;
2048 } else {
2049 assert(!low_priority);
2050 compiler = shader->compiler_ctx_state.compiler;
2051 }
2052
2053 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
2054 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2055 sel->type);
2056 shader->compilation_failed = true;
2057 return;
2058 }
2059
2060 if (shader->compiler_ctx_state.is_debug_context) {
2061 FILE *f = open_memstream(&shader->shader_log,
2062 &shader->shader_log_size);
2063 if (f) {
2064 si_shader_dump(sscreen, shader, NULL, f, false);
2065 fclose(f);
2066 }
2067 }
2068
2069 si_shader_init_pm4_state(sscreen, shader);
2070 }
2071
2072 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2073 {
2074 struct si_shader *shader = (struct si_shader *)job;
2075
2076 assert(thread_index >= 0);
2077
2078 si_build_shader_variant(shader, thread_index, true);
2079 }
2080
2081 static const struct si_shader_key zeroed;
2082
2083 static bool si_check_missing_main_part(struct si_screen *sscreen,
2084 struct si_shader_selector *sel,
2085 struct si_compiler_ctx_state *compiler_state,
2086 struct si_shader_key *key)
2087 {
2088 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2089
2090 if (!*mainp) {
2091 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2092
2093 if (!main_part)
2094 return false;
2095
2096 /* We can leave the fence as permanently signaled because the
2097 * main part becomes visible globally only after it has been
2098 * compiled. */
2099 util_queue_fence_init(&main_part->ready);
2100
2101 main_part->selector = sel;
2102 main_part->key.as_es = key->as_es;
2103 main_part->key.as_ls = key->as_ls;
2104 main_part->key.as_ngg = key->as_ngg;
2105 main_part->is_monolithic = false;
2106
2107 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
2108 main_part, &compiler_state->debug) != 0) {
2109 FREE(main_part);
2110 return false;
2111 }
2112 *mainp = main_part;
2113 }
2114 return true;
2115 }
2116
2117 /**
2118 * Select a shader variant according to the shader key.
2119 *
2120 * \param optimized_or_none If the key describes an optimized shader variant and
2121 * the compilation isn't finished, don't select any
2122 * shader and return an error.
2123 */
2124 int si_shader_select_with_key(struct si_screen *sscreen,
2125 struct si_shader_ctx_state *state,
2126 struct si_compiler_ctx_state *compiler_state,
2127 struct si_shader_key *key,
2128 int thread_index,
2129 bool optimized_or_none)
2130 {
2131 struct si_shader_selector *sel = state->cso;
2132 struct si_shader_selector *previous_stage_sel = NULL;
2133 struct si_shader *current = state->current;
2134 struct si_shader *iter, *shader = NULL;
2135
2136 again:
2137 /* Check if we don't need to change anything.
2138 * This path is also used for most shaders that don't need multiple
2139 * variants, it will cost just a computation of the key and this
2140 * test. */
2141 if (likely(current &&
2142 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2143 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2144 if (current->is_optimized) {
2145 if (optimized_or_none)
2146 return -1;
2147
2148 memset(&key->opt, 0, sizeof(key->opt));
2149 goto current_not_ready;
2150 }
2151
2152 util_queue_fence_wait(&current->ready);
2153 }
2154
2155 return current->compilation_failed ? -1 : 0;
2156 }
2157 current_not_ready:
2158
2159 /* This must be done before the mutex is locked, because async GS
2160 * compilation calls this function too, and therefore must enter
2161 * the mutex first.
2162 *
2163 * Only wait if we are in a draw call. Don't wait if we are
2164 * in a compiler thread.
2165 */
2166 if (thread_index < 0)
2167 util_queue_fence_wait(&sel->ready);
2168
2169 mtx_lock(&sel->mutex);
2170
2171 /* Find the shader variant. */
2172 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2173 /* Don't check the "current" shader. We checked it above. */
2174 if (current != iter &&
2175 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2176 mtx_unlock(&sel->mutex);
2177
2178 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2179 /* If it's an optimized shader and its compilation has
2180 * been started but isn't done, use the unoptimized
2181 * shader so as not to cause a stall due to compilation.
2182 */
2183 if (iter->is_optimized) {
2184 if (optimized_or_none)
2185 return -1;
2186 memset(&key->opt, 0, sizeof(key->opt));
2187 goto again;
2188 }
2189
2190 util_queue_fence_wait(&iter->ready);
2191 }
2192
2193 if (iter->compilation_failed) {
2194 return -1; /* skip the draw call */
2195 }
2196
2197 state->current = iter;
2198 return 0;
2199 }
2200 }
2201
2202 /* Build a new shader. */
2203 shader = CALLOC_STRUCT(si_shader);
2204 if (!shader) {
2205 mtx_unlock(&sel->mutex);
2206 return -ENOMEM;
2207 }
2208
2209 util_queue_fence_init(&shader->ready);
2210
2211 shader->selector = sel;
2212 shader->key = *key;
2213 shader->compiler_ctx_state = *compiler_state;
2214
2215 /* If this is a merged shader, get the first shader's selector. */
2216 if (sscreen->info.chip_class >= GFX9) {
2217 if (sel->type == PIPE_SHADER_TESS_CTRL)
2218 previous_stage_sel = key->part.tcs.ls;
2219 else if (sel->type == PIPE_SHADER_GEOMETRY)
2220 previous_stage_sel = key->part.gs.es;
2221
2222 /* We need to wait for the previous shader. */
2223 if (previous_stage_sel && thread_index < 0)
2224 util_queue_fence_wait(&previous_stage_sel->ready);
2225 }
2226
2227 bool is_pure_monolithic =
2228 sscreen->use_monolithic_shaders ||
2229 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2230
2231 /* Compile the main shader part if it doesn't exist. This can happen
2232 * if the initial guess was wrong.
2233 *
2234 * The prim discard CS doesn't need the main shader part.
2235 */
2236 if (!is_pure_monolithic &&
2237 !key->opt.vs_as_prim_discard_cs) {
2238 bool ok = true;
2239
2240 /* Make sure the main shader part is present. This is needed
2241 * for shaders that can be compiled as VS, LS, or ES, and only
2242 * one of them is compiled at creation.
2243 *
2244 * It is also needed for GS, which can be compiled as non-NGG
2245 * and NGG.
2246 *
2247 * For merged shaders, check that the starting shader's main
2248 * part is present.
2249 */
2250 if (previous_stage_sel) {
2251 struct si_shader_key shader1_key = zeroed;
2252
2253 if (sel->type == PIPE_SHADER_TESS_CTRL)
2254 shader1_key.as_ls = 1;
2255 else if (sel->type == PIPE_SHADER_GEOMETRY)
2256 shader1_key.as_es = 1;
2257 else
2258 assert(0);
2259
2260 mtx_lock(&previous_stage_sel->mutex);
2261 ok = si_check_missing_main_part(sscreen,
2262 previous_stage_sel,
2263 compiler_state, &shader1_key);
2264 mtx_unlock(&previous_stage_sel->mutex);
2265 }
2266
2267 if (ok) {
2268 ok = si_check_missing_main_part(sscreen, sel,
2269 compiler_state, key);
2270 }
2271
2272 if (!ok) {
2273 FREE(shader);
2274 mtx_unlock(&sel->mutex);
2275 return -ENOMEM; /* skip the draw call */
2276 }
2277 }
2278
2279 /* Keep the reference to the 1st shader of merged shaders, so that
2280 * Gallium can't destroy it before we destroy the 2nd shader.
2281 *
2282 * Set sctx = NULL, because it's unused if we're not releasing
2283 * the shader, and we don't have any sctx here.
2284 */
2285 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2286 previous_stage_sel);
2287
2288 /* Monolithic-only shaders don't make a distinction between optimized
2289 * and unoptimized. */
2290 shader->is_monolithic =
2291 is_pure_monolithic ||
2292 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2293
2294 /* The prim discard CS is always optimized. */
2295 shader->is_optimized =
2296 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2297 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2298
2299 /* If it's an optimized shader, compile it asynchronously. */
2300 if (shader->is_optimized && thread_index < 0) {
2301 /* Compile it asynchronously. */
2302 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2303 shader, &shader->ready,
2304 si_build_shader_variant_low_priority, NULL);
2305
2306 /* Add only after the ready fence was reset, to guard against a
2307 * race with si_bind_XX_shader. */
2308 if (!sel->last_variant) {
2309 sel->first_variant = shader;
2310 sel->last_variant = shader;
2311 } else {
2312 sel->last_variant->next_variant = shader;
2313 sel->last_variant = shader;
2314 }
2315
2316 /* Use the default (unoptimized) shader for now. */
2317 memset(&key->opt, 0, sizeof(key->opt));
2318 mtx_unlock(&sel->mutex);
2319
2320 if (sscreen->options.sync_compile)
2321 util_queue_fence_wait(&shader->ready);
2322
2323 if (optimized_or_none)
2324 return -1;
2325 goto again;
2326 }
2327
2328 /* Reset the fence before adding to the variant list. */
2329 util_queue_fence_reset(&shader->ready);
2330
2331 if (!sel->last_variant) {
2332 sel->first_variant = shader;
2333 sel->last_variant = shader;
2334 } else {
2335 sel->last_variant->next_variant = shader;
2336 sel->last_variant = shader;
2337 }
2338
2339 mtx_unlock(&sel->mutex);
2340
2341 assert(!shader->is_optimized);
2342 si_build_shader_variant(shader, thread_index, false);
2343
2344 util_queue_fence_signal(&shader->ready);
2345
2346 if (!shader->compilation_failed)
2347 state->current = shader;
2348
2349 return shader->compilation_failed ? -1 : 0;
2350 }
2351
2352 static int si_shader_select(struct pipe_context *ctx,
2353 struct si_shader_ctx_state *state,
2354 union si_vgt_stages_key stages_key,
2355 struct si_compiler_ctx_state *compiler_state)
2356 {
2357 struct si_context *sctx = (struct si_context *)ctx;
2358 struct si_shader_key key;
2359
2360 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2361 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2362 &key, -1, false);
2363 }
2364
2365 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2366 bool streamout,
2367 struct si_shader_key *key)
2368 {
2369 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2370
2371 switch (info->processor) {
2372 case PIPE_SHADER_VERTEX:
2373 switch (next_shader) {
2374 case PIPE_SHADER_GEOMETRY:
2375 key->as_es = 1;
2376 break;
2377 case PIPE_SHADER_TESS_CTRL:
2378 case PIPE_SHADER_TESS_EVAL:
2379 key->as_ls = 1;
2380 break;
2381 default:
2382 /* If POSITION isn't written, it can only be a HW VS
2383 * if streamout is used. If streamout isn't used,
2384 * assume that it's a HW LS. (the next shader is TCS)
2385 * This heuristic is needed for separate shader objects.
2386 */
2387 if (!info->writes_position && !streamout)
2388 key->as_ls = 1;
2389 }
2390 break;
2391
2392 case PIPE_SHADER_TESS_EVAL:
2393 if (next_shader == PIPE_SHADER_GEOMETRY ||
2394 !info->writes_position)
2395 key->as_es = 1;
2396 break;
2397 }
2398 }
2399
2400 /**
2401 * Compile the main shader part or the monolithic shader as part of
2402 * si_shader_selector initialization. Since it can be done asynchronously,
2403 * there is no way to report compile failures to applications.
2404 */
2405 static void si_init_shader_selector_async(void *job, int thread_index)
2406 {
2407 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2408 struct si_screen *sscreen = sel->screen;
2409 struct ac_llvm_compiler *compiler;
2410 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2411
2412 assert(!debug->debug_message || debug->async);
2413 assert(thread_index >= 0);
2414 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2415 compiler = &sscreen->compiler[thread_index];
2416
2417 if (sel->nir)
2418 si_lower_nir(sel);
2419
2420 /* Compile the main shader part for use with a prolog and/or epilog.
2421 * If this fails, the driver will try to compile a monolithic shader
2422 * on demand.
2423 */
2424 if (!sscreen->use_monolithic_shaders) {
2425 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2426 void *ir_binary = NULL;
2427
2428 if (!shader) {
2429 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2430 return;
2431 }
2432
2433 /* We can leave the fence signaled because use of the default
2434 * main part is guarded by the selector's ready fence. */
2435 util_queue_fence_init(&shader->ready);
2436
2437 shader->selector = sel;
2438 shader->is_monolithic = false;
2439 si_parse_next_shader_property(&sel->info,
2440 sel->so.num_outputs != 0,
2441 &shader->key);
2442 if (sscreen->info.chip_class >= GFX10 &&
2443 !sscreen->options.disable_ngg &&
2444 (((sel->type == PIPE_SHADER_VERTEX ||
2445 sel->type == PIPE_SHADER_TESS_EVAL) &&
2446 !shader->key.as_ls && !shader->key.as_es) ||
2447 sel->type == PIPE_SHADER_GEOMETRY))
2448 shader->key.as_ngg = 1;
2449
2450 if (sel->tokens || sel->nir)
2451 ir_binary = si_get_ir_binary(sel);
2452
2453 /* Try to load the shader from the shader cache. */
2454 mtx_lock(&sscreen->shader_cache_mutex);
2455
2456 if (ir_binary &&
2457 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2458 mtx_unlock(&sscreen->shader_cache_mutex);
2459 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2460 } else {
2461 mtx_unlock(&sscreen->shader_cache_mutex);
2462
2463 /* Compile the shader if it hasn't been loaded from the cache. */
2464 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2465 debug) != 0) {
2466 FREE(shader);
2467 FREE(ir_binary);
2468 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2469 return;
2470 }
2471
2472 if (ir_binary) {
2473 mtx_lock(&sscreen->shader_cache_mutex);
2474 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2475 FREE(ir_binary);
2476 mtx_unlock(&sscreen->shader_cache_mutex);
2477 }
2478 }
2479
2480 *si_get_main_shader_part(sel, &shader->key) = shader;
2481
2482 /* Unset "outputs_written" flags for outputs converted to
2483 * DEFAULT_VAL, so that later inter-shader optimizations don't
2484 * try to eliminate outputs that don't exist in the final
2485 * shader.
2486 *
2487 * This is only done if non-monolithic shaders are enabled.
2488 */
2489 if ((sel->type == PIPE_SHADER_VERTEX ||
2490 sel->type == PIPE_SHADER_TESS_EVAL) &&
2491 !shader->key.as_ls &&
2492 !shader->key.as_es) {
2493 unsigned i;
2494
2495 for (i = 0; i < sel->info.num_outputs; i++) {
2496 unsigned offset = shader->info.vs_output_param_offset[i];
2497
2498 if (offset <= AC_EXP_PARAM_OFFSET_31)
2499 continue;
2500
2501 unsigned name = sel->info.output_semantic_name[i];
2502 unsigned index = sel->info.output_semantic_index[i];
2503 unsigned id;
2504
2505 switch (name) {
2506 case TGSI_SEMANTIC_GENERIC:
2507 /* don't process indices the function can't handle */
2508 if (index >= SI_MAX_IO_GENERIC)
2509 break;
2510 /* fall through */
2511 default:
2512 id = si_shader_io_get_unique_index(name, index, true);
2513 sel->outputs_written_before_ps &= ~(1ull << id);
2514 break;
2515 case TGSI_SEMANTIC_POSITION: /* ignore these */
2516 case TGSI_SEMANTIC_PSIZE:
2517 case TGSI_SEMANTIC_CLIPVERTEX:
2518 case TGSI_SEMANTIC_EDGEFLAG:
2519 break;
2520 }
2521 }
2522 }
2523 }
2524
2525 /* The GS copy shader is always pre-compiled.
2526 *
2527 * TODO-GFX10: We could compile the GS copy shader on demand, since it
2528 * is only used in the (rare) non-NGG case.
2529 */
2530 if (sel->type == PIPE_SHADER_GEOMETRY) {
2531 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2532 if (!sel->gs_copy_shader) {
2533 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2534 return;
2535 }
2536
2537 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2538 }
2539 }
2540
2541 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2542 struct util_queue_fence *ready_fence,
2543 struct si_compiler_ctx_state *compiler_ctx_state,
2544 void *job, util_queue_execute_func execute)
2545 {
2546 util_queue_fence_init(ready_fence);
2547
2548 struct util_async_debug_callback async_debug;
2549 bool debug =
2550 (sctx->debug.debug_message && !sctx->debug.async) ||
2551 sctx->is_debug ||
2552 si_can_dump_shader(sctx->screen, processor);
2553
2554 if (debug) {
2555 u_async_debug_init(&async_debug);
2556 compiler_ctx_state->debug = async_debug.base;
2557 }
2558
2559 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2560 ready_fence, execute, NULL);
2561
2562 if (debug) {
2563 util_queue_fence_wait(ready_fence);
2564 u_async_debug_drain(&async_debug, &sctx->debug);
2565 u_async_debug_cleanup(&async_debug);
2566 }
2567
2568 if (sctx->screen->options.sync_compile)
2569 util_queue_fence_wait(ready_fence);
2570 }
2571
2572 /* Return descriptor slot usage masks from the given shader info. */
2573 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2574 uint32_t *const_and_shader_buffers,
2575 uint64_t *samplers_and_images)
2576 {
2577 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2578
2579 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2580 num_constbufs = util_last_bit(info->const_buffers_declared);
2581 /* two 8-byte images share one 16-byte slot */
2582 num_images = align(util_last_bit(info->images_declared), 2);
2583 num_samplers = util_last_bit(info->samplers_declared);
2584
2585 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2586 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2587 *const_and_shader_buffers =
2588 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2589
2590 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2591 start = si_get_image_slot(num_images - 1) / 2;
2592 *samplers_and_images =
2593 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2594 }
2595
2596 static void *si_create_shader_selector(struct pipe_context *ctx,
2597 const struct pipe_shader_state *state)
2598 {
2599 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2600 struct si_context *sctx = (struct si_context*)ctx;
2601 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2602 int i;
2603
2604 if (!sel)
2605 return NULL;
2606
2607 pipe_reference_init(&sel->reference, 1);
2608 sel->screen = sscreen;
2609 sel->compiler_ctx_state.debug = sctx->debug;
2610 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2611
2612 sel->so = state->stream_output;
2613
2614 if (state->type == PIPE_SHADER_IR_TGSI) {
2615 sel->tokens = tgsi_dup_tokens(state->tokens);
2616 if (!sel->tokens) {
2617 FREE(sel);
2618 return NULL;
2619 }
2620
2621 tgsi_scan_shader(state->tokens, &sel->info);
2622 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2623 } else {
2624 assert(state->type == PIPE_SHADER_IR_NIR);
2625
2626 sel->nir = state->ir.nir;
2627
2628 si_nir_opts(sel->nir);
2629 si_nir_scan_shader(sel->nir, &sel->info);
2630 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2631 }
2632
2633 sel->type = sel->info.processor;
2634 p_atomic_inc(&sscreen->num_shaders_created);
2635 si_get_active_slot_masks(&sel->info,
2636 &sel->active_const_and_shader_buffers,
2637 &sel->active_samplers_and_images);
2638
2639 /* Record which streamout buffers are enabled. */
2640 for (i = 0; i < sel->so.num_outputs; i++) {
2641 sel->enabled_streamout_buffer_mask |=
2642 (1 << sel->so.output[i].output_buffer) <<
2643 (sel->so.output[i].stream * 4);
2644 }
2645
2646 /* The prolog is a no-op if there are no inputs. */
2647 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2648 sel->info.num_inputs &&
2649 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2650
2651 sel->force_correct_derivs_after_kill =
2652 sel->type == PIPE_SHADER_FRAGMENT &&
2653 sel->info.uses_derivatives &&
2654 sel->info.uses_kill &&
2655 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2656
2657 sel->prim_discard_cs_allowed =
2658 sel->type == PIPE_SHADER_VERTEX &&
2659 !sel->info.uses_bindless_images &&
2660 !sel->info.uses_bindless_samplers &&
2661 !sel->info.writes_memory &&
2662 !sel->info.writes_viewport_index &&
2663 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2664 !sel->so.num_outputs;
2665
2666 /* Set which opcode uses which (i,j) pair. */
2667 if (sel->info.uses_persp_opcode_interp_centroid)
2668 sel->info.uses_persp_centroid = true;
2669
2670 if (sel->info.uses_linear_opcode_interp_centroid)
2671 sel->info.uses_linear_centroid = true;
2672
2673 if (sel->info.uses_persp_opcode_interp_offset ||
2674 sel->info.uses_persp_opcode_interp_sample)
2675 sel->info.uses_persp_center = true;
2676
2677 if (sel->info.uses_linear_opcode_interp_offset ||
2678 sel->info.uses_linear_opcode_interp_sample)
2679 sel->info.uses_linear_center = true;
2680
2681 switch (sel->type) {
2682 case PIPE_SHADER_GEOMETRY:
2683 sel->gs_output_prim =
2684 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2685
2686 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2687 sel->rast_prim = sel->gs_output_prim;
2688 if (util_rast_prim_is_triangles(sel->rast_prim))
2689 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2690
2691 sel->gs_max_out_vertices =
2692 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2693 sel->gs_num_invocations =
2694 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2695 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2696 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2697 sel->gs_max_out_vertices;
2698
2699 sel->max_gs_stream = 0;
2700 for (i = 0; i < sel->so.num_outputs; i++)
2701 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2702 sel->so.output[i].stream);
2703
2704 sel->gs_input_verts_per_prim =
2705 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2706 break;
2707
2708 case PIPE_SHADER_TESS_CTRL:
2709 /* Always reserve space for these. */
2710 sel->patch_outputs_written |=
2711 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2712 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2713 /* fall through */
2714 case PIPE_SHADER_VERTEX:
2715 case PIPE_SHADER_TESS_EVAL:
2716 for (i = 0; i < sel->info.num_outputs; i++) {
2717 unsigned name = sel->info.output_semantic_name[i];
2718 unsigned index = sel->info.output_semantic_index[i];
2719
2720 switch (name) {
2721 case TGSI_SEMANTIC_TESSINNER:
2722 case TGSI_SEMANTIC_TESSOUTER:
2723 case TGSI_SEMANTIC_PATCH:
2724 sel->patch_outputs_written |=
2725 1ull << si_shader_io_get_unique_index_patch(name, index);
2726 break;
2727
2728 case TGSI_SEMANTIC_GENERIC:
2729 /* don't process indices the function can't handle */
2730 if (index >= SI_MAX_IO_GENERIC)
2731 break;
2732 /* fall through */
2733 default:
2734 sel->outputs_written |=
2735 1ull << si_shader_io_get_unique_index(name, index, false);
2736 sel->outputs_written_before_ps |=
2737 1ull << si_shader_io_get_unique_index(name, index, true);
2738 break;
2739 case TGSI_SEMANTIC_EDGEFLAG:
2740 break;
2741 }
2742 }
2743 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2744 sel->lshs_vertex_stride = sel->esgs_itemsize;
2745
2746 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2747 * will start on a different bank. (except for the maximum 32*16).
2748 */
2749 if (sel->lshs_vertex_stride < 32*16)
2750 sel->lshs_vertex_stride += 4;
2751
2752 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2753 * conflicts, i.e. each vertex will start at a different bank.
2754 */
2755 if (sctx->chip_class >= GFX9)
2756 sel->esgs_itemsize += 4;
2757
2758 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2759
2760 /* Only for TES: */
2761 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2762 sel->rast_prim = PIPE_PRIM_POINTS;
2763 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2764 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2765 else
2766 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2767 break;
2768
2769 case PIPE_SHADER_FRAGMENT:
2770 for (i = 0; i < sel->info.num_inputs; i++) {
2771 unsigned name = sel->info.input_semantic_name[i];
2772 unsigned index = sel->info.input_semantic_index[i];
2773
2774 switch (name) {
2775 case TGSI_SEMANTIC_GENERIC:
2776 /* don't process indices the function can't handle */
2777 if (index >= SI_MAX_IO_GENERIC)
2778 break;
2779 /* fall through */
2780 default:
2781 sel->inputs_read |=
2782 1ull << si_shader_io_get_unique_index(name, index, true);
2783 break;
2784 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2785 break;
2786 }
2787 }
2788
2789 for (i = 0; i < 8; i++)
2790 if (sel->info.colors_written & (1 << i))
2791 sel->colors_written_4bit |= 0xf << (4 * i);
2792
2793 for (i = 0; i < sel->info.num_inputs; i++) {
2794 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2795 int index = sel->info.input_semantic_index[i];
2796 sel->color_attr_index[index] = i;
2797 }
2798 }
2799 break;
2800 default:;
2801 }
2802
2803 /* PA_CL_VS_OUT_CNTL */
2804 bool misc_vec_ena =
2805 sel->info.writes_psize || sel->info.writes_edgeflag ||
2806 sel->info.writes_layer || sel->info.writes_viewport_index;
2807 sel->pa_cl_vs_out_cntl =
2808 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2809 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2810 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2811 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2812 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2813 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2814 sel->clipdist_mask = sel->info.writes_clipvertex ?
2815 SIX_BITS : sel->info.clipdist_writemask;
2816 sel->culldist_mask = sel->info.culldist_writemask <<
2817 sel->info.num_written_clipdistance;
2818
2819 /* DB_SHADER_CONTROL */
2820 sel->db_shader_control =
2821 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2822 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2823 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2824 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2825
2826 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2827 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2828 sel->db_shader_control |=
2829 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2830 break;
2831 case TGSI_FS_DEPTH_LAYOUT_LESS:
2832 sel->db_shader_control |=
2833 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2834 break;
2835 }
2836
2837 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2838 *
2839 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2840 * --|-----------|------------|------------|--------------------|-------------------|-------------
2841 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2842 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2843 * 2 | false | true | n/a | LateZ | 1 | 0
2844 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2845 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2846 *
2847 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2848 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2849 *
2850 * Don't use ReZ without profiling !!!
2851 *
2852 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2853 * shaders.
2854 */
2855 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2856 /* Cases 3, 4. */
2857 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2858 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2859 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2860 } else if (sel->info.writes_memory) {
2861 /* Case 2. */
2862 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2863 S_02880C_EXEC_ON_HIER_FAIL(1);
2864 } else {
2865 /* Case 1. */
2866 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2867 }
2868
2869 (void) mtx_init(&sel->mutex, mtx_plain);
2870
2871 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2872 &sel->compiler_ctx_state, sel,
2873 si_init_shader_selector_async);
2874 return sel;
2875 }
2876
2877 static void si_update_streamout_state(struct si_context *sctx)
2878 {
2879 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2880
2881 if (!shader_with_so)
2882 return;
2883
2884 sctx->streamout.enabled_stream_buffers_mask =
2885 shader_with_so->enabled_streamout_buffer_mask;
2886 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2887 }
2888
2889 static void si_update_clip_regs(struct si_context *sctx,
2890 struct si_shader_selector *old_hw_vs,
2891 struct si_shader *old_hw_vs_variant,
2892 struct si_shader_selector *next_hw_vs,
2893 struct si_shader *next_hw_vs_variant)
2894 {
2895 if (next_hw_vs &&
2896 (!old_hw_vs ||
2897 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2898 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2899 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2900 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2901 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2902 !old_hw_vs_variant ||
2903 !next_hw_vs_variant ||
2904 old_hw_vs_variant->key.opt.clip_disable !=
2905 next_hw_vs_variant->key.opt.clip_disable))
2906 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2907 }
2908
2909 static void si_update_common_shader_state(struct si_context *sctx)
2910 {
2911 sctx->uses_bindless_samplers =
2912 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2913 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2914 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2915 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2916 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2917 sctx->uses_bindless_images =
2918 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2919 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2920 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2921 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2922 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2923 sctx->do_update_shaders = true;
2924 }
2925
2926 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2927 {
2928 struct si_context *sctx = (struct si_context *)ctx;
2929 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2930 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2931 struct si_shader_selector *sel = state;
2932
2933 if (sctx->vs_shader.cso == sel)
2934 return;
2935
2936 sctx->vs_shader.cso = sel;
2937 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2938 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2939
2940 si_update_common_shader_state(sctx);
2941 si_update_vs_viewport_state(sctx);
2942 si_set_active_descriptors_for_shader(sctx, sel);
2943 si_update_streamout_state(sctx);
2944 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2945 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2946 }
2947
2948 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2949 {
2950 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2951 (sctx->tes_shader.cso &&
2952 sctx->tes_shader.cso->info.uses_primid) ||
2953 (sctx->tcs_shader.cso &&
2954 sctx->tcs_shader.cso->info.uses_primid) ||
2955 (sctx->gs_shader.cso &&
2956 sctx->gs_shader.cso->info.uses_primid) ||
2957 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2958 sctx->ps_shader.cso->info.uses_primid);
2959 }
2960
2961 static bool si_update_ngg(struct si_context *sctx)
2962 {
2963 if (sctx->chip_class <= GFX9 ||
2964 sctx->screen->options.disable_ngg)
2965 return false;
2966
2967 bool new_ngg = true;
2968
2969 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2970 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
2971 sctx->gs_shader.cso->gs_num_invocations * sctx->gs_shader.cso->gs_max_out_vertices > 256)
2972 new_ngg = false;
2973
2974 if (new_ngg != sctx->ngg) {
2975 sctx->ngg = new_ngg;
2976 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2977 return true;
2978 }
2979 return false;
2980 }
2981
2982 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2983 {
2984 struct si_context *sctx = (struct si_context *)ctx;
2985 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2986 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2987 struct si_shader_selector *sel = state;
2988 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2989 bool ngg_changed;
2990
2991 if (sctx->gs_shader.cso == sel)
2992 return;
2993
2994 sctx->gs_shader.cso = sel;
2995 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2996 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2997
2998 si_update_common_shader_state(sctx);
2999 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3000
3001 ngg_changed = si_update_ngg(sctx);
3002 if (ngg_changed || enable_changed)
3003 si_shader_change_notify(sctx);
3004 if (enable_changed) {
3005 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3006 si_update_tess_uses_prim_id(sctx);
3007 }
3008 si_update_vs_viewport_state(sctx);
3009 si_set_active_descriptors_for_shader(sctx, sel);
3010 si_update_streamout_state(sctx);
3011 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3012 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3013 }
3014
3015 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3016 {
3017 struct si_context *sctx = (struct si_context *)ctx;
3018 struct si_shader_selector *sel = state;
3019 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3020
3021 if (sctx->tcs_shader.cso == sel)
3022 return;
3023
3024 sctx->tcs_shader.cso = sel;
3025 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3026 si_update_tess_uses_prim_id(sctx);
3027
3028 si_update_common_shader_state(sctx);
3029
3030 if (enable_changed)
3031 sctx->last_tcs = NULL; /* invalidate derived tess state */
3032
3033 si_set_active_descriptors_for_shader(sctx, sel);
3034 }
3035
3036 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3037 {
3038 struct si_context *sctx = (struct si_context *)ctx;
3039 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3040 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3041 struct si_shader_selector *sel = state;
3042 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3043
3044 if (sctx->tes_shader.cso == sel)
3045 return;
3046
3047 sctx->tes_shader.cso = sel;
3048 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3049 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3050 si_update_tess_uses_prim_id(sctx);
3051
3052 si_update_common_shader_state(sctx);
3053 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3054
3055 if (enable_changed) {
3056 si_update_ngg(sctx);
3057 si_shader_change_notify(sctx);
3058 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3059 }
3060 si_update_vs_viewport_state(sctx);
3061 si_set_active_descriptors_for_shader(sctx, sel);
3062 si_update_streamout_state(sctx);
3063 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3064 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3065 }
3066
3067 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3068 {
3069 struct si_context *sctx = (struct si_context *)ctx;
3070 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3071 struct si_shader_selector *sel = state;
3072
3073 /* skip if supplied shader is one already in use */
3074 if (old_sel == sel)
3075 return;
3076
3077 sctx->ps_shader.cso = sel;
3078 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3079
3080 si_update_common_shader_state(sctx);
3081 if (sel) {
3082 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3083 si_update_tess_uses_prim_id(sctx);
3084
3085 if (!old_sel ||
3086 old_sel->info.colors_written != sel->info.colors_written)
3087 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3088
3089 if (sctx->screen->has_out_of_order_rast &&
3090 (!old_sel ||
3091 old_sel->info.writes_memory != sel->info.writes_memory ||
3092 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3093 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3094 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3095 }
3096 si_set_active_descriptors_for_shader(sctx, sel);
3097 si_update_ps_colorbuf0_slot(sctx);
3098 }
3099
3100 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3101 {
3102 if (shader->is_optimized) {
3103 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3104 &shader->ready);
3105 }
3106
3107 util_queue_fence_destroy(&shader->ready);
3108
3109 if (shader->pm4) {
3110 /* If destroyed shaders were not unbound, the next compiled
3111 * shader variant could get the same pointer address and so
3112 * binding it to the same shader stage would be considered
3113 * a no-op, causing random behavior.
3114 */
3115 switch (shader->selector->type) {
3116 case PIPE_SHADER_VERTEX:
3117 if (shader->key.as_ls) {
3118 assert(sctx->chip_class <= GFX8);
3119 si_pm4_delete_state(sctx, ls, shader->pm4);
3120 } else if (shader->key.as_es) {
3121 assert(sctx->chip_class <= GFX8);
3122 si_pm4_delete_state(sctx, es, shader->pm4);
3123 } else if (shader->key.as_ngg) {
3124 si_pm4_delete_state(sctx, gs, shader->pm4);
3125 } else {
3126 si_pm4_delete_state(sctx, vs, shader->pm4);
3127 }
3128 break;
3129 case PIPE_SHADER_TESS_CTRL:
3130 si_pm4_delete_state(sctx, hs, shader->pm4);
3131 break;
3132 case PIPE_SHADER_TESS_EVAL:
3133 if (shader->key.as_es) {
3134 assert(sctx->chip_class <= GFX8);
3135 si_pm4_delete_state(sctx, es, shader->pm4);
3136 } else if (shader->key.as_ngg) {
3137 si_pm4_delete_state(sctx, gs, shader->pm4);
3138 } else {
3139 si_pm4_delete_state(sctx, vs, shader->pm4);
3140 }
3141 break;
3142 case PIPE_SHADER_GEOMETRY:
3143 if (shader->is_gs_copy_shader)
3144 si_pm4_delete_state(sctx, vs, shader->pm4);
3145 else
3146 si_pm4_delete_state(sctx, gs, shader->pm4);
3147 break;
3148 case PIPE_SHADER_FRAGMENT:
3149 si_pm4_delete_state(sctx, ps, shader->pm4);
3150 break;
3151 default:;
3152 }
3153 }
3154
3155 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3156 si_shader_destroy(shader);
3157 free(shader);
3158 }
3159
3160 void si_destroy_shader_selector(struct si_context *sctx,
3161 struct si_shader_selector *sel)
3162 {
3163 struct si_shader *p = sel->first_variant, *c;
3164 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3165 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3166 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3167 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3168 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3169 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3170 };
3171
3172 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3173
3174 if (current_shader[sel->type]->cso == sel) {
3175 current_shader[sel->type]->cso = NULL;
3176 current_shader[sel->type]->current = NULL;
3177 }
3178
3179 while (p) {
3180 c = p->next_variant;
3181 si_delete_shader(sctx, p);
3182 p = c;
3183 }
3184
3185 if (sel->main_shader_part)
3186 si_delete_shader(sctx, sel->main_shader_part);
3187 if (sel->main_shader_part_ls)
3188 si_delete_shader(sctx, sel->main_shader_part_ls);
3189 if (sel->main_shader_part_es)
3190 si_delete_shader(sctx, sel->main_shader_part_es);
3191 if (sel->main_shader_part_ngg)
3192 si_delete_shader(sctx, sel->main_shader_part_ngg);
3193 if (sel->gs_copy_shader)
3194 si_delete_shader(sctx, sel->gs_copy_shader);
3195
3196 util_queue_fence_destroy(&sel->ready);
3197 mtx_destroy(&sel->mutex);
3198 free(sel->tokens);
3199 ralloc_free(sel->nir);
3200 free(sel);
3201 }
3202
3203 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3204 {
3205 struct si_context *sctx = (struct si_context *)ctx;
3206 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3207
3208 si_shader_selector_reference(sctx, &sel, NULL);
3209 }
3210
3211 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3212 struct si_shader *vs, unsigned name,
3213 unsigned index, unsigned interpolate)
3214 {
3215 struct tgsi_shader_info *vsinfo = &vs->selector->info;
3216 unsigned j, offset, ps_input_cntl = 0;
3217
3218 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3219 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3220 name == TGSI_SEMANTIC_PRIMID)
3221 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3222
3223 if (name == TGSI_SEMANTIC_PCOORD ||
3224 (name == TGSI_SEMANTIC_TEXCOORD &&
3225 sctx->sprite_coord_enable & (1 << index))) {
3226 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3227 }
3228
3229 for (j = 0; j < vsinfo->num_outputs; j++) {
3230 if (name == vsinfo->output_semantic_name[j] &&
3231 index == vsinfo->output_semantic_index[j]) {
3232 offset = vs->info.vs_output_param_offset[j];
3233
3234 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3235 /* The input is loaded from parameter memory. */
3236 ps_input_cntl |= S_028644_OFFSET(offset);
3237 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3238 if (offset == AC_EXP_PARAM_UNDEFINED) {
3239 /* This can happen with depth-only rendering. */
3240 offset = 0;
3241 } else {
3242 /* The input is a DEFAULT_VAL constant. */
3243 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3244 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3245 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3246 }
3247
3248 ps_input_cntl = S_028644_OFFSET(0x20) |
3249 S_028644_DEFAULT_VAL(offset);
3250 }
3251 break;
3252 }
3253 }
3254
3255 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3256 /* PrimID is written after the last output when HW VS is used. */
3257 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3258 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3259 /* No corresponding output found, load defaults into input.
3260 * Don't set any other bits.
3261 * (FLAT_SHADE=1 completely changes behavior) */
3262 ps_input_cntl = S_028644_OFFSET(0x20);
3263 /* D3D 9 behaviour. GL is undefined */
3264 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3265 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3266 }
3267 return ps_input_cntl;
3268 }
3269
3270 static void si_emit_spi_map(struct si_context *sctx)
3271 {
3272 struct si_shader *ps = sctx->ps_shader.current;
3273 struct si_shader *vs = si_get_vs_state(sctx);
3274 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3275 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3276 unsigned spi_ps_input_cntl[32];
3277
3278 if (!ps || !ps->selector->info.num_inputs)
3279 return;
3280
3281 num_interp = si_get_ps_num_interp(ps);
3282 assert(num_interp > 0);
3283
3284 for (i = 0; i < psinfo->num_inputs; i++) {
3285 unsigned name = psinfo->input_semantic_name[i];
3286 unsigned index = psinfo->input_semantic_index[i];
3287 unsigned interpolate = psinfo->input_interpolate[i];
3288
3289 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3290 index, interpolate);
3291
3292 if (name == TGSI_SEMANTIC_COLOR) {
3293 assert(index < ARRAY_SIZE(bcol_interp));
3294 bcol_interp[index] = interpolate;
3295 }
3296 }
3297
3298 if (ps->key.part.ps.prolog.color_two_side) {
3299 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3300
3301 for (i = 0; i < 2; i++) {
3302 if (!(psinfo->colors_read & (0xf << (i * 4))))
3303 continue;
3304
3305 spi_ps_input_cntl[num_written++] =
3306 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3307
3308 }
3309 }
3310 assert(num_interp == num_written);
3311
3312 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3313 /* Dota 2: Only ~16% of SPI map updates set different values. */
3314 /* Talos: Only ~9% of SPI map updates set different values. */
3315 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3316 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3317 spi_ps_input_cntl,
3318 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3319
3320 if (initial_cdw != sctx->gfx_cs->current.cdw)
3321 sctx->context_roll = true;
3322 }
3323
3324 /**
3325 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3326 */
3327 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3328 {
3329 if (sctx->init_config_has_vgt_flush)
3330 return;
3331
3332 /* Done by Vulkan before VGT_FLUSH. */
3333 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3334 si_pm4_cmd_add(sctx->init_config,
3335 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3336 si_pm4_cmd_end(sctx->init_config, false);
3337
3338 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3339 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3340 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3341 si_pm4_cmd_end(sctx->init_config, false);
3342 sctx->init_config_has_vgt_flush = true;
3343 }
3344
3345 /* Initialize state related to ESGS / GSVS ring buffers */
3346 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3347 {
3348 struct si_shader_selector *es =
3349 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3350 struct si_shader_selector *gs = sctx->gs_shader.cso;
3351 struct si_pm4_state *pm4;
3352
3353 /* Chip constants. */
3354 unsigned num_se = sctx->screen->info.max_se;
3355 unsigned wave_size = 64;
3356 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3357 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3358 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3359 */
3360 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3361 unsigned alignment = 256 * num_se;
3362 /* The maximum size is 63.999 MB per SE. */
3363 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3364
3365 /* Calculate the minimum size. */
3366 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3367 wave_size, alignment);
3368
3369 /* These are recommended sizes, not minimum sizes. */
3370 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3371 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3372 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3373 gs->max_gsvs_emit_size;
3374
3375 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3376 esgs_ring_size = align(esgs_ring_size, alignment);
3377 gsvs_ring_size = align(gsvs_ring_size, alignment);
3378
3379 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3380 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3381
3382 /* Some rings don't have to be allocated if shaders don't use them.
3383 * (e.g. no varyings between ES and GS or GS and VS)
3384 *
3385 * GFX9 doesn't have the ESGS ring.
3386 */
3387 bool update_esgs = sctx->chip_class <= GFX8 &&
3388 esgs_ring_size &&
3389 (!sctx->esgs_ring ||
3390 sctx->esgs_ring->width0 < esgs_ring_size);
3391 bool update_gsvs = gsvs_ring_size &&
3392 (!sctx->gsvs_ring ||
3393 sctx->gsvs_ring->width0 < gsvs_ring_size);
3394
3395 if (!update_esgs && !update_gsvs)
3396 return true;
3397
3398 if (update_esgs) {
3399 pipe_resource_reference(&sctx->esgs_ring, NULL);
3400 sctx->esgs_ring =
3401 pipe_aligned_buffer_create(sctx->b.screen,
3402 SI_RESOURCE_FLAG_UNMAPPABLE,
3403 PIPE_USAGE_DEFAULT,
3404 esgs_ring_size, alignment);
3405 if (!sctx->esgs_ring)
3406 return false;
3407 }
3408
3409 if (update_gsvs) {
3410 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3411 sctx->gsvs_ring =
3412 pipe_aligned_buffer_create(sctx->b.screen,
3413 SI_RESOURCE_FLAG_UNMAPPABLE,
3414 PIPE_USAGE_DEFAULT,
3415 gsvs_ring_size, alignment);
3416 if (!sctx->gsvs_ring)
3417 return false;
3418 }
3419
3420 /* Create the "init_config_gs_rings" state. */
3421 pm4 = CALLOC_STRUCT(si_pm4_state);
3422 if (!pm4)
3423 return false;
3424
3425 if (sctx->chip_class >= GFX7) {
3426 if (sctx->esgs_ring) {
3427 assert(sctx->chip_class <= GFX8);
3428 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3429 sctx->esgs_ring->width0 / 256);
3430 }
3431 if (sctx->gsvs_ring)
3432 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3433 sctx->gsvs_ring->width0 / 256);
3434 } else {
3435 if (sctx->esgs_ring)
3436 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3437 sctx->esgs_ring->width0 / 256);
3438 if (sctx->gsvs_ring)
3439 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3440 sctx->gsvs_ring->width0 / 256);
3441 }
3442
3443 /* Set the state. */
3444 if (sctx->init_config_gs_rings)
3445 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3446 sctx->init_config_gs_rings = pm4;
3447
3448 if (!sctx->init_config_has_vgt_flush) {
3449 si_init_config_add_vgt_flush(sctx);
3450 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3451 }
3452
3453 /* Flush the context to re-emit both init_config states. */
3454 sctx->initial_gfx_cs_size = 0; /* force flush */
3455 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3456
3457 /* Set ring bindings. */
3458 if (sctx->esgs_ring) {
3459 assert(sctx->chip_class <= GFX8);
3460 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3461 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3462 true, true, 4, 64, 0);
3463 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3464 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3465 false, false, 0, 0, 0);
3466 }
3467 if (sctx->gsvs_ring) {
3468 si_set_ring_buffer(sctx, SI_RING_GSVS,
3469 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3470 false, false, 0, 0, 0);
3471 }
3472
3473 return true;
3474 }
3475
3476 static void si_shader_lock(struct si_shader *shader)
3477 {
3478 mtx_lock(&shader->selector->mutex);
3479 if (shader->previous_stage_sel) {
3480 assert(shader->previous_stage_sel != shader->selector);
3481 mtx_lock(&shader->previous_stage_sel->mutex);
3482 }
3483 }
3484
3485 static void si_shader_unlock(struct si_shader *shader)
3486 {
3487 if (shader->previous_stage_sel)
3488 mtx_unlock(&shader->previous_stage_sel->mutex);
3489 mtx_unlock(&shader->selector->mutex);
3490 }
3491
3492 /**
3493 * @returns 1 if \p sel has been updated to use a new scratch buffer
3494 * 0 if not
3495 * < 0 if there was a failure
3496 */
3497 static int si_update_scratch_buffer(struct si_context *sctx,
3498 struct si_shader *shader)
3499 {
3500 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3501
3502 if (!shader)
3503 return 0;
3504
3505 /* This shader doesn't need a scratch buffer */
3506 if (shader->config.scratch_bytes_per_wave == 0)
3507 return 0;
3508
3509 /* Prevent race conditions when updating:
3510 * - si_shader::scratch_bo
3511 * - si_shader::binary::code
3512 * - si_shader::previous_stage::binary::code.
3513 */
3514 si_shader_lock(shader);
3515
3516 /* This shader is already configured to use the current
3517 * scratch buffer. */
3518 if (shader->scratch_bo == sctx->scratch_buffer) {
3519 si_shader_unlock(shader);
3520 return 0;
3521 }
3522
3523 assert(sctx->scratch_buffer);
3524
3525 /* Replace the shader bo with a new bo that has the relocs applied. */
3526 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3527 si_shader_unlock(shader);
3528 return -1;
3529 }
3530
3531 /* Update the shader state to use the new shader bo. */
3532 si_shader_init_pm4_state(sctx->screen, shader);
3533
3534 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3535
3536 si_shader_unlock(shader);
3537 return 1;
3538 }
3539
3540 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3541 {
3542 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3543 }
3544
3545 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3546 {
3547 return shader ? shader->config.scratch_bytes_per_wave : 0;
3548 }
3549
3550 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3551 {
3552 if (!sctx->tes_shader.cso)
3553 return NULL; /* tessellation disabled */
3554
3555 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3556 sctx->fixed_func_tcs_shader.current;
3557 }
3558
3559 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3560 {
3561 unsigned bytes = 0;
3562
3563 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3564 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3565 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3566 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3567
3568 if (sctx->tes_shader.cso) {
3569 struct si_shader *tcs = si_get_tcs_current(sctx);
3570
3571 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3572 }
3573 return bytes;
3574 }
3575
3576 static bool si_update_scratch_relocs(struct si_context *sctx)
3577 {
3578 struct si_shader *tcs = si_get_tcs_current(sctx);
3579 int r;
3580
3581 /* Update the shaders, so that they are using the latest scratch.
3582 * The scratch buffer may have been changed since these shaders were
3583 * last used, so we still need to try to update them, even if they
3584 * require scratch buffers smaller than the current size.
3585 */
3586 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3587 if (r < 0)
3588 return false;
3589 if (r == 1)
3590 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3591
3592 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3593 if (r < 0)
3594 return false;
3595 if (r == 1)
3596 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3597
3598 r = si_update_scratch_buffer(sctx, tcs);
3599 if (r < 0)
3600 return false;
3601 if (r == 1)
3602 si_pm4_bind_state(sctx, hs, tcs->pm4);
3603
3604 /* VS can be bound as LS, ES, or VS. */
3605 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3606 if (r < 0)
3607 return false;
3608 if (r == 1) {
3609 if (sctx->vs_shader.current->key.as_ls)
3610 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3611 else if (sctx->vs_shader.current->key.as_es)
3612 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3613 else if (sctx->vs_shader.current->key.as_ngg)
3614 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3615 else
3616 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3617 }
3618
3619 /* TES can be bound as ES or VS. */
3620 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3621 if (r < 0)
3622 return false;
3623 if (r == 1) {
3624 if (sctx->tes_shader.current->key.as_es)
3625 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3626 else if (sctx->tes_shader.current->key.as_ngg)
3627 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3628 else
3629 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3630 }
3631
3632 return true;
3633 }
3634
3635 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3636 {
3637 unsigned current_scratch_buffer_size =
3638 si_get_current_scratch_buffer_size(sctx);
3639 unsigned scratch_bytes_per_wave =
3640 si_get_max_scratch_bytes_per_wave(sctx);
3641 unsigned scratch_needed_size = scratch_bytes_per_wave *
3642 sctx->scratch_waves;
3643 unsigned spi_tmpring_size;
3644
3645 if (scratch_needed_size > 0) {
3646 if (scratch_needed_size > current_scratch_buffer_size) {
3647 /* Create a bigger scratch buffer */
3648 si_resource_reference(&sctx->scratch_buffer, NULL);
3649
3650 sctx->scratch_buffer =
3651 si_aligned_buffer_create(&sctx->screen->b,
3652 SI_RESOURCE_FLAG_UNMAPPABLE,
3653 PIPE_USAGE_DEFAULT,
3654 scratch_needed_size, 256);
3655 if (!sctx->scratch_buffer)
3656 return false;
3657
3658 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3659 si_context_add_resource_size(sctx,
3660 &sctx->scratch_buffer->b.b);
3661 }
3662
3663 if (!si_update_scratch_relocs(sctx))
3664 return false;
3665 }
3666
3667 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3668 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3669 "scratch size should already be aligned correctly.");
3670
3671 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3672 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3673 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3674 sctx->spi_tmpring_size = spi_tmpring_size;
3675 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3676 }
3677 return true;
3678 }
3679
3680 static void si_init_tess_factor_ring(struct si_context *sctx)
3681 {
3682 assert(!sctx->tess_rings);
3683
3684 /* The address must be aligned to 2^19, because the shader only
3685 * receives the high 13 bits.
3686 */
3687 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3688 SI_RESOURCE_FLAG_32BIT,
3689 PIPE_USAGE_DEFAULT,
3690 sctx->screen->tess_offchip_ring_size +
3691 sctx->screen->tess_factor_ring_size,
3692 1 << 19);
3693 if (!sctx->tess_rings)
3694 return;
3695
3696 si_init_config_add_vgt_flush(sctx);
3697
3698 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3699 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3700
3701 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3702 sctx->screen->tess_offchip_ring_size;
3703
3704 /* Append these registers to the init config state. */
3705 if (sctx->chip_class >= GFX7) {
3706 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3707 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3708 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3709 factor_va >> 8);
3710 if (sctx->chip_class >= GFX10)
3711 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3712 S_030984_BASE_HI(factor_va >> 40));
3713 else if (sctx->chip_class == GFX9)
3714 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3715 S_030944_BASE_HI(factor_va >> 40));
3716 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3717 sctx->screen->vgt_hs_offchip_param);
3718 } else {
3719 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3720 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3721 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3722 factor_va >> 8);
3723 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3724 sctx->screen->vgt_hs_offchip_param);
3725 }
3726
3727 /* Flush the context to re-emit the init_config state.
3728 * This is done only once in a lifetime of a context.
3729 */
3730 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3731 sctx->initial_gfx_cs_size = 0; /* force flush */
3732 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3733 }
3734
3735 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3736 union si_vgt_stages_key key)
3737 {
3738 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3739 uint32_t stages = 0;
3740
3741 if (key.u.tess) {
3742 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3743 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3744
3745 if (key.u.gs)
3746 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3747 S_028B54_GS_EN(1);
3748 else if (key.u.ngg)
3749 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3750 else
3751 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3752 } else if (key.u.gs) {
3753 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3754 S_028B54_GS_EN(1);
3755 } else if (key.u.ngg) {
3756 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3757 }
3758
3759 if (key.u.ngg) {
3760 stages |= S_028B54_PRIMGEN_EN(1);
3761 if (key.u.streamout)
3762 stages |= S_028B54_NGG_WAVE_ID_EN(1);
3763 } else if (key.u.gs)
3764 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3765
3766 if (screen->info.chip_class >= GFX9)
3767 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3768
3769 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3770 return pm4;
3771 }
3772
3773 static void si_update_vgt_shader_config(struct si_context *sctx,
3774 union si_vgt_stages_key key)
3775 {
3776 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3777
3778 if (unlikely(!*pm4))
3779 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3780 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3781 }
3782
3783 bool si_update_shaders(struct si_context *sctx)
3784 {
3785 struct pipe_context *ctx = (struct pipe_context*)sctx;
3786 struct si_compiler_ctx_state compiler_state;
3787 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3788 struct si_shader *old_vs = si_get_vs_state(sctx);
3789 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3790 struct si_shader *old_ps = sctx->ps_shader.current;
3791 union si_vgt_stages_key key;
3792 unsigned old_spi_shader_col_format =
3793 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3794 int r;
3795
3796 compiler_state.compiler = &sctx->compiler;
3797 compiler_state.debug = sctx->debug;
3798 compiler_state.is_debug_context = sctx->is_debug;
3799
3800 key.index = 0;
3801
3802 if (sctx->tes_shader.cso)
3803 key.u.tess = 1;
3804 if (sctx->gs_shader.cso)
3805 key.u.gs = 1;
3806
3807 if (sctx->chip_class >= GFX10) {
3808 key.u.ngg = sctx->ngg;
3809
3810 if (sctx->gs_shader.cso)
3811 key.u.streamout = !!sctx->gs_shader.cso->so.num_outputs;
3812 else if (sctx->tes_shader.cso)
3813 key.u.streamout = !!sctx->tes_shader.cso->so.num_outputs;
3814 else
3815 key.u.streamout = !!sctx->vs_shader.cso->so.num_outputs;
3816 }
3817
3818 /* Update TCS and TES. */
3819 if (sctx->tes_shader.cso) {
3820 if (!sctx->tess_rings) {
3821 si_init_tess_factor_ring(sctx);
3822 if (!sctx->tess_rings)
3823 return false;
3824 }
3825
3826 if (sctx->tcs_shader.cso) {
3827 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3828 &compiler_state);
3829 if (r)
3830 return false;
3831 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3832 } else {
3833 if (!sctx->fixed_func_tcs_shader.cso) {
3834 sctx->fixed_func_tcs_shader.cso =
3835 si_create_fixed_func_tcs(sctx);
3836 if (!sctx->fixed_func_tcs_shader.cso)
3837 return false;
3838 }
3839
3840 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3841 key, &compiler_state);
3842 if (r)
3843 return false;
3844 si_pm4_bind_state(sctx, hs,
3845 sctx->fixed_func_tcs_shader.current->pm4);
3846 }
3847
3848 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3849 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3850 if (r)
3851 return false;
3852
3853 if (sctx->gs_shader.cso) {
3854 /* TES as ES */
3855 assert(sctx->chip_class <= GFX8);
3856 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3857 } else if (key.u.ngg) {
3858 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3859 } else {
3860 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3861 }
3862 }
3863 } else {
3864 if (sctx->chip_class <= GFX8)
3865 si_pm4_bind_state(sctx, ls, NULL);
3866 si_pm4_bind_state(sctx, hs, NULL);
3867 }
3868
3869 /* Update GS. */
3870 if (sctx->gs_shader.cso) {
3871 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3872 if (r)
3873 return false;
3874 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3875 if (!key.u.ngg) {
3876 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3877
3878 if (!si_update_gs_ring_buffers(sctx))
3879 return false;
3880 } else {
3881 si_pm4_bind_state(sctx, vs, NULL);
3882 }
3883 } else {
3884 if (!key.u.ngg) {
3885 si_pm4_bind_state(sctx, gs, NULL);
3886 if (sctx->chip_class <= GFX8)
3887 si_pm4_bind_state(sctx, es, NULL);
3888 }
3889 }
3890
3891 /* Update VS. */
3892 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
3893 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
3894 if (r)
3895 return false;
3896
3897 if (!key.u.tess && !key.u.gs) {
3898 if (key.u.ngg) {
3899 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3900 si_pm4_bind_state(sctx, vs, NULL);
3901 } else {
3902 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3903 }
3904 } else if (sctx->tes_shader.cso) {
3905 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3906 } else {
3907 assert(sctx->gs_shader.cso);
3908 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3909 }
3910 }
3911
3912 si_update_vgt_shader_config(sctx, key);
3913
3914 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3915 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3916
3917 if (sctx->ps_shader.cso) {
3918 unsigned db_shader_control;
3919
3920 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
3921 if (r)
3922 return false;
3923 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3924
3925 db_shader_control =
3926 sctx->ps_shader.cso->db_shader_control |
3927 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3928
3929 if (si_pm4_state_changed(sctx, ps) ||
3930 si_pm4_state_changed(sctx, vs) ||
3931 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
3932 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3933 sctx->flatshade != rs->flatshade) {
3934 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3935 sctx->flatshade = rs->flatshade;
3936 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3937 }
3938
3939 if (sctx->screen->rbplus_allowed &&
3940 si_pm4_state_changed(sctx, ps) &&
3941 (!old_ps ||
3942 old_spi_shader_col_format !=
3943 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3944 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3945
3946 if (sctx->ps_db_shader_control != db_shader_control) {
3947 sctx->ps_db_shader_control = db_shader_control;
3948 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3949 if (sctx->screen->dpbb_allowed)
3950 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3951 }
3952
3953 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3954 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3955 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3956
3957 if (sctx->chip_class == GFX6)
3958 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3959
3960 if (sctx->framebuffer.nr_samples <= 1)
3961 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3962 }
3963 }
3964
3965 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3966 si_pm4_state_enabled_and_changed(sctx, hs) ||
3967 si_pm4_state_enabled_and_changed(sctx, es) ||
3968 si_pm4_state_enabled_and_changed(sctx, gs) ||
3969 si_pm4_state_enabled_and_changed(sctx, vs) ||
3970 si_pm4_state_enabled_and_changed(sctx, ps)) {
3971 if (!si_update_spi_tmpring_size(sctx))
3972 return false;
3973 }
3974
3975 if (sctx->chip_class >= GFX7) {
3976 if (si_pm4_state_enabled_and_changed(sctx, ls))
3977 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3978 else if (!sctx->queued.named.ls)
3979 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3980
3981 if (si_pm4_state_enabled_and_changed(sctx, hs))
3982 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3983 else if (!sctx->queued.named.hs)
3984 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3985
3986 if (si_pm4_state_enabled_and_changed(sctx, es))
3987 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3988 else if (!sctx->queued.named.es)
3989 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3990
3991 if (si_pm4_state_enabled_and_changed(sctx, gs))
3992 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3993 else if (!sctx->queued.named.gs)
3994 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3995
3996 if (si_pm4_state_enabled_and_changed(sctx, vs))
3997 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3998 else if (!sctx->queued.named.vs)
3999 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4000
4001 if (si_pm4_state_enabled_and_changed(sctx, ps))
4002 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4003 else if (!sctx->queued.named.ps)
4004 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4005 }
4006
4007 sctx->do_update_shaders = false;
4008 return true;
4009 }
4010
4011 static void si_emit_scratch_state(struct si_context *sctx)
4012 {
4013 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4014
4015 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4016 sctx->spi_tmpring_size);
4017
4018 if (sctx->scratch_buffer) {
4019 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4020 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4021 RADEON_PRIO_SCRATCH_BUFFER);
4022 }
4023 }
4024
4025 void si_init_shader_functions(struct si_context *sctx)
4026 {
4027 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4028 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4029
4030 sctx->b.create_vs_state = si_create_shader_selector;
4031 sctx->b.create_tcs_state = si_create_shader_selector;
4032 sctx->b.create_tes_state = si_create_shader_selector;
4033 sctx->b.create_gs_state = si_create_shader_selector;
4034 sctx->b.create_fs_state = si_create_shader_selector;
4035
4036 sctx->b.bind_vs_state = si_bind_vs_shader;
4037 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4038 sctx->b.bind_tes_state = si_bind_tes_shader;
4039 sctx->b.bind_gs_state = si_bind_gs_shader;
4040 sctx->b.bind_fs_state = si_bind_ps_shader;
4041
4042 sctx->b.delete_vs_state = si_delete_shader_selector;
4043 sctx->b.delete_tcs_state = si_delete_shader_selector;
4044 sctx->b.delete_tes_state = si_delete_shader_selector;
4045 sctx->b.delete_gs_state = si_delete_shader_selector;
4046 sctx->b.delete_fs_state = si_delete_shader_selector;
4047 }