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21a5c88c512c681b93e70948e9bf16089d591459
[mesa.git] / src / gallium / drivers / radeonsi / si_state_streamout.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25 #include "si_pipe.h"
26 #include "si_state.h"
27 #include "sid.h"
28 #include "radeon/r600_cs.h"
29
30 #include "util/u_memory.h"
31
32 static void si_set_streamout_enable(struct si_context *sctx, bool enable);
33
34 static inline void si_so_target_reference(struct si_streamout_target **dst,
35 struct pipe_stream_output_target *src)
36 {
37 pipe_so_target_reference((struct pipe_stream_output_target**)dst, src);
38 }
39
40 static struct pipe_stream_output_target *
41 si_create_so_target(struct pipe_context *ctx,
42 struct pipe_resource *buffer,
43 unsigned buffer_offset,
44 unsigned buffer_size)
45 {
46 struct si_context *sctx = (struct si_context *)ctx;
47 struct si_streamout_target *t;
48 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
49
50 t = CALLOC_STRUCT(si_streamout_target);
51 if (!t) {
52 return NULL;
53 }
54
55 u_suballocator_alloc(sctx->b.allocator_zeroed_memory, 4, 4,
56 &t->buf_filled_size_offset,
57 (struct pipe_resource**)&t->buf_filled_size);
58 if (!t->buf_filled_size) {
59 FREE(t);
60 return NULL;
61 }
62
63 t->b.reference.count = 1;
64 t->b.context = ctx;
65 pipe_resource_reference(&t->b.buffer, buffer);
66 t->b.buffer_offset = buffer_offset;
67 t->b.buffer_size = buffer_size;
68
69 util_range_add(&rbuffer->valid_buffer_range, buffer_offset,
70 buffer_offset + buffer_size);
71 return &t->b;
72 }
73
74 static void si_so_target_destroy(struct pipe_context *ctx,
75 struct pipe_stream_output_target *target)
76 {
77 struct si_streamout_target *t = (struct si_streamout_target*)target;
78 pipe_resource_reference(&t->b.buffer, NULL);
79 r600_resource_reference(&t->buf_filled_size, NULL);
80 FREE(t);
81 }
82
83 void si_streamout_buffers_dirty(struct si_context *sctx)
84 {
85 if (!sctx->streamout.enabled_mask)
86 return;
87
88 si_mark_atom_dirty(sctx, &sctx->streamout.begin_atom);
89 si_set_streamout_enable(sctx, true);
90 }
91
92 static void si_set_streamout_targets(struct pipe_context *ctx,
93 unsigned num_targets,
94 struct pipe_stream_output_target **targets,
95 const unsigned *offsets)
96 {
97 struct si_context *sctx = (struct si_context *)ctx;
98 struct si_buffer_resources *buffers = &sctx->rw_buffers;
99 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
100 unsigned old_num_targets = sctx->streamout.num_targets;
101 unsigned i, bufidx;
102
103 /* We are going to unbind the buffers. Mark which caches need to be flushed. */
104 if (sctx->streamout.num_targets && sctx->streamout.begin_emitted) {
105 /* Since streamout uses vector writes which go through TC L2
106 * and most other clients can use TC L2 as well, we don't need
107 * to flush it.
108 *
109 * The only cases which requires flushing it is VGT DMA index
110 * fetching (on <= CIK) and indirect draw data, which are rare
111 * cases. Thus, flag the TC L2 dirtiness in the resource and
112 * handle it at draw call time.
113 */
114 for (i = 0; i < sctx->streamout.num_targets; i++)
115 if (sctx->streamout.targets[i])
116 r600_resource(sctx->streamout.targets[i]->b.buffer)->TC_L2_dirty = true;
117
118 /* Invalidate the scalar cache in case a streamout buffer is
119 * going to be used as a constant buffer.
120 *
121 * Invalidate TC L1, because streamout bypasses it (done by
122 * setting GLC=1 in the store instruction), but it can contain
123 * outdated data of streamout buffers.
124 *
125 * VS_PARTIAL_FLUSH is required if the buffers are going to be
126 * used as an input immediately.
127 */
128 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
129 SI_CONTEXT_INV_VMEM_L1 |
130 SI_CONTEXT_VS_PARTIAL_FLUSH;
131 }
132
133 /* All readers of the streamout targets need to be finished before we can
134 * start writing to the targets.
135 */
136 if (num_targets)
137 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
138 SI_CONTEXT_CS_PARTIAL_FLUSH;
139
140 /* Streamout buffers must be bound in 2 places:
141 * 1) in VGT by setting the VGT_STRMOUT registers
142 * 2) as shader resources
143 */
144
145 /* Stop streamout. */
146 if (sctx->streamout.num_targets && sctx->streamout.begin_emitted)
147 si_emit_streamout_end(sctx);
148
149 /* Set the new targets. */
150 unsigned enabled_mask = 0, append_bitmask = 0;
151 for (i = 0; i < num_targets; i++) {
152 si_so_target_reference(&sctx->streamout.targets[i], targets[i]);
153 if (!targets[i])
154 continue;
155
156 si_context_add_resource_size(sctx, targets[i]->buffer);
157 enabled_mask |= 1 << i;
158
159 if (offsets[i] == ((unsigned)-1))
160 append_bitmask |= 1 << i;
161 }
162
163 for (; i < sctx->streamout.num_targets; i++)
164 si_so_target_reference(&sctx->streamout.targets[i], NULL);
165
166 sctx->streamout.enabled_mask = enabled_mask;
167 sctx->streamout.num_targets = num_targets;
168 sctx->streamout.append_bitmask = append_bitmask;
169
170 /* Update dirty state bits. */
171 if (num_targets) {
172 si_streamout_buffers_dirty(sctx);
173 } else {
174 si_set_atom_dirty(sctx, &sctx->streamout.begin_atom, false);
175 si_set_streamout_enable(sctx, false);
176 }
177
178 /* Set the shader resources.*/
179 for (i = 0; i < num_targets; i++) {
180 bufidx = SI_VS_STREAMOUT_BUF0 + i;
181
182 if (targets[i]) {
183 struct pipe_resource *buffer = targets[i]->buffer;
184 uint64_t va = r600_resource(buffer)->gpu_address;
185
186 /* Set the descriptor.
187 *
188 * On VI, the format must be non-INVALID, otherwise
189 * the buffer will be considered not bound and store
190 * instructions will be no-ops.
191 */
192 uint32_t *desc = descs->list + bufidx*4;
193 desc[0] = va;
194 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
195 desc[2] = 0xffffffff;
196 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
197 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
198 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
199 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
200 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
201
202 /* Set the resource. */
203 pipe_resource_reference(&buffers->buffers[bufidx],
204 buffer);
205 radeon_add_to_gfx_buffer_list_check_mem(sctx,
206 (struct r600_resource*)buffer,
207 buffers->shader_usage,
208 RADEON_PRIO_SHADER_RW_BUFFER,
209 true);
210 r600_resource(buffer)->bind_history |= PIPE_BIND_STREAM_OUTPUT;
211
212 buffers->enabled_mask |= 1u << bufidx;
213 } else {
214 /* Clear the descriptor and unset the resource. */
215 memset(descs->list + bufidx*4, 0,
216 sizeof(uint32_t) * 4);
217 pipe_resource_reference(&buffers->buffers[bufidx],
218 NULL);
219 buffers->enabled_mask &= ~(1u << bufidx);
220 }
221 }
222 for (; i < old_num_targets; i++) {
223 bufidx = SI_VS_STREAMOUT_BUF0 + i;
224 /* Clear the descriptor and unset the resource. */
225 memset(descs->list + bufidx*4, 0, sizeof(uint32_t) * 4);
226 pipe_resource_reference(&buffers->buffers[bufidx], NULL);
227 buffers->enabled_mask &= ~(1u << bufidx);
228 }
229
230 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
231 }
232
233 static void si_flush_vgt_streamout(struct si_context *sctx)
234 {
235 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
236 unsigned reg_strmout_cntl;
237
238 /* The register is at different places on different ASICs. */
239 if (sctx->b.chip_class >= CIK) {
240 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
241 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
242 } else {
243 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
244 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
245 }
246
247 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
248 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
249
250 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
251 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
252 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
253 radeon_emit(cs, 0);
254 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
255 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
256 radeon_emit(cs, 4); /* poll interval */
257 }
258
259 static void si_emit_streamout_begin(struct si_context *sctx, struct r600_atom *atom)
260 {
261 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
262 struct si_streamout_target **t = sctx->streamout.targets;
263 uint16_t *stride_in_dw = sctx->streamout.stride_in_dw;
264 unsigned i;
265
266 si_flush_vgt_streamout(sctx);
267
268 for (i = 0; i < sctx->streamout.num_targets; i++) {
269 if (!t[i])
270 continue;
271
272 t[i]->stride_in_dw = stride_in_dw[i];
273
274 /* SI binds streamout buffers as shader resources.
275 * VGT only counts primitives and tells the shader
276 * through SGPRs what to do. */
277 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
278 radeon_emit(cs, (t[i]->b.buffer_offset +
279 t[i]->b.buffer_size) >> 2); /* BUFFER_SIZE (in DW) */
280 radeon_emit(cs, stride_in_dw[i]); /* VTX_STRIDE (in DW) */
281
282 if (sctx->streamout.append_bitmask & (1 << i) && t[i]->buf_filled_size_valid) {
283 uint64_t va = t[i]->buf_filled_size->gpu_address +
284 t[i]->buf_filled_size_offset;
285
286 /* Append. */
287 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
288 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
289 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
290 radeon_emit(cs, 0); /* unused */
291 radeon_emit(cs, 0); /* unused */
292 radeon_emit(cs, va); /* src address lo */
293 radeon_emit(cs, va >> 32); /* src address hi */
294
295 radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs,
296 t[i]->buf_filled_size,
297 RADEON_USAGE_READ,
298 RADEON_PRIO_SO_FILLED_SIZE);
299 } else {
300 /* Start from the beginning. */
301 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
302 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
303 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
304 radeon_emit(cs, 0); /* unused */
305 radeon_emit(cs, 0); /* unused */
306 radeon_emit(cs, t[i]->b.buffer_offset >> 2); /* buffer offset in DW */
307 radeon_emit(cs, 0); /* unused */
308 }
309 }
310
311 sctx->streamout.begin_emitted = true;
312 }
313
314 void si_emit_streamout_end(struct si_context *sctx)
315 {
316 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
317 struct si_streamout_target **t = sctx->streamout.targets;
318 unsigned i;
319 uint64_t va;
320
321 si_flush_vgt_streamout(sctx);
322
323 for (i = 0; i < sctx->streamout.num_targets; i++) {
324 if (!t[i])
325 continue;
326
327 va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset;
328 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
329 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
330 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
331 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
332 radeon_emit(cs, va); /* dst address lo */
333 radeon_emit(cs, va >> 32); /* dst address hi */
334 radeon_emit(cs, 0); /* unused */
335 radeon_emit(cs, 0); /* unused */
336
337 radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs,
338 t[i]->buf_filled_size,
339 RADEON_USAGE_WRITE,
340 RADEON_PRIO_SO_FILLED_SIZE);
341
342 /* Zero the buffer size. The counters (primitives generated,
343 * primitives emitted) may be enabled even if there is not
344 * buffer bound. This ensures that the primitives-emitted query
345 * won't increment. */
346 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
347
348 t[i]->buf_filled_size_valid = true;
349 }
350
351 sctx->streamout.begin_emitted = false;
352 }
353
354 /* STREAMOUT CONFIG DERIVED STATE
355 *
356 * Streamout must be enabled for the PRIMITIVES_GENERATED query to work.
357 * The buffer mask is an independent state, so no writes occur if there
358 * are no buffers bound.
359 */
360
361 static void si_emit_streamout_enable(struct si_context *sctx,
362 struct r600_atom *atom)
363 {
364 radeon_set_context_reg_seq(sctx->b.gfx_cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
365 radeon_emit(sctx->b.gfx_cs,
366 S_028B94_STREAMOUT_0_EN(si_get_strmout_en(sctx)) |
367 S_028B94_RAST_STREAM(0) |
368 S_028B94_STREAMOUT_1_EN(si_get_strmout_en(sctx)) |
369 S_028B94_STREAMOUT_2_EN(si_get_strmout_en(sctx)) |
370 S_028B94_STREAMOUT_3_EN(si_get_strmout_en(sctx)));
371 radeon_emit(sctx->b.gfx_cs,
372 sctx->streamout.hw_enabled_mask &
373 sctx->streamout.enabled_stream_buffers_mask);
374 }
375
376 static void si_set_streamout_enable(struct si_context *sctx, bool enable)
377 {
378 bool old_strmout_en = si_get_strmout_en(sctx);
379 unsigned old_hw_enabled_mask = sctx->streamout.hw_enabled_mask;
380
381 sctx->streamout.streamout_enabled = enable;
382
383 sctx->streamout.hw_enabled_mask = sctx->streamout.enabled_mask |
384 (sctx->streamout.enabled_mask << 4) |
385 (sctx->streamout.enabled_mask << 8) |
386 (sctx->streamout.enabled_mask << 12);
387
388 if ((old_strmout_en != si_get_strmout_en(sctx)) ||
389 (old_hw_enabled_mask != sctx->streamout.hw_enabled_mask))
390 si_mark_atom_dirty(sctx, &sctx->streamout.enable_atom);
391 }
392
393 void si_update_prims_generated_query_state(struct si_context *sctx,
394 unsigned type, int diff)
395 {
396 if (type == PIPE_QUERY_PRIMITIVES_GENERATED) {
397 bool old_strmout_en = si_get_strmout_en(sctx);
398
399 sctx->streamout.num_prims_gen_queries += diff;
400 assert(sctx->streamout.num_prims_gen_queries >= 0);
401
402 sctx->streamout.prims_gen_query_enabled =
403 sctx->streamout.num_prims_gen_queries != 0;
404
405 if (old_strmout_en != si_get_strmout_en(sctx))
406 si_mark_atom_dirty(sctx, &sctx->streamout.enable_atom);
407 }
408 }
409
410 void si_init_streamout_functions(struct si_context *sctx)
411 {
412 sctx->b.b.create_stream_output_target = si_create_so_target;
413 sctx->b.b.stream_output_target_destroy = si_so_target_destroy;
414 sctx->b.b.set_stream_output_targets = si_set_streamout_targets;
415 sctx->streamout.begin_atom.emit = si_emit_streamout_begin;
416 sctx->streamout.enable_atom.emit = si_emit_streamout_enable;
417 }