src/gallium/drivers/radeonsi/si_state_streamout.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  */
  24
  25 #include "si_build_pm4.h"
  26
  27 #include "util/u_memory.h"
  28 #include "util/u_suballoc.h"
  29
  30 static void si_set_streamout_enable(struct si_context *sctx, bool enable);
  31
  32 static inline void si_so_target_reference(struct si_streamout_target **dst,
  33                                           struct pipe_stream_output_target *src)
  34 {
  35         pipe_so_target_reference((struct pipe_stream_output_target**)dst, src);
  36 }
  37
  38 static struct pipe_stream_output_target *
  39 si_create_so_target(struct pipe_context *ctx,
  40                     struct pipe_resource *buffer,
  41                     unsigned buffer_offset,
  42                     unsigned buffer_size)
  43 {
  44         struct si_context *sctx = (struct si_context *)ctx;
  45         struct si_streamout_target *t;
  46         struct r600_resource *rbuffer = (struct r600_resource*)buffer;
  47
  48         t = CALLOC_STRUCT(si_streamout_target);
  49         if (!t) {
  50                 return NULL;
  51         }
  52
  53         u_suballocator_alloc(sctx->allocator_zeroed_memory, 4, 4,
  54                              &t->buf_filled_size_offset,
  55                              (struct pipe_resource**)&t->buf_filled_size);
  56         if (!t->buf_filled_size) {
  57                 FREE(t);
  58                 return NULL;
  59         }
  60
  61         t->b.reference.count = 1;
  62         t->b.context = ctx;
  63         pipe_resource_reference(&t->b.buffer, buffer);
  64         t->b.buffer_offset = buffer_offset;
  65         t->b.buffer_size = buffer_size;
  66
  67         util_range_add(&rbuffer->valid_buffer_range, buffer_offset,
  68                        buffer_offset + buffer_size);
  69         return &t->b;
  70 }
  71
  72 static void si_so_target_destroy(struct pipe_context *ctx,
  73                                  struct pipe_stream_output_target *target)
  74 {
  75         struct si_streamout_target *t = (struct si_streamout_target*)target;
  76         pipe_resource_reference(&t->b.buffer, NULL);
  77         r600_resource_reference(&t->buf_filled_size, NULL);
  78         FREE(t);
  79 }
  80
  81 void si_streamout_buffers_dirty(struct si_context *sctx)
  82 {
  83         if (!sctx->streamout.enabled_mask)
  84                 return;
  85
  86         si_mark_atom_dirty(sctx, &sctx->atoms.s.streamout_begin);
  87         si_set_streamout_enable(sctx, true);
  88 }
  89
  90 static void si_set_streamout_targets(struct pipe_context *ctx,
  91                                      unsigned num_targets,
  92                                      struct pipe_stream_output_target **targets,
  93                                      const unsigned *offsets)
  94 {
  95         struct si_context *sctx = (struct si_context *)ctx;
  96         struct si_buffer_resources *buffers = &sctx->rw_buffers;
  97         struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
  98         unsigned old_num_targets = sctx->streamout.num_targets;
  99         unsigned i, bufidx;
 100
 101         /* We are going to unbind the buffers. Mark which caches need to be flushed. */
 102         if (sctx->streamout.num_targets && sctx->streamout.begin_emitted) {
 103                 /* Since streamout uses vector writes which go through TC L2
 104                  * and most other clients can use TC L2 as well, we don't need
 105                  * to flush it.
 106                  *
 107                  * The only cases which requires flushing it is VGT DMA index
 108                  * fetching (on <= CIK) and indirect draw data, which are rare
 109                  * cases. Thus, flag the TC L2 dirtiness in the resource and
 110                  * handle it at draw call time.
 111                  */
 112                 for (i = 0; i < sctx->streamout.num_targets; i++)
 113                         if (sctx->streamout.targets[i])
 114                                 r600_resource(sctx->streamout.targets[i]->b.buffer)->TC_L2_dirty = true;
 115
 116                 /* Invalidate the scalar cache in case a streamout buffer is
 117                  * going to be used as a constant buffer.
 118                  *
 119                  * Invalidate TC L1, because streamout bypasses it (done by
 120                  * setting GLC=1 in the store instruction), but it can contain
 121                  * outdated data of streamout buffers.
 122                  *
 123                  * VS_PARTIAL_FLUSH is required if the buffers are going to be
 124                  * used as an input immediately.
 125                  */
 126                 sctx->flags |= SI_CONTEXT_INV_SMEM_L1 |
 127                                  SI_CONTEXT_INV_VMEM_L1 |
 128                                  SI_CONTEXT_VS_PARTIAL_FLUSH;
 129         }
 130
 131         /* All readers of the streamout targets need to be finished before we can
 132          * start writing to the targets.
 133          */
 134         if (num_targets)
 135                 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
 136                                  SI_CONTEXT_CS_PARTIAL_FLUSH;
 137
 138         /* Streamout buffers must be bound in 2 places:
 139          * 1) in VGT by setting the VGT_STRMOUT registers
 140          * 2) as shader resources
 141          */
 142
 143         /* Stop streamout. */
 144         if (sctx->streamout.num_targets && sctx->streamout.begin_emitted)
 145                 si_emit_streamout_end(sctx);
 146
 147         /* Set the new targets. */
 148         unsigned enabled_mask = 0, append_bitmask = 0;
 149         for (i = 0; i < num_targets; i++) {
 150                 si_so_target_reference(&sctx->streamout.targets[i], targets[i]);
 151                 if (!targets[i])
 152                         continue;
 153
 154                 si_context_add_resource_size(sctx, targets[i]->buffer);
 155                 enabled_mask |= 1 << i;
 156
 157                 if (offsets[i] == ((unsigned)-1))
 158                         append_bitmask |= 1 << i;
 159         }
 160
 161         for (; i < sctx->streamout.num_targets; i++)
 162                 si_so_target_reference(&sctx->streamout.targets[i], NULL);
 163
 164         sctx->streamout.enabled_mask = enabled_mask;
 165         sctx->streamout.num_targets = num_targets;
 166         sctx->streamout.append_bitmask = append_bitmask;
 167
 168         /* Update dirty state bits. */
 169         if (num_targets) {
 170                 si_streamout_buffers_dirty(sctx);
 171         } else {
 172                 si_set_atom_dirty(sctx, &sctx->atoms.s.streamout_begin, false);
 173                 si_set_streamout_enable(sctx, false);
 174         }
 175
 176         /* Set the shader resources.*/
 177         for (i = 0; i < num_targets; i++) {
 178                 bufidx = SI_VS_STREAMOUT_BUF0 + i;
 179
 180                 if (targets[i]) {
 181                         struct pipe_resource *buffer = targets[i]->buffer;
 182                         uint64_t va = r600_resource(buffer)->gpu_address;
 183
 184                         /* Set the descriptor.
 185                          *
 186                          * On VI, the format must be non-INVALID, otherwise
 187                          * the buffer will be considered not bound and store
 188                          * instructions will be no-ops.
 189                          */
 190                         uint32_t *desc = descs->list + bufidx*4;
 191                         desc[0] = va;
 192                         desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
 193                         desc[2] = 0xffffffff;
 194                         desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
 195                                   S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
 196                                   S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
 197                                   S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
 198                                   S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
 199
 200                         /* Set the resource. */
 201                         pipe_resource_reference(&buffers->buffers[bufidx],
 202                                                 buffer);
 203                         radeon_add_to_gfx_buffer_list_check_mem(sctx,
 204                                                             (struct r600_resource*)buffer,
 205                                                             buffers->shader_usage,
 206                                                             RADEON_PRIO_SHADER_RW_BUFFER,
 207                                                             true);
 208                         r600_resource(buffer)->bind_history |= PIPE_BIND_STREAM_OUTPUT;
 209
 210                         buffers->enabled_mask |= 1u << bufidx;
 211                 } else {
 212                         /* Clear the descriptor and unset the resource. */
 213                         memset(descs->list + bufidx*4, 0,
 214                                sizeof(uint32_t) * 4);
 215                         pipe_resource_reference(&buffers->buffers[bufidx],
 216                                                 NULL);
 217                         buffers->enabled_mask &= ~(1u << bufidx);
 218                 }
 219         }
 220         for (; i < old_num_targets; i++) {
 221                 bufidx = SI_VS_STREAMOUT_BUF0 + i;
 222                 /* Clear the descriptor and unset the resource. */
 223                 memset(descs->list + bufidx*4, 0, sizeof(uint32_t) * 4);
 224                 pipe_resource_reference(&buffers->buffers[bufidx], NULL);
 225                 buffers->enabled_mask &= ~(1u << bufidx);
 226         }
 227
 228         sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
 229 }
 230
 231 static void si_flush_vgt_streamout(struct si_context *sctx)
 232 {
 233         struct radeon_winsys_cs *cs = sctx->gfx_cs;
 234         unsigned reg_strmout_cntl;
 235
 236         /* The register is at different places on different ASICs. */
 237         if (sctx->chip_class >= CIK) {
 238                 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
 239                 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
 240         } else {
 241                 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
 242                 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
 243         }
 244
 245         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 246         radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
 247
 248         radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
 249         radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
 250         radeon_emit(cs, reg_strmout_cntl >> 2);  /* register */
 251         radeon_emit(cs, 0);
 252         radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
 253         radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
 254         radeon_emit(cs, 4); /* poll interval */
 255 }
 256
 257 static void si_emit_streamout_begin(struct si_context *sctx)
 258 {
 259         struct radeon_winsys_cs *cs = sctx->gfx_cs;
 260         struct si_streamout_target **t = sctx->streamout.targets;
 261         uint16_t *stride_in_dw = sctx->streamout.stride_in_dw;
 262         unsigned i;
 263
 264         si_flush_vgt_streamout(sctx);
 265
 266         for (i = 0; i < sctx->streamout.num_targets; i++) {
 267                 if (!t[i])
 268                         continue;
 269
 270                 t[i]->stride_in_dw = stride_in_dw[i];
 271
 272                 /* SI binds streamout buffers as shader resources.
 273                  * VGT only counts primitives and tells the shader
 274                  * through SGPRs what to do. */
 275                 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
 276                 radeon_emit(cs, (t[i]->b.buffer_offset +
 277                                  t[i]->b.buffer_size) >> 2);    /* BUFFER_SIZE (in DW) */
 278                 radeon_emit(cs, stride_in_dw[i]);               /* VTX_STRIDE (in DW) */
 279
 280                 if (sctx->streamout.append_bitmask & (1 << i) && t[i]->buf_filled_size_valid) {
 281                         uint64_t va = t[i]->buf_filled_size->gpu_address +
 282                                       t[i]->buf_filled_size_offset;
 283
 284                         /* Append. */
 285                         radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
 286                         radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
 287                                     STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
 288                         radeon_emit(cs, 0); /* unused */
 289                         radeon_emit(cs, 0); /* unused */
 290                         radeon_emit(cs, va); /* src address lo */
 291                         radeon_emit(cs, va >> 32); /* src address hi */
 292
 293                         radeon_add_to_buffer_list(sctx,  sctx->gfx_cs,
 294                                                   t[i]->buf_filled_size,
 295                                                   RADEON_USAGE_READ,
 296                                                   RADEON_PRIO_SO_FILLED_SIZE);
 297                 } else {
 298                         /* Start from the beginning. */
 299                         radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
 300                         radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
 301                                     STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
 302                         radeon_emit(cs, 0); /* unused */
 303                         radeon_emit(cs, 0); /* unused */
 304                         radeon_emit(cs, t[i]->b.buffer_offset >> 2); /* buffer offset in DW */
 305                         radeon_emit(cs, 0); /* unused */
 306                 }
 307         }
 308
 309         sctx->streamout.begin_emitted = true;
 310 }
 311
 312 void si_emit_streamout_end(struct si_context *sctx)
 313 {
 314         struct radeon_winsys_cs *cs = sctx->gfx_cs;
 315         struct si_streamout_target **t = sctx->streamout.targets;
 316         unsigned i;
 317         uint64_t va;
 318
 319         si_flush_vgt_streamout(sctx);
 320
 321         for (i = 0; i < sctx->streamout.num_targets; i++) {
 322                 if (!t[i])
 323                         continue;
 324
 325                 va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset;
 326                 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
 327                 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
 328                             STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
 329                             STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
 330                 radeon_emit(cs, va);     /* dst address lo */
 331                 radeon_emit(cs, va >> 32); /* dst address hi */
 332                 radeon_emit(cs, 0); /* unused */
 333                 radeon_emit(cs, 0); /* unused */
 334
 335                 radeon_add_to_buffer_list(sctx,  sctx->gfx_cs,
 336                                           t[i]->buf_filled_size,
 337                                           RADEON_USAGE_WRITE,
 338                                           RADEON_PRIO_SO_FILLED_SIZE);
 339
 340                 /* Zero the buffer size. The counters (primitives generated,
 341                  * primitives emitted) may be enabled even if there is not
 342                  * buffer bound. This ensures that the primitives-emitted query
 343                  * won't increment. */
 344                 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
 345
 346                 t[i]->buf_filled_size_valid = true;
 347         }
 348
 349         sctx->streamout.begin_emitted = false;
 350 }
 351
 352 /* STREAMOUT CONFIG DERIVED STATE
 353  *
 354  * Streamout must be enabled for the PRIMITIVES_GENERATED query to work.
 355  * The buffer mask is an independent state, so no writes occur if there
 356  * are no buffers bound.
 357  */
 358
 359 static void si_emit_streamout_enable(struct si_context *sctx)
 360 {
 361         radeon_set_context_reg_seq(sctx->gfx_cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
 362         radeon_emit(sctx->gfx_cs,
 363                     S_028B94_STREAMOUT_0_EN(si_get_strmout_en(sctx)) |
 364                     S_028B94_RAST_STREAM(0) |
 365                     S_028B94_STREAMOUT_1_EN(si_get_strmout_en(sctx)) |
 366                     S_028B94_STREAMOUT_2_EN(si_get_strmout_en(sctx)) |
 367                     S_028B94_STREAMOUT_3_EN(si_get_strmout_en(sctx)));
 368         radeon_emit(sctx->gfx_cs,
 369                     sctx->streamout.hw_enabled_mask &
 370                     sctx->streamout.enabled_stream_buffers_mask);
 371 }
 372
 373 static void si_set_streamout_enable(struct si_context *sctx, bool enable)
 374 {
 375         bool old_strmout_en = si_get_strmout_en(sctx);
 376         unsigned old_hw_enabled_mask = sctx->streamout.hw_enabled_mask;
 377
 378         sctx->streamout.streamout_enabled = enable;
 379
 380         sctx->streamout.hw_enabled_mask = sctx->streamout.enabled_mask |
 381                                           (sctx->streamout.enabled_mask << 4) |
 382                                           (sctx->streamout.enabled_mask << 8) |
 383                                           (sctx->streamout.enabled_mask << 12);
 384
 385         if ((old_strmout_en != si_get_strmout_en(sctx)) ||
 386             (old_hw_enabled_mask != sctx->streamout.hw_enabled_mask))
 387                 si_mark_atom_dirty(sctx, &sctx->atoms.s.streamout_enable);
 388 }
 389
 390 void si_update_prims_generated_query_state(struct si_context *sctx,
 391                                            unsigned type, int diff)
 392 {
 393         if (type == PIPE_QUERY_PRIMITIVES_GENERATED) {
 394                 bool old_strmout_en = si_get_strmout_en(sctx);
 395
 396                 sctx->streamout.num_prims_gen_queries += diff;
 397                 assert(sctx->streamout.num_prims_gen_queries >= 0);
 398
 399                 sctx->streamout.prims_gen_query_enabled =
 400                         sctx->streamout.num_prims_gen_queries != 0;
 401
 402                 if (old_strmout_en != si_get_strmout_en(sctx))
 403                         si_mark_atom_dirty(sctx, &sctx->atoms.s.streamout_enable);
 404         }
 405 }
 406
 407 void si_init_streamout_functions(struct si_context *sctx)
 408 {
 409         sctx->b.create_stream_output_target = si_create_so_target;
 410         sctx->b.stream_output_target_destroy = si_so_target_destroy;
 411         sctx->b.set_stream_output_targets = si_set_streamout_targets;
 412         sctx->atoms.s.streamout_begin.emit = si_emit_streamout_begin;
 413         sctx->atoms.s.streamout_enable.emit = si_emit_streamout_enable;
 414 }