src/gallium/drivers/radeonsi/si_state_streamout.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #include "radeonsi_pipe.h"
  28 #include "si_state.h"
  29
  30 /*
  31  * Stream out
  32  */
  33
  34 #if 0
  35 void si_context_streamout_begin(struct r600_context *ctx)
  36 {
  37         struct radeon_winsys_cs *cs = ctx->cs;
  38         struct si_so_target **t = ctx->so_targets;
  39         unsigned *strides = ctx->vs_shader_so_strides;
  40         unsigned buffer_en, i;
  41
  42         buffer_en = (ctx->num_so_targets >= 1 && t[0] ? 1 : 0) |
  43                     (ctx->num_so_targets >= 2 && t[1] ? 2 : 0) |
  44                     (ctx->num_so_targets >= 3 && t[2] ? 4 : 0) |
  45                     (ctx->num_so_targets >= 4 && t[3] ? 8 : 0);
  46
  47         ctx->num_cs_dw_streamout_end =
  48                 12 + /* flush_vgt_streamout */
  49                 util_bitcount(buffer_en) * 8 +
  50                 3;
  51
  52         si_need_cs_space(ctx,
  53                            12 + /* flush_vgt_streamout */
  54                            6 + /* enables */
  55                            util_bitcount(buffer_en & ctx->streamout_append_bitmask) * 8 +
  56                            util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 +
  57                            ctx->num_cs_dw_streamout_end, TRUE);
  58
  59         evergreen_flush_vgt_streamout(ctx);
  60         evergreen_set_streamout_enable(ctx, buffer_en);
  61
  62         for (i = 0; i < ctx->num_so_targets; i++) {
  63 #if 0
  64                 if (t[i]) {
  65                         t[i]->stride = strides[i];
  66                         t[i]->so_index = i;
  67
  68                         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 3, 0);
  69                         cs->buf[cs->cdw++] = (R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 +
  70                                                         16*i - SI_CONTEXT_REG_OFFSET) >> 2;
  71                         cs->buf[cs->cdw++] = (t[i]->b.buffer_offset +
  72                                                         t[i]->b.buffer_size) >> 2; /* BUFFER_SIZE (in DW) */
  73                         cs->buf[cs->cdw++] = strides[i] >> 2;              /* VTX_STRIDE (in DW) */
  74                         cs->buf[cs->cdw++] = 0;                    /* BUFFER_BASE */
  75
  76                         cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
  77                         cs->buf[cs->cdw++] =
  78                                 si_context_bo_reloc(ctx, si_resource(t[i]->b.buffer),
  79                                                       RADEON_USAGE_WRITE);
  80
  81                         if (ctx->streamout_append_bitmask & (1 << i)) {
  82                                 /* Append. */
  83                                 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
  84                                 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
  85                                                                STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM); /* control */
  86                                 cs->buf[cs->cdw++] = 0; /* unused */
  87                                 cs->buf[cs->cdw++] = 0; /* unused */
  88                                 cs->buf[cs->cdw++] = 0; /* src address lo */
  89                                 cs->buf[cs->cdw++] = 0; /* src address hi */
  90
  91                                 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
  92                                 cs->buf[cs->cdw++] =
  93                                         si_context_bo_reloc(ctx,  t[i]->filled_size,
  94                                                               RADEON_USAGE_READ);
  95                         } else {
  96                                 /* Start from the beginning. */
  97                                 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
  98                                 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
  99                                                                STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET); /* control */
 100                                 cs->buf[cs->cdw++] = 0; /* unused */
 101                                 cs->buf[cs->cdw++] = 0; /* unused */
 102                                 cs->buf[cs->cdw++] = t[i]->b.buffer_offset >> 2; /* buffer offset in DW */
 103                                 cs->buf[cs->cdw++] = 0; /* unused */
 104                         }
 105                 }
 106 #endif
 107         }
 108 }
 109
 110 void si_context_streamout_end(struct r600_context *ctx)
 111 {
 112         struct radeon_winsys_cs *cs = ctx->cs;
 113         struct si_so_target **t = ctx->so_targets;
 114         unsigned i, flush_flags = 0;
 115
 116         evergreen_flush_vgt_streamout(ctx);
 117
 118         for (i = 0; i < ctx->num_so_targets; i++) {
 119 #if 0
 120                 if (t[i]) {
 121                         cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
 122                         cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
 123                                                        STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
 124                                                        STRMOUT_STORE_BUFFER_FILLED_SIZE; /* control */
 125                         cs->buf[cs->cdw++] = 0; /* dst address lo */
 126                         cs->buf[cs->cdw++] = 0; /* dst address hi */
 127                         cs->buf[cs->cdw++] = 0; /* unused */
 128                         cs->buf[cs->cdw++] = 0; /* unused */
 129
 130                         cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
 131                         cs->buf[cs->cdw++] =
 132                                 si_context_bo_reloc(ctx,  t[i]->filled_size,
 133                                                       RADEON_USAGE_WRITE);
 134
 135                         flush_flags |= S_0085F0_SO0_DEST_BASE_ENA(1) << i;
 136                 }
 137 #endif
 138         }
 139
 140         evergreen_set_streamout_enable(ctx, 0);
 141
 142         ctx->atom_surface_sync.flush_flags |= flush_flags;
 143         si_atom_dirty(ctx, &ctx->atom_surface_sync.atom);
 144
 145         ctx->num_cs_dw_streamout_end = 0;
 146
 147         /* XXX print some debug info */
 148         for (i = 0; i < ctx->num_so_targets; i++) {
 149                 if (!t[i])
 150                         continue;
 151
 152                 uint32_t *ptr = ctx->ws->buffer_map(t[i]->filled_size->cs_buf, ctx->cs, RADEON_USAGE_READ);
 153                 printf("FILLED_SIZE%i: %u\n", i, *ptr);
 154                 ctx->ws->buffer_unmap(t[i]->filled_size->cs_buf);
 155         }
 156 }
 157
 158 void evergreen_flush_vgt_streamout(struct si_context *ctx)
 159 {
 160         struct radeon_winsys_cs *cs = ctx->cs;
 161
 162         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0);
 163         cs->buf[cs->cdw++] = (R_0084FC_CP_STRMOUT_CNTL - SI_CONFIG_REG_OFFSET) >> 2;
 164         cs->buf[cs->cdw++] = 0;
 165
 166         cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
 167         cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
 168
 169         cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
 170         cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
 171         cs->buf[cs->cdw++] = R_0084FC_CP_STRMOUT_CNTL >> 2;  /* register */
 172         cs->buf[cs->cdw++] = 0;
 173         cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* reference value */
 174         cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* mask */
 175         cs->buf[cs->cdw++] = 4; /* poll interval */
 176 }
 177
 178 void evergreen_set_streamout_enable(struct si_context *ctx, unsigned buffer_enable_bit)
 179 {
 180         struct radeon_winsys_cs *cs = ctx->cs;
 181
 182         if (buffer_enable_bit) {
 183                 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
 184                 cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
 185                 cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(1);
 186
 187                 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
 188                 cs->buf[cs->cdw++] = (R_028B98_VGT_STRMOUT_BUFFER_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
 189                 cs->buf[cs->cdw++] = S_028B98_STREAM_0_BUFFER_EN(buffer_enable_bit);
 190         } else {
 191                 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
 192                 cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
 193                 cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(0);
 194         }
 195 }
 196
 197 #endif
 198
 199 struct pipe_stream_output_target *
 200 si_create_so_target(struct pipe_context *ctx,
 201                     struct pipe_resource *buffer,
 202                     unsigned buffer_offset,
 203                     unsigned buffer_size)
 204 {
 205 #if 0
 206         struct si_context *rctx = (struct r600_context *)ctx;
 207         struct si_so_target *t;
 208         void *ptr;
 209
 210         t = CALLOC_STRUCT(si_so_target);
 211         if (!t) {
 212                 return NULL;
 213         }
 214
 215         t->b.reference.count = 1;
 216         t->b.context = ctx;
 217         pipe_resource_reference(&t->b.buffer, buffer);
 218         t->b.buffer_offset = buffer_offset;
 219         t->b.buffer_size = buffer_size;
 220
 221         t->filled_size = si_resource_create_custom(ctx->screen, PIPE_USAGE_STATIC, 4);
 222         ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
 223         memset(ptr, 0, t->filled_size->buf->size);
 224         rctx->ws->buffer_unmap(t->filled_size->cs_buf);
 225
 226         return &t->b;
 227 #endif
 228         return NULL;
 229 }
 230
 231 void si_so_target_destroy(struct pipe_context *ctx,
 232                           struct pipe_stream_output_target *target)
 233 {
 234 #if 0
 235         struct si_so_target *t = (struct r600_so_target*)target;
 236         pipe_resource_reference(&t->b.buffer, NULL);
 237         si_resource_reference(&t->filled_size, NULL);
 238         FREE(t);
 239 #endif
 240 }
 241
 242 void si_set_so_targets(struct pipe_context *ctx,
 243                        unsigned num_targets,
 244                        struct pipe_stream_output_target **targets,
 245                        unsigned append_bitmask)
 246 {
 247         assert(num_targets == 0);
 248 #if 0
 249         struct si_context *rctx = (struct r600_context *)ctx;
 250         unsigned i;
 251
 252         /* Stop streamout. */
 253         if (rctx->num_so_targets) {
 254                 si_context_streamout_end(rctx);
 255         }
 256
 257         /* Set the new targets. */
 258         for (i = 0; i < num_targets; i++) {
 259                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
 260         }
 261         for (; i < rctx->num_so_targets; i++) {
 262                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
 263         }
 264
 265         rctx->num_so_targets = num_targets;
 266         rctx->streamout_start = num_targets != 0;
 267         rctx->streamout_append_bitmask = append_bitmask;
 268 #endif
 269 }