2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
26 #include "util/u_upload_mgr.h"
27 #include "util/u_viewport.h"
29 #define SI_MAX_SCISSOR 16384
31 void si_update_ngg_small_prim_precision(struct si_context
*ctx
)
33 if (!ctx
->screen
->use_ngg_culling
)
36 /* Set VS_STATE.SMALL_PRIM_PRECISION for NGG culling. */
37 unsigned num_samples
= ctx
->framebuffer
.nr_samples
;
38 unsigned quant_mode
= ctx
->viewports
.as_scissor
[0].quant_mode
;
41 if (quant_mode
== SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH
)
42 precision
= num_samples
/ 4096.0;
43 else if (quant_mode
== SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH
)
44 precision
= num_samples
/ 1024.0;
46 precision
= num_samples
/ 256.0;
48 ctx
->current_vs_state
&= C_VS_STATE_SMALL_PRIM_PRECISION
;
49 ctx
->current_vs_state
|= S_VS_STATE_SMALL_PRIM_PRECISION(fui(precision
) >> 23);
52 void si_get_small_prim_cull_info(struct si_context
*sctx
, struct si_small_prim_cull_info
*out
)
54 /* This is needed by the small primitive culling, because it's done
57 struct si_small_prim_cull_info info
;
58 unsigned num_samples
= sctx
->framebuffer
.nr_samples
;
59 assert(num_samples
>= 1);
61 info
.scale
[0] = sctx
->viewports
.states
[0].scale
[0];
62 info
.scale
[1] = sctx
->viewports
.states
[0].scale
[1];
63 info
.translate
[0] = sctx
->viewports
.states
[0].translate
[0];
64 info
.translate
[1] = sctx
->viewports
.states
[0].translate
[1];
66 /* The viewport shouldn't flip the X axis for the small prim culling to work. */
67 assert(-info
.scale
[0] + info
.translate
[0] <= info
.scale
[0] + info
.translate
[0]);
69 /* If the Y axis is inverted (OpenGL default framebuffer), reverse it.
70 * This is because the viewport transformation inverts the clip space
71 * bounding box, so min becomes max, which breaks small primitive
74 if (sctx
->viewports
.y_inverted
) {
75 info
.scale
[1] = -info
.scale
[1];
76 info
.translate
[1] = -info
.translate
[1];
79 /* Scale the framebuffer up, so that samples become pixels and small
80 * primitive culling is the same for all sample counts.
81 * This only works with the standard DX sample positions, because
82 * the samples are evenly spaced on both X and Y axes.
84 for (unsigned i
= 0; i
< 2; i
++) {
85 info
.scale
[i
] *= num_samples
;
86 info
.translate
[i
] *= num_samples
;
91 static void si_set_scissor_states(struct pipe_context
*pctx
, unsigned start_slot
,
92 unsigned num_scissors
, const struct pipe_scissor_state
*state
)
94 struct si_context
*ctx
= (struct si_context
*)pctx
;
97 for (i
= 0; i
< num_scissors
; i
++)
98 ctx
->scissors
[start_slot
+ i
] = state
[i
];
100 if (!ctx
->queued
.named
.rasterizer
->scissor_enable
)
103 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.scissors
);
106 /* Since the guard band disables clipping, we have to clip per-pixel
109 static void si_get_scissor_from_viewport(struct si_context
*ctx
,
110 const struct pipe_viewport_state
*vp
,
111 struct si_signed_scissor
*scissor
)
113 float tmp
, minx
, miny
, maxx
, maxy
;
115 /* Convert (-1, -1) and (1, 1) from clip space into window space. */
116 minx
= -vp
->scale
[0] + vp
->translate
[0];
117 miny
= -vp
->scale
[1] + vp
->translate
[1];
118 maxx
= vp
->scale
[0] + vp
->translate
[0];
119 maxy
= vp
->scale
[1] + vp
->translate
[1];
121 /* Handle inverted viewports. */
133 /* Convert to integer and round up the max bounds. */
134 scissor
->minx
= minx
;
135 scissor
->miny
= miny
;
136 scissor
->maxx
= ceilf(maxx
);
137 scissor
->maxy
= ceilf(maxy
);
140 static void si_clamp_scissor(struct si_context
*ctx
, struct pipe_scissor_state
*out
,
141 struct si_signed_scissor
*scissor
)
143 out
->minx
= CLAMP(scissor
->minx
, 0, SI_MAX_SCISSOR
);
144 out
->miny
= CLAMP(scissor
->miny
, 0, SI_MAX_SCISSOR
);
145 out
->maxx
= CLAMP(scissor
->maxx
, 0, SI_MAX_SCISSOR
);
146 out
->maxy
= CLAMP(scissor
->maxy
, 0, SI_MAX_SCISSOR
);
149 static void si_clip_scissor(struct pipe_scissor_state
*out
, struct pipe_scissor_state
*clip
)
151 out
->minx
= MAX2(out
->minx
, clip
->minx
);
152 out
->miny
= MAX2(out
->miny
, clip
->miny
);
153 out
->maxx
= MIN2(out
->maxx
, clip
->maxx
);
154 out
->maxy
= MIN2(out
->maxy
, clip
->maxy
);
157 static void si_scissor_make_union(struct si_signed_scissor
*out
, struct si_signed_scissor
*in
)
159 out
->minx
= MIN2(out
->minx
, in
->minx
);
160 out
->miny
= MIN2(out
->miny
, in
->miny
);
161 out
->maxx
= MAX2(out
->maxx
, in
->maxx
);
162 out
->maxy
= MAX2(out
->maxy
, in
->maxy
);
163 out
->quant_mode
= MIN2(out
->quant_mode
, in
->quant_mode
);
166 static void si_emit_one_scissor(struct si_context
*ctx
, struct radeon_cmdbuf
*cs
,
167 struct si_signed_scissor
*vp_scissor
,
168 struct pipe_scissor_state
*scissor
)
170 struct pipe_scissor_state final
;
172 if (ctx
->vs_disables_clipping_viewport
) {
173 final
.minx
= final
.miny
= 0;
174 final
.maxx
= final
.maxy
= SI_MAX_SCISSOR
;
176 si_clamp_scissor(ctx
, &final
, vp_scissor
);
180 si_clip_scissor(&final
, scissor
);
182 /* Workaround for a hw bug on GFX6 that occurs when PA_SU_HARDWARE_-
183 * SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
185 if (ctx
->chip_class
== GFX6
&& (final
.maxx
== 0 || final
.maxy
== 0)) {
186 radeon_emit(cs
, S_028250_TL_X(1) | S_028250_TL_Y(1) | S_028250_WINDOW_OFFSET_DISABLE(1));
187 radeon_emit(cs
, S_028254_BR_X(1) | S_028254_BR_Y(1));
191 radeon_emit(cs
, S_028250_TL_X(final
.minx
) | S_028250_TL_Y(final
.miny
) |
192 S_028250_WINDOW_OFFSET_DISABLE(1));
193 radeon_emit(cs
, S_028254_BR_X(final
.maxx
) | S_028254_BR_Y(final
.maxy
));
196 #define MAX_PA_SU_HARDWARE_SCREEN_OFFSET 8176
198 static void si_emit_guardband(struct si_context
*ctx
)
200 const struct si_state_rasterizer
*rs
= ctx
->queued
.named
.rasterizer
;
201 struct si_signed_scissor vp_as_scissor
;
202 struct pipe_viewport_state vp
;
203 float left
, top
, right
, bottom
, max_range
, guardband_x
, guardband_y
;
204 float discard_x
, discard_y
;
206 if (ctx
->vs_writes_viewport_index
) {
207 /* Shaders can draw to any viewport. Make a union of all
209 vp_as_scissor
= ctx
->viewports
.as_scissor
[0];
210 for (unsigned i
= 1; i
< SI_MAX_VIEWPORTS
; i
++) {
211 si_scissor_make_union(&vp_as_scissor
, &ctx
->viewports
.as_scissor
[i
]);
214 vp_as_scissor
= ctx
->viewports
.as_scissor
[0];
217 /* Blits don't set the viewport state. The vertex shader determines
218 * the viewport size by scaling the coordinates, so we don't know
219 * how large the viewport is. Assume the worst case.
221 if (ctx
->vs_disables_clipping_viewport
)
222 vp_as_scissor
.quant_mode
= SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH
;
224 /* Determine the optimal hardware screen offset to center the viewport
225 * within the viewport range in order to maximize the guardband size.
227 int hw_screen_offset_x
= (vp_as_scissor
.maxx
+ vp_as_scissor
.minx
) / 2;
228 int hw_screen_offset_y
= (vp_as_scissor
.maxy
+ vp_as_scissor
.miny
) / 2;
230 /* GFX6-GFX7 need to align the offset to an ubertile consisting of all SEs. */
231 const unsigned hw_screen_offset_alignment
=
232 ctx
->chip_class
>= GFX8
? 16 : MAX2(ctx
->screen
->se_tile_repeat
, 16);
234 /* Indexed by quantization modes */
235 static int max_viewport_size
[] = {65535, 16383, 4095};
237 /* Ensure that the whole viewport stays representable in
238 * absolute coordinates.
239 * See comment in si_set_viewport_states.
241 assert(vp_as_scissor
.maxx
<= max_viewport_size
[vp_as_scissor
.quant_mode
] &&
242 vp_as_scissor
.maxy
<= max_viewport_size
[vp_as_scissor
.quant_mode
]);
244 hw_screen_offset_x
= CLAMP(hw_screen_offset_x
, 0, MAX_PA_SU_HARDWARE_SCREEN_OFFSET
);
245 hw_screen_offset_y
= CLAMP(hw_screen_offset_y
, 0, MAX_PA_SU_HARDWARE_SCREEN_OFFSET
);
247 /* Align the screen offset by dropping the low bits. */
248 hw_screen_offset_x
&= ~(hw_screen_offset_alignment
- 1);
249 hw_screen_offset_y
&= ~(hw_screen_offset_alignment
- 1);
251 /* Apply the offset to center the viewport and maximize the guardband. */
252 vp_as_scissor
.minx
-= hw_screen_offset_x
;
253 vp_as_scissor
.maxx
-= hw_screen_offset_x
;
254 vp_as_scissor
.miny
-= hw_screen_offset_y
;
255 vp_as_scissor
.maxy
-= hw_screen_offset_y
;
257 /* Reconstruct the viewport transformation from the scissor. */
258 vp
.translate
[0] = (vp_as_scissor
.minx
+ vp_as_scissor
.maxx
) / 2.0;
259 vp
.translate
[1] = (vp_as_scissor
.miny
+ vp_as_scissor
.maxy
) / 2.0;
260 vp
.scale
[0] = vp_as_scissor
.maxx
- vp
.translate
[0];
261 vp
.scale
[1] = vp_as_scissor
.maxy
- vp
.translate
[1];
263 /* Treat a 0x0 viewport as 1x1 to prevent division by zero. */
264 if (vp_as_scissor
.minx
== vp_as_scissor
.maxx
)
266 if (vp_as_scissor
.miny
== vp_as_scissor
.maxy
)
269 /* Find the biggest guard band that is inside the supported viewport
270 * range. The guard band is specified as a horizontal and vertical
271 * distance from (0,0) in clip space.
273 * This is done by applying the inverse viewport transformation
274 * on the viewport limits to get those limits in clip space.
276 * The viewport range is [-max_viewport_size/2, max_viewport_size/2].
278 assert(vp_as_scissor
.quant_mode
< ARRAY_SIZE(max_viewport_size
));
279 max_range
= max_viewport_size
[vp_as_scissor
.quant_mode
] / 2;
280 left
= (-max_range
- vp
.translate
[0]) / vp
.scale
[0];
281 right
= (max_range
- vp
.translate
[0]) / vp
.scale
[0];
282 top
= (-max_range
- vp
.translate
[1]) / vp
.scale
[1];
283 bottom
= (max_range
- vp
.translate
[1]) / vp
.scale
[1];
285 assert(left
<= -1 && top
<= -1 && right
>= 1 && bottom
>= 1);
287 guardband_x
= MIN2(-left
, right
);
288 guardband_y
= MIN2(-top
, bottom
);
293 if (unlikely(util_prim_is_points_or_lines(ctx
->current_rast_prim
))) {
294 /* When rendering wide points or lines, we need to be more
295 * conservative about when to discard them entirely. */
298 if (ctx
->current_rast_prim
== PIPE_PRIM_POINTS
)
299 pixels
= rs
->max_point_size
;
301 pixels
= rs
->line_width
;
303 /* Add half the point size / line width */
304 discard_x
+= pixels
/ (2.0 * vp
.scale
[0]);
305 discard_y
+= pixels
/ (2.0 * vp
.scale
[1]);
307 /* Discard primitives that would lie entirely outside the clip
309 discard_x
= MIN2(discard_x
, guardband_x
);
310 discard_y
= MIN2(discard_y
, guardband_y
);
313 /* If any of the GB registers is updated, all of them must be updated.
314 * R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, R_028BEC_PA_CL_GB_VERT_DISC_ADJ
315 * R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ
317 unsigned initial_cdw
= ctx
->gfx_cs
->current
.cdw
;
318 radeon_opt_set_context_reg4(ctx
, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
,
319 SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ
, fui(guardband_y
), fui(discard_y
),
320 fui(guardband_x
), fui(discard_x
));
321 radeon_opt_set_context_reg(ctx
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
,
322 SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET
,
323 S_028234_HW_SCREEN_OFFSET_X(hw_screen_offset_x
>> 4) |
324 S_028234_HW_SCREEN_OFFSET_Y(hw_screen_offset_y
>> 4));
325 radeon_opt_set_context_reg(
326 ctx
, R_028BE4_PA_SU_VTX_CNTL
, SI_TRACKED_PA_SU_VTX_CNTL
,
327 S_028BE4_PIX_CENTER(rs
->half_pixel_center
) |
328 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
+ vp_as_scissor
.quant_mode
));
329 if (initial_cdw
!= ctx
->gfx_cs
->current
.cdw
)
330 ctx
->context_roll
= true;
332 si_update_ngg_small_prim_precision(ctx
);
335 static void si_emit_scissors(struct si_context
*ctx
)
337 struct radeon_cmdbuf
*cs
= ctx
->gfx_cs
;
338 struct pipe_scissor_state
*states
= ctx
->scissors
;
339 bool scissor_enabled
= ctx
->queued
.named
.rasterizer
->scissor_enable
;
341 /* The simple case: Only 1 viewport is active. */
342 if (!ctx
->vs_writes_viewport_index
) {
343 struct si_signed_scissor
*vp
= &ctx
->viewports
.as_scissor
[0];
345 radeon_set_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 2);
346 si_emit_one_scissor(ctx
, cs
, vp
, scissor_enabled
? &states
[0] : NULL
);
350 /* All registers in the array need to be updated if any of them is changed.
351 * This is a hardware requirement.
353 radeon_set_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, SI_MAX_VIEWPORTS
* 2);
354 for (unsigned i
= 0; i
< SI_MAX_VIEWPORTS
; i
++) {
355 si_emit_one_scissor(ctx
, cs
, &ctx
->viewports
.as_scissor
[i
],
356 scissor_enabled
? &states
[i
] : NULL
);
360 static void si_set_viewport_states(struct pipe_context
*pctx
, unsigned start_slot
,
361 unsigned num_viewports
, const struct pipe_viewport_state
*state
)
363 struct si_context
*ctx
= (struct si_context
*)pctx
;
366 for (i
= 0; i
< num_viewports
; i
++) {
367 unsigned index
= start_slot
+ i
;
368 struct si_signed_scissor
*scissor
= &ctx
->viewports
.as_scissor
[index
];
370 ctx
->viewports
.states
[index
] = state
[i
];
372 si_get_scissor_from_viewport(ctx
, &state
[i
], scissor
);
374 unsigned w
= scissor
->maxx
- scissor
->minx
;
375 unsigned h
= scissor
->maxy
- scissor
->miny
;
376 unsigned max_extent
= MAX2(w
, h
);
378 int max_corner
= MAX2(scissor
->maxx
, scissor
->maxy
);
380 unsigned center_x
= (scissor
->maxx
+ scissor
->minx
) / 2;
381 unsigned center_y
= (scissor
->maxy
+ scissor
->miny
) / 2;
382 unsigned max_center
= MAX2(center_x
, center_y
);
384 /* PA_SU_HARDWARE_SCREEN_OFFSET can't center viewports whose
385 * center start farther than MAX_PA_SU_HARDWARE_SCREEN_OFFSET.
386 * (for example, a 1x1 viewport in the lower right corner of
387 * 16Kx16K) Such viewports need a greater guardband, so they
388 * have to use a worse quantization mode.
390 unsigned distance_off_center
= MAX2(0, (int)max_center
- MAX_PA_SU_HARDWARE_SCREEN_OFFSET
);
391 max_extent
+= distance_off_center
;
393 /* Determine the best quantization mode (subpixel precision),
394 * but also leave enough space for the guardband.
396 * Note that primitive binning requires QUANT_MODE == 16_8 on Vega10
397 * and Raven1 for line and rectangle primitive types to work correctly.
398 * Always use 16_8 if primitive binning is possible to occur.
400 if ((ctx
->family
== CHIP_VEGA10
|| ctx
->family
== CHIP_RAVEN
) && ctx
->screen
->dpbb_allowed
)
401 max_extent
= 16384; /* Use QUANT_MODE == 16_8. */
403 /* Another constraint is that all coordinates in the viewport
404 * are representable in fixed point with respect to the
407 * It means that PA_SU_HARDWARE_SCREEN_OFFSET can't be given
408 * an offset that would make the upper corner of the viewport
409 * greater than the maximum representable number post
410 * quantization, ie 2^quant_bits.
412 * This does not matter for 14.10 and 16.8 formats since the
413 * offset is already limited at 8k, but it means we can't use
414 * 12.12 if we are drawing to some pixels outside the lower
415 * 4k x 4k of the render target.
418 if (max_extent
<= 1024 && max_corner
< 4096) /* 4K scanline area for guardband */
419 scissor
->quant_mode
= SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH
;
420 else if (max_extent
<= 4096) /* 16K scanline area for guardband */
421 scissor
->quant_mode
= SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH
;
422 else /* 64K scanline area for guardband */
423 scissor
->quant_mode
= SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH
;
426 if (start_slot
== 0) {
427 ctx
->viewports
.y_inverted
=
428 -state
->scale
[1] + state
->translate
[1] > state
->scale
[1] + state
->translate
[1];
431 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.viewports
);
432 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.guardband
);
433 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.scissors
);
436 static void si_emit_one_viewport(struct si_context
*ctx
, struct pipe_viewport_state
*state
)
438 struct radeon_cmdbuf
*cs
= ctx
->gfx_cs
;
440 radeon_emit(cs
, fui(state
->scale
[0]));
441 radeon_emit(cs
, fui(state
->translate
[0]));
442 radeon_emit(cs
, fui(state
->scale
[1]));
443 radeon_emit(cs
, fui(state
->translate
[1]));
444 radeon_emit(cs
, fui(state
->scale
[2]));
445 radeon_emit(cs
, fui(state
->translate
[2]));
448 static void si_emit_viewports(struct si_context
*ctx
)
450 struct radeon_cmdbuf
*cs
= ctx
->gfx_cs
;
451 struct pipe_viewport_state
*states
= ctx
->viewports
.states
;
453 if (ctx
->screen
->use_ngg_culling
) {
454 /* Set the viewport info for small primitive culling. */
455 struct si_small_prim_cull_info info
;
456 si_get_small_prim_cull_info(ctx
, &info
);
458 if (memcmp(&info
, &ctx
->last_small_prim_cull_info
, sizeof(info
))) {
461 /* Align to 256, because the address is shifted by 8 bits. */
462 u_upload_data(ctx
->b
.const_uploader
, 0, sizeof(info
), 256, &info
, &offset
,
463 (struct pipe_resource
**)&ctx
->small_prim_cull_info_buf
);
465 ctx
->small_prim_cull_info_address
= ctx
->small_prim_cull_info_buf
->gpu_address
+ offset
;
466 ctx
->last_small_prim_cull_info
= info
;
467 ctx
->small_prim_cull_info_dirty
= true;
470 if (ctx
->small_prim_cull_info_dirty
) {
471 /* This will end up in SGPR6 as (value << 8), shifted by the hw. */
472 radeon_add_to_buffer_list(ctx
, ctx
->gfx_cs
, ctx
->small_prim_cull_info_buf
,
473 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
);
474 radeon_set_sh_reg(ctx
->gfx_cs
, R_00B220_SPI_SHADER_PGM_LO_GS
,
475 ctx
->small_prim_cull_info_address
>> 8);
476 ctx
->small_prim_cull_info_dirty
= false;
480 /* The simple case: Only 1 viewport is active. */
481 if (!ctx
->vs_writes_viewport_index
) {
482 radeon_set_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE
, 6);
483 si_emit_one_viewport(ctx
, &states
[0]);
487 /* All registers in the array need to be updated if any of them is changed.
488 * This is a hardware requirement.
490 radeon_set_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE
+ 0, SI_MAX_VIEWPORTS
* 6);
491 for (unsigned i
= 0; i
< SI_MAX_VIEWPORTS
; i
++)
492 si_emit_one_viewport(ctx
, &states
[i
]);
495 static inline void si_viewport_zmin_zmax(const struct pipe_viewport_state
*vp
, bool halfz
,
496 bool window_space_position
, float *zmin
, float *zmax
)
498 if (window_space_position
) {
503 util_viewport_zmin_zmax(vp
, halfz
, zmin
, zmax
);
506 static void si_emit_depth_ranges(struct si_context
*ctx
)
508 struct radeon_cmdbuf
*cs
= ctx
->gfx_cs
;
509 struct pipe_viewport_state
*states
= ctx
->viewports
.states
;
510 bool clip_halfz
= ctx
->queued
.named
.rasterizer
->clip_halfz
;
511 bool window_space
= ctx
->vs_disables_clipping_viewport
;
514 /* The simple case: Only 1 viewport is active. */
515 if (!ctx
->vs_writes_viewport_index
) {
516 si_viewport_zmin_zmax(&states
[0], clip_halfz
, window_space
, &zmin
, &zmax
);
518 radeon_set_context_reg_seq(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
519 radeon_emit(cs
, fui(zmin
));
520 radeon_emit(cs
, fui(zmax
));
524 /* All registers in the array need to be updated if any of them is changed.
525 * This is a hardware requirement.
527 radeon_set_context_reg_seq(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
, SI_MAX_VIEWPORTS
* 2);
528 for (unsigned i
= 0; i
< SI_MAX_VIEWPORTS
; i
++) {
529 si_viewport_zmin_zmax(&states
[i
], clip_halfz
, window_space
, &zmin
, &zmax
);
530 radeon_emit(cs
, fui(zmin
));
531 radeon_emit(cs
, fui(zmax
));
535 static void si_emit_viewport_states(struct si_context
*ctx
)
537 si_emit_viewports(ctx
);
538 si_emit_depth_ranges(ctx
);
542 * This reacts to 2 state changes:
543 * - VS.writes_viewport_index
544 * - VS output position in window space (enable/disable)
546 * Normally, we only emit 1 viewport and 1 scissor if no shader is using
547 * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
548 * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
549 * called to emit the rest.
551 void si_update_vs_viewport_state(struct si_context
*ctx
)
553 struct si_shader_info
*info
= si_get_vs_info(ctx
);
554 bool vs_window_space
;
559 /* When the VS disables clipping and viewport transformation. */
560 vs_window_space
= info
->stage
== MESA_SHADER_VERTEX
&& info
->base
.vs
.window_space_position
;
562 if (ctx
->vs_disables_clipping_viewport
!= vs_window_space
) {
563 ctx
->vs_disables_clipping_viewport
= vs_window_space
;
564 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.scissors
);
565 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.viewports
);
568 /* Viewport index handling. */
569 if (ctx
->vs_writes_viewport_index
== info
->writes_viewport_index
)
572 /* This changes how the guardband is computed. */
573 ctx
->vs_writes_viewport_index
= info
->writes_viewport_index
;
574 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.guardband
);
576 /* Emit scissors and viewports that were enabled by having
577 * the ViewportIndex output.
579 if (info
->writes_viewport_index
) {
580 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.scissors
);
581 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.viewports
);
585 static void si_emit_window_rectangles(struct si_context
*sctx
)
587 /* There are four clipping rectangles. Their corner coordinates are inclusive.
588 * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending
589 * on whether the pixel is inside cliprects 0-3, respectively. For example,
590 * if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned
591 * the number 3 (binary 0011).
593 * If CLIPRECT_RULE & (1 << number), the pixel is rasterized.
595 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
596 static const unsigned outside
[4] = {
597 /* outside rectangle 0 */
598 V_02820C_OUT
| V_02820C_IN_1
| V_02820C_IN_2
| V_02820C_IN_21
| V_02820C_IN_3
|
599 V_02820C_IN_31
| V_02820C_IN_32
| V_02820C_IN_321
,
600 /* outside rectangles 0, 1 */
601 V_02820C_OUT
| V_02820C_IN_2
| V_02820C_IN_3
| V_02820C_IN_32
,
602 /* outside rectangles 0, 1, 2 */
603 V_02820C_OUT
| V_02820C_IN_3
,
604 /* outside rectangles 0, 1, 2, 3 */
607 const unsigned disabled
= 0xffff; /* all inside and outside cases */
608 unsigned num_rectangles
= sctx
->num_window_rectangles
;
609 struct pipe_scissor_state
*rects
= sctx
->window_rectangles
;
612 assert(num_rectangles
<= 4);
614 if (num_rectangles
== 0)
616 else if (sctx
->window_rectangles_include
)
617 rule
= ~outside
[num_rectangles
- 1];
619 rule
= outside
[num_rectangles
- 1];
621 radeon_opt_set_context_reg(sctx
, R_02820C_PA_SC_CLIPRECT_RULE
, SI_TRACKED_PA_SC_CLIPRECT_RULE
,
623 if (num_rectangles
== 0)
626 radeon_set_context_reg_seq(cs
, R_028210_PA_SC_CLIPRECT_0_TL
, num_rectangles
* 2);
627 for (unsigned i
= 0; i
< num_rectangles
; i
++) {
628 radeon_emit(cs
, S_028210_TL_X(rects
[i
].minx
) | S_028210_TL_Y(rects
[i
].miny
));
629 radeon_emit(cs
, S_028214_BR_X(rects
[i
].maxx
) | S_028214_BR_Y(rects
[i
].maxy
));
633 static void si_set_window_rectangles(struct pipe_context
*ctx
, bool include
,
634 unsigned num_rectangles
,
635 const struct pipe_scissor_state
*rects
)
637 struct si_context
*sctx
= (struct si_context
*)ctx
;
639 sctx
->num_window_rectangles
= num_rectangles
;
640 sctx
->window_rectangles_include
= include
;
641 if (num_rectangles
) {
642 memcpy(sctx
->window_rectangles
, rects
, sizeof(*rects
) * num_rectangles
);
645 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.window_rectangles
);
648 void si_init_viewport_functions(struct si_context
*ctx
)
650 ctx
->atoms
.s
.guardband
.emit
= si_emit_guardband
;
651 ctx
->atoms
.s
.scissors
.emit
= si_emit_scissors
;
652 ctx
->atoms
.s
.viewports
.emit
= si_emit_viewport_states
;
653 ctx
->atoms
.s
.window_rectangles
.emit
= si_emit_window_rectangles
;
655 ctx
->b
.set_scissor_states
= si_set_scissor_states
;
656 ctx
->b
.set_viewport_states
= si_set_viewport_states
;
657 ctx
->b
.set_window_rectangles
= si_set_window_rectangles
;
659 for (unsigned i
= 0; i
< 16; i
++)
660 ctx
->viewports
.as_scissor
[i
].quant_mode
= SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH
;