2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeon/r600_cs.h"
27 #include "util/u_viewport.h"
28 #include "tgsi/tgsi_scan.h"
30 #define SI_MAX_SCISSOR 16384
32 static void si_set_scissor_states(struct pipe_context
*pctx
,
34 unsigned num_scissors
,
35 const struct pipe_scissor_state
*state
)
37 struct si_context
*ctx
= (struct si_context
*)pctx
;
40 for (i
= 0; i
< num_scissors
; i
++)
41 ctx
->scissors
.states
[start_slot
+ i
] = state
[i
];
43 if (!ctx
->queued
.named
.rasterizer
||
44 !ctx
->queued
.named
.rasterizer
->scissor_enable
)
47 ctx
->scissors
.dirty_mask
|= ((1 << num_scissors
) - 1) << start_slot
;
48 si_mark_atom_dirty(ctx
, &ctx
->scissors
.atom
);
51 /* Since the guard band disables clipping, we have to clip per-pixel
54 static void si_get_scissor_from_viewport(struct si_context
*ctx
,
55 const struct pipe_viewport_state
*vp
,
56 struct si_signed_scissor
*scissor
)
58 float tmp
, minx
, miny
, maxx
, maxy
;
60 /* Convert (-1, -1) and (1, 1) from clip space into window space. */
61 minx
= -vp
->scale
[0] + vp
->translate
[0];
62 miny
= -vp
->scale
[1] + vp
->translate
[1];
63 maxx
= vp
->scale
[0] + vp
->translate
[0];
64 maxy
= vp
->scale
[1] + vp
->translate
[1];
66 /* r600_draw_rectangle sets this. Disable the scissor. */
67 if (minx
== -1 && miny
== -1 && maxx
== 1 && maxy
== 1) {
68 scissor
->minx
= scissor
->miny
= 0;
69 scissor
->maxx
= scissor
->maxy
= SI_MAX_SCISSOR
;
73 /* Handle inverted viewports. */
85 /* Convert to integer and round up the max bounds. */
88 scissor
->maxx
= ceilf(maxx
);
89 scissor
->maxy
= ceilf(maxy
);
92 static void si_clamp_scissor(struct si_context
*ctx
,
93 struct pipe_scissor_state
*out
,
94 struct si_signed_scissor
*scissor
)
96 out
->minx
= CLAMP(scissor
->minx
, 0, SI_MAX_SCISSOR
);
97 out
->miny
= CLAMP(scissor
->miny
, 0, SI_MAX_SCISSOR
);
98 out
->maxx
= CLAMP(scissor
->maxx
, 0, SI_MAX_SCISSOR
);
99 out
->maxy
= CLAMP(scissor
->maxy
, 0, SI_MAX_SCISSOR
);
102 static void si_clip_scissor(struct pipe_scissor_state
*out
,
103 struct pipe_scissor_state
*clip
)
105 out
->minx
= MAX2(out
->minx
, clip
->minx
);
106 out
->miny
= MAX2(out
->miny
, clip
->miny
);
107 out
->maxx
= MIN2(out
->maxx
, clip
->maxx
);
108 out
->maxy
= MIN2(out
->maxy
, clip
->maxy
);
111 static void si_scissor_make_union(struct si_signed_scissor
*out
,
112 struct si_signed_scissor
*in
)
114 out
->minx
= MIN2(out
->minx
, in
->minx
);
115 out
->miny
= MIN2(out
->miny
, in
->miny
);
116 out
->maxx
= MAX2(out
->maxx
, in
->maxx
);
117 out
->maxy
= MAX2(out
->maxy
, in
->maxy
);
120 static void si_emit_one_scissor(struct si_context
*ctx
,
121 struct radeon_winsys_cs
*cs
,
122 struct si_signed_scissor
*vp_scissor
,
123 struct pipe_scissor_state
*scissor
)
125 struct pipe_scissor_state final
;
127 if (ctx
->vs_disables_clipping_viewport
) {
128 final
.minx
= final
.miny
= 0;
129 final
.maxx
= final
.maxy
= SI_MAX_SCISSOR
;
131 si_clamp_scissor(ctx
, &final
, vp_scissor
);
135 si_clip_scissor(&final
, scissor
);
137 radeon_emit(cs
, S_028250_TL_X(final
.minx
) |
138 S_028250_TL_Y(final
.miny
) |
139 S_028250_WINDOW_OFFSET_DISABLE(1));
140 radeon_emit(cs
, S_028254_BR_X(final
.maxx
) |
141 S_028254_BR_Y(final
.maxy
));
144 /* the range is [-MAX, MAX] */
145 #define GET_MAX_VIEWPORT_RANGE(rctx) (32768)
147 static void si_emit_guardband(struct si_context
*ctx
,
148 struct si_signed_scissor
*vp_as_scissor
)
150 struct radeon_winsys_cs
*cs
= ctx
->b
.gfx
.cs
;
151 struct pipe_viewport_state vp
;
152 float left
, top
, right
, bottom
, max_range
, guardband_x
, guardband_y
;
153 float discard_x
, discard_y
;
155 /* Reconstruct the viewport transformation from the scissor. */
156 vp
.translate
[0] = (vp_as_scissor
->minx
+ vp_as_scissor
->maxx
) / 2.0;
157 vp
.translate
[1] = (vp_as_scissor
->miny
+ vp_as_scissor
->maxy
) / 2.0;
158 vp
.scale
[0] = vp_as_scissor
->maxx
- vp
.translate
[0];
159 vp
.scale
[1] = vp_as_scissor
->maxy
- vp
.translate
[1];
161 /* Treat a 0x0 viewport as 1x1 to prevent division by zero. */
162 if (vp_as_scissor
->minx
== vp_as_scissor
->maxx
)
164 if (vp_as_scissor
->miny
== vp_as_scissor
->maxy
)
167 /* Find the biggest guard band that is inside the supported viewport
168 * range. The guard band is specified as a horizontal and vertical
169 * distance from (0,0) in clip space.
171 * This is done by applying the inverse viewport transformation
172 * on the viewport limits to get those limits in clip space.
174 * Use a limit one pixel smaller to allow for some precision error.
176 max_range
= GET_MAX_VIEWPORT_RANGE(ctx
) - 1;
177 left
= (-max_range
- vp
.translate
[0]) / vp
.scale
[0];
178 right
= ( max_range
- vp
.translate
[0]) / vp
.scale
[0];
179 top
= (-max_range
- vp
.translate
[1]) / vp
.scale
[1];
180 bottom
= ( max_range
- vp
.translate
[1]) / vp
.scale
[1];
182 assert(left
<= -1 && top
<= -1 && right
>= 1 && bottom
>= 1);
184 guardband_x
= MIN2(-left
, right
);
185 guardband_y
= MIN2(-top
, bottom
);
190 if (unlikely(ctx
->current_rast_prim
< PIPE_PRIM_TRIANGLES
) &&
191 ctx
->queued
.named
.rasterizer
) {
192 /* When rendering wide points or lines, we need to be more
193 * conservative about when to discard them entirely. */
194 const struct si_state_rasterizer
*rs
= ctx
->queued
.named
.rasterizer
;
197 if (ctx
->current_rast_prim
== PIPE_PRIM_POINTS
)
198 pixels
= rs
->max_point_size
;
200 pixels
= rs
->line_width
;
202 /* Add half the point size / line width */
203 discard_x
+= pixels
/ (2.0 * vp
.scale
[0]);
204 discard_y
+= pixels
/ (2.0 * vp
.scale
[1]);
206 /* Discard primitives that would lie entirely outside the clip
208 discard_x
= MIN2(discard_x
, guardband_x
);
209 discard_y
= MIN2(discard_y
, guardband_y
);
212 /* If any of the GB registers is updated, all of them must be updated. */
213 radeon_set_context_reg_seq(cs
, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 4);
215 radeon_emit(cs
, fui(guardband_y
)); /* R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
216 radeon_emit(cs
, fui(discard_y
)); /* R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
217 radeon_emit(cs
, fui(guardband_x
)); /* R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
218 radeon_emit(cs
, fui(discard_x
)); /* R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
221 static void si_emit_scissors(struct r600_common_context
*rctx
, struct r600_atom
*atom
)
223 struct si_context
*ctx
= (struct si_context
*)rctx
;
224 struct radeon_winsys_cs
*cs
= ctx
->b
.gfx
.cs
;
225 struct pipe_scissor_state
*states
= ctx
->scissors
.states
;
226 unsigned mask
= ctx
->scissors
.dirty_mask
;
227 bool scissor_enabled
= false;
228 struct si_signed_scissor max_vp_scissor
;
231 if (ctx
->queued
.named
.rasterizer
)
232 scissor_enabled
= ctx
->queued
.named
.rasterizer
->scissor_enable
;
234 /* The simple case: Only 1 viewport is active. */
235 if (!ctx
->vs_writes_viewport_index
) {
236 struct si_signed_scissor
*vp
= &ctx
->viewports
.as_scissor
[0];
241 radeon_set_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 2);
242 si_emit_one_scissor(ctx
, cs
, vp
, scissor_enabled
? &states
[0] : NULL
);
243 si_emit_guardband(ctx
, vp
);
244 ctx
->scissors
.dirty_mask
&= ~1; /* clear one bit */
248 /* Shaders can draw to any viewport. Make a union of all viewports. */
249 max_vp_scissor
= ctx
->viewports
.as_scissor
[0];
250 for (i
= 1; i
< SI_MAX_VIEWPORTS
; i
++)
251 si_scissor_make_union(&max_vp_scissor
,
252 &ctx
->viewports
.as_scissor
[i
]);
257 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
259 radeon_set_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
+
260 start
* 4 * 2, count
* 2);
261 for (i
= start
; i
< start
+count
; i
++) {
262 si_emit_one_scissor(ctx
, cs
, &ctx
->viewports
.as_scissor
[i
],
263 scissor_enabled
? &states
[i
] : NULL
);
266 si_emit_guardband(ctx
, &max_vp_scissor
);
267 ctx
->scissors
.dirty_mask
= 0;
270 static void si_set_viewport_states(struct pipe_context
*pctx
,
272 unsigned num_viewports
,
273 const struct pipe_viewport_state
*state
)
275 struct si_context
*ctx
= (struct si_context
*)pctx
;
279 for (i
= 0; i
< num_viewports
; i
++) {
280 unsigned index
= start_slot
+ i
;
282 ctx
->viewports
.states
[index
] = state
[i
];
283 si_get_scissor_from_viewport(ctx
, &state
[i
],
284 &ctx
->viewports
.as_scissor
[index
]);
287 mask
= ((1 << num_viewports
) - 1) << start_slot
;
288 ctx
->viewports
.dirty_mask
|= mask
;
289 ctx
->viewports
.depth_range_dirty_mask
|= mask
;
290 ctx
->scissors
.dirty_mask
|= mask
;
291 si_mark_atom_dirty(ctx
, &ctx
->viewports
.atom
);
292 si_mark_atom_dirty(ctx
, &ctx
->scissors
.atom
);
295 static void si_emit_one_viewport(struct si_context
*ctx
,
296 struct pipe_viewport_state
*state
)
298 struct radeon_winsys_cs
*cs
= ctx
->b
.gfx
.cs
;
300 radeon_emit(cs
, fui(state
->scale
[0]));
301 radeon_emit(cs
, fui(state
->translate
[0]));
302 radeon_emit(cs
, fui(state
->scale
[1]));
303 radeon_emit(cs
, fui(state
->translate
[1]));
304 radeon_emit(cs
, fui(state
->scale
[2]));
305 radeon_emit(cs
, fui(state
->translate
[2]));
308 static void si_emit_viewports(struct si_context
*ctx
)
310 struct radeon_winsys_cs
*cs
= ctx
->b
.gfx
.cs
;
311 struct pipe_viewport_state
*states
= ctx
->viewports
.states
;
312 unsigned mask
= ctx
->viewports
.dirty_mask
;
314 /* The simple case: Only 1 viewport is active. */
315 if (!ctx
->vs_writes_viewport_index
) {
319 radeon_set_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE
, 6);
320 si_emit_one_viewport(ctx
, &states
[0]);
321 ctx
->viewports
.dirty_mask
&= ~1; /* clear one bit */
328 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
330 radeon_set_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE
+
331 start
* 4 * 6, count
* 6);
332 for (i
= start
; i
< start
+count
; i
++)
333 si_emit_one_viewport(ctx
, &states
[i
]);
335 ctx
->viewports
.dirty_mask
= 0;
338 static void si_emit_depth_ranges(struct si_context
*ctx
)
340 struct radeon_winsys_cs
*cs
= ctx
->b
.gfx
.cs
;
341 struct pipe_viewport_state
*states
= ctx
->viewports
.states
;
342 unsigned mask
= ctx
->viewports
.depth_range_dirty_mask
;
343 bool clip_halfz
= false;
346 if (ctx
->queued
.named
.rasterizer
)
347 clip_halfz
= ctx
->queued
.named
.rasterizer
->clip_halfz
;
349 /* The simple case: Only 1 viewport is active. */
350 if (!ctx
->vs_writes_viewport_index
) {
354 util_viewport_zmin_zmax(&states
[0], clip_halfz
, &zmin
, &zmax
);
356 radeon_set_context_reg_seq(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
357 radeon_emit(cs
, fui(zmin
));
358 radeon_emit(cs
, fui(zmax
));
359 ctx
->viewports
.depth_range_dirty_mask
&= ~1; /* clear one bit */
366 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
368 radeon_set_context_reg_seq(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
+
369 start
* 4 * 2, count
* 2);
370 for (i
= start
; i
< start
+count
; i
++) {
371 util_viewport_zmin_zmax(&states
[i
], clip_halfz
, &zmin
, &zmax
);
372 radeon_emit(cs
, fui(zmin
));
373 radeon_emit(cs
, fui(zmax
));
376 ctx
->viewports
.depth_range_dirty_mask
= 0;
379 static void si_emit_viewport_states(struct r600_common_context
*rctx
,
380 struct r600_atom
*atom
)
382 struct si_context
*ctx
= (struct si_context
*)rctx
;
383 si_emit_viewports(ctx
);
384 si_emit_depth_ranges(ctx
);
388 * Normally, we only emit 1 viewport and 1 scissor if no shader is using
389 * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
390 * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
391 * called to emit the rest.
393 void si_update_vs_writes_viewport_index(struct si_context
*ctx
)
395 struct tgsi_shader_info
*info
= si_get_vs_info(ctx
);
396 bool vs_window_space
;
401 /* When the VS disables clipping and viewport transformation. */
403 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
405 if (ctx
->vs_disables_clipping_viewport
!= vs_window_space
) {
406 ctx
->vs_disables_clipping_viewport
= vs_window_space
;
407 ctx
->scissors
.dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
408 si_mark_atom_dirty(ctx
, &ctx
->scissors
.atom
);
411 /* Viewport index handling. */
412 ctx
->vs_writes_viewport_index
= info
->writes_viewport_index
;
413 if (!ctx
->vs_writes_viewport_index
)
416 if (ctx
->scissors
.dirty_mask
)
417 si_mark_atom_dirty(ctx
, &ctx
->scissors
.atom
);
419 if (ctx
->viewports
.dirty_mask
||
420 ctx
->viewports
.depth_range_dirty_mask
)
421 si_mark_atom_dirty(ctx
, &ctx
->viewports
.atom
);
424 void si_init_viewport_functions(struct si_context
*ctx
)
426 ctx
->scissors
.atom
.emit
= si_emit_scissors
;
427 ctx
->viewports
.atom
.emit
= si_emit_viewport_states
;
429 ctx
->scissors
.atom
.num_dw
= (2 + 16 * 2) + 6;
430 ctx
->viewports
.atom
.num_dw
= 2 + 16 * 6;
432 ctx
->b
.b
.set_scissor_states
= si_set_scissor_states
;
433 ctx
->b
.b
.set_viewport_states
= si_set_viewport_states
;