src/gallium/drivers/radeonsi/si_state_viewport.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "sid.h"
  26 #include "radeon/r600_cs.h"
  27 #include "util/u_viewport.h"
  28 #include "tgsi/tgsi_scan.h"
  29
  30 #define SI_MAX_SCISSOR 16384
  31
  32 static void si_set_scissor_states(struct pipe_context *pctx,
  33                                   unsigned start_slot,
  34                                   unsigned num_scissors,
  35                                   const struct pipe_scissor_state *state)
  36 {
  37         struct si_context *ctx = (struct si_context *)pctx;
  38         int i;
  39
  40         for (i = 0; i < num_scissors; i++)
  41                 ctx->scissors.states[start_slot + i] = state[i];
  42
  43         if (!ctx->queued.named.rasterizer ||
  44             !ctx->queued.named.rasterizer->scissor_enable)
  45                 return;
  46
  47         ctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
  48         si_mark_atom_dirty(ctx, &ctx->scissors.atom);
  49 }
  50
  51 /* Since the guard band disables clipping, we have to clip per-pixel
  52  * using a scissor.
  53  */
  54 static void si_get_scissor_from_viewport(struct si_context *ctx,
  55                                          const struct pipe_viewport_state *vp,
  56                                          struct si_signed_scissor *scissor)
  57 {
  58         float tmp, minx, miny, maxx, maxy;
  59
  60         /* Convert (-1, -1) and (1, 1) from clip space into window space. */
  61         minx = -vp->scale[0] + vp->translate[0];
  62         miny = -vp->scale[1] + vp->translate[1];
  63         maxx = vp->scale[0] + vp->translate[0];
  64         maxy = vp->scale[1] + vp->translate[1];
  65
  66         /* Handle inverted viewports. */
  67         if (minx > maxx) {
  68                 tmp = minx;
  69                 minx = maxx;
  70                 maxx = tmp;
  71         }
  72         if (miny > maxy) {
  73                 tmp = miny;
  74                 miny = maxy;
  75                 maxy = tmp;
  76         }
  77
  78         /* Convert to integer and round up the max bounds. */
  79         scissor->minx = minx;
  80         scissor->miny = miny;
  81         scissor->maxx = ceilf(maxx);
  82         scissor->maxy = ceilf(maxy);
  83 }
  84
  85 static void si_clamp_scissor(struct si_context *ctx,
  86                              struct pipe_scissor_state *out,
  87                              struct si_signed_scissor *scissor)
  88 {
  89         out->minx = CLAMP(scissor->minx, 0, SI_MAX_SCISSOR);
  90         out->miny = CLAMP(scissor->miny, 0, SI_MAX_SCISSOR);
  91         out->maxx = CLAMP(scissor->maxx, 0, SI_MAX_SCISSOR);
  92         out->maxy = CLAMP(scissor->maxy, 0, SI_MAX_SCISSOR);
  93 }
  94
  95 static void si_clip_scissor(struct pipe_scissor_state *out,
  96                             struct pipe_scissor_state *clip)
  97 {
  98         out->minx = MAX2(out->minx, clip->minx);
  99         out->miny = MAX2(out->miny, clip->miny);
 100         out->maxx = MIN2(out->maxx, clip->maxx);
 101         out->maxy = MIN2(out->maxy, clip->maxy);
 102 }
 103
 104 static void si_scissor_make_union(struct si_signed_scissor *out,
 105                                   struct si_signed_scissor *in)
 106 {
 107         out->minx = MIN2(out->minx, in->minx);
 108         out->miny = MIN2(out->miny, in->miny);
 109         out->maxx = MAX2(out->maxx, in->maxx);
 110         out->maxy = MAX2(out->maxy, in->maxy);
 111 }
 112
 113 static void si_emit_one_scissor(struct si_context *ctx,
 114                                 struct radeon_winsys_cs *cs,
 115                                 struct si_signed_scissor *vp_scissor,
 116                                 struct pipe_scissor_state *scissor)
 117 {
 118         struct pipe_scissor_state final;
 119
 120         if (ctx->vs_disables_clipping_viewport) {
 121                 final.minx = final.miny = 0;
 122                 final.maxx = final.maxy = SI_MAX_SCISSOR;
 123         } else {
 124                 si_clamp_scissor(ctx, &final, vp_scissor);
 125         }
 126
 127         if (scissor)
 128                 si_clip_scissor(&final, scissor);
 129
 130         radeon_emit(cs, S_028250_TL_X(final.minx) |
 131                         S_028250_TL_Y(final.miny) |
 132                         S_028250_WINDOW_OFFSET_DISABLE(1));
 133         radeon_emit(cs, S_028254_BR_X(final.maxx) |
 134                         S_028254_BR_Y(final.maxy));
 135 }
 136
 137 /* the range is [-MAX, MAX] */
 138 #define GET_MAX_VIEWPORT_RANGE(rctx) (32768)
 139
 140 static void si_emit_guardband(struct si_context *ctx,
 141                               struct si_signed_scissor *vp_as_scissor)
 142 {
 143         struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
 144         struct pipe_viewport_state vp;
 145         float left, top, right, bottom, max_range, guardband_x, guardband_y;
 146         float discard_x, discard_y;
 147
 148         /* Reconstruct the viewport transformation from the scissor. */
 149         vp.translate[0] = (vp_as_scissor->minx + vp_as_scissor->maxx) / 2.0;
 150         vp.translate[1] = (vp_as_scissor->miny + vp_as_scissor->maxy) / 2.0;
 151         vp.scale[0] = vp_as_scissor->maxx - vp.translate[0];
 152         vp.scale[1] = vp_as_scissor->maxy - vp.translate[1];
 153
 154         /* Treat a 0x0 viewport as 1x1 to prevent division by zero. */
 155         if (vp_as_scissor->minx == vp_as_scissor->maxx)
 156                 vp.scale[0] = 0.5;
 157         if (vp_as_scissor->miny == vp_as_scissor->maxy)
 158                 vp.scale[1] = 0.5;
 159
 160         /* Find the biggest guard band that is inside the supported viewport
 161          * range. The guard band is specified as a horizontal and vertical
 162          * distance from (0,0) in clip space.
 163          *
 164          * This is done by applying the inverse viewport transformation
 165          * on the viewport limits to get those limits in clip space.
 166          *
 167          * Use a limit one pixel smaller to allow for some precision error.
 168          */
 169         max_range = GET_MAX_VIEWPORT_RANGE(ctx) - 1;
 170         left   = (-max_range - vp.translate[0]) / vp.scale[0];
 171         right  = ( max_range - vp.translate[0]) / vp.scale[0];
 172         top    = (-max_range - vp.translate[1]) / vp.scale[1];
 173         bottom = ( max_range - vp.translate[1]) / vp.scale[1];
 174
 175         assert(left <= -1 && top <= -1 && right >= 1 && bottom >= 1);
 176
 177         guardband_x = MIN2(-left, right);
 178         guardband_y = MIN2(-top, bottom);
 179
 180         discard_x = 1.0;
 181         discard_y = 1.0;
 182
 183         if (unlikely(ctx->current_rast_prim < PIPE_PRIM_TRIANGLES) &&
 184             ctx->queued.named.rasterizer) {
 185                 /* When rendering wide points or lines, we need to be more
 186                  * conservative about when to discard them entirely. */
 187                 const struct si_state_rasterizer *rs = ctx->queued.named.rasterizer;
 188                 float pixels;
 189
 190                 if (ctx->current_rast_prim == PIPE_PRIM_POINTS)
 191                         pixels = rs->max_point_size;
 192                 else
 193                         pixels = rs->line_width;
 194
 195                 /* Add half the point size / line width */
 196                 discard_x += pixels / (2.0 * vp.scale[0]);
 197                 discard_y += pixels / (2.0 * vp.scale[1]);
 198
 199                 /* Discard primitives that would lie entirely outside the clip
 200                  * region. */
 201                 discard_x = MIN2(discard_x, guardband_x);
 202                 discard_y = MIN2(discard_y, guardband_y);
 203         }
 204
 205         /* If any of the GB registers is updated, all of them must be updated. */
 206         radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
 207
 208         radeon_emit(cs, fui(guardband_y)); /* R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
 209         radeon_emit(cs, fui(discard_y));   /* R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
 210         radeon_emit(cs, fui(guardband_x)); /* R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
 211         radeon_emit(cs, fui(discard_x));   /* R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
 212 }
 213
 214 static void si_emit_scissors(struct r600_common_context *rctx, struct r600_atom *atom)
 215 {
 216         struct si_context *ctx = (struct si_context *)rctx;
 217         struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
 218         struct pipe_scissor_state *states = ctx->scissors.states;
 219         unsigned mask = ctx->scissors.dirty_mask;
 220         bool scissor_enabled = false;
 221         struct si_signed_scissor max_vp_scissor;
 222         int i;
 223
 224         if (ctx->queued.named.rasterizer)
 225                 scissor_enabled = ctx->queued.named.rasterizer->scissor_enable;
 226
 227         /* The simple case: Only 1 viewport is active. */
 228         if (!ctx->vs_writes_viewport_index) {
 229                 struct si_signed_scissor *vp = &ctx->viewports.as_scissor[0];
 230
 231                 if (!(mask & 1))
 232                         return;
 233
 234                 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
 235                 si_emit_one_scissor(ctx, cs, vp, scissor_enabled ? &states[0] : NULL);
 236                 si_emit_guardband(ctx, vp);
 237                 ctx->scissors.dirty_mask &= ~1; /* clear one bit */
 238                 return;
 239         }
 240
 241         /* Shaders can draw to any viewport. Make a union of all viewports. */
 242         max_vp_scissor = ctx->viewports.as_scissor[0];
 243         for (i = 1; i < SI_MAX_VIEWPORTS; i++)
 244                 si_scissor_make_union(&max_vp_scissor,
 245                                       &ctx->viewports.as_scissor[i]);
 246
 247         while (mask) {
 248                 int start, count, i;
 249
 250                 u_bit_scan_consecutive_range(&mask, &start, &count);
 251
 252                 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
 253                                                start * 4 * 2, count * 2);
 254                 for (i = start; i < start+count; i++) {
 255                         si_emit_one_scissor(ctx, cs, &ctx->viewports.as_scissor[i],
 256                                             scissor_enabled ? &states[i] : NULL);
 257                 }
 258         }
 259         si_emit_guardband(ctx, &max_vp_scissor);
 260         ctx->scissors.dirty_mask = 0;
 261 }
 262
 263 static void si_set_viewport_states(struct pipe_context *pctx,
 264                                    unsigned start_slot,
 265                                    unsigned num_viewports,
 266                                    const struct pipe_viewport_state *state)
 267 {
 268         struct si_context *ctx = (struct si_context *)pctx;
 269         unsigned mask;
 270         int i;
 271
 272         for (i = 0; i < num_viewports; i++) {
 273                 unsigned index = start_slot + i;
 274
 275                 ctx->viewports.states[index] = state[i];
 276                 si_get_scissor_from_viewport(ctx, &state[i],
 277                                              &ctx->viewports.as_scissor[index]);
 278         }
 279
 280         mask = ((1 << num_viewports) - 1) << start_slot;
 281         ctx->viewports.dirty_mask |= mask;
 282         ctx->viewports.depth_range_dirty_mask |= mask;
 283         ctx->scissors.dirty_mask |= mask;
 284         si_mark_atom_dirty(ctx, &ctx->viewports.atom);
 285         si_mark_atom_dirty(ctx, &ctx->scissors.atom);
 286 }
 287
 288 static void si_emit_one_viewport(struct si_context *ctx,
 289                                  struct pipe_viewport_state *state)
 290 {
 291         struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
 292
 293         radeon_emit(cs, fui(state->scale[0]));
 294         radeon_emit(cs, fui(state->translate[0]));
 295         radeon_emit(cs, fui(state->scale[1]));
 296         radeon_emit(cs, fui(state->translate[1]));
 297         radeon_emit(cs, fui(state->scale[2]));
 298         radeon_emit(cs, fui(state->translate[2]));
 299 }
 300
 301 static void si_emit_viewports(struct si_context *ctx)
 302 {
 303         struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
 304         struct pipe_viewport_state *states = ctx->viewports.states;
 305         unsigned mask = ctx->viewports.dirty_mask;
 306
 307         /* The simple case: Only 1 viewport is active. */
 308         if (!ctx->vs_writes_viewport_index) {
 309                 if (!(mask & 1))
 310                         return;
 311
 312                 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
 313                 si_emit_one_viewport(ctx, &states[0]);
 314                 ctx->viewports.dirty_mask &= ~1; /* clear one bit */
 315                 return;
 316         }
 317
 318         while (mask) {
 319                 int start, count, i;
 320
 321                 u_bit_scan_consecutive_range(&mask, &start, &count);
 322
 323                 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
 324                                                start * 4 * 6, count * 6);
 325                 for (i = start; i < start+count; i++)
 326                         si_emit_one_viewport(ctx, &states[i]);
 327         }
 328         ctx->viewports.dirty_mask = 0;
 329 }
 330
 331 static inline void
 332 si_viewport_zmin_zmax(const struct pipe_viewport_state *vp, bool halfz,
 333                       bool window_space_position, float *zmin, float *zmax)
 334 {
 335         if (window_space_position) {
 336                 *zmin = 0;
 337                 *zmax = 1;
 338                 return;
 339         }
 340         util_viewport_zmin_zmax(vp, halfz, zmin, zmax);
 341 }
 342
 343 static void si_emit_depth_ranges(struct si_context *ctx)
 344 {
 345         struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
 346         struct pipe_viewport_state *states = ctx->viewports.states;
 347         unsigned mask = ctx->viewports.depth_range_dirty_mask;
 348         bool clip_halfz = false;
 349         bool window_space = ctx->vs_disables_clipping_viewport;
 350         float zmin, zmax;
 351
 352         if (ctx->queued.named.rasterizer)
 353                 clip_halfz = ctx->queued.named.rasterizer->clip_halfz;
 354
 355         /* The simple case: Only 1 viewport is active. */
 356         if (!ctx->vs_writes_viewport_index) {
 357                 if (!(mask & 1))
 358                         return;
 359
 360                 si_viewport_zmin_zmax(&states[0], clip_halfz, window_space,
 361                                       &zmin, &zmax);
 362
 363                 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
 364                 radeon_emit(cs, fui(zmin));
 365                 radeon_emit(cs, fui(zmax));
 366                 ctx->viewports.depth_range_dirty_mask &= ~1; /* clear one bit */
 367                 return;
 368         }
 369
 370         while (mask) {
 371                 int start, count, i;
 372
 373                 u_bit_scan_consecutive_range(&mask, &start, &count);
 374
 375                 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
 376                                            start * 4 * 2, count * 2);
 377                 for (i = start; i < start+count; i++) {
 378                         si_viewport_zmin_zmax(&states[i], clip_halfz, window_space,
 379                                               &zmin, &zmax);
 380                         radeon_emit(cs, fui(zmin));
 381                         radeon_emit(cs, fui(zmax));
 382                 }
 383         }
 384         ctx->viewports.depth_range_dirty_mask = 0;
 385 }
 386
 387 static void si_emit_viewport_states(struct r600_common_context *rctx,
 388                                     struct r600_atom *atom)
 389 {
 390         struct si_context *ctx = (struct si_context *)rctx;
 391         si_emit_viewports(ctx);
 392         si_emit_depth_ranges(ctx);
 393 }
 394
 395 /**
 396  * This reacts to 2 state changes:
 397  * - VS.writes_viewport_index
 398  * - VS output position in window space (enable/disable)
 399  *
 400  * Normally, we only emit 1 viewport and 1 scissor if no shader is using
 401  * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
 402  * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
 403  * called to emit the rest.
 404  */
 405 void si_update_vs_viewport_state(struct si_context *ctx)
 406 {
 407         struct tgsi_shader_info *info = si_get_vs_info(ctx);
 408         bool vs_window_space;
 409
 410         if (!info)
 411                 return;
 412
 413         /* When the VS disables clipping and viewport transformation. */
 414         vs_window_space =
 415                 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
 416
 417         if (ctx->vs_disables_clipping_viewport != vs_window_space) {
 418                 ctx->vs_disables_clipping_viewport = vs_window_space;
 419                 ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 420                 ctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 421                 si_mark_atom_dirty(ctx, &ctx->scissors.atom);
 422                 si_mark_atom_dirty(ctx, &ctx->viewports.atom);
 423         }
 424
 425         /* Viewport index handling. */
 426         ctx->vs_writes_viewport_index = info->writes_viewport_index;
 427         if (!ctx->vs_writes_viewport_index)
 428                 return;
 429
 430         if (ctx->scissors.dirty_mask)
 431             si_mark_atom_dirty(ctx, &ctx->scissors.atom);
 432
 433         if (ctx->viewports.dirty_mask ||
 434             ctx->viewports.depth_range_dirty_mask)
 435             si_mark_atom_dirty(ctx, &ctx->viewports.atom);
 436 }
 437
 438 void si_init_viewport_functions(struct si_context *ctx)
 439 {
 440         ctx->scissors.atom.emit = si_emit_scissors;
 441         ctx->viewports.atom.emit = si_emit_viewport_states;
 442
 443         ctx->b.b.set_scissor_states = si_set_scissor_states;
 444         ctx->b.b.set_viewport_states = si_set_viewport_states;
 445 }