2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
26 #include "util/u_viewport.h"
27 #include "tgsi/tgsi_scan.h"
29 #define SI_MAX_SCISSOR 16384
31 static void si_set_scissor_states(struct pipe_context
*pctx
,
33 unsigned num_scissors
,
34 const struct pipe_scissor_state
*state
)
36 struct si_context
*ctx
= (struct si_context
*)pctx
;
39 for (i
= 0; i
< num_scissors
; i
++)
40 ctx
->scissors
.states
[start_slot
+ i
] = state
[i
];
42 if (!ctx
->queued
.named
.rasterizer
||
43 !ctx
->queued
.named
.rasterizer
->scissor_enable
)
46 ctx
->scissors
.dirty_mask
|= ((1 << num_scissors
) - 1) << start_slot
;
47 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.scissors
);
50 /* Since the guard band disables clipping, we have to clip per-pixel
53 static void si_get_scissor_from_viewport(struct si_context
*ctx
,
54 const struct pipe_viewport_state
*vp
,
55 struct si_signed_scissor
*scissor
)
57 float tmp
, minx
, miny
, maxx
, maxy
;
59 /* Convert (-1, -1) and (1, 1) from clip space into window space. */
60 minx
= -vp
->scale
[0] + vp
->translate
[0];
61 miny
= -vp
->scale
[1] + vp
->translate
[1];
62 maxx
= vp
->scale
[0] + vp
->translate
[0];
63 maxy
= vp
->scale
[1] + vp
->translate
[1];
65 /* Handle inverted viewports. */
77 /* Convert to integer and round up the max bounds. */
80 scissor
->maxx
= ceilf(maxx
);
81 scissor
->maxy
= ceilf(maxy
);
84 static void si_clamp_scissor(struct si_context
*ctx
,
85 struct pipe_scissor_state
*out
,
86 struct si_signed_scissor
*scissor
)
88 out
->minx
= CLAMP(scissor
->minx
, 0, SI_MAX_SCISSOR
);
89 out
->miny
= CLAMP(scissor
->miny
, 0, SI_MAX_SCISSOR
);
90 out
->maxx
= CLAMP(scissor
->maxx
, 0, SI_MAX_SCISSOR
);
91 out
->maxy
= CLAMP(scissor
->maxy
, 0, SI_MAX_SCISSOR
);
94 static void si_clip_scissor(struct pipe_scissor_state
*out
,
95 struct pipe_scissor_state
*clip
)
97 out
->minx
= MAX2(out
->minx
, clip
->minx
);
98 out
->miny
= MAX2(out
->miny
, clip
->miny
);
99 out
->maxx
= MIN2(out
->maxx
, clip
->maxx
);
100 out
->maxy
= MIN2(out
->maxy
, clip
->maxy
);
103 static void si_scissor_make_union(struct si_signed_scissor
*out
,
104 struct si_signed_scissor
*in
)
106 out
->minx
= MIN2(out
->minx
, in
->minx
);
107 out
->miny
= MIN2(out
->miny
, in
->miny
);
108 out
->maxx
= MAX2(out
->maxx
, in
->maxx
);
109 out
->maxy
= MAX2(out
->maxy
, in
->maxy
);
112 static void si_emit_one_scissor(struct si_context
*ctx
,
113 struct radeon_winsys_cs
*cs
,
114 struct si_signed_scissor
*vp_scissor
,
115 struct pipe_scissor_state
*scissor
)
117 struct pipe_scissor_state final
;
119 if (ctx
->vs_disables_clipping_viewport
) {
120 final
.minx
= final
.miny
= 0;
121 final
.maxx
= final
.maxy
= SI_MAX_SCISSOR
;
123 si_clamp_scissor(ctx
, &final
, vp_scissor
);
127 si_clip_scissor(&final
, scissor
);
129 radeon_emit(cs
, S_028250_TL_X(final
.minx
) |
130 S_028250_TL_Y(final
.miny
) |
131 S_028250_WINDOW_OFFSET_DISABLE(1));
132 radeon_emit(cs
, S_028254_BR_X(final
.maxx
) |
133 S_028254_BR_Y(final
.maxy
));
136 /* the range is [-MAX, MAX] */
137 #define SI_MAX_VIEWPORT_RANGE 32768
139 static void si_emit_guardband(struct si_context
*ctx
)
141 const struct si_signed_scissor
*vp_as_scissor
;
142 struct si_signed_scissor max_vp_scissor
;
143 struct radeon_winsys_cs
*cs
= ctx
->gfx_cs
;
144 struct pipe_viewport_state vp
;
145 float left
, top
, right
, bottom
, max_range
, guardband_x
, guardband_y
;
146 float discard_x
, discard_y
;
148 if (ctx
->vs_writes_viewport_index
) {
149 /* Shaders can draw to any viewport. Make a union of all
151 max_vp_scissor
= ctx
->viewports
.as_scissor
[0];
152 for (unsigned i
= 1; i
< SI_MAX_VIEWPORTS
; i
++) {
153 si_scissor_make_union(&max_vp_scissor
,
154 &ctx
->viewports
.as_scissor
[i
]);
156 vp_as_scissor
= &max_vp_scissor
;
158 vp_as_scissor
= &ctx
->viewports
.as_scissor
[0];
161 /* Reconstruct the viewport transformation from the scissor. */
162 vp
.translate
[0] = (vp_as_scissor
->minx
+ vp_as_scissor
->maxx
) / 2.0;
163 vp
.translate
[1] = (vp_as_scissor
->miny
+ vp_as_scissor
->maxy
) / 2.0;
164 vp
.scale
[0] = vp_as_scissor
->maxx
- vp
.translate
[0];
165 vp
.scale
[1] = vp_as_scissor
->maxy
- vp
.translate
[1];
167 /* Treat a 0x0 viewport as 1x1 to prevent division by zero. */
168 if (vp_as_scissor
->minx
== vp_as_scissor
->maxx
)
170 if (vp_as_scissor
->miny
== vp_as_scissor
->maxy
)
173 /* Find the biggest guard band that is inside the supported viewport
174 * range. The guard band is specified as a horizontal and vertical
175 * distance from (0,0) in clip space.
177 * This is done by applying the inverse viewport transformation
178 * on the viewport limits to get those limits in clip space.
180 * Use a limit one pixel smaller to allow for some precision error.
182 max_range
= SI_MAX_VIEWPORT_RANGE
- 1;
183 left
= (-max_range
- vp
.translate
[0]) / vp
.scale
[0];
184 right
= ( max_range
- vp
.translate
[0]) / vp
.scale
[0];
185 top
= (-max_range
- vp
.translate
[1]) / vp
.scale
[1];
186 bottom
= ( max_range
- vp
.translate
[1]) / vp
.scale
[1];
188 assert(left
<= -1 && top
<= -1 && right
>= 1 && bottom
>= 1);
190 guardband_x
= MIN2(-left
, right
);
191 guardband_y
= MIN2(-top
, bottom
);
196 if (unlikely(util_prim_is_points_or_lines(ctx
->current_rast_prim
))) {
197 /* When rendering wide points or lines, we need to be more
198 * conservative about when to discard them entirely. */
199 const struct si_state_rasterizer
*rs
= ctx
->queued
.named
.rasterizer
;
202 if (ctx
->current_rast_prim
== PIPE_PRIM_POINTS
)
203 pixels
= rs
->max_point_size
;
205 pixels
= rs
->line_width
;
207 /* Add half the point size / line width */
208 discard_x
+= pixels
/ (2.0 * vp
.scale
[0]);
209 discard_y
+= pixels
/ (2.0 * vp
.scale
[1]);
211 /* Discard primitives that would lie entirely outside the clip
213 discard_x
= MIN2(discard_x
, guardband_x
);
214 discard_y
= MIN2(discard_y
, guardband_y
);
217 /* If any of the GB registers is updated, all of them must be updated. */
218 radeon_set_context_reg_seq(cs
, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 4);
220 radeon_emit(cs
, fui(guardband_y
)); /* R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
221 radeon_emit(cs
, fui(discard_y
)); /* R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
222 radeon_emit(cs
, fui(guardband_x
)); /* R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
223 radeon_emit(cs
, fui(discard_x
)); /* R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
226 static void si_emit_scissors(struct si_context
*ctx
)
228 struct radeon_winsys_cs
*cs
= ctx
->gfx_cs
;
229 struct pipe_scissor_state
*states
= ctx
->scissors
.states
;
230 unsigned mask
= ctx
->scissors
.dirty_mask
;
231 bool scissor_enabled
= ctx
->queued
.named
.rasterizer
->scissor_enable
;
233 /* The simple case: Only 1 viewport is active. */
234 if (!ctx
->vs_writes_viewport_index
) {
235 struct si_signed_scissor
*vp
= &ctx
->viewports
.as_scissor
[0];
240 radeon_set_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 2);
241 si_emit_one_scissor(ctx
, cs
, vp
, scissor_enabled
? &states
[0] : NULL
);
242 ctx
->scissors
.dirty_mask
&= ~1; /* clear one bit */
249 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
251 radeon_set_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
+
252 start
* 4 * 2, count
* 2);
253 for (i
= start
; i
< start
+count
; i
++) {
254 si_emit_one_scissor(ctx
, cs
, &ctx
->viewports
.as_scissor
[i
],
255 scissor_enabled
? &states
[i
] : NULL
);
258 ctx
->scissors
.dirty_mask
= 0;
261 static void si_set_viewport_states(struct pipe_context
*pctx
,
263 unsigned num_viewports
,
264 const struct pipe_viewport_state
*state
)
266 struct si_context
*ctx
= (struct si_context
*)pctx
;
270 for (i
= 0; i
< num_viewports
; i
++) {
271 unsigned index
= start_slot
+ i
;
273 ctx
->viewports
.states
[index
] = state
[i
];
274 si_get_scissor_from_viewport(ctx
, &state
[i
],
275 &ctx
->viewports
.as_scissor
[index
]);
278 mask
= ((1 << num_viewports
) - 1) << start_slot
;
279 ctx
->viewports
.dirty_mask
|= mask
;
280 ctx
->viewports
.depth_range_dirty_mask
|= mask
;
281 ctx
->scissors
.dirty_mask
|= mask
;
282 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.viewports
);
283 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.guardband
);
284 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.scissors
);
287 static void si_emit_one_viewport(struct si_context
*ctx
,
288 struct pipe_viewport_state
*state
)
290 struct radeon_winsys_cs
*cs
= ctx
->gfx_cs
;
292 radeon_emit(cs
, fui(state
->scale
[0]));
293 radeon_emit(cs
, fui(state
->translate
[0]));
294 radeon_emit(cs
, fui(state
->scale
[1]));
295 radeon_emit(cs
, fui(state
->translate
[1]));
296 radeon_emit(cs
, fui(state
->scale
[2]));
297 radeon_emit(cs
, fui(state
->translate
[2]));
300 static void si_emit_viewports(struct si_context
*ctx
)
302 struct radeon_winsys_cs
*cs
= ctx
->gfx_cs
;
303 struct pipe_viewport_state
*states
= ctx
->viewports
.states
;
304 unsigned mask
= ctx
->viewports
.dirty_mask
;
306 /* The simple case: Only 1 viewport is active. */
307 if (!ctx
->vs_writes_viewport_index
) {
311 radeon_set_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE
, 6);
312 si_emit_one_viewport(ctx
, &states
[0]);
313 ctx
->viewports
.dirty_mask
&= ~1; /* clear one bit */
320 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
322 radeon_set_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE
+
323 start
* 4 * 6, count
* 6);
324 for (i
= start
; i
< start
+count
; i
++)
325 si_emit_one_viewport(ctx
, &states
[i
]);
327 ctx
->viewports
.dirty_mask
= 0;
331 si_viewport_zmin_zmax(const struct pipe_viewport_state
*vp
, bool halfz
,
332 bool window_space_position
, float *zmin
, float *zmax
)
334 if (window_space_position
) {
339 util_viewport_zmin_zmax(vp
, halfz
, zmin
, zmax
);
342 static void si_emit_depth_ranges(struct si_context
*ctx
)
344 struct radeon_winsys_cs
*cs
= ctx
->gfx_cs
;
345 struct pipe_viewport_state
*states
= ctx
->viewports
.states
;
346 unsigned mask
= ctx
->viewports
.depth_range_dirty_mask
;
347 bool clip_halfz
= ctx
->queued
.named
.rasterizer
->clip_halfz
;
348 bool window_space
= ctx
->vs_disables_clipping_viewport
;
351 /* The simple case: Only 1 viewport is active. */
352 if (!ctx
->vs_writes_viewport_index
) {
356 si_viewport_zmin_zmax(&states
[0], clip_halfz
, window_space
,
359 radeon_set_context_reg_seq(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
360 radeon_emit(cs
, fui(zmin
));
361 radeon_emit(cs
, fui(zmax
));
362 ctx
->viewports
.depth_range_dirty_mask
&= ~1; /* clear one bit */
369 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
371 radeon_set_context_reg_seq(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
+
372 start
* 4 * 2, count
* 2);
373 for (i
= start
; i
< start
+count
; i
++) {
374 si_viewport_zmin_zmax(&states
[i
], clip_halfz
, window_space
,
376 radeon_emit(cs
, fui(zmin
));
377 radeon_emit(cs
, fui(zmax
));
380 ctx
->viewports
.depth_range_dirty_mask
= 0;
383 static void si_emit_viewport_states(struct si_context
*ctx
)
385 si_emit_viewports(ctx
);
386 si_emit_depth_ranges(ctx
);
390 * This reacts to 2 state changes:
391 * - VS.writes_viewport_index
392 * - VS output position in window space (enable/disable)
394 * Normally, we only emit 1 viewport and 1 scissor if no shader is using
395 * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
396 * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
397 * called to emit the rest.
399 void si_update_vs_viewport_state(struct si_context
*ctx
)
401 struct tgsi_shader_info
*info
= si_get_vs_info(ctx
);
402 bool vs_window_space
;
407 /* When the VS disables clipping and viewport transformation. */
409 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
411 if (ctx
->vs_disables_clipping_viewport
!= vs_window_space
) {
412 ctx
->vs_disables_clipping_viewport
= vs_window_space
;
413 ctx
->scissors
.dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
414 ctx
->viewports
.depth_range_dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
415 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.scissors
);
416 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.viewports
);
419 /* Viewport index handling. */
420 if (ctx
->vs_writes_viewport_index
== info
->writes_viewport_index
)
423 /* This changes how the guardband is computed. */
424 ctx
->vs_writes_viewport_index
= info
->writes_viewport_index
;
425 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.guardband
);
427 if (!ctx
->vs_writes_viewport_index
)
430 if (ctx
->scissors
.dirty_mask
)
431 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.scissors
);
433 if (ctx
->viewports
.dirty_mask
||
434 ctx
->viewports
.depth_range_dirty_mask
)
435 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.viewports
);
438 void si_init_viewport_functions(struct si_context
*ctx
)
440 ctx
->atoms
.s
.guardband
.emit
= si_emit_guardband
;
441 ctx
->atoms
.s
.scissors
.emit
= si_emit_scissors
;
442 ctx
->atoms
.s
.viewports
.emit
= si_emit_viewport_states
;
444 ctx
->b
.set_scissor_states
= si_set_scissor_states
;
445 ctx
->b
.set_viewport_states
= si_set_viewport_states
;