2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "radeon/r600_cs.h"
25 #include "util/u_viewport.h"
26 #include "tgsi/tgsi_scan.h"
28 #define GET_MAX_SCISSOR(rctx) (rctx->chip_class >= EVERGREEN ? 16384 : 8192)
30 static void r600_set_scissor_states(struct pipe_context
*ctx
,
32 unsigned num_scissors
,
33 const struct pipe_scissor_state
*state
)
35 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
38 for (i
= 0; i
< num_scissors
; i
++)
39 rctx
->scissors
.states
[start_slot
+ i
] = state
[i
];
41 if (!rctx
->scissor_enabled
)
44 rctx
->scissors
.dirty_mask
|= ((1 << num_scissors
) - 1) << start_slot
;
45 rctx
->set_atom_dirty(rctx
, &rctx
->scissors
.atom
, true);
48 /* Since the guard band disables clipping, we have to clip per-pixel
51 static void r600_get_scissor_from_viewport(struct r600_common_context
*rctx
,
52 const struct pipe_viewport_state
*vp
,
53 struct r600_signed_scissor
*scissor
)
55 float tmp
, minx
, miny
, maxx
, maxy
;
57 /* Convert (-1, -1) and (1, 1) from clip space into window space. */
58 minx
= -vp
->scale
[0] + vp
->translate
[0];
59 miny
= -vp
->scale
[1] + vp
->translate
[1];
60 maxx
= vp
->scale
[0] + vp
->translate
[0];
61 maxy
= vp
->scale
[1] + vp
->translate
[1];
63 /* r600_draw_rectangle sets this. Disable the scissor. */
64 if (minx
== -1 && miny
== -1 && maxx
== 1 && maxy
== 1) {
65 scissor
->minx
= scissor
->miny
= 0;
66 scissor
->maxx
= scissor
->maxy
= GET_MAX_SCISSOR(rctx
);
70 /* Handle inverted viewports. */
82 /* Convert to integer and round up the max bounds. */
85 scissor
->maxx
= ceilf(maxx
);
86 scissor
->maxy
= ceilf(maxy
);
89 static void r600_clamp_scissor(struct r600_common_context
*rctx
,
90 struct pipe_scissor_state
*out
,
91 struct r600_signed_scissor
*scissor
)
93 unsigned max_scissor
= GET_MAX_SCISSOR(rctx
);
94 out
->minx
= CLAMP(scissor
->minx
, 0, max_scissor
);
95 out
->miny
= CLAMP(scissor
->miny
, 0, max_scissor
);
96 out
->maxx
= CLAMP(scissor
->maxx
, 0, max_scissor
);
97 out
->maxy
= CLAMP(scissor
->maxy
, 0, max_scissor
);
100 static void r600_clip_scissor(struct pipe_scissor_state
*out
,
101 struct pipe_scissor_state
*clip
)
103 out
->minx
= MAX2(out
->minx
, clip
->minx
);
104 out
->miny
= MAX2(out
->miny
, clip
->miny
);
105 out
->maxx
= MIN2(out
->maxx
, clip
->maxx
);
106 out
->maxy
= MIN2(out
->maxy
, clip
->maxy
);
109 static void r600_scissor_make_union(struct r600_signed_scissor
*out
,
110 struct r600_signed_scissor
*in
)
112 out
->minx
= MIN2(out
->minx
, in
->minx
);
113 out
->miny
= MIN2(out
->miny
, in
->miny
);
114 out
->maxx
= MAX2(out
->maxx
, in
->maxx
);
115 out
->maxy
= MAX2(out
->maxy
, in
->maxy
);
118 static void r600_emit_one_scissor(struct r600_common_context
*rctx
,
119 struct radeon_winsys_cs
*cs
,
120 struct r600_signed_scissor
*vp_scissor
,
121 struct pipe_scissor_state
*scissor
)
123 struct pipe_scissor_state final
;
125 if (rctx
->vs_disables_clipping_viewport
) {
126 final
.minx
= final
.miny
= 0;
127 final
.maxx
= final
.maxy
= GET_MAX_SCISSOR(rctx
);
129 r600_clamp_scissor(rctx
, &final
, vp_scissor
);
133 r600_clip_scissor(&final
, scissor
);
135 radeon_emit(cs
, S_028250_TL_X(final
.minx
) |
136 S_028250_TL_Y(final
.miny
) |
137 S_028250_WINDOW_OFFSET_DISABLE(1));
138 radeon_emit(cs
, S_028254_BR_X(final
.maxx
) |
139 S_028254_BR_Y(final
.maxy
));
142 /* the range is [-MAX, MAX] */
143 #define GET_MAX_VIEWPORT_RANGE(rctx) (rctx->chip_class >= EVERGREEN ? 32768 : 16384)
145 static void r600_emit_guardband(struct r600_common_context
*rctx
,
146 struct r600_signed_scissor
*vp_as_scissor
)
148 struct radeon_winsys_cs
*cs
= rctx
->gfx
.cs
;
149 struct pipe_viewport_state vp
;
150 float left
, top
, right
, bottom
, max_range
, guardband_x
, guardband_y
;
151 float discard_x
, discard_y
;
153 /* Reconstruct the viewport transformation from the scissor. */
154 vp
.translate
[0] = (vp_as_scissor
->minx
+ vp_as_scissor
->maxx
) / 2.0;
155 vp
.translate
[1] = (vp_as_scissor
->miny
+ vp_as_scissor
->maxy
) / 2.0;
156 vp
.scale
[0] = vp_as_scissor
->maxx
- vp
.translate
[0];
157 vp
.scale
[1] = vp_as_scissor
->maxy
- vp
.translate
[1];
159 /* Treat a 0x0 viewport as 1x1 to prevent division by zero. */
160 if (vp_as_scissor
->minx
== vp_as_scissor
->maxx
)
162 if (vp_as_scissor
->miny
== vp_as_scissor
->maxy
)
165 /* Find the biggest guard band that is inside the supported viewport
166 * range. The guard band is specified as a horizontal and vertical
167 * distance from (0,0) in clip space.
169 * This is done by applying the inverse viewport transformation
170 * on the viewport limits to get those limits in clip space.
172 * Use a limit one pixel smaller to allow for some precision error.
174 max_range
= GET_MAX_VIEWPORT_RANGE(rctx
) - 1;
175 left
= (-max_range
- vp
.translate
[0]) / vp
.scale
[0];
176 right
= ( max_range
- vp
.translate
[0]) / vp
.scale
[0];
177 top
= (-max_range
- vp
.translate
[1]) / vp
.scale
[1];
178 bottom
= ( max_range
- vp
.translate
[1]) / vp
.scale
[1];
180 assert(left
<= -1 && top
<= -1 && right
>= 1 && bottom
>= 1);
182 guardband_x
= MIN2(-left
, right
);
183 guardband_y
= MIN2(-top
, bottom
);
188 if (rctx
->current_rast_prim
< PIPE_PRIM_TRIANGLES
) {
189 /* When rendering wide points or lines, we need to be more
190 * conservative about when to discard them entirely. Since
191 * point size can be determined by the VS output, we basically
192 * disable discard completely completely here.
194 * TODO: This can hurt performance when rendering lines and
195 * points with fixed size, and could be improved.
197 discard_x
= guardband_x
;
198 discard_y
= guardband_y
;
201 /* If any of the GB registers is updated, all of them must be updated. */
202 if (rctx
->chip_class
>= CAYMAN
)
203 radeon_set_context_reg_seq(cs
, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 4);
205 radeon_set_context_reg_seq(cs
, R600_R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 4);
207 radeon_emit(cs
, fui(guardband_y
)); /* R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
208 radeon_emit(cs
, fui(discard_y
)); /* R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
209 radeon_emit(cs
, fui(guardband_x
)); /* R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
210 radeon_emit(cs
, fui(discard_x
)); /* R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
213 static void r600_emit_scissors(struct r600_common_context
*rctx
, struct r600_atom
*atom
)
215 struct radeon_winsys_cs
*cs
= rctx
->gfx
.cs
;
216 struct pipe_scissor_state
*states
= rctx
->scissors
.states
;
217 unsigned mask
= rctx
->scissors
.dirty_mask
;
218 bool scissor_enabled
= rctx
->scissor_enabled
;
219 struct r600_signed_scissor max_vp_scissor
;
222 /* The simple case: Only 1 viewport is active. */
223 if (!rctx
->vs_writes_viewport_index
) {
224 struct r600_signed_scissor
*vp
= &rctx
->viewports
.as_scissor
[0];
229 radeon_set_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 2);
230 r600_emit_one_scissor(rctx
, cs
, vp
, scissor_enabled
? &states
[0] : NULL
);
231 r600_emit_guardband(rctx
, vp
);
232 rctx
->scissors
.dirty_mask
&= ~1; /* clear one bit */
236 /* Shaders can draw to any viewport. Make a union of all viewports. */
237 max_vp_scissor
= rctx
->viewports
.as_scissor
[0];
238 for (i
= 1; i
< R600_MAX_VIEWPORTS
; i
++)
239 r600_scissor_make_union(&max_vp_scissor
,
240 &rctx
->viewports
.as_scissor
[i
]);
245 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
247 radeon_set_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
+
248 start
* 4 * 2, count
* 2);
249 for (i
= start
; i
< start
+count
; i
++) {
250 r600_emit_one_scissor(rctx
, cs
, &rctx
->viewports
.as_scissor
[i
],
251 scissor_enabled
? &states
[i
] : NULL
);
254 r600_emit_guardband(rctx
, &max_vp_scissor
);
255 rctx
->scissors
.dirty_mask
= 0;
258 static void r600_set_viewport_states(struct pipe_context
*ctx
,
260 unsigned num_viewports
,
261 const struct pipe_viewport_state
*state
)
263 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
267 for (i
= 0; i
< num_viewports
; i
++) {
268 unsigned index
= start_slot
+ i
;
270 rctx
->viewports
.states
[index
] = state
[i
];
271 r600_get_scissor_from_viewport(rctx
, &state
[i
],
272 &rctx
->viewports
.as_scissor
[index
]);
275 mask
= ((1 << num_viewports
) - 1) << start_slot
;
276 rctx
->viewports
.dirty_mask
|= mask
;
277 rctx
->viewports
.depth_range_dirty_mask
|= mask
;
278 rctx
->scissors
.dirty_mask
|= mask
;
279 rctx
->set_atom_dirty(rctx
, &rctx
->viewports
.atom
, true);
280 rctx
->set_atom_dirty(rctx
, &rctx
->scissors
.atom
, true);
283 static void r600_emit_one_viewport(struct r600_common_context
*rctx
,
284 struct pipe_viewport_state
*state
)
286 struct radeon_winsys_cs
*cs
= rctx
->gfx
.cs
;
288 radeon_emit(cs
, fui(state
->scale
[0]));
289 radeon_emit(cs
, fui(state
->translate
[0]));
290 radeon_emit(cs
, fui(state
->scale
[1]));
291 radeon_emit(cs
, fui(state
->translate
[1]));
292 radeon_emit(cs
, fui(state
->scale
[2]));
293 radeon_emit(cs
, fui(state
->translate
[2]));
296 static void r600_emit_viewports(struct r600_common_context
*rctx
)
298 struct radeon_winsys_cs
*cs
= rctx
->gfx
.cs
;
299 struct pipe_viewport_state
*states
= rctx
->viewports
.states
;
300 unsigned mask
= rctx
->viewports
.dirty_mask
;
302 /* The simple case: Only 1 viewport is active. */
303 if (!rctx
->vs_writes_viewport_index
) {
307 radeon_set_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE
, 6);
308 r600_emit_one_viewport(rctx
, &states
[0]);
309 rctx
->viewports
.dirty_mask
&= ~1; /* clear one bit */
316 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
318 radeon_set_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE
+
319 start
* 4 * 6, count
* 6);
320 for (i
= start
; i
< start
+count
; i
++)
321 r600_emit_one_viewport(rctx
, &states
[i
]);
323 rctx
->viewports
.dirty_mask
= 0;
326 static void r600_emit_depth_ranges(struct r600_common_context
*rctx
)
328 struct radeon_winsys_cs
*cs
= rctx
->gfx
.cs
;
329 struct pipe_viewport_state
*states
= rctx
->viewports
.states
;
330 unsigned mask
= rctx
->viewports
.depth_range_dirty_mask
;
333 /* The simple case: Only 1 viewport is active. */
334 if (!rctx
->vs_writes_viewport_index
) {
338 util_viewport_zmin_zmax(&states
[0], rctx
->clip_halfz
, &zmin
, &zmax
);
340 radeon_set_context_reg_seq(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
341 radeon_emit(cs
, fui(zmin
));
342 radeon_emit(cs
, fui(zmax
));
343 rctx
->viewports
.depth_range_dirty_mask
&= ~1; /* clear one bit */
350 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
352 radeon_set_context_reg_seq(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
+
353 start
* 4 * 2, count
* 2);
354 for (i
= start
; i
< start
+count
; i
++) {
355 util_viewport_zmin_zmax(&states
[i
], rctx
->clip_halfz
, &zmin
, &zmax
);
356 radeon_emit(cs
, fui(zmin
));
357 radeon_emit(cs
, fui(zmax
));
360 rctx
->viewports
.depth_range_dirty_mask
= 0;
363 static void r600_emit_viewport_states(struct r600_common_context
*rctx
,
364 struct r600_atom
*atom
)
366 r600_emit_viewports(rctx
);
367 r600_emit_depth_ranges(rctx
);
370 /* Set viewport dependencies on pipe_rasterizer_state. */
371 void si_viewport_set_rast_deps(struct r600_common_context
*rctx
,
372 bool scissor_enable
, bool clip_halfz
)
374 if (rctx
->scissor_enabled
!= scissor_enable
) {
375 rctx
->scissor_enabled
= scissor_enable
;
376 rctx
->scissors
.dirty_mask
= (1 << R600_MAX_VIEWPORTS
) - 1;
377 rctx
->set_atom_dirty(rctx
, &rctx
->scissors
.atom
, true);
379 if (rctx
->clip_halfz
!= clip_halfz
) {
380 rctx
->clip_halfz
= clip_halfz
;
381 rctx
->viewports
.depth_range_dirty_mask
= (1 << R600_MAX_VIEWPORTS
) - 1;
382 rctx
->set_atom_dirty(rctx
, &rctx
->viewports
.atom
, true);
387 * Normally, we only emit 1 viewport and 1 scissor if no shader is using
388 * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
389 * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
390 * called to emit the rest.
392 void si_update_vs_writes_viewport_index(struct r600_common_context
*rctx
,
393 struct tgsi_shader_info
*info
)
395 bool vs_window_space
;
400 /* When the VS disables clipping and viewport transformation. */
402 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
404 if (rctx
->vs_disables_clipping_viewport
!= vs_window_space
) {
405 rctx
->vs_disables_clipping_viewport
= vs_window_space
;
406 rctx
->scissors
.dirty_mask
= (1 << R600_MAX_VIEWPORTS
) - 1;
407 rctx
->set_atom_dirty(rctx
, &rctx
->scissors
.atom
, true);
410 /* Viewport index handling. */
411 rctx
->vs_writes_viewport_index
= info
->writes_viewport_index
;
412 if (!rctx
->vs_writes_viewport_index
)
415 if (rctx
->scissors
.dirty_mask
)
416 rctx
->set_atom_dirty(rctx
, &rctx
->scissors
.atom
, true);
418 if (rctx
->viewports
.dirty_mask
||
419 rctx
->viewports
.depth_range_dirty_mask
)
420 rctx
->set_atom_dirty(rctx
, &rctx
->viewports
.atom
, true);
423 void si_init_viewport_functions(struct r600_common_context
*rctx
)
425 rctx
->scissors
.atom
.emit
= r600_emit_scissors
;
426 rctx
->viewports
.atom
.emit
= r600_emit_viewport_states
;
428 rctx
->scissors
.atom
.num_dw
= (2 + 16 * 2) + 6;
429 rctx
->viewports
.atom
.num_dw
= 2 + 16 * 6;
431 rctx
->b
.set_scissor_states
= r600_set_scissor_states
;
432 rctx
->b
.set_viewport_states
= r600_set_viewport_states
;