src/gallium/drivers/radeonsi/si_state_viewport.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "radeon/r600_cs.h"
  25 #include "util/u_viewport.h"
  26 #include "tgsi/tgsi_scan.h"
  27
  28 #define GET_MAX_SCISSOR(rctx) (rctx->chip_class >= EVERGREEN ? 16384 : 8192)
  29
  30 static void r600_set_scissor_states(struct pipe_context *ctx,
  31                                     unsigned start_slot,
  32                                     unsigned num_scissors,
  33                                     const struct pipe_scissor_state *state)
  34 {
  35         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
  36         int i;
  37
  38         for (i = 0; i < num_scissors; i++)
  39                 rctx->scissors.states[start_slot + i] = state[i];
  40
  41         if (!rctx->scissor_enabled)
  42                 return;
  43
  44         rctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
  45         rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
  46 }
  47
  48 /* Since the guard band disables clipping, we have to clip per-pixel
  49  * using a scissor.
  50  */
  51 static void r600_get_scissor_from_viewport(struct r600_common_context *rctx,
  52                                            const struct pipe_viewport_state *vp,
  53                                            struct r600_signed_scissor *scissor)
  54 {
  55         float tmp, minx, miny, maxx, maxy;
  56
  57         /* Convert (-1, -1) and (1, 1) from clip space into window space. */
  58         minx = -vp->scale[0] + vp->translate[0];
  59         miny = -vp->scale[1] + vp->translate[1];
  60         maxx = vp->scale[0] + vp->translate[0];
  61         maxy = vp->scale[1] + vp->translate[1];
  62
  63         /* r600_draw_rectangle sets this. Disable the scissor. */
  64         if (minx == -1 && miny == -1 && maxx == 1 && maxy == 1) {
  65                 scissor->minx = scissor->miny = 0;
  66                 scissor->maxx = scissor->maxy = GET_MAX_SCISSOR(rctx);
  67                 return;
  68         }
  69
  70         /* Handle inverted viewports. */
  71         if (minx > maxx) {
  72                 tmp = minx;
  73                 minx = maxx;
  74                 maxx = tmp;
  75         }
  76         if (miny > maxy) {
  77                 tmp = miny;
  78                 miny = maxy;
  79                 maxy = tmp;
  80         }
  81
  82         /* Convert to integer and round up the max bounds. */
  83         scissor->minx = minx;
  84         scissor->miny = miny;
  85         scissor->maxx = ceilf(maxx);
  86         scissor->maxy = ceilf(maxy);
  87 }
  88
  89 static void r600_clamp_scissor(struct r600_common_context *rctx,
  90                                struct pipe_scissor_state *out,
  91                                struct r600_signed_scissor *scissor)
  92 {
  93         unsigned max_scissor = GET_MAX_SCISSOR(rctx);
  94         out->minx = CLAMP(scissor->minx, 0, max_scissor);
  95         out->miny = CLAMP(scissor->miny, 0, max_scissor);
  96         out->maxx = CLAMP(scissor->maxx, 0, max_scissor);
  97         out->maxy = CLAMP(scissor->maxy, 0, max_scissor);
  98 }
  99
 100 static void r600_clip_scissor(struct pipe_scissor_state *out,
 101                               struct pipe_scissor_state *clip)
 102 {
 103         out->minx = MAX2(out->minx, clip->minx);
 104         out->miny = MAX2(out->miny, clip->miny);
 105         out->maxx = MIN2(out->maxx, clip->maxx);
 106         out->maxy = MIN2(out->maxy, clip->maxy);
 107 }
 108
 109 static void r600_scissor_make_union(struct r600_signed_scissor *out,
 110                                     struct r600_signed_scissor *in)
 111 {
 112         out->minx = MIN2(out->minx, in->minx);
 113         out->miny = MIN2(out->miny, in->miny);
 114         out->maxx = MAX2(out->maxx, in->maxx);
 115         out->maxy = MAX2(out->maxy, in->maxy);
 116 }
 117
 118 void si_apply_scissor_bug_workaround(struct r600_common_context *rctx,
 119                                      struct pipe_scissor_state *scissor)
 120 {
 121         if (rctx->chip_class == EVERGREEN || rctx->chip_class == CAYMAN) {
 122                 if (scissor->maxx == 0)
 123                         scissor->minx = 1;
 124                 if (scissor->maxy == 0)
 125                         scissor->miny = 1;
 126
 127                 if (rctx->chip_class == CAYMAN &&
 128                     scissor->maxx == 1 && scissor->maxy == 1)
 129                         scissor->maxx = 2;
 130         }
 131 }
 132
 133 static void r600_emit_one_scissor(struct r600_common_context *rctx,
 134                                   struct radeon_winsys_cs *cs,
 135                                   struct r600_signed_scissor *vp_scissor,
 136                                   struct pipe_scissor_state *scissor)
 137 {
 138         struct pipe_scissor_state final;
 139
 140         if (rctx->vs_disables_clipping_viewport) {
 141                 final.minx = final.miny = 0;
 142                 final.maxx = final.maxy = GET_MAX_SCISSOR(rctx);
 143         } else {
 144                 r600_clamp_scissor(rctx, &final, vp_scissor);
 145         }
 146
 147         if (scissor)
 148                 r600_clip_scissor(&final, scissor);
 149
 150         si_apply_scissor_bug_workaround(rctx, &final);
 151
 152         radeon_emit(cs, S_028250_TL_X(final.minx) |
 153                         S_028250_TL_Y(final.miny) |
 154                         S_028250_WINDOW_OFFSET_DISABLE(1));
 155         radeon_emit(cs, S_028254_BR_X(final.maxx) |
 156                         S_028254_BR_Y(final.maxy));
 157 }
 158
 159 /* the range is [-MAX, MAX] */
 160 #define GET_MAX_VIEWPORT_RANGE(rctx) (rctx->chip_class >= EVERGREEN ? 32768 : 16384)
 161
 162 static void r600_emit_guardband(struct r600_common_context *rctx,
 163                                 struct r600_signed_scissor *vp_as_scissor)
 164 {
 165         struct radeon_winsys_cs *cs = rctx->gfx.cs;
 166         struct pipe_viewport_state vp;
 167         float left, top, right, bottom, max_range, guardband_x, guardband_y;
 168         float discard_x, discard_y;
 169
 170         /* Reconstruct the viewport transformation from the scissor. */
 171         vp.translate[0] = (vp_as_scissor->minx + vp_as_scissor->maxx) / 2.0;
 172         vp.translate[1] = (vp_as_scissor->miny + vp_as_scissor->maxy) / 2.0;
 173         vp.scale[0] = vp_as_scissor->maxx - vp.translate[0];
 174         vp.scale[1] = vp_as_scissor->maxy - vp.translate[1];
 175
 176         /* Treat a 0x0 viewport as 1x1 to prevent division by zero. */
 177         if (vp_as_scissor->minx == vp_as_scissor->maxx)
 178                 vp.scale[0] = 0.5;
 179         if (vp_as_scissor->miny == vp_as_scissor->maxy)
 180                 vp.scale[1] = 0.5;
 181
 182         /* Find the biggest guard band that is inside the supported viewport
 183          * range. The guard band is specified as a horizontal and vertical
 184          * distance from (0,0) in clip space.
 185          *
 186          * This is done by applying the inverse viewport transformation
 187          * on the viewport limits to get those limits in clip space.
 188          *
 189          * Use a limit one pixel smaller to allow for some precision error.
 190          */
 191         max_range = GET_MAX_VIEWPORT_RANGE(rctx) - 1;
 192         left   = (-max_range - vp.translate[0]) / vp.scale[0];
 193         right  = ( max_range - vp.translate[0]) / vp.scale[0];
 194         top    = (-max_range - vp.translate[1]) / vp.scale[1];
 195         bottom = ( max_range - vp.translate[1]) / vp.scale[1];
 196
 197         assert(left <= -1 && top <= -1 && right >= 1 && bottom >= 1);
 198
 199         guardband_x = MIN2(-left, right);
 200         guardband_y = MIN2(-top, bottom);
 201
 202         discard_x = 1.0;
 203         discard_y = 1.0;
 204
 205         if (rctx->current_rast_prim < PIPE_PRIM_TRIANGLES) {
 206                 /* When rendering wide points or lines, we need to be more
 207                  * conservative about when to discard them entirely. Since
 208                  * point size can be determined by the VS output, we basically
 209                  * disable discard completely completely here.
 210                  *
 211                  * TODO: This can hurt performance when rendering lines and
 212                  * points with fixed size, and could be improved.
 213                  */
 214                 discard_x = guardband_x;
 215                 discard_y = guardband_y;
 216         }
 217
 218         /* If any of the GB registers is updated, all of them must be updated. */
 219         if (rctx->chip_class >= CAYMAN)
 220                 radeon_set_context_reg_seq(cs, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
 221         else
 222                 radeon_set_context_reg_seq(cs, R600_R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
 223
 224         radeon_emit(cs, fui(guardband_y)); /* R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
 225         radeon_emit(cs, fui(discard_y));   /* R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
 226         radeon_emit(cs, fui(guardband_x)); /* R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
 227         radeon_emit(cs, fui(discard_x));   /* R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
 228 }
 229
 230 static void r600_emit_scissors(struct r600_common_context *rctx, struct r600_atom *atom)
 231 {
 232         struct radeon_winsys_cs *cs = rctx->gfx.cs;
 233         struct pipe_scissor_state *states = rctx->scissors.states;
 234         unsigned mask = rctx->scissors.dirty_mask;
 235         bool scissor_enabled = rctx->scissor_enabled;
 236         struct r600_signed_scissor max_vp_scissor;
 237         int i;
 238
 239         /* The simple case: Only 1 viewport is active. */
 240         if (!rctx->vs_writes_viewport_index) {
 241                 struct r600_signed_scissor *vp = &rctx->viewports.as_scissor[0];
 242
 243                 if (!(mask & 1))
 244                         return;
 245
 246                 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
 247                 r600_emit_one_scissor(rctx, cs, vp, scissor_enabled ? &states[0] : NULL);
 248                 r600_emit_guardband(rctx, vp);
 249                 rctx->scissors.dirty_mask &= ~1; /* clear one bit */
 250                 return;
 251         }
 252
 253         /* Shaders can draw to any viewport. Make a union of all viewports. */
 254         max_vp_scissor = rctx->viewports.as_scissor[0];
 255         for (i = 1; i < R600_MAX_VIEWPORTS; i++)
 256                 r600_scissor_make_union(&max_vp_scissor,
 257                                       &rctx->viewports.as_scissor[i]);
 258
 259         while (mask) {
 260                 int start, count, i;
 261
 262                 u_bit_scan_consecutive_range(&mask, &start, &count);
 263
 264                 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
 265                                                start * 4 * 2, count * 2);
 266                 for (i = start; i < start+count; i++) {
 267                         r600_emit_one_scissor(rctx, cs, &rctx->viewports.as_scissor[i],
 268                                               scissor_enabled ? &states[i] : NULL);
 269                 }
 270         }
 271         r600_emit_guardband(rctx, &max_vp_scissor);
 272         rctx->scissors.dirty_mask = 0;
 273 }
 274
 275 static void r600_set_viewport_states(struct pipe_context *ctx,
 276                                      unsigned start_slot,
 277                                      unsigned num_viewports,
 278                                      const struct pipe_viewport_state *state)
 279 {
 280         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 281         unsigned mask;
 282         int i;
 283
 284         for (i = 0; i < num_viewports; i++) {
 285                 unsigned index = start_slot + i;
 286
 287                 rctx->viewports.states[index] = state[i];
 288                 r600_get_scissor_from_viewport(rctx, &state[i],
 289                                                &rctx->viewports.as_scissor[index]);
 290         }
 291
 292         mask = ((1 << num_viewports) - 1) << start_slot;
 293         rctx->viewports.dirty_mask |= mask;
 294         rctx->viewports.depth_range_dirty_mask |= mask;
 295         rctx->scissors.dirty_mask |= mask;
 296         rctx->set_atom_dirty(rctx, &rctx->viewports.atom, true);
 297         rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
 298 }
 299
 300 static void r600_emit_one_viewport(struct r600_common_context *rctx,
 301                                    struct pipe_viewport_state *state)
 302 {
 303         struct radeon_winsys_cs *cs = rctx->gfx.cs;
 304
 305         radeon_emit(cs, fui(state->scale[0]));
 306         radeon_emit(cs, fui(state->translate[0]));
 307         radeon_emit(cs, fui(state->scale[1]));
 308         radeon_emit(cs, fui(state->translate[1]));
 309         radeon_emit(cs, fui(state->scale[2]));
 310         radeon_emit(cs, fui(state->translate[2]));
 311 }
 312
 313 static void r600_emit_viewports(struct r600_common_context *rctx)
 314 {
 315         struct radeon_winsys_cs *cs = rctx->gfx.cs;
 316         struct pipe_viewport_state *states = rctx->viewports.states;
 317         unsigned mask = rctx->viewports.dirty_mask;
 318
 319         /* The simple case: Only 1 viewport is active. */
 320         if (!rctx->vs_writes_viewport_index) {
 321                 if (!(mask & 1))
 322                         return;
 323
 324                 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
 325                 r600_emit_one_viewport(rctx, &states[0]);
 326                 rctx->viewports.dirty_mask &= ~1; /* clear one bit */
 327                 return;
 328         }
 329
 330         while (mask) {
 331                 int start, count, i;
 332
 333                 u_bit_scan_consecutive_range(&mask, &start, &count);
 334
 335                 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
 336                                                start * 4 * 6, count * 6);
 337                 for (i = start; i < start+count; i++)
 338                         r600_emit_one_viewport(rctx, &states[i]);
 339         }
 340         rctx->viewports.dirty_mask = 0;
 341 }
 342
 343 static void r600_emit_depth_ranges(struct r600_common_context *rctx)
 344 {
 345         struct radeon_winsys_cs *cs = rctx->gfx.cs;
 346         struct pipe_viewport_state *states = rctx->viewports.states;
 347         unsigned mask = rctx->viewports.depth_range_dirty_mask;
 348         float zmin, zmax;
 349
 350         /* The simple case: Only 1 viewport is active. */
 351         if (!rctx->vs_writes_viewport_index) {
 352                 if (!(mask & 1))
 353                         return;
 354
 355                 util_viewport_zmin_zmax(&states[0], rctx->clip_halfz, &zmin, &zmax);
 356
 357                 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
 358                 radeon_emit(cs, fui(zmin));
 359                 radeon_emit(cs, fui(zmax));
 360                 rctx->viewports.depth_range_dirty_mask &= ~1; /* clear one bit */
 361                 return;
 362         }
 363
 364         while (mask) {
 365                 int start, count, i;
 366
 367                 u_bit_scan_consecutive_range(&mask, &start, &count);
 368
 369                 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
 370                                            start * 4 * 2, count * 2);
 371                 for (i = start; i < start+count; i++) {
 372                         util_viewport_zmin_zmax(&states[i], rctx->clip_halfz, &zmin, &zmax);
 373                         radeon_emit(cs, fui(zmin));
 374                         radeon_emit(cs, fui(zmax));
 375                 }
 376         }
 377         rctx->viewports.depth_range_dirty_mask = 0;
 378 }
 379
 380 static void r600_emit_viewport_states(struct r600_common_context *rctx,
 381                                       struct r600_atom *atom)
 382 {
 383         r600_emit_viewports(rctx);
 384         r600_emit_depth_ranges(rctx);
 385 }
 386
 387 /* Set viewport dependencies on pipe_rasterizer_state. */
 388 void si_viewport_set_rast_deps(struct r600_common_context *rctx,
 389                                bool scissor_enable, bool clip_halfz)
 390 {
 391         if (rctx->scissor_enabled != scissor_enable) {
 392                 rctx->scissor_enabled = scissor_enable;
 393                 rctx->scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
 394                 rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
 395         }
 396         if (rctx->clip_halfz != clip_halfz) {
 397                 rctx->clip_halfz = clip_halfz;
 398                 rctx->viewports.depth_range_dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
 399                 rctx->set_atom_dirty(rctx, &rctx->viewports.atom, true);
 400         }
 401 }
 402
 403 /**
 404  * Normally, we only emit 1 viewport and 1 scissor if no shader is using
 405  * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
 406  * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
 407  * called to emit the rest.
 408  */
 409 void si_update_vs_writes_viewport_index(struct r600_common_context *rctx,
 410                                         struct tgsi_shader_info *info)
 411 {
 412         bool vs_window_space;
 413
 414         if (!info)
 415                 return;
 416
 417         /* When the VS disables clipping and viewport transformation. */
 418         vs_window_space =
 419                 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
 420
 421         if (rctx->vs_disables_clipping_viewport != vs_window_space) {
 422                 rctx->vs_disables_clipping_viewport = vs_window_space;
 423                 rctx->scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
 424                 rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
 425         }
 426
 427         /* Viewport index handling. */
 428         rctx->vs_writes_viewport_index = info->writes_viewport_index;
 429         if (!rctx->vs_writes_viewport_index)
 430                 return;
 431
 432         if (rctx->scissors.dirty_mask)
 433             rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
 434
 435         if (rctx->viewports.dirty_mask ||
 436             rctx->viewports.depth_range_dirty_mask)
 437             rctx->set_atom_dirty(rctx, &rctx->viewports.atom, true);
 438 }
 439
 440 void si_init_viewport_functions(struct r600_common_context *rctx)
 441 {
 442         rctx->scissors.atom.emit = r600_emit_scissors;
 443         rctx->viewports.atom.emit = r600_emit_viewport_states;
 444
 445         rctx->scissors.atom.num_dw = (2 + 16 * 2) + 6;
 446         rctx->viewports.atom.num_dw = 2 + 16 * 6;
 447
 448         rctx->b.set_scissor_states = r600_set_scissor_states;
 449         rctx->b.set_viewport_states = r600_set_viewport_states;
 450 }