src/gallium/drivers/radeonsi/si_state_viewport.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_build_pm4.h"
  26 #include "util/u_viewport.h"
  27 #include "tgsi/tgsi_scan.h"
  28
  29 #define SI_MAX_SCISSOR 16384
  30
  31 static void si_set_scissor_states(struct pipe_context *pctx,
  32                                   unsigned start_slot,
  33                                   unsigned num_scissors,
  34                                   const struct pipe_scissor_state *state)
  35 {
  36         struct si_context *ctx = (struct si_context *)pctx;
  37         int i;
  38
  39         for (i = 0; i < num_scissors; i++)
  40                 ctx->scissors.states[start_slot + i] = state[i];
  41
  42         if (!ctx->queued.named.rasterizer ||
  43             !ctx->queued.named.rasterizer->scissor_enable)
  44                 return;
  45
  46         ctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
  47         si_mark_atom_dirty(ctx, &ctx->scissors.atom);
  48 }
  49
  50 /* Since the guard band disables clipping, we have to clip per-pixel
  51  * using a scissor.
  52  */
  53 static void si_get_scissor_from_viewport(struct si_context *ctx,
  54                                          const struct pipe_viewport_state *vp,
  55                                          struct si_signed_scissor *scissor)
  56 {
  57         float tmp, minx, miny, maxx, maxy;
  58
  59         /* Convert (-1, -1) and (1, 1) from clip space into window space. */
  60         minx = -vp->scale[0] + vp->translate[0];
  61         miny = -vp->scale[1] + vp->translate[1];
  62         maxx = vp->scale[0] + vp->translate[0];
  63         maxy = vp->scale[1] + vp->translate[1];
  64
  65         /* Handle inverted viewports. */
  66         if (minx > maxx) {
  67                 tmp = minx;
  68                 minx = maxx;
  69                 maxx = tmp;
  70         }
  71         if (miny > maxy) {
  72                 tmp = miny;
  73                 miny = maxy;
  74                 maxy = tmp;
  75         }
  76
  77         /* Convert to integer and round up the max bounds. */
  78         scissor->minx = minx;
  79         scissor->miny = miny;
  80         scissor->maxx = ceilf(maxx);
  81         scissor->maxy = ceilf(maxy);
  82 }
  83
  84 static void si_clamp_scissor(struct si_context *ctx,
  85                              struct pipe_scissor_state *out,
  86                              struct si_signed_scissor *scissor)
  87 {
  88         out->minx = CLAMP(scissor->minx, 0, SI_MAX_SCISSOR);
  89         out->miny = CLAMP(scissor->miny, 0, SI_MAX_SCISSOR);
  90         out->maxx = CLAMP(scissor->maxx, 0, SI_MAX_SCISSOR);
  91         out->maxy = CLAMP(scissor->maxy, 0, SI_MAX_SCISSOR);
  92 }
  93
  94 static void si_clip_scissor(struct pipe_scissor_state *out,
  95                             struct pipe_scissor_state *clip)
  96 {
  97         out->minx = MAX2(out->minx, clip->minx);
  98         out->miny = MAX2(out->miny, clip->miny);
  99         out->maxx = MIN2(out->maxx, clip->maxx);
 100         out->maxy = MIN2(out->maxy, clip->maxy);
 101 }
 102
 103 static void si_scissor_make_union(struct si_signed_scissor *out,
 104                                   struct si_signed_scissor *in)
 105 {
 106         out->minx = MIN2(out->minx, in->minx);
 107         out->miny = MIN2(out->miny, in->miny);
 108         out->maxx = MAX2(out->maxx, in->maxx);
 109         out->maxy = MAX2(out->maxy, in->maxy);
 110 }
 111
 112 static void si_emit_one_scissor(struct si_context *ctx,
 113                                 struct radeon_winsys_cs *cs,
 114                                 struct si_signed_scissor *vp_scissor,
 115                                 struct pipe_scissor_state *scissor)
 116 {
 117         struct pipe_scissor_state final;
 118
 119         if (ctx->vs_disables_clipping_viewport) {
 120                 final.minx = final.miny = 0;
 121                 final.maxx = final.maxy = SI_MAX_SCISSOR;
 122         } else {
 123                 si_clamp_scissor(ctx, &final, vp_scissor);
 124         }
 125
 126         if (scissor)
 127                 si_clip_scissor(&final, scissor);
 128
 129         radeon_emit(cs, S_028250_TL_X(final.minx) |
 130                         S_028250_TL_Y(final.miny) |
 131                         S_028250_WINDOW_OFFSET_DISABLE(1));
 132         radeon_emit(cs, S_028254_BR_X(final.maxx) |
 133                         S_028254_BR_Y(final.maxy));
 134 }
 135
 136 /* the range is [-MAX, MAX] */
 137 #define SI_MAX_VIEWPORT_RANGE 32768
 138
 139 static void si_emit_guardband(struct si_context *ctx,
 140                               struct si_signed_scissor *vp_as_scissor)
 141 {
 142         struct radeon_winsys_cs *cs = ctx->gfx_cs;
 143         struct pipe_viewport_state vp;
 144         float left, top, right, bottom, max_range, guardband_x, guardband_y;
 145         float discard_x, discard_y;
 146
 147         /* Reconstruct the viewport transformation from the scissor. */
 148         vp.translate[0] = (vp_as_scissor->minx + vp_as_scissor->maxx) / 2.0;
 149         vp.translate[1] = (vp_as_scissor->miny + vp_as_scissor->maxy) / 2.0;
 150         vp.scale[0] = vp_as_scissor->maxx - vp.translate[0];
 151         vp.scale[1] = vp_as_scissor->maxy - vp.translate[1];
 152
 153         /* Treat a 0x0 viewport as 1x1 to prevent division by zero. */
 154         if (vp_as_scissor->minx == vp_as_scissor->maxx)
 155                 vp.scale[0] = 0.5;
 156         if (vp_as_scissor->miny == vp_as_scissor->maxy)
 157                 vp.scale[1] = 0.5;
 158
 159         /* Find the biggest guard band that is inside the supported viewport
 160          * range. The guard band is specified as a horizontal and vertical
 161          * distance from (0,0) in clip space.
 162          *
 163          * This is done by applying the inverse viewport transformation
 164          * on the viewport limits to get those limits in clip space.
 165          *
 166          * Use a limit one pixel smaller to allow for some precision error.
 167          */
 168         max_range = SI_MAX_VIEWPORT_RANGE - 1;
 169         left   = (-max_range - vp.translate[0]) / vp.scale[0];
 170         right  = ( max_range - vp.translate[0]) / vp.scale[0];
 171         top    = (-max_range - vp.translate[1]) / vp.scale[1];
 172         bottom = ( max_range - vp.translate[1]) / vp.scale[1];
 173
 174         assert(left <= -1 && top <= -1 && right >= 1 && bottom >= 1);
 175
 176         guardband_x = MIN2(-left, right);
 177         guardband_y = MIN2(-top, bottom);
 178
 179         discard_x = 1.0;
 180         discard_y = 1.0;
 181
 182         if (unlikely(ctx->current_rast_prim < PIPE_PRIM_TRIANGLES) &&
 183             ctx->queued.named.rasterizer) {
 184                 /* When rendering wide points or lines, we need to be more
 185                  * conservative about when to discard them entirely. */
 186                 const struct si_state_rasterizer *rs = ctx->queued.named.rasterizer;
 187                 float pixels;
 188
 189                 if (ctx->current_rast_prim == PIPE_PRIM_POINTS)
 190                         pixels = rs->max_point_size;
 191                 else
 192                         pixels = rs->line_width;
 193
 194                 /* Add half the point size / line width */
 195                 discard_x += pixels / (2.0 * vp.scale[0]);
 196                 discard_y += pixels / (2.0 * vp.scale[1]);
 197
 198                 /* Discard primitives that would lie entirely outside the clip
 199                  * region. */
 200                 discard_x = MIN2(discard_x, guardband_x);
 201                 discard_y = MIN2(discard_y, guardband_y);
 202         }
 203
 204         /* If any of the GB registers is updated, all of them must be updated. */
 205         radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
 206
 207         radeon_emit(cs, fui(guardband_y)); /* R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
 208         radeon_emit(cs, fui(discard_y));   /* R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
 209         radeon_emit(cs, fui(guardband_x)); /* R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
 210         radeon_emit(cs, fui(discard_x));   /* R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
 211 }
 212
 213 static void si_emit_scissors(struct si_context *ctx, struct r600_atom *atom)
 214 {
 215         struct radeon_winsys_cs *cs = ctx->gfx_cs;
 216         struct pipe_scissor_state *states = ctx->scissors.states;
 217         unsigned mask = ctx->scissors.dirty_mask;
 218         bool scissor_enabled = false;
 219         struct si_signed_scissor max_vp_scissor;
 220         int i;
 221
 222         if (ctx->queued.named.rasterizer)
 223                 scissor_enabled = ctx->queued.named.rasterizer->scissor_enable;
 224
 225         /* The simple case: Only 1 viewport is active. */
 226         if (!ctx->vs_writes_viewport_index) {
 227                 struct si_signed_scissor *vp = &ctx->viewports.as_scissor[0];
 228
 229                 if (!(mask & 1))
 230                         return;
 231
 232                 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
 233                 si_emit_one_scissor(ctx, cs, vp, scissor_enabled ? &states[0] : NULL);
 234                 si_emit_guardband(ctx, vp);
 235                 ctx->scissors.dirty_mask &= ~1; /* clear one bit */
 236                 return;
 237         }
 238
 239         /* Shaders can draw to any viewport. Make a union of all viewports. */
 240         max_vp_scissor = ctx->viewports.as_scissor[0];
 241         for (i = 1; i < SI_MAX_VIEWPORTS; i++)
 242                 si_scissor_make_union(&max_vp_scissor,
 243                                       &ctx->viewports.as_scissor[i]);
 244
 245         while (mask) {
 246                 int start, count, i;
 247
 248                 u_bit_scan_consecutive_range(&mask, &start, &count);
 249
 250                 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
 251                                                start * 4 * 2, count * 2);
 252                 for (i = start; i < start+count; i++) {
 253                         si_emit_one_scissor(ctx, cs, &ctx->viewports.as_scissor[i],
 254                                             scissor_enabled ? &states[i] : NULL);
 255                 }
 256         }
 257         si_emit_guardband(ctx, &max_vp_scissor);
 258         ctx->scissors.dirty_mask = 0;
 259 }
 260
 261 static void si_set_viewport_states(struct pipe_context *pctx,
 262                                    unsigned start_slot,
 263                                    unsigned num_viewports,
 264                                    const struct pipe_viewport_state *state)
 265 {
 266         struct si_context *ctx = (struct si_context *)pctx;
 267         unsigned mask;
 268         int i;
 269
 270         for (i = 0; i < num_viewports; i++) {
 271                 unsigned index = start_slot + i;
 272
 273                 ctx->viewports.states[index] = state[i];
 274                 si_get_scissor_from_viewport(ctx, &state[i],
 275                                              &ctx->viewports.as_scissor[index]);
 276         }
 277
 278         mask = ((1 << num_viewports) - 1) << start_slot;
 279         ctx->viewports.dirty_mask |= mask;
 280         ctx->viewports.depth_range_dirty_mask |= mask;
 281         ctx->scissors.dirty_mask |= mask;
 282         si_mark_atom_dirty(ctx, &ctx->viewports.atom);
 283         si_mark_atom_dirty(ctx, &ctx->scissors.atom);
 284 }
 285
 286 static void si_emit_one_viewport(struct si_context *ctx,
 287                                  struct pipe_viewport_state *state)
 288 {
 289         struct radeon_winsys_cs *cs = ctx->gfx_cs;
 290
 291         radeon_emit(cs, fui(state->scale[0]));
 292         radeon_emit(cs, fui(state->translate[0]));
 293         radeon_emit(cs, fui(state->scale[1]));
 294         radeon_emit(cs, fui(state->translate[1]));
 295         radeon_emit(cs, fui(state->scale[2]));
 296         radeon_emit(cs, fui(state->translate[2]));
 297 }
 298
 299 static void si_emit_viewports(struct si_context *ctx)
 300 {
 301         struct radeon_winsys_cs *cs = ctx->gfx_cs;
 302         struct pipe_viewport_state *states = ctx->viewports.states;
 303         unsigned mask = ctx->viewports.dirty_mask;
 304
 305         /* The simple case: Only 1 viewport is active. */
 306         if (!ctx->vs_writes_viewport_index) {
 307                 if (!(mask & 1))
 308                         return;
 309
 310                 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
 311                 si_emit_one_viewport(ctx, &states[0]);
 312                 ctx->viewports.dirty_mask &= ~1; /* clear one bit */
 313                 return;
 314         }
 315
 316         while (mask) {
 317                 int start, count, i;
 318
 319                 u_bit_scan_consecutive_range(&mask, &start, &count);
 320
 321                 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
 322                                                start * 4 * 6, count * 6);
 323                 for (i = start; i < start+count; i++)
 324                         si_emit_one_viewport(ctx, &states[i]);
 325         }
 326         ctx->viewports.dirty_mask = 0;
 327 }
 328
 329 static inline void
 330 si_viewport_zmin_zmax(const struct pipe_viewport_state *vp, bool halfz,
 331                       bool window_space_position, float *zmin, float *zmax)
 332 {
 333         if (window_space_position) {
 334                 *zmin = 0;
 335                 *zmax = 1;
 336                 return;
 337         }
 338         util_viewport_zmin_zmax(vp, halfz, zmin, zmax);
 339 }
 340
 341 static void si_emit_depth_ranges(struct si_context *ctx)
 342 {
 343         struct radeon_winsys_cs *cs = ctx->gfx_cs;
 344         struct pipe_viewport_state *states = ctx->viewports.states;
 345         unsigned mask = ctx->viewports.depth_range_dirty_mask;
 346         bool clip_halfz = false;
 347         bool window_space = ctx->vs_disables_clipping_viewport;
 348         float zmin, zmax;
 349
 350         if (ctx->queued.named.rasterizer)
 351                 clip_halfz = ctx->queued.named.rasterizer->clip_halfz;
 352
 353         /* The simple case: Only 1 viewport is active. */
 354         if (!ctx->vs_writes_viewport_index) {
 355                 if (!(mask & 1))
 356                         return;
 357
 358                 si_viewport_zmin_zmax(&states[0], clip_halfz, window_space,
 359                                       &zmin, &zmax);
 360
 361                 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
 362                 radeon_emit(cs, fui(zmin));
 363                 radeon_emit(cs, fui(zmax));
 364                 ctx->viewports.depth_range_dirty_mask &= ~1; /* clear one bit */
 365                 return;
 366         }
 367
 368         while (mask) {
 369                 int start, count, i;
 370
 371                 u_bit_scan_consecutive_range(&mask, &start, &count);
 372
 373                 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
 374                                            start * 4 * 2, count * 2);
 375                 for (i = start; i < start+count; i++) {
 376                         si_viewport_zmin_zmax(&states[i], clip_halfz, window_space,
 377                                               &zmin, &zmax);
 378                         radeon_emit(cs, fui(zmin));
 379                         radeon_emit(cs, fui(zmax));
 380                 }
 381         }
 382         ctx->viewports.depth_range_dirty_mask = 0;
 383 }
 384
 385 static void si_emit_viewport_states(struct si_context *ctx,
 386                                     struct r600_atom *atom)
 387 {
 388         si_emit_viewports(ctx);
 389         si_emit_depth_ranges(ctx);
 390 }
 391
 392 /**
 393  * This reacts to 2 state changes:
 394  * - VS.writes_viewport_index
 395  * - VS output position in window space (enable/disable)
 396  *
 397  * Normally, we only emit 1 viewport and 1 scissor if no shader is using
 398  * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
 399  * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
 400  * called to emit the rest.
 401  */
 402 void si_update_vs_viewport_state(struct si_context *ctx)
 403 {
 404         struct tgsi_shader_info *info = si_get_vs_info(ctx);
 405         bool vs_window_space;
 406
 407         if (!info)
 408                 return;
 409
 410         /* When the VS disables clipping and viewport transformation. */
 411         vs_window_space =
 412                 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
 413
 414         if (ctx->vs_disables_clipping_viewport != vs_window_space) {
 415                 ctx->vs_disables_clipping_viewport = vs_window_space;
 416                 ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 417                 ctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 418                 si_mark_atom_dirty(ctx, &ctx->scissors.atom);
 419                 si_mark_atom_dirty(ctx, &ctx->viewports.atom);
 420         }
 421
 422         /* Viewport index handling. */
 423         ctx->vs_writes_viewport_index = info->writes_viewport_index;
 424         if (!ctx->vs_writes_viewport_index)
 425                 return;
 426
 427         if (ctx->scissors.dirty_mask)
 428             si_mark_atom_dirty(ctx, &ctx->scissors.atom);
 429
 430         if (ctx->viewports.dirty_mask ||
 431             ctx->viewports.depth_range_dirty_mask)
 432             si_mark_atom_dirty(ctx, &ctx->viewports.atom);
 433 }
 434
 435 void si_init_viewport_functions(struct si_context *ctx)
 436 {
 437         ctx->scissors.atom.emit = si_emit_scissors;
 438         ctx->viewports.atom.emit = si_emit_viewport_states;
 439
 440         ctx->b.set_scissor_states = si_set_scissor_states;
 441         ctx->b.set_viewport_states = si_set_viewport_states;
 442 }