src/gallium/drivers/radeonsi/si_test_dma.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  */
  25
  26 /* This file implements randomized SDMA texture blit tests. */
  27
  28 #include "si_pipe.h"
  29 #include "util/u_surface.h"
  30 #include "util/rand_xor.h"
  31
  32 static uint64_t seed_xorshift128plus[2];
  33
  34 #define RAND_NUM_SIZE 8
  35
  36 /* The GPU blits are emulated on the CPU using these CPU textures. */
  37
  38 struct cpu_texture {
  39         uint8_t *ptr;
  40         uint64_t size;
  41         uint64_t layer_stride;
  42         unsigned stride;
  43 };
  44
  45 static void alloc_cpu_texture(struct cpu_texture *tex,
  46                               struct pipe_resource *templ)
  47 {
  48         tex->stride = align(util_format_get_stride(templ->format, templ->width0),
  49                             RAND_NUM_SIZE);
  50         tex->layer_stride = (uint64_t)tex->stride * templ->height0;
  51         tex->size = tex->layer_stride * templ->array_size;
  52         tex->ptr = malloc(tex->size);
  53         assert(tex->ptr);
  54 }
  55
  56 static void set_random_pixels(struct pipe_context *ctx,
  57                               struct pipe_resource *tex,
  58                               struct cpu_texture *cpu)
  59 {
  60         struct pipe_transfer *t;
  61         uint8_t *map;
  62         int x,y,z;
  63
  64         map = pipe_transfer_map_3d(ctx, tex, 0, PIPE_TRANSFER_WRITE,
  65                                    0, 0, 0, tex->width0, tex->height0,
  66                                    tex->array_size, &t);
  67         assert(map);
  68
  69         for (z = 0; z < tex->array_size; z++) {
  70                 for (y = 0; y < tex->height0; y++) {
  71                         uint64_t *ptr = (uint64_t*)
  72                                 (map + t->layer_stride*z + t->stride*y);
  73                         uint64_t *ptr_cpu = (uint64_t*)
  74                                 (cpu->ptr + cpu->layer_stride*z + cpu->stride*y);
  75                         unsigned size = cpu->stride / RAND_NUM_SIZE;
  76
  77                         assert(t->stride % RAND_NUM_SIZE == 0);
  78                         assert(cpu->stride % RAND_NUM_SIZE == 0);
  79
  80                         for (x = 0; x < size; x++) {
  81                                 *ptr++ = *ptr_cpu++ =
  82                                         rand_xorshift128plus(seed_xorshift128plus);
  83                         }
  84                 }
  85         }
  86
  87         pipe_transfer_unmap(ctx, t);
  88 }
  89
  90 static bool compare_textures(struct pipe_context *ctx,
  91                              struct pipe_resource *tex,
  92                              struct cpu_texture *cpu)
  93 {
  94         struct pipe_transfer *t;
  95         uint8_t *map;
  96         int y,z;
  97         bool pass = true;
  98         unsigned stride = util_format_get_stride(tex->format, tex->width0);
  99
 100         map = pipe_transfer_map_3d(ctx, tex, 0, PIPE_TRANSFER_READ,
 101                                    0, 0, 0, tex->width0, tex->height0,
 102                                    tex->array_size, &t);
 103         assert(map);
 104
 105         for (z = 0; z < tex->array_size; z++) {
 106                 for (y = 0; y < tex->height0; y++) {
 107                         uint8_t *ptr = map + t->layer_stride*z + t->stride*y;
 108                         uint8_t *cpu_ptr = cpu->ptr +
 109                                            cpu->layer_stride*z + cpu->stride*y;
 110
 111                         if (memcmp(ptr, cpu_ptr, stride)) {
 112                                 pass = false;
 113                                 goto done;
 114                         }
 115                 }
 116         }
 117 done:
 118         pipe_transfer_unmap(ctx, t);
 119         return pass;
 120 }
 121
 122 static enum pipe_format choose_format()
 123 {
 124         enum pipe_format formats[] = {
 125                 PIPE_FORMAT_R8_UINT,
 126                 PIPE_FORMAT_R16_UINT,
 127                 PIPE_FORMAT_R32_UINT,
 128                 PIPE_FORMAT_R32G32_UINT,
 129                 PIPE_FORMAT_R32G32B32A32_UINT,
 130                 PIPE_FORMAT_G8R8_B8R8_UNORM,
 131         };
 132         return formats[rand() % ARRAY_SIZE(formats)];
 133 }
 134
 135 static const char *array_mode_to_string(struct si_screen *sscreen,
 136                                         struct radeon_surf *surf)
 137 {
 138         if (sscreen->info.chip_class >= GFX9) {
 139                 switch (surf->u.gfx9.surf.swizzle_mode) {
 140                 case 0:
 141                         return "  LINEAR";
 142                 case 21:
 143                         return " 4KB_S_X";
 144                 case 22:
 145                         return " 4KB_D_X";
 146                 case 25:
 147                         return "64KB_S_X";
 148                 case 26:
 149                         return "64KB_D_X";
 150                 default:
 151                         printf("Unhandled swizzle mode = %u\n",
 152                                surf->u.gfx9.surf.swizzle_mode);
 153                         return " UNKNOWN";
 154                 }
 155         } else {
 156                 switch (surf->u.legacy.level[0].mode) {
 157                 case RADEON_SURF_MODE_LINEAR_ALIGNED:
 158                         return "LINEAR_ALIGNED";
 159                 case RADEON_SURF_MODE_1D:
 160                         return "1D_TILED_THIN1";
 161                 case RADEON_SURF_MODE_2D:
 162                         return "2D_TILED_THIN1";
 163                 default:
 164                         assert(0);
 165                         return "       UNKNOWN";
 166                 }
 167         }
 168 }
 169
 170 static unsigned generate_max_tex_side(unsigned max_tex_side)
 171 {
 172         switch (rand() % 4) {
 173         case 0:
 174                 /* Try to hit large sizes in 1/4 of the cases. */
 175                 return max_tex_side;
 176         case 1:
 177                 /* Try to hit 1D tiling in 1/4 of the cases. */
 178                 return 128;
 179         default:
 180                 /* Try to hit common sizes in 2/4 of the cases. */
 181                 return 2048;
 182         }
 183 }
 184
 185 void si_test_dma(struct si_screen *sscreen)
 186 {
 187         struct pipe_screen *screen = &sscreen->b;
 188         struct pipe_context *ctx = screen->context_create(screen, NULL, 0);
 189         struct si_context *sctx = (struct si_context*)ctx;
 190         uint64_t max_alloc_size;
 191         unsigned i, iterations, num_partial_copies, max_tex_side;
 192         unsigned num_pass = 0, num_fail = 0;
 193
 194         max_tex_side = screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_SIZE);
 195
 196         /* Max 128 MB allowed for both textures. */
 197         max_alloc_size = 128 * 1024 * 1024;
 198
 199         /* the seed for random test parameters */
 200         srand(0x9b47d95b);
 201         /* the seed for random pixel data */
 202         s_rand_xorshift128plus(seed_xorshift128plus, false);
 203
 204         iterations = 1000000000; /* just kill it when you are bored */
 205         num_partial_copies = 30;
 206
 207         /* These parameters are randomly generated per test:
 208          * - whether to do one whole-surface copy or N partial copies per test
 209          * - which tiling modes to use (LINEAR_ALIGNED, 1D, 2D)
 210          * - which texture dimensions to use
 211          * - whether to use VRAM (all tiling modes) and GTT (staging, linear
 212          *   only) allocations
 213          * - random initial pixels in src
 214          * - generate random subrectangle copies for partial blits
 215          */
 216         for (i = 0; i < iterations; i++) {
 217                 struct pipe_resource tsrc = {}, tdst = {}, *src, *dst;
 218                 struct si_texture *sdst;
 219                 struct si_texture *ssrc;
 220                 struct cpu_texture src_cpu, dst_cpu;
 221                 unsigned max_width, max_height, max_depth, j, num;
 222                 unsigned gfx_blits = 0, dma_blits = 0, cs_blits = 0, max_tex_side_gen;
 223                 unsigned max_tex_layers;
 224                 bool pass;
 225                 bool do_partial_copies = rand() & 1;
 226
 227                 /* generate a random test case */
 228                 tsrc.target = tdst.target = PIPE_TEXTURE_2D_ARRAY;
 229                 tsrc.depth0 = tdst.depth0 = 1;
 230
 231                 tsrc.format = tdst.format = choose_format();
 232
 233                 max_tex_side_gen = generate_max_tex_side(max_tex_side);
 234                 max_tex_layers = rand() % 4 ? 1 : 5;
 235
 236                 tsrc.width0 = (rand() % max_tex_side_gen) + 1;
 237                 tsrc.height0 = (rand() % max_tex_side_gen) + 1;
 238                 tsrc.array_size = (rand() % max_tex_layers) + 1;
 239
 240                 if (tsrc.format == PIPE_FORMAT_G8R8_B8R8_UNORM)
 241                         tsrc.width0 = align(tsrc.width0, 2);
 242
 243                 /* Have a 1/4 chance of getting power-of-two dimensions. */
 244                 if (rand() % 4 == 0) {
 245                         tsrc.width0 = util_next_power_of_two(tsrc.width0);
 246                         tsrc.height0 = util_next_power_of_two(tsrc.height0);
 247                 }
 248
 249                 if (!do_partial_copies) {
 250                         /* whole-surface copies only, same dimensions */
 251                         tdst = tsrc;
 252                 } else {
 253                         max_tex_side_gen = generate_max_tex_side(max_tex_side);
 254                         max_tex_layers = rand() % 4 ? 1 : 5;
 255
 256                         /* many partial copies, dimensions can be different */
 257                         tdst.width0 = (rand() % max_tex_side_gen) + 1;
 258                         tdst.height0 = (rand() % max_tex_side_gen) + 1;
 259                         tdst.array_size = (rand() % max_tex_layers) + 1;
 260
 261                         /* Have a 1/4 chance of getting power-of-two dimensions. */
 262                         if (rand() % 4 == 0) {
 263                                 tdst.width0 = util_next_power_of_two(tdst.width0);
 264                                 tdst.height0 = util_next_power_of_two(tdst.height0);
 265                         }
 266                 }
 267
 268                 /* check texture sizes */
 269                 if ((uint64_t) util_format_get_nblocks(tsrc.format, tsrc.width0, tsrc.height0)
 270                         * tsrc.array_size * util_format_get_blocksize(tsrc.format) +
 271                     (uint64_t) util_format_get_nblocks(tdst.format, tdst.width0, tdst.height0)
 272                         * tdst.array_size * util_format_get_blocksize(tdst.format) >
 273                     max_alloc_size) {
 274                         /* too large, try again */
 275                         i--;
 276                         continue;
 277                 }
 278
 279                 /* VRAM + the tiling mode depends on dimensions (3/4 of cases),
 280                  * or GTT + linear only (1/4 of cases)
 281                  */
 282                 tsrc.usage = rand() % 4 ? PIPE_USAGE_DEFAULT : PIPE_USAGE_STAGING;
 283                 tdst.usage = rand() % 4 ? PIPE_USAGE_DEFAULT : PIPE_USAGE_STAGING;
 284
 285                 /* Allocate textures (both the GPU and CPU copies).
 286                  * The CPU will emulate what the GPU should be doing.
 287                  */
 288                 src = screen->resource_create(screen, &tsrc);
 289                 dst = screen->resource_create(screen, &tdst);
 290                 assert(src);
 291                 assert(dst);
 292                 sdst = (struct si_texture*)dst;
 293                 ssrc = (struct si_texture*)src;
 294                 alloc_cpu_texture(&src_cpu, &tsrc);
 295                 alloc_cpu_texture(&dst_cpu, &tdst);
 296
 297                 printf("%4u: dst = (%5u x %5u x %u, %s), "
 298                        " src = (%5u x %5u x %u, %s), format = %s, ",
 299                        i, tdst.width0, tdst.height0, tdst.array_size,
 300                        array_mode_to_string(sscreen, &sdst->surface),
 301                        tsrc.width0, tsrc.height0, tsrc.array_size,
 302                        array_mode_to_string(sscreen, &ssrc->surface),
 303                        util_format_description(tsrc.format)->name);
 304                 fflush(stdout);
 305
 306                 /* set src pixels */
 307                 set_random_pixels(ctx, src, &src_cpu);
 308
 309                 /* clear dst pixels */
 310                 uint32_t zero = 0;
 311                 si_clear_buffer(sctx, dst, 0, sdst->surface.surf_size, &zero, 4,
 312                                 SI_COHERENCY_SHADER, false);
 313                 memset(dst_cpu.ptr, 0, dst_cpu.layer_stride * tdst.array_size);
 314
 315                 /* preparation */
 316                 max_width = MIN2(tsrc.width0, tdst.width0);
 317                 max_height = MIN2(tsrc.height0, tdst.height0);
 318                 max_depth = MIN2(tsrc.array_size, tdst.array_size);
 319
 320                 num = do_partial_copies ? num_partial_copies : 1;
 321                 for (j = 0; j < num; j++) {
 322                         int width, height, depth;
 323                         int srcx, srcy, srcz, dstx, dsty, dstz;
 324                         struct pipe_box box;
 325                         unsigned old_num_draw_calls = sctx->num_draw_calls;
 326                         unsigned old_num_dma_calls = sctx->num_dma_calls;
 327                         unsigned old_num_cs_calls = sctx->num_compute_calls;
 328
 329                         if (!do_partial_copies) {
 330                                 /* copy whole src to dst */
 331                                 width = max_width;
 332                                 height = max_height;
 333                                 depth = max_depth;
 334
 335                                 srcx = srcy = srcz = dstx = dsty = dstz = 0;
 336                         } else {
 337                                 /* random sub-rectangle copies from src to dst */
 338                                 depth = (rand() % max_depth) + 1;
 339                                 srcz = rand() % (tsrc.array_size - depth + 1);
 340                                 dstz = rand() % (tdst.array_size - depth + 1);
 341
 342                                 /* special code path to hit the tiled partial copies */
 343                                 if (!ssrc->surface.is_linear &&
 344                                     !sdst->surface.is_linear &&
 345                                     rand() & 1) {
 346                                         if (max_width < 8 || max_height < 8)
 347                                                 continue;
 348                                         width = ((rand() % (max_width / 8)) + 1) * 8;
 349                                         height = ((rand() % (max_height / 8)) + 1) * 8;
 350
 351                                         srcx = rand() % (tsrc.width0 - width + 1) & ~0x7;
 352                                         srcy = rand() % (tsrc.height0 - height + 1) & ~0x7;
 353
 354                                         dstx = rand() % (tdst.width0 - width + 1) & ~0x7;
 355                                         dsty = rand() % (tdst.height0 - height + 1) & ~0x7;
 356                                 } else {
 357                                         /* just make sure that it doesn't divide by zero */
 358                                         assert(max_width > 0 && max_height > 0);
 359
 360                                         width = (rand() % max_width) + 1;
 361                                         height = (rand() % max_height) + 1;
 362
 363                                         srcx = rand() % (tsrc.width0 - width + 1);
 364                                         srcy = rand() % (tsrc.height0 - height + 1);
 365
 366                                         dstx = rand() % (tdst.width0 - width + 1);
 367                                         dsty = rand() % (tdst.height0 - height + 1);
 368                                 }
 369
 370                                 /* special code path to hit out-of-bounds reads in L2T */
 371                                 if (ssrc->surface.is_linear &&
 372                                     !sdst->surface.is_linear &&
 373                                     rand() % 4 == 0) {
 374                                         srcx = 0;
 375                                         srcy = 0;
 376                                         srcz = 0;
 377                                 }
 378                         }
 379
 380                         /* GPU copy */
 381                         u_box_3d(srcx, srcy, srcz, width, height, depth, &box);
 382                         sctx->dma_copy(ctx, dst, 0, dstx, dsty, dstz, src, 0, &box);
 383
 384                         /* See which engine was used. */
 385                         gfx_blits += sctx->num_draw_calls > old_num_draw_calls;
 386                         dma_blits += sctx->num_dma_calls > old_num_dma_calls;
 387                         cs_blits  += sctx->num_compute_calls > old_num_cs_calls;
 388
 389                         /* CPU copy */
 390                         util_copy_box(dst_cpu.ptr, tdst.format, dst_cpu.stride,
 391                                       dst_cpu.layer_stride,
 392                                       dstx, dsty, dstz, width, height, depth,
 393                                       src_cpu.ptr, src_cpu.stride,
 394                                       src_cpu.layer_stride,
 395                                       srcx, srcy, srcz);
 396                 }
 397
 398                 pass = compare_textures(ctx, dst, &dst_cpu);
 399                 if (pass)
 400                         num_pass++;
 401                 else
 402                         num_fail++;
 403
 404                 printf("BLITs: GFX = %2u, DMA = %2u, CS = %2u, %s [%u/%u]\n",
 405                        gfx_blits, dma_blits, cs_blits, pass ? "pass" : "fail",
 406                        num_pass, num_pass+num_fail);
 407
 408                 /* cleanup */
 409                 pipe_resource_reference(&src, NULL);
 410                 pipe_resource_reference(&dst, NULL);
 411                 free(src_cpu.ptr);
 412                 free(dst_cpu.ptr);
 413         }
 414
 415         ctx->destroy(ctx);
 416         exit(0);
 417 }