2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "drm-uapi/drm_fourcc.h"
30 #include "state_tracker/drm_driver.h"
31 #include "util/format/u_format.h"
32 #include "util/os_time.h"
33 #include "util/u_log.h"
34 #include "util/u_memory.h"
35 #include "util/u_pack_color.h"
36 #include "util/u_resource.h"
37 #include "util/u_surface.h"
38 #include "util/u_transfer.h"
43 #include "amd/addrlib/inc/addrinterface.h"
45 static enum radeon_surf_mode
si_choose_tiling(struct si_screen
*sscreen
,
46 const struct pipe_resource
*templ
,
47 bool tc_compatible_htile
);
49 bool si_prepare_for_dma_blit(struct si_context
*sctx
, struct si_texture
*dst
, unsigned dst_level
,
50 unsigned dstx
, unsigned dsty
, unsigned dstz
, struct si_texture
*src
,
51 unsigned src_level
, const struct pipe_box
*src_box
)
56 if (dst
->surface
.bpe
!= src
->surface
.bpe
)
59 /* MSAA: Blits don't exist in the real world. */
60 if (src
->buffer
.b
.b
.nr_samples
> 1 || dst
->buffer
.b
.b
.nr_samples
> 1)
63 /* Depth-stencil surfaces:
64 * When dst is linear, the DB->CB copy preserves HTILE.
65 * When dst is tiled, the 3D path must be used to update HTILE.
67 if (src
->is_depth
|| dst
->is_depth
)
71 * src: Use the 3D path. DCC decompression is expensive.
72 * dst: Use the 3D path to compress the pixels with DCC.
74 if (vi_dcc_enabled(src
, src_level
) || vi_dcc_enabled(dst
, dst_level
))
78 * src: Both texture and SDMA paths need decompression. Use SDMA.
79 * dst: If overwriting the whole texture, discard CMASK and use
80 * SDMA. Otherwise, use the 3D path.
82 if (dst
->cmask_buffer
&& dst
->dirty_level_mask
& (1 << dst_level
)) {
83 /* The CMASK clear is only enabled for the first level. */
84 assert(dst_level
== 0);
85 if (!util_texrange_covers_whole_level(&dst
->buffer
.b
.b
, dst_level
, dstx
, dsty
, dstz
,
86 src_box
->width
, src_box
->height
, src_box
->depth
))
89 si_texture_discard_cmask(sctx
->screen
, dst
);
92 /* All requirements are met. Prepare textures for SDMA. */
93 if (src
->cmask_buffer
&& src
->dirty_level_mask
& (1 << src_level
))
94 sctx
->b
.flush_resource(&sctx
->b
, &src
->buffer
.b
.b
);
96 assert(!(src
->dirty_level_mask
& (1 << src_level
)));
97 assert(!(dst
->dirty_level_mask
& (1 << dst_level
)));
102 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
103 static void si_copy_region_with_blit(struct pipe_context
*pipe
, struct pipe_resource
*dst
,
104 unsigned dst_level
, unsigned dstx
, unsigned dsty
,
105 unsigned dstz
, struct pipe_resource
*src
, unsigned src_level
,
106 const struct pipe_box
*src_box
)
108 struct pipe_blit_info blit
;
110 memset(&blit
, 0, sizeof(blit
));
111 blit
.src
.resource
= src
;
112 blit
.src
.format
= src
->format
;
113 blit
.src
.level
= src_level
;
114 blit
.src
.box
= *src_box
;
115 blit
.dst
.resource
= dst
;
116 blit
.dst
.format
= dst
->format
;
117 blit
.dst
.level
= dst_level
;
118 blit
.dst
.box
.x
= dstx
;
119 blit
.dst
.box
.y
= dsty
;
120 blit
.dst
.box
.z
= dstz
;
121 blit
.dst
.box
.width
= src_box
->width
;
122 blit
.dst
.box
.height
= src_box
->height
;
123 blit
.dst
.box
.depth
= src_box
->depth
;
124 blit
.mask
= util_format_get_mask(dst
->format
);
125 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
128 pipe
->blit(pipe
, &blit
);
132 /* Copy from a full GPU texture to a transfer's staging one. */
133 static void si_copy_to_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
135 struct si_context
*sctx
= (struct si_context
*)ctx
;
136 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
137 struct pipe_resource
*dst
= &stransfer
->staging
->b
.b
;
138 struct pipe_resource
*src
= transfer
->resource
;
140 if (src
->nr_samples
> 1 || ((struct si_texture
*)src
)->is_depth
) {
141 si_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
, &transfer
->box
);
145 sctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
, &transfer
->box
);
148 /* Copy from a transfer's staging texture to a full GPU one. */
149 static void si_copy_from_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
151 struct si_context
*sctx
= (struct si_context
*)ctx
;
152 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
153 struct pipe_resource
*dst
= transfer
->resource
;
154 struct pipe_resource
*src
= &stransfer
->staging
->b
.b
;
155 struct pipe_box sbox
;
157 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
159 if (dst
->nr_samples
> 1 || ((struct si_texture
*)dst
)->is_depth
) {
160 si_copy_region_with_blit(ctx
, dst
, transfer
->level
, transfer
->box
.x
, transfer
->box
.y
,
161 transfer
->box
.z
, src
, 0, &sbox
);
165 if (util_format_is_compressed(dst
->format
)) {
166 sbox
.width
= util_format_get_nblocksx(dst
->format
, sbox
.width
);
167 sbox
.height
= util_format_get_nblocksx(dst
->format
, sbox
.height
);
170 sctx
->dma_copy(ctx
, dst
, transfer
->level
, transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
, src
,
174 static unsigned si_texture_get_offset(struct si_screen
*sscreen
, struct si_texture
*tex
,
175 unsigned level
, const struct pipe_box
*box
, unsigned *stride
,
176 unsigned *layer_stride
)
178 if (sscreen
->info
.chip_class
>= GFX9
) {
179 *stride
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
180 *layer_stride
= tex
->surface
.u
.gfx9
.surf_slice_size
;
185 /* Each texture is an array of slices. Each slice is an array
186 * of mipmap levels. */
187 return tex
->surface
.u
.gfx9
.surf_offset
+ box
->z
* tex
->surface
.u
.gfx9
.surf_slice_size
+
188 tex
->surface
.u
.gfx9
.offset
[level
] +
189 (box
->y
/ tex
->surface
.blk_h
* tex
->surface
.u
.gfx9
.surf_pitch
+
190 box
->x
/ tex
->surface
.blk_w
) *
193 *stride
= tex
->surface
.u
.legacy
.level
[level
].nblk_x
* tex
->surface
.bpe
;
194 assert((uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
195 *layer_stride
= (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
198 return tex
->surface
.u
.legacy
.level
[level
].offset
;
200 /* Each texture is an array of mipmap levels. Each level is
201 * an array of slices. */
202 return tex
->surface
.u
.legacy
.level
[level
].offset
+
203 box
->z
* (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
204 (box
->y
/ tex
->surface
.blk_h
* tex
->surface
.u
.legacy
.level
[level
].nblk_x
+
205 box
->x
/ tex
->surface
.blk_w
) *
210 static int si_init_surface(struct si_screen
*sscreen
, struct radeon_surf
*surface
,
211 const struct pipe_resource
*ptex
, enum radeon_surf_mode array_mode
,
212 unsigned pitch_in_bytes_override
, bool is_imported
, bool is_scanout
,
213 bool is_flushed_depth
, bool tc_compatible_htile
)
215 const struct util_format_description
*desc
= util_format_description(ptex
->format
);
216 bool is_depth
, is_stencil
;
218 unsigned bpe
, flags
= 0;
220 is_depth
= util_format_has_depth(desc
);
221 is_stencil
= util_format_has_stencil(desc
);
223 if (!is_flushed_depth
&& ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
224 bpe
= 4; /* stencil is allocated separately */
226 bpe
= util_format_get_blocksize(ptex
->format
);
227 assert(util_is_power_of_two_or_zero(bpe
));
230 if (!is_flushed_depth
&& is_depth
) {
231 flags
|= RADEON_SURF_ZBUFFER
;
233 if (sscreen
->debug_flags
& DBG(NO_HYPERZ
)) {
234 flags
|= RADEON_SURF_NO_HTILE
;
235 } else if (tc_compatible_htile
&&
236 (sscreen
->info
.chip_class
>= GFX9
|| array_mode
== RADEON_SURF_MODE_2D
)) {
237 /* TC-compatible HTILE only supports Z32_FLOAT.
238 * GFX9 also supports Z16_UNORM.
239 * On GFX8, promote Z16 to Z32. DB->CB copies will convert
240 * the format for transfers.
242 if (sscreen
->info
.chip_class
== GFX8
)
247 flags
|= RADEON_SURF_SBUFFER
;
250 if (sscreen
->info
.chip_class
>= GFX8
&&
251 (ptex
->flags
& SI_RESOURCE_FLAG_DISABLE_DCC
|| ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
252 (ptex
->nr_samples
>= 2 && !sscreen
->dcc_msaa_allowed
)))
253 flags
|= RADEON_SURF_DISABLE_DCC
;
255 /* Stoney: 128bpp MSAA textures randomly fail piglit tests with DCC. */
256 if (sscreen
->info
.family
== CHIP_STONEY
&& bpe
== 16 && ptex
->nr_samples
>= 2)
257 flags
|= RADEON_SURF_DISABLE_DCC
;
259 /* GFX8: DCC clear for 4x and 8x MSAA array textures unimplemented. */
260 if (sscreen
->info
.chip_class
== GFX8
&& ptex
->nr_storage_samples
>= 4 && ptex
->array_size
> 1)
261 flags
|= RADEON_SURF_DISABLE_DCC
;
263 /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
264 if (sscreen
->info
.chip_class
== GFX9
&&
265 (ptex
->nr_storage_samples
>= 4 ||
266 (sscreen
->info
.family
== CHIP_RAVEN
&& ptex
->nr_storage_samples
>= 2 && bpe
< 4)))
267 flags
|= RADEON_SURF_DISABLE_DCC
;
269 /* TODO: GFX10: DCC causes corruption with MSAA. */
270 if (sscreen
->info
.chip_class
>= GFX10
&& ptex
->nr_storage_samples
>= 2)
271 flags
|= RADEON_SURF_DISABLE_DCC
;
273 /* Shared textures must always set up DCC.
274 * If it's not present, it will be disabled by
275 * si_get_opaque_metadata later.
277 if (!is_imported
&& (sscreen
->debug_flags
& DBG(NO_DCC
)))
278 flags
|= RADEON_SURF_DISABLE_DCC
;
281 /* This should catch bugs in gallium users setting incorrect flags. */
282 assert(ptex
->nr_samples
<= 1 && ptex
->array_size
== 1 && ptex
->depth0
== 1 &&
283 ptex
->last_level
== 0 && !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
285 flags
|= RADEON_SURF_SCANOUT
;
288 if (ptex
->bind
& PIPE_BIND_SHARED
)
289 flags
|= RADEON_SURF_SHAREABLE
;
291 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
292 if (sscreen
->debug_flags
& DBG(NO_FMASK
))
293 flags
|= RADEON_SURF_NO_FMASK
;
295 if (sscreen
->info
.chip_class
== GFX9
&& (ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE
)) {
296 flags
|= RADEON_SURF_FORCE_MICRO_TILE_MODE
;
297 surface
->micro_tile_mode
= SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(ptex
->flags
);
300 if (ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
) {
301 flags
|= RADEON_SURF_FORCE_SWIZZLE_MODE
;
303 if (sscreen
->info
.chip_class
>= GFX10
)
304 surface
->u
.gfx9
.surf
.swizzle_mode
= ADDR_SW_64KB_R_X
;
307 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, flags
, bpe
, array_mode
, surface
);
312 unsigned pitch
= pitch_in_bytes_override
/ bpe
;
314 if (sscreen
->info
.chip_class
>= GFX9
) {
316 surface
->u
.gfx9
.surf_pitch
= pitch
;
317 if (ptex
->last_level
== 0)
318 surface
->u
.gfx9
.surf
.epitch
= pitch
- 1;
319 surface
->u
.gfx9
.surf_slice_size
= (uint64_t)pitch
* surface
->u
.gfx9
.surf_height
* bpe
;
323 surface
->u
.legacy
.level
[0].nblk_x
= pitch
;
324 surface
->u
.legacy
.level
[0].slice_size_dw
=
325 ((uint64_t)pitch
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
331 static void si_get_display_metadata(struct si_screen
*sscreen
, struct radeon_surf
*surf
,
332 struct radeon_bo_metadata
*metadata
,
333 enum radeon_surf_mode
*array_mode
, bool *is_scanout
)
335 if (sscreen
->info
.chip_class
>= GFX9
) {
336 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
337 *array_mode
= RADEON_SURF_MODE_2D
;
339 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
341 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
342 surf
->u
.gfx9
.dcc
.independent_64B_blocks
= metadata
->u
.gfx9
.dcc_independent_64B
;
343 surf
->u
.gfx9
.dcc
.independent_128B_blocks
= metadata
->u
.gfx9
.dcc_independent_128B
;
344 surf
->u
.gfx9
.dcc
.max_compressed_block_size
= metadata
->u
.gfx9
.dcc_max_compressed_block_size
;
345 surf
->u
.gfx9
.display_dcc_pitch_max
= metadata
->u
.gfx9
.dcc_pitch_max
;
346 *is_scanout
= metadata
->u
.gfx9
.scanout
;
348 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
349 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
350 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
351 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
352 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
353 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
355 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
356 *array_mode
= RADEON_SURF_MODE_2D
;
357 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
358 *array_mode
= RADEON_SURF_MODE_1D
;
360 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
362 *is_scanout
= metadata
->u
.legacy
.scanout
;
366 void si_eliminate_fast_color_clear(struct si_context
*sctx
, struct si_texture
*tex
)
368 struct si_screen
*sscreen
= sctx
->screen
;
369 struct pipe_context
*ctx
= &sctx
->b
;
371 if (ctx
== sscreen
->aux_context
)
372 simple_mtx_lock(&sscreen
->aux_context_lock
);
374 unsigned n
= sctx
->num_decompress_calls
;
375 ctx
->flush_resource(ctx
, &tex
->buffer
.b
.b
);
377 /* Flush only if any fast clear elimination took place. */
378 if (n
!= sctx
->num_decompress_calls
)
379 ctx
->flush(ctx
, NULL
, 0);
381 if (ctx
== sscreen
->aux_context
)
382 simple_mtx_unlock(&sscreen
->aux_context_lock
);
385 void si_texture_discard_cmask(struct si_screen
*sscreen
, struct si_texture
*tex
)
387 if (!tex
->cmask_buffer
)
390 assert(tex
->buffer
.b
.b
.nr_samples
<= 1);
393 tex
->cmask_base_address_reg
= tex
->buffer
.gpu_address
>> 8;
394 tex
->dirty_level_mask
= 0;
396 tex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
398 if (tex
->cmask_buffer
!= &tex
->buffer
)
399 si_resource_reference(&tex
->cmask_buffer
, NULL
);
401 tex
->cmask_buffer
= NULL
;
403 /* Notify all contexts about the change. */
404 p_atomic_inc(&sscreen
->dirty_tex_counter
);
405 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
408 static bool si_can_disable_dcc(struct si_texture
*tex
)
410 /* We can't disable DCC if it can be written by another process. */
411 return tex
->surface
.dcc_offset
&&
412 (!tex
->buffer
.b
.is_shared
||
413 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
));
416 static void si_texture_zero_dcc_fields(struct si_texture
*tex
)
418 tex
->surface
.dcc_offset
= 0;
419 tex
->surface
.display_dcc_offset
= 0;
420 tex
->surface
.dcc_retile_map_offset
= 0;
423 static bool si_texture_discard_dcc(struct si_screen
*sscreen
, struct si_texture
*tex
)
425 if (!si_can_disable_dcc(tex
))
428 assert(tex
->dcc_separate_buffer
== NULL
);
431 si_texture_zero_dcc_fields(tex
);
433 /* Notify all contexts about the change. */
434 p_atomic_inc(&sscreen
->dirty_tex_counter
);
439 * Disable DCC for the texture. (first decompress, then discard metadata).
441 * There is unresolved multi-context synchronization issue between
442 * screen::aux_context and the current context. If applications do this with
443 * multiple contexts, it's already undefined behavior for them and we don't
444 * have to worry about that. The scenario is:
446 * If context 1 disables DCC and context 2 has queued commands that write
447 * to the texture via CB with DCC enabled, and the order of operations is
449 * context 2 queues draw calls rendering to the texture, but doesn't flush
450 * context 1 disables DCC and flushes
451 * context 1 & 2 reset descriptors and FB state
452 * context 2 flushes (new compressed tiles written by the draw calls)
453 * context 1 & 2 read garbage, because DCC is disabled, yet there are
456 * \param sctx the current context if you have one, or sscreen->aux_context
459 bool si_texture_disable_dcc(struct si_context
*sctx
, struct si_texture
*tex
)
461 struct si_screen
*sscreen
= sctx
->screen
;
463 if (!sctx
->has_graphics
)
464 return si_texture_discard_dcc(sscreen
, tex
);
466 if (!si_can_disable_dcc(tex
))
469 if (&sctx
->b
== sscreen
->aux_context
)
470 simple_mtx_lock(&sscreen
->aux_context_lock
);
472 /* Decompress DCC. */
473 si_decompress_dcc(sctx
, tex
);
474 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
476 if (&sctx
->b
== sscreen
->aux_context
)
477 simple_mtx_unlock(&sscreen
->aux_context_lock
);
479 return si_texture_discard_dcc(sscreen
, tex
);
482 static void si_reallocate_texture_inplace(struct si_context
*sctx
, struct si_texture
*tex
,
483 unsigned new_bind_flag
, bool invalidate_storage
)
485 struct pipe_screen
*screen
= sctx
->b
.screen
;
486 struct si_texture
*new_tex
;
487 struct pipe_resource templ
= tex
->buffer
.b
.b
;
490 templ
.bind
|= new_bind_flag
;
492 if (tex
->buffer
.b
.is_shared
|| tex
->num_planes
> 1)
495 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
496 if (tex
->surface
.is_linear
)
499 /* This fails with MSAA, depth, and compressed textures. */
500 if (si_choose_tiling(sctx
->screen
, &templ
, false) != RADEON_SURF_MODE_LINEAR_ALIGNED
)
504 new_tex
= (struct si_texture
*)screen
->resource_create(screen
, &templ
);
508 /* Copy the pixels to the new texture. */
509 if (!invalidate_storage
) {
510 for (i
= 0; i
<= templ
.last_level
; i
++) {
513 u_box_3d(0, 0, 0, u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
514 util_num_layers(&templ
, i
), &box
);
516 sctx
->dma_copy(&sctx
->b
, &new_tex
->buffer
.b
.b
, i
, 0, 0, 0, &tex
->buffer
.b
.b
, i
, &box
);
520 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
521 si_texture_discard_cmask(sctx
->screen
, tex
);
522 si_texture_discard_dcc(sctx
->screen
, tex
);
525 /* Replace the structure fields of tex. */
526 tex
->buffer
.b
.b
.bind
= templ
.bind
;
527 pb_reference(&tex
->buffer
.buf
, new_tex
->buffer
.buf
);
528 tex
->buffer
.gpu_address
= new_tex
->buffer
.gpu_address
;
529 tex
->buffer
.vram_usage
= new_tex
->buffer
.vram_usage
;
530 tex
->buffer
.gart_usage
= new_tex
->buffer
.gart_usage
;
531 tex
->buffer
.bo_size
= new_tex
->buffer
.bo_size
;
532 tex
->buffer
.bo_alignment
= new_tex
->buffer
.bo_alignment
;
533 tex
->buffer
.domains
= new_tex
->buffer
.domains
;
534 tex
->buffer
.flags
= new_tex
->buffer
.flags
;
536 tex
->surface
= new_tex
->surface
;
537 si_texture_reference(&tex
->flushed_depth_texture
, new_tex
->flushed_depth_texture
);
539 tex
->surface
.fmask_offset
= new_tex
->surface
.fmask_offset
;
540 tex
->surface
.cmask_offset
= new_tex
->surface
.cmask_offset
;
541 tex
->cmask_base_address_reg
= new_tex
->cmask_base_address_reg
;
543 if (tex
->cmask_buffer
== &tex
->buffer
)
544 tex
->cmask_buffer
= NULL
;
546 si_resource_reference(&tex
->cmask_buffer
, NULL
);
548 if (new_tex
->cmask_buffer
== &new_tex
->buffer
)
549 tex
->cmask_buffer
= &tex
->buffer
;
551 si_resource_reference(&tex
->cmask_buffer
, new_tex
->cmask_buffer
);
553 tex
->surface
.dcc_offset
= new_tex
->surface
.dcc_offset
;
554 tex
->cb_color_info
= new_tex
->cb_color_info
;
555 memcpy(tex
->color_clear_value
, new_tex
->color_clear_value
, sizeof(tex
->color_clear_value
));
556 tex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
558 tex
->surface
.htile_offset
= new_tex
->surface
.htile_offset
;
559 tex
->depth_clear_value
= new_tex
->depth_clear_value
;
560 tex
->dirty_level_mask
= new_tex
->dirty_level_mask
;
561 tex
->stencil_dirty_level_mask
= new_tex
->stencil_dirty_level_mask
;
562 tex
->db_render_format
= new_tex
->db_render_format
;
563 tex
->stencil_clear_value
= new_tex
->stencil_clear_value
;
564 tex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
565 tex
->depth_cleared
= new_tex
->depth_cleared
;
566 tex
->stencil_cleared
= new_tex
->stencil_cleared
;
567 tex
->upgraded_depth
= new_tex
->upgraded_depth
;
568 tex
->db_compatible
= new_tex
->db_compatible
;
569 tex
->can_sample_z
= new_tex
->can_sample_z
;
570 tex
->can_sample_s
= new_tex
->can_sample_s
;
572 tex
->separate_dcc_dirty
= new_tex
->separate_dcc_dirty
;
573 tex
->displayable_dcc_dirty
= new_tex
->displayable_dcc_dirty
;
574 tex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
575 si_resource_reference(&tex
->dcc_separate_buffer
, new_tex
->dcc_separate_buffer
);
576 si_resource_reference(&tex
->last_dcc_separate_buffer
, new_tex
->last_dcc_separate_buffer
);
578 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
579 assert(!tex
->surface
.htile_offset
);
580 assert(!tex
->cmask_buffer
);
581 assert(!tex
->surface
.fmask_size
);
582 assert(!tex
->surface
.dcc_offset
);
583 assert(!tex
->is_depth
);
586 si_texture_reference(&new_tex
, NULL
);
588 p_atomic_inc(&sctx
->screen
->dirty_tex_counter
);
591 static uint32_t si_get_bo_metadata_word1(struct si_screen
*sscreen
)
593 return (ATI_VENDOR_ID
<< 16) | sscreen
->info
.pci_id
;
596 static void si_set_tex_bo_metadata(struct si_screen
*sscreen
, struct si_texture
*tex
)
598 struct radeon_surf
*surface
= &tex
->surface
;
599 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
600 struct radeon_bo_metadata md
;
602 memset(&md
, 0, sizeof(md
));
604 if (sscreen
->info
.chip_class
>= GFX9
) {
605 md
.u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
606 md
.u
.gfx9
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
608 if (tex
->surface
.dcc_offset
&& !tex
->dcc_separate_buffer
) {
609 uint64_t dcc_offset
= tex
->surface
.display_dcc_offset
? tex
->surface
.display_dcc_offset
610 : tex
->surface
.dcc_offset
;
612 assert((dcc_offset
>> 8) != 0 && (dcc_offset
>> 8) < (1 << 24));
613 md
.u
.gfx9
.dcc_offset_256B
= dcc_offset
>> 8;
614 md
.u
.gfx9
.dcc_pitch_max
= tex
->surface
.u
.gfx9
.display_dcc_pitch_max
;
615 md
.u
.gfx9
.dcc_independent_64B
= tex
->surface
.u
.gfx9
.dcc
.independent_64B_blocks
;
616 md
.u
.gfx9
.dcc_independent_128B
= tex
->surface
.u
.gfx9
.dcc
.independent_128B_blocks
;
617 md
.u
.gfx9
.dcc_max_compressed_block_size
= tex
->surface
.u
.gfx9
.dcc
.max_compressed_block_size
;
620 md
.u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
621 ? RADEON_LAYOUT_TILED
622 : RADEON_LAYOUT_LINEAR
;
623 md
.u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
624 ? RADEON_LAYOUT_TILED
625 : RADEON_LAYOUT_LINEAR
;
626 md
.u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
627 md
.u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
628 md
.u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
629 md
.u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
630 md
.u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
631 md
.u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
632 md
.u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
633 md
.u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
636 assert(tex
->dcc_separate_buffer
== NULL
);
637 assert(tex
->surface
.fmask_size
== 0);
639 /* Metadata image format format version 1:
640 * [0] = 1 (metadata format identifier)
641 * [1] = (VENDOR_ID << 16) | PCI_ID
642 * [2:9] = image descriptor for the whole resource
643 * [2] is always 0, because the base address is cleared
644 * [9] is the DCC offset bits [39:8] from the beginning of
646 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
649 md
.metadata
[0] = 1; /* metadata image format version 1 */
651 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
652 md
.metadata
[1] = si_get_bo_metadata_word1(sscreen
);
654 static const unsigned char swizzle
[] = {PIPE_SWIZZLE_X
, PIPE_SWIZZLE_Y
, PIPE_SWIZZLE_Z
,
656 bool is_array
= util_texture_is_array(res
->target
);
659 sscreen
->make_texture_descriptor(sscreen
, tex
, true, res
->target
, res
->format
, swizzle
, 0,
660 res
->last_level
, 0, is_array
? res
->array_size
- 1 : 0,
661 res
->width0
, res
->height0
, res
->depth0
, desc
, NULL
);
663 si_set_mutable_tex_desc_fields(sscreen
, tex
, &tex
->surface
.u
.legacy
.level
[0], 0, 0,
664 tex
->surface
.blk_w
, false, desc
);
666 /* Clear the base address and set the relative DCC offset. */
668 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
670 switch (sscreen
->info
.chip_class
) {
675 desc
[7] = tex
->surface
.dcc_offset
>> 8;
678 desc
[7] = tex
->surface
.dcc_offset
>> 8;
679 desc
[5] &= C_008F24_META_DATA_ADDRESS
;
680 desc
[5] |= S_008F24_META_DATA_ADDRESS(tex
->surface
.dcc_offset
>> 40);
683 desc
[6] &= C_00A018_META_DATA_ADDRESS_LO
;
684 desc
[6] |= S_00A018_META_DATA_ADDRESS_LO(tex
->surface
.dcc_offset
>> 8);
685 desc
[7] = tex
->surface
.dcc_offset
>> 16;
691 /* Dwords [2:9] contain the image descriptor. */
692 memcpy(&md
.metadata
[2], desc
, sizeof(desc
));
693 md
.size_metadata
= 10 * 4;
695 /* Dwords [10:..] contain the mipmap level offsets. */
696 if (sscreen
->info
.chip_class
<= GFX8
) {
697 for (unsigned i
= 0; i
<= res
->last_level
; i
++)
698 md
.metadata
[10 + i
] = tex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
700 md
.size_metadata
+= (1 + res
->last_level
) * 4;
703 sscreen
->ws
->buffer_set_metadata(tex
->buffer
.buf
, &md
);
706 static bool si_read_tex_bo_metadata(struct si_screen
*sscreen
, struct si_texture
*tex
,
707 uint64_t offset
, struct radeon_bo_metadata
*md
)
709 uint32_t *desc
= &md
->metadata
[2];
711 if (offset
|| /* Non-zero planes ignore metadata. */
712 md
->size_metadata
< 10 * 4 || /* at least 2(header) + 8(desc) dwords */
713 md
->metadata
[0] == 0 || /* invalid version number */
714 md
->metadata
[1] != si_get_bo_metadata_word1(sscreen
)) /* invalid PCI ID */ {
715 /* Disable DCC because it might not be enabled. */
716 si_texture_zero_dcc_fields(tex
);
718 /* Don't report an error if the texture comes from an incompatible driver,
719 * but this might not work.
724 /* Validate that sample counts and the number of mipmap levels match. */
725 unsigned last_level
= G_008F1C_LAST_LEVEL(desc
[3]);
726 unsigned type
= G_008F1C_TYPE(desc
[3]);
728 if (type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA
|| type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
729 unsigned log_samples
= util_logbase2(MAX2(1, tex
->buffer
.b
.b
.nr_storage_samples
));
731 if (last_level
!= log_samples
) {
733 "radeonsi: invalid MSAA texture import, "
734 "metadata has log2(samples) = %u, the caller set %u\n",
735 last_level
, log_samples
);
739 if (last_level
!= tex
->buffer
.b
.b
.last_level
) {
741 "radeonsi: invalid mipmapped texture import, "
742 "metadata has last_level = %u, the caller set %u\n",
743 last_level
, tex
->buffer
.b
.b
.last_level
);
748 if (sscreen
->info
.chip_class
>= GFX8
&& G_008F28_COMPRESSION_EN(desc
[6])) {
749 /* Read DCC information. */
750 switch (sscreen
->info
.chip_class
) {
752 tex
->surface
.dcc_offset
= (uint64_t)desc
[7] << 8;
756 tex
->surface
.dcc_offset
=
757 ((uint64_t)desc
[7] << 8) | ((uint64_t)G_008F24_META_DATA_ADDRESS(desc
[5]) << 40);
758 tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
= G_008F24_META_PIPE_ALIGNED(desc
[5]);
759 tex
->surface
.u
.gfx9
.dcc
.rb_aligned
= G_008F24_META_RB_ALIGNED(desc
[5]);
761 /* If DCC is unaligned, this can only be a displayable image. */
762 if (!tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
&& !tex
->surface
.u
.gfx9
.dcc
.rb_aligned
)
763 assert(tex
->surface
.is_displayable
);
767 tex
->surface
.dcc_offset
=
768 ((uint64_t)G_00A018_META_DATA_ADDRESS_LO(desc
[6]) << 8) | ((uint64_t)desc
[7] << 16);
769 tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
= G_00A018_META_PIPE_ALIGNED(desc
[6]);
777 /* Disable DCC. dcc_offset is always set by texture_from_handle
778 * and must be cleared here.
780 si_texture_zero_dcc_fields(tex
);
786 static bool si_has_displayable_dcc(struct si_texture
*tex
)
788 struct si_screen
*sscreen
= (struct si_screen
*)tex
->buffer
.b
.b
.screen
;
790 if (sscreen
->info
.chip_class
<= GFX8
)
793 return tex
->surface
.is_displayable
&& tex
->surface
.dcc_offset
;
796 static bool si_resource_get_param(struct pipe_screen
*screen
, struct pipe_context
*context
,
797 struct pipe_resource
*resource
, unsigned plane
, unsigned layer
,
798 enum pipe_resource_param param
, unsigned handle_usage
,
801 for (unsigned i
= 0; i
< plane
; i
++)
802 resource
= resource
->next
;
804 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
805 struct si_texture
*tex
= (struct si_texture
*)resource
;
806 struct winsys_handle whandle
;
809 case PIPE_RESOURCE_PARAM_NPLANES
:
810 *value
= resource
->target
== PIPE_BUFFER
? 1 : tex
->num_planes
;
813 case PIPE_RESOURCE_PARAM_STRIDE
:
814 if (resource
->target
== PIPE_BUFFER
)
816 else if (sscreen
->info
.chip_class
>= GFX9
)
817 *value
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
819 *value
= tex
->surface
.u
.legacy
.level
[0].nblk_x
* tex
->surface
.bpe
;
822 case PIPE_RESOURCE_PARAM_OFFSET
:
823 if (resource
->target
== PIPE_BUFFER
)
825 else if (sscreen
->info
.chip_class
>= GFX9
)
826 *value
= tex
->surface
.u
.gfx9
.surf_offset
+ layer
* tex
->surface
.u
.gfx9
.surf_slice_size
;
828 *value
= tex
->surface
.u
.legacy
.level
[0].offset
+
829 layer
* (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
832 case PIPE_RESOURCE_PARAM_MODIFIER
:
833 *value
= DRM_FORMAT_MOD_INVALID
;
836 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
:
837 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
:
838 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
:
839 memset(&whandle
, 0, sizeof(whandle
));
841 if (param
== PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
)
842 whandle
.type
= WINSYS_HANDLE_TYPE_SHARED
;
843 else if (param
== PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
)
844 whandle
.type
= WINSYS_HANDLE_TYPE_KMS
;
845 else if (param
== PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
)
846 whandle
.type
= WINSYS_HANDLE_TYPE_FD
;
848 if (!screen
->resource_get_handle(screen
, context
, resource
, &whandle
, handle_usage
))
851 *value
= whandle
.handle
;
857 static void si_texture_get_info(struct pipe_screen
*screen
, struct pipe_resource
*resource
,
858 unsigned *pstride
, unsigned *poffset
)
863 si_resource_get_param(screen
, NULL
, resource
, 0, 0, PIPE_RESOURCE_PARAM_STRIDE
, 0, &value
);
868 si_resource_get_param(screen
, NULL
, resource
, 0, 0, PIPE_RESOURCE_PARAM_OFFSET
, 0, &value
);
873 static bool si_texture_get_handle(struct pipe_screen
*screen
, struct pipe_context
*ctx
,
874 struct pipe_resource
*resource
, struct winsys_handle
*whandle
,
877 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
878 struct si_context
*sctx
;
879 struct si_resource
*res
= si_resource(resource
);
880 struct si_texture
*tex
= (struct si_texture
*)resource
;
881 bool update_metadata
= false;
882 unsigned stride
, offset
, slice_size
;
885 ctx
= threaded_context_unwrap_sync(ctx
);
886 sctx
= (struct si_context
*)(ctx
? ctx
: sscreen
->aux_context
);
888 if (resource
->target
!= PIPE_BUFFER
) {
889 /* Individual planes are chained pipe_resource instances. */
890 for (unsigned i
= 0; i
< whandle
->plane
; i
++) {
891 resource
= resource
->next
;
892 res
= si_resource(resource
);
893 tex
= (struct si_texture
*)resource
;
896 /* This is not supported now, but it might be required for OpenCL
897 * interop in the future.
899 if (resource
->nr_samples
> 1 || tex
->is_depth
)
902 /* Move a suballocated texture into a non-suballocated allocation. */
903 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) || tex
->surface
.tile_swizzle
||
904 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
905 sscreen
->info
.has_local_buffers
)) {
906 assert(!res
->b
.is_shared
);
907 si_reallocate_texture_inplace(sctx
, tex
, PIPE_BIND_SHARED
, false);
909 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
910 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
911 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
912 assert(tex
->surface
.tile_swizzle
== 0);
915 /* Since shader image stores don't support DCC on GFX8,
916 * disable it for external clients that want write
919 if ((usage
& PIPE_HANDLE_USAGE_SHADER_WRITE
&& tex
->surface
.dcc_offset
) ||
920 /* Displayable DCC requires an explicit flush. */
921 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && si_has_displayable_dcc(tex
))) {
922 if (si_texture_disable_dcc(sctx
, tex
)) {
923 update_metadata
= true;
924 /* si_texture_disable_dcc flushes the context */
929 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
930 (tex
->cmask_buffer
|| tex
->surface
.dcc_offset
)) {
931 /* Eliminate fast clear (both CMASK and DCC) */
932 si_eliminate_fast_color_clear(sctx
, tex
);
933 /* eliminate_fast_color_clear flushes the context */
936 /* Disable CMASK if flush_resource isn't going
939 if (tex
->cmask_buffer
)
940 si_texture_discard_cmask(sscreen
, tex
);
944 if ((!res
->b
.is_shared
|| update_metadata
) && whandle
->offset
== 0)
945 si_set_tex_bo_metadata(sscreen
, tex
);
947 if (sscreen
->info
.chip_class
>= GFX9
) {
948 slice_size
= tex
->surface
.u
.gfx9
.surf_slice_size
;
950 slice_size
= (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
953 /* Buffer exports are for the OpenCL interop. */
954 /* Move a suballocated buffer into a non-suballocated allocation. */
955 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
956 /* A DMABUF export always fails if the BO is local. */
957 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
958 sscreen
->info
.has_local_buffers
)) {
959 assert(!res
->b
.is_shared
);
961 /* Allocate a new buffer with PIPE_BIND_SHARED. */
962 struct pipe_resource templ
= res
->b
.b
;
963 templ
.bind
|= PIPE_BIND_SHARED
;
965 struct pipe_resource
*newb
= screen
->resource_create(screen
, &templ
);
969 /* Copy the old buffer contents to the new one. */
971 u_box_1d(0, newb
->width0
, &box
);
972 sctx
->b
.resource_copy_region(&sctx
->b
, newb
, 0, 0, 0, 0, &res
->b
.b
, 0, &box
);
974 /* Move the new buffer storage to the old pipe_resource. */
975 si_replace_buffer_storage(&sctx
->b
, &res
->b
.b
, newb
);
976 pipe_resource_reference(&newb
, NULL
);
978 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
979 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
986 si_texture_get_info(screen
, resource
, &stride
, &offset
);
989 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
991 if (res
->b
.is_shared
) {
992 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
995 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
996 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
997 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
999 res
->b
.is_shared
= true;
1000 res
->external_usage
= usage
;
1003 whandle
->stride
= stride
;
1004 whandle
->offset
= offset
+ slice_size
* whandle
->layer
;
1006 return sscreen
->ws
->buffer_get_handle(sscreen
->ws
, res
->buf
, whandle
);
1009 static void si_texture_destroy(struct pipe_screen
*screen
, struct pipe_resource
*ptex
)
1011 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1012 struct si_texture
*tex
= (struct si_texture
*)ptex
;
1013 struct si_resource
*resource
= &tex
->buffer
;
1015 if (sscreen
->info
.chip_class
>= GFX9
)
1016 free(tex
->surface
.u
.gfx9
.dcc_retile_map
);
1018 si_texture_reference(&tex
->flushed_depth_texture
, NULL
);
1020 if (tex
->cmask_buffer
!= &tex
->buffer
) {
1021 si_resource_reference(&tex
->cmask_buffer
, NULL
);
1023 pb_reference(&resource
->buf
, NULL
);
1024 si_resource_reference(&tex
->dcc_separate_buffer
, NULL
);
1025 si_resource_reference(&tex
->last_dcc_separate_buffer
, NULL
);
1029 static const struct u_resource_vtbl si_texture_vtbl
;
1031 void si_print_texture_info(struct si_screen
*sscreen
, struct si_texture
*tex
,
1032 struct u_log_context
*log
)
1036 /* Common parameters. */
1038 " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
1039 "blk_h=%u, array_size=%u, last_level=%u, "
1040 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
1041 tex
->buffer
.b
.b
.width0
, tex
->buffer
.b
.b
.height0
, tex
->buffer
.b
.b
.depth0
,
1042 tex
->surface
.blk_w
, tex
->surface
.blk_h
, tex
->buffer
.b
.b
.array_size
,
1043 tex
->buffer
.b
.b
.last_level
, tex
->surface
.bpe
, tex
->buffer
.b
.b
.nr_samples
,
1044 tex
->surface
.flags
, util_format_short_name(tex
->buffer
.b
.b
.format
));
1046 if (sscreen
->info
.chip_class
>= GFX9
) {
1048 " Surf: size=%" PRIu64
", slice_size=%" PRIu64
", "
1049 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
1050 tex
->surface
.surf_size
, tex
->surface
.u
.gfx9
.surf_slice_size
,
1051 tex
->surface
.surf_alignment
, tex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
1052 tex
->surface
.u
.gfx9
.surf
.epitch
, tex
->surface
.u
.gfx9
.surf_pitch
);
1054 if (tex
->surface
.fmask_offset
) {
1056 " FMASK: offset=%" PRIu64
", size=%" PRIu64
", "
1057 "alignment=%u, swmode=%u, epitch=%u\n",
1058 tex
->surface
.fmask_offset
, tex
->surface
.fmask_size
,
1059 tex
->surface
.fmask_alignment
, tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1060 tex
->surface
.u
.gfx9
.fmask
.epitch
);
1063 if (tex
->cmask_buffer
) {
1065 " CMask: offset=%" PRIu64
", size=%u, "
1066 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1067 tex
->surface
.cmask_offset
, tex
->surface
.cmask_size
,
1068 tex
->surface
.cmask_alignment
, tex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1069 tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1072 if (tex
->surface
.htile_offset
) {
1074 " HTile: offset=%" PRIu64
", size=%u, alignment=%u, "
1075 "rb_aligned=%u, pipe_aligned=%u\n",
1076 tex
->surface
.htile_offset
, tex
->surface
.htile_size
,
1077 tex
->surface
.htile_alignment
, tex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1078 tex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1081 if (tex
->surface
.dcc_offset
) {
1083 " DCC: offset=%" PRIu64
", size=%u, "
1084 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1085 tex
->surface
.dcc_offset
, tex
->surface
.dcc_size
, tex
->surface
.dcc_alignment
,
1086 tex
->surface
.u
.gfx9
.display_dcc_pitch_max
, tex
->surface
.num_dcc_levels
);
1089 if (tex
->surface
.u
.gfx9
.stencil_offset
) {
1090 u_log_printf(log
, " Stencil: offset=%" PRIu64
", swmode=%u, epitch=%u\n",
1091 tex
->surface
.u
.gfx9
.stencil_offset
, tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1092 tex
->surface
.u
.gfx9
.stencil
.epitch
);
1098 " Layout: size=%" PRIu64
", alignment=%u, bankw=%u, "
1099 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1100 tex
->surface
.surf_size
, tex
->surface
.surf_alignment
, tex
->surface
.u
.legacy
.bankw
,
1101 tex
->surface
.u
.legacy
.bankh
, tex
->surface
.u
.legacy
.num_banks
,
1102 tex
->surface
.u
.legacy
.mtilea
, tex
->surface
.u
.legacy
.tile_split
,
1103 tex
->surface
.u
.legacy
.pipe_config
, (tex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1105 if (tex
->surface
.fmask_offset
)
1108 " FMask: offset=%" PRIu64
", size=%" PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1109 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1110 tex
->surface
.fmask_offset
, tex
->surface
.fmask_size
, tex
->surface
.fmask_alignment
,
1111 tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
, tex
->surface
.u
.legacy
.fmask
.bankh
,
1112 tex
->surface
.u
.legacy
.fmask
.slice_tile_max
, tex
->surface
.u
.legacy
.fmask
.tiling_index
);
1114 if (tex
->cmask_buffer
)
1116 " CMask: offset=%" PRIu64
", size=%u, alignment=%u, "
1117 "slice_tile_max=%u\n",
1118 tex
->surface
.cmask_offset
, tex
->surface
.cmask_size
, tex
->surface
.cmask_alignment
,
1119 tex
->surface
.u
.legacy
.cmask_slice_tile_max
);
1121 if (tex
->surface
.htile_offset
)
1123 " HTile: offset=%" PRIu64
", size=%u, "
1124 "alignment=%u, TC_compatible = %u\n",
1125 tex
->surface
.htile_offset
, tex
->surface
.htile_size
, tex
->surface
.htile_alignment
,
1126 tex
->tc_compatible_htile
);
1128 if (tex
->surface
.dcc_offset
) {
1129 u_log_printf(log
, " DCC: offset=%" PRIu64
", size=%u, alignment=%u\n",
1130 tex
->surface
.dcc_offset
, tex
->surface
.dcc_size
, tex
->surface
.dcc_alignment
);
1131 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1133 " DCCLevel[%i]: enabled=%u, offset=%u, "
1134 "fast_clear_size=%u\n",
1135 i
, i
< tex
->surface
.num_dcc_levels
, tex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1136 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1139 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1141 " Level[%i]: offset=%" PRIu64
", slice_size=%" PRIu64
", "
1142 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1143 "mode=%u, tiling_index = %u\n",
1144 i
, tex
->surface
.u
.legacy
.level
[i
].offset
,
1145 (uint64_t)tex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
1146 u_minify(tex
->buffer
.b
.b
.width0
, i
), u_minify(tex
->buffer
.b
.b
.height0
, i
),
1147 u_minify(tex
->buffer
.b
.b
.depth0
, i
), tex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1148 tex
->surface
.u
.legacy
.level
[i
].nblk_y
, tex
->surface
.u
.legacy
.level
[i
].mode
,
1149 tex
->surface
.u
.legacy
.tiling_index
[i
]);
1151 if (tex
->surface
.has_stencil
) {
1152 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1153 tex
->surface
.u
.legacy
.stencil_tile_split
);
1154 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++) {
1156 " StencilLevel[%i]: offset=%" PRIu64
", "
1157 "slice_size=%" PRIu64
", npix_x=%u, "
1158 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1159 "mode=%u, tiling_index = %u\n",
1160 i
, tex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1161 (uint64_t)tex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
1162 u_minify(tex
->buffer
.b
.b
.width0
, i
), u_minify(tex
->buffer
.b
.b
.height0
, i
),
1163 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1164 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1165 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1166 tex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1167 tex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1173 * Common function for si_texture_create and si_texture_from_handle.
1175 * \param screen screen
1176 * \param base resource template
1177 * \param surface radeon_surf
1178 * \param plane0 if a non-zero plane is being created, this is the first plane
1179 * \param imported_buf from si_texture_from_handle
1180 * \param offset offset for non-zero planes or imported buffers
1181 * \param alloc_size the size to allocate if plane0 != NULL
1182 * \param alignment alignment for the allocation
1184 static struct si_texture
*si_texture_create_object(struct pipe_screen
*screen
,
1185 const struct pipe_resource
*base
,
1186 const struct radeon_surf
*surface
,
1187 const struct si_texture
*plane0
,
1188 struct pb_buffer
*imported_buf
, uint64_t offset
,
1189 uint64_t alloc_size
, unsigned alignment
,
1190 bool tc_compatible_htile
)
1192 struct si_texture
*tex
;
1193 struct si_resource
*resource
;
1194 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1196 tex
= CALLOC_STRUCT(si_texture
);
1200 resource
= &tex
->buffer
;
1201 resource
->b
.b
= *base
;
1202 resource
->b
.vtbl
= &si_texture_vtbl
;
1203 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1204 resource
->b
.b
.screen
= screen
;
1206 /* don't include stencil-only formats which we don't support for rendering */
1207 tex
->is_depth
= util_format_has_depth(util_format_description(tex
->buffer
.b
.b
.format
));
1208 tex
->surface
= *surface
;
1209 tex
->tc_compatible_htile
= tex
->surface
.tc_compatible_htile_allowed
&&
1210 tc_compatible_htile
;
1212 /* TC-compatible HTILE:
1213 * - GFX8 only supports Z32_FLOAT.
1214 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1215 if (tex
->tc_compatible_htile
) {
1216 if (sscreen
->info
.chip_class
>= GFX9
&& base
->format
== PIPE_FORMAT_Z16_UNORM
)
1217 tex
->db_render_format
= base
->format
;
1219 tex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1220 tex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1221 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1224 tex
->db_render_format
= base
->format
;
1227 /* Applies to GCN. */
1228 tex
->last_msaa_resolve_target_micro_mode
= tex
->surface
.micro_tile_mode
;
1230 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1231 * between frames, so the only thing that can enable separate DCC
1232 * with DRI2 is multiple slow clears within a frame.
1234 tex
->ps_draw_ratio
= 0;
1236 if (sscreen
->info
.chip_class
>= GFX9
) {
1237 tex
->surface
.u
.gfx9
.surf_offset
= offset
;
1239 for (unsigned i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
1240 tex
->surface
.u
.legacy
.level
[i
].offset
+= offset
;
1243 if (tex
->is_depth
) {
1244 if (sscreen
->info
.chip_class
>= GFX9
) {
1245 tex
->can_sample_z
= true;
1246 tex
->can_sample_s
= true;
1248 /* Stencil texturing with HTILE doesn't work
1249 * with mipmapping on Navi10-14. */
1250 if (sscreen
->info
.chip_class
== GFX10
&& base
->last_level
> 0)
1251 tex
->htile_stencil_disabled
= true;
1253 tex
->can_sample_z
= !tex
->surface
.u
.legacy
.depth_adjusted
;
1254 tex
->can_sample_s
= !tex
->surface
.u
.legacy
.stencil_adjusted
;
1257 tex
->db_compatible
= surface
->flags
& RADEON_SURF_ZBUFFER
;
1259 if (tex
->surface
.cmask_offset
) {
1260 tex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
1261 tex
->cmask_buffer
= &tex
->buffer
;
1266 /* The buffer is shared with the first plane. */
1267 resource
->bo_size
= plane0
->buffer
.bo_size
;
1268 resource
->bo_alignment
= plane0
->buffer
.bo_alignment
;
1269 resource
->flags
= plane0
->buffer
.flags
;
1270 resource
->domains
= plane0
->buffer
.domains
;
1271 resource
->vram_usage
= plane0
->buffer
.vram_usage
;
1272 resource
->gart_usage
= plane0
->buffer
.gart_usage
;
1274 pb_reference(&resource
->buf
, plane0
->buffer
.buf
);
1275 resource
->gpu_address
= plane0
->buffer
.gpu_address
;
1276 } else if (!(surface
->flags
& RADEON_SURF_IMPORTED
)) {
1277 /* Create the backing buffer. */
1278 si_init_resource_fields(sscreen
, resource
, alloc_size
, alignment
);
1280 if (!si_alloc_resource(sscreen
, resource
))
1283 resource
->buf
= imported_buf
;
1284 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1285 resource
->bo_size
= imported_buf
->size
;
1286 resource
->bo_alignment
= imported_buf
->alignment
;
1287 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1288 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1289 resource
->vram_usage
= resource
->bo_size
;
1290 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1291 resource
->gart_usage
= resource
->bo_size
;
1292 if (sscreen
->ws
->buffer_get_flags
)
1293 resource
->flags
= sscreen
->ws
->buffer_get_flags(resource
->buf
);
1296 if (tex
->cmask_buffer
) {
1297 /* Initialize the cmask to 0xCC (= compressed state). */
1298 si_screen_clear_buffer(sscreen
, &tex
->cmask_buffer
->b
.b
, tex
->surface
.cmask_offset
,
1299 tex
->surface
.cmask_size
, 0xCCCCCCCC);
1301 if (tex
->surface
.htile_offset
) {
1302 uint32_t clear_value
= 0;
1304 if (sscreen
->info
.chip_class
>= GFX9
|| tex
->tc_compatible_htile
)
1305 clear_value
= 0x0000030F;
1307 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.htile_offset
,
1308 tex
->surface
.htile_size
, clear_value
);
1311 /* Initialize DCC only if the texture is not being imported. */
1312 if (!(surface
->flags
& RADEON_SURF_IMPORTED
) && tex
->surface
.dcc_offset
) {
1313 /* Clear DCC to black for all tiles with DCC enabled.
1315 * This fixes corruption in 3DMark Slingshot Extreme, which
1316 * uses uninitialized textures, causing corruption.
1318 if (tex
->surface
.num_dcc_levels
== tex
->buffer
.b
.b
.last_level
+ 1 &&
1319 tex
->buffer
.b
.b
.nr_samples
<= 2) {
1320 /* Simple case - all tiles have DCC enabled. */
1321 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
,
1322 tex
->surface
.dcc_size
, DCC_CLEAR_COLOR_0000
);
1323 } else if (sscreen
->info
.chip_class
>= GFX9
) {
1324 /* Clear to uncompressed. Clearing this to black is complicated. */
1325 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
,
1326 tex
->surface
.dcc_size
, DCC_UNCOMPRESSED
);
1328 /* GFX8: Initialize mipmap levels and multisamples separately. */
1329 if (tex
->buffer
.b
.b
.nr_samples
>= 2) {
1330 /* Clearing this to black is complicated. */
1331 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
,
1332 tex
->surface
.dcc_size
, DCC_UNCOMPRESSED
);
1334 /* Clear the enabled mipmap levels to black. */
1337 for (unsigned i
= 0; i
< tex
->surface
.num_dcc_levels
; i
++) {
1338 if (!tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
)
1341 size
= tex
->surface
.u
.legacy
.level
[i
].dcc_offset
+
1342 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
;
1345 /* Mipmap levels with DCC. */
1347 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
, size
,
1348 DCC_CLEAR_COLOR_0000
);
1350 /* Mipmap levels without DCC. */
1351 if (size
!= tex
->surface
.dcc_size
) {
1352 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
+ size
,
1353 tex
->surface
.dcc_size
- size
, DCC_UNCOMPRESSED
);
1358 /* Initialize displayable DCC that requires the retile blit. */
1359 if (tex
->surface
.dcc_retile_map_offset
) {
1360 /* Uninitialized DCC can hang the display hw.
1361 * Clear to white to indicate that. */
1362 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.display_dcc_offset
,
1363 tex
->surface
.u
.gfx9
.display_dcc_size
, DCC_CLEAR_COLOR_1111
);
1365 /* Upload the DCC retile map.
1366 * Use a staging buffer for the upload, because
1367 * the buffer backing the texture is unmappable.
1369 bool use_uint16
= tex
->surface
.u
.gfx9
.dcc_retile_use_uint16
;
1370 unsigned num_elements
= tex
->surface
.u
.gfx9
.dcc_retile_num_elements
;
1371 struct si_resource
*buf
= si_aligned_buffer_create(screen
, 0, PIPE_USAGE_STREAM
,
1372 num_elements
* (use_uint16
? 2 : 4),
1373 sscreen
->info
.tcc_cache_line_size
);
1374 uint32_t *ui
= (uint32_t *)sscreen
->ws
->buffer_map(buf
->buf
, NULL
, PIPE_TRANSFER_WRITE
);
1375 uint16_t *us
= (uint16_t *)ui
;
1377 /* Upload the retile map into a staging buffer. */
1379 for (unsigned i
= 0; i
< num_elements
; i
++)
1380 us
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1382 for (unsigned i
= 0; i
< num_elements
; i
++)
1383 ui
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1386 /* Copy the staging buffer to the buffer backing the texture. */
1387 struct si_context
*sctx
= (struct si_context
*)sscreen
->aux_context
;
1389 assert(tex
->surface
.dcc_retile_map_offset
<= UINT_MAX
);
1390 simple_mtx_lock(&sscreen
->aux_context_lock
);
1391 si_sdma_copy_buffer(sctx
, &tex
->buffer
.b
.b
, &buf
->b
.b
, tex
->surface
.dcc_retile_map_offset
,
1392 0, buf
->b
.b
.width0
);
1393 sscreen
->aux_context
->flush(sscreen
->aux_context
, NULL
, 0);
1394 simple_mtx_unlock(&sscreen
->aux_context_lock
);
1396 si_resource_reference(&buf
, NULL
);
1400 /* Initialize the CMASK base register value. */
1401 tex
->cmask_base_address_reg
= (tex
->buffer
.gpu_address
+ tex
->surface
.cmask_offset
) >> 8;
1403 if (sscreen
->debug_flags
& DBG(VM
)) {
1405 "VM start=0x%" PRIX64
" end=0x%" PRIX64
1406 " | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1407 tex
->buffer
.gpu_address
, tex
->buffer
.gpu_address
+ tex
->buffer
.buf
->size
,
1408 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+ 1,
1409 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1412 if (sscreen
->debug_flags
& DBG(TEX
)) {
1414 struct u_log_context log
;
1415 u_log_context_init(&log
);
1416 si_print_texture_info(sscreen
, tex
, &log
);
1417 u_log_new_page_print(&log
, stdout
);
1419 u_log_context_destroy(&log
);
1426 if (sscreen
->info
.chip_class
>= GFX9
)
1427 free(surface
->u
.gfx9
.dcc_retile_map
);
1431 static enum radeon_surf_mode
si_choose_tiling(struct si_screen
*sscreen
,
1432 const struct pipe_resource
*templ
,
1433 bool tc_compatible_htile
)
1435 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1436 bool force_tiling
= templ
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
;
1437 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1438 !(templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
);
1440 /* MSAA resources must be 2D tiled. */
1441 if (templ
->nr_samples
> 1)
1442 return RADEON_SURF_MODE_2D
;
1444 /* Transfer resources should be linear. */
1445 if (templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
)
1446 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1448 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on GFX8,
1449 * which requires 2D tiling.
1451 if (sscreen
->info
.chip_class
== GFX8
&& tc_compatible_htile
)
1452 return RADEON_SURF_MODE_2D
;
1454 /* Handle common candidates for the linear mode.
1455 * Compressed textures and DB surfaces must always be tiled.
1457 if (!force_tiling
&& !is_depth_stencil
&& !util_format_is_compressed(templ
->format
)) {
1458 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1459 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1461 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. */
1462 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1463 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1465 /* Cursors are linear on AMD GCN.
1466 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1467 if (templ
->bind
& PIPE_BIND_CURSOR
)
1468 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1470 if (templ
->bind
& PIPE_BIND_LINEAR
)
1471 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1473 /* Textures with a very small height are recommended to be linear. */
1474 if (templ
->target
== PIPE_TEXTURE_1D
|| templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1475 /* Only very thin and long 2D textures should benefit from
1476 * linear_aligned. */
1477 (templ
->width0
> 8 && templ
->height0
<= 2))
1478 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1480 /* Textures likely to be mapped often. */
1481 if (templ
->usage
== PIPE_USAGE_STAGING
|| templ
->usage
== PIPE_USAGE_STREAM
)
1482 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1485 /* Make small textures 1D tiled. */
1486 if (templ
->width0
<= 16 || templ
->height0
<= 16 || (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1487 return RADEON_SURF_MODE_1D
;
1489 /* The allocator will switch to 1D if needed. */
1490 return RADEON_SURF_MODE_2D
;
1493 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1494 const struct pipe_resource
*templ
)
1496 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1497 bool is_zs
= util_format_is_depth_or_stencil(templ
->format
);
1499 if (templ
->nr_samples
>= 2) {
1500 /* This is hackish (overwriting the const pipe_resource template),
1501 * but should be harmless and state trackers can also see
1502 * the overriden number of samples in the created pipe_resource.
1504 if (is_zs
&& sscreen
->eqaa_force_z_samples
) {
1505 ((struct pipe_resource
*)templ
)->nr_samples
=
1506 ((struct pipe_resource
*)templ
)->nr_storage_samples
= sscreen
->eqaa_force_z_samples
;
1507 } else if (!is_zs
&& sscreen
->eqaa_force_color_samples
) {
1508 ((struct pipe_resource
*)templ
)->nr_samples
= sscreen
->eqaa_force_coverage_samples
;
1509 ((struct pipe_resource
*)templ
)->nr_storage_samples
= sscreen
->eqaa_force_color_samples
;
1513 bool is_flushed_depth
=
1514 templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
|| templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
;
1515 bool tc_compatible_htile
=
1516 sscreen
->info
.chip_class
>= GFX8
&&
1517 /* There are issues with TC-compatible HTILE on Tonga (and
1518 * Iceland is the same design), and documented bug workarounds
1519 * don't help. For example, this fails:
1520 * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow -auto
1522 sscreen
->info
.family
!= CHIP_TONGA
&& sscreen
->info
.family
!= CHIP_ICELAND
&&
1523 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1524 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) && !is_flushed_depth
&&
1525 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1527 enum radeon_surf_mode tile_mode
= si_choose_tiling(sscreen
, templ
, tc_compatible_htile
);
1529 /* This allocates textures with multiple planes like NV12 in 1 buffer. */
1532 SI_TEXTURE_MAX_PLANES
= 3
1534 struct radeon_surf surface
[SI_TEXTURE_MAX_PLANES
] = {};
1535 struct pipe_resource plane_templ
[SI_TEXTURE_MAX_PLANES
];
1536 uint64_t plane_offset
[SI_TEXTURE_MAX_PLANES
] = {};
1537 uint64_t total_size
= 0;
1538 unsigned max_alignment
= 0;
1539 unsigned num_planes
= util_format_get_num_planes(templ
->format
);
1540 assert(num_planes
<= SI_TEXTURE_MAX_PLANES
);
1542 /* Compute texture or plane layouts and offsets. */
1543 for (unsigned i
= 0; i
< num_planes
; i
++) {
1544 plane_templ
[i
] = *templ
;
1545 plane_templ
[i
].format
= util_format_get_plane_format(templ
->format
, i
);
1546 plane_templ
[i
].width0
= util_format_get_plane_width(templ
->format
, i
, templ
->width0
);
1547 plane_templ
[i
].height0
= util_format_get_plane_height(templ
->format
, i
, templ
->height0
);
1549 /* Multi-plane allocations need PIPE_BIND_SHARED, because we can't
1550 * reallocate the storage to add PIPE_BIND_SHARED, because it's
1551 * shared by 3 pipe_resources.
1554 plane_templ
[i
].bind
|= PIPE_BIND_SHARED
;
1556 if (si_init_surface(sscreen
, &surface
[i
], &plane_templ
[i
], tile_mode
, 0, false,
1557 plane_templ
[i
].bind
& PIPE_BIND_SCANOUT
, is_flushed_depth
,
1558 tc_compatible_htile
))
1561 plane_offset
[i
] = align64(total_size
, surface
[i
].surf_alignment
);
1562 total_size
= plane_offset
[i
] + surface
[i
].total_size
;
1563 max_alignment
= MAX2(max_alignment
, surface
[i
].surf_alignment
);
1566 struct si_texture
*plane0
= NULL
, *last_plane
= NULL
;
1568 for (unsigned i
= 0; i
< num_planes
; i
++) {
1569 struct si_texture
*tex
=
1570 si_texture_create_object(screen
, &plane_templ
[i
], &surface
[i
], plane0
, NULL
,
1571 plane_offset
[i
], total_size
, max_alignment
,
1572 tc_compatible_htile
);
1574 si_texture_reference(&plane0
, NULL
);
1578 tex
->plane_index
= i
;
1579 tex
->num_planes
= num_planes
;
1582 plane0
= last_plane
= tex
;
1584 last_plane
->buffer
.b
.b
.next
= &tex
->buffer
.b
.b
;
1589 return (struct pipe_resource
*)plane0
;
1592 static struct pipe_resource
*si_texture_from_winsys_buffer(struct si_screen
*sscreen
,
1593 const struct pipe_resource
*templ
,
1594 struct pb_buffer
*buf
, unsigned stride
,
1595 unsigned offset
, unsigned usage
,
1598 enum radeon_surf_mode array_mode
;
1599 struct radeon_surf surface
= {};
1600 struct radeon_bo_metadata metadata
= {};
1601 struct si_texture
*tex
;
1605 /* Ignore metadata for non-zero planes. */
1610 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1611 si_get_display_metadata(sscreen
, &surface
, &metadata
, &array_mode
, &is_scanout
);
1614 * The bo metadata is unset for un-dedicated images. So we fall
1615 * back to linear. See answer to question 5 of the
1616 * VK_KHX_external_memory spec for some details.
1618 * It is possible that this case isn't going to work if the
1619 * surface pitch isn't correctly aligned by default.
1621 * In order to support it correctly we require multi-image
1622 * metadata to be syncrhonized between radv and radeonsi. The
1623 * semantics of associating multiple image metadata to a memory
1624 * object on the vulkan export side are not concretely defined
1627 * All the use cases we are aware of at the moment for memory
1628 * objects use dedicated allocations. So lets keep the initial
1629 * implementation simple.
1631 * A possible alternative is to attempt to reconstruct the
1632 * tiling information when the TexParameter TEXTURE_TILING_EXT
1635 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1640 si_init_surface(sscreen
, &surface
, templ
, array_mode
, stride
, true, is_scanout
, false, false);
1644 tex
= si_texture_create_object(&sscreen
->b
, templ
, &surface
, NULL
, buf
, offset
, 0, 0, false);
1648 tex
->buffer
.b
.is_shared
= true;
1649 tex
->buffer
.external_usage
= usage
;
1650 tex
->num_planes
= 1;
1652 /* Account for multiple planes with lowered yuv import. */
1653 struct pipe_resource
*next_plane
= tex
->buffer
.b
.b
.next
;
1655 struct si_texture
*next_tex
= (struct si_texture
*)next_plane
;
1656 ++next_tex
->num_planes
;
1658 next_plane
= next_plane
->next
;
1661 if (!si_read_tex_bo_metadata(sscreen
, tex
, offset
, &metadata
)) {
1662 si_texture_reference(&tex
, NULL
);
1666 /* Displayable DCC requires an explicit flush. */
1667 if (dedicated
&& offset
== 0 && !(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
1668 si_has_displayable_dcc(tex
)) {
1669 /* TODO: do we need to decompress DCC? */
1670 if (si_texture_discard_dcc(sscreen
, tex
)) {
1671 /* Update BO metadata after disabling DCC. */
1672 si_set_tex_bo_metadata(sscreen
, tex
);
1676 assert(tex
->surface
.tile_swizzle
== 0);
1677 return &tex
->buffer
.b
.b
;
1680 static struct pipe_resource
*si_texture_from_handle(struct pipe_screen
*screen
,
1681 const struct pipe_resource
*templ
,
1682 struct winsys_handle
*whandle
, unsigned usage
)
1684 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1685 struct pb_buffer
*buf
= NULL
;
1687 /* Support only 2D textures without mipmaps */
1688 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
&&
1689 templ
->target
!= PIPE_TEXTURE_2D_ARRAY
) ||
1690 templ
->last_level
!= 0)
1693 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
, sscreen
->info
.max_alignment
);
1697 return si_texture_from_winsys_buffer(sscreen
, templ
, buf
, whandle
->stride
, whandle
->offset
,
1701 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
, struct pipe_resource
*texture
)
1703 struct si_texture
*tex
= (struct si_texture
*)texture
;
1704 struct pipe_resource resource
;
1705 enum pipe_format pipe_format
= texture
->format
;
1707 assert(!tex
->flushed_depth_texture
);
1709 if (!tex
->can_sample_z
&& tex
->can_sample_s
) {
1710 switch (pipe_format
) {
1711 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1712 /* Save memory by not allocating the S plane. */
1713 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1715 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1716 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1717 /* Save memory bandwidth by not copying the
1718 * stencil part during flush.
1720 * This potentially increases memory bandwidth
1721 * if an application uses both Z and S texturing
1722 * simultaneously (a flushed Z24S8 texture
1723 * would be stored compactly), but how often
1724 * does that really happen?
1726 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1730 } else if (!tex
->can_sample_s
&& tex
->can_sample_z
) {
1731 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1733 /* DB->CB copies to an 8bpp surface don't work. */
1734 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1737 memset(&resource
, 0, sizeof(resource
));
1738 resource
.target
= texture
->target
;
1739 resource
.format
= pipe_format
;
1740 resource
.width0
= texture
->width0
;
1741 resource
.height0
= texture
->height0
;
1742 resource
.depth0
= texture
->depth0
;
1743 resource
.array_size
= texture
->array_size
;
1744 resource
.last_level
= texture
->last_level
;
1745 resource
.nr_samples
= texture
->nr_samples
;
1746 resource
.usage
= PIPE_USAGE_DEFAULT
;
1747 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1748 resource
.flags
= texture
->flags
| SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1750 tex
->flushed_depth_texture
=
1751 (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1752 if (!tex
->flushed_depth_texture
) {
1753 PRINT_ERR("failed to create temporary texture to hold flushed depth\n");
1760 * Initialize the pipe_resource descriptor to be of the same size as the box,
1761 * which is supposed to hold a subregion of the texture "orig" at the given
1764 static void si_init_temp_resource_from_box(struct pipe_resource
*res
, struct pipe_resource
*orig
,
1765 const struct pipe_box
*box
, unsigned level
,
1768 memset(res
, 0, sizeof(*res
));
1769 res
->format
= orig
->format
;
1770 res
->width0
= box
->width
;
1771 res
->height0
= box
->height
;
1773 res
->array_size
= 1;
1774 res
->usage
= flags
& SI_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1777 if (flags
& SI_RESOURCE_FLAG_TRANSFER
&& util_format_is_compressed(orig
->format
)) {
1778 /* Transfer resources are allocated with linear tiling, which is
1779 * not supported for compressed formats.
1781 unsigned blocksize
= util_format_get_blocksize(orig
->format
);
1783 if (blocksize
== 8) {
1784 res
->format
= PIPE_FORMAT_R16G16B16A16_UINT
;
1786 assert(blocksize
== 16);
1787 res
->format
= PIPE_FORMAT_R32G32B32A32_UINT
;
1790 res
->width0
= util_format_get_nblocksx(orig
->format
, box
->width
);
1791 res
->height0
= util_format_get_nblocksy(orig
->format
, box
->height
);
1794 /* We must set the correct texture target and dimensions for a 3D box. */
1795 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1796 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1797 res
->array_size
= box
->depth
;
1799 res
->target
= PIPE_TEXTURE_2D
;
1803 static bool si_can_invalidate_texture(struct si_screen
*sscreen
, struct si_texture
*tex
,
1804 unsigned transfer_usage
, const struct pipe_box
*box
)
1806 return !tex
->buffer
.b
.is_shared
&& !(tex
->surface
.flags
& RADEON_SURF_IMPORTED
) &&
1807 !(transfer_usage
& PIPE_TRANSFER_READ
) && tex
->buffer
.b
.b
.last_level
== 0 &&
1808 util_texrange_covers_whole_level(&tex
->buffer
.b
.b
, 0, box
->x
, box
->y
, box
->z
, box
->width
,
1809 box
->height
, box
->depth
);
1812 static void si_texture_invalidate_storage(struct si_context
*sctx
, struct si_texture
*tex
)
1814 struct si_screen
*sscreen
= sctx
->screen
;
1816 /* There is no point in discarding depth and tiled buffers. */
1817 assert(!tex
->is_depth
);
1818 assert(tex
->surface
.is_linear
);
1820 /* Reallocate the buffer in the same pipe_resource. */
1821 si_alloc_resource(sscreen
, &tex
->buffer
);
1823 /* Initialize the CMASK base address (needed even without CMASK). */
1824 tex
->cmask_base_address_reg
= (tex
->buffer
.gpu_address
+ tex
->surface
.cmask_offset
) >> 8;
1826 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1828 sctx
->num_alloc_tex_transfer_bytes
+= tex
->surface
.total_size
;
1831 static void *si_texture_transfer_map(struct pipe_context
*ctx
, struct pipe_resource
*texture
,
1832 unsigned level
, unsigned usage
, const struct pipe_box
*box
,
1833 struct pipe_transfer
**ptransfer
)
1835 struct si_context
*sctx
= (struct si_context
*)ctx
;
1836 struct si_texture
*tex
= (struct si_texture
*)texture
;
1837 struct si_transfer
*trans
;
1838 struct si_resource
*buf
;
1839 unsigned offset
= 0;
1841 bool use_staging_texture
= false;
1843 assert(!(texture
->flags
& SI_RESOURCE_FLAG_TRANSFER
));
1844 assert(box
->width
&& box
->height
&& box
->depth
);
1846 if (tex
->is_depth
) {
1847 /* Depth textures use staging unconditionally. */
1848 use_staging_texture
= true;
1850 /* Degrade the tile mode if we get too many transfers on APUs.
1851 * On dGPUs, the staging texture is always faster.
1852 * Only count uploads that are at least 4x4 pixels large.
1854 if (!sctx
->screen
->info
.has_dedicated_vram
&& level
== 0 && box
->width
>= 4 &&
1855 box
->height
>= 4 && p_atomic_inc_return(&tex
->num_level0_transfers
) == 10) {
1856 bool can_invalidate
= si_can_invalidate_texture(sctx
->screen
, tex
, usage
, box
);
1858 si_reallocate_texture_inplace(sctx
, tex
, PIPE_BIND_LINEAR
, can_invalidate
);
1861 /* Tiled textures need to be converted into a linear texture for CPU
1862 * access. The staging texture is always linear and is placed in GART.
1864 * Reading from VRAM or GTT WC is slow, always use the staging
1865 * texture in this case.
1867 * Use the staging texture for uploads if the underlying BO
1870 if (!tex
->surface
.is_linear
)
1871 use_staging_texture
= true;
1872 else if (usage
& PIPE_TRANSFER_READ
)
1873 use_staging_texture
=
1874 tex
->buffer
.domains
& RADEON_DOMAIN_VRAM
|| tex
->buffer
.flags
& RADEON_FLAG_GTT_WC
;
1875 /* Write & linear only: */
1876 else if (si_rings_is_buffer_referenced(sctx
, tex
->buffer
.buf
, RADEON_USAGE_READWRITE
) ||
1877 !sctx
->ws
->buffer_wait(tex
->buffer
.buf
, 0, RADEON_USAGE_READWRITE
)) {
1879 if (si_can_invalidate_texture(sctx
->screen
, tex
, usage
, box
))
1880 si_texture_invalidate_storage(sctx
, tex
);
1882 use_staging_texture
= true;
1886 trans
= CALLOC_STRUCT(si_transfer
);
1889 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1890 trans
->b
.b
.level
= level
;
1891 trans
->b
.b
.usage
= usage
;
1892 trans
->b
.b
.box
= *box
;
1894 if (use_staging_texture
) {
1895 struct pipe_resource resource
;
1896 struct si_texture
*staging
;
1898 si_init_temp_resource_from_box(&resource
, texture
, box
, level
, SI_RESOURCE_FLAG_TRANSFER
);
1899 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ? PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1901 /* Since depth-stencil textures don't support linear tiling,
1902 * blit from ZS to color and vice versa. u_blitter will do
1903 * the packing for these formats.
1906 resource
.format
= util_blitter_get_color_format_for_zs(resource
.format
);
1908 /* Create the temporary texture. */
1909 staging
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1911 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1914 trans
->staging
= &staging
->buffer
;
1916 /* Just get the strides. */
1917 si_texture_get_offset(sctx
->screen
, staging
, 0, NULL
, &trans
->b
.b
.stride
,
1918 &trans
->b
.b
.layer_stride
);
1920 if (usage
& PIPE_TRANSFER_READ
)
1921 si_copy_to_staging_texture(ctx
, trans
);
1923 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1925 buf
= trans
->staging
;
1927 /* the resource is mapped directly */
1928 offset
= si_texture_get_offset(sctx
->screen
, tex
, level
, box
, &trans
->b
.b
.stride
,
1929 &trans
->b
.b
.layer_stride
);
1933 /* Always unmap texture CPU mappings on 32-bit architectures, so that
1934 * we don't run out of the CPU address space.
1936 if (sizeof(void *) == 4)
1937 usage
|= RADEON_TRANSFER_TEMPORARY
;
1939 if (!(map
= si_buffer_map_sync_with_rings(sctx
, buf
, usage
)))
1942 *ptransfer
= &trans
->b
.b
;
1943 return map
+ offset
;
1946 si_resource_reference(&trans
->staging
, NULL
);
1947 pipe_resource_reference(&trans
->b
.b
.resource
, NULL
);
1952 static void si_texture_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*transfer
)
1954 struct si_context
*sctx
= (struct si_context
*)ctx
;
1955 struct si_transfer
*stransfer
= (struct si_transfer
*)transfer
;
1956 struct pipe_resource
*texture
= transfer
->resource
;
1957 struct si_texture
*tex
= (struct si_texture
*)texture
;
1959 /* Always unmap texture CPU mappings on 32-bit architectures, so that
1960 * we don't run out of the CPU address space.
1962 if (sizeof(void *) == 4) {
1963 struct si_resource
*buf
= stransfer
->staging
? stransfer
->staging
: &tex
->buffer
;
1965 sctx
->ws
->buffer_unmap(buf
->buf
);
1968 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && stransfer
->staging
)
1969 si_copy_from_staging_texture(ctx
, stransfer
);
1971 if (stransfer
->staging
) {
1972 sctx
->num_alloc_tex_transfer_bytes
+= stransfer
->staging
->buf
->size
;
1973 si_resource_reference(&stransfer
->staging
, NULL
);
1976 /* Heuristic for {upload, draw, upload, draw, ..}:
1978 * Flush the gfx IB if we've allocated too much texture storage.
1980 * The idea is that we don't want to build IBs that use too much
1981 * memory and put pressure on the kernel memory manager and we also
1982 * want to make temporary and invalidated buffers go idle ASAP to
1983 * decrease the total memory usage or make them reusable. The memory
1984 * usage will be slightly higher than given here because of the buffer
1985 * cache in the winsys.
1987 * The result is that the kernel memory manager is never a bottleneck.
1989 if (sctx
->num_alloc_tex_transfer_bytes
> sctx
->screen
->info
.gart_size
/ 4) {
1990 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1991 sctx
->num_alloc_tex_transfer_bytes
= 0;
1994 pipe_resource_reference(&transfer
->resource
, NULL
);
1998 static const struct u_resource_vtbl si_texture_vtbl
= {
1999 NULL
, /* get_handle */
2000 si_texture_destroy
, /* resource_destroy */
2001 si_texture_transfer_map
, /* transfer_map */
2002 u_default_transfer_flush_region
, /* transfer_flush_region */
2003 si_texture_transfer_unmap
, /* transfer_unmap */
2006 /* Return if it's allowed to reinterpret one format as another with DCC enabled.
2008 bool vi_dcc_formats_compatible(struct si_screen
*sscreen
, enum pipe_format format1
,
2009 enum pipe_format format2
)
2011 const struct util_format_description
*desc1
, *desc2
;
2013 /* No format change - exit early. */
2014 if (format1
== format2
)
2017 format1
= si_simplify_cb_format(format1
);
2018 format2
= si_simplify_cb_format(format2
);
2020 /* Check again after format adjustments. */
2021 if (format1
== format2
)
2024 desc1
= util_format_description(format1
);
2025 desc2
= util_format_description(format2
);
2027 if (desc1
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
|| desc2
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2030 /* Float and non-float are totally incompatible. */
2031 if ((desc1
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
) !=
2032 (desc2
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
))
2035 /* Channel sizes must match across DCC formats.
2036 * Comparing just the first 2 channels should be enough.
2038 if (desc1
->channel
[0].size
!= desc2
->channel
[0].size
||
2039 (desc1
->nr_channels
>= 2 && desc1
->channel
[1].size
!= desc2
->channel
[1].size
))
2042 /* Everything below is not needed if the driver never uses the DCC
2043 * clear code with the value of 1.
2046 /* If the clear values are all 1 or all 0, this constraint can be
2048 if (vi_alpha_is_on_msb(sscreen
, format1
) != vi_alpha_is_on_msb(sscreen
, format2
))
2051 /* Channel types must match if the clear value of 1 is used.
2052 * The type categories are only float, signed, unsigned.
2053 * NORM and INT are always compatible.
2055 if (desc1
->channel
[0].type
!= desc2
->channel
[0].type
||
2056 (desc1
->nr_channels
>= 2 && desc1
->channel
[1].type
!= desc2
->channel
[1].type
))
2062 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
, unsigned level
,
2063 enum pipe_format view_format
)
2065 struct si_texture
*stex
= (struct si_texture
*)tex
;
2067 return vi_dcc_enabled(stex
, level
) &&
2068 !vi_dcc_formats_compatible((struct si_screen
*)tex
->screen
, tex
->format
, view_format
);
2071 /* This can't be merged with the above function, because
2072 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
2073 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
, struct pipe_resource
*tex
,
2074 unsigned level
, enum pipe_format view_format
)
2076 struct si_texture
*stex
= (struct si_texture
*)tex
;
2078 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
2079 if (!si_texture_disable_dcc(sctx
, stex
))
2080 si_decompress_dcc(sctx
, stex
);
2083 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
2084 struct pipe_resource
*texture
,
2085 const struct pipe_surface
*templ
, unsigned width0
,
2086 unsigned height0
, unsigned width
, unsigned height
)
2088 struct si_surface
*surface
= CALLOC_STRUCT(si_surface
);
2093 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2094 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2096 pipe_reference_init(&surface
->base
.reference
, 1);
2097 pipe_resource_reference(&surface
->base
.texture
, texture
);
2098 surface
->base
.context
= pipe
;
2099 surface
->base
.format
= templ
->format
;
2100 surface
->base
.width
= width
;
2101 surface
->base
.height
= height
;
2102 surface
->base
.u
= templ
->u
;
2104 surface
->width0
= width0
;
2105 surface
->height0
= height0
;
2107 surface
->dcc_incompatible
=
2108 texture
->target
!= PIPE_BUFFER
&&
2109 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
, templ
->format
);
2110 return &surface
->base
;
2113 static struct pipe_surface
*si_create_surface(struct pipe_context
*pipe
, struct pipe_resource
*tex
,
2114 const struct pipe_surface
*templ
)
2116 unsigned level
= templ
->u
.tex
.level
;
2117 unsigned width
= u_minify(tex
->width0
, level
);
2118 unsigned height
= u_minify(tex
->height0
, level
);
2119 unsigned width0
= tex
->width0
;
2120 unsigned height0
= tex
->height0
;
2122 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2123 const struct util_format_description
*tex_desc
= util_format_description(tex
->format
);
2124 const struct util_format_description
*templ_desc
= util_format_description(templ
->format
);
2126 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2128 /* Adjust size of surface if and only if the block width or
2129 * height is changed. */
2130 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2131 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2132 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2133 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2135 width
= nblks_x
* templ_desc
->block
.width
;
2136 height
= nblks_y
* templ_desc
->block
.height
;
2138 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2139 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2143 return si_create_surface_custom(pipe
, tex
, templ
, width0
, height0
, width
, height
);
2146 static void si_surface_destroy(struct pipe_context
*pipe
, struct pipe_surface
*surface
)
2148 pipe_resource_reference(&surface
->texture
, NULL
);
2152 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2154 const struct util_format_description
*desc
= util_format_description(format
);
2156 #define HAS_SWIZZLE(chan, swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2158 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2159 return V_028C70_SWAP_STD
;
2161 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2164 switch (desc
->nr_channels
) {
2166 if (HAS_SWIZZLE(0, X
))
2167 return V_028C70_SWAP_STD
; /* X___ */
2168 else if (HAS_SWIZZLE(3, X
))
2169 return V_028C70_SWAP_ALT_REV
; /* ___X */
2172 if ((HAS_SWIZZLE(0, X
) && HAS_SWIZZLE(1, Y
)) || (HAS_SWIZZLE(0, X
) && HAS_SWIZZLE(1, NONE
)) ||
2173 (HAS_SWIZZLE(0, NONE
) && HAS_SWIZZLE(1, Y
)))
2174 return V_028C70_SWAP_STD
; /* XY__ */
2175 else if ((HAS_SWIZZLE(0, Y
) && HAS_SWIZZLE(1, X
)) ||
2176 (HAS_SWIZZLE(0, Y
) && HAS_SWIZZLE(1, NONE
)) ||
2177 (HAS_SWIZZLE(0, NONE
) && HAS_SWIZZLE(1, X
)))
2179 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2180 else if (HAS_SWIZZLE(0, X
) && HAS_SWIZZLE(3, Y
))
2181 return V_028C70_SWAP_ALT
; /* X__Y */
2182 else if (HAS_SWIZZLE(0, Y
) && HAS_SWIZZLE(3, X
))
2183 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2186 if (HAS_SWIZZLE(0, X
))
2187 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2188 else if (HAS_SWIZZLE(0, Z
))
2189 return V_028C70_SWAP_STD_REV
; /* ZYX */
2192 /* check the middle channels, the 1st and 4th channel can be NONE */
2193 if (HAS_SWIZZLE(1, Y
) && HAS_SWIZZLE(2, Z
)) {
2194 return V_028C70_SWAP_STD
; /* XYZW */
2195 } else if (HAS_SWIZZLE(1, Z
) && HAS_SWIZZLE(2, Y
)) {
2196 return V_028C70_SWAP_STD_REV
; /* WZYX */
2197 } else if (HAS_SWIZZLE(1, Y
) && HAS_SWIZZLE(2, X
)) {
2198 return V_028C70_SWAP_ALT
; /* ZYXW */
2199 } else if (HAS_SWIZZLE(1, Z
) && HAS_SWIZZLE(2, W
)) {
2202 return V_028C70_SWAP_ALT_REV
;
2204 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2211 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2213 static void vi_dcc_clean_up_context_slot(struct si_context
*sctx
, int slot
)
2217 if (sctx
->dcc_stats
[slot
].query_active
)
2218 vi_separate_dcc_stop_query(sctx
, sctx
->dcc_stats
[slot
].tex
);
2220 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
[slot
].ps_stats
); i
++)
2221 if (sctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2222 sctx
->b
.destroy_query(&sctx
->b
, sctx
->dcc_stats
[slot
].ps_stats
[i
]);
2223 sctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2226 si_texture_reference(&sctx
->dcc_stats
[slot
].tex
, NULL
);
2230 * Return the per-context slot where DCC statistics queries for the texture live.
2232 static unsigned vi_get_context_dcc_stats_index(struct si_context
*sctx
, struct si_texture
*tex
)
2234 int i
, empty_slot
= -1;
2236 /* Remove zombie textures (textures kept alive by this array only). */
2237 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2238 if (sctx
->dcc_stats
[i
].tex
&& sctx
->dcc_stats
[i
].tex
->buffer
.b
.b
.reference
.count
== 1)
2239 vi_dcc_clean_up_context_slot(sctx
, i
);
2241 /* Find the texture. */
2242 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
2243 /* Return if found. */
2244 if (sctx
->dcc_stats
[i
].tex
== tex
) {
2245 sctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2249 /* Record the first seen empty slot. */
2250 if (empty_slot
== -1 && !sctx
->dcc_stats
[i
].tex
)
2254 /* Not found. Remove the oldest member to make space in the array. */
2255 if (empty_slot
== -1) {
2256 int oldest_slot
= 0;
2258 /* Find the oldest slot. */
2259 for (i
= 1; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2260 if (sctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2261 sctx
->dcc_stats
[i
].last_use_timestamp
)
2264 /* Clean up the oldest slot. */
2265 vi_dcc_clean_up_context_slot(sctx
, oldest_slot
);
2266 empty_slot
= oldest_slot
;
2269 /* Add the texture to the new slot. */
2270 si_texture_reference(&sctx
->dcc_stats
[empty_slot
].tex
, tex
);
2271 sctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2275 static struct pipe_query
*vi_create_resuming_pipestats_query(struct si_context
*sctx
)
2277 struct si_query_hw
*query
=
2278 (struct si_query_hw
*)sctx
->b
.create_query(&sctx
->b
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2280 query
->flags
|= SI_QUERY_HW_FLAG_BEGIN_RESUMES
;
2281 return (struct pipe_query
*)query
;
2285 * Called when binding a color buffer.
2287 void vi_separate_dcc_start_query(struct si_context
*sctx
, struct si_texture
*tex
)
2289 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2291 assert(!sctx
->dcc_stats
[i
].query_active
);
2293 if (!sctx
->dcc_stats
[i
].ps_stats
[0])
2294 sctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(sctx
);
2296 /* begin or resume the query */
2297 sctx
->b
.begin_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2298 sctx
->dcc_stats
[i
].query_active
= true;
2302 * Called when unbinding a color buffer.
2304 void vi_separate_dcc_stop_query(struct si_context
*sctx
, struct si_texture
*tex
)
2306 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2308 assert(sctx
->dcc_stats
[i
].query_active
);
2309 assert(sctx
->dcc_stats
[i
].ps_stats
[0]);
2311 /* pause or end the query */
2312 sctx
->b
.end_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2313 sctx
->dcc_stats
[i
].query_active
= false;
2316 static bool vi_should_enable_separate_dcc(struct si_texture
*tex
)
2318 /* The minimum number of fullscreen draws per frame that is required
2320 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2323 /* Called by fast clear. */
2324 void vi_separate_dcc_try_enable(struct si_context
*sctx
, struct si_texture
*tex
)
2326 /* The intent is to use this with shared displayable back buffers,
2327 * but it's not strictly limited only to them.
2329 if (!tex
->buffer
.b
.is_shared
||
2330 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2331 tex
->buffer
.b
.b
.target
!= PIPE_TEXTURE_2D
|| tex
->buffer
.b
.b
.last_level
> 0 ||
2332 !tex
->surface
.dcc_size
|| sctx
->screen
->debug_flags
& DBG(NO_DCC
) ||
2333 sctx
->screen
->debug_flags
& DBG(NO_DCC_FB
))
2336 assert(sctx
->chip_class
>= GFX8
);
2338 if (tex
->surface
.dcc_offset
)
2339 return; /* already enabled */
2341 /* Enable the DCC stat gathering. */
2342 if (!tex
->dcc_gather_statistics
) {
2343 tex
->dcc_gather_statistics
= true;
2344 vi_separate_dcc_start_query(sctx
, tex
);
2347 if (!vi_should_enable_separate_dcc(tex
))
2348 return; /* stats show that DCC decompression is too expensive */
2350 assert(tex
->surface
.num_dcc_levels
);
2351 assert(!tex
->dcc_separate_buffer
);
2353 si_texture_discard_cmask(sctx
->screen
, tex
);
2355 /* Get a DCC buffer. */
2356 if (tex
->last_dcc_separate_buffer
) {
2357 assert(tex
->dcc_gather_statistics
);
2358 assert(!tex
->dcc_separate_buffer
);
2359 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2360 tex
->last_dcc_separate_buffer
= NULL
;
2362 tex
->dcc_separate_buffer
=
2363 si_aligned_buffer_create(sctx
->b
.screen
, SI_RESOURCE_FLAG_UNMAPPABLE
, PIPE_USAGE_DEFAULT
,
2364 tex
->surface
.dcc_size
, tex
->surface
.dcc_alignment
);
2365 if (!tex
->dcc_separate_buffer
)
2369 /* dcc_offset is the absolute GPUVM address. */
2370 tex
->surface
.dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2372 /* no need to flag anything since this is called by fast clear that
2373 * flags framebuffer state
2378 * Called by pipe_context::flush_resource, the place where DCC decompression
2381 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
, struct si_texture
*tex
)
2383 struct si_context
*sctx
= (struct si_context
*)ctx
;
2384 struct pipe_query
*tmp
;
2385 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2386 bool query_active
= sctx
->dcc_stats
[i
].query_active
;
2387 bool disable
= false;
2389 if (sctx
->dcc_stats
[i
].ps_stats
[2]) {
2390 union pipe_query_result result
;
2392 /* Read the results. */
2393 struct pipe_query
*query
= sctx
->dcc_stats
[i
].ps_stats
[2];
2394 ctx
->get_query_result(ctx
, query
, true, &result
);
2395 si_query_buffer_reset(sctx
, &((struct si_query_hw
*)query
)->buffer
);
2397 /* Compute the approximate number of fullscreen draws. */
2398 tex
->ps_draw_ratio
= result
.pipeline_statistics
.ps_invocations
/
2399 (tex
->buffer
.b
.b
.width0
* tex
->buffer
.b
.b
.height0
);
2400 sctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2402 disable
= tex
->dcc_separate_buffer
&& !vi_should_enable_separate_dcc(tex
);
2405 tex
->num_slow_clears
= 0;
2407 /* stop the statistics query for ps_stats[0] */
2409 vi_separate_dcc_stop_query(sctx
, tex
);
2411 /* Move the queries in the queue by one. */
2412 tmp
= sctx
->dcc_stats
[i
].ps_stats
[2];
2413 sctx
->dcc_stats
[i
].ps_stats
[2] = sctx
->dcc_stats
[i
].ps_stats
[1];
2414 sctx
->dcc_stats
[i
].ps_stats
[1] = sctx
->dcc_stats
[i
].ps_stats
[0];
2415 sctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2417 /* create and start a new query as ps_stats[0] */
2419 vi_separate_dcc_start_query(sctx
, tex
);
2422 assert(!tex
->last_dcc_separate_buffer
);
2423 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2424 tex
->dcc_separate_buffer
= NULL
;
2425 tex
->surface
.dcc_offset
= 0;
2426 /* no need to flag anything since this is called after
2427 * decompression that re-sets framebuffer state
2432 static struct pipe_memory_object
*
2433 si_memobj_from_handle(struct pipe_screen
*screen
, struct winsys_handle
*whandle
, bool dedicated
)
2435 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2436 struct si_memory_object
*memobj
= CALLOC_STRUCT(si_memory_object
);
2437 struct pb_buffer
*buf
= NULL
;
2442 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
, sscreen
->info
.max_alignment
);
2448 memobj
->b
.dedicated
= dedicated
;
2450 memobj
->stride
= whandle
->stride
;
2452 return (struct pipe_memory_object
*)memobj
;
2455 static void si_memobj_destroy(struct pipe_screen
*screen
, struct pipe_memory_object
*_memobj
)
2457 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2459 pb_reference(&memobj
->buf
, NULL
);
2463 static struct pipe_resource
*si_texture_from_memobj(struct pipe_screen
*screen
,
2464 const struct pipe_resource
*templ
,
2465 struct pipe_memory_object
*_memobj
,
2468 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2469 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2470 struct pipe_resource
*tex
= si_texture_from_winsys_buffer(
2471 sscreen
, templ
, memobj
->buf
, memobj
->stride
, offset
,
2472 PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
| PIPE_HANDLE_USAGE_SHADER_WRITE
, memobj
->b
.dedicated
);
2476 /* si_texture_from_winsys_buffer doesn't increment refcount of
2477 * memobj->buf, so increment it here.
2479 struct pb_buffer
*buf
= NULL
;
2480 pb_reference(&buf
, memobj
->buf
);
2484 static bool si_check_resource_capability(struct pipe_screen
*screen
, struct pipe_resource
*resource
,
2487 struct si_texture
*tex
= (struct si_texture
*)resource
;
2489 /* Buffers only support the linear flag. */
2490 if (resource
->target
== PIPE_BUFFER
)
2491 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2493 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2496 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2499 /* TODO: PIPE_BIND_CURSOR - do we care? */
2503 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2505 sscreen
->b
.resource_from_handle
= si_texture_from_handle
;
2506 sscreen
->b
.resource_get_handle
= si_texture_get_handle
;
2507 sscreen
->b
.resource_get_param
= si_resource_get_param
;
2508 sscreen
->b
.resource_get_info
= si_texture_get_info
;
2509 sscreen
->b
.resource_from_memobj
= si_texture_from_memobj
;
2510 sscreen
->b
.memobj_create_from_handle
= si_memobj_from_handle
;
2511 sscreen
->b
.memobj_destroy
= si_memobj_destroy
;
2512 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2515 void si_init_context_texture_functions(struct si_context
*sctx
)
2517 sctx
->b
.create_surface
= si_create_surface
;
2518 sctx
->b
.surface_destroy
= si_surface_destroy
;