2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeonsi/si_pipe.h"
27 #include "radeonsi/si_query.h"
28 #include "util/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/u_resource.h"
33 #include "util/u_surface.h"
34 #include "util/u_transfer.h"
35 #include "util/os_time.h"
38 #include "state_tracker/drm_driver.h"
39 #include "amd/common/sid.h"
41 static enum radeon_surf_mode
42 si_choose_tiling(struct si_screen
*sscreen
,
43 const struct pipe_resource
*templ
, bool tc_compatible_htile
);
46 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
47 struct si_texture
*dst
,
48 unsigned dst_level
, unsigned dstx
,
49 unsigned dsty
, unsigned dstz
,
50 struct si_texture
*src
,
52 const struct pipe_box
*src_box
)
57 if (dst
->surface
.bpe
!= src
->surface
.bpe
)
60 /* MSAA: Blits don't exist in the real world. */
61 if (src
->buffer
.b
.b
.nr_samples
> 1 ||
62 dst
->buffer
.b
.b
.nr_samples
> 1)
65 /* Depth-stencil surfaces:
66 * When dst is linear, the DB->CB copy preserves HTILE.
67 * When dst is tiled, the 3D path must be used to update HTILE.
69 if (src
->is_depth
|| dst
->is_depth
)
73 * src: Use the 3D path. DCC decompression is expensive.
74 * dst: Use the 3D path to compress the pixels with DCC.
76 if (vi_dcc_enabled(src
, src_level
) ||
77 vi_dcc_enabled(dst
, dst_level
))
81 * src: Both texture and SDMA paths need decompression. Use SDMA.
82 * dst: If overwriting the whole texture, discard CMASK and use
83 * SDMA. Otherwise, use the 3D path.
85 if (dst
->cmask_buffer
&& dst
->dirty_level_mask
& (1 << dst_level
)) {
86 /* The CMASK clear is only enabled for the first level. */
87 assert(dst_level
== 0);
88 if (!util_texrange_covers_whole_level(&dst
->buffer
.b
.b
, dst_level
,
89 dstx
, dsty
, dstz
, src_box
->width
,
90 src_box
->height
, src_box
->depth
))
93 si_texture_discard_cmask(sctx
->screen
, dst
);
96 /* All requirements are met. Prepare textures for SDMA. */
97 if (src
->cmask_buffer
&& src
->dirty_level_mask
& (1 << src_level
))
98 sctx
->b
.flush_resource(&sctx
->b
, &src
->buffer
.b
.b
);
100 assert(!(src
->dirty_level_mask
& (1 << src_level
)));
101 assert(!(dst
->dirty_level_mask
& (1 << dst_level
)));
106 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
107 static void si_copy_region_with_blit(struct pipe_context
*pipe
,
108 struct pipe_resource
*dst
,
110 unsigned dstx
, unsigned dsty
, unsigned dstz
,
111 struct pipe_resource
*src
,
113 const struct pipe_box
*src_box
)
115 struct pipe_blit_info blit
;
117 memset(&blit
, 0, sizeof(blit
));
118 blit
.src
.resource
= src
;
119 blit
.src
.format
= src
->format
;
120 blit
.src
.level
= src_level
;
121 blit
.src
.box
= *src_box
;
122 blit
.dst
.resource
= dst
;
123 blit
.dst
.format
= dst
->format
;
124 blit
.dst
.level
= dst_level
;
125 blit
.dst
.box
.x
= dstx
;
126 blit
.dst
.box
.y
= dsty
;
127 blit
.dst
.box
.z
= dstz
;
128 blit
.dst
.box
.width
= src_box
->width
;
129 blit
.dst
.box
.height
= src_box
->height
;
130 blit
.dst
.box
.depth
= src_box
->depth
;
131 blit
.mask
= util_format_get_mask(src
->format
) &
132 util_format_get_mask(dst
->format
);
133 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
136 pipe
->blit(pipe
, &blit
);
140 /* Copy from a full GPU texture to a transfer's staging one. */
141 static void si_copy_to_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
143 struct si_context
*sctx
= (struct si_context
*)ctx
;
144 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
145 struct pipe_resource
*dst
= &stransfer
->staging
->b
.b
;
146 struct pipe_resource
*src
= transfer
->resource
;
148 if (src
->nr_samples
> 1) {
149 si_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
150 src
, transfer
->level
, &transfer
->box
);
154 sctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
158 /* Copy from a transfer's staging texture to a full GPU one. */
159 static void si_copy_from_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
161 struct si_context
*sctx
= (struct si_context
*)ctx
;
162 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
163 struct pipe_resource
*dst
= transfer
->resource
;
164 struct pipe_resource
*src
= &stransfer
->staging
->b
.b
;
165 struct pipe_box sbox
;
167 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
169 if (dst
->nr_samples
> 1) {
170 si_copy_region_with_blit(ctx
, dst
, transfer
->level
,
171 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
176 sctx
->dma_copy(ctx
, dst
, transfer
->level
,
177 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
181 static unsigned si_texture_get_offset(struct si_screen
*sscreen
,
182 struct si_texture
*tex
, unsigned level
,
183 const struct pipe_box
*box
,
185 unsigned *layer_stride
)
187 if (sscreen
->info
.chip_class
>= GFX9
) {
188 *stride
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
189 *layer_stride
= tex
->surface
.u
.gfx9
.surf_slice_size
;
194 /* Each texture is an array of slices. Each slice is an array
195 * of mipmap levels. */
196 return box
->z
* tex
->surface
.u
.gfx9
.surf_slice_size
+
197 tex
->surface
.u
.gfx9
.offset
[level
] +
198 (box
->y
/ tex
->surface
.blk_h
*
199 tex
->surface
.u
.gfx9
.surf_pitch
+
200 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
202 *stride
= tex
->surface
.u
.legacy
.level
[level
].nblk_x
*
204 assert((uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
205 *layer_stride
= (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
208 return tex
->surface
.u
.legacy
.level
[level
].offset
;
210 /* Each texture is an array of mipmap levels. Each level is
211 * an array of slices. */
212 return tex
->surface
.u
.legacy
.level
[level
].offset
+
213 box
->z
* (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
214 (box
->y
/ tex
->surface
.blk_h
*
215 tex
->surface
.u
.legacy
.level
[level
].nblk_x
+
216 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
220 static int si_init_surface(struct si_screen
*sscreen
,
221 struct radeon_surf
*surface
,
222 const struct pipe_resource
*ptex
,
223 enum radeon_surf_mode array_mode
,
224 unsigned pitch_in_bytes_override
,
228 bool is_flushed_depth
,
229 bool tc_compatible_htile
)
231 const struct util_format_description
*desc
=
232 util_format_description(ptex
->format
);
233 bool is_depth
, is_stencil
;
235 unsigned i
, bpe
, flags
= 0;
237 is_depth
= util_format_has_depth(desc
);
238 is_stencil
= util_format_has_stencil(desc
);
240 if (!is_flushed_depth
&&
241 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
242 bpe
= 4; /* stencil is allocated separately */
244 bpe
= util_format_get_blocksize(ptex
->format
);
245 assert(util_is_power_of_two_or_zero(bpe
));
248 if (!is_flushed_depth
&& is_depth
) {
249 flags
|= RADEON_SURF_ZBUFFER
;
251 if (tc_compatible_htile
&&
252 (sscreen
->info
.chip_class
>= GFX9
||
253 array_mode
== RADEON_SURF_MODE_2D
)) {
254 /* TC-compatible HTILE only supports Z32_FLOAT.
255 * GFX9 also supports Z16_UNORM.
256 * On VI, promote Z16 to Z32. DB->CB copies will convert
257 * the format for transfers.
259 if (sscreen
->info
.chip_class
== VI
)
262 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
266 flags
|= RADEON_SURF_SBUFFER
;
269 if (sscreen
->info
.chip_class
>= VI
&&
270 (ptex
->flags
& SI_RESOURCE_FLAG_DISABLE_DCC
||
271 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
272 (ptex
->nr_samples
>= 2 && !sscreen
->dcc_msaa_allowed
)))
273 flags
|= RADEON_SURF_DISABLE_DCC
;
275 /* Stoney: 128bpp MSAA textures randomly fail piglit tests with DCC. */
276 if (sscreen
->info
.family
== CHIP_STONEY
&&
277 bpe
== 16 && ptex
->nr_samples
>= 2)
278 flags
|= RADEON_SURF_DISABLE_DCC
;
280 /* VI: DCC clear for 4x and 8x MSAA array textures unimplemented. */
281 if (sscreen
->info
.chip_class
== VI
&&
282 ptex
->nr_storage_samples
>= 4 &&
283 ptex
->array_size
> 1)
284 flags
|= RADEON_SURF_DISABLE_DCC
;
286 /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
287 if (sscreen
->info
.chip_class
>= GFX9
&&
288 ptex
->nr_storage_samples
>= 4)
289 flags
|= RADEON_SURF_DISABLE_DCC
;
291 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
292 /* This should catch bugs in gallium users setting incorrect flags. */
293 assert(ptex
->nr_samples
<= 1 &&
294 ptex
->array_size
== 1 &&
296 ptex
->last_level
== 0 &&
297 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
299 flags
|= RADEON_SURF_SCANOUT
;
302 if (ptex
->bind
& PIPE_BIND_SHARED
)
303 flags
|= RADEON_SURF_SHAREABLE
;
305 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
306 if (!(ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
))
307 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
309 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, flags
, bpe
,
310 array_mode
, surface
);
315 unsigned pitch
= pitch_in_bytes_override
/ bpe
;
317 if (sscreen
->info
.chip_class
>= GFX9
) {
319 surface
->u
.gfx9
.surf_pitch
= pitch
;
320 surface
->u
.gfx9
.surf_slice_size
=
321 (uint64_t)pitch
* surface
->u
.gfx9
.surf_height
* bpe
;
323 surface
->u
.gfx9
.surf_offset
= offset
;
326 surface
->u
.legacy
.level
[0].nblk_x
= pitch
;
327 surface
->u
.legacy
.level
[0].slice_size_dw
=
328 ((uint64_t)pitch
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
331 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
332 surface
->u
.legacy
.level
[i
].offset
+= offset
;
338 static void si_get_display_metadata(struct si_screen
*sscreen
,
339 struct radeon_surf
*surf
,
340 struct radeon_bo_metadata
*metadata
,
341 enum radeon_surf_mode
*array_mode
,
344 if (sscreen
->info
.chip_class
>= GFX9
) {
345 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
346 *array_mode
= RADEON_SURF_MODE_2D
;
348 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
350 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
351 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
353 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
355 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
356 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
357 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
358 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
359 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
360 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
362 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
363 *array_mode
= RADEON_SURF_MODE_2D
;
364 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
365 *array_mode
= RADEON_SURF_MODE_1D
;
367 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
369 *is_scanout
= metadata
->u
.legacy
.scanout
;
373 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
374 struct si_texture
*tex
)
376 struct si_screen
*sscreen
= sctx
->screen
;
377 struct pipe_context
*ctx
= &sctx
->b
;
379 if (ctx
== sscreen
->aux_context
)
380 mtx_lock(&sscreen
->aux_context_lock
);
382 unsigned n
= sctx
->num_decompress_calls
;
383 ctx
->flush_resource(ctx
, &tex
->buffer
.b
.b
);
385 /* Flush only if any fast clear elimination took place. */
386 if (n
!= sctx
->num_decompress_calls
)
387 ctx
->flush(ctx
, NULL
, 0);
389 if (ctx
== sscreen
->aux_context
)
390 mtx_unlock(&sscreen
->aux_context_lock
);
393 void si_texture_discard_cmask(struct si_screen
*sscreen
,
394 struct si_texture
*tex
)
396 if (!tex
->cmask_buffer
)
399 assert(tex
->buffer
.b
.b
.nr_samples
<= 1);
402 tex
->cmask_base_address_reg
= tex
->buffer
.gpu_address
>> 8;
403 tex
->dirty_level_mask
= 0;
405 tex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
407 if (tex
->cmask_buffer
!= &tex
->buffer
)
408 si_resource_reference(&tex
->cmask_buffer
, NULL
);
410 tex
->cmask_buffer
= NULL
;
412 /* Notify all contexts about the change. */
413 p_atomic_inc(&sscreen
->dirty_tex_counter
);
414 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
417 static bool si_can_disable_dcc(struct si_texture
*tex
)
419 /* We can't disable DCC if it can be written by another process. */
420 return tex
->dcc_offset
&&
421 (!tex
->buffer
.b
.is_shared
||
422 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
));
425 static bool si_texture_discard_dcc(struct si_screen
*sscreen
,
426 struct si_texture
*tex
)
428 if (!si_can_disable_dcc(tex
))
431 assert(tex
->dcc_separate_buffer
== NULL
);
436 /* Notify all contexts about the change. */
437 p_atomic_inc(&sscreen
->dirty_tex_counter
);
442 * Disable DCC for the texture. (first decompress, then discard metadata).
444 * There is unresolved multi-context synchronization issue between
445 * screen::aux_context and the current context. If applications do this with
446 * multiple contexts, it's already undefined behavior for them and we don't
447 * have to worry about that. The scenario is:
449 * If context 1 disables DCC and context 2 has queued commands that write
450 * to the texture via CB with DCC enabled, and the order of operations is
452 * context 2 queues draw calls rendering to the texture, but doesn't flush
453 * context 1 disables DCC and flushes
454 * context 1 & 2 reset descriptors and FB state
455 * context 2 flushes (new compressed tiles written by the draw calls)
456 * context 1 & 2 read garbage, because DCC is disabled, yet there are
459 * \param sctx the current context if you have one, or sscreen->aux_context
462 bool si_texture_disable_dcc(struct si_context
*sctx
,
463 struct si_texture
*tex
)
465 struct si_screen
*sscreen
= sctx
->screen
;
467 if (!si_can_disable_dcc(tex
))
470 if (&sctx
->b
== sscreen
->aux_context
)
471 mtx_lock(&sscreen
->aux_context_lock
);
473 /* Decompress DCC. */
474 si_decompress_dcc(sctx
, tex
);
475 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
477 if (&sctx
->b
== sscreen
->aux_context
)
478 mtx_unlock(&sscreen
->aux_context_lock
);
480 return si_texture_discard_dcc(sscreen
, tex
);
483 static void si_reallocate_texture_inplace(struct si_context
*sctx
,
484 struct si_texture
*tex
,
485 unsigned new_bind_flag
,
486 bool invalidate_storage
)
488 struct pipe_screen
*screen
= sctx
->b
.screen
;
489 struct si_texture
*new_tex
;
490 struct pipe_resource templ
= tex
->buffer
.b
.b
;
493 templ
.bind
|= new_bind_flag
;
495 if (tex
->buffer
.b
.is_shared
)
498 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
499 if (tex
->surface
.is_linear
)
502 /* This fails with MSAA, depth, and compressed textures. */
503 if (si_choose_tiling(sctx
->screen
, &templ
, false) !=
504 RADEON_SURF_MODE_LINEAR_ALIGNED
)
508 new_tex
= (struct si_texture
*)screen
->resource_create(screen
, &templ
);
512 /* Copy the pixels to the new texture. */
513 if (!invalidate_storage
) {
514 for (i
= 0; i
<= templ
.last_level
; i
++) {
518 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
519 util_num_layers(&templ
, i
), &box
);
521 sctx
->dma_copy(&sctx
->b
, &new_tex
->buffer
.b
.b
, i
, 0, 0, 0,
522 &tex
->buffer
.b
.b
, i
, &box
);
526 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
527 si_texture_discard_cmask(sctx
->screen
, tex
);
528 si_texture_discard_dcc(sctx
->screen
, tex
);
531 /* Replace the structure fields of tex. */
532 tex
->buffer
.b
.b
.bind
= templ
.bind
;
533 pb_reference(&tex
->buffer
.buf
, new_tex
->buffer
.buf
);
534 tex
->buffer
.gpu_address
= new_tex
->buffer
.gpu_address
;
535 tex
->buffer
.vram_usage
= new_tex
->buffer
.vram_usage
;
536 tex
->buffer
.gart_usage
= new_tex
->buffer
.gart_usage
;
537 tex
->buffer
.bo_size
= new_tex
->buffer
.bo_size
;
538 tex
->buffer
.bo_alignment
= new_tex
->buffer
.bo_alignment
;
539 tex
->buffer
.domains
= new_tex
->buffer
.domains
;
540 tex
->buffer
.flags
= new_tex
->buffer
.flags
;
542 tex
->surface
= new_tex
->surface
;
543 tex
->size
= new_tex
->size
;
544 si_texture_reference(&tex
->flushed_depth_texture
,
545 new_tex
->flushed_depth_texture
);
547 tex
->fmask_offset
= new_tex
->fmask_offset
;
548 tex
->cmask_offset
= new_tex
->cmask_offset
;
549 tex
->cmask_base_address_reg
= new_tex
->cmask_base_address_reg
;
551 if (tex
->cmask_buffer
== &tex
->buffer
)
552 tex
->cmask_buffer
= NULL
;
554 si_resource_reference(&tex
->cmask_buffer
, NULL
);
556 if (new_tex
->cmask_buffer
== &new_tex
->buffer
)
557 tex
->cmask_buffer
= &tex
->buffer
;
559 si_resource_reference(&tex
->cmask_buffer
, new_tex
->cmask_buffer
);
561 tex
->dcc_offset
= new_tex
->dcc_offset
;
562 tex
->cb_color_info
= new_tex
->cb_color_info
;
563 memcpy(tex
->color_clear_value
, new_tex
->color_clear_value
,
564 sizeof(tex
->color_clear_value
));
565 tex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
567 tex
->htile_offset
= new_tex
->htile_offset
;
568 tex
->depth_clear_value
= new_tex
->depth_clear_value
;
569 tex
->dirty_level_mask
= new_tex
->dirty_level_mask
;
570 tex
->stencil_dirty_level_mask
= new_tex
->stencil_dirty_level_mask
;
571 tex
->db_render_format
= new_tex
->db_render_format
;
572 tex
->stencil_clear_value
= new_tex
->stencil_clear_value
;
573 tex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
574 tex
->depth_cleared
= new_tex
->depth_cleared
;
575 tex
->stencil_cleared
= new_tex
->stencil_cleared
;
576 tex
->upgraded_depth
= new_tex
->upgraded_depth
;
577 tex
->db_compatible
= new_tex
->db_compatible
;
578 tex
->can_sample_z
= new_tex
->can_sample_z
;
579 tex
->can_sample_s
= new_tex
->can_sample_s
;
581 tex
->separate_dcc_dirty
= new_tex
->separate_dcc_dirty
;
582 tex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
583 si_resource_reference(&tex
->dcc_separate_buffer
,
584 new_tex
->dcc_separate_buffer
);
585 si_resource_reference(&tex
->last_dcc_separate_buffer
,
586 new_tex
->last_dcc_separate_buffer
);
588 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
589 assert(!tex
->htile_offset
);
590 assert(!tex
->cmask_buffer
);
591 assert(!tex
->surface
.fmask_size
);
592 assert(!tex
->dcc_offset
);
593 assert(!tex
->is_depth
);
596 si_texture_reference(&new_tex
, NULL
);
598 p_atomic_inc(&sctx
->screen
->dirty_tex_counter
);
601 static uint32_t si_get_bo_metadata_word1(struct si_screen
*sscreen
)
603 return (ATI_VENDOR_ID
<< 16) | sscreen
->info
.pci_id
;
606 static void si_set_tex_bo_metadata(struct si_screen
*sscreen
,
607 struct si_texture
*tex
)
609 struct radeon_surf
*surface
= &tex
->surface
;
610 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
611 struct radeon_bo_metadata md
;
613 memset(&md
, 0, sizeof(md
));
615 if (sscreen
->info
.chip_class
>= GFX9
) {
616 md
.u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
618 md
.u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
619 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
620 md
.u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
621 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
622 md
.u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
623 md
.u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
624 md
.u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
625 md
.u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
626 md
.u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
627 md
.u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
628 md
.u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
629 md
.u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
632 assert(tex
->dcc_separate_buffer
== NULL
);
633 assert(tex
->surface
.fmask_size
== 0);
635 /* Metadata image format format version 1:
636 * [0] = 1 (metadata format identifier)
637 * [1] = (VENDOR_ID << 16) | PCI_ID
638 * [2:9] = image descriptor for the whole resource
639 * [2] is always 0, because the base address is cleared
640 * [9] is the DCC offset bits [39:8] from the beginning of
642 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
645 md
.metadata
[0] = 1; /* metadata image format version 1 */
647 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
648 md
.metadata
[1] = si_get_bo_metadata_word1(sscreen
);
650 static const unsigned char swizzle
[] = {
656 bool is_array
= util_texture_is_array(res
->target
);
659 si_make_texture_descriptor(sscreen
, tex
, true,
660 res
->target
, res
->format
,
661 swizzle
, 0, res
->last_level
, 0,
662 is_array
? res
->array_size
- 1 : 0,
663 res
->width0
, res
->height0
, res
->depth0
,
666 si_set_mutable_tex_desc_fields(sscreen
, tex
, &tex
->surface
.u
.legacy
.level
[0],
667 0, 0, tex
->surface
.blk_w
, false, desc
);
669 /* Clear the base address and set the relative DCC offset. */
671 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
672 desc
[7] = tex
->dcc_offset
>> 8;
674 /* Dwords [2:9] contain the image descriptor. */
675 memcpy(&md
.metadata
[2], desc
, sizeof(desc
));
676 md
.size_metadata
= 10 * 4;
678 /* Dwords [10:..] contain the mipmap level offsets. */
679 if (sscreen
->info
.chip_class
<= VI
) {
680 for (unsigned i
= 0; i
<= res
->last_level
; i
++)
681 md
.metadata
[10+i
] = tex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
683 md
.size_metadata
+= (1 + res
->last_level
) * 4;
686 sscreen
->ws
->buffer_set_metadata(tex
->buffer
.buf
, &md
);
689 static void si_get_opaque_metadata(struct si_screen
*sscreen
,
690 struct si_texture
*tex
,
691 struct radeon_bo_metadata
*md
)
693 uint32_t *desc
= &md
->metadata
[2];
695 if (sscreen
->info
.chip_class
< VI
)
698 /* Return if DCC is enabled. The texture should be set up with it
701 if (md
->size_metadata
>= 10 * 4 && /* at least 2(header) + 8(desc) dwords */
702 md
->metadata
[0] != 0 &&
703 md
->metadata
[1] == si_get_bo_metadata_word1(sscreen
) &&
704 G_008F28_COMPRESSION_EN(desc
[6])) {
705 tex
->dcc_offset
= (uint64_t)desc
[7] << 8;
709 /* Disable DCC. These are always set by texture_from_handle and must
715 static boolean
si_texture_get_handle(struct pipe_screen
* screen
,
716 struct pipe_context
*ctx
,
717 struct pipe_resource
*resource
,
718 struct winsys_handle
*whandle
,
721 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
722 struct si_context
*sctx
;
723 struct si_resource
*res
= si_resource(resource
);
724 struct si_texture
*tex
= (struct si_texture
*)resource
;
725 bool update_metadata
= false;
726 unsigned stride
, offset
, slice_size
;
729 ctx
= threaded_context_unwrap_sync(ctx
);
730 sctx
= (struct si_context
*)(ctx
? ctx
: sscreen
->aux_context
);
732 if (resource
->target
!= PIPE_BUFFER
) {
733 /* This is not supported now, but it might be required for OpenCL
734 * interop in the future.
736 if (resource
->nr_samples
> 1 || tex
->is_depth
)
739 /* Move a suballocated texture into a non-suballocated allocation. */
740 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
741 tex
->surface
.tile_swizzle
||
742 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
743 sscreen
->info
.has_local_buffers
&&
744 whandle
->type
!= WINSYS_HANDLE_TYPE_KMS
)) {
745 assert(!res
->b
.is_shared
);
746 si_reallocate_texture_inplace(sctx
, tex
,
747 PIPE_BIND_SHARED
, false);
749 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
750 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
751 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
752 assert(tex
->surface
.tile_swizzle
== 0);
755 /* Since shader image stores don't support DCC on VI,
756 * disable it for external clients that want write
759 if (usage
& PIPE_HANDLE_USAGE_SHADER_WRITE
&& tex
->dcc_offset
) {
760 if (si_texture_disable_dcc(sctx
, tex
)) {
761 update_metadata
= true;
762 /* si_texture_disable_dcc flushes the context */
767 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
768 (tex
->cmask_buffer
|| tex
->dcc_offset
)) {
769 /* Eliminate fast clear (both CMASK and DCC) */
770 si_eliminate_fast_color_clear(sctx
, tex
);
771 /* eliminate_fast_color_clear flushes the context */
774 /* Disable CMASK if flush_resource isn't going
777 if (tex
->cmask_buffer
)
778 si_texture_discard_cmask(sscreen
, tex
);
782 if (!res
->b
.is_shared
|| update_metadata
)
783 si_set_tex_bo_metadata(sscreen
, tex
);
785 if (sscreen
->info
.chip_class
>= GFX9
) {
786 offset
= tex
->surface
.u
.gfx9
.surf_offset
;
787 stride
= tex
->surface
.u
.gfx9
.surf_pitch
*
789 slice_size
= tex
->surface
.u
.gfx9
.surf_slice_size
;
791 offset
= tex
->surface
.u
.legacy
.level
[0].offset
;
792 stride
= tex
->surface
.u
.legacy
.level
[0].nblk_x
*
794 slice_size
= (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
797 /* Buffer exports are for the OpenCL interop. */
798 /* Move a suballocated buffer into a non-suballocated allocation. */
799 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
800 /* A DMABUF export always fails if the BO is local. */
801 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
802 sscreen
->info
.has_local_buffers
)) {
803 assert(!res
->b
.is_shared
);
805 /* Allocate a new buffer with PIPE_BIND_SHARED. */
806 struct pipe_resource templ
= res
->b
.b
;
807 templ
.bind
|= PIPE_BIND_SHARED
;
809 struct pipe_resource
*newb
=
810 screen
->resource_create(screen
, &templ
);
814 /* Copy the old buffer contents to the new one. */
816 u_box_1d(0, newb
->width0
, &box
);
817 sctx
->b
.resource_copy_region(&sctx
->b
, newb
, 0, 0, 0, 0,
820 /* Move the new buffer storage to the old pipe_resource. */
821 si_replace_buffer_storage(&sctx
->b
, &res
->b
.b
, newb
);
822 pipe_resource_reference(&newb
, NULL
);
824 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
825 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
835 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
837 if (res
->b
.is_shared
) {
838 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
841 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
842 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
843 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
845 res
->b
.is_shared
= true;
846 res
->external_usage
= usage
;
849 return sscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
850 slice_size
, whandle
);
853 static void si_texture_destroy(struct pipe_screen
*screen
,
854 struct pipe_resource
*ptex
)
856 struct si_texture
*tex
= (struct si_texture
*)ptex
;
857 struct si_resource
*resource
= &tex
->buffer
;
859 si_texture_reference(&tex
->flushed_depth_texture
, NULL
);
861 if (tex
->cmask_buffer
!= &tex
->buffer
) {
862 si_resource_reference(&tex
->cmask_buffer
, NULL
);
864 pb_reference(&resource
->buf
, NULL
);
865 si_resource_reference(&tex
->dcc_separate_buffer
, NULL
);
866 si_resource_reference(&tex
->last_dcc_separate_buffer
, NULL
);
870 static const struct u_resource_vtbl si_texture_vtbl
;
872 static void si_texture_get_htile_size(struct si_screen
*sscreen
,
873 struct si_texture
*tex
)
875 unsigned cl_width
, cl_height
, width
, height
;
876 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
877 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
879 assert(sscreen
->info
.chip_class
<= VI
);
881 tex
->surface
.htile_size
= 0;
883 if (tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
884 !sscreen
->info
.htile_cmask_support_1d_tiling
)
887 /* Overalign HTILE on P2 configs to work around GPU hangs in
888 * piglit/depthstencil-render-miplevels 585.
890 * This has been confirmed to help Kabini & Stoney, where the hangs
891 * are always reproducible. I think I have seen the test hang
892 * on Carrizo too, though it was very rare there.
894 if (sscreen
->info
.chip_class
>= CIK
&& num_pipes
< 4)
923 width
= align(tex
->surface
.u
.legacy
.level
[0].nblk_x
, cl_width
* 8);
924 height
= align(tex
->surface
.u
.legacy
.level
[0].nblk_y
, cl_height
* 8);
926 slice_elements
= (width
* height
) / (8 * 8);
927 slice_bytes
= slice_elements
* 4;
929 pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
930 base_align
= num_pipes
* pipe_interleave_bytes
;
932 tex
->surface
.htile_alignment
= base_align
;
933 tex
->surface
.htile_size
=
934 util_num_layers(&tex
->buffer
.b
.b
, 0) *
935 align(slice_bytes
, base_align
);
938 static void si_texture_allocate_htile(struct si_screen
*sscreen
,
939 struct si_texture
*tex
)
941 if (sscreen
->info
.chip_class
<= VI
&& !tex
->tc_compatible_htile
)
942 si_texture_get_htile_size(sscreen
, tex
);
944 if (!tex
->surface
.htile_size
)
947 tex
->htile_offset
= align(tex
->size
, tex
->surface
.htile_alignment
);
948 tex
->size
= tex
->htile_offset
+ tex
->surface
.htile_size
;
951 void si_print_texture_info(struct si_screen
*sscreen
,
952 struct si_texture
*tex
, struct u_log_context
*log
)
956 /* Common parameters. */
957 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
958 "blk_h=%u, array_size=%u, last_level=%u, "
959 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
960 tex
->buffer
.b
.b
.width0
, tex
->buffer
.b
.b
.height0
,
961 tex
->buffer
.b
.b
.depth0
, tex
->surface
.blk_w
,
963 tex
->buffer
.b
.b
.array_size
, tex
->buffer
.b
.b
.last_level
,
964 tex
->surface
.bpe
, tex
->buffer
.b
.b
.nr_samples
,
965 tex
->surface
.flags
, util_format_short_name(tex
->buffer
.b
.b
.format
));
967 if (sscreen
->info
.chip_class
>= GFX9
) {
968 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
969 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
970 tex
->surface
.surf_size
,
971 tex
->surface
.u
.gfx9
.surf_slice_size
,
972 tex
->surface
.surf_alignment
,
973 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
974 tex
->surface
.u
.gfx9
.surf
.epitch
,
975 tex
->surface
.u
.gfx9
.surf_pitch
);
977 if (tex
->surface
.fmask_size
) {
978 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
979 "alignment=%u, swmode=%u, epitch=%u\n",
981 tex
->surface
.fmask_size
,
982 tex
->surface
.fmask_alignment
,
983 tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
984 tex
->surface
.u
.gfx9
.fmask
.epitch
);
987 if (tex
->cmask_buffer
) {
988 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%u, "
989 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
991 tex
->surface
.cmask_size
,
992 tex
->surface
.cmask_alignment
,
993 tex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
994 tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
997 if (tex
->htile_offset
) {
998 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, alignment=%u, "
999 "rb_aligned=%u, pipe_aligned=%u\n",
1001 tex
->surface
.htile_size
,
1002 tex
->surface
.htile_alignment
,
1003 tex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1004 tex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1007 if (tex
->dcc_offset
) {
1008 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, "
1009 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1010 tex
->dcc_offset
, tex
->surface
.dcc_size
,
1011 tex
->surface
.dcc_alignment
,
1012 tex
->surface
.u
.gfx9
.dcc_pitch_max
,
1013 tex
->surface
.num_dcc_levels
);
1016 if (tex
->surface
.u
.gfx9
.stencil_offset
) {
1017 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1018 tex
->surface
.u
.gfx9
.stencil_offset
,
1019 tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1020 tex
->surface
.u
.gfx9
.stencil
.epitch
);
1025 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1026 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1027 tex
->surface
.surf_size
, tex
->surface
.surf_alignment
, tex
->surface
.u
.legacy
.bankw
,
1028 tex
->surface
.u
.legacy
.bankh
, tex
->surface
.u
.legacy
.num_banks
, tex
->surface
.u
.legacy
.mtilea
,
1029 tex
->surface
.u
.legacy
.tile_split
, tex
->surface
.u
.legacy
.pipe_config
,
1030 (tex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1032 if (tex
->surface
.fmask_size
)
1033 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1034 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1035 tex
->fmask_offset
, tex
->surface
.fmask_size
, tex
->surface
.fmask_alignment
,
1036 tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
,
1037 tex
->surface
.u
.legacy
.fmask
.bankh
,
1038 tex
->surface
.u
.legacy
.fmask
.slice_tile_max
,
1039 tex
->surface
.u
.legacy
.fmask
.tiling_index
);
1041 if (tex
->cmask_buffer
)
1042 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%u, alignment=%u, "
1043 "slice_tile_max=%u\n",
1044 tex
->cmask_offset
, tex
->surface
.cmask_size
, tex
->surface
.cmask_alignment
,
1045 tex
->surface
.u
.legacy
.cmask_slice_tile_max
);
1047 if (tex
->htile_offset
)
1048 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, "
1049 "alignment=%u, TC_compatible = %u\n",
1050 tex
->htile_offset
, tex
->surface
.htile_size
,
1051 tex
->surface
.htile_alignment
,
1052 tex
->tc_compatible_htile
);
1054 if (tex
->dcc_offset
) {
1055 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, alignment=%u\n",
1056 tex
->dcc_offset
, tex
->surface
.dcc_size
,
1057 tex
->surface
.dcc_alignment
);
1058 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1059 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%u, "
1060 "fast_clear_size=%u\n",
1061 i
, i
< tex
->surface
.num_dcc_levels
,
1062 tex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1063 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1066 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1067 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1068 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1069 "mode=%u, tiling_index = %u\n",
1070 i
, tex
->surface
.u
.legacy
.level
[i
].offset
,
1071 (uint64_t)tex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
1072 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1073 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1074 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1075 tex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1076 tex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1077 tex
->surface
.u
.legacy
.level
[i
].mode
,
1078 tex
->surface
.u
.legacy
.tiling_index
[i
]);
1080 if (tex
->surface
.has_stencil
) {
1081 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1082 tex
->surface
.u
.legacy
.stencil_tile_split
);
1083 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++) {
1084 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1085 "slice_size=%"PRIu64
", npix_x=%u, "
1086 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1087 "mode=%u, tiling_index = %u\n",
1088 i
, tex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1089 (uint64_t)tex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
1090 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1091 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1092 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1093 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1094 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1095 tex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1096 tex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1101 /* Common processing for si_texture_create and si_texture_from_handle */
1102 static struct si_texture
*
1103 si_texture_create_object(struct pipe_screen
*screen
,
1104 const struct pipe_resource
*base
,
1105 struct pb_buffer
*buf
,
1106 struct radeon_surf
*surface
)
1108 struct si_texture
*tex
;
1109 struct si_resource
*resource
;
1110 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1112 tex
= CALLOC_STRUCT(si_texture
);
1116 resource
= &tex
->buffer
;
1117 resource
->b
.b
= *base
;
1118 resource
->b
.b
.next
= NULL
;
1119 resource
->b
.vtbl
= &si_texture_vtbl
;
1120 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1121 resource
->b
.b
.screen
= screen
;
1123 /* don't include stencil-only formats which we don't support for rendering */
1124 tex
->is_depth
= util_format_has_depth(util_format_description(tex
->buffer
.b
.b
.format
));
1126 tex
->surface
= *surface
;
1127 tex
->size
= tex
->surface
.surf_size
;
1129 tex
->tc_compatible_htile
= tex
->surface
.htile_size
!= 0 &&
1130 (tex
->surface
.flags
&
1131 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1133 /* TC-compatible HTILE:
1134 * - VI only supports Z32_FLOAT.
1135 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1136 if (tex
->tc_compatible_htile
) {
1137 if (sscreen
->info
.chip_class
>= GFX9
&&
1138 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1139 tex
->db_render_format
= base
->format
;
1141 tex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1142 tex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1143 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1146 tex
->db_render_format
= base
->format
;
1149 /* Applies to GCN. */
1150 tex
->last_msaa_resolve_target_micro_mode
= tex
->surface
.micro_tile_mode
;
1152 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1153 * between frames, so the only thing that can enable separate DCC
1154 * with DRI2 is multiple slow clears within a frame.
1156 tex
->ps_draw_ratio
= 0;
1158 if (tex
->is_depth
) {
1159 if (sscreen
->info
.chip_class
>= GFX9
) {
1160 tex
->can_sample_z
= true;
1161 tex
->can_sample_s
= true;
1163 tex
->can_sample_z
= !tex
->surface
.u
.legacy
.depth_adjusted
;
1164 tex
->can_sample_s
= !tex
->surface
.u
.legacy
.stencil_adjusted
;
1167 if (!(base
->flags
& (SI_RESOURCE_FLAG_TRANSFER
|
1168 SI_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1169 tex
->db_compatible
= true;
1171 if (!(sscreen
->debug_flags
& DBG(NO_HYPERZ
)))
1172 si_texture_allocate_htile(sscreen
, tex
);
1175 if (base
->nr_samples
> 1 &&
1177 !(sscreen
->debug_flags
& DBG(NO_FMASK
))) {
1178 /* Allocate FMASK. */
1179 tex
->fmask_offset
= align64(tex
->size
,
1180 tex
->surface
.fmask_alignment
);
1181 tex
->size
= tex
->fmask_offset
+ tex
->surface
.fmask_size
;
1183 /* Allocate CMASK. */
1184 tex
->cmask_offset
= align64(tex
->size
, tex
->surface
.cmask_alignment
);
1185 tex
->size
= tex
->cmask_offset
+ tex
->surface
.cmask_size
;
1186 tex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
1187 tex
->cmask_buffer
= &tex
->buffer
;
1189 if (!tex
->surface
.fmask_size
|| !tex
->surface
.cmask_size
) {
1195 /* Shared textures must always set up DCC here.
1196 * If it's not present, it will be disabled by
1197 * apply_opaque_metadata later.
1199 if (tex
->surface
.dcc_size
&&
1200 (buf
|| !(sscreen
->debug_flags
& DBG(NO_DCC
))) &&
1201 !(tex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1202 /* Reserve space for the DCC buffer. */
1203 tex
->dcc_offset
= align64(tex
->size
, tex
->surface
.dcc_alignment
);
1204 tex
->size
= tex
->dcc_offset
+ tex
->surface
.dcc_size
;
1208 /* Now create the backing buffer. */
1210 si_init_resource_fields(sscreen
, resource
, tex
->size
,
1211 tex
->surface
.surf_alignment
);
1213 if (!si_alloc_resource(sscreen
, resource
)) {
1218 resource
->buf
= buf
;
1219 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1220 resource
->bo_size
= buf
->size
;
1221 resource
->bo_alignment
= buf
->alignment
;
1222 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1223 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1224 resource
->vram_usage
= buf
->size
;
1225 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1226 resource
->gart_usage
= buf
->size
;
1229 if (tex
->cmask_buffer
) {
1230 /* Initialize the cmask to 0xCC (= compressed state). */
1231 si_screen_clear_buffer(sscreen
, &tex
->cmask_buffer
->b
.b
,
1232 tex
->cmask_offset
, tex
->surface
.cmask_size
,
1235 if (tex
->htile_offset
) {
1236 uint32_t clear_value
= 0;
1238 if (sscreen
->info
.chip_class
>= GFX9
|| tex
->tc_compatible_htile
)
1239 clear_value
= 0x0000030F;
1241 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1243 tex
->surface
.htile_size
,
1247 /* Initialize DCC only if the texture is not being imported. */
1248 if (!buf
&& tex
->dcc_offset
) {
1249 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1251 tex
->surface
.dcc_size
,
1255 /* Initialize the CMASK base register value. */
1256 tex
->cmask_base_address_reg
=
1257 (tex
->buffer
.gpu_address
+ tex
->cmask_offset
) >> 8;
1259 if (sscreen
->debug_flags
& DBG(VM
)) {
1260 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1261 tex
->buffer
.gpu_address
,
1262 tex
->buffer
.gpu_address
+ tex
->buffer
.buf
->size
,
1263 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+1,
1264 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1267 if (sscreen
->debug_flags
& DBG(TEX
)) {
1269 struct u_log_context log
;
1270 u_log_context_init(&log
);
1271 si_print_texture_info(sscreen
, tex
, &log
);
1272 u_log_new_page_print(&log
, stdout
);
1274 u_log_context_destroy(&log
);
1280 static enum radeon_surf_mode
1281 si_choose_tiling(struct si_screen
*sscreen
,
1282 const struct pipe_resource
*templ
, bool tc_compatible_htile
)
1284 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1285 bool force_tiling
= templ
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
;
1286 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1287 !(templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
);
1289 /* MSAA resources must be 2D tiled. */
1290 if (templ
->nr_samples
> 1)
1291 return RADEON_SURF_MODE_2D
;
1293 /* Transfer resources should be linear. */
1294 if (templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
)
1295 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1297 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
1298 * which requires 2D tiling.
1300 if (sscreen
->info
.chip_class
== VI
&& tc_compatible_htile
)
1301 return RADEON_SURF_MODE_2D
;
1303 /* Handle common candidates for the linear mode.
1304 * Compressed textures and DB surfaces must always be tiled.
1306 if (!force_tiling
&&
1307 !is_depth_stencil
&&
1308 !util_format_is_compressed(templ
->format
)) {
1309 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1310 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1312 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. */
1313 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1314 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1316 /* Cursors are linear on SI.
1317 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1318 if (templ
->bind
& PIPE_BIND_CURSOR
)
1319 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1321 if (templ
->bind
& PIPE_BIND_LINEAR
)
1322 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1324 /* Textures with a very small height are recommended to be linear. */
1325 if (templ
->target
== PIPE_TEXTURE_1D
||
1326 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1327 /* Only very thin and long 2D textures should benefit from
1328 * linear_aligned. */
1329 (templ
->width0
> 8 && templ
->height0
<= 2))
1330 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1332 /* Textures likely to be mapped often. */
1333 if (templ
->usage
== PIPE_USAGE_STAGING
||
1334 templ
->usage
== PIPE_USAGE_STREAM
)
1335 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1338 /* Make small textures 1D tiled. */
1339 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1340 (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1341 return RADEON_SURF_MODE_1D
;
1343 /* The allocator will switch to 1D if needed. */
1344 return RADEON_SURF_MODE_2D
;
1347 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1348 const struct pipe_resource
*templ
)
1350 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1351 bool is_zs
= util_format_is_depth_or_stencil(templ
->format
);
1353 if (templ
->nr_samples
>= 2) {
1354 /* This is hackish (overwriting the const pipe_resource template),
1355 * but should be harmless and state trackers can also see
1356 * the overriden number of samples in the created pipe_resource.
1358 if (is_zs
&& sscreen
->eqaa_force_z_samples
) {
1359 ((struct pipe_resource
*)templ
)->nr_samples
=
1360 ((struct pipe_resource
*)templ
)->nr_storage_samples
=
1361 sscreen
->eqaa_force_z_samples
;
1362 } else if (!is_zs
&& sscreen
->eqaa_force_color_samples
) {
1363 ((struct pipe_resource
*)templ
)->nr_samples
=
1364 sscreen
->eqaa_force_coverage_samples
;
1365 ((struct pipe_resource
*)templ
)->nr_storage_samples
=
1366 sscreen
->eqaa_force_color_samples
;
1370 struct radeon_surf surface
= {0};
1371 bool is_flushed_depth
= templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1372 bool tc_compatible_htile
=
1373 sscreen
->info
.chip_class
>= VI
&&
1374 /* There are issues with TC-compatible HTILE on Tonga (and
1375 * Iceland is the same design), and documented bug workarounds
1376 * don't help. For example, this fails:
1377 * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow -auto
1379 sscreen
->info
.family
!= CHIP_TONGA
&&
1380 sscreen
->info
.family
!= CHIP_ICELAND
&&
1381 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1382 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) &&
1383 !is_flushed_depth
&&
1384 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1388 r
= si_init_surface(sscreen
, &surface
, templ
,
1389 si_choose_tiling(sscreen
, templ
, tc_compatible_htile
),
1390 0, 0, false, false, is_flushed_depth
,
1391 tc_compatible_htile
);
1396 return (struct pipe_resource
*)
1397 si_texture_create_object(screen
, templ
, NULL
, &surface
);
1400 static struct pipe_resource
*si_texture_from_winsys_buffer(struct si_screen
*sscreen
,
1401 const struct pipe_resource
*templ
,
1402 struct pb_buffer
*buf
,
1408 enum radeon_surf_mode array_mode
;
1409 struct radeon_surf surface
= {};
1410 struct radeon_bo_metadata metadata
= {};
1411 struct si_texture
*tex
;
1416 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1417 si_get_display_metadata(sscreen
, &surface
, &metadata
,
1418 &array_mode
, &is_scanout
);
1421 * The bo metadata is unset for un-dedicated images. So we fall
1422 * back to linear. See answer to question 5 of the
1423 * VK_KHX_external_memory spec for some details.
1425 * It is possible that this case isn't going to work if the
1426 * surface pitch isn't correctly aligned by default.
1428 * In order to support it correctly we require multi-image
1429 * metadata to be syncrhonized between radv and radeonsi. The
1430 * semantics of associating multiple image metadata to a memory
1431 * object on the vulkan export side are not concretely defined
1434 * All the use cases we are aware of at the moment for memory
1435 * objects use dedicated allocations. So lets keep the initial
1436 * implementation simple.
1438 * A possible alternative is to attempt to reconstruct the
1439 * tiling information when the TexParameter TEXTURE_TILING_EXT
1442 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1446 r
= si_init_surface(sscreen
, &surface
, templ
,
1447 array_mode
, stride
, offset
, true, is_scanout
,
1452 tex
= si_texture_create_object(&sscreen
->b
, templ
, buf
, &surface
);
1456 tex
->buffer
.b
.is_shared
= true;
1457 tex
->buffer
.external_usage
= usage
;
1459 si_get_opaque_metadata(sscreen
, tex
, &metadata
);
1461 assert(tex
->surface
.tile_swizzle
== 0);
1462 return &tex
->buffer
.b
.b
;
1465 static struct pipe_resource
*si_texture_from_handle(struct pipe_screen
*screen
,
1466 const struct pipe_resource
*templ
,
1467 struct winsys_handle
*whandle
,
1470 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1471 struct pb_buffer
*buf
= NULL
;
1472 unsigned stride
= 0, offset
= 0;
1474 /* Support only 2D textures without mipmaps */
1475 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1476 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1479 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
1480 sscreen
->info
.max_alignment
,
1485 return si_texture_from_winsys_buffer(sscreen
, templ
, buf
, stride
,
1486 offset
, usage
, true);
1489 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1490 struct pipe_resource
*texture
,
1491 struct si_texture
**staging
)
1493 struct si_texture
*tex
= (struct si_texture
*)texture
;
1494 struct pipe_resource resource
;
1495 struct si_texture
**flushed_depth_texture
= staging
?
1496 staging
: &tex
->flushed_depth_texture
;
1497 enum pipe_format pipe_format
= texture
->format
;
1500 if (tex
->flushed_depth_texture
)
1501 return true; /* it's ready */
1503 if (!tex
->can_sample_z
&& tex
->can_sample_s
) {
1504 switch (pipe_format
) {
1505 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1506 /* Save memory by not allocating the S plane. */
1507 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1509 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1510 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1511 /* Save memory bandwidth by not copying the
1512 * stencil part during flush.
1514 * This potentially increases memory bandwidth
1515 * if an application uses both Z and S texturing
1516 * simultaneously (a flushed Z24S8 texture
1517 * would be stored compactly), but how often
1518 * does that really happen?
1520 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1524 } else if (!tex
->can_sample_s
&& tex
->can_sample_z
) {
1525 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1527 /* DB->CB copies to an 8bpp surface don't work. */
1528 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1532 memset(&resource
, 0, sizeof(resource
));
1533 resource
.target
= texture
->target
;
1534 resource
.format
= pipe_format
;
1535 resource
.width0
= texture
->width0
;
1536 resource
.height0
= texture
->height0
;
1537 resource
.depth0
= texture
->depth0
;
1538 resource
.array_size
= texture
->array_size
;
1539 resource
.last_level
= texture
->last_level
;
1540 resource
.nr_samples
= texture
->nr_samples
;
1541 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1542 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1543 resource
.flags
= texture
->flags
| SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1546 resource
.flags
|= SI_RESOURCE_FLAG_TRANSFER
;
1548 *flushed_depth_texture
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1549 if (*flushed_depth_texture
== NULL
) {
1550 PRINT_ERR("failed to create temporary texture to hold flushed depth\n");
1557 * Initialize the pipe_resource descriptor to be of the same size as the box,
1558 * which is supposed to hold a subregion of the texture "orig" at the given
1561 static void si_init_temp_resource_from_box(struct pipe_resource
*res
,
1562 struct pipe_resource
*orig
,
1563 const struct pipe_box
*box
,
1564 unsigned level
, unsigned flags
)
1566 memset(res
, 0, sizeof(*res
));
1567 res
->format
= orig
->format
;
1568 res
->width0
= box
->width
;
1569 res
->height0
= box
->height
;
1571 res
->array_size
= 1;
1572 res
->usage
= flags
& SI_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1575 /* We must set the correct texture target and dimensions for a 3D box. */
1576 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1577 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1578 res
->array_size
= box
->depth
;
1580 res
->target
= PIPE_TEXTURE_2D
;
1584 static bool si_can_invalidate_texture(struct si_screen
*sscreen
,
1585 struct si_texture
*tex
,
1586 unsigned transfer_usage
,
1587 const struct pipe_box
*box
)
1589 return !tex
->buffer
.b
.is_shared
&&
1590 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1591 tex
->buffer
.b
.b
.last_level
== 0 &&
1592 util_texrange_covers_whole_level(&tex
->buffer
.b
.b
, 0,
1593 box
->x
, box
->y
, box
->z
,
1594 box
->width
, box
->height
,
1598 static void si_texture_invalidate_storage(struct si_context
*sctx
,
1599 struct si_texture
*tex
)
1601 struct si_screen
*sscreen
= sctx
->screen
;
1603 /* There is no point in discarding depth and tiled buffers. */
1604 assert(!tex
->is_depth
);
1605 assert(tex
->surface
.is_linear
);
1607 /* Reallocate the buffer in the same pipe_resource. */
1608 si_alloc_resource(sscreen
, &tex
->buffer
);
1610 /* Initialize the CMASK base address (needed even without CMASK). */
1611 tex
->cmask_base_address_reg
=
1612 (tex
->buffer
.gpu_address
+ tex
->cmask_offset
) >> 8;
1614 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1616 sctx
->num_alloc_tex_transfer_bytes
+= tex
->size
;
1619 static void *si_texture_transfer_map(struct pipe_context
*ctx
,
1620 struct pipe_resource
*texture
,
1623 const struct pipe_box
*box
,
1624 struct pipe_transfer
**ptransfer
)
1626 struct si_context
*sctx
= (struct si_context
*)ctx
;
1627 struct si_texture
*tex
= (struct si_texture
*)texture
;
1628 struct si_transfer
*trans
;
1629 struct si_resource
*buf
;
1630 unsigned offset
= 0;
1632 bool use_staging_texture
= false;
1634 assert(!(texture
->flags
& SI_RESOURCE_FLAG_TRANSFER
));
1635 assert(box
->width
&& box
->height
&& box
->depth
);
1637 /* Depth textures use staging unconditionally. */
1638 if (!tex
->is_depth
) {
1639 /* Degrade the tile mode if we get too many transfers on APUs.
1640 * On dGPUs, the staging texture is always faster.
1641 * Only count uploads that are at least 4x4 pixels large.
1643 if (!sctx
->screen
->info
.has_dedicated_vram
&&
1645 box
->width
>= 4 && box
->height
>= 4 &&
1646 p_atomic_inc_return(&tex
->num_level0_transfers
) == 10) {
1647 bool can_invalidate
=
1648 si_can_invalidate_texture(sctx
->screen
, tex
,
1651 si_reallocate_texture_inplace(sctx
, tex
,
1656 /* Tiled textures need to be converted into a linear texture for CPU
1657 * access. The staging texture is always linear and is placed in GART.
1659 * Reading from VRAM or GTT WC is slow, always use the staging
1660 * texture in this case.
1662 * Use the staging texture for uploads if the underlying BO
1665 if (!tex
->surface
.is_linear
)
1666 use_staging_texture
= true;
1667 else if (usage
& PIPE_TRANSFER_READ
)
1668 use_staging_texture
=
1669 tex
->buffer
.domains
& RADEON_DOMAIN_VRAM
||
1670 tex
->buffer
.flags
& RADEON_FLAG_GTT_WC
;
1671 /* Write & linear only: */
1672 else if (si_rings_is_buffer_referenced(sctx
, tex
->buffer
.buf
,
1673 RADEON_USAGE_READWRITE
) ||
1674 !sctx
->ws
->buffer_wait(tex
->buffer
.buf
, 0,
1675 RADEON_USAGE_READWRITE
)) {
1677 if (si_can_invalidate_texture(sctx
->screen
, tex
,
1679 si_texture_invalidate_storage(sctx
, tex
);
1681 use_staging_texture
= true;
1685 trans
= CALLOC_STRUCT(si_transfer
);
1688 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1689 trans
->b
.b
.level
= level
;
1690 trans
->b
.b
.usage
= usage
;
1691 trans
->b
.b
.box
= *box
;
1693 if (tex
->is_depth
) {
1694 struct si_texture
*staging_depth
;
1696 if (tex
->buffer
.b
.b
.nr_samples
> 1) {
1697 /* MSAA depth buffers need to be converted to single sample buffers.
1699 * Mapping MSAA depth buffers can occur if ReadPixels is called
1700 * with a multisample GLX visual.
1702 * First downsample the depth buffer to a temporary texture,
1703 * then decompress the temporary one to staging.
1705 * Only the region being mapped is transfered.
1707 struct pipe_resource resource
;
1709 si_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1711 if (!si_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1712 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1716 if (usage
& PIPE_TRANSFER_READ
) {
1717 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1719 PRINT_ERR("failed to create a temporary depth texture\n");
1723 si_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1724 si_blit_decompress_depth(ctx
, (struct si_texture
*)temp
, staging_depth
,
1725 0, 0, 0, box
->depth
, 0, 0);
1726 pipe_resource_reference(&temp
, NULL
);
1729 /* Just get the strides. */
1730 si_texture_get_offset(sctx
->screen
, staging_depth
, level
, NULL
,
1732 &trans
->b
.b
.layer_stride
);
1734 /* XXX: only readback the rectangle which is being mapped? */
1735 /* XXX: when discard is true, no need to read back from depth texture */
1736 if (!si_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1737 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1741 si_blit_decompress_depth(ctx
, tex
, staging_depth
,
1743 box
->z
, box
->z
+ box
->depth
- 1,
1746 offset
= si_texture_get_offset(sctx
->screen
, staging_depth
,
1749 &trans
->b
.b
.layer_stride
);
1752 trans
->staging
= &staging_depth
->buffer
;
1753 buf
= trans
->staging
;
1754 } else if (use_staging_texture
) {
1755 struct pipe_resource resource
;
1756 struct si_texture
*staging
;
1758 si_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1759 SI_RESOURCE_FLAG_TRANSFER
);
1760 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1761 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1763 /* Create the temporary texture. */
1764 staging
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1766 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1769 trans
->staging
= &staging
->buffer
;
1771 /* Just get the strides. */
1772 si_texture_get_offset(sctx
->screen
, staging
, 0, NULL
,
1774 &trans
->b
.b
.layer_stride
);
1776 if (usage
& PIPE_TRANSFER_READ
)
1777 si_copy_to_staging_texture(ctx
, trans
);
1779 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1781 buf
= trans
->staging
;
1783 /* the resource is mapped directly */
1784 offset
= si_texture_get_offset(sctx
->screen
, tex
, level
, box
,
1786 &trans
->b
.b
.layer_stride
);
1790 /* Always unmap texture CPU mappings on 32-bit architectures, so that
1791 * we don't run out of the CPU address space.
1793 if (sizeof(void*) == 4)
1794 usage
|= RADEON_TRANSFER_TEMPORARY
;
1796 if (!(map
= si_buffer_map_sync_with_rings(sctx
, buf
, usage
)))
1799 *ptransfer
= &trans
->b
.b
;
1800 return map
+ offset
;
1803 si_resource_reference(&trans
->staging
, NULL
);
1804 pipe_resource_reference(&trans
->b
.b
.resource
, NULL
);
1809 static void si_texture_transfer_unmap(struct pipe_context
*ctx
,
1810 struct pipe_transfer
* transfer
)
1812 struct si_context
*sctx
= (struct si_context
*)ctx
;
1813 struct si_transfer
*stransfer
= (struct si_transfer
*)transfer
;
1814 struct pipe_resource
*texture
= transfer
->resource
;
1815 struct si_texture
*tex
= (struct si_texture
*)texture
;
1817 /* Always unmap texture CPU mappings on 32-bit architectures, so that
1818 * we don't run out of the CPU address space.
1820 if (sizeof(void*) == 4) {
1821 struct si_resource
*buf
=
1822 stransfer
->staging
? stransfer
->staging
: &tex
->buffer
;
1824 sctx
->ws
->buffer_unmap(buf
->buf
);
1827 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && stransfer
->staging
) {
1828 if (tex
->is_depth
&& tex
->buffer
.b
.b
.nr_samples
<= 1) {
1829 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1830 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1831 &stransfer
->staging
->b
.b
, transfer
->level
,
1834 si_copy_from_staging_texture(ctx
, stransfer
);
1838 if (stransfer
->staging
) {
1839 sctx
->num_alloc_tex_transfer_bytes
+= stransfer
->staging
->buf
->size
;
1840 si_resource_reference(&stransfer
->staging
, NULL
);
1843 /* Heuristic for {upload, draw, upload, draw, ..}:
1845 * Flush the gfx IB if we've allocated too much texture storage.
1847 * The idea is that we don't want to build IBs that use too much
1848 * memory and put pressure on the kernel memory manager and we also
1849 * want to make temporary and invalidated buffers go idle ASAP to
1850 * decrease the total memory usage or make them reusable. The memory
1851 * usage will be slightly higher than given here because of the buffer
1852 * cache in the winsys.
1854 * The result is that the kernel memory manager is never a bottleneck.
1856 if (sctx
->num_alloc_tex_transfer_bytes
> sctx
->screen
->info
.gart_size
/ 4) {
1857 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1858 sctx
->num_alloc_tex_transfer_bytes
= 0;
1861 pipe_resource_reference(&transfer
->resource
, NULL
);
1865 static const struct u_resource_vtbl si_texture_vtbl
=
1867 NULL
, /* get_handle */
1868 si_texture_destroy
, /* resource_destroy */
1869 si_texture_transfer_map
, /* transfer_map */
1870 u_default_transfer_flush_region
, /* transfer_flush_region */
1871 si_texture_transfer_unmap
, /* transfer_unmap */
1874 /* Return if it's allowed to reinterpret one format as another with DCC enabled.
1876 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1877 enum pipe_format format2
)
1879 const struct util_format_description
*desc1
, *desc2
;
1881 /* No format change - exit early. */
1882 if (format1
== format2
)
1885 format1
= si_simplify_cb_format(format1
);
1886 format2
= si_simplify_cb_format(format2
);
1888 /* Check again after format adjustments. */
1889 if (format1
== format2
)
1892 desc1
= util_format_description(format1
);
1893 desc2
= util_format_description(format2
);
1895 if (desc1
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
1896 desc2
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1899 /* Float and non-float are totally incompatible. */
1900 if ((desc1
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
) !=
1901 (desc2
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
))
1904 /* Channel sizes must match across DCC formats.
1905 * Comparing just the first 2 channels should be enough.
1907 if (desc1
->channel
[0].size
!= desc2
->channel
[0].size
||
1908 (desc1
->nr_channels
>= 2 &&
1909 desc1
->channel
[1].size
!= desc2
->channel
[1].size
))
1912 /* Everything below is not needed if the driver never uses the DCC
1913 * clear code with the value of 1.
1916 /* If the clear values are all 1 or all 0, this constraint can be
1918 if (vi_alpha_is_on_msb(format1
) != vi_alpha_is_on_msb(format2
))
1921 /* Channel types must match if the clear value of 1 is used.
1922 * The type categories are only float, signed, unsigned.
1923 * NORM and INT are always compatible.
1925 if (desc1
->channel
[0].type
!= desc2
->channel
[0].type
||
1926 (desc1
->nr_channels
>= 2 &&
1927 desc1
->channel
[1].type
!= desc2
->channel
[1].type
))
1933 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1935 enum pipe_format view_format
)
1937 struct si_texture
*stex
= (struct si_texture
*)tex
;
1939 return vi_dcc_enabled(stex
, level
) &&
1940 !vi_dcc_formats_compatible(tex
->format
, view_format
);
1943 /* This can't be merged with the above function, because
1944 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
1945 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
1946 struct pipe_resource
*tex
,
1948 enum pipe_format view_format
)
1950 struct si_texture
*stex
= (struct si_texture
*)tex
;
1952 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
1953 if (!si_texture_disable_dcc(sctx
, stex
))
1954 si_decompress_dcc(sctx
, stex
);
1957 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1958 struct pipe_resource
*texture
,
1959 const struct pipe_surface
*templ
,
1960 unsigned width0
, unsigned height0
,
1961 unsigned width
, unsigned height
)
1963 struct si_surface
*surface
= CALLOC_STRUCT(si_surface
);
1968 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1969 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1971 pipe_reference_init(&surface
->base
.reference
, 1);
1972 pipe_resource_reference(&surface
->base
.texture
, texture
);
1973 surface
->base
.context
= pipe
;
1974 surface
->base
.format
= templ
->format
;
1975 surface
->base
.width
= width
;
1976 surface
->base
.height
= height
;
1977 surface
->base
.u
= templ
->u
;
1979 surface
->width0
= width0
;
1980 surface
->height0
= height0
;
1982 surface
->dcc_incompatible
=
1983 texture
->target
!= PIPE_BUFFER
&&
1984 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
1986 return &surface
->base
;
1989 static struct pipe_surface
*si_create_surface(struct pipe_context
*pipe
,
1990 struct pipe_resource
*tex
,
1991 const struct pipe_surface
*templ
)
1993 unsigned level
= templ
->u
.tex
.level
;
1994 unsigned width
= u_minify(tex
->width0
, level
);
1995 unsigned height
= u_minify(tex
->height0
, level
);
1996 unsigned width0
= tex
->width0
;
1997 unsigned height0
= tex
->height0
;
1999 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2000 const struct util_format_description
*tex_desc
2001 = util_format_description(tex
->format
);
2002 const struct util_format_description
*templ_desc
2003 = util_format_description(templ
->format
);
2005 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2007 /* Adjust size of surface if and only if the block width or
2008 * height is changed. */
2009 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2010 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2011 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2012 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2014 width
= nblks_x
* templ_desc
->block
.width
;
2015 height
= nblks_y
* templ_desc
->block
.height
;
2017 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2018 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2022 return si_create_surface_custom(pipe
, tex
, templ
,
2027 static void si_surface_destroy(struct pipe_context
*pipe
,
2028 struct pipe_surface
*surface
)
2030 pipe_resource_reference(&surface
->texture
, NULL
);
2034 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2036 const struct util_format_description
*desc
= util_format_description(format
);
2038 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2040 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2041 return V_028C70_SWAP_STD
;
2043 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2046 switch (desc
->nr_channels
) {
2048 if (HAS_SWIZZLE(0,X
))
2049 return V_028C70_SWAP_STD
; /* X___ */
2050 else if (HAS_SWIZZLE(3,X
))
2051 return V_028C70_SWAP_ALT_REV
; /* ___X */
2054 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2055 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2056 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2057 return V_028C70_SWAP_STD
; /* XY__ */
2058 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2059 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2060 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2062 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2063 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2064 return V_028C70_SWAP_ALT
; /* X__Y */
2065 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2066 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2069 if (HAS_SWIZZLE(0,X
))
2070 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2071 else if (HAS_SWIZZLE(0,Z
))
2072 return V_028C70_SWAP_STD_REV
; /* ZYX */
2075 /* check the middle channels, the 1st and 4th channel can be NONE */
2076 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2077 return V_028C70_SWAP_STD
; /* XYZW */
2078 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2079 return V_028C70_SWAP_STD_REV
; /* WZYX */
2080 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2081 return V_028C70_SWAP_ALT
; /* ZYXW */
2082 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2085 return V_028C70_SWAP_ALT_REV
;
2087 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2094 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2096 static void vi_dcc_clean_up_context_slot(struct si_context
*sctx
,
2101 if (sctx
->dcc_stats
[slot
].query_active
)
2102 vi_separate_dcc_stop_query(sctx
,
2103 sctx
->dcc_stats
[slot
].tex
);
2105 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
[slot
].ps_stats
); i
++)
2106 if (sctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2107 sctx
->b
.destroy_query(&sctx
->b
,
2108 sctx
->dcc_stats
[slot
].ps_stats
[i
]);
2109 sctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2112 si_texture_reference(&sctx
->dcc_stats
[slot
].tex
, NULL
);
2116 * Return the per-context slot where DCC statistics queries for the texture live.
2118 static unsigned vi_get_context_dcc_stats_index(struct si_context
*sctx
,
2119 struct si_texture
*tex
)
2121 int i
, empty_slot
= -1;
2123 /* Remove zombie textures (textures kept alive by this array only). */
2124 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2125 if (sctx
->dcc_stats
[i
].tex
&&
2126 sctx
->dcc_stats
[i
].tex
->buffer
.b
.b
.reference
.count
== 1)
2127 vi_dcc_clean_up_context_slot(sctx
, i
);
2129 /* Find the texture. */
2130 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
2131 /* Return if found. */
2132 if (sctx
->dcc_stats
[i
].tex
== tex
) {
2133 sctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2137 /* Record the first seen empty slot. */
2138 if (empty_slot
== -1 && !sctx
->dcc_stats
[i
].tex
)
2142 /* Not found. Remove the oldest member to make space in the array. */
2143 if (empty_slot
== -1) {
2144 int oldest_slot
= 0;
2146 /* Find the oldest slot. */
2147 for (i
= 1; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2148 if (sctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2149 sctx
->dcc_stats
[i
].last_use_timestamp
)
2152 /* Clean up the oldest slot. */
2153 vi_dcc_clean_up_context_slot(sctx
, oldest_slot
);
2154 empty_slot
= oldest_slot
;
2157 /* Add the texture to the new slot. */
2158 si_texture_reference(&sctx
->dcc_stats
[empty_slot
].tex
, tex
);
2159 sctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2163 static struct pipe_query
*
2164 vi_create_resuming_pipestats_query(struct si_context
*sctx
)
2166 struct si_query_hw
*query
= (struct si_query_hw
*)
2167 sctx
->b
.create_query(&sctx
->b
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2169 query
->flags
|= SI_QUERY_HW_FLAG_BEGIN_RESUMES
;
2170 return (struct pipe_query
*)query
;
2174 * Called when binding a color buffer.
2176 void vi_separate_dcc_start_query(struct si_context
*sctx
,
2177 struct si_texture
*tex
)
2179 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2181 assert(!sctx
->dcc_stats
[i
].query_active
);
2183 if (!sctx
->dcc_stats
[i
].ps_stats
[0])
2184 sctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(sctx
);
2186 /* begin or resume the query */
2187 sctx
->b
.begin_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2188 sctx
->dcc_stats
[i
].query_active
= true;
2192 * Called when unbinding a color buffer.
2194 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
2195 struct si_texture
*tex
)
2197 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2199 assert(sctx
->dcc_stats
[i
].query_active
);
2200 assert(sctx
->dcc_stats
[i
].ps_stats
[0]);
2202 /* pause or end the query */
2203 sctx
->b
.end_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2204 sctx
->dcc_stats
[i
].query_active
= false;
2207 static bool vi_should_enable_separate_dcc(struct si_texture
*tex
)
2209 /* The minimum number of fullscreen draws per frame that is required
2211 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2214 /* Called by fast clear. */
2215 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
2216 struct si_texture
*tex
)
2218 /* The intent is to use this with shared displayable back buffers,
2219 * but it's not strictly limited only to them.
2221 if (!tex
->buffer
.b
.is_shared
||
2222 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2223 tex
->buffer
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2224 tex
->buffer
.b
.b
.last_level
> 0 ||
2225 !tex
->surface
.dcc_size
||
2226 sctx
->screen
->debug_flags
& DBG(NO_DCC
) ||
2227 sctx
->screen
->debug_flags
& DBG(NO_DCC_FB
))
2230 assert(sctx
->chip_class
>= VI
);
2232 if (tex
->dcc_offset
)
2233 return; /* already enabled */
2235 /* Enable the DCC stat gathering. */
2236 if (!tex
->dcc_gather_statistics
) {
2237 tex
->dcc_gather_statistics
= true;
2238 vi_separate_dcc_start_query(sctx
, tex
);
2241 if (!vi_should_enable_separate_dcc(tex
))
2242 return; /* stats show that DCC decompression is too expensive */
2244 assert(tex
->surface
.num_dcc_levels
);
2245 assert(!tex
->dcc_separate_buffer
);
2247 si_texture_discard_cmask(sctx
->screen
, tex
);
2249 /* Get a DCC buffer. */
2250 if (tex
->last_dcc_separate_buffer
) {
2251 assert(tex
->dcc_gather_statistics
);
2252 assert(!tex
->dcc_separate_buffer
);
2253 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2254 tex
->last_dcc_separate_buffer
= NULL
;
2256 tex
->dcc_separate_buffer
=
2257 si_aligned_buffer_create(sctx
->b
.screen
,
2258 SI_RESOURCE_FLAG_UNMAPPABLE
,
2260 tex
->surface
.dcc_size
,
2261 tex
->surface
.dcc_alignment
);
2262 if (!tex
->dcc_separate_buffer
)
2266 /* dcc_offset is the absolute GPUVM address. */
2267 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2269 /* no need to flag anything since this is called by fast clear that
2270 * flags framebuffer state
2275 * Called by pipe_context::flush_resource, the place where DCC decompression
2278 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2279 struct si_texture
*tex
)
2281 struct si_context
*sctx
= (struct si_context
*)ctx
;
2282 struct pipe_query
*tmp
;
2283 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2284 bool query_active
= sctx
->dcc_stats
[i
].query_active
;
2285 bool disable
= false;
2287 if (sctx
->dcc_stats
[i
].ps_stats
[2]) {
2288 union pipe_query_result result
;
2290 /* Read the results. */
2291 struct pipe_query
*query
= sctx
->dcc_stats
[i
].ps_stats
[2];
2292 ctx
->get_query_result(ctx
, query
,
2294 si_query_buffer_reset(sctx
, &((struct si_query_hw
*)query
)->buffer
);
2296 /* Compute the approximate number of fullscreen draws. */
2297 tex
->ps_draw_ratio
=
2298 result
.pipeline_statistics
.ps_invocations
/
2299 (tex
->buffer
.b
.b
.width0
* tex
->buffer
.b
.b
.height0
);
2300 sctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2302 disable
= tex
->dcc_separate_buffer
&&
2303 !vi_should_enable_separate_dcc(tex
);
2306 tex
->num_slow_clears
= 0;
2308 /* stop the statistics query for ps_stats[0] */
2310 vi_separate_dcc_stop_query(sctx
, tex
);
2312 /* Move the queries in the queue by one. */
2313 tmp
= sctx
->dcc_stats
[i
].ps_stats
[2];
2314 sctx
->dcc_stats
[i
].ps_stats
[2] = sctx
->dcc_stats
[i
].ps_stats
[1];
2315 sctx
->dcc_stats
[i
].ps_stats
[1] = sctx
->dcc_stats
[i
].ps_stats
[0];
2316 sctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2318 /* create and start a new query as ps_stats[0] */
2320 vi_separate_dcc_start_query(sctx
, tex
);
2323 assert(!tex
->last_dcc_separate_buffer
);
2324 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2325 tex
->dcc_separate_buffer
= NULL
;
2326 tex
->dcc_offset
= 0;
2327 /* no need to flag anything since this is called after
2328 * decompression that re-sets framebuffer state
2333 static struct pipe_memory_object
*
2334 si_memobj_from_handle(struct pipe_screen
*screen
,
2335 struct winsys_handle
*whandle
,
2338 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2339 struct si_memory_object
*memobj
= CALLOC_STRUCT(si_memory_object
);
2340 struct pb_buffer
*buf
= NULL
;
2341 uint32_t stride
, offset
;
2346 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
2347 sscreen
->info
.max_alignment
,
2354 memobj
->b
.dedicated
= dedicated
;
2356 memobj
->stride
= stride
;
2358 return (struct pipe_memory_object
*)memobj
;
2363 si_memobj_destroy(struct pipe_screen
*screen
,
2364 struct pipe_memory_object
*_memobj
)
2366 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2368 pb_reference(&memobj
->buf
, NULL
);
2372 static struct pipe_resource
*
2373 si_texture_from_memobj(struct pipe_screen
*screen
,
2374 const struct pipe_resource
*templ
,
2375 struct pipe_memory_object
*_memobj
,
2378 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2379 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2380 struct pipe_resource
*tex
=
2381 si_texture_from_winsys_buffer(sscreen
, templ
, memobj
->buf
,
2382 memobj
->stride
, offset
,
2383 PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
|
2384 PIPE_HANDLE_USAGE_SHADER_WRITE
,
2385 memobj
->b
.dedicated
);
2389 /* si_texture_from_winsys_buffer doesn't increment refcount of
2390 * memobj->buf, so increment it here.
2392 struct pb_buffer
*buf
= NULL
;
2393 pb_reference(&buf
, memobj
->buf
);
2397 static bool si_check_resource_capability(struct pipe_screen
*screen
,
2398 struct pipe_resource
*resource
,
2401 struct si_texture
*tex
= (struct si_texture
*)resource
;
2403 /* Buffers only support the linear flag. */
2404 if (resource
->target
== PIPE_BUFFER
)
2405 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2407 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2410 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2413 /* TODO: PIPE_BIND_CURSOR - do we care? */
2417 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2419 sscreen
->b
.resource_from_handle
= si_texture_from_handle
;
2420 sscreen
->b
.resource_get_handle
= si_texture_get_handle
;
2421 sscreen
->b
.resource_from_memobj
= si_texture_from_memobj
;
2422 sscreen
->b
.memobj_create_from_handle
= si_memobj_from_handle
;
2423 sscreen
->b
.memobj_destroy
= si_memobj_destroy
;
2424 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2427 void si_init_context_texture_functions(struct si_context
*sctx
)
2429 sctx
->b
.create_surface
= si_create_surface
;
2430 sctx
->b
.surface_destroy
= si_surface_destroy
;