2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeonsi/si_pipe.h"
27 #include "radeonsi/si_query.h"
28 #include "util/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/u_resource.h"
33 #include "util/u_surface.h"
34 #include "util/os_time.h"
37 #include "state_tracker/drm_driver.h"
38 #include "amd/common/sid.h"
40 static enum radeon_surf_mode
41 si_choose_tiling(struct si_screen
*sscreen
,
42 const struct pipe_resource
*templ
, bool tc_compatible_htile
);
45 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
46 struct r600_texture
*rdst
,
47 unsigned dst_level
, unsigned dstx
,
48 unsigned dsty
, unsigned dstz
,
49 struct r600_texture
*rsrc
,
51 const struct pipe_box
*src_box
)
56 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
59 /* MSAA: Blits don't exist in the real world. */
60 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
61 rdst
->resource
.b
.b
.nr_samples
> 1)
64 /* Depth-stencil surfaces:
65 * When dst is linear, the DB->CB copy preserves HTILE.
66 * When dst is tiled, the 3D path must be used to update HTILE.
68 if (rsrc
->is_depth
|| rdst
->is_depth
)
72 * src: Use the 3D path. DCC decompression is expensive.
73 * dst: Use the 3D path to compress the pixels with DCC.
75 if (vi_dcc_enabled(rsrc
, src_level
) ||
76 vi_dcc_enabled(rdst
, dst_level
))
80 * src: Both texture and SDMA paths need decompression. Use SDMA.
81 * dst: If overwriting the whole texture, discard CMASK and use
82 * SDMA. Otherwise, use the 3D path.
84 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
85 /* The CMASK clear is only enabled for the first level. */
86 assert(dst_level
== 0);
87 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
88 dstx
, dsty
, dstz
, src_box
->width
,
89 src_box
->height
, src_box
->depth
))
92 si_texture_discard_cmask(sctx
->screen
, rdst
);
95 /* All requirements are met. Prepare textures for SDMA. */
96 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
97 sctx
->b
.flush_resource(&sctx
->b
, &rsrc
->resource
.b
.b
);
99 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
100 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
105 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
106 static void si_copy_region_with_blit(struct pipe_context
*pipe
,
107 struct pipe_resource
*dst
,
109 unsigned dstx
, unsigned dsty
, unsigned dstz
,
110 struct pipe_resource
*src
,
112 const struct pipe_box
*src_box
)
114 struct pipe_blit_info blit
;
116 memset(&blit
, 0, sizeof(blit
));
117 blit
.src
.resource
= src
;
118 blit
.src
.format
= src
->format
;
119 blit
.src
.level
= src_level
;
120 blit
.src
.box
= *src_box
;
121 blit
.dst
.resource
= dst
;
122 blit
.dst
.format
= dst
->format
;
123 blit
.dst
.level
= dst_level
;
124 blit
.dst
.box
.x
= dstx
;
125 blit
.dst
.box
.y
= dsty
;
126 blit
.dst
.box
.z
= dstz
;
127 blit
.dst
.box
.width
= src_box
->width
;
128 blit
.dst
.box
.height
= src_box
->height
;
129 blit
.dst
.box
.depth
= src_box
->depth
;
130 blit
.mask
= util_format_get_mask(src
->format
) &
131 util_format_get_mask(dst
->format
);
132 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
135 pipe
->blit(pipe
, &blit
);
139 /* Copy from a full GPU texture to a transfer's staging one. */
140 static void si_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
142 struct si_context
*sctx
= (struct si_context
*)ctx
;
143 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
144 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
145 struct pipe_resource
*src
= transfer
->resource
;
147 if (src
->nr_samples
> 1) {
148 si_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
149 src
, transfer
->level
, &transfer
->box
);
153 sctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
157 /* Copy from a transfer's staging texture to a full GPU one. */
158 static void si_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
160 struct si_context
*sctx
= (struct si_context
*)ctx
;
161 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
162 struct pipe_resource
*dst
= transfer
->resource
;
163 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
164 struct pipe_box sbox
;
166 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
168 if (dst
->nr_samples
> 1) {
169 si_copy_region_with_blit(ctx
, dst
, transfer
->level
,
170 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
175 sctx
->dma_copy(ctx
, dst
, transfer
->level
,
176 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
180 static unsigned si_texture_get_offset(struct si_screen
*sscreen
,
181 struct r600_texture
*rtex
, unsigned level
,
182 const struct pipe_box
*box
,
184 unsigned *layer_stride
)
186 if (sscreen
->info
.chip_class
>= GFX9
) {
187 *stride
= rtex
->surface
.u
.gfx9
.surf_pitch
* rtex
->surface
.bpe
;
188 *layer_stride
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
193 /* Each texture is an array of slices. Each slice is an array
194 * of mipmap levels. */
195 return box
->z
* rtex
->surface
.u
.gfx9
.surf_slice_size
+
196 rtex
->surface
.u
.gfx9
.offset
[level
] +
197 (box
->y
/ rtex
->surface
.blk_h
*
198 rtex
->surface
.u
.gfx9
.surf_pitch
+
199 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
201 *stride
= rtex
->surface
.u
.legacy
.level
[level
].nblk_x
*
203 assert((uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
204 *layer_stride
= (uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
207 return rtex
->surface
.u
.legacy
.level
[level
].offset
;
209 /* Each texture is an array of mipmap levels. Each level is
210 * an array of slices. */
211 return rtex
->surface
.u
.legacy
.level
[level
].offset
+
212 box
->z
* (uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
213 (box
->y
/ rtex
->surface
.blk_h
*
214 rtex
->surface
.u
.legacy
.level
[level
].nblk_x
+
215 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
219 static int si_init_surface(struct si_screen
*sscreen
,
220 struct radeon_surf
*surface
,
221 const struct pipe_resource
*ptex
,
222 enum radeon_surf_mode array_mode
,
223 unsigned pitch_in_bytes_override
,
227 bool is_flushed_depth
,
228 bool tc_compatible_htile
)
230 const struct util_format_description
*desc
=
231 util_format_description(ptex
->format
);
232 bool is_depth
, is_stencil
;
234 unsigned i
, bpe
, flags
= 0;
236 is_depth
= util_format_has_depth(desc
);
237 is_stencil
= util_format_has_stencil(desc
);
239 if (!is_flushed_depth
&&
240 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
241 bpe
= 4; /* stencil is allocated separately on evergreen */
243 bpe
= util_format_get_blocksize(ptex
->format
);
244 assert(util_is_power_of_two_or_zero(bpe
));
247 if (!is_flushed_depth
&& is_depth
) {
248 flags
|= RADEON_SURF_ZBUFFER
;
250 if (tc_compatible_htile
&&
251 (sscreen
->info
.chip_class
>= GFX9
||
252 array_mode
== RADEON_SURF_MODE_2D
)) {
253 /* TC-compatible HTILE only supports Z32_FLOAT.
254 * GFX9 also supports Z16_UNORM.
255 * On VI, promote Z16 to Z32. DB->CB copies will convert
256 * the format for transfers.
258 if (sscreen
->info
.chip_class
== VI
)
261 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
265 flags
|= RADEON_SURF_SBUFFER
;
268 if (sscreen
->info
.chip_class
>= VI
&&
269 (ptex
->flags
& SI_RESOURCE_FLAG_DISABLE_DCC
||
270 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
271 /* DCC MSAA array textures are disallowed due to incomplete clear impl. */
272 (ptex
->nr_samples
>= 2 &&
273 (!sscreen
->dcc_msaa_allowed
|| ptex
->array_size
> 1))))
274 flags
|= RADEON_SURF_DISABLE_DCC
;
276 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
277 /* This should catch bugs in gallium users setting incorrect flags. */
278 assert(ptex
->nr_samples
<= 1 &&
279 ptex
->array_size
== 1 &&
281 ptex
->last_level
== 0 &&
282 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
284 flags
|= RADEON_SURF_SCANOUT
;
287 if (ptex
->bind
& PIPE_BIND_SHARED
)
288 flags
|= RADEON_SURF_SHAREABLE
;
290 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
291 if (!(ptex
->flags
& SI_RESOURCE_FLAG_FORCE_TILING
))
292 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
294 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, flags
, bpe
,
295 array_mode
, surface
);
300 unsigned pitch
= pitch_in_bytes_override
/ bpe
;
302 if (sscreen
->info
.chip_class
>= GFX9
) {
304 surface
->u
.gfx9
.surf_pitch
= pitch
;
305 surface
->u
.gfx9
.surf_slice_size
=
306 (uint64_t)pitch
* surface
->u
.gfx9
.surf_height
* bpe
;
308 surface
->u
.gfx9
.surf_offset
= offset
;
311 surface
->u
.legacy
.level
[0].nblk_x
= pitch
;
312 surface
->u
.legacy
.level
[0].slice_size_dw
=
313 ((uint64_t)pitch
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
316 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
317 surface
->u
.legacy
.level
[i
].offset
+= offset
;
323 static void si_texture_init_metadata(struct si_screen
*sscreen
,
324 struct r600_texture
*rtex
,
325 struct radeon_bo_metadata
*metadata
)
327 struct radeon_surf
*surface
= &rtex
->surface
;
329 memset(metadata
, 0, sizeof(*metadata
));
331 if (sscreen
->info
.chip_class
>= GFX9
) {
332 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
334 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
335 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
336 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
337 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
338 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
339 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
340 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
341 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
342 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
343 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
344 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
345 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
349 static void si_surface_import_metadata(struct si_screen
*sscreen
,
350 struct radeon_surf
*surf
,
351 struct radeon_bo_metadata
*metadata
,
352 enum radeon_surf_mode
*array_mode
,
355 if (sscreen
->info
.chip_class
>= GFX9
) {
356 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
357 *array_mode
= RADEON_SURF_MODE_2D
;
359 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
361 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
362 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
364 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
366 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
367 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
368 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
369 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
370 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
371 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
373 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
374 *array_mode
= RADEON_SURF_MODE_2D
;
375 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
376 *array_mode
= RADEON_SURF_MODE_1D
;
378 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
380 *is_scanout
= metadata
->u
.legacy
.scanout
;
384 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
385 struct r600_texture
*rtex
)
387 struct si_screen
*sscreen
= sctx
->screen
;
388 struct pipe_context
*ctx
= &sctx
->b
;
390 if (ctx
== sscreen
->aux_context
)
391 mtx_lock(&sscreen
->aux_context_lock
);
393 unsigned n
= sctx
->num_decompress_calls
;
394 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
396 /* Flush only if any fast clear elimination took place. */
397 if (n
!= sctx
->num_decompress_calls
)
398 ctx
->flush(ctx
, NULL
, 0);
400 if (ctx
== sscreen
->aux_context
)
401 mtx_unlock(&sscreen
->aux_context_lock
);
404 void si_texture_discard_cmask(struct si_screen
*sscreen
,
405 struct r600_texture
*rtex
)
407 if (!rtex
->cmask
.size
)
410 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
413 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
414 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
415 rtex
->dirty_level_mask
= 0;
417 rtex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
419 if (rtex
->cmask_buffer
!= &rtex
->resource
)
420 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
422 /* Notify all contexts about the change. */
423 p_atomic_inc(&sscreen
->dirty_tex_counter
);
424 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
427 static bool si_can_disable_dcc(struct r600_texture
*rtex
)
429 /* We can't disable DCC if it can be written by another process. */
430 return rtex
->dcc_offset
&&
431 (!rtex
->resource
.b
.is_shared
||
432 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
435 static bool si_texture_discard_dcc(struct si_screen
*sscreen
,
436 struct r600_texture
*rtex
)
438 if (!si_can_disable_dcc(rtex
))
441 assert(rtex
->dcc_separate_buffer
== NULL
);
444 rtex
->dcc_offset
= 0;
446 /* Notify all contexts about the change. */
447 p_atomic_inc(&sscreen
->dirty_tex_counter
);
452 * Disable DCC for the texture. (first decompress, then discard metadata).
454 * There is unresolved multi-context synchronization issue between
455 * screen::aux_context and the current context. If applications do this with
456 * multiple contexts, it's already undefined behavior for them and we don't
457 * have to worry about that. The scenario is:
459 * If context 1 disables DCC and context 2 has queued commands that write
460 * to the texture via CB with DCC enabled, and the order of operations is
462 * context 2 queues draw calls rendering to the texture, but doesn't flush
463 * context 1 disables DCC and flushes
464 * context 1 & 2 reset descriptors and FB state
465 * context 2 flushes (new compressed tiles written by the draw calls)
466 * context 1 & 2 read garbage, because DCC is disabled, yet there are
469 * \param sctx the current context if you have one, or rscreen->aux_context
472 bool si_texture_disable_dcc(struct si_context
*sctx
,
473 struct r600_texture
*rtex
)
475 struct si_screen
*sscreen
= sctx
->screen
;
477 if (!si_can_disable_dcc(rtex
))
480 if (&sctx
->b
== sscreen
->aux_context
)
481 mtx_lock(&sscreen
->aux_context_lock
);
483 /* Decompress DCC. */
484 si_decompress_dcc(sctx
, rtex
);
485 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
487 if (&sctx
->b
== sscreen
->aux_context
)
488 mtx_unlock(&sscreen
->aux_context_lock
);
490 return si_texture_discard_dcc(sscreen
, rtex
);
493 static void si_reallocate_texture_inplace(struct si_context
*sctx
,
494 struct r600_texture
*rtex
,
495 unsigned new_bind_flag
,
496 bool invalidate_storage
)
498 struct pipe_screen
*screen
= sctx
->b
.screen
;
499 struct r600_texture
*new_tex
;
500 struct pipe_resource templ
= rtex
->resource
.b
.b
;
503 templ
.bind
|= new_bind_flag
;
505 if (rtex
->resource
.b
.is_shared
)
508 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
509 if (rtex
->surface
.is_linear
)
512 /* This fails with MSAA, depth, and compressed textures. */
513 if (si_choose_tiling(sctx
->screen
, &templ
, false) !=
514 RADEON_SURF_MODE_LINEAR_ALIGNED
)
518 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
522 /* Copy the pixels to the new texture. */
523 if (!invalidate_storage
) {
524 for (i
= 0; i
<= templ
.last_level
; i
++) {
528 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
529 util_num_layers(&templ
, i
), &box
);
531 sctx
->dma_copy(&sctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
532 &rtex
->resource
.b
.b
, i
, &box
);
536 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
537 si_texture_discard_cmask(sctx
->screen
, rtex
);
538 si_texture_discard_dcc(sctx
->screen
, rtex
);
541 /* Replace the structure fields of rtex. */
542 rtex
->resource
.b
.b
.bind
= templ
.bind
;
543 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
544 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
545 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
546 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
547 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
548 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
549 rtex
->resource
.domains
= new_tex
->resource
.domains
;
550 rtex
->resource
.flags
= new_tex
->resource
.flags
;
551 rtex
->size
= new_tex
->size
;
552 rtex
->db_render_format
= new_tex
->db_render_format
;
553 rtex
->db_compatible
= new_tex
->db_compatible
;
554 rtex
->can_sample_z
= new_tex
->can_sample_z
;
555 rtex
->can_sample_s
= new_tex
->can_sample_s
;
556 rtex
->surface
= new_tex
->surface
;
557 rtex
->fmask
= new_tex
->fmask
;
558 rtex
->cmask
= new_tex
->cmask
;
559 rtex
->cb_color_info
= new_tex
->cb_color_info
;
560 rtex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
561 rtex
->htile_offset
= new_tex
->htile_offset
;
562 rtex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
563 rtex
->depth_cleared
= new_tex
->depth_cleared
;
564 rtex
->stencil_cleared
= new_tex
->stencil_cleared
;
565 rtex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
566 rtex
->framebuffers_bound
= new_tex
->framebuffers_bound
;
568 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
569 assert(!rtex
->htile_offset
);
570 assert(!rtex
->cmask
.size
);
571 assert(!rtex
->fmask
.size
);
572 assert(!rtex
->dcc_offset
);
573 assert(!rtex
->is_depth
);
576 r600_texture_reference(&new_tex
, NULL
);
578 p_atomic_inc(&sctx
->screen
->dirty_tex_counter
);
581 static uint32_t si_get_bo_metadata_word1(struct si_screen
*sscreen
)
583 return (ATI_VENDOR_ID
<< 16) | sscreen
->info
.pci_id
;
586 static void si_query_opaque_metadata(struct si_screen
*sscreen
,
587 struct r600_texture
*rtex
,
588 struct radeon_bo_metadata
*md
)
590 struct pipe_resource
*res
= &rtex
->resource
.b
.b
;
591 static const unsigned char swizzle
[] = {
598 bool is_array
= util_texture_is_array(res
->target
);
600 /* DRM 2.x.x doesn't support this. */
601 if (sscreen
->info
.drm_major
!= 3)
604 assert(rtex
->dcc_separate_buffer
== NULL
);
605 assert(rtex
->fmask
.size
== 0);
607 /* Metadata image format format version 1:
608 * [0] = 1 (metadata format identifier)
609 * [1] = (VENDOR_ID << 16) | PCI_ID
610 * [2:9] = image descriptor for the whole resource
611 * [2] is always 0, because the base address is cleared
612 * [9] is the DCC offset bits [39:8] from the beginning of
614 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
617 md
->metadata
[0] = 1; /* metadata image format version 1 */
619 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
620 md
->metadata
[1] = si_get_bo_metadata_word1(sscreen
);
622 si_make_texture_descriptor(sscreen
, rtex
, true,
623 res
->target
, res
->format
,
624 swizzle
, 0, res
->last_level
, 0,
625 is_array
? res
->array_size
- 1 : 0,
626 res
->width0
, res
->height0
, res
->depth0
,
629 si_set_mutable_tex_desc_fields(sscreen
, rtex
, &rtex
->surface
.u
.legacy
.level
[0],
630 0, 0, rtex
->surface
.blk_w
, false, desc
);
632 /* Clear the base address and set the relative DCC offset. */
634 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
635 desc
[7] = rtex
->dcc_offset
>> 8;
637 /* Dwords [2:9] contain the image descriptor. */
638 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
639 md
->size_metadata
= 10 * 4;
641 /* Dwords [10:..] contain the mipmap level offsets. */
642 if (sscreen
->info
.chip_class
<= VI
) {
643 for (i
= 0; i
<= res
->last_level
; i
++)
644 md
->metadata
[10+i
] = rtex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
646 md
->size_metadata
+= (1 + res
->last_level
) * 4;
650 static void si_apply_opaque_metadata(struct si_screen
*sscreen
,
651 struct r600_texture
*rtex
,
652 struct radeon_bo_metadata
*md
)
654 uint32_t *desc
= &md
->metadata
[2];
656 if (sscreen
->info
.chip_class
< VI
)
659 /* Return if DCC is enabled. The texture should be set up with it
662 if (md
->size_metadata
>= 10 * 4 && /* at least 2(header) + 8(desc) dwords */
663 md
->metadata
[0] != 0 &&
664 md
->metadata
[1] == si_get_bo_metadata_word1(sscreen
) &&
665 G_008F28_COMPRESSION_EN(desc
[6])) {
666 rtex
->dcc_offset
= (uint64_t)desc
[7] << 8;
670 /* Disable DCC. These are always set by texture_from_handle and must
673 rtex
->dcc_offset
= 0;
676 static boolean
si_texture_get_handle(struct pipe_screen
* screen
,
677 struct pipe_context
*ctx
,
678 struct pipe_resource
*resource
,
679 struct winsys_handle
*whandle
,
682 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
683 struct si_context
*sctx
;
684 struct r600_resource
*res
= (struct r600_resource
*)resource
;
685 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
686 struct radeon_bo_metadata metadata
;
687 bool update_metadata
= false;
688 unsigned stride
, offset
, slice_size
;
691 ctx
= threaded_context_unwrap_sync(ctx
);
692 sctx
= (struct si_context
*)(ctx
? ctx
: sscreen
->aux_context
);
694 if (resource
->target
!= PIPE_BUFFER
) {
695 /* This is not supported now, but it might be required for OpenCL
696 * interop in the future.
698 if (resource
->nr_samples
> 1 || rtex
->is_depth
)
701 /* Move a suballocated texture into a non-suballocated allocation. */
702 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
703 rtex
->surface
.tile_swizzle
||
704 (rtex
->resource
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
705 sscreen
->info
.has_local_buffers
&&
706 whandle
->type
!= DRM_API_HANDLE_TYPE_KMS
)) {
707 assert(!res
->b
.is_shared
);
708 si_reallocate_texture_inplace(sctx
, rtex
,
709 PIPE_BIND_SHARED
, false);
711 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
712 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
713 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
714 assert(rtex
->surface
.tile_swizzle
== 0);
717 /* Since shader image stores don't support DCC on VI,
718 * disable it for external clients that want write
721 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
722 if (si_texture_disable_dcc(sctx
, rtex
)) {
723 update_metadata
= true;
724 /* si_texture_disable_dcc flushes the context */
729 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
730 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
731 /* Eliminate fast clear (both CMASK and DCC) */
732 si_eliminate_fast_color_clear(sctx
, rtex
);
733 /* eliminate_fast_color_clear flushes the context */
736 /* Disable CMASK if flush_resource isn't going
739 if (rtex
->cmask
.size
)
740 si_texture_discard_cmask(sscreen
, rtex
);
744 if (!res
->b
.is_shared
|| update_metadata
) {
745 si_texture_init_metadata(sscreen
, rtex
, &metadata
);
746 si_query_opaque_metadata(sscreen
, rtex
, &metadata
);
748 sscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
751 if (sscreen
->info
.chip_class
>= GFX9
) {
752 offset
= rtex
->surface
.u
.gfx9
.surf_offset
;
753 stride
= rtex
->surface
.u
.gfx9
.surf_pitch
*
755 slice_size
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
757 offset
= rtex
->surface
.u
.legacy
.level
[0].offset
;
758 stride
= rtex
->surface
.u
.legacy
.level
[0].nblk_x
*
760 slice_size
= (uint64_t)rtex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
763 /* Buffer exports are for the OpenCL interop. */
764 /* Move a suballocated buffer into a non-suballocated allocation. */
765 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
766 /* A DMABUF export always fails if the BO is local. */
767 (rtex
->resource
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
768 sscreen
->info
.has_local_buffers
)) {
769 assert(!res
->b
.is_shared
);
771 /* Allocate a new buffer with PIPE_BIND_SHARED. */
772 struct pipe_resource templ
= res
->b
.b
;
773 templ
.bind
|= PIPE_BIND_SHARED
;
775 struct pipe_resource
*newb
=
776 screen
->resource_create(screen
, &templ
);
780 /* Copy the old buffer contents to the new one. */
782 u_box_1d(0, newb
->width0
, &box
);
783 sctx
->b
.resource_copy_region(&sctx
->b
, newb
, 0, 0, 0, 0,
786 /* Move the new buffer storage to the old pipe_resource. */
787 si_replace_buffer_storage(&sctx
->b
, &res
->b
.b
, newb
);
788 pipe_resource_reference(&newb
, NULL
);
790 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
791 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
801 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
803 if (res
->b
.is_shared
) {
804 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
807 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
808 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
809 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
811 res
->b
.is_shared
= true;
812 res
->external_usage
= usage
;
815 return sscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
816 slice_size
, whandle
);
819 static void si_texture_destroy(struct pipe_screen
*screen
,
820 struct pipe_resource
*ptex
)
822 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
823 struct r600_resource
*resource
= &rtex
->resource
;
825 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
827 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
828 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
830 pb_reference(&resource
->buf
, NULL
);
831 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
832 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
836 static const struct u_resource_vtbl si_texture_vtbl
;
838 /* The number of samples can be specified independently of the texture. */
839 void si_texture_get_fmask_info(struct si_screen
*sscreen
,
840 struct r600_texture
*rtex
,
842 struct r600_fmask_info
*out
)
844 /* FMASK is allocated like an ordinary texture. */
845 struct pipe_resource templ
= rtex
->resource
.b
.b
;
846 struct radeon_surf fmask
= {};
849 memset(out
, 0, sizeof(*out
));
851 if (sscreen
->info
.chip_class
>= GFX9
) {
852 out
->alignment
= rtex
->surface
.u
.gfx9
.fmask_alignment
;
853 out
->size
= rtex
->surface
.u
.gfx9
.fmask_size
;
854 out
->tile_swizzle
= rtex
->surface
.u
.gfx9
.fmask_tile_swizzle
;
858 templ
.nr_samples
= 1;
859 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
861 switch (nr_samples
) {
870 PRINT_ERR("Invalid sample count for FMASK allocation.\n");
874 if (sscreen
->ws
->surface_init(sscreen
->ws
, &templ
, flags
, bpe
,
875 RADEON_SURF_MODE_2D
, &fmask
)) {
876 PRINT_ERR("Got error in surface_init while allocating FMASK.\n");
880 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
882 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
883 if (out
->slice_tile_max
)
884 out
->slice_tile_max
-= 1;
886 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
887 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
888 out
->bank_height
= fmask
.u
.legacy
.bankh
;
889 out
->tile_swizzle
= fmask
.tile_swizzle
;
890 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
891 out
->size
= fmask
.surf_size
;
894 static void si_texture_allocate_fmask(struct si_screen
*sscreen
,
895 struct r600_texture
*rtex
)
897 si_texture_get_fmask_info(sscreen
, rtex
,
898 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
900 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
901 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
904 void si_texture_get_cmask_info(struct si_screen
*sscreen
,
905 struct r600_texture
*rtex
,
906 struct r600_cmask_info
*out
)
908 unsigned pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
909 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
910 unsigned cl_width
, cl_height
;
912 if (sscreen
->info
.chip_class
>= GFX9
) {
913 out
->alignment
= rtex
->surface
.u
.gfx9
.cmask_alignment
;
914 out
->size
= rtex
->surface
.u
.gfx9
.cmask_size
;
931 case 16: /* Hawaii */
940 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
942 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
943 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
944 unsigned slice_elements
= (width
* height
) / (8*8);
946 /* Each element of CMASK is a nibble. */
947 unsigned slice_bytes
= slice_elements
/ 2;
949 out
->slice_tile_max
= (width
* height
) / (128*128);
950 if (out
->slice_tile_max
)
951 out
->slice_tile_max
-= 1;
953 out
->alignment
= MAX2(256, base_align
);
954 out
->size
= util_num_layers(&rtex
->resource
.b
.b
, 0) *
955 align(slice_bytes
, base_align
);
958 static void si_texture_allocate_cmask(struct si_screen
*sscreen
,
959 struct r600_texture
*rtex
)
961 si_texture_get_cmask_info(sscreen
, rtex
, &rtex
->cmask
);
963 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
964 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
966 rtex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
969 static void si_texture_get_htile_size(struct si_screen
*sscreen
,
970 struct r600_texture
*rtex
)
972 unsigned cl_width
, cl_height
, width
, height
;
973 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
974 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
976 assert(sscreen
->info
.chip_class
<= VI
);
978 rtex
->surface
.htile_size
= 0;
980 /* HTILE is broken with 1D tiling on old kernels and CIK. */
981 if (sscreen
->info
.chip_class
>= CIK
&&
982 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
983 sscreen
->info
.drm_major
== 2 && sscreen
->info
.drm_minor
< 38)
986 /* Overalign HTILE on P2 configs to work around GPU hangs in
987 * piglit/depthstencil-render-miplevels 585.
989 * This has been confirmed to help Kabini & Stoney, where the hangs
990 * are always reproducible. I think I have seen the test hang
991 * on Carrizo too, though it was very rare there.
993 if (sscreen
->info
.chip_class
>= CIK
&& num_pipes
< 4)
1022 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
1023 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
1025 slice_elements
= (width
* height
) / (8 * 8);
1026 slice_bytes
= slice_elements
* 4;
1028 pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
1029 base_align
= num_pipes
* pipe_interleave_bytes
;
1031 rtex
->surface
.htile_alignment
= base_align
;
1032 rtex
->surface
.htile_size
=
1033 util_num_layers(&rtex
->resource
.b
.b
, 0) *
1034 align(slice_bytes
, base_align
);
1037 static void si_texture_allocate_htile(struct si_screen
*sscreen
,
1038 struct r600_texture
*rtex
)
1040 if (sscreen
->info
.chip_class
<= VI
&& !rtex
->tc_compatible_htile
)
1041 si_texture_get_htile_size(sscreen
, rtex
);
1043 if (!rtex
->surface
.htile_size
)
1046 rtex
->htile_offset
= align(rtex
->size
, rtex
->surface
.htile_alignment
);
1047 rtex
->size
= rtex
->htile_offset
+ rtex
->surface
.htile_size
;
1050 void si_print_texture_info(struct si_screen
*sscreen
,
1051 struct r600_texture
*rtex
, struct u_log_context
*log
)
1055 /* Common parameters. */
1056 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
1057 "blk_h=%u, array_size=%u, last_level=%u, "
1058 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
1059 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
1060 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
1061 rtex
->surface
.blk_h
,
1062 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
1063 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
1064 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
1066 if (sscreen
->info
.chip_class
>= GFX9
) {
1067 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
1068 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
1069 rtex
->surface
.surf_size
,
1070 rtex
->surface
.u
.gfx9
.surf_slice_size
,
1071 rtex
->surface
.surf_alignment
,
1072 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
1073 rtex
->surface
.u
.gfx9
.surf
.epitch
,
1074 rtex
->surface
.u
.gfx9
.surf_pitch
);
1076 if (rtex
->fmask
.size
) {
1077 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
1078 "alignment=%u, swmode=%u, epitch=%u\n",
1080 rtex
->surface
.u
.gfx9
.fmask_size
,
1081 rtex
->surface
.u
.gfx9
.fmask_alignment
,
1082 rtex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1083 rtex
->surface
.u
.gfx9
.fmask
.epitch
);
1086 if (rtex
->cmask
.size
) {
1087 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", "
1088 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1090 rtex
->surface
.u
.gfx9
.cmask_size
,
1091 rtex
->surface
.u
.gfx9
.cmask_alignment
,
1092 rtex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1093 rtex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1096 if (rtex
->htile_offset
) {
1097 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, alignment=%u, "
1098 "rb_aligned=%u, pipe_aligned=%u\n",
1100 rtex
->surface
.htile_size
,
1101 rtex
->surface
.htile_alignment
,
1102 rtex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1103 rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1106 if (rtex
->dcc_offset
) {
1107 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, "
1108 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1109 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1110 rtex
->surface
.dcc_alignment
,
1111 rtex
->surface
.u
.gfx9
.dcc_pitch_max
,
1112 rtex
->surface
.num_dcc_levels
);
1115 if (rtex
->surface
.u
.gfx9
.stencil_offset
) {
1116 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1117 rtex
->surface
.u
.gfx9
.stencil_offset
,
1118 rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1119 rtex
->surface
.u
.gfx9
.stencil
.epitch
);
1124 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1125 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1126 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.u
.legacy
.bankw
,
1127 rtex
->surface
.u
.legacy
.bankh
, rtex
->surface
.u
.legacy
.num_banks
, rtex
->surface
.u
.legacy
.mtilea
,
1128 rtex
->surface
.u
.legacy
.tile_split
, rtex
->surface
.u
.legacy
.pipe_config
,
1129 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1131 if (rtex
->fmask
.size
)
1132 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1133 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1134 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
1135 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
1136 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
1138 if (rtex
->cmask
.size
)
1139 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1140 "slice_tile_max=%u\n",
1141 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
1142 rtex
->cmask
.slice_tile_max
);
1144 if (rtex
->htile_offset
)
1145 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, "
1146 "alignment=%u, TC_compatible = %u\n",
1147 rtex
->htile_offset
, rtex
->surface
.htile_size
,
1148 rtex
->surface
.htile_alignment
,
1149 rtex
->tc_compatible_htile
);
1151 if (rtex
->dcc_offset
) {
1152 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, alignment=%u\n",
1153 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1154 rtex
->surface
.dcc_alignment
);
1155 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1156 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%u, "
1157 "fast_clear_size=%u\n",
1158 i
, i
< rtex
->surface
.num_dcc_levels
,
1159 rtex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1160 rtex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1163 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1164 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1165 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1166 "mode=%u, tiling_index = %u\n",
1167 i
, rtex
->surface
.u
.legacy
.level
[i
].offset
,
1168 (uint64_t)rtex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
1169 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1170 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1171 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1172 rtex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1173 rtex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1174 rtex
->surface
.u
.legacy
.level
[i
].mode
,
1175 rtex
->surface
.u
.legacy
.tiling_index
[i
]);
1177 if (rtex
->surface
.has_stencil
) {
1178 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1179 rtex
->surface
.u
.legacy
.stencil_tile_split
);
1180 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
1181 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1182 "slice_size=%"PRIu64
", npix_x=%u, "
1183 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1184 "mode=%u, tiling_index = %u\n",
1185 i
, rtex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1186 (uint64_t)rtex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
1187 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1188 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1189 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1190 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1191 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1192 rtex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1193 rtex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1198 /* Common processing for r600_texture_create and r600_texture_from_handle */
1199 static struct r600_texture
*
1200 si_texture_create_object(struct pipe_screen
*screen
,
1201 const struct pipe_resource
*base
,
1202 struct pb_buffer
*buf
,
1203 struct radeon_surf
*surface
)
1205 struct r600_texture
*rtex
;
1206 struct r600_resource
*resource
;
1207 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1209 rtex
= CALLOC_STRUCT(r600_texture
);
1213 resource
= &rtex
->resource
;
1214 resource
->b
.b
= *base
;
1215 resource
->b
.b
.next
= NULL
;
1216 resource
->b
.vtbl
= &si_texture_vtbl
;
1217 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1218 resource
->b
.b
.screen
= screen
;
1220 /* don't include stencil-only formats which we don't support for rendering */
1221 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1223 rtex
->surface
= *surface
;
1224 rtex
->size
= rtex
->surface
.surf_size
;
1226 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0 &&
1227 (rtex
->surface
.flags
&
1228 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1230 /* TC-compatible HTILE:
1231 * - VI only supports Z32_FLOAT.
1232 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1233 if (rtex
->tc_compatible_htile
) {
1234 if (sscreen
->info
.chip_class
>= GFX9
&&
1235 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1236 rtex
->db_render_format
= base
->format
;
1238 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1239 rtex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1240 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1243 rtex
->db_render_format
= base
->format
;
1246 /* Applies to GCN. */
1247 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1249 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1250 * between frames, so the only thing that can enable separate DCC
1251 * with DRI2 is multiple slow clears within a frame.
1253 rtex
->ps_draw_ratio
= 0;
1255 if (rtex
->is_depth
) {
1256 if (sscreen
->info
.chip_class
>= GFX9
) {
1257 rtex
->can_sample_z
= true;
1258 rtex
->can_sample_s
= true;
1260 rtex
->can_sample_z
= !rtex
->surface
.u
.legacy
.depth_adjusted
;
1261 rtex
->can_sample_s
= !rtex
->surface
.u
.legacy
.stencil_adjusted
;
1264 if (!(base
->flags
& (SI_RESOURCE_FLAG_TRANSFER
|
1265 SI_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1266 rtex
->db_compatible
= true;
1268 if (!(sscreen
->debug_flags
& DBG(NO_HYPERZ
)))
1269 si_texture_allocate_htile(sscreen
, rtex
);
1272 if (base
->nr_samples
> 1 &&
1274 !(sscreen
->debug_flags
& DBG(NO_FMASK
))) {
1275 si_texture_allocate_fmask(sscreen
, rtex
);
1276 si_texture_allocate_cmask(sscreen
, rtex
);
1277 rtex
->cmask_buffer
= &rtex
->resource
;
1279 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1285 /* Shared textures must always set up DCC here.
1286 * If it's not present, it will be disabled by
1287 * apply_opaque_metadata later.
1289 if (rtex
->surface
.dcc_size
&&
1290 (buf
|| !(sscreen
->debug_flags
& DBG(NO_DCC
))) &&
1291 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1292 /* Reserve space for the DCC buffer. */
1293 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1294 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1298 /* Now create the backing buffer. */
1300 si_init_resource_fields(sscreen
, resource
, rtex
->size
,
1301 rtex
->surface
.surf_alignment
);
1303 if (!si_alloc_resource(sscreen
, resource
)) {
1308 resource
->buf
= buf
;
1309 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1310 resource
->bo_size
= buf
->size
;
1311 resource
->bo_alignment
= buf
->alignment
;
1312 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1313 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1314 resource
->vram_usage
= buf
->size
;
1315 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1316 resource
->gart_usage
= buf
->size
;
1319 if (rtex
->cmask
.size
) {
1320 /* Initialize the cmask to 0xCC (= compressed state). */
1321 si_screen_clear_buffer(sscreen
, &rtex
->cmask_buffer
->b
.b
,
1322 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1325 if (rtex
->htile_offset
) {
1326 uint32_t clear_value
= 0;
1328 if (sscreen
->info
.chip_class
>= GFX9
|| rtex
->tc_compatible_htile
)
1329 clear_value
= 0x0000030F;
1331 si_screen_clear_buffer(sscreen
, &rtex
->resource
.b
.b
,
1333 rtex
->surface
.htile_size
,
1337 /* Initialize DCC only if the texture is not being imported. */
1338 if (!buf
&& rtex
->dcc_offset
) {
1339 si_screen_clear_buffer(sscreen
, &rtex
->resource
.b
.b
,
1341 rtex
->surface
.dcc_size
,
1345 /* Initialize the CMASK base register value. */
1346 rtex
->cmask
.base_address_reg
=
1347 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1349 if (sscreen
->debug_flags
& DBG(VM
)) {
1350 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1351 rtex
->resource
.gpu_address
,
1352 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1353 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+1,
1354 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1357 if (sscreen
->debug_flags
& DBG(TEX
)) {
1359 struct u_log_context log
;
1360 u_log_context_init(&log
);
1361 si_print_texture_info(sscreen
, rtex
, &log
);
1362 u_log_new_page_print(&log
, stdout
);
1364 u_log_context_destroy(&log
);
1370 static enum radeon_surf_mode
1371 si_choose_tiling(struct si_screen
*sscreen
,
1372 const struct pipe_resource
*templ
, bool tc_compatible_htile
)
1374 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1375 bool force_tiling
= templ
->flags
& SI_RESOURCE_FLAG_FORCE_TILING
;
1376 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1377 !(templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
);
1379 /* MSAA resources must be 2D tiled. */
1380 if (templ
->nr_samples
> 1)
1381 return RADEON_SURF_MODE_2D
;
1383 /* Transfer resources should be linear. */
1384 if (templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
)
1385 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1387 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
1388 * which requires 2D tiling.
1390 if (sscreen
->info
.chip_class
== VI
&& tc_compatible_htile
)
1391 return RADEON_SURF_MODE_2D
;
1393 /* Handle common candidates for the linear mode.
1394 * Compressed textures and DB surfaces must always be tiled.
1396 if (!force_tiling
&&
1397 !is_depth_stencil
&&
1398 !util_format_is_compressed(templ
->format
)) {
1399 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1400 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1402 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. */
1403 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1404 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1406 /* Cursors are linear on SI.
1407 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1408 if (templ
->bind
& PIPE_BIND_CURSOR
)
1409 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1411 if (templ
->bind
& PIPE_BIND_LINEAR
)
1412 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1414 /* Textures with a very small height are recommended to be linear. */
1415 if (templ
->target
== PIPE_TEXTURE_1D
||
1416 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1417 /* Only very thin and long 2D textures should benefit from
1418 * linear_aligned. */
1419 (templ
->width0
> 8 && templ
->height0
<= 2))
1420 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1422 /* Textures likely to be mapped often. */
1423 if (templ
->usage
== PIPE_USAGE_STAGING
||
1424 templ
->usage
== PIPE_USAGE_STREAM
)
1425 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1428 /* Make small textures 1D tiled. */
1429 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1430 (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1431 return RADEON_SURF_MODE_1D
;
1433 /* The allocator will switch to 1D if needed. */
1434 return RADEON_SURF_MODE_2D
;
1437 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1438 const struct pipe_resource
*templ
)
1440 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1441 struct radeon_surf surface
= {0};
1442 bool is_flushed_depth
= templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1443 bool tc_compatible_htile
=
1444 sscreen
->info
.chip_class
>= VI
&&
1445 /* There are issues with TC-compatible HTILE on Tonga (and
1446 * Iceland is the same design), and documented bug workarounds
1447 * don't help. For example, this fails:
1448 * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow -auto
1450 sscreen
->info
.family
!= CHIP_TONGA
&&
1451 sscreen
->info
.family
!= CHIP_ICELAND
&&
1452 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1453 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) &&
1454 !is_flushed_depth
&&
1455 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1456 util_format_is_depth_or_stencil(templ
->format
);
1460 r
= si_init_surface(sscreen
, &surface
, templ
,
1461 si_choose_tiling(sscreen
, templ
, tc_compatible_htile
),
1462 0, 0, false, false, is_flushed_depth
,
1463 tc_compatible_htile
);
1468 return (struct pipe_resource
*)
1469 si_texture_create_object(screen
, templ
, NULL
, &surface
);
1472 static struct pipe_resource
*si_texture_from_handle(struct pipe_screen
*screen
,
1473 const struct pipe_resource
*templ
,
1474 struct winsys_handle
*whandle
,
1477 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1478 struct pb_buffer
*buf
= NULL
;
1479 unsigned stride
= 0, offset
= 0;
1480 enum radeon_surf_mode array_mode
;
1481 struct radeon_surf surface
= {};
1483 struct radeon_bo_metadata metadata
= {};
1484 struct r600_texture
*rtex
;
1487 /* Support only 2D textures without mipmaps */
1488 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1489 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1492 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
, &stride
, &offset
);
1496 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1497 si_surface_import_metadata(sscreen
, &surface
, &metadata
,
1498 &array_mode
, &is_scanout
);
1500 r
= si_init_surface(sscreen
, &surface
, templ
, array_mode
, stride
,
1501 offset
, true, is_scanout
, false, false);
1506 rtex
= si_texture_create_object(screen
, templ
, buf
, &surface
);
1510 rtex
->resource
.b
.is_shared
= true;
1511 rtex
->resource
.external_usage
= usage
;
1513 si_apply_opaque_metadata(sscreen
, rtex
, &metadata
);
1515 assert(rtex
->surface
.tile_swizzle
== 0);
1516 return &rtex
->resource
.b
.b
;
1519 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1520 struct pipe_resource
*texture
,
1521 struct r600_texture
**staging
)
1523 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1524 struct pipe_resource resource
;
1525 struct r600_texture
**flushed_depth_texture
= staging
?
1526 staging
: &rtex
->flushed_depth_texture
;
1527 enum pipe_format pipe_format
= texture
->format
;
1530 if (rtex
->flushed_depth_texture
)
1531 return true; /* it's ready */
1533 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1534 switch (pipe_format
) {
1535 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1536 /* Save memory by not allocating the S plane. */
1537 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1539 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1540 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1541 /* Save memory bandwidth by not copying the
1542 * stencil part during flush.
1544 * This potentially increases memory bandwidth
1545 * if an application uses both Z and S texturing
1546 * simultaneously (a flushed Z24S8 texture
1547 * would be stored compactly), but how often
1548 * does that really happen?
1550 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1554 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1555 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1557 /* DB->CB copies to an 8bpp surface don't work. */
1558 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1562 memset(&resource
, 0, sizeof(resource
));
1563 resource
.target
= texture
->target
;
1564 resource
.format
= pipe_format
;
1565 resource
.width0
= texture
->width0
;
1566 resource
.height0
= texture
->height0
;
1567 resource
.depth0
= texture
->depth0
;
1568 resource
.array_size
= texture
->array_size
;
1569 resource
.last_level
= texture
->last_level
;
1570 resource
.nr_samples
= texture
->nr_samples
;
1571 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1572 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1573 resource
.flags
= texture
->flags
| SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1576 resource
.flags
|= SI_RESOURCE_FLAG_TRANSFER
;
1578 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1579 if (*flushed_depth_texture
== NULL
) {
1580 PRINT_ERR("failed to create temporary texture to hold flushed depth\n");
1587 * Initialize the pipe_resource descriptor to be of the same size as the box,
1588 * which is supposed to hold a subregion of the texture "orig" at the given
1591 static void si_init_temp_resource_from_box(struct pipe_resource
*res
,
1592 struct pipe_resource
*orig
,
1593 const struct pipe_box
*box
,
1594 unsigned level
, unsigned flags
)
1596 memset(res
, 0, sizeof(*res
));
1597 res
->format
= orig
->format
;
1598 res
->width0
= box
->width
;
1599 res
->height0
= box
->height
;
1601 res
->array_size
= 1;
1602 res
->usage
= flags
& SI_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1605 /* We must set the correct texture target and dimensions for a 3D box. */
1606 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1607 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1608 res
->array_size
= box
->depth
;
1610 res
->target
= PIPE_TEXTURE_2D
;
1614 static bool si_can_invalidate_texture(struct si_screen
*sscreen
,
1615 struct r600_texture
*rtex
,
1616 unsigned transfer_usage
,
1617 const struct pipe_box
*box
)
1619 return !rtex
->resource
.b
.is_shared
&&
1620 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1621 rtex
->resource
.b
.b
.last_level
== 0 &&
1622 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1623 box
->x
, box
->y
, box
->z
,
1624 box
->width
, box
->height
,
1628 static void si_texture_invalidate_storage(struct si_context
*sctx
,
1629 struct r600_texture
*rtex
)
1631 struct si_screen
*sscreen
= sctx
->screen
;
1633 /* There is no point in discarding depth and tiled buffers. */
1634 assert(!rtex
->is_depth
);
1635 assert(rtex
->surface
.is_linear
);
1637 /* Reallocate the buffer in the same pipe_resource. */
1638 si_alloc_resource(sscreen
, &rtex
->resource
);
1640 /* Initialize the CMASK base address (needed even without CMASK). */
1641 rtex
->cmask
.base_address_reg
=
1642 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1644 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1646 sctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1649 static void *si_texture_transfer_map(struct pipe_context
*ctx
,
1650 struct pipe_resource
*texture
,
1653 const struct pipe_box
*box
,
1654 struct pipe_transfer
**ptransfer
)
1656 struct si_context
*sctx
= (struct si_context
*)ctx
;
1657 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1658 struct r600_transfer
*trans
;
1659 struct r600_resource
*buf
;
1660 unsigned offset
= 0;
1662 bool use_staging_texture
= false;
1664 assert(!(texture
->flags
& SI_RESOURCE_FLAG_TRANSFER
));
1665 assert(box
->width
&& box
->height
&& box
->depth
);
1667 /* Depth textures use staging unconditionally. */
1668 if (!rtex
->is_depth
) {
1669 /* Degrade the tile mode if we get too many transfers on APUs.
1670 * On dGPUs, the staging texture is always faster.
1671 * Only count uploads that are at least 4x4 pixels large.
1673 if (!sctx
->screen
->info
.has_dedicated_vram
&&
1675 box
->width
>= 4 && box
->height
>= 4 &&
1676 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1677 bool can_invalidate
=
1678 si_can_invalidate_texture(sctx
->screen
, rtex
,
1681 si_reallocate_texture_inplace(sctx
, rtex
,
1686 /* Tiled textures need to be converted into a linear texture for CPU
1687 * access. The staging texture is always linear and is placed in GART.
1689 * Reading from VRAM or GTT WC is slow, always use the staging
1690 * texture in this case.
1692 * Use the staging texture for uploads if the underlying BO
1695 if (!rtex
->surface
.is_linear
)
1696 use_staging_texture
= true;
1697 else if (usage
& PIPE_TRANSFER_READ
)
1698 use_staging_texture
=
1699 rtex
->resource
.domains
& RADEON_DOMAIN_VRAM
||
1700 rtex
->resource
.flags
& RADEON_FLAG_GTT_WC
;
1701 /* Write & linear only: */
1702 else if (si_rings_is_buffer_referenced(sctx
, rtex
->resource
.buf
,
1703 RADEON_USAGE_READWRITE
) ||
1704 !sctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1705 RADEON_USAGE_READWRITE
)) {
1707 if (si_can_invalidate_texture(sctx
->screen
, rtex
,
1709 si_texture_invalidate_storage(sctx
, rtex
);
1711 use_staging_texture
= true;
1715 trans
= CALLOC_STRUCT(r600_transfer
);
1718 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1719 trans
->b
.b
.level
= level
;
1720 trans
->b
.b
.usage
= usage
;
1721 trans
->b
.b
.box
= *box
;
1723 if (rtex
->is_depth
) {
1724 struct r600_texture
*staging_depth
;
1726 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1727 /* MSAA depth buffers need to be converted to single sample buffers.
1729 * Mapping MSAA depth buffers can occur if ReadPixels is called
1730 * with a multisample GLX visual.
1732 * First downsample the depth buffer to a temporary texture,
1733 * then decompress the temporary one to staging.
1735 * Only the region being mapped is transfered.
1737 struct pipe_resource resource
;
1739 si_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1741 if (!si_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1742 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1747 if (usage
& PIPE_TRANSFER_READ
) {
1748 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1750 PRINT_ERR("failed to create a temporary depth texture\n");
1755 si_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1756 si_blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1757 0, 0, 0, box
->depth
, 0, 0);
1758 pipe_resource_reference(&temp
, NULL
);
1761 /* Just get the strides. */
1762 si_texture_get_offset(sctx
->screen
, staging_depth
, level
, NULL
,
1764 &trans
->b
.b
.layer_stride
);
1766 /* XXX: only readback the rectangle which is being mapped? */
1767 /* XXX: when discard is true, no need to read back from depth texture */
1768 if (!si_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1769 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1774 si_blit_decompress_depth(ctx
, rtex
, staging_depth
,
1776 box
->z
, box
->z
+ box
->depth
- 1,
1779 offset
= si_texture_get_offset(sctx
->screen
, staging_depth
,
1782 &trans
->b
.b
.layer_stride
);
1785 trans
->staging
= (struct r600_resource
*)staging_depth
;
1786 buf
= trans
->staging
;
1787 } else if (use_staging_texture
) {
1788 struct pipe_resource resource
;
1789 struct r600_texture
*staging
;
1791 si_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1792 SI_RESOURCE_FLAG_TRANSFER
);
1793 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1794 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1796 /* Create the temporary texture. */
1797 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1799 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1803 trans
->staging
= &staging
->resource
;
1805 /* Just get the strides. */
1806 si_texture_get_offset(sctx
->screen
, staging
, 0, NULL
,
1808 &trans
->b
.b
.layer_stride
);
1810 if (usage
& PIPE_TRANSFER_READ
)
1811 si_copy_to_staging_texture(ctx
, trans
);
1813 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1815 buf
= trans
->staging
;
1817 /* the resource is mapped directly */
1818 offset
= si_texture_get_offset(sctx
->screen
, rtex
, level
, box
,
1820 &trans
->b
.b
.layer_stride
);
1821 buf
= &rtex
->resource
;
1824 if (!(map
= si_buffer_map_sync_with_rings(sctx
, buf
, usage
))) {
1825 r600_resource_reference(&trans
->staging
, NULL
);
1830 *ptransfer
= &trans
->b
.b
;
1831 return map
+ offset
;
1834 static void si_texture_transfer_unmap(struct pipe_context
*ctx
,
1835 struct pipe_transfer
* transfer
)
1837 struct si_context
*sctx
= (struct si_context
*)ctx
;
1838 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1839 struct pipe_resource
*texture
= transfer
->resource
;
1840 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1842 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1843 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1844 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1845 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1846 &rtransfer
->staging
->b
.b
, transfer
->level
,
1849 si_copy_from_staging_texture(ctx
, rtransfer
);
1853 if (rtransfer
->staging
) {
1854 sctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1855 r600_resource_reference(&rtransfer
->staging
, NULL
);
1858 /* Heuristic for {upload, draw, upload, draw, ..}:
1860 * Flush the gfx IB if we've allocated too much texture storage.
1862 * The idea is that we don't want to build IBs that use too much
1863 * memory and put pressure on the kernel memory manager and we also
1864 * want to make temporary and invalidated buffers go idle ASAP to
1865 * decrease the total memory usage or make them reusable. The memory
1866 * usage will be slightly higher than given here because of the buffer
1867 * cache in the winsys.
1869 * The result is that the kernel memory manager is never a bottleneck.
1871 if (sctx
->num_alloc_tex_transfer_bytes
> sctx
->screen
->info
.gart_size
/ 4) {
1872 si_flush_gfx_cs(sctx
, PIPE_FLUSH_ASYNC
, NULL
);
1873 sctx
->num_alloc_tex_transfer_bytes
= 0;
1876 pipe_resource_reference(&transfer
->resource
, NULL
);
1880 static const struct u_resource_vtbl si_texture_vtbl
=
1882 NULL
, /* get_handle */
1883 si_texture_destroy
, /* resource_destroy */
1884 si_texture_transfer_map
, /* transfer_map */
1885 u_default_transfer_flush_region
, /* transfer_flush_region */
1886 si_texture_transfer_unmap
, /* transfer_unmap */
1889 /* DCC channel type categories within which formats can be reinterpreted
1890 * while keeping the same DCC encoding. The swizzle must also match. */
1891 enum dcc_channel_type
{
1893 /* uint and sint can be merged if we never use TC-compatible DCC clear
1894 * encoding with the clear value of 1. */
1897 dcc_channel_uint_10_10_10_2
,
1898 dcc_channel_incompatible
,
1901 /* Return the type of DCC encoding. */
1902 static enum dcc_channel_type
1903 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1907 /* Find the first non-void channel. */
1908 for (i
= 0; i
< desc
->nr_channels
; i
++)
1909 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1911 if (i
== desc
->nr_channels
)
1912 return dcc_channel_incompatible
;
1914 switch (desc
->channel
[i
].size
) {
1918 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1919 return dcc_channel_float
;
1920 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1921 return dcc_channel_uint
;
1922 return dcc_channel_sint
;
1924 return dcc_channel_uint_10_10_10_2
;
1926 return dcc_channel_incompatible
;
1930 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1931 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1932 enum pipe_format format2
)
1934 const struct util_format_description
*desc1
, *desc2
;
1935 enum dcc_channel_type type1
, type2
;
1938 if (format1
== format2
)
1941 desc1
= util_format_description(format1
);
1942 desc2
= util_format_description(format2
);
1944 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1947 /* Swizzles must be the same. */
1948 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1949 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1950 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1951 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1954 type1
= vi_get_dcc_channel_type(desc1
);
1955 type2
= vi_get_dcc_channel_type(desc2
);
1957 return type1
!= dcc_channel_incompatible
&&
1958 type2
!= dcc_channel_incompatible
&&
1962 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1964 enum pipe_format view_format
)
1966 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1968 return vi_dcc_enabled(rtex
, level
) &&
1969 !vi_dcc_formats_compatible(tex
->format
, view_format
);
1972 /* This can't be merged with the above function, because
1973 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
1974 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
1975 struct pipe_resource
*tex
,
1977 enum pipe_format view_format
)
1979 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1981 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
1982 if (!si_texture_disable_dcc(sctx
, (struct r600_texture
*)tex
))
1983 si_decompress_dcc(sctx
, rtex
);
1986 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1987 struct pipe_resource
*texture
,
1988 const struct pipe_surface
*templ
,
1989 unsigned width0
, unsigned height0
,
1990 unsigned width
, unsigned height
)
1992 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1997 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1998 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2000 pipe_reference_init(&surface
->base
.reference
, 1);
2001 pipe_resource_reference(&surface
->base
.texture
, texture
);
2002 surface
->base
.context
= pipe
;
2003 surface
->base
.format
= templ
->format
;
2004 surface
->base
.width
= width
;
2005 surface
->base
.height
= height
;
2006 surface
->base
.u
= templ
->u
;
2008 surface
->width0
= width0
;
2009 surface
->height0
= height0
;
2011 surface
->dcc_incompatible
=
2012 texture
->target
!= PIPE_BUFFER
&&
2013 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
2015 return &surface
->base
;
2018 static struct pipe_surface
*si_create_surface(struct pipe_context
*pipe
,
2019 struct pipe_resource
*tex
,
2020 const struct pipe_surface
*templ
)
2022 unsigned level
= templ
->u
.tex
.level
;
2023 unsigned width
= u_minify(tex
->width0
, level
);
2024 unsigned height
= u_minify(tex
->height0
, level
);
2025 unsigned width0
= tex
->width0
;
2026 unsigned height0
= tex
->height0
;
2028 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2029 const struct util_format_description
*tex_desc
2030 = util_format_description(tex
->format
);
2031 const struct util_format_description
*templ_desc
2032 = util_format_description(templ
->format
);
2034 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2036 /* Adjust size of surface if and only if the block width or
2037 * height is changed. */
2038 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2039 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2040 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2041 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2043 width
= nblks_x
* templ_desc
->block
.width
;
2044 height
= nblks_y
* templ_desc
->block
.height
;
2046 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2047 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2051 return si_create_surface_custom(pipe
, tex
, templ
,
2056 static void si_surface_destroy(struct pipe_context
*pipe
,
2057 struct pipe_surface
*surface
)
2059 pipe_resource_reference(&surface
->texture
, NULL
);
2063 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2065 const struct util_format_description
*desc
= util_format_description(format
);
2067 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2069 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2070 return V_028C70_SWAP_STD
;
2072 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2075 switch (desc
->nr_channels
) {
2077 if (HAS_SWIZZLE(0,X
))
2078 return V_028C70_SWAP_STD
; /* X___ */
2079 else if (HAS_SWIZZLE(3,X
))
2080 return V_028C70_SWAP_ALT_REV
; /* ___X */
2083 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2084 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2085 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2086 return V_028C70_SWAP_STD
; /* XY__ */
2087 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2088 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2089 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2091 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2092 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2093 return V_028C70_SWAP_ALT
; /* X__Y */
2094 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2095 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2098 if (HAS_SWIZZLE(0,X
))
2099 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2100 else if (HAS_SWIZZLE(0,Z
))
2101 return V_028C70_SWAP_STD_REV
; /* ZYX */
2104 /* check the middle channels, the 1st and 4th channel can be NONE */
2105 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2106 return V_028C70_SWAP_STD
; /* XYZW */
2107 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2108 return V_028C70_SWAP_STD_REV
; /* WZYX */
2109 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2110 return V_028C70_SWAP_ALT
; /* ZYXW */
2111 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2114 return V_028C70_SWAP_ALT_REV
;
2116 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2123 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2125 static void vi_dcc_clean_up_context_slot(struct si_context
*sctx
,
2130 if (sctx
->dcc_stats
[slot
].query_active
)
2131 vi_separate_dcc_stop_query(sctx
,
2132 sctx
->dcc_stats
[slot
].tex
);
2134 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
[slot
].ps_stats
); i
++)
2135 if (sctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2136 sctx
->b
.destroy_query(&sctx
->b
,
2137 sctx
->dcc_stats
[slot
].ps_stats
[i
]);
2138 sctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2141 r600_texture_reference(&sctx
->dcc_stats
[slot
].tex
, NULL
);
2145 * Return the per-context slot where DCC statistics queries for the texture live.
2147 static unsigned vi_get_context_dcc_stats_index(struct si_context
*sctx
,
2148 struct r600_texture
*tex
)
2150 int i
, empty_slot
= -1;
2152 /* Remove zombie textures (textures kept alive by this array only). */
2153 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2154 if (sctx
->dcc_stats
[i
].tex
&&
2155 sctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
2156 vi_dcc_clean_up_context_slot(sctx
, i
);
2158 /* Find the texture. */
2159 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
2160 /* Return if found. */
2161 if (sctx
->dcc_stats
[i
].tex
== tex
) {
2162 sctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2166 /* Record the first seen empty slot. */
2167 if (empty_slot
== -1 && !sctx
->dcc_stats
[i
].tex
)
2171 /* Not found. Remove the oldest member to make space in the array. */
2172 if (empty_slot
== -1) {
2173 int oldest_slot
= 0;
2175 /* Find the oldest slot. */
2176 for (i
= 1; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2177 if (sctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2178 sctx
->dcc_stats
[i
].last_use_timestamp
)
2181 /* Clean up the oldest slot. */
2182 vi_dcc_clean_up_context_slot(sctx
, oldest_slot
);
2183 empty_slot
= oldest_slot
;
2186 /* Add the texture to the new slot. */
2187 r600_texture_reference(&sctx
->dcc_stats
[empty_slot
].tex
, tex
);
2188 sctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2192 static struct pipe_query
*
2193 vi_create_resuming_pipestats_query(struct si_context
*sctx
)
2195 struct si_query_hw
*query
= (struct si_query_hw
*)
2196 sctx
->b
.create_query(&sctx
->b
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2198 query
->flags
|= SI_QUERY_HW_FLAG_BEGIN_RESUMES
;
2199 return (struct pipe_query
*)query
;
2203 * Called when binding a color buffer.
2205 void vi_separate_dcc_start_query(struct si_context
*sctx
,
2206 struct r600_texture
*tex
)
2208 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2210 assert(!sctx
->dcc_stats
[i
].query_active
);
2212 if (!sctx
->dcc_stats
[i
].ps_stats
[0])
2213 sctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(sctx
);
2215 /* begin or resume the query */
2216 sctx
->b
.begin_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2217 sctx
->dcc_stats
[i
].query_active
= true;
2221 * Called when unbinding a color buffer.
2223 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
2224 struct r600_texture
*tex
)
2226 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2228 assert(sctx
->dcc_stats
[i
].query_active
);
2229 assert(sctx
->dcc_stats
[i
].ps_stats
[0]);
2231 /* pause or end the query */
2232 sctx
->b
.end_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2233 sctx
->dcc_stats
[i
].query_active
= false;
2236 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2238 /* The minimum number of fullscreen draws per frame that is required
2240 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2243 /* Called by fast clear. */
2244 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
2245 struct r600_texture
*tex
)
2247 /* The intent is to use this with shared displayable back buffers,
2248 * but it's not strictly limited only to them.
2250 if (!tex
->resource
.b
.is_shared
||
2251 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2252 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2253 tex
->resource
.b
.b
.last_level
> 0 ||
2254 !tex
->surface
.dcc_size
)
2257 if (tex
->dcc_offset
)
2258 return; /* already enabled */
2260 /* Enable the DCC stat gathering. */
2261 if (!tex
->dcc_gather_statistics
) {
2262 tex
->dcc_gather_statistics
= true;
2263 vi_separate_dcc_start_query(sctx
, tex
);
2266 if (!vi_should_enable_separate_dcc(tex
))
2267 return; /* stats show that DCC decompression is too expensive */
2269 assert(tex
->surface
.num_dcc_levels
);
2270 assert(!tex
->dcc_separate_buffer
);
2272 si_texture_discard_cmask(sctx
->screen
, tex
);
2274 /* Get a DCC buffer. */
2275 if (tex
->last_dcc_separate_buffer
) {
2276 assert(tex
->dcc_gather_statistics
);
2277 assert(!tex
->dcc_separate_buffer
);
2278 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2279 tex
->last_dcc_separate_buffer
= NULL
;
2281 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2282 si_aligned_buffer_create(sctx
->b
.screen
,
2283 SI_RESOURCE_FLAG_UNMAPPABLE
,
2285 tex
->surface
.dcc_size
,
2286 tex
->surface
.dcc_alignment
);
2287 if (!tex
->dcc_separate_buffer
)
2291 /* dcc_offset is the absolute GPUVM address. */
2292 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2294 /* no need to flag anything since this is called by fast clear that
2295 * flags framebuffer state
2300 * Called by pipe_context::flush_resource, the place where DCC decompression
2303 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2304 struct r600_texture
*tex
)
2306 struct si_context
*sctx
= (struct si_context
*)ctx
;
2307 struct pipe_query
*tmp
;
2308 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2309 bool query_active
= sctx
->dcc_stats
[i
].query_active
;
2310 bool disable
= false;
2312 if (sctx
->dcc_stats
[i
].ps_stats
[2]) {
2313 union pipe_query_result result
;
2315 /* Read the results. */
2316 ctx
->get_query_result(ctx
, sctx
->dcc_stats
[i
].ps_stats
[2],
2318 si_query_hw_reset_buffers(sctx
,
2319 (struct si_query_hw
*)
2320 sctx
->dcc_stats
[i
].ps_stats
[2]);
2322 /* Compute the approximate number of fullscreen draws. */
2323 tex
->ps_draw_ratio
=
2324 result
.pipeline_statistics
.ps_invocations
/
2325 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2326 sctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2328 disable
= tex
->dcc_separate_buffer
&&
2329 !vi_should_enable_separate_dcc(tex
);
2332 tex
->num_slow_clears
= 0;
2334 /* stop the statistics query for ps_stats[0] */
2336 vi_separate_dcc_stop_query(sctx
, tex
);
2338 /* Move the queries in the queue by one. */
2339 tmp
= sctx
->dcc_stats
[i
].ps_stats
[2];
2340 sctx
->dcc_stats
[i
].ps_stats
[2] = sctx
->dcc_stats
[i
].ps_stats
[1];
2341 sctx
->dcc_stats
[i
].ps_stats
[1] = sctx
->dcc_stats
[i
].ps_stats
[0];
2342 sctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2344 /* create and start a new query as ps_stats[0] */
2346 vi_separate_dcc_start_query(sctx
, tex
);
2349 assert(!tex
->last_dcc_separate_buffer
);
2350 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2351 tex
->dcc_separate_buffer
= NULL
;
2352 tex
->dcc_offset
= 0;
2353 /* no need to flag anything since this is called after
2354 * decompression that re-sets framebuffer state
2359 static struct pipe_memory_object
*
2360 si_memobj_from_handle(struct pipe_screen
*screen
,
2361 struct winsys_handle
*whandle
,
2364 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2365 struct r600_memory_object
*memobj
= CALLOC_STRUCT(r600_memory_object
);
2366 struct pb_buffer
*buf
= NULL
;
2367 uint32_t stride
, offset
;
2372 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
2379 memobj
->b
.dedicated
= dedicated
;
2381 memobj
->stride
= stride
;
2382 memobj
->offset
= offset
;
2384 return (struct pipe_memory_object
*)memobj
;
2389 si_memobj_destroy(struct pipe_screen
*screen
,
2390 struct pipe_memory_object
*_memobj
)
2392 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2394 pb_reference(&memobj
->buf
, NULL
);
2398 static struct pipe_resource
*
2399 si_texture_from_memobj(struct pipe_screen
*screen
,
2400 const struct pipe_resource
*templ
,
2401 struct pipe_memory_object
*_memobj
,
2405 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2406 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2407 struct r600_texture
*rtex
;
2408 struct radeon_surf surface
= {};
2409 struct radeon_bo_metadata metadata
= {};
2410 enum radeon_surf_mode array_mode
;
2412 struct pb_buffer
*buf
= NULL
;
2414 if (memobj
->b
.dedicated
) {
2415 sscreen
->ws
->buffer_get_metadata(memobj
->buf
, &metadata
);
2416 si_surface_import_metadata(sscreen
, &surface
, &metadata
,
2417 &array_mode
, &is_scanout
);
2420 * The bo metadata is unset for un-dedicated images. So we fall
2421 * back to linear. See answer to question 5 of the
2422 * VK_KHX_external_memory spec for some details.
2424 * It is possible that this case isn't going to work if the
2425 * surface pitch isn't correctly aligned by default.
2427 * In order to support it correctly we require multi-image
2428 * metadata to be syncrhonized between radv and radeonsi. The
2429 * semantics of associating multiple image metadata to a memory
2430 * object on the vulkan export side are not concretely defined
2433 * All the use cases we are aware of at the moment for memory
2434 * objects use dedicated allocations. So lets keep the initial
2435 * implementation simple.
2437 * A possible alternative is to attempt to reconstruct the
2438 * tiling information when the TexParameter TEXTURE_TILING_EXT
2441 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
2446 r
= si_init_surface(sscreen
, &surface
, templ
,
2447 array_mode
, memobj
->stride
,
2448 offset
, true, is_scanout
,
2453 rtex
= si_texture_create_object(screen
, templ
, memobj
->buf
, &surface
);
2457 /* r600_texture_create_object doesn't increment refcount of
2458 * memobj->buf, so increment it here.
2460 pb_reference(&buf
, memobj
->buf
);
2462 rtex
->resource
.b
.is_shared
= true;
2463 rtex
->resource
.external_usage
= PIPE_HANDLE_USAGE_READ_WRITE
;
2465 si_apply_opaque_metadata(sscreen
, rtex
, &metadata
);
2467 return &rtex
->resource
.b
.b
;
2470 static bool si_check_resource_capability(struct pipe_screen
*screen
,
2471 struct pipe_resource
*resource
,
2474 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
2476 /* Buffers only support the linear flag. */
2477 if (resource
->target
== PIPE_BUFFER
)
2478 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2480 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2483 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2486 /* TODO: PIPE_BIND_CURSOR - do we care? */
2490 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2492 sscreen
->b
.resource_from_handle
= si_texture_from_handle
;
2493 sscreen
->b
.resource_get_handle
= si_texture_get_handle
;
2494 sscreen
->b
.resource_from_memobj
= si_texture_from_memobj
;
2495 sscreen
->b
.memobj_create_from_handle
= si_memobj_from_handle
;
2496 sscreen
->b
.memobj_destroy
= si_memobj_destroy
;
2497 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2500 void si_init_context_texture_functions(struct si_context
*sctx
)
2502 sctx
->b
.create_surface
= si_create_surface
;
2503 sctx
->b
.surface_destroy
= si_surface_destroy
;