2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeonsi/si_pipe.h"
27 #include "radeonsi/si_query.h"
28 #include "util/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/u_resource.h"
33 #include "util/u_surface.h"
34 #include "util/u_transfer.h"
35 #include "util/os_time.h"
38 #include "state_tracker/drm_driver.h"
39 #include "amd/common/sid.h"
41 static enum radeon_surf_mode
42 si_choose_tiling(struct si_screen
*sscreen
,
43 const struct pipe_resource
*templ
, bool tc_compatible_htile
);
46 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
47 struct r600_texture
*rdst
,
48 unsigned dst_level
, unsigned dstx
,
49 unsigned dsty
, unsigned dstz
,
50 struct r600_texture
*rsrc
,
52 const struct pipe_box
*src_box
)
57 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
60 /* MSAA: Blits don't exist in the real world. */
61 if (rsrc
->buffer
.b
.b
.nr_samples
> 1 ||
62 rdst
->buffer
.b
.b
.nr_samples
> 1)
65 /* Depth-stencil surfaces:
66 * When dst is linear, the DB->CB copy preserves HTILE.
67 * When dst is tiled, the 3D path must be used to update HTILE.
69 if (rsrc
->is_depth
|| rdst
->is_depth
)
73 * src: Use the 3D path. DCC decompression is expensive.
74 * dst: Use the 3D path to compress the pixels with DCC.
76 if (vi_dcc_enabled(rsrc
, src_level
) ||
77 vi_dcc_enabled(rdst
, dst_level
))
81 * src: Both texture and SDMA paths need decompression. Use SDMA.
82 * dst: If overwriting the whole texture, discard CMASK and use
83 * SDMA. Otherwise, use the 3D path.
85 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
86 /* The CMASK clear is only enabled for the first level. */
87 assert(dst_level
== 0);
88 if (!util_texrange_covers_whole_level(&rdst
->buffer
.b
.b
, dst_level
,
89 dstx
, dsty
, dstz
, src_box
->width
,
90 src_box
->height
, src_box
->depth
))
93 si_texture_discard_cmask(sctx
->screen
, rdst
);
96 /* All requirements are met. Prepare textures for SDMA. */
97 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
98 sctx
->b
.flush_resource(&sctx
->b
, &rsrc
->buffer
.b
.b
);
100 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
101 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
106 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
107 static void si_copy_region_with_blit(struct pipe_context
*pipe
,
108 struct pipe_resource
*dst
,
110 unsigned dstx
, unsigned dsty
, unsigned dstz
,
111 struct pipe_resource
*src
,
113 const struct pipe_box
*src_box
)
115 struct pipe_blit_info blit
;
117 memset(&blit
, 0, sizeof(blit
));
118 blit
.src
.resource
= src
;
119 blit
.src
.format
= src
->format
;
120 blit
.src
.level
= src_level
;
121 blit
.src
.box
= *src_box
;
122 blit
.dst
.resource
= dst
;
123 blit
.dst
.format
= dst
->format
;
124 blit
.dst
.level
= dst_level
;
125 blit
.dst
.box
.x
= dstx
;
126 blit
.dst
.box
.y
= dsty
;
127 blit
.dst
.box
.z
= dstz
;
128 blit
.dst
.box
.width
= src_box
->width
;
129 blit
.dst
.box
.height
= src_box
->height
;
130 blit
.dst
.box
.depth
= src_box
->depth
;
131 blit
.mask
= util_format_get_mask(src
->format
) &
132 util_format_get_mask(dst
->format
);
133 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
136 pipe
->blit(pipe
, &blit
);
140 /* Copy from a full GPU texture to a transfer's staging one. */
141 static void si_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
143 struct si_context
*sctx
= (struct si_context
*)ctx
;
144 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
145 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
146 struct pipe_resource
*src
= transfer
->resource
;
148 if (src
->nr_samples
> 1) {
149 si_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
150 src
, transfer
->level
, &transfer
->box
);
154 sctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
158 /* Copy from a transfer's staging texture to a full GPU one. */
159 static void si_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
161 struct si_context
*sctx
= (struct si_context
*)ctx
;
162 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
163 struct pipe_resource
*dst
= transfer
->resource
;
164 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
165 struct pipe_box sbox
;
167 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
169 if (dst
->nr_samples
> 1) {
170 si_copy_region_with_blit(ctx
, dst
, transfer
->level
,
171 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
176 sctx
->dma_copy(ctx
, dst
, transfer
->level
,
177 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
181 static unsigned si_texture_get_offset(struct si_screen
*sscreen
,
182 struct r600_texture
*rtex
, unsigned level
,
183 const struct pipe_box
*box
,
185 unsigned *layer_stride
)
187 if (sscreen
->info
.chip_class
>= GFX9
) {
188 *stride
= rtex
->surface
.u
.gfx9
.surf_pitch
* rtex
->surface
.bpe
;
189 *layer_stride
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
194 /* Each texture is an array of slices. Each slice is an array
195 * of mipmap levels. */
196 return box
->z
* rtex
->surface
.u
.gfx9
.surf_slice_size
+
197 rtex
->surface
.u
.gfx9
.offset
[level
] +
198 (box
->y
/ rtex
->surface
.blk_h
*
199 rtex
->surface
.u
.gfx9
.surf_pitch
+
200 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
202 *stride
= rtex
->surface
.u
.legacy
.level
[level
].nblk_x
*
204 assert((uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
205 *layer_stride
= (uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
208 return rtex
->surface
.u
.legacy
.level
[level
].offset
;
210 /* Each texture is an array of mipmap levels. Each level is
211 * an array of slices. */
212 return rtex
->surface
.u
.legacy
.level
[level
].offset
+
213 box
->z
* (uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
214 (box
->y
/ rtex
->surface
.blk_h
*
215 rtex
->surface
.u
.legacy
.level
[level
].nblk_x
+
216 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
220 static int si_init_surface(struct si_screen
*sscreen
,
221 struct radeon_surf
*surface
,
222 const struct pipe_resource
*ptex
,
223 enum radeon_surf_mode array_mode
,
224 unsigned pitch_in_bytes_override
,
228 bool is_flushed_depth
,
229 bool tc_compatible_htile
)
231 const struct util_format_description
*desc
=
232 util_format_description(ptex
->format
);
233 bool is_depth
, is_stencil
;
235 unsigned i
, bpe
, flags
= 0;
237 is_depth
= util_format_has_depth(desc
);
238 is_stencil
= util_format_has_stencil(desc
);
240 if (!is_flushed_depth
&&
241 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
242 bpe
= 4; /* stencil is allocated separately on evergreen */
244 bpe
= util_format_get_blocksize(ptex
->format
);
245 assert(util_is_power_of_two_or_zero(bpe
));
248 if (!is_flushed_depth
&& is_depth
) {
249 flags
|= RADEON_SURF_ZBUFFER
;
251 if (tc_compatible_htile
&&
252 (sscreen
->info
.chip_class
>= GFX9
||
253 array_mode
== RADEON_SURF_MODE_2D
)) {
254 /* TC-compatible HTILE only supports Z32_FLOAT.
255 * GFX9 also supports Z16_UNORM.
256 * On VI, promote Z16 to Z32. DB->CB copies will convert
257 * the format for transfers.
259 if (sscreen
->info
.chip_class
== VI
)
262 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
266 flags
|= RADEON_SURF_SBUFFER
;
269 if (sscreen
->info
.chip_class
>= VI
&&
270 (ptex
->flags
& SI_RESOURCE_FLAG_DISABLE_DCC
||
271 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
272 (ptex
->nr_samples
>= 2 && !sscreen
->dcc_msaa_allowed
)))
273 flags
|= RADEON_SURF_DISABLE_DCC
;
275 /* VI: DCC clear for 4x and 8x MSAA array textures unimplemented. */
276 if (sscreen
->info
.chip_class
== VI
&&
277 ptex
->nr_samples
>= 4 &&
278 ptex
->array_size
> 1)
279 flags
|= RADEON_SURF_DISABLE_DCC
;
281 /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
282 if (sscreen
->info
.chip_class
>= GFX9
&&
283 ptex
->nr_samples
>= 4)
284 flags
|= RADEON_SURF_DISABLE_DCC
;
286 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
287 /* This should catch bugs in gallium users setting incorrect flags. */
288 assert(ptex
->nr_samples
<= 1 &&
289 ptex
->array_size
== 1 &&
291 ptex
->last_level
== 0 &&
292 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
294 flags
|= RADEON_SURF_SCANOUT
;
297 if (ptex
->bind
& PIPE_BIND_SHARED
)
298 flags
|= RADEON_SURF_SHAREABLE
;
300 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
301 if (!(ptex
->flags
& SI_RESOURCE_FLAG_FORCE_TILING
))
302 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
304 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, ptex
->nr_samples
,
305 flags
, bpe
, array_mode
, surface
);
310 unsigned pitch
= pitch_in_bytes_override
/ bpe
;
312 if (sscreen
->info
.chip_class
>= GFX9
) {
314 surface
->u
.gfx9
.surf_pitch
= pitch
;
315 surface
->u
.gfx9
.surf_slice_size
=
316 (uint64_t)pitch
* surface
->u
.gfx9
.surf_height
* bpe
;
318 surface
->u
.gfx9
.surf_offset
= offset
;
321 surface
->u
.legacy
.level
[0].nblk_x
= pitch
;
322 surface
->u
.legacy
.level
[0].slice_size_dw
=
323 ((uint64_t)pitch
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
326 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
327 surface
->u
.legacy
.level
[i
].offset
+= offset
;
333 static void si_texture_init_metadata(struct si_screen
*sscreen
,
334 struct r600_texture
*rtex
,
335 struct radeon_bo_metadata
*metadata
)
337 struct radeon_surf
*surface
= &rtex
->surface
;
339 memset(metadata
, 0, sizeof(*metadata
));
341 if (sscreen
->info
.chip_class
>= GFX9
) {
342 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
344 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
345 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
346 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
347 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
348 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
349 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
350 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
351 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
352 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
353 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
354 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
355 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
359 static void si_surface_import_metadata(struct si_screen
*sscreen
,
360 struct radeon_surf
*surf
,
361 struct radeon_bo_metadata
*metadata
,
362 enum radeon_surf_mode
*array_mode
,
365 if (sscreen
->info
.chip_class
>= GFX9
) {
366 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
367 *array_mode
= RADEON_SURF_MODE_2D
;
369 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
371 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
372 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
374 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
376 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
377 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
378 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
379 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
380 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
381 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
383 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
384 *array_mode
= RADEON_SURF_MODE_2D
;
385 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
386 *array_mode
= RADEON_SURF_MODE_1D
;
388 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
390 *is_scanout
= metadata
->u
.legacy
.scanout
;
394 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
395 struct r600_texture
*rtex
)
397 struct si_screen
*sscreen
= sctx
->screen
;
398 struct pipe_context
*ctx
= &sctx
->b
;
400 if (ctx
== sscreen
->aux_context
)
401 mtx_lock(&sscreen
->aux_context_lock
);
403 unsigned n
= sctx
->num_decompress_calls
;
404 ctx
->flush_resource(ctx
, &rtex
->buffer
.b
.b
);
406 /* Flush only if any fast clear elimination took place. */
407 if (n
!= sctx
->num_decompress_calls
)
408 ctx
->flush(ctx
, NULL
, 0);
410 if (ctx
== sscreen
->aux_context
)
411 mtx_unlock(&sscreen
->aux_context_lock
);
414 void si_texture_discard_cmask(struct si_screen
*sscreen
,
415 struct r600_texture
*rtex
)
417 if (!rtex
->cmask
.size
)
420 assert(rtex
->buffer
.b
.b
.nr_samples
<= 1);
423 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
424 rtex
->cmask
.base_address_reg
= rtex
->buffer
.gpu_address
>> 8;
425 rtex
->dirty_level_mask
= 0;
427 rtex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
429 if (rtex
->cmask_buffer
!= &rtex
->buffer
)
430 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
432 /* Notify all contexts about the change. */
433 p_atomic_inc(&sscreen
->dirty_tex_counter
);
434 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
437 static bool si_can_disable_dcc(struct r600_texture
*rtex
)
439 /* We can't disable DCC if it can be written by another process. */
440 return rtex
->dcc_offset
&&
441 (!rtex
->buffer
.b
.is_shared
||
442 !(rtex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
445 static bool si_texture_discard_dcc(struct si_screen
*sscreen
,
446 struct r600_texture
*rtex
)
448 if (!si_can_disable_dcc(rtex
))
451 assert(rtex
->dcc_separate_buffer
== NULL
);
454 rtex
->dcc_offset
= 0;
456 /* Notify all contexts about the change. */
457 p_atomic_inc(&sscreen
->dirty_tex_counter
);
462 * Disable DCC for the texture. (first decompress, then discard metadata).
464 * There is unresolved multi-context synchronization issue between
465 * screen::aux_context and the current context. If applications do this with
466 * multiple contexts, it's already undefined behavior for them and we don't
467 * have to worry about that. The scenario is:
469 * If context 1 disables DCC and context 2 has queued commands that write
470 * to the texture via CB with DCC enabled, and the order of operations is
472 * context 2 queues draw calls rendering to the texture, but doesn't flush
473 * context 1 disables DCC and flushes
474 * context 1 & 2 reset descriptors and FB state
475 * context 2 flushes (new compressed tiles written by the draw calls)
476 * context 1 & 2 read garbage, because DCC is disabled, yet there are
479 * \param sctx the current context if you have one, or rscreen->aux_context
482 bool si_texture_disable_dcc(struct si_context
*sctx
,
483 struct r600_texture
*rtex
)
485 struct si_screen
*sscreen
= sctx
->screen
;
487 if (!si_can_disable_dcc(rtex
))
490 if (&sctx
->b
== sscreen
->aux_context
)
491 mtx_lock(&sscreen
->aux_context_lock
);
493 /* Decompress DCC. */
494 si_decompress_dcc(sctx
, rtex
);
495 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
497 if (&sctx
->b
== sscreen
->aux_context
)
498 mtx_unlock(&sscreen
->aux_context_lock
);
500 return si_texture_discard_dcc(sscreen
, rtex
);
503 static void si_reallocate_texture_inplace(struct si_context
*sctx
,
504 struct r600_texture
*rtex
,
505 unsigned new_bind_flag
,
506 bool invalidate_storage
)
508 struct pipe_screen
*screen
= sctx
->b
.screen
;
509 struct r600_texture
*new_tex
;
510 struct pipe_resource templ
= rtex
->buffer
.b
.b
;
513 templ
.bind
|= new_bind_flag
;
515 if (rtex
->buffer
.b
.is_shared
)
518 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
519 if (rtex
->surface
.is_linear
)
522 /* This fails with MSAA, depth, and compressed textures. */
523 if (si_choose_tiling(sctx
->screen
, &templ
, false) !=
524 RADEON_SURF_MODE_LINEAR_ALIGNED
)
528 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
532 /* Copy the pixels to the new texture. */
533 if (!invalidate_storage
) {
534 for (i
= 0; i
<= templ
.last_level
; i
++) {
538 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
539 util_num_layers(&templ
, i
), &box
);
541 sctx
->dma_copy(&sctx
->b
, &new_tex
->buffer
.b
.b
, i
, 0, 0, 0,
542 &rtex
->buffer
.b
.b
, i
, &box
);
546 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
547 si_texture_discard_cmask(sctx
->screen
, rtex
);
548 si_texture_discard_dcc(sctx
->screen
, rtex
);
551 /* Replace the structure fields of rtex. */
552 rtex
->buffer
.b
.b
.bind
= templ
.bind
;
553 pb_reference(&rtex
->buffer
.buf
, new_tex
->buffer
.buf
);
554 rtex
->buffer
.gpu_address
= new_tex
->buffer
.gpu_address
;
555 rtex
->buffer
.vram_usage
= new_tex
->buffer
.vram_usage
;
556 rtex
->buffer
.gart_usage
= new_tex
->buffer
.gart_usage
;
557 rtex
->buffer
.bo_size
= new_tex
->buffer
.bo_size
;
558 rtex
->buffer
.bo_alignment
= new_tex
->buffer
.bo_alignment
;
559 rtex
->buffer
.domains
= new_tex
->buffer
.domains
;
560 rtex
->buffer
.flags
= new_tex
->buffer
.flags
;
561 rtex
->size
= new_tex
->size
;
562 rtex
->db_render_format
= new_tex
->db_render_format
;
563 rtex
->db_compatible
= new_tex
->db_compatible
;
564 rtex
->can_sample_z
= new_tex
->can_sample_z
;
565 rtex
->can_sample_s
= new_tex
->can_sample_s
;
566 rtex
->surface
= new_tex
->surface
;
567 rtex
->fmask_offset
= new_tex
->fmask_offset
;
568 rtex
->cmask
= new_tex
->cmask
;
569 rtex
->cb_color_info
= new_tex
->cb_color_info
;
570 rtex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
571 rtex
->htile_offset
= new_tex
->htile_offset
;
572 rtex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
573 rtex
->depth_cleared
= new_tex
->depth_cleared
;
574 rtex
->stencil_cleared
= new_tex
->stencil_cleared
;
575 rtex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
576 rtex
->framebuffers_bound
= new_tex
->framebuffers_bound
;
578 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
579 assert(!rtex
->htile_offset
);
580 assert(!rtex
->cmask
.size
);
581 assert(!rtex
->surface
.fmask_size
);
582 assert(!rtex
->dcc_offset
);
583 assert(!rtex
->is_depth
);
586 r600_texture_reference(&new_tex
, NULL
);
588 p_atomic_inc(&sctx
->screen
->dirty_tex_counter
);
591 static uint32_t si_get_bo_metadata_word1(struct si_screen
*sscreen
)
593 return (ATI_VENDOR_ID
<< 16) | sscreen
->info
.pci_id
;
596 static void si_query_opaque_metadata(struct si_screen
*sscreen
,
597 struct r600_texture
*rtex
,
598 struct radeon_bo_metadata
*md
)
600 struct pipe_resource
*res
= &rtex
->buffer
.b
.b
;
601 static const unsigned char swizzle
[] = {
608 bool is_array
= util_texture_is_array(res
->target
);
610 /* DRM 2.x.x doesn't support this. */
611 if (sscreen
->info
.drm_major
!= 3)
614 assert(rtex
->dcc_separate_buffer
== NULL
);
615 assert(rtex
->surface
.fmask_size
== 0);
617 /* Metadata image format format version 1:
618 * [0] = 1 (metadata format identifier)
619 * [1] = (VENDOR_ID << 16) | PCI_ID
620 * [2:9] = image descriptor for the whole resource
621 * [2] is always 0, because the base address is cleared
622 * [9] is the DCC offset bits [39:8] from the beginning of
624 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
627 md
->metadata
[0] = 1; /* metadata image format version 1 */
629 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
630 md
->metadata
[1] = si_get_bo_metadata_word1(sscreen
);
632 si_make_texture_descriptor(sscreen
, rtex
, true,
633 res
->target
, res
->format
,
634 swizzle
, 0, res
->last_level
, 0,
635 is_array
? res
->array_size
- 1 : 0,
636 res
->width0
, res
->height0
, res
->depth0
,
639 si_set_mutable_tex_desc_fields(sscreen
, rtex
, &rtex
->surface
.u
.legacy
.level
[0],
640 0, 0, rtex
->surface
.blk_w
, false, desc
);
642 /* Clear the base address and set the relative DCC offset. */
644 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
645 desc
[7] = rtex
->dcc_offset
>> 8;
647 /* Dwords [2:9] contain the image descriptor. */
648 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
649 md
->size_metadata
= 10 * 4;
651 /* Dwords [10:..] contain the mipmap level offsets. */
652 if (sscreen
->info
.chip_class
<= VI
) {
653 for (i
= 0; i
<= res
->last_level
; i
++)
654 md
->metadata
[10+i
] = rtex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
656 md
->size_metadata
+= (1 + res
->last_level
) * 4;
660 static void si_apply_opaque_metadata(struct si_screen
*sscreen
,
661 struct r600_texture
*rtex
,
662 struct radeon_bo_metadata
*md
)
664 uint32_t *desc
= &md
->metadata
[2];
666 if (sscreen
->info
.chip_class
< VI
)
669 /* Return if DCC is enabled. The texture should be set up with it
672 if (md
->size_metadata
>= 10 * 4 && /* at least 2(header) + 8(desc) dwords */
673 md
->metadata
[0] != 0 &&
674 md
->metadata
[1] == si_get_bo_metadata_word1(sscreen
) &&
675 G_008F28_COMPRESSION_EN(desc
[6])) {
676 rtex
->dcc_offset
= (uint64_t)desc
[7] << 8;
680 /* Disable DCC. These are always set by texture_from_handle and must
683 rtex
->dcc_offset
= 0;
686 static boolean
si_texture_get_handle(struct pipe_screen
* screen
,
687 struct pipe_context
*ctx
,
688 struct pipe_resource
*resource
,
689 struct winsys_handle
*whandle
,
692 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
693 struct si_context
*sctx
;
694 struct r600_resource
*res
= r600_resource(resource
);
695 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
696 struct radeon_bo_metadata metadata
;
697 bool update_metadata
= false;
698 unsigned stride
, offset
, slice_size
;
701 ctx
= threaded_context_unwrap_sync(ctx
);
702 sctx
= (struct si_context
*)(ctx
? ctx
: sscreen
->aux_context
);
704 if (resource
->target
!= PIPE_BUFFER
) {
705 /* This is not supported now, but it might be required for OpenCL
706 * interop in the future.
708 if (resource
->nr_samples
> 1 || rtex
->is_depth
)
711 /* Move a suballocated texture into a non-suballocated allocation. */
712 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
713 rtex
->surface
.tile_swizzle
||
714 (rtex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
715 sscreen
->info
.has_local_buffers
&&
716 whandle
->type
!= DRM_API_HANDLE_TYPE_KMS
)) {
717 assert(!res
->b
.is_shared
);
718 si_reallocate_texture_inplace(sctx
, rtex
,
719 PIPE_BIND_SHARED
, false);
721 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
722 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
723 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
724 assert(rtex
->surface
.tile_swizzle
== 0);
727 /* Since shader image stores don't support DCC on VI,
728 * disable it for external clients that want write
731 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
732 if (si_texture_disable_dcc(sctx
, rtex
)) {
733 update_metadata
= true;
734 /* si_texture_disable_dcc flushes the context */
739 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
740 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
741 /* Eliminate fast clear (both CMASK and DCC) */
742 si_eliminate_fast_color_clear(sctx
, rtex
);
743 /* eliminate_fast_color_clear flushes the context */
746 /* Disable CMASK if flush_resource isn't going
749 if (rtex
->cmask
.size
)
750 si_texture_discard_cmask(sscreen
, rtex
);
754 if (!res
->b
.is_shared
|| update_metadata
) {
755 si_texture_init_metadata(sscreen
, rtex
, &metadata
);
756 si_query_opaque_metadata(sscreen
, rtex
, &metadata
);
758 sscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
761 if (sscreen
->info
.chip_class
>= GFX9
) {
762 offset
= rtex
->surface
.u
.gfx9
.surf_offset
;
763 stride
= rtex
->surface
.u
.gfx9
.surf_pitch
*
765 slice_size
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
767 offset
= rtex
->surface
.u
.legacy
.level
[0].offset
;
768 stride
= rtex
->surface
.u
.legacy
.level
[0].nblk_x
*
770 slice_size
= (uint64_t)rtex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
773 /* Buffer exports are for the OpenCL interop. */
774 /* Move a suballocated buffer into a non-suballocated allocation. */
775 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
776 /* A DMABUF export always fails if the BO is local. */
777 (rtex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
778 sscreen
->info
.has_local_buffers
)) {
779 assert(!res
->b
.is_shared
);
781 /* Allocate a new buffer with PIPE_BIND_SHARED. */
782 struct pipe_resource templ
= res
->b
.b
;
783 templ
.bind
|= PIPE_BIND_SHARED
;
785 struct pipe_resource
*newb
=
786 screen
->resource_create(screen
, &templ
);
790 /* Copy the old buffer contents to the new one. */
792 u_box_1d(0, newb
->width0
, &box
);
793 sctx
->b
.resource_copy_region(&sctx
->b
, newb
, 0, 0, 0, 0,
796 /* Move the new buffer storage to the old pipe_resource. */
797 si_replace_buffer_storage(&sctx
->b
, &res
->b
.b
, newb
);
798 pipe_resource_reference(&newb
, NULL
);
800 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
801 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
811 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
813 if (res
->b
.is_shared
) {
814 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
817 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
818 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
819 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
821 res
->b
.is_shared
= true;
822 res
->external_usage
= usage
;
825 return sscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
826 slice_size
, whandle
);
829 static void si_texture_destroy(struct pipe_screen
*screen
,
830 struct pipe_resource
*ptex
)
832 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
833 struct r600_resource
*resource
= &rtex
->buffer
;
835 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
837 if (rtex
->cmask_buffer
!= &rtex
->buffer
) {
838 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
840 pb_reference(&resource
->buf
, NULL
);
841 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
842 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
846 static const struct u_resource_vtbl si_texture_vtbl
;
848 void si_texture_get_cmask_info(struct si_screen
*sscreen
,
849 struct r600_texture
*rtex
,
850 struct r600_cmask_info
*out
)
852 unsigned pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
853 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
854 unsigned cl_width
, cl_height
;
856 if (sscreen
->info
.chip_class
>= GFX9
) {
857 out
->alignment
= rtex
->surface
.u
.gfx9
.cmask_alignment
;
858 out
->size
= rtex
->surface
.u
.gfx9
.cmask_size
;
875 case 16: /* Hawaii */
884 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
886 unsigned width
= align(rtex
->buffer
.b
.b
.width0
, cl_width
*8);
887 unsigned height
= align(rtex
->buffer
.b
.b
.height0
, cl_height
*8);
888 unsigned slice_elements
= (width
* height
) / (8*8);
890 /* Each element of CMASK is a nibble. */
891 unsigned slice_bytes
= slice_elements
/ 2;
893 out
->slice_tile_max
= (width
* height
) / (128*128);
894 if (out
->slice_tile_max
)
895 out
->slice_tile_max
-= 1;
897 out
->alignment
= MAX2(256, base_align
);
898 out
->size
= util_num_layers(&rtex
->buffer
.b
.b
, 0) *
899 align(slice_bytes
, base_align
);
902 static void si_texture_allocate_cmask(struct si_screen
*sscreen
,
903 struct r600_texture
*rtex
)
905 si_texture_get_cmask_info(sscreen
, rtex
, &rtex
->cmask
);
907 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
908 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
910 rtex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
913 static void si_texture_get_htile_size(struct si_screen
*sscreen
,
914 struct r600_texture
*rtex
)
916 unsigned cl_width
, cl_height
, width
, height
;
917 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
918 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
920 assert(sscreen
->info
.chip_class
<= VI
);
922 rtex
->surface
.htile_size
= 0;
924 /* HTILE is broken with 1D tiling on old kernels and CIK. */
925 if (sscreen
->info
.chip_class
>= CIK
&&
926 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
927 sscreen
->info
.drm_major
== 2 && sscreen
->info
.drm_minor
< 38)
930 /* Overalign HTILE on P2 configs to work around GPU hangs in
931 * piglit/depthstencil-render-miplevels 585.
933 * This has been confirmed to help Kabini & Stoney, where the hangs
934 * are always reproducible. I think I have seen the test hang
935 * on Carrizo too, though it was very rare there.
937 if (sscreen
->info
.chip_class
>= CIK
&& num_pipes
< 4)
966 width
= align(rtex
->buffer
.b
.b
.width0
, cl_width
* 8);
967 height
= align(rtex
->buffer
.b
.b
.height0
, cl_height
* 8);
969 slice_elements
= (width
* height
) / (8 * 8);
970 slice_bytes
= slice_elements
* 4;
972 pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
973 base_align
= num_pipes
* pipe_interleave_bytes
;
975 rtex
->surface
.htile_alignment
= base_align
;
976 rtex
->surface
.htile_size
=
977 util_num_layers(&rtex
->buffer
.b
.b
, 0) *
978 align(slice_bytes
, base_align
);
981 static void si_texture_allocate_htile(struct si_screen
*sscreen
,
982 struct r600_texture
*rtex
)
984 if (sscreen
->info
.chip_class
<= VI
&& !rtex
->tc_compatible_htile
)
985 si_texture_get_htile_size(sscreen
, rtex
);
987 if (!rtex
->surface
.htile_size
)
990 rtex
->htile_offset
= align(rtex
->size
, rtex
->surface
.htile_alignment
);
991 rtex
->size
= rtex
->htile_offset
+ rtex
->surface
.htile_size
;
994 void si_print_texture_info(struct si_screen
*sscreen
,
995 struct r600_texture
*rtex
, struct u_log_context
*log
)
999 /* Common parameters. */
1000 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
1001 "blk_h=%u, array_size=%u, last_level=%u, "
1002 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
1003 rtex
->buffer
.b
.b
.width0
, rtex
->buffer
.b
.b
.height0
,
1004 rtex
->buffer
.b
.b
.depth0
, rtex
->surface
.blk_w
,
1005 rtex
->surface
.blk_h
,
1006 rtex
->buffer
.b
.b
.array_size
, rtex
->buffer
.b
.b
.last_level
,
1007 rtex
->surface
.bpe
, rtex
->buffer
.b
.b
.nr_samples
,
1008 rtex
->surface
.flags
, util_format_short_name(rtex
->buffer
.b
.b
.format
));
1010 if (sscreen
->info
.chip_class
>= GFX9
) {
1011 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
1012 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
1013 rtex
->surface
.surf_size
,
1014 rtex
->surface
.u
.gfx9
.surf_slice_size
,
1015 rtex
->surface
.surf_alignment
,
1016 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
1017 rtex
->surface
.u
.gfx9
.surf
.epitch
,
1018 rtex
->surface
.u
.gfx9
.surf_pitch
);
1020 if (rtex
->surface
.fmask_size
) {
1021 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
1022 "alignment=%u, swmode=%u, epitch=%u\n",
1024 rtex
->surface
.fmask_size
,
1025 rtex
->surface
.fmask_alignment
,
1026 rtex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1027 rtex
->surface
.u
.gfx9
.fmask
.epitch
);
1030 if (rtex
->cmask
.size
) {
1031 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", "
1032 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1034 rtex
->surface
.u
.gfx9
.cmask_size
,
1035 rtex
->surface
.u
.gfx9
.cmask_alignment
,
1036 rtex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1037 rtex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1040 if (rtex
->htile_offset
) {
1041 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, alignment=%u, "
1042 "rb_aligned=%u, pipe_aligned=%u\n",
1044 rtex
->surface
.htile_size
,
1045 rtex
->surface
.htile_alignment
,
1046 rtex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1047 rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1050 if (rtex
->dcc_offset
) {
1051 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, "
1052 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1053 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1054 rtex
->surface
.dcc_alignment
,
1055 rtex
->surface
.u
.gfx9
.dcc_pitch_max
,
1056 rtex
->surface
.num_dcc_levels
);
1059 if (rtex
->surface
.u
.gfx9
.stencil_offset
) {
1060 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1061 rtex
->surface
.u
.gfx9
.stencil_offset
,
1062 rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1063 rtex
->surface
.u
.gfx9
.stencil
.epitch
);
1068 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1069 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1070 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.u
.legacy
.bankw
,
1071 rtex
->surface
.u
.legacy
.bankh
, rtex
->surface
.u
.legacy
.num_banks
, rtex
->surface
.u
.legacy
.mtilea
,
1072 rtex
->surface
.u
.legacy
.tile_split
, rtex
->surface
.u
.legacy
.pipe_config
,
1073 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1075 if (rtex
->surface
.fmask_size
)
1076 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1077 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1078 rtex
->fmask_offset
, rtex
->surface
.fmask_size
, rtex
->surface
.fmask_alignment
,
1079 rtex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
,
1080 rtex
->surface
.u
.legacy
.fmask
.bankh
,
1081 rtex
->surface
.u
.legacy
.fmask
.slice_tile_max
,
1082 rtex
->surface
.u
.legacy
.fmask
.tiling_index
);
1084 if (rtex
->cmask
.size
)
1085 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1086 "slice_tile_max=%u\n",
1087 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
1088 rtex
->cmask
.slice_tile_max
);
1090 if (rtex
->htile_offset
)
1091 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, "
1092 "alignment=%u, TC_compatible = %u\n",
1093 rtex
->htile_offset
, rtex
->surface
.htile_size
,
1094 rtex
->surface
.htile_alignment
,
1095 rtex
->tc_compatible_htile
);
1097 if (rtex
->dcc_offset
) {
1098 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, alignment=%u\n",
1099 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1100 rtex
->surface
.dcc_alignment
);
1101 for (i
= 0; i
<= rtex
->buffer
.b
.b
.last_level
; i
++)
1102 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%u, "
1103 "fast_clear_size=%u\n",
1104 i
, i
< rtex
->surface
.num_dcc_levels
,
1105 rtex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1106 rtex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1109 for (i
= 0; i
<= rtex
->buffer
.b
.b
.last_level
; i
++)
1110 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1111 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1112 "mode=%u, tiling_index = %u\n",
1113 i
, rtex
->surface
.u
.legacy
.level
[i
].offset
,
1114 (uint64_t)rtex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
1115 u_minify(rtex
->buffer
.b
.b
.width0
, i
),
1116 u_minify(rtex
->buffer
.b
.b
.height0
, i
),
1117 u_minify(rtex
->buffer
.b
.b
.depth0
, i
),
1118 rtex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1119 rtex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1120 rtex
->surface
.u
.legacy
.level
[i
].mode
,
1121 rtex
->surface
.u
.legacy
.tiling_index
[i
]);
1123 if (rtex
->surface
.has_stencil
) {
1124 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1125 rtex
->surface
.u
.legacy
.stencil_tile_split
);
1126 for (i
= 0; i
<= rtex
->buffer
.b
.b
.last_level
; i
++) {
1127 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1128 "slice_size=%"PRIu64
", npix_x=%u, "
1129 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1130 "mode=%u, tiling_index = %u\n",
1131 i
, rtex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1132 (uint64_t)rtex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
1133 u_minify(rtex
->buffer
.b
.b
.width0
, i
),
1134 u_minify(rtex
->buffer
.b
.b
.height0
, i
),
1135 u_minify(rtex
->buffer
.b
.b
.depth0
, i
),
1136 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1137 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1138 rtex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1139 rtex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1144 /* Common processing for r600_texture_create and r600_texture_from_handle */
1145 static struct r600_texture
*
1146 si_texture_create_object(struct pipe_screen
*screen
,
1147 const struct pipe_resource
*base
,
1148 struct pb_buffer
*buf
,
1149 struct radeon_surf
*surface
)
1151 struct r600_texture
*rtex
;
1152 struct r600_resource
*resource
;
1153 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1155 rtex
= CALLOC_STRUCT(r600_texture
);
1159 resource
= &rtex
->buffer
;
1160 resource
->b
.b
= *base
;
1161 resource
->b
.b
.next
= NULL
;
1162 resource
->b
.vtbl
= &si_texture_vtbl
;
1163 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1164 resource
->b
.b
.screen
= screen
;
1166 /* don't include stencil-only formats which we don't support for rendering */
1167 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->buffer
.b
.b
.format
));
1169 rtex
->surface
= *surface
;
1170 rtex
->size
= rtex
->surface
.surf_size
;
1172 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0 &&
1173 (rtex
->surface
.flags
&
1174 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1176 /* TC-compatible HTILE:
1177 * - VI only supports Z32_FLOAT.
1178 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1179 if (rtex
->tc_compatible_htile
) {
1180 if (sscreen
->info
.chip_class
>= GFX9
&&
1181 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1182 rtex
->db_render_format
= base
->format
;
1184 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1185 rtex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1186 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1189 rtex
->db_render_format
= base
->format
;
1192 /* Applies to GCN. */
1193 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1195 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1196 * between frames, so the only thing that can enable separate DCC
1197 * with DRI2 is multiple slow clears within a frame.
1199 rtex
->ps_draw_ratio
= 0;
1201 if (rtex
->is_depth
) {
1202 if (sscreen
->info
.chip_class
>= GFX9
) {
1203 rtex
->can_sample_z
= true;
1204 rtex
->can_sample_s
= true;
1206 rtex
->can_sample_z
= !rtex
->surface
.u
.legacy
.depth_adjusted
;
1207 rtex
->can_sample_s
= !rtex
->surface
.u
.legacy
.stencil_adjusted
;
1210 if (!(base
->flags
& (SI_RESOURCE_FLAG_TRANSFER
|
1211 SI_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1212 rtex
->db_compatible
= true;
1214 if (!(sscreen
->debug_flags
& DBG(NO_HYPERZ
)))
1215 si_texture_allocate_htile(sscreen
, rtex
);
1218 if (base
->nr_samples
> 1 &&
1220 !(sscreen
->debug_flags
& DBG(NO_FMASK
))) {
1221 /* Allocate FMASK. */
1222 rtex
->fmask_offset
= align64(rtex
->size
,
1223 rtex
->surface
.fmask_alignment
);
1224 rtex
->size
= rtex
->fmask_offset
+ rtex
->surface
.fmask_size
;
1226 si_texture_allocate_cmask(sscreen
, rtex
);
1227 rtex
->cmask_buffer
= &rtex
->buffer
;
1229 if (!rtex
->surface
.fmask_size
|| !rtex
->cmask
.size
) {
1235 /* Shared textures must always set up DCC here.
1236 * If it's not present, it will be disabled by
1237 * apply_opaque_metadata later.
1239 if (rtex
->surface
.dcc_size
&&
1240 (buf
|| !(sscreen
->debug_flags
& DBG(NO_DCC
))) &&
1241 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1242 /* Reserve space for the DCC buffer. */
1243 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1244 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1248 /* Now create the backing buffer. */
1250 si_init_resource_fields(sscreen
, resource
, rtex
->size
,
1251 rtex
->surface
.surf_alignment
);
1253 if (!si_alloc_resource(sscreen
, resource
)) {
1258 resource
->buf
= buf
;
1259 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1260 resource
->bo_size
= buf
->size
;
1261 resource
->bo_alignment
= buf
->alignment
;
1262 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1263 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1264 resource
->vram_usage
= buf
->size
;
1265 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1266 resource
->gart_usage
= buf
->size
;
1269 if (rtex
->cmask
.size
) {
1270 /* Initialize the cmask to 0xCC (= compressed state). */
1271 si_screen_clear_buffer(sscreen
, &rtex
->cmask_buffer
->b
.b
,
1272 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1275 if (rtex
->htile_offset
) {
1276 uint32_t clear_value
= 0;
1278 if (sscreen
->info
.chip_class
>= GFX9
|| rtex
->tc_compatible_htile
)
1279 clear_value
= 0x0000030F;
1281 si_screen_clear_buffer(sscreen
, &rtex
->buffer
.b
.b
,
1283 rtex
->surface
.htile_size
,
1287 /* Initialize DCC only if the texture is not being imported. */
1288 if (!buf
&& rtex
->dcc_offset
) {
1289 si_screen_clear_buffer(sscreen
, &rtex
->buffer
.b
.b
,
1291 rtex
->surface
.dcc_size
,
1295 /* Initialize the CMASK base register value. */
1296 rtex
->cmask
.base_address_reg
=
1297 (rtex
->buffer
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1299 if (sscreen
->debug_flags
& DBG(VM
)) {
1300 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1301 rtex
->buffer
.gpu_address
,
1302 rtex
->buffer
.gpu_address
+ rtex
->buffer
.buf
->size
,
1303 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+1,
1304 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1307 if (sscreen
->debug_flags
& DBG(TEX
)) {
1309 struct u_log_context log
;
1310 u_log_context_init(&log
);
1311 si_print_texture_info(sscreen
, rtex
, &log
);
1312 u_log_new_page_print(&log
, stdout
);
1314 u_log_context_destroy(&log
);
1320 static enum radeon_surf_mode
1321 si_choose_tiling(struct si_screen
*sscreen
,
1322 const struct pipe_resource
*templ
, bool tc_compatible_htile
)
1324 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1325 bool force_tiling
= templ
->flags
& SI_RESOURCE_FLAG_FORCE_TILING
;
1326 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1327 !(templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
);
1329 /* MSAA resources must be 2D tiled. */
1330 if (templ
->nr_samples
> 1)
1331 return RADEON_SURF_MODE_2D
;
1333 /* Transfer resources should be linear. */
1334 if (templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
)
1335 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1337 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
1338 * which requires 2D tiling.
1340 if (sscreen
->info
.chip_class
== VI
&& tc_compatible_htile
)
1341 return RADEON_SURF_MODE_2D
;
1343 /* Handle common candidates for the linear mode.
1344 * Compressed textures and DB surfaces must always be tiled.
1346 if (!force_tiling
&&
1347 !is_depth_stencil
&&
1348 !util_format_is_compressed(templ
->format
)) {
1349 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1350 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1352 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. */
1353 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1354 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1356 /* Cursors are linear on SI.
1357 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1358 if (templ
->bind
& PIPE_BIND_CURSOR
)
1359 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1361 if (templ
->bind
& PIPE_BIND_LINEAR
)
1362 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1364 /* Textures with a very small height are recommended to be linear. */
1365 if (templ
->target
== PIPE_TEXTURE_1D
||
1366 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1367 /* Only very thin and long 2D textures should benefit from
1368 * linear_aligned. */
1369 (templ
->width0
> 8 && templ
->height0
<= 2))
1370 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1372 /* Textures likely to be mapped often. */
1373 if (templ
->usage
== PIPE_USAGE_STAGING
||
1374 templ
->usage
== PIPE_USAGE_STREAM
)
1375 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1378 /* Make small textures 1D tiled. */
1379 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1380 (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1381 return RADEON_SURF_MODE_1D
;
1383 /* The allocator will switch to 1D if needed. */
1384 return RADEON_SURF_MODE_2D
;
1387 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1388 const struct pipe_resource
*templ
)
1390 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1391 struct radeon_surf surface
= {0};
1392 bool is_flushed_depth
= templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1393 bool tc_compatible_htile
=
1394 sscreen
->info
.chip_class
>= VI
&&
1395 /* There are issues with TC-compatible HTILE on Tonga (and
1396 * Iceland is the same design), and documented bug workarounds
1397 * don't help. For example, this fails:
1398 * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow -auto
1400 sscreen
->info
.family
!= CHIP_TONGA
&&
1401 sscreen
->info
.family
!= CHIP_ICELAND
&&
1402 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1403 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) &&
1404 !is_flushed_depth
&&
1405 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1406 util_format_is_depth_or_stencil(templ
->format
);
1410 r
= si_init_surface(sscreen
, &surface
, templ
,
1411 si_choose_tiling(sscreen
, templ
, tc_compatible_htile
),
1412 0, 0, false, false, is_flushed_depth
,
1413 tc_compatible_htile
);
1418 return (struct pipe_resource
*)
1419 si_texture_create_object(screen
, templ
, NULL
, &surface
);
1422 static struct pipe_resource
*si_texture_from_handle(struct pipe_screen
*screen
,
1423 const struct pipe_resource
*templ
,
1424 struct winsys_handle
*whandle
,
1427 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1428 struct pb_buffer
*buf
= NULL
;
1429 unsigned stride
= 0, offset
= 0;
1430 enum radeon_surf_mode array_mode
;
1431 struct radeon_surf surface
= {};
1433 struct radeon_bo_metadata metadata
= {};
1434 struct r600_texture
*rtex
;
1437 /* Support only 2D textures without mipmaps */
1438 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1439 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1442 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
, &stride
, &offset
);
1446 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1447 si_surface_import_metadata(sscreen
, &surface
, &metadata
,
1448 &array_mode
, &is_scanout
);
1450 r
= si_init_surface(sscreen
, &surface
, templ
, array_mode
, stride
,
1451 offset
, true, is_scanout
, false, false);
1456 rtex
= si_texture_create_object(screen
, templ
, buf
, &surface
);
1460 rtex
->buffer
.b
.is_shared
= true;
1461 rtex
->buffer
.external_usage
= usage
;
1463 si_apply_opaque_metadata(sscreen
, rtex
, &metadata
);
1465 assert(rtex
->surface
.tile_swizzle
== 0);
1466 return &rtex
->buffer
.b
.b
;
1469 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1470 struct pipe_resource
*texture
,
1471 struct r600_texture
**staging
)
1473 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1474 struct pipe_resource resource
;
1475 struct r600_texture
**flushed_depth_texture
= staging
?
1476 staging
: &rtex
->flushed_depth_texture
;
1477 enum pipe_format pipe_format
= texture
->format
;
1480 if (rtex
->flushed_depth_texture
)
1481 return true; /* it's ready */
1483 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1484 switch (pipe_format
) {
1485 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1486 /* Save memory by not allocating the S plane. */
1487 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1489 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1490 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1491 /* Save memory bandwidth by not copying the
1492 * stencil part during flush.
1494 * This potentially increases memory bandwidth
1495 * if an application uses both Z and S texturing
1496 * simultaneously (a flushed Z24S8 texture
1497 * would be stored compactly), but how often
1498 * does that really happen?
1500 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1504 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1505 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1507 /* DB->CB copies to an 8bpp surface don't work. */
1508 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1512 memset(&resource
, 0, sizeof(resource
));
1513 resource
.target
= texture
->target
;
1514 resource
.format
= pipe_format
;
1515 resource
.width0
= texture
->width0
;
1516 resource
.height0
= texture
->height0
;
1517 resource
.depth0
= texture
->depth0
;
1518 resource
.array_size
= texture
->array_size
;
1519 resource
.last_level
= texture
->last_level
;
1520 resource
.nr_samples
= texture
->nr_samples
;
1521 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1522 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1523 resource
.flags
= texture
->flags
| SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1526 resource
.flags
|= SI_RESOURCE_FLAG_TRANSFER
;
1528 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1529 if (*flushed_depth_texture
== NULL
) {
1530 PRINT_ERR("failed to create temporary texture to hold flushed depth\n");
1537 * Initialize the pipe_resource descriptor to be of the same size as the box,
1538 * which is supposed to hold a subregion of the texture "orig" at the given
1541 static void si_init_temp_resource_from_box(struct pipe_resource
*res
,
1542 struct pipe_resource
*orig
,
1543 const struct pipe_box
*box
,
1544 unsigned level
, unsigned flags
)
1546 memset(res
, 0, sizeof(*res
));
1547 res
->format
= orig
->format
;
1548 res
->width0
= box
->width
;
1549 res
->height0
= box
->height
;
1551 res
->array_size
= 1;
1552 res
->usage
= flags
& SI_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1555 /* We must set the correct texture target and dimensions for a 3D box. */
1556 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1557 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1558 res
->array_size
= box
->depth
;
1560 res
->target
= PIPE_TEXTURE_2D
;
1564 static bool si_can_invalidate_texture(struct si_screen
*sscreen
,
1565 struct r600_texture
*rtex
,
1566 unsigned transfer_usage
,
1567 const struct pipe_box
*box
)
1569 return !rtex
->buffer
.b
.is_shared
&&
1570 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1571 rtex
->buffer
.b
.b
.last_level
== 0 &&
1572 util_texrange_covers_whole_level(&rtex
->buffer
.b
.b
, 0,
1573 box
->x
, box
->y
, box
->z
,
1574 box
->width
, box
->height
,
1578 static void si_texture_invalidate_storage(struct si_context
*sctx
,
1579 struct r600_texture
*rtex
)
1581 struct si_screen
*sscreen
= sctx
->screen
;
1583 /* There is no point in discarding depth and tiled buffers. */
1584 assert(!rtex
->is_depth
);
1585 assert(rtex
->surface
.is_linear
);
1587 /* Reallocate the buffer in the same pipe_resource. */
1588 si_alloc_resource(sscreen
, &rtex
->buffer
);
1590 /* Initialize the CMASK base address (needed even without CMASK). */
1591 rtex
->cmask
.base_address_reg
=
1592 (rtex
->buffer
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1594 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1596 sctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1599 static void *si_texture_transfer_map(struct pipe_context
*ctx
,
1600 struct pipe_resource
*texture
,
1603 const struct pipe_box
*box
,
1604 struct pipe_transfer
**ptransfer
)
1606 struct si_context
*sctx
= (struct si_context
*)ctx
;
1607 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1608 struct r600_transfer
*trans
;
1609 struct r600_resource
*buf
;
1610 unsigned offset
= 0;
1612 bool use_staging_texture
= false;
1614 assert(!(texture
->flags
& SI_RESOURCE_FLAG_TRANSFER
));
1615 assert(box
->width
&& box
->height
&& box
->depth
);
1617 /* Depth textures use staging unconditionally. */
1618 if (!rtex
->is_depth
) {
1619 /* Degrade the tile mode if we get too many transfers on APUs.
1620 * On dGPUs, the staging texture is always faster.
1621 * Only count uploads that are at least 4x4 pixels large.
1623 if (!sctx
->screen
->info
.has_dedicated_vram
&&
1625 box
->width
>= 4 && box
->height
>= 4 &&
1626 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1627 bool can_invalidate
=
1628 si_can_invalidate_texture(sctx
->screen
, rtex
,
1631 si_reallocate_texture_inplace(sctx
, rtex
,
1636 /* Tiled textures need to be converted into a linear texture for CPU
1637 * access. The staging texture is always linear and is placed in GART.
1639 * Reading from VRAM or GTT WC is slow, always use the staging
1640 * texture in this case.
1642 * Use the staging texture for uploads if the underlying BO
1645 if (!rtex
->surface
.is_linear
)
1646 use_staging_texture
= true;
1647 else if (usage
& PIPE_TRANSFER_READ
)
1648 use_staging_texture
=
1649 rtex
->buffer
.domains
& RADEON_DOMAIN_VRAM
||
1650 rtex
->buffer
.flags
& RADEON_FLAG_GTT_WC
;
1651 /* Write & linear only: */
1652 else if (si_rings_is_buffer_referenced(sctx
, rtex
->buffer
.buf
,
1653 RADEON_USAGE_READWRITE
) ||
1654 !sctx
->ws
->buffer_wait(rtex
->buffer
.buf
, 0,
1655 RADEON_USAGE_READWRITE
)) {
1657 if (si_can_invalidate_texture(sctx
->screen
, rtex
,
1659 si_texture_invalidate_storage(sctx
, rtex
);
1661 use_staging_texture
= true;
1665 trans
= CALLOC_STRUCT(r600_transfer
);
1668 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1669 trans
->b
.b
.level
= level
;
1670 trans
->b
.b
.usage
= usage
;
1671 trans
->b
.b
.box
= *box
;
1673 if (rtex
->is_depth
) {
1674 struct r600_texture
*staging_depth
;
1676 if (rtex
->buffer
.b
.b
.nr_samples
> 1) {
1677 /* MSAA depth buffers need to be converted to single sample buffers.
1679 * Mapping MSAA depth buffers can occur if ReadPixels is called
1680 * with a multisample GLX visual.
1682 * First downsample the depth buffer to a temporary texture,
1683 * then decompress the temporary one to staging.
1685 * Only the region being mapped is transfered.
1687 struct pipe_resource resource
;
1689 si_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1691 if (!si_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1692 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1696 if (usage
& PIPE_TRANSFER_READ
) {
1697 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1699 PRINT_ERR("failed to create a temporary depth texture\n");
1703 si_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1704 si_blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1705 0, 0, 0, box
->depth
, 0, 0);
1706 pipe_resource_reference(&temp
, NULL
);
1709 /* Just get the strides. */
1710 si_texture_get_offset(sctx
->screen
, staging_depth
, level
, NULL
,
1712 &trans
->b
.b
.layer_stride
);
1714 /* XXX: only readback the rectangle which is being mapped? */
1715 /* XXX: when discard is true, no need to read back from depth texture */
1716 if (!si_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1717 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1721 si_blit_decompress_depth(ctx
, rtex
, staging_depth
,
1723 box
->z
, box
->z
+ box
->depth
- 1,
1726 offset
= si_texture_get_offset(sctx
->screen
, staging_depth
,
1729 &trans
->b
.b
.layer_stride
);
1732 trans
->staging
= &staging_depth
->buffer
;
1733 buf
= trans
->staging
;
1734 } else if (use_staging_texture
) {
1735 struct pipe_resource resource
;
1736 struct r600_texture
*staging
;
1738 si_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1739 SI_RESOURCE_FLAG_TRANSFER
);
1740 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1741 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1743 /* Create the temporary texture. */
1744 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1746 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1749 trans
->staging
= &staging
->buffer
;
1751 /* Just get the strides. */
1752 si_texture_get_offset(sctx
->screen
, staging
, 0, NULL
,
1754 &trans
->b
.b
.layer_stride
);
1756 if (usage
& PIPE_TRANSFER_READ
)
1757 si_copy_to_staging_texture(ctx
, trans
);
1759 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1761 buf
= trans
->staging
;
1763 /* the resource is mapped directly */
1764 offset
= si_texture_get_offset(sctx
->screen
, rtex
, level
, box
,
1766 &trans
->b
.b
.layer_stride
);
1767 buf
= &rtex
->buffer
;
1770 if (!(map
= si_buffer_map_sync_with_rings(sctx
, buf
, usage
)))
1773 *ptransfer
= &trans
->b
.b
;
1774 return map
+ offset
;
1777 r600_resource_reference(&trans
->staging
, NULL
);
1778 pipe_resource_reference(&trans
->b
.b
.resource
, NULL
);
1783 static void si_texture_transfer_unmap(struct pipe_context
*ctx
,
1784 struct pipe_transfer
* transfer
)
1786 struct si_context
*sctx
= (struct si_context
*)ctx
;
1787 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1788 struct pipe_resource
*texture
= transfer
->resource
;
1789 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1791 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1792 if (rtex
->is_depth
&& rtex
->buffer
.b
.b
.nr_samples
<= 1) {
1793 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1794 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1795 &rtransfer
->staging
->b
.b
, transfer
->level
,
1798 si_copy_from_staging_texture(ctx
, rtransfer
);
1802 if (rtransfer
->staging
) {
1803 sctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1804 r600_resource_reference(&rtransfer
->staging
, NULL
);
1807 /* Heuristic for {upload, draw, upload, draw, ..}:
1809 * Flush the gfx IB if we've allocated too much texture storage.
1811 * The idea is that we don't want to build IBs that use too much
1812 * memory and put pressure on the kernel memory manager and we also
1813 * want to make temporary and invalidated buffers go idle ASAP to
1814 * decrease the total memory usage or make them reusable. The memory
1815 * usage will be slightly higher than given here because of the buffer
1816 * cache in the winsys.
1818 * The result is that the kernel memory manager is never a bottleneck.
1820 if (sctx
->num_alloc_tex_transfer_bytes
> sctx
->screen
->info
.gart_size
/ 4) {
1821 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1822 sctx
->num_alloc_tex_transfer_bytes
= 0;
1825 pipe_resource_reference(&transfer
->resource
, NULL
);
1829 static const struct u_resource_vtbl si_texture_vtbl
=
1831 NULL
, /* get_handle */
1832 si_texture_destroy
, /* resource_destroy */
1833 si_texture_transfer_map
, /* transfer_map */
1834 u_default_transfer_flush_region
, /* transfer_flush_region */
1835 si_texture_transfer_unmap
, /* transfer_unmap */
1838 /* Return if it's allowed to reinterpret one format as another with DCC enabled.
1840 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1841 enum pipe_format format2
)
1843 const struct util_format_description
*desc1
, *desc2
;
1845 /* No format change - exit early. */
1846 if (format1
== format2
)
1849 format1
= si_simplify_cb_format(format1
);
1850 format2
= si_simplify_cb_format(format2
);
1852 /* Check again after format adjustments. */
1853 if (format1
== format2
)
1856 desc1
= util_format_description(format1
);
1857 desc2
= util_format_description(format2
);
1859 if (desc1
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
1860 desc2
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1863 /* Float and non-float are totally incompatible. */
1864 if ((desc1
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
) !=
1865 (desc2
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
))
1868 /* Channel sizes must match across DCC formats.
1869 * Comparing just the first 2 channels should be enough.
1871 if (desc1
->channel
[0].size
!= desc2
->channel
[0].size
||
1872 (desc1
->nr_channels
>= 2 &&
1873 desc1
->channel
[1].size
!= desc2
->channel
[1].size
))
1876 /* Everything below is not needed if the driver never uses the DCC
1877 * clear code with the value of 1.
1880 /* If the clear values are all 1 or all 0, this constraint can be
1882 if (vi_alpha_is_on_msb(format1
) != vi_alpha_is_on_msb(format2
))
1885 /* Channel types must match if the clear value of 1 is used.
1886 * The type categories are only float, signed, unsigned.
1887 * NORM and INT are always compatible.
1889 if (desc1
->channel
[0].type
!= desc2
->channel
[0].type
||
1890 (desc1
->nr_channels
>= 2 &&
1891 desc1
->channel
[1].type
!= desc2
->channel
[1].type
))
1897 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1899 enum pipe_format view_format
)
1901 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1903 return vi_dcc_enabled(rtex
, level
) &&
1904 !vi_dcc_formats_compatible(tex
->format
, view_format
);
1907 /* This can't be merged with the above function, because
1908 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
1909 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
1910 struct pipe_resource
*tex
,
1912 enum pipe_format view_format
)
1914 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1916 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
1917 if (!si_texture_disable_dcc(sctx
, (struct r600_texture
*)tex
))
1918 si_decompress_dcc(sctx
, rtex
);
1921 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1922 struct pipe_resource
*texture
,
1923 const struct pipe_surface
*templ
,
1924 unsigned width0
, unsigned height0
,
1925 unsigned width
, unsigned height
)
1927 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1932 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1933 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1935 pipe_reference_init(&surface
->base
.reference
, 1);
1936 pipe_resource_reference(&surface
->base
.texture
, texture
);
1937 surface
->base
.context
= pipe
;
1938 surface
->base
.format
= templ
->format
;
1939 surface
->base
.width
= width
;
1940 surface
->base
.height
= height
;
1941 surface
->base
.u
= templ
->u
;
1943 surface
->width0
= width0
;
1944 surface
->height0
= height0
;
1946 surface
->dcc_incompatible
=
1947 texture
->target
!= PIPE_BUFFER
&&
1948 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
1950 return &surface
->base
;
1953 static struct pipe_surface
*si_create_surface(struct pipe_context
*pipe
,
1954 struct pipe_resource
*tex
,
1955 const struct pipe_surface
*templ
)
1957 unsigned level
= templ
->u
.tex
.level
;
1958 unsigned width
= u_minify(tex
->width0
, level
);
1959 unsigned height
= u_minify(tex
->height0
, level
);
1960 unsigned width0
= tex
->width0
;
1961 unsigned height0
= tex
->height0
;
1963 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1964 const struct util_format_description
*tex_desc
1965 = util_format_description(tex
->format
);
1966 const struct util_format_description
*templ_desc
1967 = util_format_description(templ
->format
);
1969 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1971 /* Adjust size of surface if and only if the block width or
1972 * height is changed. */
1973 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1974 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1975 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1976 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1978 width
= nblks_x
* templ_desc
->block
.width
;
1979 height
= nblks_y
* templ_desc
->block
.height
;
1981 width0
= util_format_get_nblocksx(tex
->format
, width0
);
1982 height0
= util_format_get_nblocksy(tex
->format
, height0
);
1986 return si_create_surface_custom(pipe
, tex
, templ
,
1991 static void si_surface_destroy(struct pipe_context
*pipe
,
1992 struct pipe_surface
*surface
)
1994 pipe_resource_reference(&surface
->texture
, NULL
);
1998 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2000 const struct util_format_description
*desc
= util_format_description(format
);
2002 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2004 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2005 return V_028C70_SWAP_STD
;
2007 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2010 switch (desc
->nr_channels
) {
2012 if (HAS_SWIZZLE(0,X
))
2013 return V_028C70_SWAP_STD
; /* X___ */
2014 else if (HAS_SWIZZLE(3,X
))
2015 return V_028C70_SWAP_ALT_REV
; /* ___X */
2018 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2019 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2020 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2021 return V_028C70_SWAP_STD
; /* XY__ */
2022 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2023 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2024 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2026 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2027 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2028 return V_028C70_SWAP_ALT
; /* X__Y */
2029 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2030 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2033 if (HAS_SWIZZLE(0,X
))
2034 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2035 else if (HAS_SWIZZLE(0,Z
))
2036 return V_028C70_SWAP_STD_REV
; /* ZYX */
2039 /* check the middle channels, the 1st and 4th channel can be NONE */
2040 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2041 return V_028C70_SWAP_STD
; /* XYZW */
2042 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2043 return V_028C70_SWAP_STD_REV
; /* WZYX */
2044 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2045 return V_028C70_SWAP_ALT
; /* ZYXW */
2046 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2049 return V_028C70_SWAP_ALT_REV
;
2051 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2058 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2060 static void vi_dcc_clean_up_context_slot(struct si_context
*sctx
,
2065 if (sctx
->dcc_stats
[slot
].query_active
)
2066 vi_separate_dcc_stop_query(sctx
,
2067 sctx
->dcc_stats
[slot
].tex
);
2069 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
[slot
].ps_stats
); i
++)
2070 if (sctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2071 sctx
->b
.destroy_query(&sctx
->b
,
2072 sctx
->dcc_stats
[slot
].ps_stats
[i
]);
2073 sctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2076 r600_texture_reference(&sctx
->dcc_stats
[slot
].tex
, NULL
);
2080 * Return the per-context slot where DCC statistics queries for the texture live.
2082 static unsigned vi_get_context_dcc_stats_index(struct si_context
*sctx
,
2083 struct r600_texture
*tex
)
2085 int i
, empty_slot
= -1;
2087 /* Remove zombie textures (textures kept alive by this array only). */
2088 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2089 if (sctx
->dcc_stats
[i
].tex
&&
2090 sctx
->dcc_stats
[i
].tex
->buffer
.b
.b
.reference
.count
== 1)
2091 vi_dcc_clean_up_context_slot(sctx
, i
);
2093 /* Find the texture. */
2094 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
2095 /* Return if found. */
2096 if (sctx
->dcc_stats
[i
].tex
== tex
) {
2097 sctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2101 /* Record the first seen empty slot. */
2102 if (empty_slot
== -1 && !sctx
->dcc_stats
[i
].tex
)
2106 /* Not found. Remove the oldest member to make space in the array. */
2107 if (empty_slot
== -1) {
2108 int oldest_slot
= 0;
2110 /* Find the oldest slot. */
2111 for (i
= 1; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2112 if (sctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2113 sctx
->dcc_stats
[i
].last_use_timestamp
)
2116 /* Clean up the oldest slot. */
2117 vi_dcc_clean_up_context_slot(sctx
, oldest_slot
);
2118 empty_slot
= oldest_slot
;
2121 /* Add the texture to the new slot. */
2122 r600_texture_reference(&sctx
->dcc_stats
[empty_slot
].tex
, tex
);
2123 sctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2127 static struct pipe_query
*
2128 vi_create_resuming_pipestats_query(struct si_context
*sctx
)
2130 struct si_query_hw
*query
= (struct si_query_hw
*)
2131 sctx
->b
.create_query(&sctx
->b
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2133 query
->flags
|= SI_QUERY_HW_FLAG_BEGIN_RESUMES
;
2134 return (struct pipe_query
*)query
;
2138 * Called when binding a color buffer.
2140 void vi_separate_dcc_start_query(struct si_context
*sctx
,
2141 struct r600_texture
*tex
)
2143 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2145 assert(!sctx
->dcc_stats
[i
].query_active
);
2147 if (!sctx
->dcc_stats
[i
].ps_stats
[0])
2148 sctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(sctx
);
2150 /* begin or resume the query */
2151 sctx
->b
.begin_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2152 sctx
->dcc_stats
[i
].query_active
= true;
2156 * Called when unbinding a color buffer.
2158 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
2159 struct r600_texture
*tex
)
2161 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2163 assert(sctx
->dcc_stats
[i
].query_active
);
2164 assert(sctx
->dcc_stats
[i
].ps_stats
[0]);
2166 /* pause or end the query */
2167 sctx
->b
.end_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2168 sctx
->dcc_stats
[i
].query_active
= false;
2171 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2173 /* The minimum number of fullscreen draws per frame that is required
2175 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2178 /* Called by fast clear. */
2179 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
2180 struct r600_texture
*tex
)
2182 /* The intent is to use this with shared displayable back buffers,
2183 * but it's not strictly limited only to them.
2185 if (!tex
->buffer
.b
.is_shared
||
2186 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2187 tex
->buffer
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2188 tex
->buffer
.b
.b
.last_level
> 0 ||
2189 !tex
->surface
.dcc_size
)
2192 if (tex
->dcc_offset
)
2193 return; /* already enabled */
2195 /* Enable the DCC stat gathering. */
2196 if (!tex
->dcc_gather_statistics
) {
2197 tex
->dcc_gather_statistics
= true;
2198 vi_separate_dcc_start_query(sctx
, tex
);
2201 if (!vi_should_enable_separate_dcc(tex
))
2202 return; /* stats show that DCC decompression is too expensive */
2204 assert(tex
->surface
.num_dcc_levels
);
2205 assert(!tex
->dcc_separate_buffer
);
2207 si_texture_discard_cmask(sctx
->screen
, tex
);
2209 /* Get a DCC buffer. */
2210 if (tex
->last_dcc_separate_buffer
) {
2211 assert(tex
->dcc_gather_statistics
);
2212 assert(!tex
->dcc_separate_buffer
);
2213 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2214 tex
->last_dcc_separate_buffer
= NULL
;
2216 tex
->dcc_separate_buffer
=
2217 si_aligned_buffer_create(sctx
->b
.screen
,
2218 SI_RESOURCE_FLAG_UNMAPPABLE
,
2220 tex
->surface
.dcc_size
,
2221 tex
->surface
.dcc_alignment
);
2222 if (!tex
->dcc_separate_buffer
)
2226 /* dcc_offset is the absolute GPUVM address. */
2227 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2229 /* no need to flag anything since this is called by fast clear that
2230 * flags framebuffer state
2235 * Called by pipe_context::flush_resource, the place where DCC decompression
2238 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2239 struct r600_texture
*tex
)
2241 struct si_context
*sctx
= (struct si_context
*)ctx
;
2242 struct pipe_query
*tmp
;
2243 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2244 bool query_active
= sctx
->dcc_stats
[i
].query_active
;
2245 bool disable
= false;
2247 if (sctx
->dcc_stats
[i
].ps_stats
[2]) {
2248 union pipe_query_result result
;
2250 /* Read the results. */
2251 ctx
->get_query_result(ctx
, sctx
->dcc_stats
[i
].ps_stats
[2],
2253 si_query_hw_reset_buffers(sctx
,
2254 (struct si_query_hw
*)
2255 sctx
->dcc_stats
[i
].ps_stats
[2]);
2257 /* Compute the approximate number of fullscreen draws. */
2258 tex
->ps_draw_ratio
=
2259 result
.pipeline_statistics
.ps_invocations
/
2260 (tex
->buffer
.b
.b
.width0
* tex
->buffer
.b
.b
.height0
);
2261 sctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2263 disable
= tex
->dcc_separate_buffer
&&
2264 !vi_should_enable_separate_dcc(tex
);
2267 tex
->num_slow_clears
= 0;
2269 /* stop the statistics query for ps_stats[0] */
2271 vi_separate_dcc_stop_query(sctx
, tex
);
2273 /* Move the queries in the queue by one. */
2274 tmp
= sctx
->dcc_stats
[i
].ps_stats
[2];
2275 sctx
->dcc_stats
[i
].ps_stats
[2] = sctx
->dcc_stats
[i
].ps_stats
[1];
2276 sctx
->dcc_stats
[i
].ps_stats
[1] = sctx
->dcc_stats
[i
].ps_stats
[0];
2277 sctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2279 /* create and start a new query as ps_stats[0] */
2281 vi_separate_dcc_start_query(sctx
, tex
);
2284 assert(!tex
->last_dcc_separate_buffer
);
2285 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2286 tex
->dcc_separate_buffer
= NULL
;
2287 tex
->dcc_offset
= 0;
2288 /* no need to flag anything since this is called after
2289 * decompression that re-sets framebuffer state
2294 static struct pipe_memory_object
*
2295 si_memobj_from_handle(struct pipe_screen
*screen
,
2296 struct winsys_handle
*whandle
,
2299 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2300 struct r600_memory_object
*memobj
= CALLOC_STRUCT(r600_memory_object
);
2301 struct pb_buffer
*buf
= NULL
;
2302 uint32_t stride
, offset
;
2307 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
2314 memobj
->b
.dedicated
= dedicated
;
2316 memobj
->stride
= stride
;
2317 memobj
->offset
= offset
;
2319 return (struct pipe_memory_object
*)memobj
;
2324 si_memobj_destroy(struct pipe_screen
*screen
,
2325 struct pipe_memory_object
*_memobj
)
2327 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2329 pb_reference(&memobj
->buf
, NULL
);
2333 static struct pipe_resource
*
2334 si_texture_from_memobj(struct pipe_screen
*screen
,
2335 const struct pipe_resource
*templ
,
2336 struct pipe_memory_object
*_memobj
,
2340 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2341 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2342 struct r600_texture
*rtex
;
2343 struct radeon_surf surface
= {};
2344 struct radeon_bo_metadata metadata
= {};
2345 enum radeon_surf_mode array_mode
;
2347 struct pb_buffer
*buf
= NULL
;
2349 if (memobj
->b
.dedicated
) {
2350 sscreen
->ws
->buffer_get_metadata(memobj
->buf
, &metadata
);
2351 si_surface_import_metadata(sscreen
, &surface
, &metadata
,
2352 &array_mode
, &is_scanout
);
2355 * The bo metadata is unset for un-dedicated images. So we fall
2356 * back to linear. See answer to question 5 of the
2357 * VK_KHX_external_memory spec for some details.
2359 * It is possible that this case isn't going to work if the
2360 * surface pitch isn't correctly aligned by default.
2362 * In order to support it correctly we require multi-image
2363 * metadata to be syncrhonized between radv and radeonsi. The
2364 * semantics of associating multiple image metadata to a memory
2365 * object on the vulkan export side are not concretely defined
2368 * All the use cases we are aware of at the moment for memory
2369 * objects use dedicated allocations. So lets keep the initial
2370 * implementation simple.
2372 * A possible alternative is to attempt to reconstruct the
2373 * tiling information when the TexParameter TEXTURE_TILING_EXT
2376 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
2381 r
= si_init_surface(sscreen
, &surface
, templ
,
2382 array_mode
, memobj
->stride
,
2383 offset
, true, is_scanout
,
2388 rtex
= si_texture_create_object(screen
, templ
, memobj
->buf
, &surface
);
2392 /* r600_texture_create_object doesn't increment refcount of
2393 * memobj->buf, so increment it here.
2395 pb_reference(&buf
, memobj
->buf
);
2397 rtex
->buffer
.b
.is_shared
= true;
2398 rtex
->buffer
.external_usage
= PIPE_HANDLE_USAGE_READ_WRITE
;
2400 si_apply_opaque_metadata(sscreen
, rtex
, &metadata
);
2402 return &rtex
->buffer
.b
.b
;
2405 static bool si_check_resource_capability(struct pipe_screen
*screen
,
2406 struct pipe_resource
*resource
,
2409 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
2411 /* Buffers only support the linear flag. */
2412 if (resource
->target
== PIPE_BUFFER
)
2413 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2415 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2418 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2421 /* TODO: PIPE_BIND_CURSOR - do we care? */
2425 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2427 sscreen
->b
.resource_from_handle
= si_texture_from_handle
;
2428 sscreen
->b
.resource_get_handle
= si_texture_get_handle
;
2429 sscreen
->b
.resource_from_memobj
= si_texture_from_memobj
;
2430 sscreen
->b
.memobj_create_from_handle
= si_memobj_from_handle
;
2431 sscreen
->b
.memobj_destroy
= si_memobj_destroy
;
2432 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2435 void si_init_context_texture_functions(struct si_context
*sctx
)
2437 sctx
->b
.create_surface
= si_create_surface
;
2438 sctx
->b
.surface_destroy
= si_surface_destroy
;