2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeonsi/si_pipe.h"
27 #include "radeonsi/si_query.h"
28 #include "util/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/u_resource.h"
33 #include "util/u_surface.h"
34 #include "util/u_transfer.h"
35 #include "util/os_time.h"
38 #include "state_tracker/drm_driver.h"
39 #include "amd/common/sid.h"
41 static enum radeon_surf_mode
42 si_choose_tiling(struct si_screen
*sscreen
,
43 const struct pipe_resource
*templ
, bool tc_compatible_htile
);
46 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
47 struct si_texture
*dst
,
48 unsigned dst_level
, unsigned dstx
,
49 unsigned dsty
, unsigned dstz
,
50 struct si_texture
*src
,
52 const struct pipe_box
*src_box
)
57 if (dst
->surface
.bpe
!= src
->surface
.bpe
)
60 /* MSAA: Blits don't exist in the real world. */
61 if (src
->buffer
.b
.b
.nr_samples
> 1 ||
62 dst
->buffer
.b
.b
.nr_samples
> 1)
65 /* Depth-stencil surfaces:
66 * When dst is linear, the DB->CB copy preserves HTILE.
67 * When dst is tiled, the 3D path must be used to update HTILE.
69 if (src
->is_depth
|| dst
->is_depth
)
73 * src: Use the 3D path. DCC decompression is expensive.
74 * dst: Use the 3D path to compress the pixels with DCC.
76 if (vi_dcc_enabled(src
, src_level
) ||
77 vi_dcc_enabled(dst
, dst_level
))
81 * src: Both texture and SDMA paths need decompression. Use SDMA.
82 * dst: If overwriting the whole texture, discard CMASK and use
83 * SDMA. Otherwise, use the 3D path.
85 if (dst
->cmask
.size
&& dst
->dirty_level_mask
& (1 << dst_level
)) {
86 /* The CMASK clear is only enabled for the first level. */
87 assert(dst_level
== 0);
88 if (!util_texrange_covers_whole_level(&dst
->buffer
.b
.b
, dst_level
,
89 dstx
, dsty
, dstz
, src_box
->width
,
90 src_box
->height
, src_box
->depth
))
93 si_texture_discard_cmask(sctx
->screen
, dst
);
96 /* All requirements are met. Prepare textures for SDMA. */
97 if (src
->cmask
.size
&& src
->dirty_level_mask
& (1 << src_level
))
98 sctx
->b
.flush_resource(&sctx
->b
, &src
->buffer
.b
.b
);
100 assert(!(src
->dirty_level_mask
& (1 << src_level
)));
101 assert(!(dst
->dirty_level_mask
& (1 << dst_level
)));
106 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
107 static void si_copy_region_with_blit(struct pipe_context
*pipe
,
108 struct pipe_resource
*dst
,
110 unsigned dstx
, unsigned dsty
, unsigned dstz
,
111 struct pipe_resource
*src
,
113 const struct pipe_box
*src_box
)
115 struct pipe_blit_info blit
;
117 memset(&blit
, 0, sizeof(blit
));
118 blit
.src
.resource
= src
;
119 blit
.src
.format
= src
->format
;
120 blit
.src
.level
= src_level
;
121 blit
.src
.box
= *src_box
;
122 blit
.dst
.resource
= dst
;
123 blit
.dst
.format
= dst
->format
;
124 blit
.dst
.level
= dst_level
;
125 blit
.dst
.box
.x
= dstx
;
126 blit
.dst
.box
.y
= dsty
;
127 blit
.dst
.box
.z
= dstz
;
128 blit
.dst
.box
.width
= src_box
->width
;
129 blit
.dst
.box
.height
= src_box
->height
;
130 blit
.dst
.box
.depth
= src_box
->depth
;
131 blit
.mask
= util_format_get_mask(src
->format
) &
132 util_format_get_mask(dst
->format
);
133 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
136 pipe
->blit(pipe
, &blit
);
140 /* Copy from a full GPU texture to a transfer's staging one. */
141 static void si_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
143 struct si_context
*sctx
= (struct si_context
*)ctx
;
144 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
145 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
146 struct pipe_resource
*src
= transfer
->resource
;
148 if (src
->nr_samples
> 1) {
149 si_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
150 src
, transfer
->level
, &transfer
->box
);
154 sctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
158 /* Copy from a transfer's staging texture to a full GPU one. */
159 static void si_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
161 struct si_context
*sctx
= (struct si_context
*)ctx
;
162 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
163 struct pipe_resource
*dst
= transfer
->resource
;
164 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
165 struct pipe_box sbox
;
167 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
169 if (dst
->nr_samples
> 1) {
170 si_copy_region_with_blit(ctx
, dst
, transfer
->level
,
171 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
176 sctx
->dma_copy(ctx
, dst
, transfer
->level
,
177 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
181 static unsigned si_texture_get_offset(struct si_screen
*sscreen
,
182 struct si_texture
*tex
, unsigned level
,
183 const struct pipe_box
*box
,
185 unsigned *layer_stride
)
187 if (sscreen
->info
.chip_class
>= GFX9
) {
188 *stride
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
189 *layer_stride
= tex
->surface
.u
.gfx9
.surf_slice_size
;
194 /* Each texture is an array of slices. Each slice is an array
195 * of mipmap levels. */
196 return box
->z
* tex
->surface
.u
.gfx9
.surf_slice_size
+
197 tex
->surface
.u
.gfx9
.offset
[level
] +
198 (box
->y
/ tex
->surface
.blk_h
*
199 tex
->surface
.u
.gfx9
.surf_pitch
+
200 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
202 *stride
= tex
->surface
.u
.legacy
.level
[level
].nblk_x
*
204 assert((uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
205 *layer_stride
= (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
208 return tex
->surface
.u
.legacy
.level
[level
].offset
;
210 /* Each texture is an array of mipmap levels. Each level is
211 * an array of slices. */
212 return tex
->surface
.u
.legacy
.level
[level
].offset
+
213 box
->z
* (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
214 (box
->y
/ tex
->surface
.blk_h
*
215 tex
->surface
.u
.legacy
.level
[level
].nblk_x
+
216 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
220 static int si_init_surface(struct si_screen
*sscreen
,
221 struct radeon_surf
*surface
,
222 const struct pipe_resource
*ptex
,
223 unsigned num_color_samples
,
224 enum radeon_surf_mode array_mode
,
225 unsigned pitch_in_bytes_override
,
229 bool is_flushed_depth
,
230 bool tc_compatible_htile
)
232 const struct util_format_description
*desc
=
233 util_format_description(ptex
->format
);
234 bool is_depth
, is_stencil
;
236 unsigned i
, bpe
, flags
= 0;
238 is_depth
= util_format_has_depth(desc
);
239 is_stencil
= util_format_has_stencil(desc
);
241 if (!is_flushed_depth
&&
242 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
243 bpe
= 4; /* stencil is allocated separately on evergreen */
245 bpe
= util_format_get_blocksize(ptex
->format
);
246 assert(util_is_power_of_two_or_zero(bpe
));
249 if (!is_flushed_depth
&& is_depth
) {
250 flags
|= RADEON_SURF_ZBUFFER
;
252 if (tc_compatible_htile
&&
253 (sscreen
->info
.chip_class
>= GFX9
||
254 array_mode
== RADEON_SURF_MODE_2D
)) {
255 /* TC-compatible HTILE only supports Z32_FLOAT.
256 * GFX9 also supports Z16_UNORM.
257 * On VI, promote Z16 to Z32. DB->CB copies will convert
258 * the format for transfers.
260 if (sscreen
->info
.chip_class
== VI
)
263 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
267 flags
|= RADEON_SURF_SBUFFER
;
270 if (sscreen
->info
.chip_class
>= VI
&&
271 (ptex
->flags
& SI_RESOURCE_FLAG_DISABLE_DCC
||
272 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
273 (ptex
->nr_samples
>= 2 && !sscreen
->dcc_msaa_allowed
)))
274 flags
|= RADEON_SURF_DISABLE_DCC
;
276 /* Stoney: 128bpp MSAA textures randomly fail piglit tests with DCC. */
277 if (sscreen
->info
.family
== CHIP_STONEY
&&
278 bpe
== 16 && ptex
->nr_samples
>= 2)
279 flags
|= RADEON_SURF_DISABLE_DCC
;
281 /* VI: DCC clear for 4x and 8x MSAA array textures unimplemented. */
282 if (sscreen
->info
.chip_class
== VI
&&
283 num_color_samples
>= 4 &&
284 ptex
->array_size
> 1)
285 flags
|= RADEON_SURF_DISABLE_DCC
;
287 /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
288 if (sscreen
->info
.chip_class
>= GFX9
&&
289 num_color_samples
>= 4)
290 flags
|= RADEON_SURF_DISABLE_DCC
;
292 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
293 /* This should catch bugs in gallium users setting incorrect flags. */
294 assert(ptex
->nr_samples
<= 1 &&
295 ptex
->array_size
== 1 &&
297 ptex
->last_level
== 0 &&
298 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
300 flags
|= RADEON_SURF_SCANOUT
;
303 if (ptex
->bind
& PIPE_BIND_SHARED
)
304 flags
|= RADEON_SURF_SHAREABLE
;
306 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
307 if (!(ptex
->flags
& SI_RESOURCE_FLAG_FORCE_TILING
))
308 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
310 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, num_color_samples
,
311 flags
, bpe
, array_mode
, surface
);
316 unsigned pitch
= pitch_in_bytes_override
/ bpe
;
318 if (sscreen
->info
.chip_class
>= GFX9
) {
320 surface
->u
.gfx9
.surf_pitch
= pitch
;
321 surface
->u
.gfx9
.surf_slice_size
=
322 (uint64_t)pitch
* surface
->u
.gfx9
.surf_height
* bpe
;
324 surface
->u
.gfx9
.surf_offset
= offset
;
327 surface
->u
.legacy
.level
[0].nblk_x
= pitch
;
328 surface
->u
.legacy
.level
[0].slice_size_dw
=
329 ((uint64_t)pitch
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
332 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
333 surface
->u
.legacy
.level
[i
].offset
+= offset
;
339 static void si_texture_init_metadata(struct si_screen
*sscreen
,
340 struct si_texture
*tex
,
341 struct radeon_bo_metadata
*metadata
)
343 struct radeon_surf
*surface
= &tex
->surface
;
345 memset(metadata
, 0, sizeof(*metadata
));
347 if (sscreen
->info
.chip_class
>= GFX9
) {
348 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
350 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
351 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
352 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
353 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
354 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
355 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
356 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
357 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
358 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
359 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
360 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
361 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
365 static void si_surface_import_metadata(struct si_screen
*sscreen
,
366 struct radeon_surf
*surf
,
367 struct radeon_bo_metadata
*metadata
,
368 enum radeon_surf_mode
*array_mode
,
371 if (sscreen
->info
.chip_class
>= GFX9
) {
372 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
373 *array_mode
= RADEON_SURF_MODE_2D
;
375 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
377 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
378 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
380 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
382 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
383 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
384 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
385 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
386 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
387 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
389 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
390 *array_mode
= RADEON_SURF_MODE_2D
;
391 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
392 *array_mode
= RADEON_SURF_MODE_1D
;
394 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
396 *is_scanout
= metadata
->u
.legacy
.scanout
;
400 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
401 struct si_texture
*tex
)
403 struct si_screen
*sscreen
= sctx
->screen
;
404 struct pipe_context
*ctx
= &sctx
->b
;
406 if (ctx
== sscreen
->aux_context
)
407 mtx_lock(&sscreen
->aux_context_lock
);
409 unsigned n
= sctx
->num_decompress_calls
;
410 ctx
->flush_resource(ctx
, &tex
->buffer
.b
.b
);
412 /* Flush only if any fast clear elimination took place. */
413 if (n
!= sctx
->num_decompress_calls
)
414 ctx
->flush(ctx
, NULL
, 0);
416 if (ctx
== sscreen
->aux_context
)
417 mtx_unlock(&sscreen
->aux_context_lock
);
420 void si_texture_discard_cmask(struct si_screen
*sscreen
,
421 struct si_texture
*tex
)
423 if (!tex
->cmask
.size
)
426 assert(tex
->buffer
.b
.b
.nr_samples
<= 1);
429 memset(&tex
->cmask
, 0, sizeof(tex
->cmask
));
430 tex
->cmask
.base_address_reg
= tex
->buffer
.gpu_address
>> 8;
431 tex
->dirty_level_mask
= 0;
433 tex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
435 if (tex
->cmask_buffer
!= &tex
->buffer
)
436 r600_resource_reference(&tex
->cmask_buffer
, NULL
);
438 /* Notify all contexts about the change. */
439 p_atomic_inc(&sscreen
->dirty_tex_counter
);
440 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
443 static bool si_can_disable_dcc(struct si_texture
*tex
)
445 /* We can't disable DCC if it can be written by another process. */
446 return tex
->dcc_offset
&&
447 (!tex
->buffer
.b
.is_shared
||
448 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
451 static bool si_texture_discard_dcc(struct si_screen
*sscreen
,
452 struct si_texture
*tex
)
454 if (!si_can_disable_dcc(tex
))
457 assert(tex
->dcc_separate_buffer
== NULL
);
462 /* Notify all contexts about the change. */
463 p_atomic_inc(&sscreen
->dirty_tex_counter
);
468 * Disable DCC for the texture. (first decompress, then discard metadata).
470 * There is unresolved multi-context synchronization issue between
471 * screen::aux_context and the current context. If applications do this with
472 * multiple contexts, it's already undefined behavior for them and we don't
473 * have to worry about that. The scenario is:
475 * If context 1 disables DCC and context 2 has queued commands that write
476 * to the texture via CB with DCC enabled, and the order of operations is
478 * context 2 queues draw calls rendering to the texture, but doesn't flush
479 * context 1 disables DCC and flushes
480 * context 1 & 2 reset descriptors and FB state
481 * context 2 flushes (new compressed tiles written by the draw calls)
482 * context 1 & 2 read garbage, because DCC is disabled, yet there are
485 * \param sctx the current context if you have one, or rscreen->aux_context
488 bool si_texture_disable_dcc(struct si_context
*sctx
,
489 struct si_texture
*tex
)
491 struct si_screen
*sscreen
= sctx
->screen
;
493 if (!si_can_disable_dcc(tex
))
496 if (&sctx
->b
== sscreen
->aux_context
)
497 mtx_lock(&sscreen
->aux_context_lock
);
499 /* Decompress DCC. */
500 si_decompress_dcc(sctx
, tex
);
501 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
503 if (&sctx
->b
== sscreen
->aux_context
)
504 mtx_unlock(&sscreen
->aux_context_lock
);
506 return si_texture_discard_dcc(sscreen
, tex
);
509 static void si_reallocate_texture_inplace(struct si_context
*sctx
,
510 struct si_texture
*tex
,
511 unsigned new_bind_flag
,
512 bool invalidate_storage
)
514 struct pipe_screen
*screen
= sctx
->b
.screen
;
515 struct si_texture
*new_tex
;
516 struct pipe_resource templ
= tex
->buffer
.b
.b
;
519 templ
.bind
|= new_bind_flag
;
521 if (tex
->buffer
.b
.is_shared
)
524 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
525 if (tex
->surface
.is_linear
)
528 /* This fails with MSAA, depth, and compressed textures. */
529 if (si_choose_tiling(sctx
->screen
, &templ
, false) !=
530 RADEON_SURF_MODE_LINEAR_ALIGNED
)
534 new_tex
= (struct si_texture
*)screen
->resource_create(screen
, &templ
);
538 /* Copy the pixels to the new texture. */
539 if (!invalidate_storage
) {
540 for (i
= 0; i
<= templ
.last_level
; i
++) {
544 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
545 util_num_layers(&templ
, i
), &box
);
547 sctx
->dma_copy(&sctx
->b
, &new_tex
->buffer
.b
.b
, i
, 0, 0, 0,
548 &tex
->buffer
.b
.b
, i
, &box
);
552 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
553 si_texture_discard_cmask(sctx
->screen
, tex
);
554 si_texture_discard_dcc(sctx
->screen
, tex
);
557 /* Replace the structure fields of tex. */
558 tex
->buffer
.b
.b
.bind
= templ
.bind
;
559 pb_reference(&tex
->buffer
.buf
, new_tex
->buffer
.buf
);
560 tex
->buffer
.gpu_address
= new_tex
->buffer
.gpu_address
;
561 tex
->buffer
.vram_usage
= new_tex
->buffer
.vram_usage
;
562 tex
->buffer
.gart_usage
= new_tex
->buffer
.gart_usage
;
563 tex
->buffer
.bo_size
= new_tex
->buffer
.bo_size
;
564 tex
->buffer
.bo_alignment
= new_tex
->buffer
.bo_alignment
;
565 tex
->buffer
.domains
= new_tex
->buffer
.domains
;
566 tex
->buffer
.flags
= new_tex
->buffer
.flags
;
568 tex
->surface
= new_tex
->surface
;
569 tex
->size
= new_tex
->size
;
570 si_texture_reference(&tex
->flushed_depth_texture
,
571 new_tex
->flushed_depth_texture
);
573 tex
->fmask_offset
= new_tex
->fmask_offset
;
574 tex
->cmask
= new_tex
->cmask
;
575 r600_resource_reference(&tex
->cmask_buffer
, new_tex
->cmask_buffer
);
576 tex
->dcc_offset
= new_tex
->dcc_offset
;
577 tex
->cb_color_info
= new_tex
->cb_color_info
;
578 memcpy(tex
->color_clear_value
, new_tex
->color_clear_value
,
579 sizeof(tex
->color_clear_value
));
580 tex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
582 tex
->htile_offset
= new_tex
->htile_offset
;
583 tex
->depth_clear_value
= new_tex
->depth_clear_value
;
584 tex
->dirty_level_mask
= new_tex
->dirty_level_mask
;
585 tex
->stencil_dirty_level_mask
= new_tex
->stencil_dirty_level_mask
;
586 tex
->db_render_format
= new_tex
->db_render_format
;
587 tex
->stencil_clear_value
= new_tex
->stencil_clear_value
;
588 tex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
589 tex
->depth_cleared
= new_tex
->depth_cleared
;
590 tex
->stencil_cleared
= new_tex
->stencil_cleared
;
591 tex
->upgraded_depth
= new_tex
->upgraded_depth
;
592 tex
->db_compatible
= new_tex
->db_compatible
;
593 tex
->can_sample_z
= new_tex
->can_sample_z
;
594 tex
->can_sample_s
= new_tex
->can_sample_s
;
596 tex
->separate_dcc_dirty
= new_tex
->separate_dcc_dirty
;
597 tex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
598 r600_resource_reference(&tex
->dcc_separate_buffer
,
599 new_tex
->dcc_separate_buffer
);
600 r600_resource_reference(&tex
->last_dcc_separate_buffer
,
601 new_tex
->last_dcc_separate_buffer
);
603 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
604 assert(!tex
->htile_offset
);
605 assert(!tex
->cmask
.size
);
606 assert(!tex
->surface
.fmask_size
);
607 assert(!tex
->dcc_offset
);
608 assert(!tex
->is_depth
);
611 si_texture_reference(&new_tex
, NULL
);
613 p_atomic_inc(&sctx
->screen
->dirty_tex_counter
);
616 static uint32_t si_get_bo_metadata_word1(struct si_screen
*sscreen
)
618 return (ATI_VENDOR_ID
<< 16) | sscreen
->info
.pci_id
;
621 static void si_query_opaque_metadata(struct si_screen
*sscreen
,
622 struct si_texture
*tex
,
623 struct radeon_bo_metadata
*md
)
625 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
626 static const unsigned char swizzle
[] = {
633 bool is_array
= util_texture_is_array(res
->target
);
635 if (!sscreen
->info
.has_bo_metadata
)
638 assert(tex
->dcc_separate_buffer
== NULL
);
639 assert(tex
->surface
.fmask_size
== 0);
641 /* Metadata image format format version 1:
642 * [0] = 1 (metadata format identifier)
643 * [1] = (VENDOR_ID << 16) | PCI_ID
644 * [2:9] = image descriptor for the whole resource
645 * [2] is always 0, because the base address is cleared
646 * [9] is the DCC offset bits [39:8] from the beginning of
648 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
651 md
->metadata
[0] = 1; /* metadata image format version 1 */
653 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
654 md
->metadata
[1] = si_get_bo_metadata_word1(sscreen
);
656 si_make_texture_descriptor(sscreen
, tex
, true,
657 res
->target
, res
->format
,
658 swizzle
, 0, res
->last_level
, 0,
659 is_array
? res
->array_size
- 1 : 0,
660 res
->width0
, res
->height0
, res
->depth0
,
663 si_set_mutable_tex_desc_fields(sscreen
, tex
, &tex
->surface
.u
.legacy
.level
[0],
664 0, 0, tex
->surface
.blk_w
, false, desc
);
666 /* Clear the base address and set the relative DCC offset. */
668 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
669 desc
[7] = tex
->dcc_offset
>> 8;
671 /* Dwords [2:9] contain the image descriptor. */
672 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
673 md
->size_metadata
= 10 * 4;
675 /* Dwords [10:..] contain the mipmap level offsets. */
676 if (sscreen
->info
.chip_class
<= VI
) {
677 for (i
= 0; i
<= res
->last_level
; i
++)
678 md
->metadata
[10+i
] = tex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
680 md
->size_metadata
+= (1 + res
->last_level
) * 4;
684 static void si_apply_opaque_metadata(struct si_screen
*sscreen
,
685 struct si_texture
*tex
,
686 struct radeon_bo_metadata
*md
)
688 uint32_t *desc
= &md
->metadata
[2];
690 if (sscreen
->info
.chip_class
< VI
)
693 /* Return if DCC is enabled. The texture should be set up with it
696 if (md
->size_metadata
>= 10 * 4 && /* at least 2(header) + 8(desc) dwords */
697 md
->metadata
[0] != 0 &&
698 md
->metadata
[1] == si_get_bo_metadata_word1(sscreen
) &&
699 G_008F28_COMPRESSION_EN(desc
[6])) {
700 tex
->dcc_offset
= (uint64_t)desc
[7] << 8;
704 /* Disable DCC. These are always set by texture_from_handle and must
710 static boolean
si_texture_get_handle(struct pipe_screen
* screen
,
711 struct pipe_context
*ctx
,
712 struct pipe_resource
*resource
,
713 struct winsys_handle
*whandle
,
716 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
717 struct si_context
*sctx
;
718 struct r600_resource
*res
= r600_resource(resource
);
719 struct si_texture
*tex
= (struct si_texture
*)resource
;
720 struct radeon_bo_metadata metadata
;
721 bool update_metadata
= false;
722 unsigned stride
, offset
, slice_size
;
725 ctx
= threaded_context_unwrap_sync(ctx
);
726 sctx
= (struct si_context
*)(ctx
? ctx
: sscreen
->aux_context
);
728 if (resource
->target
!= PIPE_BUFFER
) {
729 /* This is not supported now, but it might be required for OpenCL
730 * interop in the future.
732 if (resource
->nr_samples
> 1 || tex
->is_depth
)
735 /* Move a suballocated texture into a non-suballocated allocation. */
736 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
737 tex
->surface
.tile_swizzle
||
738 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
739 sscreen
->info
.has_local_buffers
&&
740 whandle
->type
!= WINSYS_HANDLE_TYPE_KMS
)) {
741 assert(!res
->b
.is_shared
);
742 si_reallocate_texture_inplace(sctx
, tex
,
743 PIPE_BIND_SHARED
, false);
745 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
746 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
747 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
748 assert(tex
->surface
.tile_swizzle
== 0);
751 /* Since shader image stores don't support DCC on VI,
752 * disable it for external clients that want write
755 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& tex
->dcc_offset
) {
756 if (si_texture_disable_dcc(sctx
, tex
)) {
757 update_metadata
= true;
758 /* si_texture_disable_dcc flushes the context */
763 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
764 (tex
->cmask
.size
|| tex
->dcc_offset
)) {
765 /* Eliminate fast clear (both CMASK and DCC) */
766 si_eliminate_fast_color_clear(sctx
, tex
);
767 /* eliminate_fast_color_clear flushes the context */
770 /* Disable CMASK if flush_resource isn't going
774 si_texture_discard_cmask(sscreen
, tex
);
778 if (!res
->b
.is_shared
|| update_metadata
) {
779 si_texture_init_metadata(sscreen
, tex
, &metadata
);
780 si_query_opaque_metadata(sscreen
, tex
, &metadata
);
782 sscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
785 if (sscreen
->info
.chip_class
>= GFX9
) {
786 offset
= tex
->surface
.u
.gfx9
.surf_offset
;
787 stride
= tex
->surface
.u
.gfx9
.surf_pitch
*
789 slice_size
= tex
->surface
.u
.gfx9
.surf_slice_size
;
791 offset
= tex
->surface
.u
.legacy
.level
[0].offset
;
792 stride
= tex
->surface
.u
.legacy
.level
[0].nblk_x
*
794 slice_size
= (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
797 /* Buffer exports are for the OpenCL interop. */
798 /* Move a suballocated buffer into a non-suballocated allocation. */
799 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
800 /* A DMABUF export always fails if the BO is local. */
801 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
802 sscreen
->info
.has_local_buffers
)) {
803 assert(!res
->b
.is_shared
);
805 /* Allocate a new buffer with PIPE_BIND_SHARED. */
806 struct pipe_resource templ
= res
->b
.b
;
807 templ
.bind
|= PIPE_BIND_SHARED
;
809 struct pipe_resource
*newb
=
810 screen
->resource_create(screen
, &templ
);
814 /* Copy the old buffer contents to the new one. */
816 u_box_1d(0, newb
->width0
, &box
);
817 sctx
->b
.resource_copy_region(&sctx
->b
, newb
, 0, 0, 0, 0,
820 /* Move the new buffer storage to the old pipe_resource. */
821 si_replace_buffer_storage(&sctx
->b
, &res
->b
.b
, newb
);
822 pipe_resource_reference(&newb
, NULL
);
824 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
825 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
835 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
837 if (res
->b
.is_shared
) {
838 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
841 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
842 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
843 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
845 res
->b
.is_shared
= true;
846 res
->external_usage
= usage
;
849 return sscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
850 slice_size
, whandle
);
853 static void si_texture_destroy(struct pipe_screen
*screen
,
854 struct pipe_resource
*ptex
)
856 struct si_texture
*tex
= (struct si_texture
*)ptex
;
857 struct r600_resource
*resource
= &tex
->buffer
;
859 si_texture_reference(&tex
->flushed_depth_texture
, NULL
);
861 if (tex
->cmask_buffer
!= &tex
->buffer
) {
862 r600_resource_reference(&tex
->cmask_buffer
, NULL
);
864 pb_reference(&resource
->buf
, NULL
);
865 r600_resource_reference(&tex
->dcc_separate_buffer
, NULL
);
866 r600_resource_reference(&tex
->last_dcc_separate_buffer
, NULL
);
870 static const struct u_resource_vtbl si_texture_vtbl
;
872 void si_texture_get_cmask_info(struct si_screen
*sscreen
,
873 struct si_texture
*tex
,
874 struct r600_cmask_info
*out
)
876 unsigned pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
877 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
878 unsigned cl_width
, cl_height
;
880 if (sscreen
->info
.chip_class
>= GFX9
) {
881 out
->alignment
= tex
->surface
.u
.gfx9
.cmask_alignment
;
882 out
->size
= tex
->surface
.u
.gfx9
.cmask_size
;
899 case 16: /* Hawaii */
908 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
910 unsigned width
= align(tex
->buffer
.b
.b
.width0
, cl_width
*8);
911 unsigned height
= align(tex
->buffer
.b
.b
.height0
, cl_height
*8);
912 unsigned slice_elements
= (width
* height
) / (8*8);
914 /* Each element of CMASK is a nibble. */
915 unsigned slice_bytes
= slice_elements
/ 2;
917 out
->slice_tile_max
= (width
* height
) / (128*128);
918 if (out
->slice_tile_max
)
919 out
->slice_tile_max
-= 1;
921 out
->alignment
= MAX2(256, base_align
);
922 out
->size
= util_num_layers(&tex
->buffer
.b
.b
, 0) *
923 align(slice_bytes
, base_align
);
926 static void si_texture_allocate_cmask(struct si_screen
*sscreen
,
927 struct si_texture
*tex
)
929 si_texture_get_cmask_info(sscreen
, tex
, &tex
->cmask
);
931 tex
->cmask
.offset
= align64(tex
->size
, tex
->cmask
.alignment
);
932 tex
->size
= tex
->cmask
.offset
+ tex
->cmask
.size
;
934 tex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
937 static void si_texture_get_htile_size(struct si_screen
*sscreen
,
938 struct si_texture
*tex
)
940 unsigned cl_width
, cl_height
, width
, height
;
941 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
942 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
944 assert(sscreen
->info
.chip_class
<= VI
);
946 tex
->surface
.htile_size
= 0;
948 if (tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
949 !sscreen
->info
.htile_cmask_support_1d_tiling
)
952 /* Overalign HTILE on P2 configs to work around GPU hangs in
953 * piglit/depthstencil-render-miplevels 585.
955 * This has been confirmed to help Kabini & Stoney, where the hangs
956 * are always reproducible. I think I have seen the test hang
957 * on Carrizo too, though it was very rare there.
959 if (sscreen
->info
.chip_class
>= CIK
&& num_pipes
< 4)
988 width
= align(tex
->buffer
.b
.b
.width0
, cl_width
* 8);
989 height
= align(tex
->buffer
.b
.b
.height0
, cl_height
* 8);
991 slice_elements
= (width
* height
) / (8 * 8);
992 slice_bytes
= slice_elements
* 4;
994 pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
995 base_align
= num_pipes
* pipe_interleave_bytes
;
997 tex
->surface
.htile_alignment
= base_align
;
998 tex
->surface
.htile_size
=
999 util_num_layers(&tex
->buffer
.b
.b
, 0) *
1000 align(slice_bytes
, base_align
);
1003 static void si_texture_allocate_htile(struct si_screen
*sscreen
,
1004 struct si_texture
*tex
)
1006 if (sscreen
->info
.chip_class
<= VI
&& !tex
->tc_compatible_htile
)
1007 si_texture_get_htile_size(sscreen
, tex
);
1009 if (!tex
->surface
.htile_size
)
1012 tex
->htile_offset
= align(tex
->size
, tex
->surface
.htile_alignment
);
1013 tex
->size
= tex
->htile_offset
+ tex
->surface
.htile_size
;
1016 void si_print_texture_info(struct si_screen
*sscreen
,
1017 struct si_texture
*tex
, struct u_log_context
*log
)
1021 /* Common parameters. */
1022 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
1023 "blk_h=%u, array_size=%u, last_level=%u, "
1024 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
1025 tex
->buffer
.b
.b
.width0
, tex
->buffer
.b
.b
.height0
,
1026 tex
->buffer
.b
.b
.depth0
, tex
->surface
.blk_w
,
1028 tex
->buffer
.b
.b
.array_size
, tex
->buffer
.b
.b
.last_level
,
1029 tex
->surface
.bpe
, tex
->buffer
.b
.b
.nr_samples
,
1030 tex
->surface
.flags
, util_format_short_name(tex
->buffer
.b
.b
.format
));
1032 if (sscreen
->info
.chip_class
>= GFX9
) {
1033 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
1034 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
1035 tex
->surface
.surf_size
,
1036 tex
->surface
.u
.gfx9
.surf_slice_size
,
1037 tex
->surface
.surf_alignment
,
1038 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
1039 tex
->surface
.u
.gfx9
.surf
.epitch
,
1040 tex
->surface
.u
.gfx9
.surf_pitch
);
1042 if (tex
->surface
.fmask_size
) {
1043 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
1044 "alignment=%u, swmode=%u, epitch=%u\n",
1046 tex
->surface
.fmask_size
,
1047 tex
->surface
.fmask_alignment
,
1048 tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1049 tex
->surface
.u
.gfx9
.fmask
.epitch
);
1052 if (tex
->cmask
.size
) {
1053 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", "
1054 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1056 tex
->surface
.u
.gfx9
.cmask_size
,
1057 tex
->surface
.u
.gfx9
.cmask_alignment
,
1058 tex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1059 tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1062 if (tex
->htile_offset
) {
1063 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, alignment=%u, "
1064 "rb_aligned=%u, pipe_aligned=%u\n",
1066 tex
->surface
.htile_size
,
1067 tex
->surface
.htile_alignment
,
1068 tex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1069 tex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1072 if (tex
->dcc_offset
) {
1073 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, "
1074 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1075 tex
->dcc_offset
, tex
->surface
.dcc_size
,
1076 tex
->surface
.dcc_alignment
,
1077 tex
->surface
.u
.gfx9
.dcc_pitch_max
,
1078 tex
->surface
.num_dcc_levels
);
1081 if (tex
->surface
.u
.gfx9
.stencil_offset
) {
1082 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1083 tex
->surface
.u
.gfx9
.stencil_offset
,
1084 tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1085 tex
->surface
.u
.gfx9
.stencil
.epitch
);
1090 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1091 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1092 tex
->surface
.surf_size
, tex
->surface
.surf_alignment
, tex
->surface
.u
.legacy
.bankw
,
1093 tex
->surface
.u
.legacy
.bankh
, tex
->surface
.u
.legacy
.num_banks
, tex
->surface
.u
.legacy
.mtilea
,
1094 tex
->surface
.u
.legacy
.tile_split
, tex
->surface
.u
.legacy
.pipe_config
,
1095 (tex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1097 if (tex
->surface
.fmask_size
)
1098 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1099 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1100 tex
->fmask_offset
, tex
->surface
.fmask_size
, tex
->surface
.fmask_alignment
,
1101 tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
,
1102 tex
->surface
.u
.legacy
.fmask
.bankh
,
1103 tex
->surface
.u
.legacy
.fmask
.slice_tile_max
,
1104 tex
->surface
.u
.legacy
.fmask
.tiling_index
);
1106 if (tex
->cmask
.size
)
1107 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1108 "slice_tile_max=%u\n",
1109 tex
->cmask
.offset
, tex
->cmask
.size
, tex
->cmask
.alignment
,
1110 tex
->cmask
.slice_tile_max
);
1112 if (tex
->htile_offset
)
1113 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, "
1114 "alignment=%u, TC_compatible = %u\n",
1115 tex
->htile_offset
, tex
->surface
.htile_size
,
1116 tex
->surface
.htile_alignment
,
1117 tex
->tc_compatible_htile
);
1119 if (tex
->dcc_offset
) {
1120 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, alignment=%u\n",
1121 tex
->dcc_offset
, tex
->surface
.dcc_size
,
1122 tex
->surface
.dcc_alignment
);
1123 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1124 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%u, "
1125 "fast_clear_size=%u\n",
1126 i
, i
< tex
->surface
.num_dcc_levels
,
1127 tex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1128 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1131 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1132 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1133 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1134 "mode=%u, tiling_index = %u\n",
1135 i
, tex
->surface
.u
.legacy
.level
[i
].offset
,
1136 (uint64_t)tex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
1137 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1138 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1139 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1140 tex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1141 tex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1142 tex
->surface
.u
.legacy
.level
[i
].mode
,
1143 tex
->surface
.u
.legacy
.tiling_index
[i
]);
1145 if (tex
->surface
.has_stencil
) {
1146 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1147 tex
->surface
.u
.legacy
.stencil_tile_split
);
1148 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++) {
1149 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1150 "slice_size=%"PRIu64
", npix_x=%u, "
1151 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1152 "mode=%u, tiling_index = %u\n",
1153 i
, tex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1154 (uint64_t)tex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
1155 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1156 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1157 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1158 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1159 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1160 tex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1161 tex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1166 /* Common processing for si_texture_create and si_texture_from_handle */
1167 static struct si_texture
*
1168 si_texture_create_object(struct pipe_screen
*screen
,
1169 const struct pipe_resource
*base
,
1170 unsigned num_color_samples
,
1171 struct pb_buffer
*buf
,
1172 struct radeon_surf
*surface
)
1174 struct si_texture
*tex
;
1175 struct r600_resource
*resource
;
1176 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1178 tex
= CALLOC_STRUCT(si_texture
);
1182 resource
= &tex
->buffer
;
1183 resource
->b
.b
= *base
;
1184 resource
->b
.b
.next
= NULL
;
1185 resource
->b
.vtbl
= &si_texture_vtbl
;
1186 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1187 resource
->b
.b
.screen
= screen
;
1189 /* don't include stencil-only formats which we don't support for rendering */
1190 tex
->is_depth
= util_format_has_depth(util_format_description(tex
->buffer
.b
.b
.format
));
1192 tex
->surface
= *surface
;
1193 tex
->size
= tex
->surface
.surf_size
;
1194 tex
->num_color_samples
= num_color_samples
;
1196 tex
->tc_compatible_htile
= tex
->surface
.htile_size
!= 0 &&
1197 (tex
->surface
.flags
&
1198 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1200 /* TC-compatible HTILE:
1201 * - VI only supports Z32_FLOAT.
1202 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1203 if (tex
->tc_compatible_htile
) {
1204 if (sscreen
->info
.chip_class
>= GFX9
&&
1205 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1206 tex
->db_render_format
= base
->format
;
1208 tex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1209 tex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1210 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1213 tex
->db_render_format
= base
->format
;
1216 /* Applies to GCN. */
1217 tex
->last_msaa_resolve_target_micro_mode
= tex
->surface
.micro_tile_mode
;
1219 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1220 * between frames, so the only thing that can enable separate DCC
1221 * with DRI2 is multiple slow clears within a frame.
1223 tex
->ps_draw_ratio
= 0;
1225 if (tex
->is_depth
) {
1226 if (sscreen
->info
.chip_class
>= GFX9
) {
1227 tex
->can_sample_z
= true;
1228 tex
->can_sample_s
= true;
1230 tex
->can_sample_z
= !tex
->surface
.u
.legacy
.depth_adjusted
;
1231 tex
->can_sample_s
= !tex
->surface
.u
.legacy
.stencil_adjusted
;
1234 if (!(base
->flags
& (SI_RESOURCE_FLAG_TRANSFER
|
1235 SI_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1236 tex
->db_compatible
= true;
1238 if (!(sscreen
->debug_flags
& DBG(NO_HYPERZ
)))
1239 si_texture_allocate_htile(sscreen
, tex
);
1242 if (base
->nr_samples
> 1 &&
1244 !(sscreen
->debug_flags
& DBG(NO_FMASK
))) {
1245 /* Allocate FMASK. */
1246 tex
->fmask_offset
= align64(tex
->size
,
1247 tex
->surface
.fmask_alignment
);
1248 tex
->size
= tex
->fmask_offset
+ tex
->surface
.fmask_size
;
1250 si_texture_allocate_cmask(sscreen
, tex
);
1251 tex
->cmask_buffer
= &tex
->buffer
;
1253 if (!tex
->surface
.fmask_size
|| !tex
->cmask
.size
) {
1259 /* Shared textures must always set up DCC here.
1260 * If it's not present, it will be disabled by
1261 * apply_opaque_metadata later.
1263 if (tex
->surface
.dcc_size
&&
1264 (buf
|| !(sscreen
->debug_flags
& DBG(NO_DCC
))) &&
1265 !(tex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1266 /* Reserve space for the DCC buffer. */
1267 tex
->dcc_offset
= align64(tex
->size
, tex
->surface
.dcc_alignment
);
1268 tex
->size
= tex
->dcc_offset
+ tex
->surface
.dcc_size
;
1272 /* Now create the backing buffer. */
1274 si_init_resource_fields(sscreen
, resource
, tex
->size
,
1275 tex
->surface
.surf_alignment
);
1277 if (!si_alloc_resource(sscreen
, resource
)) {
1282 resource
->buf
= buf
;
1283 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1284 resource
->bo_size
= buf
->size
;
1285 resource
->bo_alignment
= buf
->alignment
;
1286 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1287 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1288 resource
->vram_usage
= buf
->size
;
1289 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1290 resource
->gart_usage
= buf
->size
;
1293 if (tex
->cmask
.size
) {
1294 /* Initialize the cmask to 0xCC (= compressed state). */
1295 si_screen_clear_buffer(sscreen
, &tex
->cmask_buffer
->b
.b
,
1296 tex
->cmask
.offset
, tex
->cmask
.size
,
1299 if (tex
->htile_offset
) {
1300 uint32_t clear_value
= 0;
1302 if (sscreen
->info
.chip_class
>= GFX9
|| tex
->tc_compatible_htile
)
1303 clear_value
= 0x0000030F;
1305 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1307 tex
->surface
.htile_size
,
1311 /* Initialize DCC only if the texture is not being imported. */
1312 if (!buf
&& tex
->dcc_offset
) {
1313 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1315 tex
->surface
.dcc_size
,
1319 /* Initialize the CMASK base register value. */
1320 tex
->cmask
.base_address_reg
=
1321 (tex
->buffer
.gpu_address
+ tex
->cmask
.offset
) >> 8;
1323 if (sscreen
->debug_flags
& DBG(VM
)) {
1324 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1325 tex
->buffer
.gpu_address
,
1326 tex
->buffer
.gpu_address
+ tex
->buffer
.buf
->size
,
1327 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+1,
1328 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1331 if (sscreen
->debug_flags
& DBG(TEX
)) {
1333 struct u_log_context log
;
1334 u_log_context_init(&log
);
1335 si_print_texture_info(sscreen
, tex
, &log
);
1336 u_log_new_page_print(&log
, stdout
);
1338 u_log_context_destroy(&log
);
1344 static enum radeon_surf_mode
1345 si_choose_tiling(struct si_screen
*sscreen
,
1346 const struct pipe_resource
*templ
, bool tc_compatible_htile
)
1348 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1349 bool force_tiling
= templ
->flags
& SI_RESOURCE_FLAG_FORCE_TILING
;
1350 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1351 !(templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
);
1353 /* MSAA resources must be 2D tiled. */
1354 if (templ
->nr_samples
> 1)
1355 return RADEON_SURF_MODE_2D
;
1357 /* Transfer resources should be linear. */
1358 if (templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
)
1359 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1361 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
1362 * which requires 2D tiling.
1364 if (sscreen
->info
.chip_class
== VI
&& tc_compatible_htile
)
1365 return RADEON_SURF_MODE_2D
;
1367 /* Handle common candidates for the linear mode.
1368 * Compressed textures and DB surfaces must always be tiled.
1370 if (!force_tiling
&&
1371 !is_depth_stencil
&&
1372 !util_format_is_compressed(templ
->format
)) {
1373 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1374 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1376 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. */
1377 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1378 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1380 /* Cursors are linear on SI.
1381 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1382 if (templ
->bind
& PIPE_BIND_CURSOR
)
1383 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1385 if (templ
->bind
& PIPE_BIND_LINEAR
)
1386 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1388 /* Textures with a very small height are recommended to be linear. */
1389 if (templ
->target
== PIPE_TEXTURE_1D
||
1390 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1391 /* Only very thin and long 2D textures should benefit from
1392 * linear_aligned. */
1393 (templ
->width0
> 8 && templ
->height0
<= 2))
1394 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1396 /* Textures likely to be mapped often. */
1397 if (templ
->usage
== PIPE_USAGE_STAGING
||
1398 templ
->usage
== PIPE_USAGE_STREAM
)
1399 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1402 /* Make small textures 1D tiled. */
1403 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1404 (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1405 return RADEON_SURF_MODE_1D
;
1407 /* The allocator will switch to 1D if needed. */
1408 return RADEON_SURF_MODE_2D
;
1411 static unsigned si_get_num_color_samples(struct si_screen
*sscreen
,
1412 const struct pipe_resource
*templ
,
1415 if (!imported
&& templ
->nr_samples
>= 2 &&
1416 sscreen
->eqaa_force_color_samples
)
1417 return sscreen
->eqaa_force_color_samples
;
1419 return CLAMP(templ
->nr_samples
, 1, 8);
1422 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1423 const struct pipe_resource
*templ
)
1425 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1426 bool is_zs
= util_format_is_depth_or_stencil(templ
->format
);
1428 if (templ
->nr_samples
>= 2) {
1429 /* This is hackish (overwriting the const pipe_resource template),
1430 * but should be harmless and state trackers can also see
1431 * the overriden number of samples in the created pipe_resource.
1433 if (is_zs
&& sscreen
->eqaa_force_z_samples
) {
1434 ((struct pipe_resource
*)templ
)->nr_samples
=
1435 sscreen
->eqaa_force_z_samples
;
1436 } else if (!is_zs
&& sscreen
->eqaa_force_color_samples
) {
1437 ((struct pipe_resource
*)templ
)->nr_samples
=
1438 sscreen
->eqaa_force_coverage_samples
;
1442 struct radeon_surf surface
= {0};
1443 bool is_flushed_depth
= templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1444 bool tc_compatible_htile
=
1445 sscreen
->info
.chip_class
>= VI
&&
1446 /* There are issues with TC-compatible HTILE on Tonga (and
1447 * Iceland is the same design), and documented bug workarounds
1448 * don't help. For example, this fails:
1449 * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow -auto
1451 sscreen
->info
.family
!= CHIP_TONGA
&&
1452 sscreen
->info
.family
!= CHIP_ICELAND
&&
1453 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1454 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) &&
1455 !is_flushed_depth
&&
1456 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1458 unsigned num_color_samples
= si_get_num_color_samples(sscreen
, templ
, false);
1461 r
= si_init_surface(sscreen
, &surface
, templ
, num_color_samples
,
1462 si_choose_tiling(sscreen
, templ
, tc_compatible_htile
),
1463 0, 0, false, false, is_flushed_depth
,
1464 tc_compatible_htile
);
1469 return (struct pipe_resource
*)
1470 si_texture_create_object(screen
, templ
, num_color_samples
,
1474 static struct pipe_resource
*si_texture_from_winsys_buffer(struct si_screen
*sscreen
,
1475 const struct pipe_resource
*templ
,
1476 struct pb_buffer
*buf
,
1482 enum radeon_surf_mode array_mode
;
1483 struct radeon_surf surface
= {};
1484 struct radeon_bo_metadata metadata
= {};
1485 struct si_texture
*tex
;
1490 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1491 si_surface_import_metadata(sscreen
, &surface
, &metadata
,
1492 &array_mode
, &is_scanout
);
1495 * The bo metadata is unset for un-dedicated images. So we fall
1496 * back to linear. See answer to question 5 of the
1497 * VK_KHX_external_memory spec for some details.
1499 * It is possible that this case isn't going to work if the
1500 * surface pitch isn't correctly aligned by default.
1502 * In order to support it correctly we require multi-image
1503 * metadata to be syncrhonized between radv and radeonsi. The
1504 * semantics of associating multiple image metadata to a memory
1505 * object on the vulkan export side are not concretely defined
1508 * All the use cases we are aware of at the moment for memory
1509 * objects use dedicated allocations. So lets keep the initial
1510 * implementation simple.
1512 * A possible alternative is to attempt to reconstruct the
1513 * tiling information when the TexParameter TEXTURE_TILING_EXT
1516 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1520 unsigned num_color_samples
= si_get_num_color_samples(sscreen
, templ
, true);
1522 r
= si_init_surface(sscreen
, &surface
, templ
, num_color_samples
,
1523 array_mode
, stride
, offset
, true, is_scanout
,
1528 tex
= si_texture_create_object(&sscreen
->b
, templ
, num_color_samples
,
1533 tex
->buffer
.b
.is_shared
= true;
1534 tex
->buffer
.external_usage
= usage
;
1536 si_apply_opaque_metadata(sscreen
, tex
, &metadata
);
1538 assert(tex
->surface
.tile_swizzle
== 0);
1539 return &tex
->buffer
.b
.b
;
1542 static struct pipe_resource
*si_texture_from_handle(struct pipe_screen
*screen
,
1543 const struct pipe_resource
*templ
,
1544 struct winsys_handle
*whandle
,
1547 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1548 struct pb_buffer
*buf
= NULL
;
1549 unsigned stride
= 0, offset
= 0;
1551 /* Support only 2D textures without mipmaps */
1552 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1553 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1556 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
, &stride
, &offset
);
1560 return si_texture_from_winsys_buffer(sscreen
, templ
, buf
, stride
,
1561 offset
, usage
, true);
1564 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1565 struct pipe_resource
*texture
,
1566 struct si_texture
**staging
)
1568 struct si_texture
*tex
= (struct si_texture
*)texture
;
1569 struct pipe_resource resource
;
1570 struct si_texture
**flushed_depth_texture
= staging
?
1571 staging
: &tex
->flushed_depth_texture
;
1572 enum pipe_format pipe_format
= texture
->format
;
1575 if (tex
->flushed_depth_texture
)
1576 return true; /* it's ready */
1578 if (!tex
->can_sample_z
&& tex
->can_sample_s
) {
1579 switch (pipe_format
) {
1580 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1581 /* Save memory by not allocating the S plane. */
1582 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1584 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1585 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1586 /* Save memory bandwidth by not copying the
1587 * stencil part during flush.
1589 * This potentially increases memory bandwidth
1590 * if an application uses both Z and S texturing
1591 * simultaneously (a flushed Z24S8 texture
1592 * would be stored compactly), but how often
1593 * does that really happen?
1595 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1599 } else if (!tex
->can_sample_s
&& tex
->can_sample_z
) {
1600 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1602 /* DB->CB copies to an 8bpp surface don't work. */
1603 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1607 memset(&resource
, 0, sizeof(resource
));
1608 resource
.target
= texture
->target
;
1609 resource
.format
= pipe_format
;
1610 resource
.width0
= texture
->width0
;
1611 resource
.height0
= texture
->height0
;
1612 resource
.depth0
= texture
->depth0
;
1613 resource
.array_size
= texture
->array_size
;
1614 resource
.last_level
= texture
->last_level
;
1615 resource
.nr_samples
= texture
->nr_samples
;
1616 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1617 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1618 resource
.flags
= texture
->flags
| SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1621 resource
.flags
|= SI_RESOURCE_FLAG_TRANSFER
;
1623 *flushed_depth_texture
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1624 if (*flushed_depth_texture
== NULL
) {
1625 PRINT_ERR("failed to create temporary texture to hold flushed depth\n");
1632 * Initialize the pipe_resource descriptor to be of the same size as the box,
1633 * which is supposed to hold a subregion of the texture "orig" at the given
1636 static void si_init_temp_resource_from_box(struct pipe_resource
*res
,
1637 struct pipe_resource
*orig
,
1638 const struct pipe_box
*box
,
1639 unsigned level
, unsigned flags
)
1641 memset(res
, 0, sizeof(*res
));
1642 res
->format
= orig
->format
;
1643 res
->width0
= box
->width
;
1644 res
->height0
= box
->height
;
1646 res
->array_size
= 1;
1647 res
->usage
= flags
& SI_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1650 /* We must set the correct texture target and dimensions for a 3D box. */
1651 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1652 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1653 res
->array_size
= box
->depth
;
1655 res
->target
= PIPE_TEXTURE_2D
;
1659 static bool si_can_invalidate_texture(struct si_screen
*sscreen
,
1660 struct si_texture
*tex
,
1661 unsigned transfer_usage
,
1662 const struct pipe_box
*box
)
1664 return !tex
->buffer
.b
.is_shared
&&
1665 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1666 tex
->buffer
.b
.b
.last_level
== 0 &&
1667 util_texrange_covers_whole_level(&tex
->buffer
.b
.b
, 0,
1668 box
->x
, box
->y
, box
->z
,
1669 box
->width
, box
->height
,
1673 static void si_texture_invalidate_storage(struct si_context
*sctx
,
1674 struct si_texture
*tex
)
1676 struct si_screen
*sscreen
= sctx
->screen
;
1678 /* There is no point in discarding depth and tiled buffers. */
1679 assert(!tex
->is_depth
);
1680 assert(tex
->surface
.is_linear
);
1682 /* Reallocate the buffer in the same pipe_resource. */
1683 si_alloc_resource(sscreen
, &tex
->buffer
);
1685 /* Initialize the CMASK base address (needed even without CMASK). */
1686 tex
->cmask
.base_address_reg
=
1687 (tex
->buffer
.gpu_address
+ tex
->cmask
.offset
) >> 8;
1689 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1691 sctx
->num_alloc_tex_transfer_bytes
+= tex
->size
;
1694 static void *si_texture_transfer_map(struct pipe_context
*ctx
,
1695 struct pipe_resource
*texture
,
1698 const struct pipe_box
*box
,
1699 struct pipe_transfer
**ptransfer
)
1701 struct si_context
*sctx
= (struct si_context
*)ctx
;
1702 struct si_texture
*tex
= (struct si_texture
*)texture
;
1703 struct r600_transfer
*trans
;
1704 struct r600_resource
*buf
;
1705 unsigned offset
= 0;
1707 bool use_staging_texture
= false;
1709 assert(!(texture
->flags
& SI_RESOURCE_FLAG_TRANSFER
));
1710 assert(box
->width
&& box
->height
&& box
->depth
);
1712 /* Depth textures use staging unconditionally. */
1713 if (!tex
->is_depth
) {
1714 /* Degrade the tile mode if we get too many transfers on APUs.
1715 * On dGPUs, the staging texture is always faster.
1716 * Only count uploads that are at least 4x4 pixels large.
1718 if (!sctx
->screen
->info
.has_dedicated_vram
&&
1720 box
->width
>= 4 && box
->height
>= 4 &&
1721 p_atomic_inc_return(&tex
->num_level0_transfers
) == 10) {
1722 bool can_invalidate
=
1723 si_can_invalidate_texture(sctx
->screen
, tex
,
1726 si_reallocate_texture_inplace(sctx
, tex
,
1731 /* Tiled textures need to be converted into a linear texture for CPU
1732 * access. The staging texture is always linear and is placed in GART.
1734 * Reading from VRAM or GTT WC is slow, always use the staging
1735 * texture in this case.
1737 * Use the staging texture for uploads if the underlying BO
1740 if (!tex
->surface
.is_linear
)
1741 use_staging_texture
= true;
1742 else if (usage
& PIPE_TRANSFER_READ
)
1743 use_staging_texture
=
1744 tex
->buffer
.domains
& RADEON_DOMAIN_VRAM
||
1745 tex
->buffer
.flags
& RADEON_FLAG_GTT_WC
;
1746 /* Write & linear only: */
1747 else if (si_rings_is_buffer_referenced(sctx
, tex
->buffer
.buf
,
1748 RADEON_USAGE_READWRITE
) ||
1749 !sctx
->ws
->buffer_wait(tex
->buffer
.buf
, 0,
1750 RADEON_USAGE_READWRITE
)) {
1752 if (si_can_invalidate_texture(sctx
->screen
, tex
,
1754 si_texture_invalidate_storage(sctx
, tex
);
1756 use_staging_texture
= true;
1760 trans
= CALLOC_STRUCT(r600_transfer
);
1763 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1764 trans
->b
.b
.level
= level
;
1765 trans
->b
.b
.usage
= usage
;
1766 trans
->b
.b
.box
= *box
;
1768 if (tex
->is_depth
) {
1769 struct si_texture
*staging_depth
;
1771 if (tex
->buffer
.b
.b
.nr_samples
> 1) {
1772 /* MSAA depth buffers need to be converted to single sample buffers.
1774 * Mapping MSAA depth buffers can occur if ReadPixels is called
1775 * with a multisample GLX visual.
1777 * First downsample the depth buffer to a temporary texture,
1778 * then decompress the temporary one to staging.
1780 * Only the region being mapped is transfered.
1782 struct pipe_resource resource
;
1784 si_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1786 if (!si_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1787 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1791 if (usage
& PIPE_TRANSFER_READ
) {
1792 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1794 PRINT_ERR("failed to create a temporary depth texture\n");
1798 si_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1799 si_blit_decompress_depth(ctx
, (struct si_texture
*)temp
, staging_depth
,
1800 0, 0, 0, box
->depth
, 0, 0);
1801 pipe_resource_reference(&temp
, NULL
);
1804 /* Just get the strides. */
1805 si_texture_get_offset(sctx
->screen
, staging_depth
, level
, NULL
,
1807 &trans
->b
.b
.layer_stride
);
1809 /* XXX: only readback the rectangle which is being mapped? */
1810 /* XXX: when discard is true, no need to read back from depth texture */
1811 if (!si_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1812 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1816 si_blit_decompress_depth(ctx
, tex
, staging_depth
,
1818 box
->z
, box
->z
+ box
->depth
- 1,
1821 offset
= si_texture_get_offset(sctx
->screen
, staging_depth
,
1824 &trans
->b
.b
.layer_stride
);
1827 trans
->staging
= &staging_depth
->buffer
;
1828 buf
= trans
->staging
;
1829 } else if (use_staging_texture
) {
1830 struct pipe_resource resource
;
1831 struct si_texture
*staging
;
1833 si_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1834 SI_RESOURCE_FLAG_TRANSFER
);
1835 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1836 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1838 /* Create the temporary texture. */
1839 staging
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1841 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1844 trans
->staging
= &staging
->buffer
;
1846 /* Just get the strides. */
1847 si_texture_get_offset(sctx
->screen
, staging
, 0, NULL
,
1849 &trans
->b
.b
.layer_stride
);
1851 if (usage
& PIPE_TRANSFER_READ
)
1852 si_copy_to_staging_texture(ctx
, trans
);
1854 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1856 buf
= trans
->staging
;
1858 /* the resource is mapped directly */
1859 offset
= si_texture_get_offset(sctx
->screen
, tex
, level
, box
,
1861 &trans
->b
.b
.layer_stride
);
1865 if (!(map
= si_buffer_map_sync_with_rings(sctx
, buf
, usage
)))
1868 *ptransfer
= &trans
->b
.b
;
1869 return map
+ offset
;
1872 r600_resource_reference(&trans
->staging
, NULL
);
1873 pipe_resource_reference(&trans
->b
.b
.resource
, NULL
);
1878 static void si_texture_transfer_unmap(struct pipe_context
*ctx
,
1879 struct pipe_transfer
* transfer
)
1881 struct si_context
*sctx
= (struct si_context
*)ctx
;
1882 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1883 struct pipe_resource
*texture
= transfer
->resource
;
1884 struct si_texture
*tex
= (struct si_texture
*)texture
;
1886 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1887 if (tex
->is_depth
&& tex
->buffer
.b
.b
.nr_samples
<= 1) {
1888 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1889 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1890 &rtransfer
->staging
->b
.b
, transfer
->level
,
1893 si_copy_from_staging_texture(ctx
, rtransfer
);
1897 if (rtransfer
->staging
) {
1898 sctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1899 r600_resource_reference(&rtransfer
->staging
, NULL
);
1902 /* Heuristic for {upload, draw, upload, draw, ..}:
1904 * Flush the gfx IB if we've allocated too much texture storage.
1906 * The idea is that we don't want to build IBs that use too much
1907 * memory and put pressure on the kernel memory manager and we also
1908 * want to make temporary and invalidated buffers go idle ASAP to
1909 * decrease the total memory usage or make them reusable. The memory
1910 * usage will be slightly higher than given here because of the buffer
1911 * cache in the winsys.
1913 * The result is that the kernel memory manager is never a bottleneck.
1915 if (sctx
->num_alloc_tex_transfer_bytes
> sctx
->screen
->info
.gart_size
/ 4) {
1916 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1917 sctx
->num_alloc_tex_transfer_bytes
= 0;
1920 pipe_resource_reference(&transfer
->resource
, NULL
);
1924 static const struct u_resource_vtbl si_texture_vtbl
=
1926 NULL
, /* get_handle */
1927 si_texture_destroy
, /* resource_destroy */
1928 si_texture_transfer_map
, /* transfer_map */
1929 u_default_transfer_flush_region
, /* transfer_flush_region */
1930 si_texture_transfer_unmap
, /* transfer_unmap */
1933 /* Return if it's allowed to reinterpret one format as another with DCC enabled.
1935 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1936 enum pipe_format format2
)
1938 const struct util_format_description
*desc1
, *desc2
;
1940 /* No format change - exit early. */
1941 if (format1
== format2
)
1944 format1
= si_simplify_cb_format(format1
);
1945 format2
= si_simplify_cb_format(format2
);
1947 /* Check again after format adjustments. */
1948 if (format1
== format2
)
1951 desc1
= util_format_description(format1
);
1952 desc2
= util_format_description(format2
);
1954 if (desc1
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
1955 desc2
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1958 /* Float and non-float are totally incompatible. */
1959 if ((desc1
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
) !=
1960 (desc2
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
))
1963 /* Channel sizes must match across DCC formats.
1964 * Comparing just the first 2 channels should be enough.
1966 if (desc1
->channel
[0].size
!= desc2
->channel
[0].size
||
1967 (desc1
->nr_channels
>= 2 &&
1968 desc1
->channel
[1].size
!= desc2
->channel
[1].size
))
1971 /* Everything below is not needed if the driver never uses the DCC
1972 * clear code with the value of 1.
1975 /* If the clear values are all 1 or all 0, this constraint can be
1977 if (vi_alpha_is_on_msb(format1
) != vi_alpha_is_on_msb(format2
))
1980 /* Channel types must match if the clear value of 1 is used.
1981 * The type categories are only float, signed, unsigned.
1982 * NORM and INT are always compatible.
1984 if (desc1
->channel
[0].type
!= desc2
->channel
[0].type
||
1985 (desc1
->nr_channels
>= 2 &&
1986 desc1
->channel
[1].type
!= desc2
->channel
[1].type
))
1992 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1994 enum pipe_format view_format
)
1996 struct si_texture
*stex
= (struct si_texture
*)tex
;
1998 return vi_dcc_enabled(stex
, level
) &&
1999 !vi_dcc_formats_compatible(tex
->format
, view_format
);
2002 /* This can't be merged with the above function, because
2003 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
2004 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
2005 struct pipe_resource
*tex
,
2007 enum pipe_format view_format
)
2009 struct si_texture
*stex
= (struct si_texture
*)tex
;
2011 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
2012 if (!si_texture_disable_dcc(sctx
, stex
))
2013 si_decompress_dcc(sctx
, stex
);
2016 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
2017 struct pipe_resource
*texture
,
2018 const struct pipe_surface
*templ
,
2019 unsigned width0
, unsigned height0
,
2020 unsigned width
, unsigned height
)
2022 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
2027 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2028 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2030 pipe_reference_init(&surface
->base
.reference
, 1);
2031 pipe_resource_reference(&surface
->base
.texture
, texture
);
2032 surface
->base
.context
= pipe
;
2033 surface
->base
.format
= templ
->format
;
2034 surface
->base
.width
= width
;
2035 surface
->base
.height
= height
;
2036 surface
->base
.u
= templ
->u
;
2038 surface
->width0
= width0
;
2039 surface
->height0
= height0
;
2041 surface
->dcc_incompatible
=
2042 texture
->target
!= PIPE_BUFFER
&&
2043 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
2045 return &surface
->base
;
2048 static struct pipe_surface
*si_create_surface(struct pipe_context
*pipe
,
2049 struct pipe_resource
*tex
,
2050 const struct pipe_surface
*templ
)
2052 unsigned level
= templ
->u
.tex
.level
;
2053 unsigned width
= u_minify(tex
->width0
, level
);
2054 unsigned height
= u_minify(tex
->height0
, level
);
2055 unsigned width0
= tex
->width0
;
2056 unsigned height0
= tex
->height0
;
2058 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2059 const struct util_format_description
*tex_desc
2060 = util_format_description(tex
->format
);
2061 const struct util_format_description
*templ_desc
2062 = util_format_description(templ
->format
);
2064 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2066 /* Adjust size of surface if and only if the block width or
2067 * height is changed. */
2068 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2069 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2070 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2071 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2073 width
= nblks_x
* templ_desc
->block
.width
;
2074 height
= nblks_y
* templ_desc
->block
.height
;
2076 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2077 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2081 return si_create_surface_custom(pipe
, tex
, templ
,
2086 static void si_surface_destroy(struct pipe_context
*pipe
,
2087 struct pipe_surface
*surface
)
2089 pipe_resource_reference(&surface
->texture
, NULL
);
2093 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2095 const struct util_format_description
*desc
= util_format_description(format
);
2097 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2099 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2100 return V_028C70_SWAP_STD
;
2102 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2105 switch (desc
->nr_channels
) {
2107 if (HAS_SWIZZLE(0,X
))
2108 return V_028C70_SWAP_STD
; /* X___ */
2109 else if (HAS_SWIZZLE(3,X
))
2110 return V_028C70_SWAP_ALT_REV
; /* ___X */
2113 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2114 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2115 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2116 return V_028C70_SWAP_STD
; /* XY__ */
2117 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2118 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2119 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2121 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2122 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2123 return V_028C70_SWAP_ALT
; /* X__Y */
2124 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2125 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2128 if (HAS_SWIZZLE(0,X
))
2129 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2130 else if (HAS_SWIZZLE(0,Z
))
2131 return V_028C70_SWAP_STD_REV
; /* ZYX */
2134 /* check the middle channels, the 1st and 4th channel can be NONE */
2135 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2136 return V_028C70_SWAP_STD
; /* XYZW */
2137 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2138 return V_028C70_SWAP_STD_REV
; /* WZYX */
2139 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2140 return V_028C70_SWAP_ALT
; /* ZYXW */
2141 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2144 return V_028C70_SWAP_ALT_REV
;
2146 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2153 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2155 static void vi_dcc_clean_up_context_slot(struct si_context
*sctx
,
2160 if (sctx
->dcc_stats
[slot
].query_active
)
2161 vi_separate_dcc_stop_query(sctx
,
2162 sctx
->dcc_stats
[slot
].tex
);
2164 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
[slot
].ps_stats
); i
++)
2165 if (sctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2166 sctx
->b
.destroy_query(&sctx
->b
,
2167 sctx
->dcc_stats
[slot
].ps_stats
[i
]);
2168 sctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2171 si_texture_reference(&sctx
->dcc_stats
[slot
].tex
, NULL
);
2175 * Return the per-context slot where DCC statistics queries for the texture live.
2177 static unsigned vi_get_context_dcc_stats_index(struct si_context
*sctx
,
2178 struct si_texture
*tex
)
2180 int i
, empty_slot
= -1;
2182 /* Remove zombie textures (textures kept alive by this array only). */
2183 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2184 if (sctx
->dcc_stats
[i
].tex
&&
2185 sctx
->dcc_stats
[i
].tex
->buffer
.b
.b
.reference
.count
== 1)
2186 vi_dcc_clean_up_context_slot(sctx
, i
);
2188 /* Find the texture. */
2189 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
2190 /* Return if found. */
2191 if (sctx
->dcc_stats
[i
].tex
== tex
) {
2192 sctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2196 /* Record the first seen empty slot. */
2197 if (empty_slot
== -1 && !sctx
->dcc_stats
[i
].tex
)
2201 /* Not found. Remove the oldest member to make space in the array. */
2202 if (empty_slot
== -1) {
2203 int oldest_slot
= 0;
2205 /* Find the oldest slot. */
2206 for (i
= 1; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2207 if (sctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2208 sctx
->dcc_stats
[i
].last_use_timestamp
)
2211 /* Clean up the oldest slot. */
2212 vi_dcc_clean_up_context_slot(sctx
, oldest_slot
);
2213 empty_slot
= oldest_slot
;
2216 /* Add the texture to the new slot. */
2217 si_texture_reference(&sctx
->dcc_stats
[empty_slot
].tex
, tex
);
2218 sctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2222 static struct pipe_query
*
2223 vi_create_resuming_pipestats_query(struct si_context
*sctx
)
2225 struct si_query_hw
*query
= (struct si_query_hw
*)
2226 sctx
->b
.create_query(&sctx
->b
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2228 query
->flags
|= SI_QUERY_HW_FLAG_BEGIN_RESUMES
;
2229 return (struct pipe_query
*)query
;
2233 * Called when binding a color buffer.
2235 void vi_separate_dcc_start_query(struct si_context
*sctx
,
2236 struct si_texture
*tex
)
2238 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2240 assert(!sctx
->dcc_stats
[i
].query_active
);
2242 if (!sctx
->dcc_stats
[i
].ps_stats
[0])
2243 sctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(sctx
);
2245 /* begin or resume the query */
2246 sctx
->b
.begin_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2247 sctx
->dcc_stats
[i
].query_active
= true;
2251 * Called when unbinding a color buffer.
2253 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
2254 struct si_texture
*tex
)
2256 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2258 assert(sctx
->dcc_stats
[i
].query_active
);
2259 assert(sctx
->dcc_stats
[i
].ps_stats
[0]);
2261 /* pause or end the query */
2262 sctx
->b
.end_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2263 sctx
->dcc_stats
[i
].query_active
= false;
2266 static bool vi_should_enable_separate_dcc(struct si_texture
*tex
)
2268 /* The minimum number of fullscreen draws per frame that is required
2270 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2273 /* Called by fast clear. */
2274 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
2275 struct si_texture
*tex
)
2277 /* The intent is to use this with shared displayable back buffers,
2278 * but it's not strictly limited only to them.
2280 if (!tex
->buffer
.b
.is_shared
||
2281 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2282 tex
->buffer
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2283 tex
->buffer
.b
.b
.last_level
> 0 ||
2284 !tex
->surface
.dcc_size
)
2287 if (tex
->dcc_offset
)
2288 return; /* already enabled */
2290 /* Enable the DCC stat gathering. */
2291 if (!tex
->dcc_gather_statistics
) {
2292 tex
->dcc_gather_statistics
= true;
2293 vi_separate_dcc_start_query(sctx
, tex
);
2296 if (!vi_should_enable_separate_dcc(tex
))
2297 return; /* stats show that DCC decompression is too expensive */
2299 assert(tex
->surface
.num_dcc_levels
);
2300 assert(!tex
->dcc_separate_buffer
);
2302 si_texture_discard_cmask(sctx
->screen
, tex
);
2304 /* Get a DCC buffer. */
2305 if (tex
->last_dcc_separate_buffer
) {
2306 assert(tex
->dcc_gather_statistics
);
2307 assert(!tex
->dcc_separate_buffer
);
2308 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2309 tex
->last_dcc_separate_buffer
= NULL
;
2311 tex
->dcc_separate_buffer
=
2312 si_aligned_buffer_create(sctx
->b
.screen
,
2313 SI_RESOURCE_FLAG_UNMAPPABLE
,
2315 tex
->surface
.dcc_size
,
2316 tex
->surface
.dcc_alignment
);
2317 if (!tex
->dcc_separate_buffer
)
2321 /* dcc_offset is the absolute GPUVM address. */
2322 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2324 /* no need to flag anything since this is called by fast clear that
2325 * flags framebuffer state
2330 * Called by pipe_context::flush_resource, the place where DCC decompression
2333 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2334 struct si_texture
*tex
)
2336 struct si_context
*sctx
= (struct si_context
*)ctx
;
2337 struct pipe_query
*tmp
;
2338 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2339 bool query_active
= sctx
->dcc_stats
[i
].query_active
;
2340 bool disable
= false;
2342 if (sctx
->dcc_stats
[i
].ps_stats
[2]) {
2343 union pipe_query_result result
;
2345 /* Read the results. */
2346 ctx
->get_query_result(ctx
, sctx
->dcc_stats
[i
].ps_stats
[2],
2348 si_query_hw_reset_buffers(sctx
,
2349 (struct si_query_hw
*)
2350 sctx
->dcc_stats
[i
].ps_stats
[2]);
2352 /* Compute the approximate number of fullscreen draws. */
2353 tex
->ps_draw_ratio
=
2354 result
.pipeline_statistics
.ps_invocations
/
2355 (tex
->buffer
.b
.b
.width0
* tex
->buffer
.b
.b
.height0
);
2356 sctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2358 disable
= tex
->dcc_separate_buffer
&&
2359 !vi_should_enable_separate_dcc(tex
);
2362 tex
->num_slow_clears
= 0;
2364 /* stop the statistics query for ps_stats[0] */
2366 vi_separate_dcc_stop_query(sctx
, tex
);
2368 /* Move the queries in the queue by one. */
2369 tmp
= sctx
->dcc_stats
[i
].ps_stats
[2];
2370 sctx
->dcc_stats
[i
].ps_stats
[2] = sctx
->dcc_stats
[i
].ps_stats
[1];
2371 sctx
->dcc_stats
[i
].ps_stats
[1] = sctx
->dcc_stats
[i
].ps_stats
[0];
2372 sctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2374 /* create and start a new query as ps_stats[0] */
2376 vi_separate_dcc_start_query(sctx
, tex
);
2379 assert(!tex
->last_dcc_separate_buffer
);
2380 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2381 tex
->dcc_separate_buffer
= NULL
;
2382 tex
->dcc_offset
= 0;
2383 /* no need to flag anything since this is called after
2384 * decompression that re-sets framebuffer state
2389 static struct pipe_memory_object
*
2390 si_memobj_from_handle(struct pipe_screen
*screen
,
2391 struct winsys_handle
*whandle
,
2394 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2395 struct r600_memory_object
*memobj
= CALLOC_STRUCT(r600_memory_object
);
2396 struct pb_buffer
*buf
= NULL
;
2397 uint32_t stride
, offset
;
2402 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
2409 memobj
->b
.dedicated
= dedicated
;
2411 memobj
->stride
= stride
;
2412 memobj
->offset
= offset
;
2414 return (struct pipe_memory_object
*)memobj
;
2419 si_memobj_destroy(struct pipe_screen
*screen
,
2420 struct pipe_memory_object
*_memobj
)
2422 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2424 pb_reference(&memobj
->buf
, NULL
);
2428 static struct pipe_resource
*
2429 si_texture_from_memobj(struct pipe_screen
*screen
,
2430 const struct pipe_resource
*templ
,
2431 struct pipe_memory_object
*_memobj
,
2434 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2435 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2436 struct pipe_resource
*tex
=
2437 si_texture_from_winsys_buffer(sscreen
, templ
, memobj
->buf
,
2438 memobj
->stride
, offset
,
2439 PIPE_HANDLE_USAGE_READ_WRITE
,
2440 memobj
->b
.dedicated
);
2444 /* si_texture_from_winsys_buffer doesn't increment refcount of
2445 * memobj->buf, so increment it here.
2447 struct pb_buffer
*buf
= NULL
;
2448 pb_reference(&buf
, memobj
->buf
);
2452 static bool si_check_resource_capability(struct pipe_screen
*screen
,
2453 struct pipe_resource
*resource
,
2456 struct si_texture
*tex
= (struct si_texture
*)resource
;
2458 /* Buffers only support the linear flag. */
2459 if (resource
->target
== PIPE_BUFFER
)
2460 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2462 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2465 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2468 /* TODO: PIPE_BIND_CURSOR - do we care? */
2472 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2474 sscreen
->b
.resource_from_handle
= si_texture_from_handle
;
2475 sscreen
->b
.resource_get_handle
= si_texture_get_handle
;
2476 sscreen
->b
.resource_from_memobj
= si_texture_from_memobj
;
2477 sscreen
->b
.memobj_create_from_handle
= si_memobj_from_handle
;
2478 sscreen
->b
.memobj_destroy
= si_memobj_destroy
;
2479 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2482 void si_init_context_texture_functions(struct si_context
*sctx
)
2484 sctx
->b
.create_surface
= si_create_surface
;
2485 sctx
->b
.surface_destroy
= si_surface_destroy
;