2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "util/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/u_resource.h"
33 #include "util/u_surface.h"
34 #include "util/u_transfer.h"
35 #include "util/os_time.h"
38 #include "state_tracker/drm_driver.h"
40 #include "amd/addrlib/inc/addrinterface.h"
42 static enum radeon_surf_mode
43 si_choose_tiling(struct si_screen
*sscreen
,
44 const struct pipe_resource
*templ
, bool tc_compatible_htile
);
47 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
48 struct si_texture
*dst
,
49 unsigned dst_level
, unsigned dstx
,
50 unsigned dsty
, unsigned dstz
,
51 struct si_texture
*src
,
53 const struct pipe_box
*src_box
)
58 if (dst
->surface
.bpe
!= src
->surface
.bpe
)
61 /* MSAA: Blits don't exist in the real world. */
62 if (src
->buffer
.b
.b
.nr_samples
> 1 ||
63 dst
->buffer
.b
.b
.nr_samples
> 1)
66 /* Depth-stencil surfaces:
67 * When dst is linear, the DB->CB copy preserves HTILE.
68 * When dst is tiled, the 3D path must be used to update HTILE.
70 if (src
->is_depth
|| dst
->is_depth
)
74 * src: Use the 3D path. DCC decompression is expensive.
75 * dst: Use the 3D path to compress the pixels with DCC.
77 if (vi_dcc_enabled(src
, src_level
) ||
78 vi_dcc_enabled(dst
, dst_level
))
82 * src: Both texture and SDMA paths need decompression. Use SDMA.
83 * dst: If overwriting the whole texture, discard CMASK and use
84 * SDMA. Otherwise, use the 3D path.
86 if (dst
->cmask_buffer
&& dst
->dirty_level_mask
& (1 << dst_level
)) {
87 /* The CMASK clear is only enabled for the first level. */
88 assert(dst_level
== 0);
89 if (!util_texrange_covers_whole_level(&dst
->buffer
.b
.b
, dst_level
,
90 dstx
, dsty
, dstz
, src_box
->width
,
91 src_box
->height
, src_box
->depth
))
94 si_texture_discard_cmask(sctx
->screen
, dst
);
97 /* All requirements are met. Prepare textures for SDMA. */
98 if (src
->cmask_buffer
&& src
->dirty_level_mask
& (1 << src_level
))
99 sctx
->b
.flush_resource(&sctx
->b
, &src
->buffer
.b
.b
);
101 assert(!(src
->dirty_level_mask
& (1 << src_level
)));
102 assert(!(dst
->dirty_level_mask
& (1 << dst_level
)));
107 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
108 static void si_copy_region_with_blit(struct pipe_context
*pipe
,
109 struct pipe_resource
*dst
,
111 unsigned dstx
, unsigned dsty
, unsigned dstz
,
112 struct pipe_resource
*src
,
114 const struct pipe_box
*src_box
)
116 struct pipe_blit_info blit
;
118 memset(&blit
, 0, sizeof(blit
));
119 blit
.src
.resource
= src
;
120 blit
.src
.format
= src
->format
;
121 blit
.src
.level
= src_level
;
122 blit
.src
.box
= *src_box
;
123 blit
.dst
.resource
= dst
;
124 blit
.dst
.format
= dst
->format
;
125 blit
.dst
.level
= dst_level
;
126 blit
.dst
.box
.x
= dstx
;
127 blit
.dst
.box
.y
= dsty
;
128 blit
.dst
.box
.z
= dstz
;
129 blit
.dst
.box
.width
= src_box
->width
;
130 blit
.dst
.box
.height
= src_box
->height
;
131 blit
.dst
.box
.depth
= src_box
->depth
;
132 blit
.mask
= util_format_get_mask(dst
->format
);
133 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
136 pipe
->blit(pipe
, &blit
);
140 /* Copy from a full GPU texture to a transfer's staging one. */
141 static void si_copy_to_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
143 struct si_context
*sctx
= (struct si_context
*)ctx
;
144 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
145 struct pipe_resource
*dst
= &stransfer
->staging
->b
.b
;
146 struct pipe_resource
*src
= transfer
->resource
;
148 if (src
->nr_samples
> 1 || ((struct si_texture
*)src
)->is_depth
) {
149 si_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
150 src
, transfer
->level
, &transfer
->box
);
154 sctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
158 /* Copy from a transfer's staging texture to a full GPU one. */
159 static void si_copy_from_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
161 struct si_context
*sctx
= (struct si_context
*)ctx
;
162 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
163 struct pipe_resource
*dst
= transfer
->resource
;
164 struct pipe_resource
*src
= &stransfer
->staging
->b
.b
;
165 struct pipe_box sbox
;
167 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
169 if (dst
->nr_samples
> 1 || ((struct si_texture
*)dst
)->is_depth
) {
170 si_copy_region_with_blit(ctx
, dst
, transfer
->level
,
171 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
176 if (util_format_is_compressed(dst
->format
)) {
177 sbox
.width
= util_format_get_nblocksx(dst
->format
, sbox
.width
);
178 sbox
.height
= util_format_get_nblocksx(dst
->format
, sbox
.height
);
181 sctx
->dma_copy(ctx
, dst
, transfer
->level
,
182 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
186 static unsigned si_texture_get_offset(struct si_screen
*sscreen
,
187 struct si_texture
*tex
, unsigned level
,
188 const struct pipe_box
*box
,
190 unsigned *layer_stride
)
192 if (sscreen
->info
.chip_class
>= GFX9
) {
193 *stride
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
194 *layer_stride
= tex
->surface
.u
.gfx9
.surf_slice_size
;
199 /* Each texture is an array of slices. Each slice is an array
200 * of mipmap levels. */
201 return box
->z
* tex
->surface
.u
.gfx9
.surf_slice_size
+
202 tex
->surface
.u
.gfx9
.offset
[level
] +
203 (box
->y
/ tex
->surface
.blk_h
*
204 tex
->surface
.u
.gfx9
.surf_pitch
+
205 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
207 *stride
= tex
->surface
.u
.legacy
.level
[level
].nblk_x
*
209 assert((uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
210 *layer_stride
= (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
213 return tex
->surface
.u
.legacy
.level
[level
].offset
;
215 /* Each texture is an array of mipmap levels. Each level is
216 * an array of slices. */
217 return tex
->surface
.u
.legacy
.level
[level
].offset
+
218 box
->z
* (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
219 (box
->y
/ tex
->surface
.blk_h
*
220 tex
->surface
.u
.legacy
.level
[level
].nblk_x
+
221 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
225 static int si_init_surface(struct si_screen
*sscreen
,
226 struct radeon_surf
*surface
,
227 const struct pipe_resource
*ptex
,
228 enum radeon_surf_mode array_mode
,
229 unsigned pitch_in_bytes_override
,
233 bool is_flushed_depth
,
234 bool tc_compatible_htile
)
236 const struct util_format_description
*desc
=
237 util_format_description(ptex
->format
);
238 bool is_depth
, is_stencil
;
240 unsigned i
, bpe
, flags
= 0;
242 is_depth
= util_format_has_depth(desc
);
243 is_stencil
= util_format_has_stencil(desc
);
245 if (!is_flushed_depth
&&
246 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
247 bpe
= 4; /* stencil is allocated separately */
249 bpe
= util_format_get_blocksize(ptex
->format
);
250 assert(util_is_power_of_two_or_zero(bpe
));
253 if (!is_flushed_depth
&& is_depth
) {
254 flags
|= RADEON_SURF_ZBUFFER
;
256 if (tc_compatible_htile
&&
257 (sscreen
->info
.chip_class
>= GFX9
||
258 array_mode
== RADEON_SURF_MODE_2D
)) {
259 /* TC-compatible HTILE only supports Z32_FLOAT.
260 * GFX9 also supports Z16_UNORM.
261 * On GFX8, promote Z16 to Z32. DB->CB copies will convert
262 * the format for transfers.
264 if (sscreen
->info
.chip_class
== GFX8
)
267 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
271 flags
|= RADEON_SURF_SBUFFER
;
274 if (sscreen
->info
.chip_class
>= GFX8
&&
275 (ptex
->flags
& SI_RESOURCE_FLAG_DISABLE_DCC
||
276 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
277 (ptex
->nr_samples
>= 2 && !sscreen
->dcc_msaa_allowed
)))
278 flags
|= RADEON_SURF_DISABLE_DCC
;
280 /* Stoney: 128bpp MSAA textures randomly fail piglit tests with DCC. */
281 if (sscreen
->info
.family
== CHIP_STONEY
&&
282 bpe
== 16 && ptex
->nr_samples
>= 2)
283 flags
|= RADEON_SURF_DISABLE_DCC
;
285 /* GFX8: DCC clear for 4x and 8x MSAA array textures unimplemented. */
286 if (sscreen
->info
.chip_class
== GFX8
&&
287 ptex
->nr_storage_samples
>= 4 &&
288 ptex
->array_size
> 1)
289 flags
|= RADEON_SURF_DISABLE_DCC
;
291 /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
292 if (sscreen
->info
.chip_class
== GFX9
&&
293 ptex
->nr_storage_samples
>= 4)
294 flags
|= RADEON_SURF_DISABLE_DCC
;
296 /* TODO: GFX10: DCC causes corruption with MSAA. */
297 if (sscreen
->info
.chip_class
>= GFX10
&&
298 ptex
->nr_storage_samples
>= 2)
299 flags
|= RADEON_SURF_DISABLE_DCC
;
301 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
302 /* This should catch bugs in gallium users setting incorrect flags. */
303 assert(ptex
->nr_samples
<= 1 &&
304 ptex
->array_size
== 1 &&
306 ptex
->last_level
== 0 &&
307 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
309 flags
|= RADEON_SURF_SCANOUT
;
312 if (ptex
->bind
& PIPE_BIND_SHARED
)
313 flags
|= RADEON_SURF_SHAREABLE
;
315 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
316 if (!(ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
))
317 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
319 if (sscreen
->info
.chip_class
>= GFX10
&&
320 (ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
)) {
321 flags
|= RADEON_SURF_FORCE_SWIZZLE_MODE
;
322 surface
->u
.gfx9
.surf
.swizzle_mode
= ADDR_SW_64KB_R_X
;
325 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, flags
, bpe
,
326 array_mode
, surface
);
331 unsigned pitch
= pitch_in_bytes_override
/ bpe
;
333 if (sscreen
->info
.chip_class
>= GFX9
) {
335 surface
->u
.gfx9
.surf_pitch
= pitch
;
336 surface
->u
.gfx9
.surf_slice_size
=
337 (uint64_t)pitch
* surface
->u
.gfx9
.surf_height
* bpe
;
339 surface
->u
.gfx9
.surf_offset
= offset
;
342 surface
->u
.legacy
.level
[0].nblk_x
= pitch
;
343 surface
->u
.legacy
.level
[0].slice_size_dw
=
344 ((uint64_t)pitch
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
347 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
348 surface
->u
.legacy
.level
[i
].offset
+= offset
;
354 static void si_get_display_metadata(struct si_screen
*sscreen
,
355 struct radeon_surf
*surf
,
356 struct radeon_bo_metadata
*metadata
,
357 enum radeon_surf_mode
*array_mode
,
360 if (sscreen
->info
.chip_class
>= GFX9
) {
361 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
362 *array_mode
= RADEON_SURF_MODE_2D
;
364 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
366 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
367 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
369 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
371 if (metadata
->u
.gfx9
.dcc_offset_256B
) {
372 surf
->u
.gfx9
.display_dcc_pitch_max
= metadata
->u
.gfx9
.dcc_pitch_max
;
373 assert(metadata
->u
.gfx9
.dcc_independent_64B
== 1);
376 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
377 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
378 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
379 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
380 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
381 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
383 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
384 *array_mode
= RADEON_SURF_MODE_2D
;
385 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
386 *array_mode
= RADEON_SURF_MODE_1D
;
388 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
390 *is_scanout
= metadata
->u
.legacy
.scanout
;
394 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
395 struct si_texture
*tex
)
397 struct si_screen
*sscreen
= sctx
->screen
;
398 struct pipe_context
*ctx
= &sctx
->b
;
400 if (ctx
== sscreen
->aux_context
)
401 mtx_lock(&sscreen
->aux_context_lock
);
403 unsigned n
= sctx
->num_decompress_calls
;
404 ctx
->flush_resource(ctx
, &tex
->buffer
.b
.b
);
406 /* Flush only if any fast clear elimination took place. */
407 if (n
!= sctx
->num_decompress_calls
)
408 ctx
->flush(ctx
, NULL
, 0);
410 if (ctx
== sscreen
->aux_context
)
411 mtx_unlock(&sscreen
->aux_context_lock
);
414 void si_texture_discard_cmask(struct si_screen
*sscreen
,
415 struct si_texture
*tex
)
417 if (!tex
->cmask_buffer
)
420 assert(tex
->buffer
.b
.b
.nr_samples
<= 1);
423 tex
->cmask_base_address_reg
= tex
->buffer
.gpu_address
>> 8;
424 tex
->dirty_level_mask
= 0;
426 tex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
428 if (tex
->cmask_buffer
!= &tex
->buffer
)
429 si_resource_reference(&tex
->cmask_buffer
, NULL
);
431 tex
->cmask_buffer
= NULL
;
433 /* Notify all contexts about the change. */
434 p_atomic_inc(&sscreen
->dirty_tex_counter
);
435 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
438 static bool si_can_disable_dcc(struct si_texture
*tex
)
440 /* We can't disable DCC if it can be written by another process. */
441 return tex
->dcc_offset
&&
442 (!tex
->buffer
.b
.is_shared
||
443 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
));
446 static bool si_texture_discard_dcc(struct si_screen
*sscreen
,
447 struct si_texture
*tex
)
449 if (!si_can_disable_dcc(tex
)) {
450 assert(tex
->display_dcc_offset
== 0);
454 assert(tex
->dcc_separate_buffer
== NULL
);
458 tex
->display_dcc_offset
= 0;
459 tex
->dcc_retile_map_offset
= 0;
461 /* Notify all contexts about the change. */
462 p_atomic_inc(&sscreen
->dirty_tex_counter
);
467 * Disable DCC for the texture. (first decompress, then discard metadata).
469 * There is unresolved multi-context synchronization issue between
470 * screen::aux_context and the current context. If applications do this with
471 * multiple contexts, it's already undefined behavior for them and we don't
472 * have to worry about that. The scenario is:
474 * If context 1 disables DCC and context 2 has queued commands that write
475 * to the texture via CB with DCC enabled, and the order of operations is
477 * context 2 queues draw calls rendering to the texture, but doesn't flush
478 * context 1 disables DCC and flushes
479 * context 1 & 2 reset descriptors and FB state
480 * context 2 flushes (new compressed tiles written by the draw calls)
481 * context 1 & 2 read garbage, because DCC is disabled, yet there are
484 * \param sctx the current context if you have one, or sscreen->aux_context
487 bool si_texture_disable_dcc(struct si_context
*sctx
,
488 struct si_texture
*tex
)
490 struct si_screen
*sscreen
= sctx
->screen
;
492 if (!sctx
->has_graphics
)
493 return si_texture_discard_dcc(sscreen
, tex
);
495 if (!si_can_disable_dcc(tex
))
498 if (&sctx
->b
== sscreen
->aux_context
)
499 mtx_lock(&sscreen
->aux_context_lock
);
501 /* Decompress DCC. */
502 si_decompress_dcc(sctx
, tex
);
503 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
505 if (&sctx
->b
== sscreen
->aux_context
)
506 mtx_unlock(&sscreen
->aux_context_lock
);
508 return si_texture_discard_dcc(sscreen
, tex
);
511 static void si_reallocate_texture_inplace(struct si_context
*sctx
,
512 struct si_texture
*tex
,
513 unsigned new_bind_flag
,
514 bool invalidate_storage
)
516 struct pipe_screen
*screen
= sctx
->b
.screen
;
517 struct si_texture
*new_tex
;
518 struct pipe_resource templ
= tex
->buffer
.b
.b
;
521 templ
.bind
|= new_bind_flag
;
523 if (tex
->buffer
.b
.is_shared
)
526 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
527 if (tex
->surface
.is_linear
)
530 /* This fails with MSAA, depth, and compressed textures. */
531 if (si_choose_tiling(sctx
->screen
, &templ
, false) !=
532 RADEON_SURF_MODE_LINEAR_ALIGNED
)
536 new_tex
= (struct si_texture
*)screen
->resource_create(screen
, &templ
);
540 /* Copy the pixels to the new texture. */
541 if (!invalidate_storage
) {
542 for (i
= 0; i
<= templ
.last_level
; i
++) {
546 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
547 util_num_layers(&templ
, i
), &box
);
549 sctx
->dma_copy(&sctx
->b
, &new_tex
->buffer
.b
.b
, i
, 0, 0, 0,
550 &tex
->buffer
.b
.b
, i
, &box
);
554 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
555 si_texture_discard_cmask(sctx
->screen
, tex
);
556 si_texture_discard_dcc(sctx
->screen
, tex
);
559 /* Replace the structure fields of tex. */
560 tex
->buffer
.b
.b
.bind
= templ
.bind
;
561 pb_reference(&tex
->buffer
.buf
, new_tex
->buffer
.buf
);
562 tex
->buffer
.gpu_address
= new_tex
->buffer
.gpu_address
;
563 tex
->buffer
.vram_usage
= new_tex
->buffer
.vram_usage
;
564 tex
->buffer
.gart_usage
= new_tex
->buffer
.gart_usage
;
565 tex
->buffer
.bo_size
= new_tex
->buffer
.bo_size
;
566 tex
->buffer
.bo_alignment
= new_tex
->buffer
.bo_alignment
;
567 tex
->buffer
.domains
= new_tex
->buffer
.domains
;
568 tex
->buffer
.flags
= new_tex
->buffer
.flags
;
570 tex
->surface
= new_tex
->surface
;
571 tex
->size
= new_tex
->size
;
572 si_texture_reference(&tex
->flushed_depth_texture
,
573 new_tex
->flushed_depth_texture
);
575 tex
->fmask_offset
= new_tex
->fmask_offset
;
576 tex
->cmask_offset
= new_tex
->cmask_offset
;
577 tex
->cmask_base_address_reg
= new_tex
->cmask_base_address_reg
;
579 if (tex
->cmask_buffer
== &tex
->buffer
)
580 tex
->cmask_buffer
= NULL
;
582 si_resource_reference(&tex
->cmask_buffer
, NULL
);
584 if (new_tex
->cmask_buffer
== &new_tex
->buffer
)
585 tex
->cmask_buffer
= &tex
->buffer
;
587 si_resource_reference(&tex
->cmask_buffer
, new_tex
->cmask_buffer
);
589 tex
->dcc_offset
= new_tex
->dcc_offset
;
590 tex
->cb_color_info
= new_tex
->cb_color_info
;
591 memcpy(tex
->color_clear_value
, new_tex
->color_clear_value
,
592 sizeof(tex
->color_clear_value
));
593 tex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
595 tex
->htile_offset
= new_tex
->htile_offset
;
596 tex
->depth_clear_value
= new_tex
->depth_clear_value
;
597 tex
->dirty_level_mask
= new_tex
->dirty_level_mask
;
598 tex
->stencil_dirty_level_mask
= new_tex
->stencil_dirty_level_mask
;
599 tex
->db_render_format
= new_tex
->db_render_format
;
600 tex
->stencil_clear_value
= new_tex
->stencil_clear_value
;
601 tex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
602 tex
->depth_cleared
= new_tex
->depth_cleared
;
603 tex
->stencil_cleared
= new_tex
->stencil_cleared
;
604 tex
->upgraded_depth
= new_tex
->upgraded_depth
;
605 tex
->db_compatible
= new_tex
->db_compatible
;
606 tex
->can_sample_z
= new_tex
->can_sample_z
;
607 tex
->can_sample_s
= new_tex
->can_sample_s
;
609 tex
->separate_dcc_dirty
= new_tex
->separate_dcc_dirty
;
610 tex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
611 si_resource_reference(&tex
->dcc_separate_buffer
,
612 new_tex
->dcc_separate_buffer
);
613 si_resource_reference(&tex
->last_dcc_separate_buffer
,
614 new_tex
->last_dcc_separate_buffer
);
616 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
617 assert(!tex
->htile_offset
);
618 assert(!tex
->cmask_buffer
);
619 assert(!tex
->surface
.fmask_size
);
620 assert(!tex
->dcc_offset
);
621 assert(!tex
->is_depth
);
624 si_texture_reference(&new_tex
, NULL
);
626 p_atomic_inc(&sctx
->screen
->dirty_tex_counter
);
629 static uint32_t si_get_bo_metadata_word1(struct si_screen
*sscreen
)
631 return (ATI_VENDOR_ID
<< 16) | sscreen
->info
.pci_id
;
634 static void si_set_tex_bo_metadata(struct si_screen
*sscreen
,
635 struct si_texture
*tex
)
637 struct radeon_surf
*surface
= &tex
->surface
;
638 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
639 struct radeon_bo_metadata md
;
641 memset(&md
, 0, sizeof(md
));
643 if (sscreen
->info
.chip_class
>= GFX9
) {
644 md
.u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
646 if (tex
->dcc_offset
&& !tex
->dcc_separate_buffer
) {
647 uint64_t dcc_offset
=
648 tex
->display_dcc_offset
? tex
->display_dcc_offset
651 assert((dcc_offset
>> 8) != 0 && (dcc_offset
>> 8) < (1 << 24));
652 md
.u
.gfx9
.dcc_offset_256B
= dcc_offset
>> 8;
653 md
.u
.gfx9
.dcc_pitch_max
= tex
->surface
.u
.gfx9
.display_dcc_pitch_max
;
654 md
.u
.gfx9
.dcc_independent_64B
= 1;
657 md
.u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
658 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
659 md
.u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
660 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
661 md
.u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
662 md
.u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
663 md
.u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
664 md
.u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
665 md
.u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
666 md
.u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
667 md
.u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
668 md
.u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
671 assert(tex
->dcc_separate_buffer
== NULL
);
672 assert(tex
->surface
.fmask_size
== 0);
674 /* Metadata image format format version 1:
675 * [0] = 1 (metadata format identifier)
676 * [1] = (VENDOR_ID << 16) | PCI_ID
677 * [2:9] = image descriptor for the whole resource
678 * [2] is always 0, because the base address is cleared
679 * [9] is the DCC offset bits [39:8] from the beginning of
681 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
684 md
.metadata
[0] = 1; /* metadata image format version 1 */
686 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
687 md
.metadata
[1] = si_get_bo_metadata_word1(sscreen
);
689 static const unsigned char swizzle
[] = {
695 bool is_array
= util_texture_is_array(res
->target
);
698 sscreen
->make_texture_descriptor(sscreen
, tex
, true,
699 res
->target
, res
->format
,
700 swizzle
, 0, res
->last_level
, 0,
701 is_array
? res
->array_size
- 1 : 0,
702 res
->width0
, res
->height0
, res
->depth0
,
705 si_set_mutable_tex_desc_fields(sscreen
, tex
, &tex
->surface
.u
.legacy
.level
[0],
706 0, 0, tex
->surface
.blk_w
, false, desc
);
708 /* Clear the base address and set the relative DCC offset. */
710 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
711 desc
[7] = tex
->dcc_offset
>> 8;
713 /* Dwords [2:9] contain the image descriptor. */
714 memcpy(&md
.metadata
[2], desc
, sizeof(desc
));
715 md
.size_metadata
= 10 * 4;
717 /* Dwords [10:..] contain the mipmap level offsets. */
718 if (sscreen
->info
.chip_class
<= GFX8
) {
719 for (unsigned i
= 0; i
<= res
->last_level
; i
++)
720 md
.metadata
[10+i
] = tex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
722 md
.size_metadata
+= (1 + res
->last_level
) * 4;
725 sscreen
->ws
->buffer_set_metadata(tex
->buffer
.buf
, &md
);
728 static void si_get_opaque_metadata(struct si_screen
*sscreen
,
729 struct si_texture
*tex
,
730 struct radeon_bo_metadata
*md
)
732 uint32_t *desc
= &md
->metadata
[2];
734 if (sscreen
->info
.chip_class
< GFX8
)
737 /* Return if DCC is enabled. The texture should be set up with it
740 if (md
->size_metadata
>= 10 * 4 && /* at least 2(header) + 8(desc) dwords */
741 md
->metadata
[0] != 0 &&
742 md
->metadata
[1] == si_get_bo_metadata_word1(sscreen
) &&
743 G_008F28_COMPRESSION_EN(desc
[6])) {
744 tex
->dcc_offset
= (uint64_t)desc
[7] << 8;
746 if (sscreen
->info
.chip_class
>= GFX9
) {
747 /* Fix up parameters for displayable DCC. Some state
748 * trackers don't set the SCANOUT flag when importing
749 * displayable images, so we have to recover the correct
752 tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
=
753 G_008F24_META_PIPE_ALIGNED(desc
[5]);
754 tex
->surface
.u
.gfx9
.dcc
.rb_aligned
=
755 G_008F24_META_RB_ALIGNED(desc
[5]);
757 /* If DCC is unaligned, this can only be a displayable image. */
758 if (!tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
&&
759 !tex
->surface
.u
.gfx9
.dcc
.rb_aligned
)
760 tex
->surface
.is_displayable
= true;
765 /* Disable DCC. These are always set by texture_from_handle and must
771 static bool si_has_displayable_dcc(struct si_texture
*tex
)
773 struct si_screen
*sscreen
= (struct si_screen
*)tex
->buffer
.b
.b
.screen
;
775 if (sscreen
->info
.chip_class
<= GFX8
)
778 /* This needs a cache flush before scanout.
779 * (it can't be scanned out and rendered to simultaneously)
781 if (sscreen
->info
.use_display_dcc_unaligned
&&
783 !tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
&&
784 !tex
->surface
.u
.gfx9
.dcc
.rb_aligned
)
787 /* This needs an explicit flush (flush_resource). */
788 if (sscreen
->info
.use_display_dcc_with_retile_blit
&&
789 tex
->display_dcc_offset
)
795 static void si_texture_get_info(struct pipe_screen
* screen
,
796 struct pipe_resource
*resource
,
800 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
801 struct si_texture
*tex
= (struct si_texture
*)resource
;
805 if (!sscreen
|| !tex
)
808 if (resource
->target
!= PIPE_BUFFER
) {
809 if (sscreen
->info
.chip_class
>= GFX9
) {
810 offset
= tex
->surface
.u
.gfx9
.surf_offset
;
811 stride
= tex
->surface
.u
.gfx9
.surf_pitch
*
814 offset
= tex
->surface
.u
.legacy
.level
[0].offset
;
815 stride
= tex
->surface
.u
.legacy
.level
[0].nblk_x
*
827 static boolean
si_texture_get_handle(struct pipe_screen
* screen
,
828 struct pipe_context
*ctx
,
829 struct pipe_resource
*resource
,
830 struct winsys_handle
*whandle
,
833 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
834 struct si_context
*sctx
;
835 struct si_resource
*res
= si_resource(resource
);
836 struct si_texture
*tex
= (struct si_texture
*)resource
;
837 bool update_metadata
= false;
838 unsigned stride
, offset
, slice_size
;
841 ctx
= threaded_context_unwrap_sync(ctx
);
842 sctx
= (struct si_context
*)(ctx
? ctx
: sscreen
->aux_context
);
844 if (resource
->target
!= PIPE_BUFFER
) {
845 /* This is not supported now, but it might be required for OpenCL
846 * interop in the future.
848 if (resource
->nr_samples
> 1 || tex
->is_depth
)
851 /* Move a suballocated texture into a non-suballocated allocation. */
852 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
853 tex
->surface
.tile_swizzle
||
854 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
855 sscreen
->info
.has_local_buffers
&&
856 whandle
->type
!= WINSYS_HANDLE_TYPE_KMS
)) {
857 assert(!res
->b
.is_shared
);
858 si_reallocate_texture_inplace(sctx
, tex
,
859 PIPE_BIND_SHARED
, false);
861 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
862 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
863 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
864 assert(tex
->surface
.tile_swizzle
== 0);
867 /* Since shader image stores don't support DCC on GFX8,
868 * disable it for external clients that want write
871 if ((usage
& PIPE_HANDLE_USAGE_SHADER_WRITE
&& tex
->dcc_offset
) ||
872 /* Displayable DCC requires an explicit flush. */
873 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
874 si_has_displayable_dcc(tex
))) {
875 if (si_texture_disable_dcc(sctx
, tex
)) {
876 update_metadata
= true;
877 /* si_texture_disable_dcc flushes the context */
882 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
883 (tex
->cmask_buffer
|| tex
->dcc_offset
)) {
884 /* Eliminate fast clear (both CMASK and DCC) */
885 si_eliminate_fast_color_clear(sctx
, tex
);
886 /* eliminate_fast_color_clear flushes the context */
889 /* Disable CMASK if flush_resource isn't going
892 if (tex
->cmask_buffer
)
893 si_texture_discard_cmask(sscreen
, tex
);
897 if (!res
->b
.is_shared
|| update_metadata
)
898 si_set_tex_bo_metadata(sscreen
, tex
);
900 if (sscreen
->info
.chip_class
>= GFX9
) {
901 slice_size
= tex
->surface
.u
.gfx9
.surf_slice_size
;
903 slice_size
= (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
906 /* Buffer exports are for the OpenCL interop. */
907 /* Move a suballocated buffer into a non-suballocated allocation. */
908 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
909 /* A DMABUF export always fails if the BO is local. */
910 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
911 sscreen
->info
.has_local_buffers
)) {
912 assert(!res
->b
.is_shared
);
914 /* Allocate a new buffer with PIPE_BIND_SHARED. */
915 struct pipe_resource templ
= res
->b
.b
;
916 templ
.bind
|= PIPE_BIND_SHARED
;
918 struct pipe_resource
*newb
=
919 screen
->resource_create(screen
, &templ
);
923 /* Copy the old buffer contents to the new one. */
925 u_box_1d(0, newb
->width0
, &box
);
926 sctx
->b
.resource_copy_region(&sctx
->b
, newb
, 0, 0, 0, 0,
929 /* Move the new buffer storage to the old pipe_resource. */
930 si_replace_buffer_storage(&sctx
->b
, &res
->b
.b
, newb
);
931 pipe_resource_reference(&newb
, NULL
);
933 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
934 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
941 si_texture_get_info(screen
, resource
, &stride
, &offset
);
944 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
946 if (res
->b
.is_shared
) {
947 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
950 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
951 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
952 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
954 res
->b
.is_shared
= true;
955 res
->external_usage
= usage
;
958 return sscreen
->ws
->buffer_get_handle(sscreen
->ws
, res
->buf
, stride
,
959 offset
, slice_size
, whandle
);
962 static void si_texture_destroy(struct pipe_screen
*screen
,
963 struct pipe_resource
*ptex
)
965 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
966 struct si_texture
*tex
= (struct si_texture
*)ptex
;
967 struct si_resource
*resource
= &tex
->buffer
;
969 if (sscreen
->info
.chip_class
>= GFX9
)
970 free(tex
->surface
.u
.gfx9
.dcc_retile_map
);
972 si_texture_reference(&tex
->flushed_depth_texture
, NULL
);
974 if (tex
->cmask_buffer
!= &tex
->buffer
) {
975 si_resource_reference(&tex
->cmask_buffer
, NULL
);
977 pb_reference(&resource
->buf
, NULL
);
978 si_resource_reference(&tex
->dcc_separate_buffer
, NULL
);
979 si_resource_reference(&tex
->last_dcc_separate_buffer
, NULL
);
983 static const struct u_resource_vtbl si_texture_vtbl
;
985 static void si_texture_get_htile_size(struct si_screen
*sscreen
,
986 struct si_texture
*tex
)
988 unsigned cl_width
, cl_height
, width
, height
;
989 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
990 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
992 assert(sscreen
->info
.chip_class
<= GFX8
);
994 tex
->surface
.htile_size
= 0;
996 if (tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
997 !sscreen
->info
.htile_cmask_support_1d_tiling
)
1000 /* Overalign HTILE on P2 configs to work around GPU hangs in
1001 * piglit/depthstencil-render-miplevels 585.
1003 * This has been confirmed to help Kabini & Stoney, where the hangs
1004 * are always reproducible. I think I have seen the test hang
1005 * on Carrizo too, though it was very rare there.
1007 if (sscreen
->info
.chip_class
>= GFX7
&& num_pipes
< 4)
1010 switch (num_pipes
) {
1036 width
= align(tex
->surface
.u
.legacy
.level
[0].nblk_x
, cl_width
* 8);
1037 height
= align(tex
->surface
.u
.legacy
.level
[0].nblk_y
, cl_height
* 8);
1039 slice_elements
= (width
* height
) / (8 * 8);
1040 slice_bytes
= slice_elements
* 4;
1042 pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
1043 base_align
= num_pipes
* pipe_interleave_bytes
;
1045 tex
->surface
.htile_alignment
= base_align
;
1046 tex
->surface
.htile_size
=
1047 util_num_layers(&tex
->buffer
.b
.b
, 0) *
1048 align(slice_bytes
, base_align
);
1051 static void si_texture_allocate_htile(struct si_screen
*sscreen
,
1052 struct si_texture
*tex
)
1054 if (sscreen
->info
.chip_class
<= GFX8
&& !tex
->tc_compatible_htile
)
1055 si_texture_get_htile_size(sscreen
, tex
);
1057 if (!tex
->surface
.htile_size
)
1060 tex
->htile_offset
= align(tex
->size
, tex
->surface
.htile_alignment
);
1061 tex
->size
= tex
->htile_offset
+ tex
->surface
.htile_size
;
1064 void si_print_texture_info(struct si_screen
*sscreen
,
1065 struct si_texture
*tex
, struct u_log_context
*log
)
1069 /* Common parameters. */
1070 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
1071 "blk_h=%u, array_size=%u, last_level=%u, "
1072 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
1073 tex
->buffer
.b
.b
.width0
, tex
->buffer
.b
.b
.height0
,
1074 tex
->buffer
.b
.b
.depth0
, tex
->surface
.blk_w
,
1076 tex
->buffer
.b
.b
.array_size
, tex
->buffer
.b
.b
.last_level
,
1077 tex
->surface
.bpe
, tex
->buffer
.b
.b
.nr_samples
,
1078 tex
->surface
.flags
, util_format_short_name(tex
->buffer
.b
.b
.format
));
1080 if (sscreen
->info
.chip_class
>= GFX9
) {
1081 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
1082 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
1083 tex
->surface
.surf_size
,
1084 tex
->surface
.u
.gfx9
.surf_slice_size
,
1085 tex
->surface
.surf_alignment
,
1086 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
1087 tex
->surface
.u
.gfx9
.surf
.epitch
,
1088 tex
->surface
.u
.gfx9
.surf_pitch
);
1090 if (tex
->fmask_offset
) {
1091 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
1092 "alignment=%u, swmode=%u, epitch=%u\n",
1094 tex
->surface
.fmask_size
,
1095 tex
->surface
.fmask_alignment
,
1096 tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1097 tex
->surface
.u
.gfx9
.fmask
.epitch
);
1100 if (tex
->cmask_buffer
) {
1101 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%u, "
1102 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1104 tex
->surface
.cmask_size
,
1105 tex
->surface
.cmask_alignment
,
1106 tex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1107 tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1110 if (tex
->htile_offset
) {
1111 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, alignment=%u, "
1112 "rb_aligned=%u, pipe_aligned=%u\n",
1114 tex
->surface
.htile_size
,
1115 tex
->surface
.htile_alignment
,
1116 tex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1117 tex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1120 if (tex
->dcc_offset
) {
1121 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, "
1122 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1123 tex
->dcc_offset
, tex
->surface
.dcc_size
,
1124 tex
->surface
.dcc_alignment
,
1125 tex
->surface
.u
.gfx9
.display_dcc_pitch_max
,
1126 tex
->surface
.num_dcc_levels
);
1129 if (tex
->surface
.u
.gfx9
.stencil_offset
) {
1130 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1131 tex
->surface
.u
.gfx9
.stencil_offset
,
1132 tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1133 tex
->surface
.u
.gfx9
.stencil
.epitch
);
1138 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1139 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1140 tex
->surface
.surf_size
, tex
->surface
.surf_alignment
, tex
->surface
.u
.legacy
.bankw
,
1141 tex
->surface
.u
.legacy
.bankh
, tex
->surface
.u
.legacy
.num_banks
, tex
->surface
.u
.legacy
.mtilea
,
1142 tex
->surface
.u
.legacy
.tile_split
, tex
->surface
.u
.legacy
.pipe_config
,
1143 (tex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1145 if (tex
->fmask_offset
)
1146 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1147 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1148 tex
->fmask_offset
, tex
->surface
.fmask_size
, tex
->surface
.fmask_alignment
,
1149 tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
,
1150 tex
->surface
.u
.legacy
.fmask
.bankh
,
1151 tex
->surface
.u
.legacy
.fmask
.slice_tile_max
,
1152 tex
->surface
.u
.legacy
.fmask
.tiling_index
);
1154 if (tex
->cmask_buffer
)
1155 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%u, alignment=%u, "
1156 "slice_tile_max=%u\n",
1157 tex
->cmask_offset
, tex
->surface
.cmask_size
, tex
->surface
.cmask_alignment
,
1158 tex
->surface
.u
.legacy
.cmask_slice_tile_max
);
1160 if (tex
->htile_offset
)
1161 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, "
1162 "alignment=%u, TC_compatible = %u\n",
1163 tex
->htile_offset
, tex
->surface
.htile_size
,
1164 tex
->surface
.htile_alignment
,
1165 tex
->tc_compatible_htile
);
1167 if (tex
->dcc_offset
) {
1168 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, alignment=%u\n",
1169 tex
->dcc_offset
, tex
->surface
.dcc_size
,
1170 tex
->surface
.dcc_alignment
);
1171 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1172 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%u, "
1173 "fast_clear_size=%u\n",
1174 i
, i
< tex
->surface
.num_dcc_levels
,
1175 tex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1176 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1179 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1180 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1181 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1182 "mode=%u, tiling_index = %u\n",
1183 i
, tex
->surface
.u
.legacy
.level
[i
].offset
,
1184 (uint64_t)tex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
1185 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1186 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1187 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1188 tex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1189 tex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1190 tex
->surface
.u
.legacy
.level
[i
].mode
,
1191 tex
->surface
.u
.legacy
.tiling_index
[i
]);
1193 if (tex
->surface
.has_stencil
) {
1194 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1195 tex
->surface
.u
.legacy
.stencil_tile_split
);
1196 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++) {
1197 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1198 "slice_size=%"PRIu64
", npix_x=%u, "
1199 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1200 "mode=%u, tiling_index = %u\n",
1201 i
, tex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1202 (uint64_t)tex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
1203 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1204 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1205 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1206 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1207 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1208 tex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1209 tex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1214 /* Common processing for si_texture_create and si_texture_from_handle */
1215 static struct si_texture
*
1216 si_texture_create_object(struct pipe_screen
*screen
,
1217 const struct pipe_resource
*base
,
1218 struct pb_buffer
*buf
,
1219 struct radeon_surf
*surface
)
1221 struct si_texture
*tex
;
1222 struct si_resource
*resource
;
1223 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1225 tex
= CALLOC_STRUCT(si_texture
);
1229 resource
= &tex
->buffer
;
1230 resource
->b
.b
= *base
;
1231 resource
->b
.b
.next
= NULL
;
1232 resource
->b
.vtbl
= &si_texture_vtbl
;
1233 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1234 resource
->b
.b
.screen
= screen
;
1236 /* don't include stencil-only formats which we don't support for rendering */
1237 tex
->is_depth
= util_format_has_depth(util_format_description(tex
->buffer
.b
.b
.format
));
1239 tex
->surface
= *surface
;
1240 tex
->size
= tex
->surface
.surf_size
;
1242 tex
->tc_compatible_htile
= tex
->surface
.htile_size
!= 0 &&
1243 (tex
->surface
.flags
&
1244 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1246 /* TC-compatible HTILE:
1247 * - GFX8 only supports Z32_FLOAT.
1248 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1249 if (tex
->tc_compatible_htile
) {
1250 if (sscreen
->info
.chip_class
>= GFX9
&&
1251 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1252 tex
->db_render_format
= base
->format
;
1254 tex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1255 tex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1256 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1259 tex
->db_render_format
= base
->format
;
1262 /* Applies to GCN. */
1263 tex
->last_msaa_resolve_target_micro_mode
= tex
->surface
.micro_tile_mode
;
1265 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1266 * between frames, so the only thing that can enable separate DCC
1267 * with DRI2 is multiple slow clears within a frame.
1269 tex
->ps_draw_ratio
= 0;
1271 if (tex
->is_depth
) {
1272 if (sscreen
->info
.chip_class
>= GFX9
) {
1273 tex
->can_sample_z
= true;
1274 tex
->can_sample_s
= true;
1276 /* Stencil texturing with HTILE doesn't work
1277 * with mipmapping on Navi10-14. */
1278 if ((sscreen
->info
.family
== CHIP_NAVI10
||
1279 sscreen
->info
.family
== CHIP_NAVI12
||
1280 sscreen
->info
.family
== CHIP_NAVI14
) &&
1281 base
->last_level
> 0)
1282 tex
->htile_stencil_disabled
= true;
1284 tex
->can_sample_z
= !tex
->surface
.u
.legacy
.depth_adjusted
;
1285 tex
->can_sample_s
= !tex
->surface
.u
.legacy
.stencil_adjusted
;
1288 if (!(base
->flags
& (SI_RESOURCE_FLAG_TRANSFER
|
1289 SI_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1290 tex
->db_compatible
= true;
1292 if (!(sscreen
->debug_flags
& DBG(NO_HYPERZ
)))
1293 si_texture_allocate_htile(sscreen
, tex
);
1296 if (base
->nr_samples
> 1 &&
1298 !(sscreen
->debug_flags
& DBG(NO_FMASK
))) {
1299 /* Allocate FMASK. */
1300 tex
->fmask_offset
= align64(tex
->size
,
1301 tex
->surface
.fmask_alignment
);
1302 tex
->size
= tex
->fmask_offset
+ tex
->surface
.fmask_size
;
1304 /* Allocate CMASK. */
1305 tex
->cmask_offset
= align64(tex
->size
, tex
->surface
.cmask_alignment
);
1306 tex
->size
= tex
->cmask_offset
+ tex
->surface
.cmask_size
;
1307 tex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
1308 tex
->cmask_buffer
= &tex
->buffer
;
1310 if (!tex
->surface
.fmask_size
|| !tex
->surface
.cmask_size
)
1314 /* Shared textures must always set up DCC here.
1315 * If it's not present, it will be disabled by
1316 * apply_opaque_metadata later.
1318 if (tex
->surface
.dcc_size
&&
1319 (buf
|| !(sscreen
->debug_flags
& DBG(NO_DCC
))) &&
1320 (sscreen
->info
.use_display_dcc_unaligned
||
1321 sscreen
->info
.use_display_dcc_with_retile_blit
||
1322 !(tex
->surface
.flags
& RADEON_SURF_SCANOUT
))) {
1323 /* Add space for the DCC buffer. */
1324 tex
->dcc_offset
= align64(tex
->size
, tex
->surface
.dcc_alignment
);
1325 tex
->size
= tex
->dcc_offset
+ tex
->surface
.dcc_size
;
1327 if (sscreen
->info
.chip_class
>= GFX9
&&
1328 tex
->surface
.u
.gfx9
.dcc_retile_num_elements
) {
1329 /* Add space for the displayable DCC buffer. */
1330 tex
->display_dcc_offset
=
1331 align64(tex
->size
, tex
->surface
.u
.gfx9
.display_dcc_alignment
);
1332 tex
->size
= tex
->display_dcc_offset
+
1333 tex
->surface
.u
.gfx9
.display_dcc_size
;
1335 /* Add space for the DCC retile buffer. (16-bit or 32-bit elements) */
1336 tex
->dcc_retile_map_offset
=
1337 align64(tex
->size
, sscreen
->info
.tcc_cache_line_size
);
1339 if (tex
->surface
.u
.gfx9
.dcc_retile_use_uint16
) {
1340 tex
->size
= tex
->dcc_retile_map_offset
+
1341 tex
->surface
.u
.gfx9
.dcc_retile_num_elements
* 2;
1343 tex
->size
= tex
->dcc_retile_map_offset
+
1344 tex
->surface
.u
.gfx9
.dcc_retile_num_elements
* 4;
1350 /* Now create the backing buffer. */
1352 si_init_resource_fields(sscreen
, resource
, tex
->size
,
1353 tex
->surface
.surf_alignment
);
1355 if (!si_alloc_resource(sscreen
, resource
))
1358 resource
->buf
= buf
;
1359 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1360 resource
->bo_size
= buf
->size
;
1361 resource
->bo_alignment
= buf
->alignment
;
1362 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1363 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1364 resource
->vram_usage
= buf
->size
;
1365 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1366 resource
->gart_usage
= buf
->size
;
1369 if (tex
->cmask_buffer
) {
1370 /* Initialize the cmask to 0xCC (= compressed state). */
1371 si_screen_clear_buffer(sscreen
, &tex
->cmask_buffer
->b
.b
,
1372 tex
->cmask_offset
, tex
->surface
.cmask_size
,
1375 if (tex
->htile_offset
) {
1376 uint32_t clear_value
= 0;
1378 if (sscreen
->info
.chip_class
>= GFX9
|| tex
->tc_compatible_htile
)
1379 clear_value
= 0x0000030F;
1381 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1383 tex
->surface
.htile_size
,
1387 /* Initialize DCC only if the texture is not being imported. */
1388 if (!buf
&& tex
->dcc_offset
) {
1389 /* Clear DCC to black for all tiles with DCC enabled.
1391 * This fixes corruption in 3DMark Slingshot Extreme, which
1392 * uses uninitialized textures, causing corruption.
1394 if (tex
->surface
.num_dcc_levels
== tex
->buffer
.b
.b
.last_level
+ 1 &&
1395 tex
->buffer
.b
.b
.nr_samples
<= 2) {
1396 /* Simple case - all tiles have DCC enabled. */
1397 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1399 tex
->surface
.dcc_size
,
1400 DCC_CLEAR_COLOR_0000
);
1401 } else if (sscreen
->info
.chip_class
>= GFX9
) {
1402 /* Clear to uncompressed. Clearing this to black is complicated. */
1403 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1405 tex
->surface
.dcc_size
,
1408 /* GFX8: Initialize mipmap levels and multisamples separately. */
1409 if (tex
->buffer
.b
.b
.nr_samples
>= 2) {
1410 /* Clearing this to black is complicated. */
1411 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1413 tex
->surface
.dcc_size
,
1416 /* Clear the enabled mipmap levels to black. */
1419 for (unsigned i
= 0; i
< tex
->surface
.num_dcc_levels
; i
++) {
1420 if (!tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
)
1423 size
= tex
->surface
.u
.legacy
.level
[i
].dcc_offset
+
1424 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
;
1427 /* Mipmap levels with DCC. */
1429 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1430 tex
->dcc_offset
, size
,
1431 DCC_CLEAR_COLOR_0000
);
1433 /* Mipmap levels without DCC. */
1434 if (size
!= tex
->surface
.dcc_size
) {
1435 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1436 tex
->dcc_offset
+ size
,
1437 tex
->surface
.dcc_size
- size
,
1443 /* Upload the DCC retile map. */
1444 if (tex
->dcc_retile_map_offset
) {
1445 /* Use a staging buffer for the upload, because
1446 * the buffer backing the texture is unmappable.
1448 bool use_uint16
= tex
->surface
.u
.gfx9
.dcc_retile_use_uint16
;
1449 unsigned num_elements
= tex
->surface
.u
.gfx9
.dcc_retile_num_elements
;
1450 struct si_resource
*buf
=
1451 si_aligned_buffer_create(screen
, 0, PIPE_USAGE_STREAM
,
1452 num_elements
* (use_uint16
? 2 : 4),
1453 sscreen
->info
.tcc_cache_line_size
);
1454 uint32_t *ui
= (uint32_t*)sscreen
->ws
->buffer_map(buf
->buf
, NULL
,
1455 PIPE_TRANSFER_WRITE
);
1456 uint16_t *us
= (uint16_t*)ui
;
1458 /* Upload the retile map into a staging buffer. */
1460 for (unsigned i
= 0; i
< num_elements
; i
++)
1461 us
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1463 for (unsigned i
= 0; i
< num_elements
; i
++)
1464 ui
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1467 /* Copy the staging buffer to the buffer backing the texture. */
1468 struct si_context
*sctx
= (struct si_context
*)sscreen
->aux_context
;
1469 struct pipe_box box
;
1470 u_box_1d(0, buf
->b
.b
.width0
, &box
);
1472 assert(tex
->dcc_retile_map_offset
<= UINT_MAX
);
1473 mtx_lock(&sscreen
->aux_context_lock
);
1474 sctx
->dma_copy(&sctx
->b
, &tex
->buffer
.b
.b
, 0,
1475 tex
->dcc_retile_map_offset
, 0, 0,
1476 &buf
->b
.b
, 0, &box
);
1477 sscreen
->aux_context
->flush(sscreen
->aux_context
, NULL
, 0);
1478 mtx_unlock(&sscreen
->aux_context_lock
);
1480 si_resource_reference(&buf
, NULL
);
1484 /* Initialize the CMASK base register value. */
1485 tex
->cmask_base_address_reg
=
1486 (tex
->buffer
.gpu_address
+ tex
->cmask_offset
) >> 8;
1488 if (sscreen
->debug_flags
& DBG(VM
)) {
1489 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1490 tex
->buffer
.gpu_address
,
1491 tex
->buffer
.gpu_address
+ tex
->buffer
.buf
->size
,
1492 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+1,
1493 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1496 if (sscreen
->debug_flags
& DBG(TEX
)) {
1498 struct u_log_context log
;
1499 u_log_context_init(&log
);
1500 si_print_texture_info(sscreen
, tex
, &log
);
1501 u_log_new_page_print(&log
, stdout
);
1503 u_log_context_destroy(&log
);
1510 if (sscreen
->info
.chip_class
>= GFX9
)
1511 free(surface
->u
.gfx9
.dcc_retile_map
);
1515 static enum radeon_surf_mode
1516 si_choose_tiling(struct si_screen
*sscreen
,
1517 const struct pipe_resource
*templ
, bool tc_compatible_htile
)
1519 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1520 bool force_tiling
= templ
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
;
1521 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1522 !(templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
);
1524 /* MSAA resources must be 2D tiled. */
1525 if (templ
->nr_samples
> 1)
1526 return RADEON_SURF_MODE_2D
;
1528 /* Transfer resources should be linear. */
1529 if (templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
)
1530 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1532 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on GFX8,
1533 * which requires 2D tiling.
1535 if (sscreen
->info
.chip_class
== GFX8
&& tc_compatible_htile
)
1536 return RADEON_SURF_MODE_2D
;
1538 /* Handle common candidates for the linear mode.
1539 * Compressed textures and DB surfaces must always be tiled.
1541 if (!force_tiling
&&
1542 !is_depth_stencil
&&
1543 !util_format_is_compressed(templ
->format
)) {
1544 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1545 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1547 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. */
1548 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1549 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1551 /* Cursors are linear on AMD GCN.
1552 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1553 if (templ
->bind
& PIPE_BIND_CURSOR
)
1554 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1556 if (templ
->bind
& PIPE_BIND_LINEAR
)
1557 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1559 /* Textures with a very small height are recommended to be linear. */
1560 if (templ
->target
== PIPE_TEXTURE_1D
||
1561 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1562 /* Only very thin and long 2D textures should benefit from
1563 * linear_aligned. */
1564 (templ
->width0
> 8 && templ
->height0
<= 2))
1565 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1567 /* Textures likely to be mapped often. */
1568 if (templ
->usage
== PIPE_USAGE_STAGING
||
1569 templ
->usage
== PIPE_USAGE_STREAM
)
1570 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1573 /* Make small textures 1D tiled. */
1574 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1575 (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1576 return RADEON_SURF_MODE_1D
;
1578 /* The allocator will switch to 1D if needed. */
1579 return RADEON_SURF_MODE_2D
;
1582 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1583 const struct pipe_resource
*templ
)
1585 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1586 bool is_zs
= util_format_is_depth_or_stencil(templ
->format
);
1588 if (templ
->nr_samples
>= 2) {
1589 /* This is hackish (overwriting the const pipe_resource template),
1590 * but should be harmless and state trackers can also see
1591 * the overriden number of samples in the created pipe_resource.
1593 if (is_zs
&& sscreen
->eqaa_force_z_samples
) {
1594 ((struct pipe_resource
*)templ
)->nr_samples
=
1595 ((struct pipe_resource
*)templ
)->nr_storage_samples
=
1596 sscreen
->eqaa_force_z_samples
;
1597 } else if (!is_zs
&& sscreen
->eqaa_force_color_samples
) {
1598 ((struct pipe_resource
*)templ
)->nr_samples
=
1599 sscreen
->eqaa_force_coverage_samples
;
1600 ((struct pipe_resource
*)templ
)->nr_storage_samples
=
1601 sscreen
->eqaa_force_color_samples
;
1605 struct radeon_surf surface
= {0};
1606 bool is_flushed_depth
= templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1607 bool tc_compatible_htile
=
1608 sscreen
->info
.chip_class
>= GFX8
&&
1609 /* There are issues with TC-compatible HTILE on Tonga (and
1610 * Iceland is the same design), and documented bug workarounds
1611 * don't help. For example, this fails:
1612 * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow -auto
1614 sscreen
->info
.family
!= CHIP_TONGA
&&
1615 sscreen
->info
.family
!= CHIP_ICELAND
&&
1616 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1617 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) &&
1618 !is_flushed_depth
&&
1619 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1623 r
= si_init_surface(sscreen
, &surface
, templ
,
1624 si_choose_tiling(sscreen
, templ
, tc_compatible_htile
),
1625 0, 0, false, false, is_flushed_depth
,
1626 tc_compatible_htile
);
1631 return (struct pipe_resource
*)
1632 si_texture_create_object(screen
, templ
, NULL
, &surface
);
1635 static struct pipe_resource
*si_texture_from_winsys_buffer(struct si_screen
*sscreen
,
1636 const struct pipe_resource
*templ
,
1637 struct pb_buffer
*buf
,
1643 enum radeon_surf_mode array_mode
;
1644 struct radeon_surf surface
= {};
1645 struct radeon_bo_metadata metadata
= {};
1646 struct si_texture
*tex
;
1651 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1652 si_get_display_metadata(sscreen
, &surface
, &metadata
,
1653 &array_mode
, &is_scanout
);
1656 * The bo metadata is unset for un-dedicated images. So we fall
1657 * back to linear. See answer to question 5 of the
1658 * VK_KHX_external_memory spec for some details.
1660 * It is possible that this case isn't going to work if the
1661 * surface pitch isn't correctly aligned by default.
1663 * In order to support it correctly we require multi-image
1664 * metadata to be syncrhonized between radv and radeonsi. The
1665 * semantics of associating multiple image metadata to a memory
1666 * object on the vulkan export side are not concretely defined
1669 * All the use cases we are aware of at the moment for memory
1670 * objects use dedicated allocations. So lets keep the initial
1671 * implementation simple.
1673 * A possible alternative is to attempt to reconstruct the
1674 * tiling information when the TexParameter TEXTURE_TILING_EXT
1677 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1681 r
= si_init_surface(sscreen
, &surface
, templ
,
1682 array_mode
, stride
, offset
, true, is_scanout
,
1687 tex
= si_texture_create_object(&sscreen
->b
, templ
, buf
, &surface
);
1691 tex
->buffer
.b
.is_shared
= true;
1692 tex
->buffer
.external_usage
= usage
;
1694 si_get_opaque_metadata(sscreen
, tex
, &metadata
);
1696 /* Displayable DCC requires an explicit flush. */
1698 !(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
1699 si_has_displayable_dcc(tex
)) {
1700 /* TODO: do we need to decompress DCC? */
1701 if (si_texture_discard_dcc(sscreen
, tex
)) {
1702 /* Update BO metadata after disabling DCC. */
1703 si_set_tex_bo_metadata(sscreen
, tex
);
1707 assert(tex
->surface
.tile_swizzle
== 0);
1708 return &tex
->buffer
.b
.b
;
1711 static struct pipe_resource
*si_texture_from_handle(struct pipe_screen
*screen
,
1712 const struct pipe_resource
*templ
,
1713 struct winsys_handle
*whandle
,
1716 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1717 struct pb_buffer
*buf
= NULL
;
1718 unsigned stride
= 0, offset
= 0;
1720 /* Support only 2D textures without mipmaps */
1721 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1722 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1725 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
1726 sscreen
->info
.max_alignment
,
1731 return si_texture_from_winsys_buffer(sscreen
, templ
, buf
, stride
,
1732 offset
, usage
, true);
1735 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1736 struct pipe_resource
*texture
)
1738 struct si_texture
*tex
= (struct si_texture
*)texture
;
1739 struct pipe_resource resource
;
1740 enum pipe_format pipe_format
= texture
->format
;
1742 assert(!tex
->flushed_depth_texture
);
1744 if (!tex
->can_sample_z
&& tex
->can_sample_s
) {
1745 switch (pipe_format
) {
1746 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1747 /* Save memory by not allocating the S plane. */
1748 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1750 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1751 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1752 /* Save memory bandwidth by not copying the
1753 * stencil part during flush.
1755 * This potentially increases memory bandwidth
1756 * if an application uses both Z and S texturing
1757 * simultaneously (a flushed Z24S8 texture
1758 * would be stored compactly), but how often
1759 * does that really happen?
1761 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1765 } else if (!tex
->can_sample_s
&& tex
->can_sample_z
) {
1766 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1768 /* DB->CB copies to an 8bpp surface don't work. */
1769 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1772 memset(&resource
, 0, sizeof(resource
));
1773 resource
.target
= texture
->target
;
1774 resource
.format
= pipe_format
;
1775 resource
.width0
= texture
->width0
;
1776 resource
.height0
= texture
->height0
;
1777 resource
.depth0
= texture
->depth0
;
1778 resource
.array_size
= texture
->array_size
;
1779 resource
.last_level
= texture
->last_level
;
1780 resource
.nr_samples
= texture
->nr_samples
;
1781 resource
.usage
= PIPE_USAGE_DEFAULT
;
1782 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1783 resource
.flags
= texture
->flags
| SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1785 tex
->flushed_depth_texture
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1786 if (!tex
->flushed_depth_texture
) {
1787 PRINT_ERR("failed to create temporary texture to hold flushed depth\n");
1794 * Initialize the pipe_resource descriptor to be of the same size as the box,
1795 * which is supposed to hold a subregion of the texture "orig" at the given
1798 static void si_init_temp_resource_from_box(struct pipe_resource
*res
,
1799 struct pipe_resource
*orig
,
1800 const struct pipe_box
*box
,
1801 unsigned level
, unsigned flags
)
1803 memset(res
, 0, sizeof(*res
));
1804 res
->format
= orig
->format
;
1805 res
->width0
= box
->width
;
1806 res
->height0
= box
->height
;
1808 res
->array_size
= 1;
1809 res
->usage
= flags
& SI_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1812 if (flags
& SI_RESOURCE_FLAG_TRANSFER
&&
1813 util_format_is_compressed(orig
->format
)) {
1814 /* Transfer resources are allocated with linear tiling, which is
1815 * not supported for compressed formats.
1817 unsigned blocksize
=
1818 util_format_get_blocksize(orig
->format
);
1820 if (blocksize
== 8) {
1821 res
->format
= PIPE_FORMAT_R16G16B16A16_UINT
;
1823 assert(blocksize
== 16);
1824 res
->format
= PIPE_FORMAT_R32G32B32A32_UINT
;
1827 res
->width0
= util_format_get_nblocksx(orig
->format
, box
->width
);
1828 res
->height0
= util_format_get_nblocksy(orig
->format
, box
->height
);
1831 /* We must set the correct texture target and dimensions for a 3D box. */
1832 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1833 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1834 res
->array_size
= box
->depth
;
1836 res
->target
= PIPE_TEXTURE_2D
;
1840 static bool si_can_invalidate_texture(struct si_screen
*sscreen
,
1841 struct si_texture
*tex
,
1842 unsigned transfer_usage
,
1843 const struct pipe_box
*box
)
1845 return !tex
->buffer
.b
.is_shared
&&
1846 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1847 tex
->buffer
.b
.b
.last_level
== 0 &&
1848 util_texrange_covers_whole_level(&tex
->buffer
.b
.b
, 0,
1849 box
->x
, box
->y
, box
->z
,
1850 box
->width
, box
->height
,
1854 static void si_texture_invalidate_storage(struct si_context
*sctx
,
1855 struct si_texture
*tex
)
1857 struct si_screen
*sscreen
= sctx
->screen
;
1859 /* There is no point in discarding depth and tiled buffers. */
1860 assert(!tex
->is_depth
);
1861 assert(tex
->surface
.is_linear
);
1863 /* Reallocate the buffer in the same pipe_resource. */
1864 si_alloc_resource(sscreen
, &tex
->buffer
);
1866 /* Initialize the CMASK base address (needed even without CMASK). */
1867 tex
->cmask_base_address_reg
=
1868 (tex
->buffer
.gpu_address
+ tex
->cmask_offset
) >> 8;
1870 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1872 sctx
->num_alloc_tex_transfer_bytes
+= tex
->size
;
1875 static void *si_texture_transfer_map(struct pipe_context
*ctx
,
1876 struct pipe_resource
*texture
,
1879 const struct pipe_box
*box
,
1880 struct pipe_transfer
**ptransfer
)
1882 struct si_context
*sctx
= (struct si_context
*)ctx
;
1883 struct si_texture
*tex
= (struct si_texture
*)texture
;
1884 struct si_transfer
*trans
;
1885 struct si_resource
*buf
;
1886 unsigned offset
= 0;
1888 bool use_staging_texture
= false;
1890 assert(!(texture
->flags
& SI_RESOURCE_FLAG_TRANSFER
));
1891 assert(box
->width
&& box
->height
&& box
->depth
);
1893 if (tex
->is_depth
) {
1894 /* Depth textures use staging unconditionally. */
1895 use_staging_texture
= true;
1897 /* Degrade the tile mode if we get too many transfers on APUs.
1898 * On dGPUs, the staging texture is always faster.
1899 * Only count uploads that are at least 4x4 pixels large.
1901 if (!sctx
->screen
->info
.has_dedicated_vram
&&
1903 box
->width
>= 4 && box
->height
>= 4 &&
1904 p_atomic_inc_return(&tex
->num_level0_transfers
) == 10) {
1905 bool can_invalidate
=
1906 si_can_invalidate_texture(sctx
->screen
, tex
,
1909 si_reallocate_texture_inplace(sctx
, tex
,
1914 /* Tiled textures need to be converted into a linear texture for CPU
1915 * access. The staging texture is always linear and is placed in GART.
1917 * Reading from VRAM or GTT WC is slow, always use the staging
1918 * texture in this case.
1920 * Use the staging texture for uploads if the underlying BO
1923 if (!tex
->surface
.is_linear
)
1924 use_staging_texture
= true;
1925 else if (usage
& PIPE_TRANSFER_READ
)
1926 use_staging_texture
=
1927 tex
->buffer
.domains
& RADEON_DOMAIN_VRAM
||
1928 tex
->buffer
.flags
& RADEON_FLAG_GTT_WC
;
1929 /* Write & linear only: */
1930 else if (si_rings_is_buffer_referenced(sctx
, tex
->buffer
.buf
,
1931 RADEON_USAGE_READWRITE
) ||
1932 !sctx
->ws
->buffer_wait(tex
->buffer
.buf
, 0,
1933 RADEON_USAGE_READWRITE
)) {
1935 if (si_can_invalidate_texture(sctx
->screen
, tex
,
1937 si_texture_invalidate_storage(sctx
, tex
);
1939 use_staging_texture
= true;
1943 trans
= CALLOC_STRUCT(si_transfer
);
1946 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1947 trans
->b
.b
.level
= level
;
1948 trans
->b
.b
.usage
= usage
;
1949 trans
->b
.b
.box
= *box
;
1951 if (use_staging_texture
) {
1952 struct pipe_resource resource
;
1953 struct si_texture
*staging
;
1955 si_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1956 SI_RESOURCE_FLAG_TRANSFER
);
1957 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1958 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1960 /* Since depth-stencil textures don't support linear tiling,
1961 * blit from ZS to color and vice versa. u_blitter will do
1962 * the packing for these formats.
1965 resource
.format
= util_blitter_get_color_format_for_zs(resource
.format
);
1967 /* Create the temporary texture. */
1968 staging
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1970 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1973 trans
->staging
= &staging
->buffer
;
1975 /* Just get the strides. */
1976 si_texture_get_offset(sctx
->screen
, staging
, 0, NULL
,
1978 &trans
->b
.b
.layer_stride
);
1980 if (usage
& PIPE_TRANSFER_READ
)
1981 si_copy_to_staging_texture(ctx
, trans
);
1983 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1985 buf
= trans
->staging
;
1987 /* the resource is mapped directly */
1988 offset
= si_texture_get_offset(sctx
->screen
, tex
, level
, box
,
1990 &trans
->b
.b
.layer_stride
);
1994 /* Always unmap texture CPU mappings on 32-bit architectures, so that
1995 * we don't run out of the CPU address space.
1997 if (sizeof(void*) == 4)
1998 usage
|= RADEON_TRANSFER_TEMPORARY
;
2000 if (!(map
= si_buffer_map_sync_with_rings(sctx
, buf
, usage
)))
2003 *ptransfer
= &trans
->b
.b
;
2004 return map
+ offset
;
2007 si_resource_reference(&trans
->staging
, NULL
);
2008 pipe_resource_reference(&trans
->b
.b
.resource
, NULL
);
2013 static void si_texture_transfer_unmap(struct pipe_context
*ctx
,
2014 struct pipe_transfer
* transfer
)
2016 struct si_context
*sctx
= (struct si_context
*)ctx
;
2017 struct si_transfer
*stransfer
= (struct si_transfer
*)transfer
;
2018 struct pipe_resource
*texture
= transfer
->resource
;
2019 struct si_texture
*tex
= (struct si_texture
*)texture
;
2021 /* Always unmap texture CPU mappings on 32-bit architectures, so that
2022 * we don't run out of the CPU address space.
2024 if (sizeof(void*) == 4) {
2025 struct si_resource
*buf
=
2026 stransfer
->staging
? stransfer
->staging
: &tex
->buffer
;
2028 sctx
->ws
->buffer_unmap(buf
->buf
);
2031 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && stransfer
->staging
)
2032 si_copy_from_staging_texture(ctx
, stransfer
);
2034 if (stransfer
->staging
) {
2035 sctx
->num_alloc_tex_transfer_bytes
+= stransfer
->staging
->buf
->size
;
2036 si_resource_reference(&stransfer
->staging
, NULL
);
2039 /* Heuristic for {upload, draw, upload, draw, ..}:
2041 * Flush the gfx IB if we've allocated too much texture storage.
2043 * The idea is that we don't want to build IBs that use too much
2044 * memory and put pressure on the kernel memory manager and we also
2045 * want to make temporary and invalidated buffers go idle ASAP to
2046 * decrease the total memory usage or make them reusable. The memory
2047 * usage will be slightly higher than given here because of the buffer
2048 * cache in the winsys.
2050 * The result is that the kernel memory manager is never a bottleneck.
2052 if (sctx
->num_alloc_tex_transfer_bytes
> sctx
->screen
->info
.gart_size
/ 4) {
2053 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
2054 sctx
->num_alloc_tex_transfer_bytes
= 0;
2057 pipe_resource_reference(&transfer
->resource
, NULL
);
2061 static const struct u_resource_vtbl si_texture_vtbl
=
2063 NULL
, /* get_handle */
2064 si_texture_destroy
, /* resource_destroy */
2065 si_texture_transfer_map
, /* transfer_map */
2066 u_default_transfer_flush_region
, /* transfer_flush_region */
2067 si_texture_transfer_unmap
, /* transfer_unmap */
2070 /* Return if it's allowed to reinterpret one format as another with DCC enabled.
2072 bool vi_dcc_formats_compatible(struct si_screen
*sscreen
,
2073 enum pipe_format format1
,
2074 enum pipe_format format2
)
2076 const struct util_format_description
*desc1
, *desc2
;
2078 /* No format change - exit early. */
2079 if (format1
== format2
)
2082 format1
= si_simplify_cb_format(format1
);
2083 format2
= si_simplify_cb_format(format2
);
2085 /* Check again after format adjustments. */
2086 if (format1
== format2
)
2089 desc1
= util_format_description(format1
);
2090 desc2
= util_format_description(format2
);
2092 if (desc1
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
2093 desc2
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2096 /* Float and non-float are totally incompatible. */
2097 if ((desc1
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
) !=
2098 (desc2
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
))
2101 /* Channel sizes must match across DCC formats.
2102 * Comparing just the first 2 channels should be enough.
2104 if (desc1
->channel
[0].size
!= desc2
->channel
[0].size
||
2105 (desc1
->nr_channels
>= 2 &&
2106 desc1
->channel
[1].size
!= desc2
->channel
[1].size
))
2109 /* Everything below is not needed if the driver never uses the DCC
2110 * clear code with the value of 1.
2113 /* If the clear values are all 1 or all 0, this constraint can be
2115 if (vi_alpha_is_on_msb(sscreen
, format1
) != vi_alpha_is_on_msb(sscreen
, format2
))
2118 /* Channel types must match if the clear value of 1 is used.
2119 * The type categories are only float, signed, unsigned.
2120 * NORM and INT are always compatible.
2122 if (desc1
->channel
[0].type
!= desc2
->channel
[0].type
||
2123 (desc1
->nr_channels
>= 2 &&
2124 desc1
->channel
[1].type
!= desc2
->channel
[1].type
))
2130 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
2132 enum pipe_format view_format
)
2134 struct si_texture
*stex
= (struct si_texture
*)tex
;
2136 return vi_dcc_enabled(stex
, level
) &&
2137 !vi_dcc_formats_compatible((struct si_screen
*)tex
->screen
,
2138 tex
->format
, view_format
);
2141 /* This can't be merged with the above function, because
2142 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
2143 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
2144 struct pipe_resource
*tex
,
2146 enum pipe_format view_format
)
2148 struct si_texture
*stex
= (struct si_texture
*)tex
;
2150 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
2151 if (!si_texture_disable_dcc(sctx
, stex
))
2152 si_decompress_dcc(sctx
, stex
);
2155 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
2156 struct pipe_resource
*texture
,
2157 const struct pipe_surface
*templ
,
2158 unsigned width0
, unsigned height0
,
2159 unsigned width
, unsigned height
)
2161 struct si_surface
*surface
= CALLOC_STRUCT(si_surface
);
2166 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2167 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2169 pipe_reference_init(&surface
->base
.reference
, 1);
2170 pipe_resource_reference(&surface
->base
.texture
, texture
);
2171 surface
->base
.context
= pipe
;
2172 surface
->base
.format
= templ
->format
;
2173 surface
->base
.width
= width
;
2174 surface
->base
.height
= height
;
2175 surface
->base
.u
= templ
->u
;
2177 surface
->width0
= width0
;
2178 surface
->height0
= height0
;
2180 surface
->dcc_incompatible
=
2181 texture
->target
!= PIPE_BUFFER
&&
2182 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
2184 return &surface
->base
;
2187 static struct pipe_surface
*si_create_surface(struct pipe_context
*pipe
,
2188 struct pipe_resource
*tex
,
2189 const struct pipe_surface
*templ
)
2191 unsigned level
= templ
->u
.tex
.level
;
2192 unsigned width
= u_minify(tex
->width0
, level
);
2193 unsigned height
= u_minify(tex
->height0
, level
);
2194 unsigned width0
= tex
->width0
;
2195 unsigned height0
= tex
->height0
;
2197 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2198 const struct util_format_description
*tex_desc
2199 = util_format_description(tex
->format
);
2200 const struct util_format_description
*templ_desc
2201 = util_format_description(templ
->format
);
2203 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2205 /* Adjust size of surface if and only if the block width or
2206 * height is changed. */
2207 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2208 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2209 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2210 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2212 width
= nblks_x
* templ_desc
->block
.width
;
2213 height
= nblks_y
* templ_desc
->block
.height
;
2215 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2216 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2220 return si_create_surface_custom(pipe
, tex
, templ
,
2225 static void si_surface_destroy(struct pipe_context
*pipe
,
2226 struct pipe_surface
*surface
)
2228 pipe_resource_reference(&surface
->texture
, NULL
);
2232 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2234 const struct util_format_description
*desc
= util_format_description(format
);
2236 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2238 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2239 return V_028C70_SWAP_STD
;
2241 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2244 switch (desc
->nr_channels
) {
2246 if (HAS_SWIZZLE(0,X
))
2247 return V_028C70_SWAP_STD
; /* X___ */
2248 else if (HAS_SWIZZLE(3,X
))
2249 return V_028C70_SWAP_ALT_REV
; /* ___X */
2252 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2253 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2254 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2255 return V_028C70_SWAP_STD
; /* XY__ */
2256 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2257 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2258 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2260 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2261 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2262 return V_028C70_SWAP_ALT
; /* X__Y */
2263 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2264 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2267 if (HAS_SWIZZLE(0,X
))
2268 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2269 else if (HAS_SWIZZLE(0,Z
))
2270 return V_028C70_SWAP_STD_REV
; /* ZYX */
2273 /* check the middle channels, the 1st and 4th channel can be NONE */
2274 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2275 return V_028C70_SWAP_STD
; /* XYZW */
2276 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2277 return V_028C70_SWAP_STD_REV
; /* WZYX */
2278 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2279 return V_028C70_SWAP_ALT
; /* ZYXW */
2280 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2283 return V_028C70_SWAP_ALT_REV
;
2285 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2292 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2294 static void vi_dcc_clean_up_context_slot(struct si_context
*sctx
,
2299 if (sctx
->dcc_stats
[slot
].query_active
)
2300 vi_separate_dcc_stop_query(sctx
,
2301 sctx
->dcc_stats
[slot
].tex
);
2303 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
[slot
].ps_stats
); i
++)
2304 if (sctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2305 sctx
->b
.destroy_query(&sctx
->b
,
2306 sctx
->dcc_stats
[slot
].ps_stats
[i
]);
2307 sctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2310 si_texture_reference(&sctx
->dcc_stats
[slot
].tex
, NULL
);
2314 * Return the per-context slot where DCC statistics queries for the texture live.
2316 static unsigned vi_get_context_dcc_stats_index(struct si_context
*sctx
,
2317 struct si_texture
*tex
)
2319 int i
, empty_slot
= -1;
2321 /* Remove zombie textures (textures kept alive by this array only). */
2322 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2323 if (sctx
->dcc_stats
[i
].tex
&&
2324 sctx
->dcc_stats
[i
].tex
->buffer
.b
.b
.reference
.count
== 1)
2325 vi_dcc_clean_up_context_slot(sctx
, i
);
2327 /* Find the texture. */
2328 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
2329 /* Return if found. */
2330 if (sctx
->dcc_stats
[i
].tex
== tex
) {
2331 sctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2335 /* Record the first seen empty slot. */
2336 if (empty_slot
== -1 && !sctx
->dcc_stats
[i
].tex
)
2340 /* Not found. Remove the oldest member to make space in the array. */
2341 if (empty_slot
== -1) {
2342 int oldest_slot
= 0;
2344 /* Find the oldest slot. */
2345 for (i
= 1; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2346 if (sctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2347 sctx
->dcc_stats
[i
].last_use_timestamp
)
2350 /* Clean up the oldest slot. */
2351 vi_dcc_clean_up_context_slot(sctx
, oldest_slot
);
2352 empty_slot
= oldest_slot
;
2355 /* Add the texture to the new slot. */
2356 si_texture_reference(&sctx
->dcc_stats
[empty_slot
].tex
, tex
);
2357 sctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2361 static struct pipe_query
*
2362 vi_create_resuming_pipestats_query(struct si_context
*sctx
)
2364 struct si_query_hw
*query
= (struct si_query_hw
*)
2365 sctx
->b
.create_query(&sctx
->b
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2367 query
->flags
|= SI_QUERY_HW_FLAG_BEGIN_RESUMES
;
2368 return (struct pipe_query
*)query
;
2372 * Called when binding a color buffer.
2374 void vi_separate_dcc_start_query(struct si_context
*sctx
,
2375 struct si_texture
*tex
)
2377 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2379 assert(!sctx
->dcc_stats
[i
].query_active
);
2381 if (!sctx
->dcc_stats
[i
].ps_stats
[0])
2382 sctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(sctx
);
2384 /* begin or resume the query */
2385 sctx
->b
.begin_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2386 sctx
->dcc_stats
[i
].query_active
= true;
2390 * Called when unbinding a color buffer.
2392 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
2393 struct si_texture
*tex
)
2395 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2397 assert(sctx
->dcc_stats
[i
].query_active
);
2398 assert(sctx
->dcc_stats
[i
].ps_stats
[0]);
2400 /* pause or end the query */
2401 sctx
->b
.end_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2402 sctx
->dcc_stats
[i
].query_active
= false;
2405 static bool vi_should_enable_separate_dcc(struct si_texture
*tex
)
2407 /* The minimum number of fullscreen draws per frame that is required
2409 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2412 /* Called by fast clear. */
2413 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
2414 struct si_texture
*tex
)
2416 /* The intent is to use this with shared displayable back buffers,
2417 * but it's not strictly limited only to them.
2419 if (!tex
->buffer
.b
.is_shared
||
2420 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2421 tex
->buffer
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2422 tex
->buffer
.b
.b
.last_level
> 0 ||
2423 !tex
->surface
.dcc_size
||
2424 sctx
->screen
->debug_flags
& DBG(NO_DCC
) ||
2425 sctx
->screen
->debug_flags
& DBG(NO_DCC_FB
))
2428 assert(sctx
->chip_class
>= GFX8
);
2430 if (tex
->dcc_offset
)
2431 return; /* already enabled */
2433 /* Enable the DCC stat gathering. */
2434 if (!tex
->dcc_gather_statistics
) {
2435 tex
->dcc_gather_statistics
= true;
2436 vi_separate_dcc_start_query(sctx
, tex
);
2439 if (!vi_should_enable_separate_dcc(tex
))
2440 return; /* stats show that DCC decompression is too expensive */
2442 assert(tex
->surface
.num_dcc_levels
);
2443 assert(!tex
->dcc_separate_buffer
);
2445 si_texture_discard_cmask(sctx
->screen
, tex
);
2447 /* Get a DCC buffer. */
2448 if (tex
->last_dcc_separate_buffer
) {
2449 assert(tex
->dcc_gather_statistics
);
2450 assert(!tex
->dcc_separate_buffer
);
2451 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2452 tex
->last_dcc_separate_buffer
= NULL
;
2454 tex
->dcc_separate_buffer
=
2455 si_aligned_buffer_create(sctx
->b
.screen
,
2456 SI_RESOURCE_FLAG_UNMAPPABLE
,
2458 tex
->surface
.dcc_size
,
2459 tex
->surface
.dcc_alignment
);
2460 if (!tex
->dcc_separate_buffer
)
2464 /* dcc_offset is the absolute GPUVM address. */
2465 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2467 /* no need to flag anything since this is called by fast clear that
2468 * flags framebuffer state
2473 * Called by pipe_context::flush_resource, the place where DCC decompression
2476 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2477 struct si_texture
*tex
)
2479 struct si_context
*sctx
= (struct si_context
*)ctx
;
2480 struct pipe_query
*tmp
;
2481 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2482 bool query_active
= sctx
->dcc_stats
[i
].query_active
;
2483 bool disable
= false;
2485 if (sctx
->dcc_stats
[i
].ps_stats
[2]) {
2486 union pipe_query_result result
;
2488 /* Read the results. */
2489 struct pipe_query
*query
= sctx
->dcc_stats
[i
].ps_stats
[2];
2490 ctx
->get_query_result(ctx
, query
,
2492 si_query_buffer_reset(sctx
, &((struct si_query_hw
*)query
)->buffer
);
2494 /* Compute the approximate number of fullscreen draws. */
2495 tex
->ps_draw_ratio
=
2496 result
.pipeline_statistics
.ps_invocations
/
2497 (tex
->buffer
.b
.b
.width0
* tex
->buffer
.b
.b
.height0
);
2498 sctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2500 disable
= tex
->dcc_separate_buffer
&&
2501 !vi_should_enable_separate_dcc(tex
);
2504 tex
->num_slow_clears
= 0;
2506 /* stop the statistics query for ps_stats[0] */
2508 vi_separate_dcc_stop_query(sctx
, tex
);
2510 /* Move the queries in the queue by one. */
2511 tmp
= sctx
->dcc_stats
[i
].ps_stats
[2];
2512 sctx
->dcc_stats
[i
].ps_stats
[2] = sctx
->dcc_stats
[i
].ps_stats
[1];
2513 sctx
->dcc_stats
[i
].ps_stats
[1] = sctx
->dcc_stats
[i
].ps_stats
[0];
2514 sctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2516 /* create and start a new query as ps_stats[0] */
2518 vi_separate_dcc_start_query(sctx
, tex
);
2521 assert(!tex
->last_dcc_separate_buffer
);
2522 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2523 tex
->dcc_separate_buffer
= NULL
;
2524 tex
->dcc_offset
= 0;
2525 /* no need to flag anything since this is called after
2526 * decompression that re-sets framebuffer state
2531 static struct pipe_memory_object
*
2532 si_memobj_from_handle(struct pipe_screen
*screen
,
2533 struct winsys_handle
*whandle
,
2536 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2537 struct si_memory_object
*memobj
= CALLOC_STRUCT(si_memory_object
);
2538 struct pb_buffer
*buf
= NULL
;
2539 uint32_t stride
, offset
;
2544 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
2545 sscreen
->info
.max_alignment
,
2552 memobj
->b
.dedicated
= dedicated
;
2554 memobj
->stride
= stride
;
2556 return (struct pipe_memory_object
*)memobj
;
2561 si_memobj_destroy(struct pipe_screen
*screen
,
2562 struct pipe_memory_object
*_memobj
)
2564 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2566 pb_reference(&memobj
->buf
, NULL
);
2570 static struct pipe_resource
*
2571 si_texture_from_memobj(struct pipe_screen
*screen
,
2572 const struct pipe_resource
*templ
,
2573 struct pipe_memory_object
*_memobj
,
2576 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2577 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2578 struct pipe_resource
*tex
=
2579 si_texture_from_winsys_buffer(sscreen
, templ
, memobj
->buf
,
2580 memobj
->stride
, offset
,
2581 PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
|
2582 PIPE_HANDLE_USAGE_SHADER_WRITE
,
2583 memobj
->b
.dedicated
);
2587 /* si_texture_from_winsys_buffer doesn't increment refcount of
2588 * memobj->buf, so increment it here.
2590 struct pb_buffer
*buf
= NULL
;
2591 pb_reference(&buf
, memobj
->buf
);
2595 static bool si_check_resource_capability(struct pipe_screen
*screen
,
2596 struct pipe_resource
*resource
,
2599 struct si_texture
*tex
= (struct si_texture
*)resource
;
2601 /* Buffers only support the linear flag. */
2602 if (resource
->target
== PIPE_BUFFER
)
2603 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2605 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2608 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2611 /* TODO: PIPE_BIND_CURSOR - do we care? */
2615 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2617 sscreen
->b
.resource_from_handle
= si_texture_from_handle
;
2618 sscreen
->b
.resource_get_handle
= si_texture_get_handle
;
2619 sscreen
->b
.resource_get_info
= si_texture_get_info
;
2620 sscreen
->b
.resource_from_memobj
= si_texture_from_memobj
;
2621 sscreen
->b
.memobj_create_from_handle
= si_memobj_from_handle
;
2622 sscreen
->b
.memobj_destroy
= si_memobj_destroy
;
2623 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2626 void si_init_context_texture_functions(struct si_context
*sctx
)
2628 sctx
->b
.create_surface
= si_create_surface
;
2629 sctx
->b
.surface_destroy
= si_surface_destroy
;