2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeonsi/si_pipe.h"
27 #include "radeonsi/si_query.h"
28 #include "util/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/u_resource.h"
33 #include "util/u_surface.h"
34 #include "util/u_transfer.h"
35 #include "util/os_time.h"
38 #include "state_tracker/drm_driver.h"
39 #include "amd/common/sid.h"
41 static enum radeon_surf_mode
42 si_choose_tiling(struct si_screen
*sscreen
,
43 const struct pipe_resource
*templ
, bool tc_compatible_htile
);
46 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
47 struct r600_texture
*rdst
,
48 unsigned dst_level
, unsigned dstx
,
49 unsigned dsty
, unsigned dstz
,
50 struct r600_texture
*rsrc
,
52 const struct pipe_box
*src_box
)
57 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
60 /* MSAA: Blits don't exist in the real world. */
61 if (rsrc
->buffer
.b
.b
.nr_samples
> 1 ||
62 rdst
->buffer
.b
.b
.nr_samples
> 1)
65 /* Depth-stencil surfaces:
66 * When dst is linear, the DB->CB copy preserves HTILE.
67 * When dst is tiled, the 3D path must be used to update HTILE.
69 if (rsrc
->is_depth
|| rdst
->is_depth
)
73 * src: Use the 3D path. DCC decompression is expensive.
74 * dst: Use the 3D path to compress the pixels with DCC.
76 if (vi_dcc_enabled(rsrc
, src_level
) ||
77 vi_dcc_enabled(rdst
, dst_level
))
81 * src: Both texture and SDMA paths need decompression. Use SDMA.
82 * dst: If overwriting the whole texture, discard CMASK and use
83 * SDMA. Otherwise, use the 3D path.
85 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
86 /* The CMASK clear is only enabled for the first level. */
87 assert(dst_level
== 0);
88 if (!util_texrange_covers_whole_level(&rdst
->buffer
.b
.b
, dst_level
,
89 dstx
, dsty
, dstz
, src_box
->width
,
90 src_box
->height
, src_box
->depth
))
93 si_texture_discard_cmask(sctx
->screen
, rdst
);
96 /* All requirements are met. Prepare textures for SDMA. */
97 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
98 sctx
->b
.flush_resource(&sctx
->b
, &rsrc
->buffer
.b
.b
);
100 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
101 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
106 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
107 static void si_copy_region_with_blit(struct pipe_context
*pipe
,
108 struct pipe_resource
*dst
,
110 unsigned dstx
, unsigned dsty
, unsigned dstz
,
111 struct pipe_resource
*src
,
113 const struct pipe_box
*src_box
)
115 struct pipe_blit_info blit
;
117 memset(&blit
, 0, sizeof(blit
));
118 blit
.src
.resource
= src
;
119 blit
.src
.format
= src
->format
;
120 blit
.src
.level
= src_level
;
121 blit
.src
.box
= *src_box
;
122 blit
.dst
.resource
= dst
;
123 blit
.dst
.format
= dst
->format
;
124 blit
.dst
.level
= dst_level
;
125 blit
.dst
.box
.x
= dstx
;
126 blit
.dst
.box
.y
= dsty
;
127 blit
.dst
.box
.z
= dstz
;
128 blit
.dst
.box
.width
= src_box
->width
;
129 blit
.dst
.box
.height
= src_box
->height
;
130 blit
.dst
.box
.depth
= src_box
->depth
;
131 blit
.mask
= util_format_get_mask(src
->format
) &
132 util_format_get_mask(dst
->format
);
133 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
136 pipe
->blit(pipe
, &blit
);
140 /* Copy from a full GPU texture to a transfer's staging one. */
141 static void si_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
143 struct si_context
*sctx
= (struct si_context
*)ctx
;
144 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
145 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
146 struct pipe_resource
*src
= transfer
->resource
;
148 if (src
->nr_samples
> 1) {
149 si_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
150 src
, transfer
->level
, &transfer
->box
);
154 sctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
158 /* Copy from a transfer's staging texture to a full GPU one. */
159 static void si_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
161 struct si_context
*sctx
= (struct si_context
*)ctx
;
162 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
163 struct pipe_resource
*dst
= transfer
->resource
;
164 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
165 struct pipe_box sbox
;
167 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
169 if (dst
->nr_samples
> 1) {
170 si_copy_region_with_blit(ctx
, dst
, transfer
->level
,
171 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
176 sctx
->dma_copy(ctx
, dst
, transfer
->level
,
177 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
181 static unsigned si_texture_get_offset(struct si_screen
*sscreen
,
182 struct r600_texture
*rtex
, unsigned level
,
183 const struct pipe_box
*box
,
185 unsigned *layer_stride
)
187 if (sscreen
->info
.chip_class
>= GFX9
) {
188 *stride
= rtex
->surface
.u
.gfx9
.surf_pitch
* rtex
->surface
.bpe
;
189 *layer_stride
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
194 /* Each texture is an array of slices. Each slice is an array
195 * of mipmap levels. */
196 return box
->z
* rtex
->surface
.u
.gfx9
.surf_slice_size
+
197 rtex
->surface
.u
.gfx9
.offset
[level
] +
198 (box
->y
/ rtex
->surface
.blk_h
*
199 rtex
->surface
.u
.gfx9
.surf_pitch
+
200 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
202 *stride
= rtex
->surface
.u
.legacy
.level
[level
].nblk_x
*
204 assert((uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
205 *layer_stride
= (uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
208 return rtex
->surface
.u
.legacy
.level
[level
].offset
;
210 /* Each texture is an array of mipmap levels. Each level is
211 * an array of slices. */
212 return rtex
->surface
.u
.legacy
.level
[level
].offset
+
213 box
->z
* (uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
214 (box
->y
/ rtex
->surface
.blk_h
*
215 rtex
->surface
.u
.legacy
.level
[level
].nblk_x
+
216 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
220 static int si_init_surface(struct si_screen
*sscreen
,
221 struct radeon_surf
*surface
,
222 const struct pipe_resource
*ptex
,
223 unsigned num_color_samples
,
224 enum radeon_surf_mode array_mode
,
225 unsigned pitch_in_bytes_override
,
229 bool is_flushed_depth
,
230 bool tc_compatible_htile
)
232 const struct util_format_description
*desc
=
233 util_format_description(ptex
->format
);
234 bool is_depth
, is_stencil
;
236 unsigned i
, bpe
, flags
= 0;
238 is_depth
= util_format_has_depth(desc
);
239 is_stencil
= util_format_has_stencil(desc
);
241 if (!is_flushed_depth
&&
242 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
243 bpe
= 4; /* stencil is allocated separately on evergreen */
245 bpe
= util_format_get_blocksize(ptex
->format
);
246 assert(util_is_power_of_two_or_zero(bpe
));
249 if (!is_flushed_depth
&& is_depth
) {
250 flags
|= RADEON_SURF_ZBUFFER
;
252 if (tc_compatible_htile
&&
253 (sscreen
->info
.chip_class
>= GFX9
||
254 array_mode
== RADEON_SURF_MODE_2D
)) {
255 /* TC-compatible HTILE only supports Z32_FLOAT.
256 * GFX9 also supports Z16_UNORM.
257 * On VI, promote Z16 to Z32. DB->CB copies will convert
258 * the format for transfers.
260 if (sscreen
->info
.chip_class
== VI
)
263 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
267 flags
|= RADEON_SURF_SBUFFER
;
270 if (sscreen
->info
.chip_class
>= VI
&&
271 (ptex
->flags
& SI_RESOURCE_FLAG_DISABLE_DCC
||
272 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
273 (ptex
->nr_samples
>= 2 && !sscreen
->dcc_msaa_allowed
)))
274 flags
|= RADEON_SURF_DISABLE_DCC
;
276 /* VI: DCC clear for 4x and 8x MSAA array textures unimplemented. */
277 if (sscreen
->info
.chip_class
== VI
&&
278 num_color_samples
>= 4 &&
279 ptex
->array_size
> 1)
280 flags
|= RADEON_SURF_DISABLE_DCC
;
282 /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
283 if (sscreen
->info
.chip_class
>= GFX9
&&
284 num_color_samples
>= 4)
285 flags
|= RADEON_SURF_DISABLE_DCC
;
287 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
288 /* This should catch bugs in gallium users setting incorrect flags. */
289 assert(ptex
->nr_samples
<= 1 &&
290 ptex
->array_size
== 1 &&
292 ptex
->last_level
== 0 &&
293 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
295 flags
|= RADEON_SURF_SCANOUT
;
298 if (ptex
->bind
& PIPE_BIND_SHARED
)
299 flags
|= RADEON_SURF_SHAREABLE
;
301 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
302 if (!(ptex
->flags
& SI_RESOURCE_FLAG_FORCE_TILING
))
303 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
305 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, num_color_samples
,
306 flags
, bpe
, array_mode
, surface
);
311 unsigned pitch
= pitch_in_bytes_override
/ bpe
;
313 if (sscreen
->info
.chip_class
>= GFX9
) {
315 surface
->u
.gfx9
.surf_pitch
= pitch
;
316 surface
->u
.gfx9
.surf_slice_size
=
317 (uint64_t)pitch
* surface
->u
.gfx9
.surf_height
* bpe
;
319 surface
->u
.gfx9
.surf_offset
= offset
;
322 surface
->u
.legacy
.level
[0].nblk_x
= pitch
;
323 surface
->u
.legacy
.level
[0].slice_size_dw
=
324 ((uint64_t)pitch
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
327 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
328 surface
->u
.legacy
.level
[i
].offset
+= offset
;
334 static void si_texture_init_metadata(struct si_screen
*sscreen
,
335 struct r600_texture
*rtex
,
336 struct radeon_bo_metadata
*metadata
)
338 struct radeon_surf
*surface
= &rtex
->surface
;
340 memset(metadata
, 0, sizeof(*metadata
));
342 if (sscreen
->info
.chip_class
>= GFX9
) {
343 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
345 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
346 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
347 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
348 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
349 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
350 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
351 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
352 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
353 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
354 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
355 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
356 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
360 static void si_surface_import_metadata(struct si_screen
*sscreen
,
361 struct radeon_surf
*surf
,
362 struct radeon_bo_metadata
*metadata
,
363 enum radeon_surf_mode
*array_mode
,
366 if (sscreen
->info
.chip_class
>= GFX9
) {
367 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
368 *array_mode
= RADEON_SURF_MODE_2D
;
370 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
372 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
373 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
375 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
377 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
378 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
379 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
380 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
381 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
382 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
384 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
385 *array_mode
= RADEON_SURF_MODE_2D
;
386 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
387 *array_mode
= RADEON_SURF_MODE_1D
;
389 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
391 *is_scanout
= metadata
->u
.legacy
.scanout
;
395 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
396 struct r600_texture
*rtex
)
398 struct si_screen
*sscreen
= sctx
->screen
;
399 struct pipe_context
*ctx
= &sctx
->b
;
401 if (ctx
== sscreen
->aux_context
)
402 mtx_lock(&sscreen
->aux_context_lock
);
404 unsigned n
= sctx
->num_decompress_calls
;
405 ctx
->flush_resource(ctx
, &rtex
->buffer
.b
.b
);
407 /* Flush only if any fast clear elimination took place. */
408 if (n
!= sctx
->num_decompress_calls
)
409 ctx
->flush(ctx
, NULL
, 0);
411 if (ctx
== sscreen
->aux_context
)
412 mtx_unlock(&sscreen
->aux_context_lock
);
415 void si_texture_discard_cmask(struct si_screen
*sscreen
,
416 struct r600_texture
*rtex
)
418 if (!rtex
->cmask
.size
)
421 assert(rtex
->buffer
.b
.b
.nr_samples
<= 1);
424 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
425 rtex
->cmask
.base_address_reg
= rtex
->buffer
.gpu_address
>> 8;
426 rtex
->dirty_level_mask
= 0;
428 rtex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
430 if (rtex
->cmask_buffer
!= &rtex
->buffer
)
431 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
433 /* Notify all contexts about the change. */
434 p_atomic_inc(&sscreen
->dirty_tex_counter
);
435 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
438 static bool si_can_disable_dcc(struct r600_texture
*rtex
)
440 /* We can't disable DCC if it can be written by another process. */
441 return rtex
->dcc_offset
&&
442 (!rtex
->buffer
.b
.is_shared
||
443 !(rtex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
446 static bool si_texture_discard_dcc(struct si_screen
*sscreen
,
447 struct r600_texture
*rtex
)
449 if (!si_can_disable_dcc(rtex
))
452 assert(rtex
->dcc_separate_buffer
== NULL
);
455 rtex
->dcc_offset
= 0;
457 /* Notify all contexts about the change. */
458 p_atomic_inc(&sscreen
->dirty_tex_counter
);
463 * Disable DCC for the texture. (first decompress, then discard metadata).
465 * There is unresolved multi-context synchronization issue between
466 * screen::aux_context and the current context. If applications do this with
467 * multiple contexts, it's already undefined behavior for them and we don't
468 * have to worry about that. The scenario is:
470 * If context 1 disables DCC and context 2 has queued commands that write
471 * to the texture via CB with DCC enabled, and the order of operations is
473 * context 2 queues draw calls rendering to the texture, but doesn't flush
474 * context 1 disables DCC and flushes
475 * context 1 & 2 reset descriptors and FB state
476 * context 2 flushes (new compressed tiles written by the draw calls)
477 * context 1 & 2 read garbage, because DCC is disabled, yet there are
480 * \param sctx the current context if you have one, or rscreen->aux_context
483 bool si_texture_disable_dcc(struct si_context
*sctx
,
484 struct r600_texture
*rtex
)
486 struct si_screen
*sscreen
= sctx
->screen
;
488 if (!si_can_disable_dcc(rtex
))
491 if (&sctx
->b
== sscreen
->aux_context
)
492 mtx_lock(&sscreen
->aux_context_lock
);
494 /* Decompress DCC. */
495 si_decompress_dcc(sctx
, rtex
);
496 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
498 if (&sctx
->b
== sscreen
->aux_context
)
499 mtx_unlock(&sscreen
->aux_context_lock
);
501 return si_texture_discard_dcc(sscreen
, rtex
);
504 static void si_reallocate_texture_inplace(struct si_context
*sctx
,
505 struct r600_texture
*rtex
,
506 unsigned new_bind_flag
,
507 bool invalidate_storage
)
509 struct pipe_screen
*screen
= sctx
->b
.screen
;
510 struct r600_texture
*new_tex
;
511 struct pipe_resource templ
= rtex
->buffer
.b
.b
;
514 templ
.bind
|= new_bind_flag
;
516 if (rtex
->buffer
.b
.is_shared
)
519 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
520 if (rtex
->surface
.is_linear
)
523 /* This fails with MSAA, depth, and compressed textures. */
524 if (si_choose_tiling(sctx
->screen
, &templ
, false) !=
525 RADEON_SURF_MODE_LINEAR_ALIGNED
)
529 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
533 /* Copy the pixels to the new texture. */
534 if (!invalidate_storage
) {
535 for (i
= 0; i
<= templ
.last_level
; i
++) {
539 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
540 util_num_layers(&templ
, i
), &box
);
542 sctx
->dma_copy(&sctx
->b
, &new_tex
->buffer
.b
.b
, i
, 0, 0, 0,
543 &rtex
->buffer
.b
.b
, i
, &box
);
547 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
548 si_texture_discard_cmask(sctx
->screen
, rtex
);
549 si_texture_discard_dcc(sctx
->screen
, rtex
);
552 /* Replace the structure fields of rtex. */
553 rtex
->buffer
.b
.b
.bind
= templ
.bind
;
554 pb_reference(&rtex
->buffer
.buf
, new_tex
->buffer
.buf
);
555 rtex
->buffer
.gpu_address
= new_tex
->buffer
.gpu_address
;
556 rtex
->buffer
.vram_usage
= new_tex
->buffer
.vram_usage
;
557 rtex
->buffer
.gart_usage
= new_tex
->buffer
.gart_usage
;
558 rtex
->buffer
.bo_size
= new_tex
->buffer
.bo_size
;
559 rtex
->buffer
.bo_alignment
= new_tex
->buffer
.bo_alignment
;
560 rtex
->buffer
.domains
= new_tex
->buffer
.domains
;
561 rtex
->buffer
.flags
= new_tex
->buffer
.flags
;
562 rtex
->size
= new_tex
->size
;
563 rtex
->db_render_format
= new_tex
->db_render_format
;
564 rtex
->db_compatible
= new_tex
->db_compatible
;
565 rtex
->can_sample_z
= new_tex
->can_sample_z
;
566 rtex
->can_sample_s
= new_tex
->can_sample_s
;
567 rtex
->surface
= new_tex
->surface
;
568 rtex
->fmask_offset
= new_tex
->fmask_offset
;
569 rtex
->cmask
= new_tex
->cmask
;
570 rtex
->cb_color_info
= new_tex
->cb_color_info
;
571 rtex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
572 rtex
->htile_offset
= new_tex
->htile_offset
;
573 rtex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
574 rtex
->depth_cleared
= new_tex
->depth_cleared
;
575 rtex
->stencil_cleared
= new_tex
->stencil_cleared
;
576 rtex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
577 rtex
->framebuffers_bound
= new_tex
->framebuffers_bound
;
579 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
580 assert(!rtex
->htile_offset
);
581 assert(!rtex
->cmask
.size
);
582 assert(!rtex
->surface
.fmask_size
);
583 assert(!rtex
->dcc_offset
);
584 assert(!rtex
->is_depth
);
587 r600_texture_reference(&new_tex
, NULL
);
589 p_atomic_inc(&sctx
->screen
->dirty_tex_counter
);
592 static uint32_t si_get_bo_metadata_word1(struct si_screen
*sscreen
)
594 return (ATI_VENDOR_ID
<< 16) | sscreen
->info
.pci_id
;
597 static void si_query_opaque_metadata(struct si_screen
*sscreen
,
598 struct r600_texture
*rtex
,
599 struct radeon_bo_metadata
*md
)
601 struct pipe_resource
*res
= &rtex
->buffer
.b
.b
;
602 static const unsigned char swizzle
[] = {
609 bool is_array
= util_texture_is_array(res
->target
);
611 /* DRM 2.x.x doesn't support this. */
612 if (sscreen
->info
.drm_major
!= 3)
615 assert(rtex
->dcc_separate_buffer
== NULL
);
616 assert(rtex
->surface
.fmask_size
== 0);
618 /* Metadata image format format version 1:
619 * [0] = 1 (metadata format identifier)
620 * [1] = (VENDOR_ID << 16) | PCI_ID
621 * [2:9] = image descriptor for the whole resource
622 * [2] is always 0, because the base address is cleared
623 * [9] is the DCC offset bits [39:8] from the beginning of
625 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
628 md
->metadata
[0] = 1; /* metadata image format version 1 */
630 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
631 md
->metadata
[1] = si_get_bo_metadata_word1(sscreen
);
633 si_make_texture_descriptor(sscreen
, rtex
, true,
634 res
->target
, res
->format
,
635 swizzle
, 0, res
->last_level
, 0,
636 is_array
? res
->array_size
- 1 : 0,
637 res
->width0
, res
->height0
, res
->depth0
,
640 si_set_mutable_tex_desc_fields(sscreen
, rtex
, &rtex
->surface
.u
.legacy
.level
[0],
641 0, 0, rtex
->surface
.blk_w
, false, desc
);
643 /* Clear the base address and set the relative DCC offset. */
645 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
646 desc
[7] = rtex
->dcc_offset
>> 8;
648 /* Dwords [2:9] contain the image descriptor. */
649 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
650 md
->size_metadata
= 10 * 4;
652 /* Dwords [10:..] contain the mipmap level offsets. */
653 if (sscreen
->info
.chip_class
<= VI
) {
654 for (i
= 0; i
<= res
->last_level
; i
++)
655 md
->metadata
[10+i
] = rtex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
657 md
->size_metadata
+= (1 + res
->last_level
) * 4;
661 static void si_apply_opaque_metadata(struct si_screen
*sscreen
,
662 struct r600_texture
*rtex
,
663 struct radeon_bo_metadata
*md
)
665 uint32_t *desc
= &md
->metadata
[2];
667 if (sscreen
->info
.chip_class
< VI
)
670 /* Return if DCC is enabled. The texture should be set up with it
673 if (md
->size_metadata
>= 10 * 4 && /* at least 2(header) + 8(desc) dwords */
674 md
->metadata
[0] != 0 &&
675 md
->metadata
[1] == si_get_bo_metadata_word1(sscreen
) &&
676 G_008F28_COMPRESSION_EN(desc
[6])) {
677 rtex
->dcc_offset
= (uint64_t)desc
[7] << 8;
681 /* Disable DCC. These are always set by texture_from_handle and must
684 rtex
->dcc_offset
= 0;
687 static boolean
si_texture_get_handle(struct pipe_screen
* screen
,
688 struct pipe_context
*ctx
,
689 struct pipe_resource
*resource
,
690 struct winsys_handle
*whandle
,
693 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
694 struct si_context
*sctx
;
695 struct r600_resource
*res
= r600_resource(resource
);
696 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
697 struct radeon_bo_metadata metadata
;
698 bool update_metadata
= false;
699 unsigned stride
, offset
, slice_size
;
702 ctx
= threaded_context_unwrap_sync(ctx
);
703 sctx
= (struct si_context
*)(ctx
? ctx
: sscreen
->aux_context
);
705 if (resource
->target
!= PIPE_BUFFER
) {
706 /* This is not supported now, but it might be required for OpenCL
707 * interop in the future.
709 if (resource
->nr_samples
> 1 || rtex
->is_depth
)
712 /* Move a suballocated texture into a non-suballocated allocation. */
713 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
714 rtex
->surface
.tile_swizzle
||
715 (rtex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
716 sscreen
->info
.has_local_buffers
&&
717 whandle
->type
!= DRM_API_HANDLE_TYPE_KMS
)) {
718 assert(!res
->b
.is_shared
);
719 si_reallocate_texture_inplace(sctx
, rtex
,
720 PIPE_BIND_SHARED
, false);
722 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
723 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
724 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
725 assert(rtex
->surface
.tile_swizzle
== 0);
728 /* Since shader image stores don't support DCC on VI,
729 * disable it for external clients that want write
732 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
733 if (si_texture_disable_dcc(sctx
, rtex
)) {
734 update_metadata
= true;
735 /* si_texture_disable_dcc flushes the context */
740 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
741 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
742 /* Eliminate fast clear (both CMASK and DCC) */
743 si_eliminate_fast_color_clear(sctx
, rtex
);
744 /* eliminate_fast_color_clear flushes the context */
747 /* Disable CMASK if flush_resource isn't going
750 if (rtex
->cmask
.size
)
751 si_texture_discard_cmask(sscreen
, rtex
);
755 if (!res
->b
.is_shared
|| update_metadata
) {
756 si_texture_init_metadata(sscreen
, rtex
, &metadata
);
757 si_query_opaque_metadata(sscreen
, rtex
, &metadata
);
759 sscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
762 if (sscreen
->info
.chip_class
>= GFX9
) {
763 offset
= rtex
->surface
.u
.gfx9
.surf_offset
;
764 stride
= rtex
->surface
.u
.gfx9
.surf_pitch
*
766 slice_size
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
768 offset
= rtex
->surface
.u
.legacy
.level
[0].offset
;
769 stride
= rtex
->surface
.u
.legacy
.level
[0].nblk_x
*
771 slice_size
= (uint64_t)rtex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
774 /* Buffer exports are for the OpenCL interop. */
775 /* Move a suballocated buffer into a non-suballocated allocation. */
776 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
777 /* A DMABUF export always fails if the BO is local. */
778 (rtex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
779 sscreen
->info
.has_local_buffers
)) {
780 assert(!res
->b
.is_shared
);
782 /* Allocate a new buffer with PIPE_BIND_SHARED. */
783 struct pipe_resource templ
= res
->b
.b
;
784 templ
.bind
|= PIPE_BIND_SHARED
;
786 struct pipe_resource
*newb
=
787 screen
->resource_create(screen
, &templ
);
791 /* Copy the old buffer contents to the new one. */
793 u_box_1d(0, newb
->width0
, &box
);
794 sctx
->b
.resource_copy_region(&sctx
->b
, newb
, 0, 0, 0, 0,
797 /* Move the new buffer storage to the old pipe_resource. */
798 si_replace_buffer_storage(&sctx
->b
, &res
->b
.b
, newb
);
799 pipe_resource_reference(&newb
, NULL
);
801 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
802 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
812 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
814 if (res
->b
.is_shared
) {
815 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
818 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
819 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
820 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
822 res
->b
.is_shared
= true;
823 res
->external_usage
= usage
;
826 return sscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
827 slice_size
, whandle
);
830 static void si_texture_destroy(struct pipe_screen
*screen
,
831 struct pipe_resource
*ptex
)
833 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
834 struct r600_resource
*resource
= &rtex
->buffer
;
836 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
838 if (rtex
->cmask_buffer
!= &rtex
->buffer
) {
839 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
841 pb_reference(&resource
->buf
, NULL
);
842 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
843 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
847 static const struct u_resource_vtbl si_texture_vtbl
;
849 void si_texture_get_cmask_info(struct si_screen
*sscreen
,
850 struct r600_texture
*rtex
,
851 struct r600_cmask_info
*out
)
853 unsigned pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
854 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
855 unsigned cl_width
, cl_height
;
857 if (sscreen
->info
.chip_class
>= GFX9
) {
858 out
->alignment
= rtex
->surface
.u
.gfx9
.cmask_alignment
;
859 out
->size
= rtex
->surface
.u
.gfx9
.cmask_size
;
876 case 16: /* Hawaii */
885 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
887 unsigned width
= align(rtex
->buffer
.b
.b
.width0
, cl_width
*8);
888 unsigned height
= align(rtex
->buffer
.b
.b
.height0
, cl_height
*8);
889 unsigned slice_elements
= (width
* height
) / (8*8);
891 /* Each element of CMASK is a nibble. */
892 unsigned slice_bytes
= slice_elements
/ 2;
894 out
->slice_tile_max
= (width
* height
) / (128*128);
895 if (out
->slice_tile_max
)
896 out
->slice_tile_max
-= 1;
898 out
->alignment
= MAX2(256, base_align
);
899 out
->size
= util_num_layers(&rtex
->buffer
.b
.b
, 0) *
900 align(slice_bytes
, base_align
);
903 static void si_texture_allocate_cmask(struct si_screen
*sscreen
,
904 struct r600_texture
*rtex
)
906 si_texture_get_cmask_info(sscreen
, rtex
, &rtex
->cmask
);
908 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
909 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
911 rtex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
914 static void si_texture_get_htile_size(struct si_screen
*sscreen
,
915 struct r600_texture
*rtex
)
917 unsigned cl_width
, cl_height
, width
, height
;
918 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
919 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
921 assert(sscreen
->info
.chip_class
<= VI
);
923 rtex
->surface
.htile_size
= 0;
925 /* HTILE is broken with 1D tiling on old kernels and CIK. */
926 if (sscreen
->info
.chip_class
>= CIK
&&
927 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
928 sscreen
->info
.drm_major
== 2 && sscreen
->info
.drm_minor
< 38)
931 /* Overalign HTILE on P2 configs to work around GPU hangs in
932 * piglit/depthstencil-render-miplevels 585.
934 * This has been confirmed to help Kabini & Stoney, where the hangs
935 * are always reproducible. I think I have seen the test hang
936 * on Carrizo too, though it was very rare there.
938 if (sscreen
->info
.chip_class
>= CIK
&& num_pipes
< 4)
967 width
= align(rtex
->buffer
.b
.b
.width0
, cl_width
* 8);
968 height
= align(rtex
->buffer
.b
.b
.height0
, cl_height
* 8);
970 slice_elements
= (width
* height
) / (8 * 8);
971 slice_bytes
= slice_elements
* 4;
973 pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
974 base_align
= num_pipes
* pipe_interleave_bytes
;
976 rtex
->surface
.htile_alignment
= base_align
;
977 rtex
->surface
.htile_size
=
978 util_num_layers(&rtex
->buffer
.b
.b
, 0) *
979 align(slice_bytes
, base_align
);
982 static void si_texture_allocate_htile(struct si_screen
*sscreen
,
983 struct r600_texture
*rtex
)
985 if (sscreen
->info
.chip_class
<= VI
&& !rtex
->tc_compatible_htile
)
986 si_texture_get_htile_size(sscreen
, rtex
);
988 if (!rtex
->surface
.htile_size
)
991 rtex
->htile_offset
= align(rtex
->size
, rtex
->surface
.htile_alignment
);
992 rtex
->size
= rtex
->htile_offset
+ rtex
->surface
.htile_size
;
995 void si_print_texture_info(struct si_screen
*sscreen
,
996 struct r600_texture
*rtex
, struct u_log_context
*log
)
1000 /* Common parameters. */
1001 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
1002 "blk_h=%u, array_size=%u, last_level=%u, "
1003 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
1004 rtex
->buffer
.b
.b
.width0
, rtex
->buffer
.b
.b
.height0
,
1005 rtex
->buffer
.b
.b
.depth0
, rtex
->surface
.blk_w
,
1006 rtex
->surface
.blk_h
,
1007 rtex
->buffer
.b
.b
.array_size
, rtex
->buffer
.b
.b
.last_level
,
1008 rtex
->surface
.bpe
, rtex
->buffer
.b
.b
.nr_samples
,
1009 rtex
->surface
.flags
, util_format_short_name(rtex
->buffer
.b
.b
.format
));
1011 if (sscreen
->info
.chip_class
>= GFX9
) {
1012 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
1013 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
1014 rtex
->surface
.surf_size
,
1015 rtex
->surface
.u
.gfx9
.surf_slice_size
,
1016 rtex
->surface
.surf_alignment
,
1017 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
1018 rtex
->surface
.u
.gfx9
.surf
.epitch
,
1019 rtex
->surface
.u
.gfx9
.surf_pitch
);
1021 if (rtex
->surface
.fmask_size
) {
1022 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
1023 "alignment=%u, swmode=%u, epitch=%u\n",
1025 rtex
->surface
.fmask_size
,
1026 rtex
->surface
.fmask_alignment
,
1027 rtex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1028 rtex
->surface
.u
.gfx9
.fmask
.epitch
);
1031 if (rtex
->cmask
.size
) {
1032 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", "
1033 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1035 rtex
->surface
.u
.gfx9
.cmask_size
,
1036 rtex
->surface
.u
.gfx9
.cmask_alignment
,
1037 rtex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1038 rtex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1041 if (rtex
->htile_offset
) {
1042 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, alignment=%u, "
1043 "rb_aligned=%u, pipe_aligned=%u\n",
1045 rtex
->surface
.htile_size
,
1046 rtex
->surface
.htile_alignment
,
1047 rtex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1048 rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1051 if (rtex
->dcc_offset
) {
1052 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, "
1053 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1054 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1055 rtex
->surface
.dcc_alignment
,
1056 rtex
->surface
.u
.gfx9
.dcc_pitch_max
,
1057 rtex
->surface
.num_dcc_levels
);
1060 if (rtex
->surface
.u
.gfx9
.stencil_offset
) {
1061 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1062 rtex
->surface
.u
.gfx9
.stencil_offset
,
1063 rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1064 rtex
->surface
.u
.gfx9
.stencil
.epitch
);
1069 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1070 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1071 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.u
.legacy
.bankw
,
1072 rtex
->surface
.u
.legacy
.bankh
, rtex
->surface
.u
.legacy
.num_banks
, rtex
->surface
.u
.legacy
.mtilea
,
1073 rtex
->surface
.u
.legacy
.tile_split
, rtex
->surface
.u
.legacy
.pipe_config
,
1074 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1076 if (rtex
->surface
.fmask_size
)
1077 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1078 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1079 rtex
->fmask_offset
, rtex
->surface
.fmask_size
, rtex
->surface
.fmask_alignment
,
1080 rtex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
,
1081 rtex
->surface
.u
.legacy
.fmask
.bankh
,
1082 rtex
->surface
.u
.legacy
.fmask
.slice_tile_max
,
1083 rtex
->surface
.u
.legacy
.fmask
.tiling_index
);
1085 if (rtex
->cmask
.size
)
1086 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1087 "slice_tile_max=%u\n",
1088 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
1089 rtex
->cmask
.slice_tile_max
);
1091 if (rtex
->htile_offset
)
1092 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, "
1093 "alignment=%u, TC_compatible = %u\n",
1094 rtex
->htile_offset
, rtex
->surface
.htile_size
,
1095 rtex
->surface
.htile_alignment
,
1096 rtex
->tc_compatible_htile
);
1098 if (rtex
->dcc_offset
) {
1099 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, alignment=%u\n",
1100 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1101 rtex
->surface
.dcc_alignment
);
1102 for (i
= 0; i
<= rtex
->buffer
.b
.b
.last_level
; i
++)
1103 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%u, "
1104 "fast_clear_size=%u\n",
1105 i
, i
< rtex
->surface
.num_dcc_levels
,
1106 rtex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1107 rtex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1110 for (i
= 0; i
<= rtex
->buffer
.b
.b
.last_level
; i
++)
1111 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1112 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1113 "mode=%u, tiling_index = %u\n",
1114 i
, rtex
->surface
.u
.legacy
.level
[i
].offset
,
1115 (uint64_t)rtex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
1116 u_minify(rtex
->buffer
.b
.b
.width0
, i
),
1117 u_minify(rtex
->buffer
.b
.b
.height0
, i
),
1118 u_minify(rtex
->buffer
.b
.b
.depth0
, i
),
1119 rtex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1120 rtex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1121 rtex
->surface
.u
.legacy
.level
[i
].mode
,
1122 rtex
->surface
.u
.legacy
.tiling_index
[i
]);
1124 if (rtex
->surface
.has_stencil
) {
1125 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1126 rtex
->surface
.u
.legacy
.stencil_tile_split
);
1127 for (i
= 0; i
<= rtex
->buffer
.b
.b
.last_level
; i
++) {
1128 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1129 "slice_size=%"PRIu64
", npix_x=%u, "
1130 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1131 "mode=%u, tiling_index = %u\n",
1132 i
, rtex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1133 (uint64_t)rtex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
1134 u_minify(rtex
->buffer
.b
.b
.width0
, i
),
1135 u_minify(rtex
->buffer
.b
.b
.height0
, i
),
1136 u_minify(rtex
->buffer
.b
.b
.depth0
, i
),
1137 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1138 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1139 rtex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1140 rtex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1145 /* Common processing for r600_texture_create and r600_texture_from_handle */
1146 static struct r600_texture
*
1147 si_texture_create_object(struct pipe_screen
*screen
,
1148 const struct pipe_resource
*base
,
1149 unsigned num_color_samples
,
1150 struct pb_buffer
*buf
,
1151 struct radeon_surf
*surface
)
1153 struct r600_texture
*rtex
;
1154 struct r600_resource
*resource
;
1155 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1157 rtex
= CALLOC_STRUCT(r600_texture
);
1161 resource
= &rtex
->buffer
;
1162 resource
->b
.b
= *base
;
1163 resource
->b
.b
.next
= NULL
;
1164 resource
->b
.vtbl
= &si_texture_vtbl
;
1165 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1166 resource
->b
.b
.screen
= screen
;
1168 /* don't include stencil-only formats which we don't support for rendering */
1169 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->buffer
.b
.b
.format
));
1171 rtex
->surface
= *surface
;
1172 rtex
->size
= rtex
->surface
.surf_size
;
1173 rtex
->num_color_samples
= num_color_samples
;
1175 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0 &&
1176 (rtex
->surface
.flags
&
1177 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1179 /* TC-compatible HTILE:
1180 * - VI only supports Z32_FLOAT.
1181 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1182 if (rtex
->tc_compatible_htile
) {
1183 if (sscreen
->info
.chip_class
>= GFX9
&&
1184 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1185 rtex
->db_render_format
= base
->format
;
1187 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1188 rtex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1189 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1192 rtex
->db_render_format
= base
->format
;
1195 /* Applies to GCN. */
1196 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1198 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1199 * between frames, so the only thing that can enable separate DCC
1200 * with DRI2 is multiple slow clears within a frame.
1202 rtex
->ps_draw_ratio
= 0;
1204 if (rtex
->is_depth
) {
1205 if (sscreen
->info
.chip_class
>= GFX9
) {
1206 rtex
->can_sample_z
= true;
1207 rtex
->can_sample_s
= true;
1209 rtex
->can_sample_z
= !rtex
->surface
.u
.legacy
.depth_adjusted
;
1210 rtex
->can_sample_s
= !rtex
->surface
.u
.legacy
.stencil_adjusted
;
1213 if (!(base
->flags
& (SI_RESOURCE_FLAG_TRANSFER
|
1214 SI_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1215 rtex
->db_compatible
= true;
1217 if (!(sscreen
->debug_flags
& DBG(NO_HYPERZ
)))
1218 si_texture_allocate_htile(sscreen
, rtex
);
1221 if (base
->nr_samples
> 1 &&
1223 !(sscreen
->debug_flags
& DBG(NO_FMASK
))) {
1224 /* Allocate FMASK. */
1225 rtex
->fmask_offset
= align64(rtex
->size
,
1226 rtex
->surface
.fmask_alignment
);
1227 rtex
->size
= rtex
->fmask_offset
+ rtex
->surface
.fmask_size
;
1229 si_texture_allocate_cmask(sscreen
, rtex
);
1230 rtex
->cmask_buffer
= &rtex
->buffer
;
1232 if (!rtex
->surface
.fmask_size
|| !rtex
->cmask
.size
) {
1238 /* Shared textures must always set up DCC here.
1239 * If it's not present, it will be disabled by
1240 * apply_opaque_metadata later.
1242 if (rtex
->surface
.dcc_size
&&
1243 (buf
|| !(sscreen
->debug_flags
& DBG(NO_DCC
))) &&
1244 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1245 /* Reserve space for the DCC buffer. */
1246 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1247 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1251 /* Now create the backing buffer. */
1253 si_init_resource_fields(sscreen
, resource
, rtex
->size
,
1254 rtex
->surface
.surf_alignment
);
1256 if (!si_alloc_resource(sscreen
, resource
)) {
1261 resource
->buf
= buf
;
1262 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1263 resource
->bo_size
= buf
->size
;
1264 resource
->bo_alignment
= buf
->alignment
;
1265 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1266 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1267 resource
->vram_usage
= buf
->size
;
1268 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1269 resource
->gart_usage
= buf
->size
;
1272 if (rtex
->cmask
.size
) {
1273 /* Initialize the cmask to 0xCC (= compressed state). */
1274 si_screen_clear_buffer(sscreen
, &rtex
->cmask_buffer
->b
.b
,
1275 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1278 if (rtex
->htile_offset
) {
1279 uint32_t clear_value
= 0;
1281 if (sscreen
->info
.chip_class
>= GFX9
|| rtex
->tc_compatible_htile
)
1282 clear_value
= 0x0000030F;
1284 si_screen_clear_buffer(sscreen
, &rtex
->buffer
.b
.b
,
1286 rtex
->surface
.htile_size
,
1290 /* Initialize DCC only if the texture is not being imported. */
1291 if (!buf
&& rtex
->dcc_offset
) {
1292 si_screen_clear_buffer(sscreen
, &rtex
->buffer
.b
.b
,
1294 rtex
->surface
.dcc_size
,
1298 /* Initialize the CMASK base register value. */
1299 rtex
->cmask
.base_address_reg
=
1300 (rtex
->buffer
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1302 if (sscreen
->debug_flags
& DBG(VM
)) {
1303 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1304 rtex
->buffer
.gpu_address
,
1305 rtex
->buffer
.gpu_address
+ rtex
->buffer
.buf
->size
,
1306 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+1,
1307 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1310 if (sscreen
->debug_flags
& DBG(TEX
)) {
1312 struct u_log_context log
;
1313 u_log_context_init(&log
);
1314 si_print_texture_info(sscreen
, rtex
, &log
);
1315 u_log_new_page_print(&log
, stdout
);
1317 u_log_context_destroy(&log
);
1323 static enum radeon_surf_mode
1324 si_choose_tiling(struct si_screen
*sscreen
,
1325 const struct pipe_resource
*templ
, bool tc_compatible_htile
)
1327 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1328 bool force_tiling
= templ
->flags
& SI_RESOURCE_FLAG_FORCE_TILING
;
1329 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1330 !(templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
);
1332 /* MSAA resources must be 2D tiled. */
1333 if (templ
->nr_samples
> 1)
1334 return RADEON_SURF_MODE_2D
;
1336 /* Transfer resources should be linear. */
1337 if (templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
)
1338 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1340 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
1341 * which requires 2D tiling.
1343 if (sscreen
->info
.chip_class
== VI
&& tc_compatible_htile
)
1344 return RADEON_SURF_MODE_2D
;
1346 /* Handle common candidates for the linear mode.
1347 * Compressed textures and DB surfaces must always be tiled.
1349 if (!force_tiling
&&
1350 !is_depth_stencil
&&
1351 !util_format_is_compressed(templ
->format
)) {
1352 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1353 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1355 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. */
1356 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1357 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1359 /* Cursors are linear on SI.
1360 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1361 if (templ
->bind
& PIPE_BIND_CURSOR
)
1362 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1364 if (templ
->bind
& PIPE_BIND_LINEAR
)
1365 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1367 /* Textures with a very small height are recommended to be linear. */
1368 if (templ
->target
== PIPE_TEXTURE_1D
||
1369 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1370 /* Only very thin and long 2D textures should benefit from
1371 * linear_aligned. */
1372 (templ
->width0
> 8 && templ
->height0
<= 2))
1373 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1375 /* Textures likely to be mapped often. */
1376 if (templ
->usage
== PIPE_USAGE_STAGING
||
1377 templ
->usage
== PIPE_USAGE_STREAM
)
1378 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1381 /* Make small textures 1D tiled. */
1382 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1383 (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1384 return RADEON_SURF_MODE_1D
;
1386 /* The allocator will switch to 1D if needed. */
1387 return RADEON_SURF_MODE_2D
;
1390 static unsigned si_get_num_color_samples(struct si_screen
*sscreen
,
1391 const struct pipe_resource
*templ
,
1394 if (!imported
&& templ
->nr_samples
>= 2 &&
1395 sscreen
->eqaa_force_color_samples
)
1396 return sscreen
->eqaa_force_color_samples
;
1398 return CLAMP(templ
->nr_samples
, 1, 8);
1401 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1402 const struct pipe_resource
*templ
)
1404 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1405 bool is_zs
= util_format_is_depth_or_stencil(templ
->format
);
1407 if (templ
->nr_samples
>= 2) {
1408 /* This is hackish (overwriting the const pipe_resource template),
1409 * but should be harmless and state trackers can also see
1410 * the overriden number of samples in the created pipe_resource.
1412 if (is_zs
&& sscreen
->eqaa_force_z_samples
) {
1413 ((struct pipe_resource
*)templ
)->nr_samples
=
1414 sscreen
->eqaa_force_z_samples
;
1415 } else if (!is_zs
&& sscreen
->eqaa_force_color_samples
) {
1416 ((struct pipe_resource
*)templ
)->nr_samples
=
1417 sscreen
->eqaa_force_coverage_samples
;
1421 struct radeon_surf surface
= {0};
1422 bool is_flushed_depth
= templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1423 bool tc_compatible_htile
=
1424 sscreen
->info
.chip_class
>= VI
&&
1425 /* There are issues with TC-compatible HTILE on Tonga (and
1426 * Iceland is the same design), and documented bug workarounds
1427 * don't help. For example, this fails:
1428 * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow -auto
1430 sscreen
->info
.family
!= CHIP_TONGA
&&
1431 sscreen
->info
.family
!= CHIP_ICELAND
&&
1432 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1433 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) &&
1434 !is_flushed_depth
&&
1435 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1437 unsigned num_color_samples
= si_get_num_color_samples(sscreen
, templ
, false);
1440 r
= si_init_surface(sscreen
, &surface
, templ
, num_color_samples
,
1441 si_choose_tiling(sscreen
, templ
, tc_compatible_htile
),
1442 0, 0, false, false, is_flushed_depth
,
1443 tc_compatible_htile
);
1448 return (struct pipe_resource
*)
1449 si_texture_create_object(screen
, templ
, num_color_samples
,
1453 static struct pipe_resource
*si_texture_from_handle(struct pipe_screen
*screen
,
1454 const struct pipe_resource
*templ
,
1455 struct winsys_handle
*whandle
,
1458 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1459 struct pb_buffer
*buf
= NULL
;
1460 unsigned stride
= 0, offset
= 0;
1461 enum radeon_surf_mode array_mode
;
1462 struct radeon_surf surface
= {};
1464 struct radeon_bo_metadata metadata
= {};
1465 struct r600_texture
*rtex
;
1468 /* Support only 2D textures without mipmaps */
1469 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1470 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1473 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
, &stride
, &offset
);
1477 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1478 si_surface_import_metadata(sscreen
, &surface
, &metadata
,
1479 &array_mode
, &is_scanout
);
1481 unsigned num_color_samples
= si_get_num_color_samples(sscreen
, templ
, true);
1483 r
= si_init_surface(sscreen
, &surface
, templ
, num_color_samples
,
1484 array_mode
, stride
, offset
, true, is_scanout
,
1490 rtex
= si_texture_create_object(screen
, templ
, num_color_samples
,
1495 rtex
->buffer
.b
.is_shared
= true;
1496 rtex
->buffer
.external_usage
= usage
;
1498 si_apply_opaque_metadata(sscreen
, rtex
, &metadata
);
1500 assert(rtex
->surface
.tile_swizzle
== 0);
1501 return &rtex
->buffer
.b
.b
;
1504 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1505 struct pipe_resource
*texture
,
1506 struct r600_texture
**staging
)
1508 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1509 struct pipe_resource resource
;
1510 struct r600_texture
**flushed_depth_texture
= staging
?
1511 staging
: &rtex
->flushed_depth_texture
;
1512 enum pipe_format pipe_format
= texture
->format
;
1515 if (rtex
->flushed_depth_texture
)
1516 return true; /* it's ready */
1518 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1519 switch (pipe_format
) {
1520 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1521 /* Save memory by not allocating the S plane. */
1522 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1524 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1525 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1526 /* Save memory bandwidth by not copying the
1527 * stencil part during flush.
1529 * This potentially increases memory bandwidth
1530 * if an application uses both Z and S texturing
1531 * simultaneously (a flushed Z24S8 texture
1532 * would be stored compactly), but how often
1533 * does that really happen?
1535 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1539 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1540 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1542 /* DB->CB copies to an 8bpp surface don't work. */
1543 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1547 memset(&resource
, 0, sizeof(resource
));
1548 resource
.target
= texture
->target
;
1549 resource
.format
= pipe_format
;
1550 resource
.width0
= texture
->width0
;
1551 resource
.height0
= texture
->height0
;
1552 resource
.depth0
= texture
->depth0
;
1553 resource
.array_size
= texture
->array_size
;
1554 resource
.last_level
= texture
->last_level
;
1555 resource
.nr_samples
= texture
->nr_samples
;
1556 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1557 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1558 resource
.flags
= texture
->flags
| SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1561 resource
.flags
|= SI_RESOURCE_FLAG_TRANSFER
;
1563 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1564 if (*flushed_depth_texture
== NULL
) {
1565 PRINT_ERR("failed to create temporary texture to hold flushed depth\n");
1572 * Initialize the pipe_resource descriptor to be of the same size as the box,
1573 * which is supposed to hold a subregion of the texture "orig" at the given
1576 static void si_init_temp_resource_from_box(struct pipe_resource
*res
,
1577 struct pipe_resource
*orig
,
1578 const struct pipe_box
*box
,
1579 unsigned level
, unsigned flags
)
1581 memset(res
, 0, sizeof(*res
));
1582 res
->format
= orig
->format
;
1583 res
->width0
= box
->width
;
1584 res
->height0
= box
->height
;
1586 res
->array_size
= 1;
1587 res
->usage
= flags
& SI_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1590 /* We must set the correct texture target and dimensions for a 3D box. */
1591 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1592 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1593 res
->array_size
= box
->depth
;
1595 res
->target
= PIPE_TEXTURE_2D
;
1599 static bool si_can_invalidate_texture(struct si_screen
*sscreen
,
1600 struct r600_texture
*rtex
,
1601 unsigned transfer_usage
,
1602 const struct pipe_box
*box
)
1604 return !rtex
->buffer
.b
.is_shared
&&
1605 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1606 rtex
->buffer
.b
.b
.last_level
== 0 &&
1607 util_texrange_covers_whole_level(&rtex
->buffer
.b
.b
, 0,
1608 box
->x
, box
->y
, box
->z
,
1609 box
->width
, box
->height
,
1613 static void si_texture_invalidate_storage(struct si_context
*sctx
,
1614 struct r600_texture
*rtex
)
1616 struct si_screen
*sscreen
= sctx
->screen
;
1618 /* There is no point in discarding depth and tiled buffers. */
1619 assert(!rtex
->is_depth
);
1620 assert(rtex
->surface
.is_linear
);
1622 /* Reallocate the buffer in the same pipe_resource. */
1623 si_alloc_resource(sscreen
, &rtex
->buffer
);
1625 /* Initialize the CMASK base address (needed even without CMASK). */
1626 rtex
->cmask
.base_address_reg
=
1627 (rtex
->buffer
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1629 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1631 sctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1634 static void *si_texture_transfer_map(struct pipe_context
*ctx
,
1635 struct pipe_resource
*texture
,
1638 const struct pipe_box
*box
,
1639 struct pipe_transfer
**ptransfer
)
1641 struct si_context
*sctx
= (struct si_context
*)ctx
;
1642 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1643 struct r600_transfer
*trans
;
1644 struct r600_resource
*buf
;
1645 unsigned offset
= 0;
1647 bool use_staging_texture
= false;
1649 assert(!(texture
->flags
& SI_RESOURCE_FLAG_TRANSFER
));
1650 assert(box
->width
&& box
->height
&& box
->depth
);
1652 /* Depth textures use staging unconditionally. */
1653 if (!rtex
->is_depth
) {
1654 /* Degrade the tile mode if we get too many transfers on APUs.
1655 * On dGPUs, the staging texture is always faster.
1656 * Only count uploads that are at least 4x4 pixels large.
1658 if (!sctx
->screen
->info
.has_dedicated_vram
&&
1660 box
->width
>= 4 && box
->height
>= 4 &&
1661 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1662 bool can_invalidate
=
1663 si_can_invalidate_texture(sctx
->screen
, rtex
,
1666 si_reallocate_texture_inplace(sctx
, rtex
,
1671 /* Tiled textures need to be converted into a linear texture for CPU
1672 * access. The staging texture is always linear and is placed in GART.
1674 * Reading from VRAM or GTT WC is slow, always use the staging
1675 * texture in this case.
1677 * Use the staging texture for uploads if the underlying BO
1680 if (!rtex
->surface
.is_linear
)
1681 use_staging_texture
= true;
1682 else if (usage
& PIPE_TRANSFER_READ
)
1683 use_staging_texture
=
1684 rtex
->buffer
.domains
& RADEON_DOMAIN_VRAM
||
1685 rtex
->buffer
.flags
& RADEON_FLAG_GTT_WC
;
1686 /* Write & linear only: */
1687 else if (si_rings_is_buffer_referenced(sctx
, rtex
->buffer
.buf
,
1688 RADEON_USAGE_READWRITE
) ||
1689 !sctx
->ws
->buffer_wait(rtex
->buffer
.buf
, 0,
1690 RADEON_USAGE_READWRITE
)) {
1692 if (si_can_invalidate_texture(sctx
->screen
, rtex
,
1694 si_texture_invalidate_storage(sctx
, rtex
);
1696 use_staging_texture
= true;
1700 trans
= CALLOC_STRUCT(r600_transfer
);
1703 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1704 trans
->b
.b
.level
= level
;
1705 trans
->b
.b
.usage
= usage
;
1706 trans
->b
.b
.box
= *box
;
1708 if (rtex
->is_depth
) {
1709 struct r600_texture
*staging_depth
;
1711 if (rtex
->buffer
.b
.b
.nr_samples
> 1) {
1712 /* MSAA depth buffers need to be converted to single sample buffers.
1714 * Mapping MSAA depth buffers can occur if ReadPixels is called
1715 * with a multisample GLX visual.
1717 * First downsample the depth buffer to a temporary texture,
1718 * then decompress the temporary one to staging.
1720 * Only the region being mapped is transfered.
1722 struct pipe_resource resource
;
1724 si_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1726 if (!si_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1727 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1731 if (usage
& PIPE_TRANSFER_READ
) {
1732 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1734 PRINT_ERR("failed to create a temporary depth texture\n");
1738 si_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1739 si_blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1740 0, 0, 0, box
->depth
, 0, 0);
1741 pipe_resource_reference(&temp
, NULL
);
1744 /* Just get the strides. */
1745 si_texture_get_offset(sctx
->screen
, staging_depth
, level
, NULL
,
1747 &trans
->b
.b
.layer_stride
);
1749 /* XXX: only readback the rectangle which is being mapped? */
1750 /* XXX: when discard is true, no need to read back from depth texture */
1751 if (!si_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1752 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1756 si_blit_decompress_depth(ctx
, rtex
, staging_depth
,
1758 box
->z
, box
->z
+ box
->depth
- 1,
1761 offset
= si_texture_get_offset(sctx
->screen
, staging_depth
,
1764 &trans
->b
.b
.layer_stride
);
1767 trans
->staging
= &staging_depth
->buffer
;
1768 buf
= trans
->staging
;
1769 } else if (use_staging_texture
) {
1770 struct pipe_resource resource
;
1771 struct r600_texture
*staging
;
1773 si_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1774 SI_RESOURCE_FLAG_TRANSFER
);
1775 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1776 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1778 /* Create the temporary texture. */
1779 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1781 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1784 trans
->staging
= &staging
->buffer
;
1786 /* Just get the strides. */
1787 si_texture_get_offset(sctx
->screen
, staging
, 0, NULL
,
1789 &trans
->b
.b
.layer_stride
);
1791 if (usage
& PIPE_TRANSFER_READ
)
1792 si_copy_to_staging_texture(ctx
, trans
);
1794 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1796 buf
= trans
->staging
;
1798 /* the resource is mapped directly */
1799 offset
= si_texture_get_offset(sctx
->screen
, rtex
, level
, box
,
1801 &trans
->b
.b
.layer_stride
);
1802 buf
= &rtex
->buffer
;
1805 if (!(map
= si_buffer_map_sync_with_rings(sctx
, buf
, usage
)))
1808 *ptransfer
= &trans
->b
.b
;
1809 return map
+ offset
;
1812 r600_resource_reference(&trans
->staging
, NULL
);
1813 pipe_resource_reference(&trans
->b
.b
.resource
, NULL
);
1818 static void si_texture_transfer_unmap(struct pipe_context
*ctx
,
1819 struct pipe_transfer
* transfer
)
1821 struct si_context
*sctx
= (struct si_context
*)ctx
;
1822 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1823 struct pipe_resource
*texture
= transfer
->resource
;
1824 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1826 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1827 if (rtex
->is_depth
&& rtex
->buffer
.b
.b
.nr_samples
<= 1) {
1828 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1829 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1830 &rtransfer
->staging
->b
.b
, transfer
->level
,
1833 si_copy_from_staging_texture(ctx
, rtransfer
);
1837 if (rtransfer
->staging
) {
1838 sctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1839 r600_resource_reference(&rtransfer
->staging
, NULL
);
1842 /* Heuristic for {upload, draw, upload, draw, ..}:
1844 * Flush the gfx IB if we've allocated too much texture storage.
1846 * The idea is that we don't want to build IBs that use too much
1847 * memory and put pressure on the kernel memory manager and we also
1848 * want to make temporary and invalidated buffers go idle ASAP to
1849 * decrease the total memory usage or make them reusable. The memory
1850 * usage will be slightly higher than given here because of the buffer
1851 * cache in the winsys.
1853 * The result is that the kernel memory manager is never a bottleneck.
1855 if (sctx
->num_alloc_tex_transfer_bytes
> sctx
->screen
->info
.gart_size
/ 4) {
1856 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1857 sctx
->num_alloc_tex_transfer_bytes
= 0;
1860 pipe_resource_reference(&transfer
->resource
, NULL
);
1864 static const struct u_resource_vtbl si_texture_vtbl
=
1866 NULL
, /* get_handle */
1867 si_texture_destroy
, /* resource_destroy */
1868 si_texture_transfer_map
, /* transfer_map */
1869 u_default_transfer_flush_region
, /* transfer_flush_region */
1870 si_texture_transfer_unmap
, /* transfer_unmap */
1873 /* Return if it's allowed to reinterpret one format as another with DCC enabled.
1875 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1876 enum pipe_format format2
)
1878 const struct util_format_description
*desc1
, *desc2
;
1880 /* No format change - exit early. */
1881 if (format1
== format2
)
1884 format1
= si_simplify_cb_format(format1
);
1885 format2
= si_simplify_cb_format(format2
);
1887 /* Check again after format adjustments. */
1888 if (format1
== format2
)
1891 desc1
= util_format_description(format1
);
1892 desc2
= util_format_description(format2
);
1894 if (desc1
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
1895 desc2
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1898 /* Float and non-float are totally incompatible. */
1899 if ((desc1
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
) !=
1900 (desc2
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
))
1903 /* Channel sizes must match across DCC formats.
1904 * Comparing just the first 2 channels should be enough.
1906 if (desc1
->channel
[0].size
!= desc2
->channel
[0].size
||
1907 (desc1
->nr_channels
>= 2 &&
1908 desc1
->channel
[1].size
!= desc2
->channel
[1].size
))
1911 /* Everything below is not needed if the driver never uses the DCC
1912 * clear code with the value of 1.
1915 /* If the clear values are all 1 or all 0, this constraint can be
1917 if (vi_alpha_is_on_msb(format1
) != vi_alpha_is_on_msb(format2
))
1920 /* Channel types must match if the clear value of 1 is used.
1921 * The type categories are only float, signed, unsigned.
1922 * NORM and INT are always compatible.
1924 if (desc1
->channel
[0].type
!= desc2
->channel
[0].type
||
1925 (desc1
->nr_channels
>= 2 &&
1926 desc1
->channel
[1].type
!= desc2
->channel
[1].type
))
1932 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1934 enum pipe_format view_format
)
1936 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1938 return vi_dcc_enabled(rtex
, level
) &&
1939 !vi_dcc_formats_compatible(tex
->format
, view_format
);
1942 /* This can't be merged with the above function, because
1943 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
1944 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
1945 struct pipe_resource
*tex
,
1947 enum pipe_format view_format
)
1949 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1951 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
1952 if (!si_texture_disable_dcc(sctx
, (struct r600_texture
*)tex
))
1953 si_decompress_dcc(sctx
, rtex
);
1956 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1957 struct pipe_resource
*texture
,
1958 const struct pipe_surface
*templ
,
1959 unsigned width0
, unsigned height0
,
1960 unsigned width
, unsigned height
)
1962 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1967 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1968 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1970 pipe_reference_init(&surface
->base
.reference
, 1);
1971 pipe_resource_reference(&surface
->base
.texture
, texture
);
1972 surface
->base
.context
= pipe
;
1973 surface
->base
.format
= templ
->format
;
1974 surface
->base
.width
= width
;
1975 surface
->base
.height
= height
;
1976 surface
->base
.u
= templ
->u
;
1978 surface
->width0
= width0
;
1979 surface
->height0
= height0
;
1981 surface
->dcc_incompatible
=
1982 texture
->target
!= PIPE_BUFFER
&&
1983 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
1985 return &surface
->base
;
1988 static struct pipe_surface
*si_create_surface(struct pipe_context
*pipe
,
1989 struct pipe_resource
*tex
,
1990 const struct pipe_surface
*templ
)
1992 unsigned level
= templ
->u
.tex
.level
;
1993 unsigned width
= u_minify(tex
->width0
, level
);
1994 unsigned height
= u_minify(tex
->height0
, level
);
1995 unsigned width0
= tex
->width0
;
1996 unsigned height0
= tex
->height0
;
1998 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1999 const struct util_format_description
*tex_desc
2000 = util_format_description(tex
->format
);
2001 const struct util_format_description
*templ_desc
2002 = util_format_description(templ
->format
);
2004 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2006 /* Adjust size of surface if and only if the block width or
2007 * height is changed. */
2008 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2009 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2010 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2011 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2013 width
= nblks_x
* templ_desc
->block
.width
;
2014 height
= nblks_y
* templ_desc
->block
.height
;
2016 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2017 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2021 return si_create_surface_custom(pipe
, tex
, templ
,
2026 static void si_surface_destroy(struct pipe_context
*pipe
,
2027 struct pipe_surface
*surface
)
2029 pipe_resource_reference(&surface
->texture
, NULL
);
2033 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2035 const struct util_format_description
*desc
= util_format_description(format
);
2037 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2039 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2040 return V_028C70_SWAP_STD
;
2042 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2045 switch (desc
->nr_channels
) {
2047 if (HAS_SWIZZLE(0,X
))
2048 return V_028C70_SWAP_STD
; /* X___ */
2049 else if (HAS_SWIZZLE(3,X
))
2050 return V_028C70_SWAP_ALT_REV
; /* ___X */
2053 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2054 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2055 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2056 return V_028C70_SWAP_STD
; /* XY__ */
2057 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2058 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2059 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2061 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2062 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2063 return V_028C70_SWAP_ALT
; /* X__Y */
2064 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2065 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2068 if (HAS_SWIZZLE(0,X
))
2069 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2070 else if (HAS_SWIZZLE(0,Z
))
2071 return V_028C70_SWAP_STD_REV
; /* ZYX */
2074 /* check the middle channels, the 1st and 4th channel can be NONE */
2075 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2076 return V_028C70_SWAP_STD
; /* XYZW */
2077 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2078 return V_028C70_SWAP_STD_REV
; /* WZYX */
2079 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2080 return V_028C70_SWAP_ALT
; /* ZYXW */
2081 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2084 return V_028C70_SWAP_ALT_REV
;
2086 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2093 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2095 static void vi_dcc_clean_up_context_slot(struct si_context
*sctx
,
2100 if (sctx
->dcc_stats
[slot
].query_active
)
2101 vi_separate_dcc_stop_query(sctx
,
2102 sctx
->dcc_stats
[slot
].tex
);
2104 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
[slot
].ps_stats
); i
++)
2105 if (sctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2106 sctx
->b
.destroy_query(&sctx
->b
,
2107 sctx
->dcc_stats
[slot
].ps_stats
[i
]);
2108 sctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2111 r600_texture_reference(&sctx
->dcc_stats
[slot
].tex
, NULL
);
2115 * Return the per-context slot where DCC statistics queries for the texture live.
2117 static unsigned vi_get_context_dcc_stats_index(struct si_context
*sctx
,
2118 struct r600_texture
*tex
)
2120 int i
, empty_slot
= -1;
2122 /* Remove zombie textures (textures kept alive by this array only). */
2123 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2124 if (sctx
->dcc_stats
[i
].tex
&&
2125 sctx
->dcc_stats
[i
].tex
->buffer
.b
.b
.reference
.count
== 1)
2126 vi_dcc_clean_up_context_slot(sctx
, i
);
2128 /* Find the texture. */
2129 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
2130 /* Return if found. */
2131 if (sctx
->dcc_stats
[i
].tex
== tex
) {
2132 sctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2136 /* Record the first seen empty slot. */
2137 if (empty_slot
== -1 && !sctx
->dcc_stats
[i
].tex
)
2141 /* Not found. Remove the oldest member to make space in the array. */
2142 if (empty_slot
== -1) {
2143 int oldest_slot
= 0;
2145 /* Find the oldest slot. */
2146 for (i
= 1; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2147 if (sctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2148 sctx
->dcc_stats
[i
].last_use_timestamp
)
2151 /* Clean up the oldest slot. */
2152 vi_dcc_clean_up_context_slot(sctx
, oldest_slot
);
2153 empty_slot
= oldest_slot
;
2156 /* Add the texture to the new slot. */
2157 r600_texture_reference(&sctx
->dcc_stats
[empty_slot
].tex
, tex
);
2158 sctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2162 static struct pipe_query
*
2163 vi_create_resuming_pipestats_query(struct si_context
*sctx
)
2165 struct si_query_hw
*query
= (struct si_query_hw
*)
2166 sctx
->b
.create_query(&sctx
->b
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2168 query
->flags
|= SI_QUERY_HW_FLAG_BEGIN_RESUMES
;
2169 return (struct pipe_query
*)query
;
2173 * Called when binding a color buffer.
2175 void vi_separate_dcc_start_query(struct si_context
*sctx
,
2176 struct r600_texture
*tex
)
2178 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2180 assert(!sctx
->dcc_stats
[i
].query_active
);
2182 if (!sctx
->dcc_stats
[i
].ps_stats
[0])
2183 sctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(sctx
);
2185 /* begin or resume the query */
2186 sctx
->b
.begin_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2187 sctx
->dcc_stats
[i
].query_active
= true;
2191 * Called when unbinding a color buffer.
2193 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
2194 struct r600_texture
*tex
)
2196 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2198 assert(sctx
->dcc_stats
[i
].query_active
);
2199 assert(sctx
->dcc_stats
[i
].ps_stats
[0]);
2201 /* pause or end the query */
2202 sctx
->b
.end_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2203 sctx
->dcc_stats
[i
].query_active
= false;
2206 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2208 /* The minimum number of fullscreen draws per frame that is required
2210 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2213 /* Called by fast clear. */
2214 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
2215 struct r600_texture
*tex
)
2217 /* The intent is to use this with shared displayable back buffers,
2218 * but it's not strictly limited only to them.
2220 if (!tex
->buffer
.b
.is_shared
||
2221 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2222 tex
->buffer
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2223 tex
->buffer
.b
.b
.last_level
> 0 ||
2224 !tex
->surface
.dcc_size
)
2227 if (tex
->dcc_offset
)
2228 return; /* already enabled */
2230 /* Enable the DCC stat gathering. */
2231 if (!tex
->dcc_gather_statistics
) {
2232 tex
->dcc_gather_statistics
= true;
2233 vi_separate_dcc_start_query(sctx
, tex
);
2236 if (!vi_should_enable_separate_dcc(tex
))
2237 return; /* stats show that DCC decompression is too expensive */
2239 assert(tex
->surface
.num_dcc_levels
);
2240 assert(!tex
->dcc_separate_buffer
);
2242 si_texture_discard_cmask(sctx
->screen
, tex
);
2244 /* Get a DCC buffer. */
2245 if (tex
->last_dcc_separate_buffer
) {
2246 assert(tex
->dcc_gather_statistics
);
2247 assert(!tex
->dcc_separate_buffer
);
2248 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2249 tex
->last_dcc_separate_buffer
= NULL
;
2251 tex
->dcc_separate_buffer
=
2252 si_aligned_buffer_create(sctx
->b
.screen
,
2253 SI_RESOURCE_FLAG_UNMAPPABLE
,
2255 tex
->surface
.dcc_size
,
2256 tex
->surface
.dcc_alignment
);
2257 if (!tex
->dcc_separate_buffer
)
2261 /* dcc_offset is the absolute GPUVM address. */
2262 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2264 /* no need to flag anything since this is called by fast clear that
2265 * flags framebuffer state
2270 * Called by pipe_context::flush_resource, the place where DCC decompression
2273 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2274 struct r600_texture
*tex
)
2276 struct si_context
*sctx
= (struct si_context
*)ctx
;
2277 struct pipe_query
*tmp
;
2278 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2279 bool query_active
= sctx
->dcc_stats
[i
].query_active
;
2280 bool disable
= false;
2282 if (sctx
->dcc_stats
[i
].ps_stats
[2]) {
2283 union pipe_query_result result
;
2285 /* Read the results. */
2286 ctx
->get_query_result(ctx
, sctx
->dcc_stats
[i
].ps_stats
[2],
2288 si_query_hw_reset_buffers(sctx
,
2289 (struct si_query_hw
*)
2290 sctx
->dcc_stats
[i
].ps_stats
[2]);
2292 /* Compute the approximate number of fullscreen draws. */
2293 tex
->ps_draw_ratio
=
2294 result
.pipeline_statistics
.ps_invocations
/
2295 (tex
->buffer
.b
.b
.width0
* tex
->buffer
.b
.b
.height0
);
2296 sctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2298 disable
= tex
->dcc_separate_buffer
&&
2299 !vi_should_enable_separate_dcc(tex
);
2302 tex
->num_slow_clears
= 0;
2304 /* stop the statistics query for ps_stats[0] */
2306 vi_separate_dcc_stop_query(sctx
, tex
);
2308 /* Move the queries in the queue by one. */
2309 tmp
= sctx
->dcc_stats
[i
].ps_stats
[2];
2310 sctx
->dcc_stats
[i
].ps_stats
[2] = sctx
->dcc_stats
[i
].ps_stats
[1];
2311 sctx
->dcc_stats
[i
].ps_stats
[1] = sctx
->dcc_stats
[i
].ps_stats
[0];
2312 sctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2314 /* create and start a new query as ps_stats[0] */
2316 vi_separate_dcc_start_query(sctx
, tex
);
2319 assert(!tex
->last_dcc_separate_buffer
);
2320 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2321 tex
->dcc_separate_buffer
= NULL
;
2322 tex
->dcc_offset
= 0;
2323 /* no need to flag anything since this is called after
2324 * decompression that re-sets framebuffer state
2329 static struct pipe_memory_object
*
2330 si_memobj_from_handle(struct pipe_screen
*screen
,
2331 struct winsys_handle
*whandle
,
2334 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2335 struct r600_memory_object
*memobj
= CALLOC_STRUCT(r600_memory_object
);
2336 struct pb_buffer
*buf
= NULL
;
2337 uint32_t stride
, offset
;
2342 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
2349 memobj
->b
.dedicated
= dedicated
;
2351 memobj
->stride
= stride
;
2352 memobj
->offset
= offset
;
2354 return (struct pipe_memory_object
*)memobj
;
2359 si_memobj_destroy(struct pipe_screen
*screen
,
2360 struct pipe_memory_object
*_memobj
)
2362 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2364 pb_reference(&memobj
->buf
, NULL
);
2368 static struct pipe_resource
*
2369 si_texture_from_memobj(struct pipe_screen
*screen
,
2370 const struct pipe_resource
*templ
,
2371 struct pipe_memory_object
*_memobj
,
2375 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2376 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2377 struct r600_texture
*rtex
;
2378 struct radeon_surf surface
= {};
2379 struct radeon_bo_metadata metadata
= {};
2380 enum radeon_surf_mode array_mode
;
2382 struct pb_buffer
*buf
= NULL
;
2384 if (memobj
->b
.dedicated
) {
2385 sscreen
->ws
->buffer_get_metadata(memobj
->buf
, &metadata
);
2386 si_surface_import_metadata(sscreen
, &surface
, &metadata
,
2387 &array_mode
, &is_scanout
);
2390 * The bo metadata is unset for un-dedicated images. So we fall
2391 * back to linear. See answer to question 5 of the
2392 * VK_KHX_external_memory spec for some details.
2394 * It is possible that this case isn't going to work if the
2395 * surface pitch isn't correctly aligned by default.
2397 * In order to support it correctly we require multi-image
2398 * metadata to be syncrhonized between radv and radeonsi. The
2399 * semantics of associating multiple image metadata to a memory
2400 * object on the vulkan export side are not concretely defined
2403 * All the use cases we are aware of at the moment for memory
2404 * objects use dedicated allocations. So lets keep the initial
2405 * implementation simple.
2407 * A possible alternative is to attempt to reconstruct the
2408 * tiling information when the TexParameter TEXTURE_TILING_EXT
2411 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
2415 unsigned num_color_samples
= si_get_num_color_samples(sscreen
, templ
, true);
2417 r
= si_init_surface(sscreen
, &surface
, templ
, num_color_samples
,
2418 array_mode
, memobj
->stride
, offset
, true,
2419 is_scanout
, false, false);
2423 rtex
= si_texture_create_object(screen
, templ
, num_color_samples
,
2424 memobj
->buf
, &surface
);
2428 /* r600_texture_create_object doesn't increment refcount of
2429 * memobj->buf, so increment it here.
2431 pb_reference(&buf
, memobj
->buf
);
2433 rtex
->buffer
.b
.is_shared
= true;
2434 rtex
->buffer
.external_usage
= PIPE_HANDLE_USAGE_READ_WRITE
;
2436 si_apply_opaque_metadata(sscreen
, rtex
, &metadata
);
2438 return &rtex
->buffer
.b
.b
;
2441 static bool si_check_resource_capability(struct pipe_screen
*screen
,
2442 struct pipe_resource
*resource
,
2445 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
2447 /* Buffers only support the linear flag. */
2448 if (resource
->target
== PIPE_BUFFER
)
2449 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2451 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2454 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2457 /* TODO: PIPE_BIND_CURSOR - do we care? */
2461 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2463 sscreen
->b
.resource_from_handle
= si_texture_from_handle
;
2464 sscreen
->b
.resource_get_handle
= si_texture_get_handle
;
2465 sscreen
->b
.resource_from_memobj
= si_texture_from_memobj
;
2466 sscreen
->b
.memobj_create_from_handle
= si_memobj_from_handle
;
2467 sscreen
->b
.memobj_destroy
= si_memobj_destroy
;
2468 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2471 void si_init_context_texture_functions(struct si_context
*sctx
)
2473 sctx
->b
.create_surface
= si_create_surface
;
2474 sctx
->b
.surface_destroy
= si_surface_destroy
;