2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeonsi/si_pipe.h"
27 #include "radeonsi/si_query.h"
28 #include "util/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/u_resource.h"
33 #include "util/u_surface.h"
34 #include "util/u_transfer.h"
35 #include "util/os_time.h"
38 #include "state_tracker/drm_driver.h"
39 #include "amd/common/sid.h"
40 #include "amd/common/gfx9d.h"
42 static enum radeon_surf_mode
43 si_choose_tiling(struct si_screen
*sscreen
,
44 const struct pipe_resource
*templ
, bool tc_compatible_htile
);
47 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
48 struct si_texture
*dst
,
49 unsigned dst_level
, unsigned dstx
,
50 unsigned dsty
, unsigned dstz
,
51 struct si_texture
*src
,
53 const struct pipe_box
*src_box
)
58 if (dst
->surface
.bpe
!= src
->surface
.bpe
)
61 /* MSAA: Blits don't exist in the real world. */
62 if (src
->buffer
.b
.b
.nr_samples
> 1 ||
63 dst
->buffer
.b
.b
.nr_samples
> 1)
66 /* Depth-stencil surfaces:
67 * When dst is linear, the DB->CB copy preserves HTILE.
68 * When dst is tiled, the 3D path must be used to update HTILE.
70 if (src
->is_depth
|| dst
->is_depth
)
74 * src: Use the 3D path. DCC decompression is expensive.
75 * dst: Use the 3D path to compress the pixels with DCC.
77 if (vi_dcc_enabled(src
, src_level
) ||
78 vi_dcc_enabled(dst
, dst_level
))
82 * src: Both texture and SDMA paths need decompression. Use SDMA.
83 * dst: If overwriting the whole texture, discard CMASK and use
84 * SDMA. Otherwise, use the 3D path.
86 if (dst
->cmask_buffer
&& dst
->dirty_level_mask
& (1 << dst_level
)) {
87 /* The CMASK clear is only enabled for the first level. */
88 assert(dst_level
== 0);
89 if (!util_texrange_covers_whole_level(&dst
->buffer
.b
.b
, dst_level
,
90 dstx
, dsty
, dstz
, src_box
->width
,
91 src_box
->height
, src_box
->depth
))
94 si_texture_discard_cmask(sctx
->screen
, dst
);
97 /* All requirements are met. Prepare textures for SDMA. */
98 if (src
->cmask_buffer
&& src
->dirty_level_mask
& (1 << src_level
))
99 sctx
->b
.flush_resource(&sctx
->b
, &src
->buffer
.b
.b
);
101 assert(!(src
->dirty_level_mask
& (1 << src_level
)));
102 assert(!(dst
->dirty_level_mask
& (1 << dst_level
)));
107 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
108 static void si_copy_region_with_blit(struct pipe_context
*pipe
,
109 struct pipe_resource
*dst
,
111 unsigned dstx
, unsigned dsty
, unsigned dstz
,
112 struct pipe_resource
*src
,
114 const struct pipe_box
*src_box
)
116 struct pipe_blit_info blit
;
118 memset(&blit
, 0, sizeof(blit
));
119 blit
.src
.resource
= src
;
120 blit
.src
.format
= src
->format
;
121 blit
.src
.level
= src_level
;
122 blit
.src
.box
= *src_box
;
123 blit
.dst
.resource
= dst
;
124 blit
.dst
.format
= dst
->format
;
125 blit
.dst
.level
= dst_level
;
126 blit
.dst
.box
.x
= dstx
;
127 blit
.dst
.box
.y
= dsty
;
128 blit
.dst
.box
.z
= dstz
;
129 blit
.dst
.box
.width
= src_box
->width
;
130 blit
.dst
.box
.height
= src_box
->height
;
131 blit
.dst
.box
.depth
= src_box
->depth
;
132 blit
.mask
= util_format_get_mask(src
->format
) &
133 util_format_get_mask(dst
->format
);
134 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
137 pipe
->blit(pipe
, &blit
);
141 /* Copy from a full GPU texture to a transfer's staging one. */
142 static void si_copy_to_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
144 struct si_context
*sctx
= (struct si_context
*)ctx
;
145 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
146 struct pipe_resource
*dst
= &stransfer
->staging
->b
.b
;
147 struct pipe_resource
*src
= transfer
->resource
;
149 if (src
->nr_samples
> 1) {
150 si_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
151 src
, transfer
->level
, &transfer
->box
);
155 sctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
159 /* Copy from a transfer's staging texture to a full GPU one. */
160 static void si_copy_from_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
162 struct si_context
*sctx
= (struct si_context
*)ctx
;
163 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
164 struct pipe_resource
*dst
= transfer
->resource
;
165 struct pipe_resource
*src
= &stransfer
->staging
->b
.b
;
166 struct pipe_box sbox
;
168 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
170 if (dst
->nr_samples
> 1) {
171 si_copy_region_with_blit(ctx
, dst
, transfer
->level
,
172 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
177 sctx
->dma_copy(ctx
, dst
, transfer
->level
,
178 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
182 static unsigned si_texture_get_offset(struct si_screen
*sscreen
,
183 struct si_texture
*tex
, unsigned level
,
184 const struct pipe_box
*box
,
186 unsigned *layer_stride
)
188 if (sscreen
->info
.chip_class
>= GFX9
) {
189 *stride
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
190 *layer_stride
= tex
->surface
.u
.gfx9
.surf_slice_size
;
195 /* Each texture is an array of slices. Each slice is an array
196 * of mipmap levels. */
197 return box
->z
* tex
->surface
.u
.gfx9
.surf_slice_size
+
198 tex
->surface
.u
.gfx9
.offset
[level
] +
199 (box
->y
/ tex
->surface
.blk_h
*
200 tex
->surface
.u
.gfx9
.surf_pitch
+
201 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
203 *stride
= tex
->surface
.u
.legacy
.level
[level
].nblk_x
*
205 assert((uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
206 *layer_stride
= (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
209 return tex
->surface
.u
.legacy
.level
[level
].offset
;
211 /* Each texture is an array of mipmap levels. Each level is
212 * an array of slices. */
213 return tex
->surface
.u
.legacy
.level
[level
].offset
+
214 box
->z
* (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
215 (box
->y
/ tex
->surface
.blk_h
*
216 tex
->surface
.u
.legacy
.level
[level
].nblk_x
+
217 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
221 static int si_init_surface(struct si_screen
*sscreen
,
222 struct radeon_surf
*surface
,
223 const struct pipe_resource
*ptex
,
224 enum radeon_surf_mode array_mode
,
225 unsigned pitch_in_bytes_override
,
229 bool is_flushed_depth
,
230 bool tc_compatible_htile
)
232 const struct util_format_description
*desc
=
233 util_format_description(ptex
->format
);
234 bool is_depth
, is_stencil
;
236 unsigned i
, bpe
, flags
= 0;
238 is_depth
= util_format_has_depth(desc
);
239 is_stencil
= util_format_has_stencil(desc
);
241 if (!is_flushed_depth
&&
242 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
243 bpe
= 4; /* stencil is allocated separately */
245 bpe
= util_format_get_blocksize(ptex
->format
);
246 assert(util_is_power_of_two_or_zero(bpe
));
249 if (!is_flushed_depth
&& is_depth
) {
250 flags
|= RADEON_SURF_ZBUFFER
;
252 if (tc_compatible_htile
&&
253 (sscreen
->info
.chip_class
>= GFX9
||
254 array_mode
== RADEON_SURF_MODE_2D
)) {
255 /* TC-compatible HTILE only supports Z32_FLOAT.
256 * GFX9 also supports Z16_UNORM.
257 * On VI, promote Z16 to Z32. DB->CB copies will convert
258 * the format for transfers.
260 if (sscreen
->info
.chip_class
== VI
)
263 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
267 flags
|= RADEON_SURF_SBUFFER
;
270 if (sscreen
->info
.chip_class
>= VI
&&
271 (ptex
->flags
& SI_RESOURCE_FLAG_DISABLE_DCC
||
272 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
273 (ptex
->nr_samples
>= 2 && !sscreen
->dcc_msaa_allowed
)))
274 flags
|= RADEON_SURF_DISABLE_DCC
;
276 /* Stoney: 128bpp MSAA textures randomly fail piglit tests with DCC. */
277 if (sscreen
->info
.family
== CHIP_STONEY
&&
278 bpe
== 16 && ptex
->nr_samples
>= 2)
279 flags
|= RADEON_SURF_DISABLE_DCC
;
281 /* VI: DCC clear for 4x and 8x MSAA array textures unimplemented. */
282 if (sscreen
->info
.chip_class
== VI
&&
283 ptex
->nr_storage_samples
>= 4 &&
284 ptex
->array_size
> 1)
285 flags
|= RADEON_SURF_DISABLE_DCC
;
287 /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
288 if (sscreen
->info
.chip_class
>= GFX9
&&
289 ptex
->nr_storage_samples
>= 4)
290 flags
|= RADEON_SURF_DISABLE_DCC
;
292 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
293 /* This should catch bugs in gallium users setting incorrect flags. */
294 assert(ptex
->nr_samples
<= 1 &&
295 ptex
->array_size
== 1 &&
297 ptex
->last_level
== 0 &&
298 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
300 flags
|= RADEON_SURF_SCANOUT
;
303 if (ptex
->bind
& PIPE_BIND_SHARED
)
304 flags
|= RADEON_SURF_SHAREABLE
;
306 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
307 if (!(ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
))
308 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
310 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, flags
, bpe
,
311 array_mode
, surface
);
316 unsigned pitch
= pitch_in_bytes_override
/ bpe
;
318 if (sscreen
->info
.chip_class
>= GFX9
) {
320 surface
->u
.gfx9
.surf_pitch
= pitch
;
321 surface
->u
.gfx9
.surf_slice_size
=
322 (uint64_t)pitch
* surface
->u
.gfx9
.surf_height
* bpe
;
324 surface
->u
.gfx9
.surf_offset
= offset
;
327 surface
->u
.legacy
.level
[0].nblk_x
= pitch
;
328 surface
->u
.legacy
.level
[0].slice_size_dw
=
329 ((uint64_t)pitch
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
332 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
333 surface
->u
.legacy
.level
[i
].offset
+= offset
;
339 static void si_get_display_metadata(struct si_screen
*sscreen
,
340 struct radeon_surf
*surf
,
341 struct radeon_bo_metadata
*metadata
,
342 enum radeon_surf_mode
*array_mode
,
345 if (sscreen
->info
.chip_class
>= GFX9
) {
346 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
347 *array_mode
= RADEON_SURF_MODE_2D
;
349 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
351 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
352 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
354 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
356 if (metadata
->u
.gfx9
.dcc_offset_256B
) {
357 surf
->u
.gfx9
.display_dcc_pitch_max
= metadata
->u
.gfx9
.dcc_pitch_max
;
358 assert(metadata
->u
.gfx9
.dcc_independent_64B
== 1);
361 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
362 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
363 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
364 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
365 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
366 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
368 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
369 *array_mode
= RADEON_SURF_MODE_2D
;
370 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
371 *array_mode
= RADEON_SURF_MODE_1D
;
373 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
375 *is_scanout
= metadata
->u
.legacy
.scanout
;
379 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
380 struct si_texture
*tex
)
382 struct si_screen
*sscreen
= sctx
->screen
;
383 struct pipe_context
*ctx
= &sctx
->b
;
385 if (ctx
== sscreen
->aux_context
)
386 mtx_lock(&sscreen
->aux_context_lock
);
388 unsigned n
= sctx
->num_decompress_calls
;
389 ctx
->flush_resource(ctx
, &tex
->buffer
.b
.b
);
391 /* Flush only if any fast clear elimination took place. */
392 if (n
!= sctx
->num_decompress_calls
)
393 ctx
->flush(ctx
, NULL
, 0);
395 if (ctx
== sscreen
->aux_context
)
396 mtx_unlock(&sscreen
->aux_context_lock
);
399 void si_texture_discard_cmask(struct si_screen
*sscreen
,
400 struct si_texture
*tex
)
402 if (!tex
->cmask_buffer
)
405 assert(tex
->buffer
.b
.b
.nr_samples
<= 1);
408 tex
->cmask_base_address_reg
= tex
->buffer
.gpu_address
>> 8;
409 tex
->dirty_level_mask
= 0;
411 tex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
413 if (tex
->cmask_buffer
!= &tex
->buffer
)
414 si_resource_reference(&tex
->cmask_buffer
, NULL
);
416 tex
->cmask_buffer
= NULL
;
418 /* Notify all contexts about the change. */
419 p_atomic_inc(&sscreen
->dirty_tex_counter
);
420 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
423 static bool si_can_disable_dcc(struct si_texture
*tex
)
425 /* We can't disable DCC if it can be written by another process. */
426 return tex
->dcc_offset
&&
427 (!tex
->buffer
.b
.is_shared
||
428 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
));
431 static bool si_texture_discard_dcc(struct si_screen
*sscreen
,
432 struct si_texture
*tex
)
434 if (!si_can_disable_dcc(tex
)) {
435 assert(tex
->display_dcc_offset
== 0);
439 assert(tex
->dcc_separate_buffer
== NULL
);
443 tex
->display_dcc_offset
= 0;
444 tex
->dcc_retile_map_offset
= 0;
446 /* Notify all contexts about the change. */
447 p_atomic_inc(&sscreen
->dirty_tex_counter
);
452 * Disable DCC for the texture. (first decompress, then discard metadata).
454 * There is unresolved multi-context synchronization issue between
455 * screen::aux_context and the current context. If applications do this with
456 * multiple contexts, it's already undefined behavior for them and we don't
457 * have to worry about that. The scenario is:
459 * If context 1 disables DCC and context 2 has queued commands that write
460 * to the texture via CB with DCC enabled, and the order of operations is
462 * context 2 queues draw calls rendering to the texture, but doesn't flush
463 * context 1 disables DCC and flushes
464 * context 1 & 2 reset descriptors and FB state
465 * context 2 flushes (new compressed tiles written by the draw calls)
466 * context 1 & 2 read garbage, because DCC is disabled, yet there are
469 * \param sctx the current context if you have one, or sscreen->aux_context
472 bool si_texture_disable_dcc(struct si_context
*sctx
,
473 struct si_texture
*tex
)
475 struct si_screen
*sscreen
= sctx
->screen
;
477 if (!sctx
->has_graphics
)
478 return si_texture_discard_dcc(sscreen
, tex
);
480 if (!si_can_disable_dcc(tex
))
483 if (&sctx
->b
== sscreen
->aux_context
)
484 mtx_lock(&sscreen
->aux_context_lock
);
486 /* Decompress DCC. */
487 si_decompress_dcc(sctx
, tex
);
488 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
490 if (&sctx
->b
== sscreen
->aux_context
)
491 mtx_unlock(&sscreen
->aux_context_lock
);
493 return si_texture_discard_dcc(sscreen
, tex
);
496 static void si_reallocate_texture_inplace(struct si_context
*sctx
,
497 struct si_texture
*tex
,
498 unsigned new_bind_flag
,
499 bool invalidate_storage
)
501 struct pipe_screen
*screen
= sctx
->b
.screen
;
502 struct si_texture
*new_tex
;
503 struct pipe_resource templ
= tex
->buffer
.b
.b
;
506 templ
.bind
|= new_bind_flag
;
508 if (tex
->buffer
.b
.is_shared
)
511 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
512 if (tex
->surface
.is_linear
)
515 /* This fails with MSAA, depth, and compressed textures. */
516 if (si_choose_tiling(sctx
->screen
, &templ
, false) !=
517 RADEON_SURF_MODE_LINEAR_ALIGNED
)
521 new_tex
= (struct si_texture
*)screen
->resource_create(screen
, &templ
);
525 /* Copy the pixels to the new texture. */
526 if (!invalidate_storage
) {
527 for (i
= 0; i
<= templ
.last_level
; i
++) {
531 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
532 util_num_layers(&templ
, i
), &box
);
534 sctx
->dma_copy(&sctx
->b
, &new_tex
->buffer
.b
.b
, i
, 0, 0, 0,
535 &tex
->buffer
.b
.b
, i
, &box
);
539 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
540 si_texture_discard_cmask(sctx
->screen
, tex
);
541 si_texture_discard_dcc(sctx
->screen
, tex
);
544 /* Replace the structure fields of tex. */
545 tex
->buffer
.b
.b
.bind
= templ
.bind
;
546 pb_reference(&tex
->buffer
.buf
, new_tex
->buffer
.buf
);
547 tex
->buffer
.gpu_address
= new_tex
->buffer
.gpu_address
;
548 tex
->buffer
.vram_usage
= new_tex
->buffer
.vram_usage
;
549 tex
->buffer
.gart_usage
= new_tex
->buffer
.gart_usage
;
550 tex
->buffer
.bo_size
= new_tex
->buffer
.bo_size
;
551 tex
->buffer
.bo_alignment
= new_tex
->buffer
.bo_alignment
;
552 tex
->buffer
.domains
= new_tex
->buffer
.domains
;
553 tex
->buffer
.flags
= new_tex
->buffer
.flags
;
555 tex
->surface
= new_tex
->surface
;
556 tex
->size
= new_tex
->size
;
557 si_texture_reference(&tex
->flushed_depth_texture
,
558 new_tex
->flushed_depth_texture
);
560 tex
->fmask_offset
= new_tex
->fmask_offset
;
561 tex
->cmask_offset
= new_tex
->cmask_offset
;
562 tex
->cmask_base_address_reg
= new_tex
->cmask_base_address_reg
;
564 if (tex
->cmask_buffer
== &tex
->buffer
)
565 tex
->cmask_buffer
= NULL
;
567 si_resource_reference(&tex
->cmask_buffer
, NULL
);
569 if (new_tex
->cmask_buffer
== &new_tex
->buffer
)
570 tex
->cmask_buffer
= &tex
->buffer
;
572 si_resource_reference(&tex
->cmask_buffer
, new_tex
->cmask_buffer
);
574 tex
->dcc_offset
= new_tex
->dcc_offset
;
575 tex
->cb_color_info
= new_tex
->cb_color_info
;
576 memcpy(tex
->color_clear_value
, new_tex
->color_clear_value
,
577 sizeof(tex
->color_clear_value
));
578 tex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
580 tex
->htile_offset
= new_tex
->htile_offset
;
581 tex
->depth_clear_value
= new_tex
->depth_clear_value
;
582 tex
->dirty_level_mask
= new_tex
->dirty_level_mask
;
583 tex
->stencil_dirty_level_mask
= new_tex
->stencil_dirty_level_mask
;
584 tex
->db_render_format
= new_tex
->db_render_format
;
585 tex
->stencil_clear_value
= new_tex
->stencil_clear_value
;
586 tex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
587 tex
->depth_cleared
= new_tex
->depth_cleared
;
588 tex
->stencil_cleared
= new_tex
->stencil_cleared
;
589 tex
->upgraded_depth
= new_tex
->upgraded_depth
;
590 tex
->db_compatible
= new_tex
->db_compatible
;
591 tex
->can_sample_z
= new_tex
->can_sample_z
;
592 tex
->can_sample_s
= new_tex
->can_sample_s
;
594 tex
->separate_dcc_dirty
= new_tex
->separate_dcc_dirty
;
595 tex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
596 si_resource_reference(&tex
->dcc_separate_buffer
,
597 new_tex
->dcc_separate_buffer
);
598 si_resource_reference(&tex
->last_dcc_separate_buffer
,
599 new_tex
->last_dcc_separate_buffer
);
601 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
602 assert(!tex
->htile_offset
);
603 assert(!tex
->cmask_buffer
);
604 assert(!tex
->surface
.fmask_size
);
605 assert(!tex
->dcc_offset
);
606 assert(!tex
->is_depth
);
609 si_texture_reference(&new_tex
, NULL
);
611 p_atomic_inc(&sctx
->screen
->dirty_tex_counter
);
614 static uint32_t si_get_bo_metadata_word1(struct si_screen
*sscreen
)
616 return (ATI_VENDOR_ID
<< 16) | sscreen
->info
.pci_id
;
619 static void si_set_tex_bo_metadata(struct si_screen
*sscreen
,
620 struct si_texture
*tex
)
622 struct radeon_surf
*surface
= &tex
->surface
;
623 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
624 struct radeon_bo_metadata md
;
626 memset(&md
, 0, sizeof(md
));
628 if (sscreen
->info
.chip_class
>= GFX9
) {
629 md
.u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
631 if (tex
->dcc_offset
&& !tex
->dcc_separate_buffer
) {
632 uint64_t dcc_offset
=
633 tex
->display_dcc_offset
? tex
->display_dcc_offset
636 assert((dcc_offset
>> 8) != 0 && (dcc_offset
>> 8) < (1 << 24));
637 md
.u
.gfx9
.dcc_offset_256B
= dcc_offset
>> 8;
638 md
.u
.gfx9
.dcc_pitch_max
= tex
->surface
.u
.gfx9
.display_dcc_pitch_max
;
639 md
.u
.gfx9
.dcc_independent_64B
= 1;
642 md
.u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
643 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
644 md
.u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
645 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
646 md
.u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
647 md
.u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
648 md
.u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
649 md
.u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
650 md
.u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
651 md
.u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
652 md
.u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
653 md
.u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
656 assert(tex
->dcc_separate_buffer
== NULL
);
657 assert(tex
->surface
.fmask_size
== 0);
659 /* Metadata image format format version 1:
660 * [0] = 1 (metadata format identifier)
661 * [1] = (VENDOR_ID << 16) | PCI_ID
662 * [2:9] = image descriptor for the whole resource
663 * [2] is always 0, because the base address is cleared
664 * [9] is the DCC offset bits [39:8] from the beginning of
666 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
669 md
.metadata
[0] = 1; /* metadata image format version 1 */
671 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
672 md
.metadata
[1] = si_get_bo_metadata_word1(sscreen
);
674 static const unsigned char swizzle
[] = {
680 bool is_array
= util_texture_is_array(res
->target
);
683 si_make_texture_descriptor(sscreen
, tex
, true,
684 res
->target
, res
->format
,
685 swizzle
, 0, res
->last_level
, 0,
686 is_array
? res
->array_size
- 1 : 0,
687 res
->width0
, res
->height0
, res
->depth0
,
690 si_set_mutable_tex_desc_fields(sscreen
, tex
, &tex
->surface
.u
.legacy
.level
[0],
691 0, 0, tex
->surface
.blk_w
, false, desc
);
693 /* Clear the base address and set the relative DCC offset. */
695 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
696 desc
[7] = tex
->dcc_offset
>> 8;
698 /* Dwords [2:9] contain the image descriptor. */
699 memcpy(&md
.metadata
[2], desc
, sizeof(desc
));
700 md
.size_metadata
= 10 * 4;
702 /* Dwords [10:..] contain the mipmap level offsets. */
703 if (sscreen
->info
.chip_class
<= VI
) {
704 for (unsigned i
= 0; i
<= res
->last_level
; i
++)
705 md
.metadata
[10+i
] = tex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
707 md
.size_metadata
+= (1 + res
->last_level
) * 4;
710 sscreen
->ws
->buffer_set_metadata(tex
->buffer
.buf
, &md
);
713 static void si_get_opaque_metadata(struct si_screen
*sscreen
,
714 struct si_texture
*tex
,
715 struct radeon_bo_metadata
*md
)
717 uint32_t *desc
= &md
->metadata
[2];
719 if (sscreen
->info
.chip_class
< VI
)
722 /* Return if DCC is enabled. The texture should be set up with it
725 if (md
->size_metadata
>= 10 * 4 && /* at least 2(header) + 8(desc) dwords */
726 md
->metadata
[0] != 0 &&
727 md
->metadata
[1] == si_get_bo_metadata_word1(sscreen
) &&
728 G_008F28_COMPRESSION_EN(desc
[6])) {
729 tex
->dcc_offset
= (uint64_t)desc
[7] << 8;
731 if (sscreen
->info
.chip_class
>= GFX9
) {
732 /* Fix up parameters for displayable DCC. Some state
733 * trackers don't set the SCANOUT flag when importing
734 * displayable images, so we have to recover the correct
737 tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
=
738 G_008F24_META_PIPE_ALIGNED(desc
[5]);
739 tex
->surface
.u
.gfx9
.dcc
.rb_aligned
=
740 G_008F24_META_RB_ALIGNED(desc
[5]);
742 /* If DCC is unaligned, this can only be a displayable image. */
743 if (!tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
&&
744 !tex
->surface
.u
.gfx9
.dcc
.rb_aligned
)
745 tex
->surface
.is_displayable
= true;
750 /* Disable DCC. These are always set by texture_from_handle and must
756 static bool si_has_displayable_dcc(struct si_texture
*tex
)
758 struct si_screen
*sscreen
= (struct si_screen
*)tex
->buffer
.b
.b
.screen
;
760 if (sscreen
->info
.chip_class
<= VI
)
763 /* This needs a cache flush before scanout.
764 * (it can't be scanned out and rendered to simultaneously)
766 if (sscreen
->info
.use_display_dcc_unaligned
&&
768 !tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
&&
769 !tex
->surface
.u
.gfx9
.dcc
.rb_aligned
)
772 /* This needs an explicit flush (flush_resource). */
773 if (sscreen
->info
.use_display_dcc_with_retile_blit
&&
774 tex
->display_dcc_offset
)
780 static boolean
si_texture_get_handle(struct pipe_screen
* screen
,
781 struct pipe_context
*ctx
,
782 struct pipe_resource
*resource
,
783 struct winsys_handle
*whandle
,
786 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
787 struct si_context
*sctx
;
788 struct si_resource
*res
= si_resource(resource
);
789 struct si_texture
*tex
= (struct si_texture
*)resource
;
790 bool update_metadata
= false;
791 unsigned stride
, offset
, slice_size
;
794 ctx
= threaded_context_unwrap_sync(ctx
);
795 sctx
= (struct si_context
*)(ctx
? ctx
: sscreen
->aux_context
);
797 if (resource
->target
!= PIPE_BUFFER
) {
798 /* This is not supported now, but it might be required for OpenCL
799 * interop in the future.
801 if (resource
->nr_samples
> 1 || tex
->is_depth
)
804 /* Move a suballocated texture into a non-suballocated allocation. */
805 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
806 tex
->surface
.tile_swizzle
||
807 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
808 sscreen
->info
.has_local_buffers
&&
809 whandle
->type
!= WINSYS_HANDLE_TYPE_KMS
)) {
810 assert(!res
->b
.is_shared
);
811 si_reallocate_texture_inplace(sctx
, tex
,
812 PIPE_BIND_SHARED
, false);
814 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
815 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
816 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
817 assert(tex
->surface
.tile_swizzle
== 0);
820 /* Since shader image stores don't support DCC on VI,
821 * disable it for external clients that want write
824 if ((usage
& PIPE_HANDLE_USAGE_SHADER_WRITE
&& tex
->dcc_offset
) ||
825 /* Displayable DCC requires an explicit flush. */
826 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
827 si_has_displayable_dcc(tex
))) {
828 if (si_texture_disable_dcc(sctx
, tex
)) {
829 update_metadata
= true;
830 /* si_texture_disable_dcc flushes the context */
835 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
836 (tex
->cmask_buffer
|| tex
->dcc_offset
)) {
837 /* Eliminate fast clear (both CMASK and DCC) */
838 si_eliminate_fast_color_clear(sctx
, tex
);
839 /* eliminate_fast_color_clear flushes the context */
842 /* Disable CMASK if flush_resource isn't going
845 if (tex
->cmask_buffer
)
846 si_texture_discard_cmask(sscreen
, tex
);
850 if (!res
->b
.is_shared
|| update_metadata
)
851 si_set_tex_bo_metadata(sscreen
, tex
);
853 if (sscreen
->info
.chip_class
>= GFX9
) {
854 offset
= tex
->surface
.u
.gfx9
.surf_offset
;
855 stride
= tex
->surface
.u
.gfx9
.surf_pitch
*
857 slice_size
= tex
->surface
.u
.gfx9
.surf_slice_size
;
859 offset
= tex
->surface
.u
.legacy
.level
[0].offset
;
860 stride
= tex
->surface
.u
.legacy
.level
[0].nblk_x
*
862 slice_size
= (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
865 /* Buffer exports are for the OpenCL interop. */
866 /* Move a suballocated buffer into a non-suballocated allocation. */
867 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
868 /* A DMABUF export always fails if the BO is local. */
869 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
870 sscreen
->info
.has_local_buffers
)) {
871 assert(!res
->b
.is_shared
);
873 /* Allocate a new buffer with PIPE_BIND_SHARED. */
874 struct pipe_resource templ
= res
->b
.b
;
875 templ
.bind
|= PIPE_BIND_SHARED
;
877 struct pipe_resource
*newb
=
878 screen
->resource_create(screen
, &templ
);
882 /* Copy the old buffer contents to the new one. */
884 u_box_1d(0, newb
->width0
, &box
);
885 sctx
->b
.resource_copy_region(&sctx
->b
, newb
, 0, 0, 0, 0,
888 /* Move the new buffer storage to the old pipe_resource. */
889 si_replace_buffer_storage(&sctx
->b
, &res
->b
.b
, newb
);
890 pipe_resource_reference(&newb
, NULL
);
892 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
893 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
903 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
905 if (res
->b
.is_shared
) {
906 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
909 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
910 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
911 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
913 res
->b
.is_shared
= true;
914 res
->external_usage
= usage
;
917 return sscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
918 slice_size
, whandle
);
921 static void si_texture_destroy(struct pipe_screen
*screen
,
922 struct pipe_resource
*ptex
)
924 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
925 struct si_texture
*tex
= (struct si_texture
*)ptex
;
926 struct si_resource
*resource
= &tex
->buffer
;
928 if (sscreen
->info
.chip_class
>= GFX9
)
929 free(tex
->surface
.u
.gfx9
.dcc_retile_map
);
931 si_texture_reference(&tex
->flushed_depth_texture
, NULL
);
933 if (tex
->cmask_buffer
!= &tex
->buffer
) {
934 si_resource_reference(&tex
->cmask_buffer
, NULL
);
936 pb_reference(&resource
->buf
, NULL
);
937 si_resource_reference(&tex
->dcc_separate_buffer
, NULL
);
938 si_resource_reference(&tex
->last_dcc_separate_buffer
, NULL
);
942 static const struct u_resource_vtbl si_texture_vtbl
;
944 static void si_texture_get_htile_size(struct si_screen
*sscreen
,
945 struct si_texture
*tex
)
947 unsigned cl_width
, cl_height
, width
, height
;
948 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
949 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
951 assert(sscreen
->info
.chip_class
<= VI
);
953 tex
->surface
.htile_size
= 0;
955 if (tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
956 !sscreen
->info
.htile_cmask_support_1d_tiling
)
959 /* Overalign HTILE on P2 configs to work around GPU hangs in
960 * piglit/depthstencil-render-miplevels 585.
962 * This has been confirmed to help Kabini & Stoney, where the hangs
963 * are always reproducible. I think I have seen the test hang
964 * on Carrizo too, though it was very rare there.
966 if (sscreen
->info
.chip_class
>= CIK
&& num_pipes
< 4)
995 width
= align(tex
->surface
.u
.legacy
.level
[0].nblk_x
, cl_width
* 8);
996 height
= align(tex
->surface
.u
.legacy
.level
[0].nblk_y
, cl_height
* 8);
998 slice_elements
= (width
* height
) / (8 * 8);
999 slice_bytes
= slice_elements
* 4;
1001 pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
1002 base_align
= num_pipes
* pipe_interleave_bytes
;
1004 tex
->surface
.htile_alignment
= base_align
;
1005 tex
->surface
.htile_size
=
1006 util_num_layers(&tex
->buffer
.b
.b
, 0) *
1007 align(slice_bytes
, base_align
);
1010 static void si_texture_allocate_htile(struct si_screen
*sscreen
,
1011 struct si_texture
*tex
)
1013 if (sscreen
->info
.chip_class
<= VI
&& !tex
->tc_compatible_htile
)
1014 si_texture_get_htile_size(sscreen
, tex
);
1016 if (!tex
->surface
.htile_size
)
1019 tex
->htile_offset
= align(tex
->size
, tex
->surface
.htile_alignment
);
1020 tex
->size
= tex
->htile_offset
+ tex
->surface
.htile_size
;
1023 void si_print_texture_info(struct si_screen
*sscreen
,
1024 struct si_texture
*tex
, struct u_log_context
*log
)
1028 /* Common parameters. */
1029 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
1030 "blk_h=%u, array_size=%u, last_level=%u, "
1031 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
1032 tex
->buffer
.b
.b
.width0
, tex
->buffer
.b
.b
.height0
,
1033 tex
->buffer
.b
.b
.depth0
, tex
->surface
.blk_w
,
1035 tex
->buffer
.b
.b
.array_size
, tex
->buffer
.b
.b
.last_level
,
1036 tex
->surface
.bpe
, tex
->buffer
.b
.b
.nr_samples
,
1037 tex
->surface
.flags
, util_format_short_name(tex
->buffer
.b
.b
.format
));
1039 if (sscreen
->info
.chip_class
>= GFX9
) {
1040 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
1041 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
1042 tex
->surface
.surf_size
,
1043 tex
->surface
.u
.gfx9
.surf_slice_size
,
1044 tex
->surface
.surf_alignment
,
1045 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
1046 tex
->surface
.u
.gfx9
.surf
.epitch
,
1047 tex
->surface
.u
.gfx9
.surf_pitch
);
1049 if (tex
->surface
.fmask_size
) {
1050 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
1051 "alignment=%u, swmode=%u, epitch=%u\n",
1053 tex
->surface
.fmask_size
,
1054 tex
->surface
.fmask_alignment
,
1055 tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1056 tex
->surface
.u
.gfx9
.fmask
.epitch
);
1059 if (tex
->cmask_buffer
) {
1060 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%u, "
1061 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1063 tex
->surface
.cmask_size
,
1064 tex
->surface
.cmask_alignment
,
1065 tex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1066 tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1069 if (tex
->htile_offset
) {
1070 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, alignment=%u, "
1071 "rb_aligned=%u, pipe_aligned=%u\n",
1073 tex
->surface
.htile_size
,
1074 tex
->surface
.htile_alignment
,
1075 tex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1076 tex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1079 if (tex
->dcc_offset
) {
1080 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, "
1081 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1082 tex
->dcc_offset
, tex
->surface
.dcc_size
,
1083 tex
->surface
.dcc_alignment
,
1084 tex
->surface
.u
.gfx9
.display_dcc_pitch_max
,
1085 tex
->surface
.num_dcc_levels
);
1088 if (tex
->surface
.u
.gfx9
.stencil_offset
) {
1089 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1090 tex
->surface
.u
.gfx9
.stencil_offset
,
1091 tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1092 tex
->surface
.u
.gfx9
.stencil
.epitch
);
1097 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1098 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1099 tex
->surface
.surf_size
, tex
->surface
.surf_alignment
, tex
->surface
.u
.legacy
.bankw
,
1100 tex
->surface
.u
.legacy
.bankh
, tex
->surface
.u
.legacy
.num_banks
, tex
->surface
.u
.legacy
.mtilea
,
1101 tex
->surface
.u
.legacy
.tile_split
, tex
->surface
.u
.legacy
.pipe_config
,
1102 (tex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1104 if (tex
->surface
.fmask_size
)
1105 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1106 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1107 tex
->fmask_offset
, tex
->surface
.fmask_size
, tex
->surface
.fmask_alignment
,
1108 tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
,
1109 tex
->surface
.u
.legacy
.fmask
.bankh
,
1110 tex
->surface
.u
.legacy
.fmask
.slice_tile_max
,
1111 tex
->surface
.u
.legacy
.fmask
.tiling_index
);
1113 if (tex
->cmask_buffer
)
1114 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%u, alignment=%u, "
1115 "slice_tile_max=%u\n",
1116 tex
->cmask_offset
, tex
->surface
.cmask_size
, tex
->surface
.cmask_alignment
,
1117 tex
->surface
.u
.legacy
.cmask_slice_tile_max
);
1119 if (tex
->htile_offset
)
1120 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, "
1121 "alignment=%u, TC_compatible = %u\n",
1122 tex
->htile_offset
, tex
->surface
.htile_size
,
1123 tex
->surface
.htile_alignment
,
1124 tex
->tc_compatible_htile
);
1126 if (tex
->dcc_offset
) {
1127 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, alignment=%u\n",
1128 tex
->dcc_offset
, tex
->surface
.dcc_size
,
1129 tex
->surface
.dcc_alignment
);
1130 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1131 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%u, "
1132 "fast_clear_size=%u\n",
1133 i
, i
< tex
->surface
.num_dcc_levels
,
1134 tex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1135 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1138 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1139 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1140 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1141 "mode=%u, tiling_index = %u\n",
1142 i
, tex
->surface
.u
.legacy
.level
[i
].offset
,
1143 (uint64_t)tex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
1144 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1145 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1146 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1147 tex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1148 tex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1149 tex
->surface
.u
.legacy
.level
[i
].mode
,
1150 tex
->surface
.u
.legacy
.tiling_index
[i
]);
1152 if (tex
->surface
.has_stencil
) {
1153 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1154 tex
->surface
.u
.legacy
.stencil_tile_split
);
1155 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++) {
1156 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1157 "slice_size=%"PRIu64
", npix_x=%u, "
1158 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1159 "mode=%u, tiling_index = %u\n",
1160 i
, tex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1161 (uint64_t)tex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
1162 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1163 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1164 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1165 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1166 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1167 tex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1168 tex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1173 /* Common processing for si_texture_create and si_texture_from_handle */
1174 static struct si_texture
*
1175 si_texture_create_object(struct pipe_screen
*screen
,
1176 const struct pipe_resource
*base
,
1177 struct pb_buffer
*buf
,
1178 struct radeon_surf
*surface
)
1180 struct si_texture
*tex
;
1181 struct si_resource
*resource
;
1182 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1184 tex
= CALLOC_STRUCT(si_texture
);
1188 resource
= &tex
->buffer
;
1189 resource
->b
.b
= *base
;
1190 resource
->b
.b
.next
= NULL
;
1191 resource
->b
.vtbl
= &si_texture_vtbl
;
1192 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1193 resource
->b
.b
.screen
= screen
;
1195 /* don't include stencil-only formats which we don't support for rendering */
1196 tex
->is_depth
= util_format_has_depth(util_format_description(tex
->buffer
.b
.b
.format
));
1198 tex
->surface
= *surface
;
1199 tex
->size
= tex
->surface
.surf_size
;
1201 tex
->tc_compatible_htile
= tex
->surface
.htile_size
!= 0 &&
1202 (tex
->surface
.flags
&
1203 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1205 /* TC-compatible HTILE:
1206 * - VI only supports Z32_FLOAT.
1207 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1208 if (tex
->tc_compatible_htile
) {
1209 if (sscreen
->info
.chip_class
>= GFX9
&&
1210 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1211 tex
->db_render_format
= base
->format
;
1213 tex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1214 tex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1215 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1218 tex
->db_render_format
= base
->format
;
1221 /* Applies to GCN. */
1222 tex
->last_msaa_resolve_target_micro_mode
= tex
->surface
.micro_tile_mode
;
1224 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1225 * between frames, so the only thing that can enable separate DCC
1226 * with DRI2 is multiple slow clears within a frame.
1228 tex
->ps_draw_ratio
= 0;
1230 if (tex
->is_depth
) {
1231 if (sscreen
->info
.chip_class
>= GFX9
) {
1232 tex
->can_sample_z
= true;
1233 tex
->can_sample_s
= true;
1235 tex
->can_sample_z
= !tex
->surface
.u
.legacy
.depth_adjusted
;
1236 tex
->can_sample_s
= !tex
->surface
.u
.legacy
.stencil_adjusted
;
1239 if (!(base
->flags
& (SI_RESOURCE_FLAG_TRANSFER
|
1240 SI_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1241 tex
->db_compatible
= true;
1243 if (!(sscreen
->debug_flags
& DBG(NO_HYPERZ
)))
1244 si_texture_allocate_htile(sscreen
, tex
);
1247 if (base
->nr_samples
> 1 &&
1249 !(sscreen
->debug_flags
& DBG(NO_FMASK
))) {
1250 /* Allocate FMASK. */
1251 tex
->fmask_offset
= align64(tex
->size
,
1252 tex
->surface
.fmask_alignment
);
1253 tex
->size
= tex
->fmask_offset
+ tex
->surface
.fmask_size
;
1255 /* Allocate CMASK. */
1256 tex
->cmask_offset
= align64(tex
->size
, tex
->surface
.cmask_alignment
);
1257 tex
->size
= tex
->cmask_offset
+ tex
->surface
.cmask_size
;
1258 tex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
1259 tex
->cmask_buffer
= &tex
->buffer
;
1261 if (!tex
->surface
.fmask_size
|| !tex
->surface
.cmask_size
)
1265 /* Shared textures must always set up DCC here.
1266 * If it's not present, it will be disabled by
1267 * apply_opaque_metadata later.
1269 if (tex
->surface
.dcc_size
&&
1270 (buf
|| !(sscreen
->debug_flags
& DBG(NO_DCC
))) &&
1271 (sscreen
->info
.use_display_dcc_unaligned
||
1272 sscreen
->info
.use_display_dcc_with_retile_blit
||
1273 !(tex
->surface
.flags
& RADEON_SURF_SCANOUT
))) {
1274 /* Add space for the DCC buffer. */
1275 tex
->dcc_offset
= align64(tex
->size
, tex
->surface
.dcc_alignment
);
1276 tex
->size
= tex
->dcc_offset
+ tex
->surface
.dcc_size
;
1278 if (sscreen
->info
.chip_class
>= GFX9
&&
1279 tex
->surface
.u
.gfx9
.dcc_retile_num_elements
) {
1280 /* Add space for the displayable DCC buffer. */
1281 tex
->display_dcc_offset
=
1282 align64(tex
->size
, tex
->surface
.u
.gfx9
.display_dcc_alignment
);
1283 tex
->size
= tex
->display_dcc_offset
+
1284 tex
->surface
.u
.gfx9
.display_dcc_size
;
1286 /* Add space for the DCC retile buffer. (16-bit or 32-bit elements) */
1287 tex
->dcc_retile_map_offset
=
1288 align64(tex
->size
, sscreen
->info
.tcc_cache_line_size
);
1290 if (tex
->surface
.u
.gfx9
.dcc_retile_use_uint16
) {
1291 tex
->size
= tex
->dcc_retile_map_offset
+
1292 tex
->surface
.u
.gfx9
.dcc_retile_num_elements
* 2;
1294 tex
->size
= tex
->dcc_retile_map_offset
+
1295 tex
->surface
.u
.gfx9
.dcc_retile_num_elements
* 4;
1301 /* Now create the backing buffer. */
1303 si_init_resource_fields(sscreen
, resource
, tex
->size
,
1304 tex
->surface
.surf_alignment
);
1306 if (!si_alloc_resource(sscreen
, resource
))
1309 resource
->buf
= buf
;
1310 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1311 resource
->bo_size
= buf
->size
;
1312 resource
->bo_alignment
= buf
->alignment
;
1313 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1314 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1315 resource
->vram_usage
= buf
->size
;
1316 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1317 resource
->gart_usage
= buf
->size
;
1320 if (tex
->cmask_buffer
) {
1321 /* Initialize the cmask to 0xCC (= compressed state). */
1322 si_screen_clear_buffer(sscreen
, &tex
->cmask_buffer
->b
.b
,
1323 tex
->cmask_offset
, tex
->surface
.cmask_size
,
1326 if (tex
->htile_offset
) {
1327 uint32_t clear_value
= 0;
1329 if (sscreen
->info
.chip_class
>= GFX9
|| tex
->tc_compatible_htile
)
1330 clear_value
= 0x0000030F;
1332 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1334 tex
->surface
.htile_size
,
1338 /* Initialize DCC only if the texture is not being imported. */
1339 if (!buf
&& tex
->dcc_offset
) {
1340 /* Clear DCC to black for all tiles with DCC enabled.
1342 * This fixes corruption in 3DMark Slingshot Extreme, which
1343 * uses uninitialized textures, causing corruption.
1345 if (tex
->surface
.num_dcc_levels
== tex
->buffer
.b
.b
.last_level
+ 1 &&
1346 tex
->buffer
.b
.b
.nr_samples
<= 2) {
1347 /* Simple case - all tiles have DCC enabled. */
1348 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1350 tex
->surface
.dcc_size
,
1351 DCC_CLEAR_COLOR_0000
);
1352 } else if (sscreen
->info
.chip_class
>= GFX9
) {
1353 /* Clear to uncompressed. Clearing this to black is complicated. */
1354 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1356 tex
->surface
.dcc_size
,
1359 /* GFX8: Initialize mipmap levels and multisamples separately. */
1360 if (tex
->buffer
.b
.b
.nr_samples
>= 2) {
1361 /* Clearing this to black is complicated. */
1362 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1364 tex
->surface
.dcc_size
,
1367 /* Clear the enabled mipmap levels to black. */
1370 for (unsigned i
= 0; i
< tex
->surface
.num_dcc_levels
; i
++) {
1371 if (!tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
)
1374 size
= tex
->surface
.u
.legacy
.level
[i
].dcc_offset
+
1375 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
;
1378 /* Mipmap levels with DCC. */
1380 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1381 tex
->dcc_offset
, size
,
1382 DCC_CLEAR_COLOR_0000
);
1384 /* Mipmap levels without DCC. */
1385 if (size
!= tex
->surface
.dcc_size
) {
1386 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1387 tex
->dcc_offset
+ size
,
1388 tex
->surface
.dcc_size
- size
,
1394 /* Upload the DCC retile map. */
1395 if (tex
->dcc_retile_map_offset
) {
1396 /* Use a staging buffer for the upload, because
1397 * the buffer backing the texture is unmappable.
1399 bool use_uint16
= tex
->surface
.u
.gfx9
.dcc_retile_use_uint16
;
1400 unsigned num_elements
= tex
->surface
.u
.gfx9
.dcc_retile_num_elements
;
1401 struct si_resource
*buf
=
1402 si_aligned_buffer_create(screen
, 0, PIPE_USAGE_STREAM
,
1403 num_elements
* (use_uint16
? 2 : 4),
1404 sscreen
->info
.tcc_cache_line_size
);
1405 uint32_t *ui
= (uint32_t*)sscreen
->ws
->buffer_map(buf
->buf
, NULL
,
1406 PIPE_TRANSFER_WRITE
);
1407 uint16_t *us
= (uint16_t*)ui
;
1409 /* Upload the retile map into a staging buffer. */
1411 for (unsigned i
= 0; i
< num_elements
; i
++)
1412 us
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1414 for (unsigned i
= 0; i
< num_elements
; i
++)
1415 ui
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1418 /* Copy the staging buffer to the buffer backing the texture. */
1419 struct si_context
*sctx
= (struct si_context
*)sscreen
->aux_context
;
1420 struct pipe_box box
;
1421 u_box_1d(0, buf
->b
.b
.width0
, &box
);
1423 assert(tex
->dcc_retile_map_offset
<= UINT_MAX
);
1424 mtx_lock(&sscreen
->aux_context_lock
);
1425 sctx
->dma_copy(&sctx
->b
, &tex
->buffer
.b
.b
, 0,
1426 tex
->dcc_retile_map_offset
, 0, 0,
1427 &buf
->b
.b
, 0, &box
);
1428 sscreen
->aux_context
->flush(sscreen
->aux_context
, NULL
, 0);
1429 mtx_unlock(&sscreen
->aux_context_lock
);
1431 si_resource_reference(&buf
, NULL
);
1435 /* Initialize the CMASK base register value. */
1436 tex
->cmask_base_address_reg
=
1437 (tex
->buffer
.gpu_address
+ tex
->cmask_offset
) >> 8;
1439 if (sscreen
->debug_flags
& DBG(VM
)) {
1440 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1441 tex
->buffer
.gpu_address
,
1442 tex
->buffer
.gpu_address
+ tex
->buffer
.buf
->size
,
1443 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+1,
1444 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1447 if (sscreen
->debug_flags
& DBG(TEX
)) {
1449 struct u_log_context log
;
1450 u_log_context_init(&log
);
1451 si_print_texture_info(sscreen
, tex
, &log
);
1452 u_log_new_page_print(&log
, stdout
);
1454 u_log_context_destroy(&log
);
1461 if (sscreen
->info
.chip_class
>= GFX9
)
1462 free(surface
->u
.gfx9
.dcc_retile_map
);
1466 static enum radeon_surf_mode
1467 si_choose_tiling(struct si_screen
*sscreen
,
1468 const struct pipe_resource
*templ
, bool tc_compatible_htile
)
1470 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1471 bool force_tiling
= templ
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
;
1472 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1473 !(templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
);
1475 /* MSAA resources must be 2D tiled. */
1476 if (templ
->nr_samples
> 1)
1477 return RADEON_SURF_MODE_2D
;
1479 /* Transfer resources should be linear. */
1480 if (templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
)
1481 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1483 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
1484 * which requires 2D tiling.
1486 if (sscreen
->info
.chip_class
== VI
&& tc_compatible_htile
)
1487 return RADEON_SURF_MODE_2D
;
1489 /* Handle common candidates for the linear mode.
1490 * Compressed textures and DB surfaces must always be tiled.
1492 if (!force_tiling
&&
1493 !is_depth_stencil
&&
1494 !util_format_is_compressed(templ
->format
)) {
1495 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1496 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1498 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. */
1499 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1500 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1502 /* Cursors are linear on SI.
1503 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1504 if (templ
->bind
& PIPE_BIND_CURSOR
)
1505 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1507 if (templ
->bind
& PIPE_BIND_LINEAR
)
1508 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1510 /* Textures with a very small height are recommended to be linear. */
1511 if (templ
->target
== PIPE_TEXTURE_1D
||
1512 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1513 /* Only very thin and long 2D textures should benefit from
1514 * linear_aligned. */
1515 (templ
->width0
> 8 && templ
->height0
<= 2))
1516 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1518 /* Textures likely to be mapped often. */
1519 if (templ
->usage
== PIPE_USAGE_STAGING
||
1520 templ
->usage
== PIPE_USAGE_STREAM
)
1521 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1524 /* Make small textures 1D tiled. */
1525 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1526 (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1527 return RADEON_SURF_MODE_1D
;
1529 /* The allocator will switch to 1D if needed. */
1530 return RADEON_SURF_MODE_2D
;
1533 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1534 const struct pipe_resource
*templ
)
1536 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1537 bool is_zs
= util_format_is_depth_or_stencil(templ
->format
);
1539 if (templ
->nr_samples
>= 2) {
1540 /* This is hackish (overwriting the const pipe_resource template),
1541 * but should be harmless and state trackers can also see
1542 * the overriden number of samples in the created pipe_resource.
1544 if (is_zs
&& sscreen
->eqaa_force_z_samples
) {
1545 ((struct pipe_resource
*)templ
)->nr_samples
=
1546 ((struct pipe_resource
*)templ
)->nr_storage_samples
=
1547 sscreen
->eqaa_force_z_samples
;
1548 } else if (!is_zs
&& sscreen
->eqaa_force_color_samples
) {
1549 ((struct pipe_resource
*)templ
)->nr_samples
=
1550 sscreen
->eqaa_force_coverage_samples
;
1551 ((struct pipe_resource
*)templ
)->nr_storage_samples
=
1552 sscreen
->eqaa_force_color_samples
;
1556 struct radeon_surf surface
= {0};
1557 bool is_flushed_depth
= templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1558 bool tc_compatible_htile
=
1559 sscreen
->info
.chip_class
>= VI
&&
1560 /* There are issues with TC-compatible HTILE on Tonga (and
1561 * Iceland is the same design), and documented bug workarounds
1562 * don't help. For example, this fails:
1563 * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow -auto
1565 sscreen
->info
.family
!= CHIP_TONGA
&&
1566 sscreen
->info
.family
!= CHIP_ICELAND
&&
1567 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1568 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) &&
1569 !is_flushed_depth
&&
1570 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1574 r
= si_init_surface(sscreen
, &surface
, templ
,
1575 si_choose_tiling(sscreen
, templ
, tc_compatible_htile
),
1576 0, 0, false, false, is_flushed_depth
,
1577 tc_compatible_htile
);
1582 return (struct pipe_resource
*)
1583 si_texture_create_object(screen
, templ
, NULL
, &surface
);
1586 static struct pipe_resource
*si_texture_from_winsys_buffer(struct si_screen
*sscreen
,
1587 const struct pipe_resource
*templ
,
1588 struct pb_buffer
*buf
,
1594 enum radeon_surf_mode array_mode
;
1595 struct radeon_surf surface
= {};
1596 struct radeon_bo_metadata metadata
= {};
1597 struct si_texture
*tex
;
1602 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1603 si_get_display_metadata(sscreen
, &surface
, &metadata
,
1604 &array_mode
, &is_scanout
);
1607 * The bo metadata is unset for un-dedicated images. So we fall
1608 * back to linear. See answer to question 5 of the
1609 * VK_KHX_external_memory spec for some details.
1611 * It is possible that this case isn't going to work if the
1612 * surface pitch isn't correctly aligned by default.
1614 * In order to support it correctly we require multi-image
1615 * metadata to be syncrhonized between radv and radeonsi. The
1616 * semantics of associating multiple image metadata to a memory
1617 * object on the vulkan export side are not concretely defined
1620 * All the use cases we are aware of at the moment for memory
1621 * objects use dedicated allocations. So lets keep the initial
1622 * implementation simple.
1624 * A possible alternative is to attempt to reconstruct the
1625 * tiling information when the TexParameter TEXTURE_TILING_EXT
1628 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1632 r
= si_init_surface(sscreen
, &surface
, templ
,
1633 array_mode
, stride
, offset
, true, is_scanout
,
1638 tex
= si_texture_create_object(&sscreen
->b
, templ
, buf
, &surface
);
1642 tex
->buffer
.b
.is_shared
= true;
1643 tex
->buffer
.external_usage
= usage
;
1645 si_get_opaque_metadata(sscreen
, tex
, &metadata
);
1647 /* Displayable DCC requires an explicit flush. */
1649 !(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
1650 si_has_displayable_dcc(tex
)) {
1651 /* TODO: do we need to decompress DCC? */
1652 if (si_texture_discard_dcc(sscreen
, tex
)) {
1653 /* Update BO metadata after disabling DCC. */
1654 si_set_tex_bo_metadata(sscreen
, tex
);
1658 assert(tex
->surface
.tile_swizzle
== 0);
1659 return &tex
->buffer
.b
.b
;
1662 static struct pipe_resource
*si_texture_from_handle(struct pipe_screen
*screen
,
1663 const struct pipe_resource
*templ
,
1664 struct winsys_handle
*whandle
,
1667 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1668 struct pb_buffer
*buf
= NULL
;
1669 unsigned stride
= 0, offset
= 0;
1671 /* Support only 2D textures without mipmaps */
1672 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1673 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1676 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
1677 sscreen
->info
.max_alignment
,
1682 return si_texture_from_winsys_buffer(sscreen
, templ
, buf
, stride
,
1683 offset
, usage
, true);
1686 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1687 struct pipe_resource
*texture
,
1688 struct si_texture
**staging
)
1690 struct si_texture
*tex
= (struct si_texture
*)texture
;
1691 struct pipe_resource resource
;
1692 struct si_texture
**flushed_depth_texture
= staging
?
1693 staging
: &tex
->flushed_depth_texture
;
1694 enum pipe_format pipe_format
= texture
->format
;
1697 if (tex
->flushed_depth_texture
)
1698 return true; /* it's ready */
1700 if (!tex
->can_sample_z
&& tex
->can_sample_s
) {
1701 switch (pipe_format
) {
1702 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1703 /* Save memory by not allocating the S plane. */
1704 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1706 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1707 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1708 /* Save memory bandwidth by not copying the
1709 * stencil part during flush.
1711 * This potentially increases memory bandwidth
1712 * if an application uses both Z and S texturing
1713 * simultaneously (a flushed Z24S8 texture
1714 * would be stored compactly), but how often
1715 * does that really happen?
1717 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1721 } else if (!tex
->can_sample_s
&& tex
->can_sample_z
) {
1722 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1724 /* DB->CB copies to an 8bpp surface don't work. */
1725 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1729 memset(&resource
, 0, sizeof(resource
));
1730 resource
.target
= texture
->target
;
1731 resource
.format
= pipe_format
;
1732 resource
.width0
= texture
->width0
;
1733 resource
.height0
= texture
->height0
;
1734 resource
.depth0
= texture
->depth0
;
1735 resource
.array_size
= texture
->array_size
;
1736 resource
.last_level
= texture
->last_level
;
1737 resource
.nr_samples
= texture
->nr_samples
;
1738 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1739 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1740 resource
.flags
= texture
->flags
| SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1743 resource
.flags
|= SI_RESOURCE_FLAG_TRANSFER
;
1745 *flushed_depth_texture
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1746 if (*flushed_depth_texture
== NULL
) {
1747 PRINT_ERR("failed to create temporary texture to hold flushed depth\n");
1754 * Initialize the pipe_resource descriptor to be of the same size as the box,
1755 * which is supposed to hold a subregion of the texture "orig" at the given
1758 static void si_init_temp_resource_from_box(struct pipe_resource
*res
,
1759 struct pipe_resource
*orig
,
1760 const struct pipe_box
*box
,
1761 unsigned level
, unsigned flags
)
1763 memset(res
, 0, sizeof(*res
));
1764 res
->format
= orig
->format
;
1765 res
->width0
= box
->width
;
1766 res
->height0
= box
->height
;
1768 res
->array_size
= 1;
1769 res
->usage
= flags
& SI_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1772 /* We must set the correct texture target and dimensions for a 3D box. */
1773 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1774 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1775 res
->array_size
= box
->depth
;
1777 res
->target
= PIPE_TEXTURE_2D
;
1781 static bool si_can_invalidate_texture(struct si_screen
*sscreen
,
1782 struct si_texture
*tex
,
1783 unsigned transfer_usage
,
1784 const struct pipe_box
*box
)
1786 return !tex
->buffer
.b
.is_shared
&&
1787 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1788 tex
->buffer
.b
.b
.last_level
== 0 &&
1789 util_texrange_covers_whole_level(&tex
->buffer
.b
.b
, 0,
1790 box
->x
, box
->y
, box
->z
,
1791 box
->width
, box
->height
,
1795 static void si_texture_invalidate_storage(struct si_context
*sctx
,
1796 struct si_texture
*tex
)
1798 struct si_screen
*sscreen
= sctx
->screen
;
1800 /* There is no point in discarding depth and tiled buffers. */
1801 assert(!tex
->is_depth
);
1802 assert(tex
->surface
.is_linear
);
1804 /* Reallocate the buffer in the same pipe_resource. */
1805 si_alloc_resource(sscreen
, &tex
->buffer
);
1807 /* Initialize the CMASK base address (needed even without CMASK). */
1808 tex
->cmask_base_address_reg
=
1809 (tex
->buffer
.gpu_address
+ tex
->cmask_offset
) >> 8;
1811 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1813 sctx
->num_alloc_tex_transfer_bytes
+= tex
->size
;
1816 static void *si_texture_transfer_map(struct pipe_context
*ctx
,
1817 struct pipe_resource
*texture
,
1820 const struct pipe_box
*box
,
1821 struct pipe_transfer
**ptransfer
)
1823 struct si_context
*sctx
= (struct si_context
*)ctx
;
1824 struct si_texture
*tex
= (struct si_texture
*)texture
;
1825 struct si_transfer
*trans
;
1826 struct si_resource
*buf
;
1827 unsigned offset
= 0;
1829 bool use_staging_texture
= false;
1831 assert(!(texture
->flags
& SI_RESOURCE_FLAG_TRANSFER
));
1832 assert(box
->width
&& box
->height
&& box
->depth
);
1834 /* Depth textures use staging unconditionally. */
1835 if (!tex
->is_depth
) {
1836 /* Degrade the tile mode if we get too many transfers on APUs.
1837 * On dGPUs, the staging texture is always faster.
1838 * Only count uploads that are at least 4x4 pixels large.
1840 if (!sctx
->screen
->info
.has_dedicated_vram
&&
1842 box
->width
>= 4 && box
->height
>= 4 &&
1843 p_atomic_inc_return(&tex
->num_level0_transfers
) == 10) {
1844 bool can_invalidate
=
1845 si_can_invalidate_texture(sctx
->screen
, tex
,
1848 si_reallocate_texture_inplace(sctx
, tex
,
1853 /* Tiled textures need to be converted into a linear texture for CPU
1854 * access. The staging texture is always linear and is placed in GART.
1856 * Reading from VRAM or GTT WC is slow, always use the staging
1857 * texture in this case.
1859 * Use the staging texture for uploads if the underlying BO
1862 if (!tex
->surface
.is_linear
)
1863 use_staging_texture
= true;
1864 else if (usage
& PIPE_TRANSFER_READ
)
1865 use_staging_texture
=
1866 tex
->buffer
.domains
& RADEON_DOMAIN_VRAM
||
1867 tex
->buffer
.flags
& RADEON_FLAG_GTT_WC
;
1868 /* Write & linear only: */
1869 else if (si_rings_is_buffer_referenced(sctx
, tex
->buffer
.buf
,
1870 RADEON_USAGE_READWRITE
) ||
1871 !sctx
->ws
->buffer_wait(tex
->buffer
.buf
, 0,
1872 RADEON_USAGE_READWRITE
)) {
1874 if (si_can_invalidate_texture(sctx
->screen
, tex
,
1876 si_texture_invalidate_storage(sctx
, tex
);
1878 use_staging_texture
= true;
1882 trans
= CALLOC_STRUCT(si_transfer
);
1885 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1886 trans
->b
.b
.level
= level
;
1887 trans
->b
.b
.usage
= usage
;
1888 trans
->b
.b
.box
= *box
;
1890 if (tex
->is_depth
) {
1891 struct si_texture
*staging_depth
;
1893 if (tex
->buffer
.b
.b
.nr_samples
> 1) {
1894 /* MSAA depth buffers need to be converted to single sample buffers.
1896 * Mapping MSAA depth buffers can occur if ReadPixels is called
1897 * with a multisample GLX visual.
1899 * First downsample the depth buffer to a temporary texture,
1900 * then decompress the temporary one to staging.
1902 * Only the region being mapped is transfered.
1904 struct pipe_resource resource
;
1906 si_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1908 if (!si_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1909 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1913 if (usage
& PIPE_TRANSFER_READ
) {
1914 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1916 PRINT_ERR("failed to create a temporary depth texture\n");
1920 si_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1921 si_blit_decompress_depth(ctx
, (struct si_texture
*)temp
, staging_depth
,
1922 0, 0, 0, box
->depth
, 0, 0);
1923 pipe_resource_reference(&temp
, NULL
);
1926 /* Just get the strides. */
1927 si_texture_get_offset(sctx
->screen
, staging_depth
, level
, NULL
,
1929 &trans
->b
.b
.layer_stride
);
1931 /* XXX: only readback the rectangle which is being mapped? */
1932 /* XXX: when discard is true, no need to read back from depth texture */
1933 if (!si_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1934 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1938 si_blit_decompress_depth(ctx
, tex
, staging_depth
,
1940 box
->z
, box
->z
+ box
->depth
- 1,
1943 offset
= si_texture_get_offset(sctx
->screen
, staging_depth
,
1946 &trans
->b
.b
.layer_stride
);
1949 trans
->staging
= &staging_depth
->buffer
;
1950 buf
= trans
->staging
;
1951 } else if (use_staging_texture
) {
1952 struct pipe_resource resource
;
1953 struct si_texture
*staging
;
1955 si_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1956 SI_RESOURCE_FLAG_TRANSFER
);
1957 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1958 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1960 /* Create the temporary texture. */
1961 staging
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1963 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1966 trans
->staging
= &staging
->buffer
;
1968 /* Just get the strides. */
1969 si_texture_get_offset(sctx
->screen
, staging
, 0, NULL
,
1971 &trans
->b
.b
.layer_stride
);
1973 if (usage
& PIPE_TRANSFER_READ
)
1974 si_copy_to_staging_texture(ctx
, trans
);
1976 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1978 buf
= trans
->staging
;
1980 /* the resource is mapped directly */
1981 offset
= si_texture_get_offset(sctx
->screen
, tex
, level
, box
,
1983 &trans
->b
.b
.layer_stride
);
1987 /* Always unmap texture CPU mappings on 32-bit architectures, so that
1988 * we don't run out of the CPU address space.
1990 if (sizeof(void*) == 4)
1991 usage
|= RADEON_TRANSFER_TEMPORARY
;
1993 if (!(map
= si_buffer_map_sync_with_rings(sctx
, buf
, usage
)))
1996 *ptransfer
= &trans
->b
.b
;
1997 return map
+ offset
;
2000 si_resource_reference(&trans
->staging
, NULL
);
2001 pipe_resource_reference(&trans
->b
.b
.resource
, NULL
);
2006 static void si_texture_transfer_unmap(struct pipe_context
*ctx
,
2007 struct pipe_transfer
* transfer
)
2009 struct si_context
*sctx
= (struct si_context
*)ctx
;
2010 struct si_transfer
*stransfer
= (struct si_transfer
*)transfer
;
2011 struct pipe_resource
*texture
= transfer
->resource
;
2012 struct si_texture
*tex
= (struct si_texture
*)texture
;
2014 /* Always unmap texture CPU mappings on 32-bit architectures, so that
2015 * we don't run out of the CPU address space.
2017 if (sizeof(void*) == 4) {
2018 struct si_resource
*buf
=
2019 stransfer
->staging
? stransfer
->staging
: &tex
->buffer
;
2021 sctx
->ws
->buffer_unmap(buf
->buf
);
2024 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && stransfer
->staging
) {
2025 if (tex
->is_depth
&& tex
->buffer
.b
.b
.nr_samples
<= 1) {
2026 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
2027 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
2028 &stransfer
->staging
->b
.b
, transfer
->level
,
2031 si_copy_from_staging_texture(ctx
, stransfer
);
2035 if (stransfer
->staging
) {
2036 sctx
->num_alloc_tex_transfer_bytes
+= stransfer
->staging
->buf
->size
;
2037 si_resource_reference(&stransfer
->staging
, NULL
);
2040 /* Heuristic for {upload, draw, upload, draw, ..}:
2042 * Flush the gfx IB if we've allocated too much texture storage.
2044 * The idea is that we don't want to build IBs that use too much
2045 * memory and put pressure on the kernel memory manager and we also
2046 * want to make temporary and invalidated buffers go idle ASAP to
2047 * decrease the total memory usage or make them reusable. The memory
2048 * usage will be slightly higher than given here because of the buffer
2049 * cache in the winsys.
2051 * The result is that the kernel memory manager is never a bottleneck.
2053 if (sctx
->num_alloc_tex_transfer_bytes
> sctx
->screen
->info
.gart_size
/ 4) {
2054 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
2055 sctx
->num_alloc_tex_transfer_bytes
= 0;
2058 pipe_resource_reference(&transfer
->resource
, NULL
);
2062 static const struct u_resource_vtbl si_texture_vtbl
=
2064 NULL
, /* get_handle */
2065 si_texture_destroy
, /* resource_destroy */
2066 si_texture_transfer_map
, /* transfer_map */
2067 u_default_transfer_flush_region
, /* transfer_flush_region */
2068 si_texture_transfer_unmap
, /* transfer_unmap */
2071 /* Return if it's allowed to reinterpret one format as another with DCC enabled.
2073 bool vi_dcc_formats_compatible(enum pipe_format format1
,
2074 enum pipe_format format2
)
2076 const struct util_format_description
*desc1
, *desc2
;
2078 /* No format change - exit early. */
2079 if (format1
== format2
)
2082 format1
= si_simplify_cb_format(format1
);
2083 format2
= si_simplify_cb_format(format2
);
2085 /* Check again after format adjustments. */
2086 if (format1
== format2
)
2089 desc1
= util_format_description(format1
);
2090 desc2
= util_format_description(format2
);
2092 if (desc1
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
2093 desc2
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2096 /* Float and non-float are totally incompatible. */
2097 if ((desc1
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
) !=
2098 (desc2
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
))
2101 /* Channel sizes must match across DCC formats.
2102 * Comparing just the first 2 channels should be enough.
2104 if (desc1
->channel
[0].size
!= desc2
->channel
[0].size
||
2105 (desc1
->nr_channels
>= 2 &&
2106 desc1
->channel
[1].size
!= desc2
->channel
[1].size
))
2109 /* Everything below is not needed if the driver never uses the DCC
2110 * clear code with the value of 1.
2113 /* If the clear values are all 1 or all 0, this constraint can be
2115 if (vi_alpha_is_on_msb(format1
) != vi_alpha_is_on_msb(format2
))
2118 /* Channel types must match if the clear value of 1 is used.
2119 * The type categories are only float, signed, unsigned.
2120 * NORM and INT are always compatible.
2122 if (desc1
->channel
[0].type
!= desc2
->channel
[0].type
||
2123 (desc1
->nr_channels
>= 2 &&
2124 desc1
->channel
[1].type
!= desc2
->channel
[1].type
))
2130 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
2132 enum pipe_format view_format
)
2134 struct si_texture
*stex
= (struct si_texture
*)tex
;
2136 return vi_dcc_enabled(stex
, level
) &&
2137 !vi_dcc_formats_compatible(tex
->format
, view_format
);
2140 /* This can't be merged with the above function, because
2141 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
2142 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
2143 struct pipe_resource
*tex
,
2145 enum pipe_format view_format
)
2147 struct si_texture
*stex
= (struct si_texture
*)tex
;
2149 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
2150 if (!si_texture_disable_dcc(sctx
, stex
))
2151 si_decompress_dcc(sctx
, stex
);
2154 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
2155 struct pipe_resource
*texture
,
2156 const struct pipe_surface
*templ
,
2157 unsigned width0
, unsigned height0
,
2158 unsigned width
, unsigned height
)
2160 struct si_surface
*surface
= CALLOC_STRUCT(si_surface
);
2165 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2166 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2168 pipe_reference_init(&surface
->base
.reference
, 1);
2169 pipe_resource_reference(&surface
->base
.texture
, texture
);
2170 surface
->base
.context
= pipe
;
2171 surface
->base
.format
= templ
->format
;
2172 surface
->base
.width
= width
;
2173 surface
->base
.height
= height
;
2174 surface
->base
.u
= templ
->u
;
2176 surface
->width0
= width0
;
2177 surface
->height0
= height0
;
2179 surface
->dcc_incompatible
=
2180 texture
->target
!= PIPE_BUFFER
&&
2181 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
2183 return &surface
->base
;
2186 static struct pipe_surface
*si_create_surface(struct pipe_context
*pipe
,
2187 struct pipe_resource
*tex
,
2188 const struct pipe_surface
*templ
)
2190 unsigned level
= templ
->u
.tex
.level
;
2191 unsigned width
= u_minify(tex
->width0
, level
);
2192 unsigned height
= u_minify(tex
->height0
, level
);
2193 unsigned width0
= tex
->width0
;
2194 unsigned height0
= tex
->height0
;
2196 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2197 const struct util_format_description
*tex_desc
2198 = util_format_description(tex
->format
);
2199 const struct util_format_description
*templ_desc
2200 = util_format_description(templ
->format
);
2202 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2204 /* Adjust size of surface if and only if the block width or
2205 * height is changed. */
2206 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2207 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2208 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2209 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2211 width
= nblks_x
* templ_desc
->block
.width
;
2212 height
= nblks_y
* templ_desc
->block
.height
;
2214 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2215 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2219 return si_create_surface_custom(pipe
, tex
, templ
,
2224 static void si_surface_destroy(struct pipe_context
*pipe
,
2225 struct pipe_surface
*surface
)
2227 pipe_resource_reference(&surface
->texture
, NULL
);
2231 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2233 const struct util_format_description
*desc
= util_format_description(format
);
2235 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2237 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2238 return V_028C70_SWAP_STD
;
2240 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2243 switch (desc
->nr_channels
) {
2245 if (HAS_SWIZZLE(0,X
))
2246 return V_028C70_SWAP_STD
; /* X___ */
2247 else if (HAS_SWIZZLE(3,X
))
2248 return V_028C70_SWAP_ALT_REV
; /* ___X */
2251 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2252 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2253 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2254 return V_028C70_SWAP_STD
; /* XY__ */
2255 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2256 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2257 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2259 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2260 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2261 return V_028C70_SWAP_ALT
; /* X__Y */
2262 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2263 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2266 if (HAS_SWIZZLE(0,X
))
2267 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2268 else if (HAS_SWIZZLE(0,Z
))
2269 return V_028C70_SWAP_STD_REV
; /* ZYX */
2272 /* check the middle channels, the 1st and 4th channel can be NONE */
2273 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2274 return V_028C70_SWAP_STD
; /* XYZW */
2275 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2276 return V_028C70_SWAP_STD_REV
; /* WZYX */
2277 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2278 return V_028C70_SWAP_ALT
; /* ZYXW */
2279 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2282 return V_028C70_SWAP_ALT_REV
;
2284 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2291 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2293 static void vi_dcc_clean_up_context_slot(struct si_context
*sctx
,
2298 if (sctx
->dcc_stats
[slot
].query_active
)
2299 vi_separate_dcc_stop_query(sctx
,
2300 sctx
->dcc_stats
[slot
].tex
);
2302 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
[slot
].ps_stats
); i
++)
2303 if (sctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2304 sctx
->b
.destroy_query(&sctx
->b
,
2305 sctx
->dcc_stats
[slot
].ps_stats
[i
]);
2306 sctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2309 si_texture_reference(&sctx
->dcc_stats
[slot
].tex
, NULL
);
2313 * Return the per-context slot where DCC statistics queries for the texture live.
2315 static unsigned vi_get_context_dcc_stats_index(struct si_context
*sctx
,
2316 struct si_texture
*tex
)
2318 int i
, empty_slot
= -1;
2320 /* Remove zombie textures (textures kept alive by this array only). */
2321 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2322 if (sctx
->dcc_stats
[i
].tex
&&
2323 sctx
->dcc_stats
[i
].tex
->buffer
.b
.b
.reference
.count
== 1)
2324 vi_dcc_clean_up_context_slot(sctx
, i
);
2326 /* Find the texture. */
2327 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
2328 /* Return if found. */
2329 if (sctx
->dcc_stats
[i
].tex
== tex
) {
2330 sctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2334 /* Record the first seen empty slot. */
2335 if (empty_slot
== -1 && !sctx
->dcc_stats
[i
].tex
)
2339 /* Not found. Remove the oldest member to make space in the array. */
2340 if (empty_slot
== -1) {
2341 int oldest_slot
= 0;
2343 /* Find the oldest slot. */
2344 for (i
= 1; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2345 if (sctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2346 sctx
->dcc_stats
[i
].last_use_timestamp
)
2349 /* Clean up the oldest slot. */
2350 vi_dcc_clean_up_context_slot(sctx
, oldest_slot
);
2351 empty_slot
= oldest_slot
;
2354 /* Add the texture to the new slot. */
2355 si_texture_reference(&sctx
->dcc_stats
[empty_slot
].tex
, tex
);
2356 sctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2360 static struct pipe_query
*
2361 vi_create_resuming_pipestats_query(struct si_context
*sctx
)
2363 struct si_query_hw
*query
= (struct si_query_hw
*)
2364 sctx
->b
.create_query(&sctx
->b
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2366 query
->flags
|= SI_QUERY_HW_FLAG_BEGIN_RESUMES
;
2367 return (struct pipe_query
*)query
;
2371 * Called when binding a color buffer.
2373 void vi_separate_dcc_start_query(struct si_context
*sctx
,
2374 struct si_texture
*tex
)
2376 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2378 assert(!sctx
->dcc_stats
[i
].query_active
);
2380 if (!sctx
->dcc_stats
[i
].ps_stats
[0])
2381 sctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(sctx
);
2383 /* begin or resume the query */
2384 sctx
->b
.begin_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2385 sctx
->dcc_stats
[i
].query_active
= true;
2389 * Called when unbinding a color buffer.
2391 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
2392 struct si_texture
*tex
)
2394 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2396 assert(sctx
->dcc_stats
[i
].query_active
);
2397 assert(sctx
->dcc_stats
[i
].ps_stats
[0]);
2399 /* pause or end the query */
2400 sctx
->b
.end_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2401 sctx
->dcc_stats
[i
].query_active
= false;
2404 static bool vi_should_enable_separate_dcc(struct si_texture
*tex
)
2406 /* The minimum number of fullscreen draws per frame that is required
2408 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2411 /* Called by fast clear. */
2412 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
2413 struct si_texture
*tex
)
2415 /* The intent is to use this with shared displayable back buffers,
2416 * but it's not strictly limited only to them.
2418 if (!tex
->buffer
.b
.is_shared
||
2419 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2420 tex
->buffer
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2421 tex
->buffer
.b
.b
.last_level
> 0 ||
2422 !tex
->surface
.dcc_size
||
2423 sctx
->screen
->debug_flags
& DBG(NO_DCC
) ||
2424 sctx
->screen
->debug_flags
& DBG(NO_DCC_FB
))
2427 assert(sctx
->chip_class
>= VI
);
2429 if (tex
->dcc_offset
)
2430 return; /* already enabled */
2432 /* Enable the DCC stat gathering. */
2433 if (!tex
->dcc_gather_statistics
) {
2434 tex
->dcc_gather_statistics
= true;
2435 vi_separate_dcc_start_query(sctx
, tex
);
2438 if (!vi_should_enable_separate_dcc(tex
))
2439 return; /* stats show that DCC decompression is too expensive */
2441 assert(tex
->surface
.num_dcc_levels
);
2442 assert(!tex
->dcc_separate_buffer
);
2444 si_texture_discard_cmask(sctx
->screen
, tex
);
2446 /* Get a DCC buffer. */
2447 if (tex
->last_dcc_separate_buffer
) {
2448 assert(tex
->dcc_gather_statistics
);
2449 assert(!tex
->dcc_separate_buffer
);
2450 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2451 tex
->last_dcc_separate_buffer
= NULL
;
2453 tex
->dcc_separate_buffer
=
2454 si_aligned_buffer_create(sctx
->b
.screen
,
2455 SI_RESOURCE_FLAG_UNMAPPABLE
,
2457 tex
->surface
.dcc_size
,
2458 tex
->surface
.dcc_alignment
);
2459 if (!tex
->dcc_separate_buffer
)
2463 /* dcc_offset is the absolute GPUVM address. */
2464 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2466 /* no need to flag anything since this is called by fast clear that
2467 * flags framebuffer state
2472 * Called by pipe_context::flush_resource, the place where DCC decompression
2475 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2476 struct si_texture
*tex
)
2478 struct si_context
*sctx
= (struct si_context
*)ctx
;
2479 struct pipe_query
*tmp
;
2480 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2481 bool query_active
= sctx
->dcc_stats
[i
].query_active
;
2482 bool disable
= false;
2484 if (sctx
->dcc_stats
[i
].ps_stats
[2]) {
2485 union pipe_query_result result
;
2487 /* Read the results. */
2488 struct pipe_query
*query
= sctx
->dcc_stats
[i
].ps_stats
[2];
2489 ctx
->get_query_result(ctx
, query
,
2491 si_query_buffer_reset(sctx
, &((struct si_query_hw
*)query
)->buffer
);
2493 /* Compute the approximate number of fullscreen draws. */
2494 tex
->ps_draw_ratio
=
2495 result
.pipeline_statistics
.ps_invocations
/
2496 (tex
->buffer
.b
.b
.width0
* tex
->buffer
.b
.b
.height0
);
2497 sctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2499 disable
= tex
->dcc_separate_buffer
&&
2500 !vi_should_enable_separate_dcc(tex
);
2503 tex
->num_slow_clears
= 0;
2505 /* stop the statistics query for ps_stats[0] */
2507 vi_separate_dcc_stop_query(sctx
, tex
);
2509 /* Move the queries in the queue by one. */
2510 tmp
= sctx
->dcc_stats
[i
].ps_stats
[2];
2511 sctx
->dcc_stats
[i
].ps_stats
[2] = sctx
->dcc_stats
[i
].ps_stats
[1];
2512 sctx
->dcc_stats
[i
].ps_stats
[1] = sctx
->dcc_stats
[i
].ps_stats
[0];
2513 sctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2515 /* create and start a new query as ps_stats[0] */
2517 vi_separate_dcc_start_query(sctx
, tex
);
2520 assert(!tex
->last_dcc_separate_buffer
);
2521 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2522 tex
->dcc_separate_buffer
= NULL
;
2523 tex
->dcc_offset
= 0;
2524 /* no need to flag anything since this is called after
2525 * decompression that re-sets framebuffer state
2530 static struct pipe_memory_object
*
2531 si_memobj_from_handle(struct pipe_screen
*screen
,
2532 struct winsys_handle
*whandle
,
2535 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2536 struct si_memory_object
*memobj
= CALLOC_STRUCT(si_memory_object
);
2537 struct pb_buffer
*buf
= NULL
;
2538 uint32_t stride
, offset
;
2543 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
2544 sscreen
->info
.max_alignment
,
2551 memobj
->b
.dedicated
= dedicated
;
2553 memobj
->stride
= stride
;
2555 return (struct pipe_memory_object
*)memobj
;
2560 si_memobj_destroy(struct pipe_screen
*screen
,
2561 struct pipe_memory_object
*_memobj
)
2563 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2565 pb_reference(&memobj
->buf
, NULL
);
2569 static struct pipe_resource
*
2570 si_texture_from_memobj(struct pipe_screen
*screen
,
2571 const struct pipe_resource
*templ
,
2572 struct pipe_memory_object
*_memobj
,
2575 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2576 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2577 struct pipe_resource
*tex
=
2578 si_texture_from_winsys_buffer(sscreen
, templ
, memobj
->buf
,
2579 memobj
->stride
, offset
,
2580 PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
|
2581 PIPE_HANDLE_USAGE_SHADER_WRITE
,
2582 memobj
->b
.dedicated
);
2586 /* si_texture_from_winsys_buffer doesn't increment refcount of
2587 * memobj->buf, so increment it here.
2589 struct pb_buffer
*buf
= NULL
;
2590 pb_reference(&buf
, memobj
->buf
);
2594 static bool si_check_resource_capability(struct pipe_screen
*screen
,
2595 struct pipe_resource
*resource
,
2598 struct si_texture
*tex
= (struct si_texture
*)resource
;
2600 /* Buffers only support the linear flag. */
2601 if (resource
->target
== PIPE_BUFFER
)
2602 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2604 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2607 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2610 /* TODO: PIPE_BIND_CURSOR - do we care? */
2614 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2616 sscreen
->b
.resource_from_handle
= si_texture_from_handle
;
2617 sscreen
->b
.resource_get_handle
= si_texture_get_handle
;
2618 sscreen
->b
.resource_from_memobj
= si_texture_from_memobj
;
2619 sscreen
->b
.memobj_create_from_handle
= si_memobj_from_handle
;
2620 sscreen
->b
.memobj_destroy
= si_memobj_destroy
;
2621 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2624 void si_init_context_texture_functions(struct si_context
*sctx
)
2626 sctx
->b
.create_surface
= si_create_surface
;
2627 sctx
->b
.surface_destroy
= si_surface_destroy
;